- CONFIG_SYSTEM_USBMONITOR_TRACEINIT=y
- CONFIG_SYSTEM_USBMONITOR_TRACECLASS=y
- CONFIG_SYSTEM_USBMONITOR_TRACETRANSFERS=y
- CONFIG_SYSTEM_USBMONITOR_TRACECONTROLLER=y
- CONFIG_SYSTEM_USBMONITOR_TRACEINTERRUPTS=y
+ CONFIG_USBMONITOR_TRACEINIT=y
+ CONFIG_USBMONITOR_TRACECLASS=y
+ CONFIG_USBMONITOR_TRACETRANSFERS=y
+ CONFIG_USBMONITOR_TRACECONTROLLER=y
+ CONFIG_USBMONITOR_TRACEINTERRUPTS=y
|
Selects which USB event(s) that you want to be traced.
diff --git a/FlatLibs.mk b/FlatLibs.mk
index 13dcc6c3400f0b24f52fe5bfd140265af0a8c6f3..69fe6a9fa067419996c597ec493e4273d519c0a8 100644
--- a/FlatLibs.mk
+++ b/FlatLibs.mk
@@ -45,6 +45,12 @@
NUTTXLIBS = lib$(DELIM)libsched$(LIBEXT)
USERLIBS =
+# Driver support. Generally depends on file descriptor support but there
+# are some components in the drivers directory that are needed even if file
+# descriptors are not supported.
+
+NUTTXLIBS += lib$(DELIM)libdrivers$(LIBEXT)
+
# Add libraries for board support
NUTTXLIBS += lib$(DELIM)libconfigs$(LIBEXT)
@@ -89,11 +95,8 @@ ifeq ($(CONFIG_NFILE_DESCRIPTORS),0)
ifneq ($(CONFIG_NSOCKET_DESCRIPTORS),0)
NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT)
endif
-ifeq ($(CONFIG_NET),y)
-NUTTXLIBS += lib$(DELIM)libdrivers$(LIBEXT)
-endif
else
-NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT) lib$(DELIM)libdrivers$(LIBEXT) lib$(DELIM)libbinfmt$(LIBEXT)
+NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT) lib$(DELIM)libbinfmt$(LIBEXT)
endif
# Add libraries for the NX graphics sub-system
diff --git a/Kconfig b/Kconfig
index 17d6e351f9eb96bb6f72fe51044c4780d9a375a1..4d7949d4e31da4417ff62727a53eb865291c86c2 100644
--- a/Kconfig
+++ b/Kconfig
@@ -45,6 +45,14 @@ config HOST_OTHER
endchoice
+config TOOLCHAIN_WINDOWS
+ bool
+ default n
+ depends on HOST_WINDOWS
+ ---help---
+ Selected internally if the selected Windows environment is compatible
+ with the use of Windows native toolchains.
+
choice
prompt "Windows Build Environment"
default WINDOWS_CYGWIN
@@ -52,24 +60,34 @@ choice
config WINDOWS_NATIVE
bool "Windows Native"
+ select TOOLCHAIN_WINDOWS
---help---
Build natively in a CMD.exe environment with Windows style paths
(like C:\cgywin\home)
config WINDOWS_CYGWIN
bool "Cygwin"
+ select TOOLCHAIN_WINDOWS
---help---
Build natively in a Cygwin environment with POSIX style paths (like
- /cygdrive/c/cgywin/home)
+ /cygdrive/c/Program Files)
+
+config WINDOWS_UBUNTU
+ bool "Ubuntu under Windows 10"
+ ---help---
+ Build natively in an Unbuntu shell under Windoes 10 environment with
+ POSIX style paths (like /mnt/c/Program Files)
config WINDOWS_MSYS
bool "MSYS"
+ select TOOLCHAIN_WINDOWS
---help---
Build natively in a Cygwin environment with POSIX style paths (like
/cygdrive/c/cgywin/home)
config WINDOWS_OTHER
bool "Windows POSIX-like environment"
+ select TOOLCHAIN_WINDOWS
---help---
Build natively in another POSIX-like environment. Additional
support may be necessary
@@ -339,10 +357,10 @@ config ARCH_MATH_H
default n
---help---
There is also a re-directing version of math.h in the source tree.
- However, it resides out-of-the-way at include/nuttx/math.h because it
+ However, it resides out-of-the-way at include/nuttx/lib/math.h because it
conflicts too often with the system math.h. If ARCH_MATH_H=y is
defined, however, the top-level makefile will copy the redirecting
- math.h header file from include/nuttx/math.h to include/math.h. math.h
+ math.h header file from include/nuttx/lib/math.h to include/math.h. math.h
will then include the architecture-specific version of math.h that you
must provide at nuttx/arch/>architecture/include/stdarg.h
If ARCH_STDARG_H=y is defined, the top-level makefile will copy the
- re-directing stdarg.h header file from include/nuttx/stdarg.h to
+ re-directing stdarg.h header file from include/nuttx/lib/stdarg.h to
include/stdarg.h. So for the architectures that cannot use their
toolchain's stdarg.h file, they can use this alternative by defining
ARCH_STDARG_H=y and providing. If ARCH_STDARG_H, is not defined, then
@@ -395,9 +413,14 @@ endmenu # Customize Header Files
menu "Debug Options"
-config DEBUG
+config DEBUG_ALERT
+ bool
+ default n
+
+config DEBUG_FEATURES
bool "Enable Debug Features"
default n
+ select DEBUG_ALERT
---help---
Enables built-in debug features. Selecting this option will (1) Enable
debug assertions in the code, (2) enable extended parameter testing in
@@ -405,71 +428,270 @@ config DEBUG
Note that enabling this option by itself does not produce debug output.
Debug output must also be selected on a subsystem-by-subsystem basis.
-config ARCH_HAVE_HEAPCHECK
- bool
+if DEBUG_FEATURES
+
+comment "Debug SYSLOG Output Controls"
+
+config DEBUG_ERROR
+ bool "Enable Error Output"
+ default n
+ ---help---
+ Enables output from [a-z]err() statements. Errors are significant system
+ exceptions that require immediate attention.
+
+config DEBUG_WARN
+ bool "Enable Warnings Output"
default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enables output from [a-z]warn() statements. Warnings are considered to
+ be various unexpected conditions, potential errors or errors that will
+ not have serious consequences.
-if DEBUG
+config DEBUG_INFO
+ bool "Enable Informational Debug Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enables verbose "informational" debug output. If you enable
+ CONFIG_DEBUG_INFO, then very chatty (and often annoying) output
+ will be generated.
-config DEBUG_VERBOSE
- bool "Enable Debug Verbose Output"
+config DEBUG_ASSERTIONS
+ bool "Enable Debug Assertions"
default n
---help---
- Enables verbose debug output (assuming debug features are enabled).
- As a general rule, when DEBUG is enabled only errors will be
- reported in the debug SYSLOG output. But if you also enable
- DEBUG_VERBOSE, then very chatty (and often annoying) output will be
- generated. This means there are two levels of debug output:
- errors-only and everything.
+ Enables the DEBUGASSERT() macro. When CONFIG_DEBUG_ASSERTIONS is
+ defined, DEBUGASSERT() will cause the system to halt if the
+ assertion fails. If CONFIG_DEBUG_ASSERTIONS is not defined
+ DEBUGASSERT() compiled out of the system. In general, you would
+ set CONFIG_DEBUG_ASSERTIONS=y during debug, but disable the
+ assertions on a final, buckled up system.
comment "Subsystem Debug Options"
config DEBUG_AUDIO
- bool "Audio Device Debug Output"
+ bool "Audio Device Debug Features"
default n
depends on AUDIO
---help---
- Enable low level debug SYSLOG output from the audio subsystem and
+ Enable audio device debug features.
+ Enable low level debug featurs for the audio subsystem and for audio
device drivers. (disabled by default). Support for this debug option
is architecture-specific and may not be available for some MCUs.
+if DEBUG_AUDIO
+
+config DEBUG_AUDIO_ERROR
+ bool "Audio Device Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable audio device error output to SYSLOG.
+
+config DEBUG_AUDIO_WARN
+ bool "Audio Device Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable audio device warning output to SYSLOG.
+
+config DEBUG_AUDIO_INFO
+ bool "Audio Device Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable audio device informational output to SYSLOG.
+
+endif # DEBUG_AUDIO
+
config DEBUG_BINFMT
- bool "Binary Loader Debug Output"
+ bool "Binary Loader Debug Features"
default n
depends on !BINFMT_DISABLE
---help---
- Enable binary loader debug SYSLOG output (disabled by default)
+ Enable binary loader debug features.
+
+if DEBUG_BINFMT
+
+config DEBUG_BINFMT_ERROR
+ bool "Binary Loader Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable binary loader error output to SYSLOG.
+
+config DEBUG_BINFMT_WARN
+ bool "Binary Loader Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable binary loader warning output to SYSLOG.
+
+config DEBUG_BINFMT_INFO
+ bool "Binary Loader Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable binary loader informational output to SYSLOG.
+
+endif # DEBUG_BINFMT
config DEBUG_CRYPTO
- bool "Crypto Debug Output"
+ bool "Crypto Debug Features"
default n
depends on CRYPTO
---help---
- Enable Crypto debug SYSLOG output (disabled by default)
+ Enable cryptographic debug features.
+
+if DEBUG_CRYPTO
+
+config DEBUG_CRYPTO_ERROR
+ bool "Crypto Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable cryptographic error output to SYSLOG.
+
+config DEBUG_CRYPTO_WARN
+ bool "Crypto Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable cryptographic warning output to SYSLOG.
+
+config DEBUG_CRYPTO_INFO
+ bool "Crypto Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable cryptographic informational output to SYSLOG.
+
+endif # DEBUG_CRYPTO
config DEBUG_FS
- bool "File System Debug Output"
+ bool "File System Debug Features"
+ default n
+ ---help---
+ Enable file system debug features.
+
+if DEBUG_FS
+
+config DEBUG_FS_ERROR
+ bool "File System Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable file system error output to SYSLOG.
+
+config DEBUG_FS_WARN
+ bool "File System Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable file system warning output to SYSLOG.
+
+config DEBUG_FS_INFO
+ bool "File System Informational Output"
default n
+ depends on DEBUG_INFO
---help---
- Enable file system debug SYSLOG output (disabled by default)
+ Enable file system informational output to SYSLOG.
+
+endif # DEBUG_FS
config DEBUG_GRAPHICS
- bool "Graphics Debug Output"
+ bool "Graphics Debug Features"
default n
---help---
- Enable NX graphics debug SYSLOG output (disabled by default)
+ Enable NX graphics subsystem debug features.
+
+if DEBUG_GRAPHICS
+
+config DEBUG_GRAPHICS_ERROR
+ bool "Graphics Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable NX graphics subsystem error output to SYSLOG.
+
+config DEBUG_GRAPHICS_WARN
+ bool "Graphics Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable NX graphics subsystem warning output to SYSLOG.
+
+config DEBUG_GRAPHICS_INFO
+ bool "Graphics Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable NX graphics subsystem informational output to SYSLOG.
+
+endif # DEBUG_GRAPHICS
config DEBUG_LIB
- bool "C Library Debug Output"
+ bool "C Library Debug Features"
+ default n
+ ---help---
+ Enable C library debug features.
+
+if DEBUG_LIB
+
+config DEBUG_LIB_ERROR
+ bool "C Library Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable C library error output to SYSLOG.
+
+config DEBUG_LIB_WARN
+ bool "C Library Warnings Output"
default n
+ depends on DEBUG_WARN
---help---
- Enable C library debug SYSLOG output (disabled by default)
+ Enable C library warning output to SYSLOG.
+
+config DEBUG_LIB_INFO
+ bool "C Library Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable C library informational output to SYSLOG.
+
+endif # DEBUG_LIB
config DEBUG_MM
- bool "Memory Manager Debug Output"
+ bool "Memory Manager Debug Features"
+ default n
+ ---help---
+ Enable memory management debug features.
+
+if DEBUG_MM
+
+config DEBUG_MM_ERROR
+ bool "Memory Manager Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable memory management error output to SYSLOG.
+
+config DEBUG_MM_WARN
+ bool "Memory Manager Warnings Output"
default n
+ depends on DEBUG_WARN
---help---
- Enable memory management debug SYSLOG output (disabled by default)
+ Enable memory management warning output to SYSLOG.
+
+config DEBUG_MM_INFO
+ bool "Memory Manager Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable memory management informational output to SYSLOG.
+
+endif # DEBUG_MM
config DEBUG_SHM
bool "Shared Memory Debug Output"
@@ -479,25 +701,101 @@ config DEBUG_SHM
Enable shared memory management debug SYSLOG output (disabled by default)
config DEBUG_NET
- bool "Network Debug Output"
+ bool "Network Debug Features"
default n
depends on ARCH_HAVE_NET
---help---
- Enable network debug SYSLOG output (disabled by default)
+ Enable network debug features.
+
+if DEBUG_NET
+
+config DEBUG_NET_ERROR
+ bool "Network Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable network error output to SYSLOG.
+
+config DEBUG_NET_WARN
+ bool "Network Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable network warning output to SYSLOG.
+
+config DEBUG_NET_INFO
+ bool "Network Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable network informational output to SYSLOG.
+
+endif # DEBUG_NET
config DEBUG_SCHED
- bool "Scheduler Debug Output"
+ bool "Scheduler Debug Features"
+ default n
+ ---help---
+ Enable OS scheduler debug features.
+
+if DEBUG_SCHED
+
+config DEBUG_SCHED_ERROR
+ bool "Scheduler Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable OS scheduler error output to SYSLOG.
+
+config DEBUG_SCHED_WARN
+ bool "Scheduler Warnings Output"
default n
+ depends on DEBUG_WARN
---help---
- Enable OS debug SYSLOG output (disabled by default)
+ Enable OS scheduler warning output to SYSLOG.
+
+config DEBUG_SCHED_INFO
+ bool "Scheduler Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable OS scheduler informational output to SYSLOG.
+
+endif # DEBUG_SCHED
config DEBUG_SYSCALL
- bool "SYSCALL Debug Output"
+ bool "SYSCALL Debug Features"
default n
depends on LIB_SYSCALL
---help---
- Enable very low level output related to system calls. This gives
- you basically a poor man's version of strace.
+ Enable very low level features related to system calls. If SYSCAL
+ output is enabled, this gives you basically a poor man's version of
+ strace.
+
+if DEBUG_SYSCALL
+
+config DEBUG_SYSCALL_ERROR
+ bool "SYSCALL Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable OS SYSCALL error output to SYSLOG.
+
+config DEBUG_SYSCALL_WARN
+ bool "SYSCALL Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable OS SYSCALL warning output to SYSLOG.
+
+config DEBUG_SYSCALL_INFO
+ bool "SYSCALL Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable OS SYSCALL informational output to SYSLOG.
+
+endif # DEBUG_SYSCALL
config DEBUG_WIRELESS
bool "Wireless Device Debug Output"
@@ -511,25 +809,46 @@ config DEBUG_WIRELESS
comment "OS Function Debug Options"
config DEBUG_DMA
- bool "DMA Debug Output"
+ bool "DMA Debug Features"
default n
depends on ARCH_DMA
---help---
- Enable DMA-releated debug SYSLOG output (disabled by default).
+ Enable DMA debug features.
+
Support for this debug option is architecture-specific and may not
be available for some MCUs.
-config DEBUG_HEAP
- bool "Heap usage debug hooks"
+if DEBUG_DMA
+
+config DEBUG_DMA_ERROR
+ bool "DMA Error Output"
default n
- depends on ARCH_HAVE_HEAPCHECK
+ depends on DEBUG_ERROR
---help---
- Enable hooks to check heap usage. Only supported by a few architectures.
+ Enable DMA error output to SYSLOG.
+
+config DEBUG_DMA_WARN
+ bool "DMA Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable DMA warning output to SYSLOG.
+
+config DEBUG_DMA_INFO
+ bool "DMA Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable DMA informational output to SYSLOG.
+
+endif # DEBUG_DMA
config DEBUG_IRQ
- bool "Interrupt Controller Debug Output"
+ bool "Interrupt Controller Debug Features"
default n
---help---
+ Enable interrupt controller debug features.
+
Some (but not all) architectures support debug output to verify
interrupt controller logic. If supported, then option will enable
that output. This may interfere with normal operations! You
@@ -537,158 +856,633 @@ config DEBUG_IRQ
that here is a problem with that logic. On some platforms, this
option may even cause crashes! Use with care!
+if DEBUG_IRQ
+
+config DEBUG_IRQ_ERROR
+ bool "Interrupt Controller Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable interrupt controller error output to SYSLOG.
+
+config DEBUG_IRQ_WARN
+ bool "Interrupt Controller Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable interrupt controller warning output to SYSLOG.
+
+config DEBUG_IRQ_INFO
+ bool "Interrupt Controller Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable interrupt controller informational output to SYSLOG.
+
+endif # DEBUG_IRQ
+
config DEBUG_PAGING
- bool "Demand Paging Debug Output"
+ bool "Paging Debug Features"
default n
depends on PAGING
---help---
- Enable demand paging debug SYSLOG output (disabled by default)
+ Enable OS demand paging debug features.
+
+if DEBUG_PAGING
+
+config DEBUG_PAGING_ERROR
+ bool "Paging Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable OS demand paging error output to SYSLOG.
+
+config DEBUG_PAGING_WARN
+ bool "Paging Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable OS demand paging warning output to SYSLOG.
+
+config DEBUG_PAGING_INFO
+ bool "Paging Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable OS demand paging informational output to SYSLOG.
+
+endif # DEBUG_PAGING
comment "Driver Debug Options"
config DEBUG_LCD
- bool "Low-level LCD Debug Output"
+ bool "Low-level LCD Debug Features"
default n
depends on LCD
---help---
- Enable low level debug SYSLOG output from the LCD driver (disabled
- by default). Support for this debug option is board-specific and
- may not be available for some boards.
+ Enable LCD driver debug features.
+
+ Support for this debug option is board-specific and may not
+ be available for some boards.
+if DEBUG_LCD
+
+config DEBUG_LCD_ERROR
+ bool "LCD Driver Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable LCD driver error output to SYSLOG.
+
+config DEBUG_LCD_WARN
+ bool "LCD Driver Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable LCD driver warning output to SYSLOG.
+
+config DEBUG_LCD_INFO
+ bool "LCD Driver Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable LCD driver informational output to SYSLOG.
+
+endif # DEBUG_LCD
config DEBUG_LEDS
- bool "Low-level LED Debug Output"
+ bool "Low-level LED Debug Features"
default n
depends on ARCH_HAVE_LEDS
---help---
- Enable low level debug from board-specific LED logic. Support for
- this debug option is board-specific and may not be available for
- some boards.
+ Enable LED driver debug features.
+
+ Support for this debug option is board-specific and may not
+ be available for some boards.
+
+if DEBUG_LEDS
+
+config DEBUG_LEDS_ERROR
+ bool "LED Driver Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable LED driver error output to SYSLOG.
+
+config DEBUG_LEDS_WARN
+ bool "LED Driver Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable LED driver warning output to SYSLOG.
+
+config DEBUG_LEDS_INFO
+ bool "LED Driver Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable LED driver informational output to SYSLOG.
+
+endif # DEBUG_LEDS
config DEBUG_INPUT
- bool "Input Device Debug Output"
+ bool "Input Device Debug Features"
default n
depends on INPUT
---help---
- Enable low level debug SYSLOG output from the input device drivers
+ Enable input d.
+ Enable low level evice debug features for the input device drivers
such as mice and touchscreens (disabled by default). Support for
this debug option is board-specific and may not be available for
some boards.
+if DEBUG_INPUT
+
+config DEBUG_INPUT_ERROR
+ bool "Input Device Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable input device error output to SYSLOG.
+
+config DEBUG_INPUT_WARN
+ bool "Input Device Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable input device warning output to SYSLOG.
+
+config DEBUG_INPUT_INFO
+ bool "Input Device Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable input device informational output to SYSLOG.
+
+endif # DEBUG_INPUT
+
config DEBUG_ANALOG
- bool "Analog Device Debug Output"
+ bool "Analog Device Debug Features"
+ default n
+ depends on ANALOG
+ ---help---
+ Enable analog device debug features.
+ Enable low level debug features the analog device drivers such as
+ A/D and D/A converters (disabled by default). Support for this
+ debug option is architecture-specific and may not be available for
+ some MCUs.
+
+if DEBUG_ANALOG
+
+config DEBUG_ANALOG_ERROR
+ bool "Analog Device Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable analog device error output to SYSLOG.
+
+config DEBUG_ANALOG_WARN
+ bool "Analog Device Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable analog device warning output to SYSLOG.
+
+config DEBUG_ANALOG_INFO
+ bool "Analog Device Informational Output"
default n
+ depends on DEBUG_INFO
---help---
- Enable low level debug SYSLOG output from the analog device drivers
- such as A/D and D/A converters (disabled by default). Support for
- this debug option is architecture-specific and may not be available
- for some MCUs.
+ Enable CAN driver informational output to SYSLOG.
+
+endif # DEBUG_ANALOG
config DEBUG_CAN
- bool "CAN Debug Output"
+ bool "CAN Debug Features"
default n
depends on CAN
---help---
- Enable CAN driver debug SYSLOG output (disabled by default).
+ Enable CAN driver debug features.
+
Support for this debug option is architecture-specific and may not
be available for some MCUs.
+if DEBUG_CAN
+
+config DEBUG_CAN_ERROR
+ bool "CAN Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable CAN driver error output to SYSLOG.
+
+config DEBUG_CAN_WARN
+ bool "CAN Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable CAN driver warning output to SYSLOG.
+
+config DEBUG_CAN_INFO
+ bool "CAN Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable CAN driver informational output to SYSLOG.
+
+endif # DEBUG_CAN
+
config DEBUG_GPIO
- bool "GPIO Debug Output"
+ bool "GPIO Debug Features"
default n
---help---
- Enable GPIO-releated debug SYSLOG output (disabled by default).
+ Enable GPIO debug features.
+
Support for this debug option is architecture-specific and may not
be available for some MCUs.
+if DEBUG_GPIO
+
+config DEBUG_GPIO_ERROR
+ bool "GPIO Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable GPIO error output to SYSLOG.
+
+config DEBUG_GPIO_WARN
+ bool "GPIO Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable GPIO warning output to SYSLOG.
+
+config DEBUG_GPIO_INFO
+ bool "GPIO Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable GPIO informational output to SYSLOG.
+
+endif # DEBUG_GPIO
+
config DEBUG_I2C
- bool "I2C Debug Output"
+ bool "I2C Debug Features"
default n
depends on I2C
---help---
- Enable I2C driver debug SYSLOG output (disabled by default).
+ Enable I2C debug features.
+
Support for this debug option is architecture-specific and may not
be available for some MCUs.
+if DEBUG_I2C
+
+config DEBUG_I2C_ERROR
+ bool "I2C Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable I2C driver error output to SYSLOG.
+
+config DEBUG_I2C_WARN
+ bool "I2C Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable I2C driver warning output to SYSLOG.
+
+config DEBUG_I2C_INFO
+ bool "I2C Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable I2C driver informational output to SYSLOG.
+
+endif # DEBUG_I2C
+
config DEBUG_I2S
- bool "I2S Debug Output"
+ bool "I2S Debug Features"
default n
depends on I2S
---help---
- Enable I2S driver debug SYSLOG output (disabled by default).
+ Enable I2S debug features.
+
Support for this debug option is architecture-specific and may not
be available for some MCUs.
+if DEBUG_I2S
+
+config DEBUG_I2S_ERROR
+ bool "I2S Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable I2S driver error output to SYSLOG.
+
+ Support for this debug option is architecture-specific and may not
+ be available for some MCUs.
+
+config DEBUG_I2S_WARN
+ bool "I2S Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable I2S driver warning output to SYSLOG.
+
+config DEBUG_I2S_INFO
+ bool "I2S Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable I2S driver informational output to SYSLOG.
+
+endif # DEBUG_I2S
+
config DEBUG_PWM
- bool "PWM Debug Output"
+ bool "PWM Debug Features"
default n
depends on PWM
---help---
- Enable PWM driver debug SYSLOG output (disabled by default).
+ Enable PWM debug features.
+
Support for this debug option is architecture-specific and may not
be available for some MCUs.
+if DEBUG_PWM
+
+config DEBUG_PWM_ERROR
+ bool "PWM Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable PWM driver error output to SYSLOG.
+
+ Support for this debug option is architecture-specific and may not
+ be available for some MCUs.
+
+config DEBUG_PWM_WARN
+ bool "PWM Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable PWM driver warning output to SYSLOG.
+
+config DEBUG_PWM_INFO
+ bool "PWM Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable PWM driver informational output to SYSLOG.
+
+endif # DEBUG_PWM
+
config DEBUG_RTC
- bool "RTC Debug Output"
+ bool "RTC Debug Features"
default n
depends on RTC
---help---
- Enable RTC driver debug SYSLOG output (disabled by default).
+ Enable RTC debug features.
+
+ Support for this debug option is architecture-specific and may not
+ be available for some MCUs.
+
+if DEBUG_RTC
+
+config DEBUG_RTC_ERROR
+ bool "RTC Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable RTC driver error output to SYSLOG.
+
+ Support for this debug option is architecture-specific and may not
+ be available for some MCUs.
+
+config DEBUG_RTC_WARN
+ bool "RTC Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable RTC driver warning output to SYSLOG.
+
+config DEBUG_RTC_INFO
+ bool "RTC Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable RTC driver informational output to SYSLOG.
+
+endif # DEBUG_RTC
+
+config DEBUG_MEMCARD
+ bool "Memory Card Driver Debug Features"
+ default n
+ depends on MMCSD
+ ---help---
+ Enable MMC/SD memory card Driver debug features.
+
Support for this debug option is architecture-specific and may not
be available for some MCUs.
-config DEBUG_SDIO
- bool "SDIO Debug Output"
+if DEBUG_MEMCARD
+
+config DEBUG_MEMCARD_ERROR
+ bool "Memory Card Driver Error Output"
default n
- depends on MMCSD_SDIO
+ depends on DEBUG_ERROR
---help---
- Enable SDIO driver debug SYSLOG output (disabled by default).
+ Enable MMC/SD memory card driver error output to SYSLOG.
+
Support for this debug option is architecture-specific and may not
be available for some MCUs.
+config DEBUG_MEMCARD_WARN
+ bool "Memory Card Driver Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable MMC/SD memory card driver warning output to SYSLOG.
+
+config DEBUG_MEMCARD_INFO
+ bool "Memory Card Driver Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable MMC/SD memory card driver informational output to SYSLOG.
+
+endif # DEBUG_MEMCARD
+
config DEBUG_SENSORS
- bool "Sensor Debug Output"
+ bool "Sensor Debug Features"
default n
depends on SENSORS
---help---
- Enable sensor driver debug SYSLOG output (disabled by default).
+ Enable sensor driver debug features.
+
Support for this debug option is architecture-specific and may not
be available for some MCUs.
+if DEBUG_SENSORS
+
+config DEBUG_SENSORS_ERROR
+ bool "Sensor Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable sensor driver error output to SYSLOG.
+
+config DEBUG_SENSORS_WARN
+ bool "Sensor Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable sensor driver warning output to SYSLOG.
+
+config DEBUG_SENSORS_INFO
+ bool "Sensor Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable sensor driver informational output to SYSLOG.
+
+endif # DEBUG_SENSORS
+
config DEBUG_SPI
- bool "SPI Debug Output"
+ bool "SPI Debug Features"
default n
depends on SPI
---help---
- Enable I2C driver debug SYSLOG output (disabled by default).
+ Enable SPI debug features.
+
Support for this debug option is architecture-specific and may not
be available for some MCUs.
+if DEBUG_SPI
+
+config DEBUG_SPI_ERROR
+ bool "SPI Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable SPI error output to SYSLOG.
+
+config DEBUG_SPI_WARN
+ bool "SPI Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable SPI warning output to SYSLOG.
+
+config DEBUG_SPI_INFO
+ bool "SPI Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable SPI informational output to SYSLOG.
+
+endif # DEBUG_SPI
+
config DEBUG_TIMER
- bool "Timer Debug Output"
+ bool "Timer Debug Features"
default n
- depends on TIMER
---help---
- Enable timer debug SYSLOG output (disabled by default).
+ Enable timer debug features.
+
Support for this debug option is architecture-specific and may not
be available for some MCUs.
+if DEBUG_TIMER
+
+config DEBUG_TIMER_ERROR
+ bool "Timer Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable timer error output to SYSLOG.
+
+config DEBUG_TIMER_WARN
+ bool "Timer Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable timer warning output to SYSLOG.
+
+config DEBUG_TIMER_INFO
+ bool "Timer Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable timer informational output to SYSLOG.
+
+endif # DEBUG_TIMER
+
config DEBUG_USB
- bool "USB Debug Output"
+ bool "USB Debug Features"
default n
depends on USBDEV || USBHOST
---help---
- Enable usb debug SYSLOG output (disabled by default)
+ Enable USB debug features.
+
+if DEBUG_USB
+
+config DEBUG_USB_ERROR
+ bool "USB Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable USB error output to SYSLOG.
+
+config DEBUG_USB_WARN
+ bool "USB Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable USB warning output to SYSLOG.
+
+config DEBUG_USB_INFO
+ bool "USB Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable USB informational output to SYSLOG.
+
+endif # DEBUG_USB
config DEBUG_WATCHDOG
- bool "Watchdog Timer Debug Output"
+ bool "Watchdog Timer Debug Features"
default n
depends on WATCHDOG
---help---
- Enable watchdog timer debug SYSLOG output (disabled by default).
+ Enable watchdog timer debug features.
+
Support for this debug option is architecture-specific and may not
be available for some MCUs.
-endif # DEBUG
+if DEBUG_WATCHDOG
+
+config DEBUG_WATCHDOG_ERROR
+ bool "Watchdog Timer Error Output"
+ default n
+ depends on DEBUG_ERROR
+ ---help---
+ Enable watchdog time error output to SYSLOG.
+
+config DEBUG_WATCHDOG_WARN
+ bool "Watchdog Timer Warnings Output"
+ default n
+ depends on DEBUG_WARN
+ ---help---
+ Enable watchdog time warning output to SYSLOG.
+
+config DEBUG_WATCHDOG_INFO
+ bool "Watchdog Timer Informational Output"
+ default n
+ depends on DEBUG_INFO
+ ---help---
+ Enable watchdog time informational output to SYSLOG.
+
+endif # DEBUG_WATCHDOG
+endif # DEBUG_FEATURES
config ARCH_HAVE_STACKCHECK
bool
@@ -705,6 +1499,18 @@ config STACK_COLORATION
Only supported by a few architectures.
+config ARCH_HAVE_HEAPCHECK
+ bool
+ default n
+
+config HEAP_COLORATION
+ bool "Heap coloration"
+ default n
+ depends on ARCH_HAVE_HEAPCHECK
+ ---help---
+ Enable heap coloration to check heap usage. Only supported by a few
+ architectures.
+
config DEBUG_SYMBOLS
bool "Generate Debug Symbols"
default n
diff --git a/KernelLibs.mk b/KernelLibs.mk
index a7888d714dceec8e15641311fc2fe46a6886d748..719430b6c9be4d435f414d62813dd4b87022f35b 100644
--- a/KernelLibs.mk
+++ b/KernelLibs.mk
@@ -45,6 +45,12 @@
NUTTXLIBS = lib$(DELIM)libsched$(LIBEXT)
USERLIBS =
+# Driver support. Generally depends on file descriptor support but there
+# are some components in the drivers directory that are needed even if file
+# descriptors are not supported.
+
+NUTTXLIBS += lib$(DELIM)libdrivers$(LIBEXT)
+
# Add libraries for board support
NUTTXLIBS += lib$(DELIM)libconfigs$(LIBEXT)
@@ -83,11 +89,8 @@ ifeq ($(CONFIG_NFILE_DESCRIPTORS),0)
ifneq ($(CONFIG_NSOCKET_DESCRIPTORS),0)
NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT)
endif
-ifeq ($(CONFIG_NET),y)
-NUTTXLIBS += lib$(DELIM)libdrivers$(LIBEXT)
-endif
else
-NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT) lib$(DELIM)libdrivers$(LIBEXT) lib$(DELIM)libbinfmt$(LIBEXT)
+NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT) lib$(DELIM)libbinfmt$(LIBEXT)
endif
# Add libraries for the NX graphics sub-system
diff --git a/Makefile.unix b/Makefile.unix
index 022c7962169728566385ea3666e8b05b01815b47..220740c5bd3a08af6492d82b3113b10b080a50b3 100644
--- a/Makefile.unix
+++ b/Makefile.unix
@@ -178,21 +178,22 @@ endif
# This is the name of the final target (relative to the top level directorty)
-BIN = nuttx$(EXEEXT)
+NUTTXNAME = nuttx
+BIN = $(NUTTXNAME)$(EXEEXT)
all: $(BIN)
-.PHONY: context clean_context check_context export subdir_clean clean subdir_distclean distclean apps_clean apps_distclean
+.PHONY: dirlinks context clean_context check_context export subdir_clean clean subdir_distclean distclean apps_clean apps_distclean
-# Target used to copy include/nuttx/math.h. If CONFIG_ARCH_MATH_H is
+# Target used to copy include/nuttx/lib/math.h. If CONFIG_ARCH_MATH_H is
# defined, then there is an architecture specific math.h header file
# that will be included indirectly from include/math.h. But first, we
# have to copy math.h from include/nuttx/. to include/. Logic within
-# include/nuttx/math.h will hand the redirection to the architecture-
+# include/nuttx/lib/math.h will hand the redirection to the architecture-
# specific math.h header file.
#
# If the CONFIG_LIBM is defined, the Rhombus libm will be built at libc/math.
# Definitions and prototypes for the Rhombus libm are also contained in
-# include/nuttx/math.h and so the file must also be copied in that case.
+# include/nuttx/lib/math.h and so the file must also be copied in that case.
#
# If neither CONFIG_ARCH_MATH_H nor CONFIG_LIBM is defined, then no math.h
# header file will be provided. You would want that behavior if (1) you
@@ -208,8 +209,8 @@ endif
endif
ifeq ($(NEED_MATH_H),y)
-include/math.h: include/nuttx/math.h
- $(Q) cp -f include/nuttx/math.h include/math.h
+include/math.h: include/nuttx/lib/math.h
+ $(Q) cp -f include/nuttx/lib/math.h include/math.h
else
include/math.h:
endif
@@ -221,20 +222,20 @@ endif
# the settings in this float.h are actually correct for your platform!
ifeq ($(CONFIG_ARCH_FLOAT_H),y)
-include/float.h: include/nuttx/float.h
- $(Q) cp -f include/nuttx/float.h include/float.h
+include/float.h: include/nuttx/lib/float.h
+ $(Q) cp -f include/nuttx/lib/float.h include/float.h
else
include/float.h:
endif
-# Target used to copy include/nuttx/stdarg.h. If CONFIG_ARCH_STDARG_H is
+# Target used to copy include/nuttx/lib/stdarg.h. If CONFIG_ARCH_STDARG_H is
# defined, then there is an architecture specific stdarg.h header file
-# that will be included indirectly from include/stdarg.h. But first, we
+# that will be included indirectly from include/lib/stdarg.h. But first, we
# have to copy stdarg.h from include/nuttx/. to include/.
ifeq ($(CONFIG_ARCH_STDARG_H),y)
-include/stdarg.h: include/nuttx/stdarg.h
- $(Q) cp -f include/nuttx/stdarg.h include/stdarg.h
+include/stdarg.h: include/nuttx/lib/stdarg.h
+ $(Q) cp -f include/nuttx/lib/stdarg.h include/stdarg.h
else
include/stdarg.h:
endif
@@ -280,16 +281,6 @@ tools/cnvwindeps$(HOSTEXEEXT):
# setting up symbolic links with 'generic' directory names to specific,
# configured directories.
#
-# Link the apps/include directory to include/apps
-
-include/apps: Make.defs
-ifneq ($(APPDIR),)
- @echo "LN: include/apps to $(APPDIR)/include"
- $(Q) if [ -d $(TOPDIR)/$(APPDIR)/include ]; then \
- $(DIRLINK) $(TOPDIR)/$(APPDIR)/include include/apps; \
- fi
-endif
-
# Link the arch//include directory to include/arch
include/arch: Make.defs
@@ -324,7 +315,9 @@ ifneq ($(CONFIG_ARCH_CHIP),)
$(Q) $(DIRLINK) $(TOPDIR)/$(ARCH_INC)/$(CONFIG_ARCH_CHIP) include/arch/chip
endif
-dirlinks: include/arch include/arch/board include/arch/chip $(ARCH_SRC)/board $(ARCH_SRC)/chip include/apps
+dirlinks: include/arch include/arch/board include/arch/chip $(ARCH_SRC)/board $(ARCH_SRC)/chip
+ $(Q) $(MAKE) -C configs dirlinks TOPDIR="$(TOPDIR)"
+ $(Q) $(MAKE) -C $(CONFIG_APPS_DIR) dirlinks TOPDIR="$(TOPDIR)"
# context
#
@@ -344,6 +337,7 @@ context: check_context include/nuttx/config.h include/nuttx/version.h include/ma
# and symbolic links created by the context target.
clean_context:
+ $(Q) $(MAKE) -C configs TOPDIR="$(TOPDIR)" clean_context
$(call DELFILE, include/nuttx/config.h)
$(call DELFILE, include/nuttx/version.h)
$(call DELFILE, include/math.h)
@@ -353,7 +347,6 @@ clean_context:
$(Q) $(DIRUNLINK) include/arch
$(Q) $(DIRUNLINK) $(ARCH_SRC)/board
$(Q) $(DIRUNLINK) $(ARCH_SRC)/chip
- $(Q) $(DIRUNLINK) include/apps
# check_context
#
@@ -413,28 +406,28 @@ pass2: pass2deps
cp -f $(BIN) /tftpboot/$(BIN).${CONFIG_ARCH}; \
fi
ifeq ($(CONFIG_RRLOAD_BINARY),y)
- @echo "MK: $(BIN).rr"
- $(Q) $(TOPDIR)/tools/mkimage.sh --Prefix $(CROSSDEV) $(BIN) $(BIN).rr
+ @echo "MK: $(NUTTXNAME).rr"
+ $(Q) $(TOPDIR)/tools/mkimage.sh --Prefix $(CROSSDEV) $(BIN) $(NUTTXNAME).rr
$(Q) if [ -w /tftpboot ] ; then \
- cp -f $(BIN).rr /tftpboot/$(BIN).rr.$(CONFIG_ARCH); \
+ cp -f $(NUTTXNAME).rr /tftpboot/$(NUTTXNAME).rr.$(CONFIG_ARCH); \
fi
endif
ifeq ($(CONFIG_INTELHEX_BINARY),y)
- @echo "CP: $(BIN).hex"
- $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex $(BIN) $(BIN).hex
+ @echo "CP: $(NUTTXNAME).hex"
+ $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex $(BIN) $(NUTTXNAME).hex
endif
ifeq ($(CONFIG_MOTOROLA_SREC),y)
- @echo "CP: $(BIN).srec"
- $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec $(BIN) $(BIN).srec
+ @echo "CP: $(NUTTXNAME).srec"
+ $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec $(BIN) $(NUTTXNAME).srec
endif
ifeq ($(CONFIG_RAW_BINARY),y)
- @echo "CP: $(BIN).bin"
- $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary $(BIN) $(BIN).bin
+ @echo "CP: $(NUTTXNAME).bin"
+ $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary $(BIN) $(NUTTXNAME).bin
endif
ifeq ($(CONFIG_UBOOT_UIMAGE),y)
@echo "MKIMAGE: uImage"
$(Q) mkimage -A arm -O linux -C none -T kernel -a $(CONFIG_UIMAGE_LOAD_ADDRESS) \
- -e $(CONFIG_UIMAGE_ENTRY_POINT) -n $(BIN) -d $(BIN).bin uImage
+ -e $(CONFIG_UIMAGE_ENTRY_POINT) -n $(BIN) -d $(NUTTXNAME).bin uImage
$(Q) if [ -w /tftpboot ] ; then \
cp -f uImage /tftpboot/uImage; \
fi
@@ -480,24 +473,36 @@ pass2dep: context tools/mkdeps$(HOSTEXEEXT) tools/cnvwindeps$(HOSTEXEEXT)
# location: http://ymorin.is-a-geek.org/projects/kconfig-frontends. See
# README.txt file in the NuttX tools GIT repository for additional information.
-config: apps_preconfig
+do_config: dirlinks apps_preconfig
$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-conf Kconfig
-oldconfig: apps_preconfig
+config: do_config clean_context
+
+do_oldconfig: dirlinks apps_preconfig
$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-conf --oldconfig Kconfig
-olddefconfig: apps_preconfig
+oldconfig: do_oldconfig clean_context
+
+do_olddefconfig: dirlinks apps_preconfig
$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-conf --olddefconfig Kconfig
-menuconfig: apps_preconfig
+olddefconfig: do_olddefconfig clean_context
+
+do_menuconfig: dirlinks apps_preconfig
$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-mconf Kconfig
-qconfig: apps_preconfig
+menuconfig: do_menuconfig clean_context
+
+do_qconfig: dirlinks apps_preconfig
$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-qconf Kconfig
-gconfig: apps_preconfig
+qconfig: do_qconfig clean_context
+
+gconfig: dirlinks apps_preconfig
$(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-gconf Kconfig
+gconfig: do_gconfig clean_context
+
# export
#
# The export target will package the NuttX libraries and header files into
diff --git a/Makefile.win b/Makefile.win
index 5a71a42122b76d51fa96d2422549c6f45480c04a..feb94d5eb3ff973dbd901ea9eed57d66808be185 100644
--- a/Makefile.win
+++ b/Makefile.win
@@ -171,10 +171,11 @@ endif
# This is the name of the final target (relative to the top level directorty)
-BIN = nuttx$(EXEEXT)
+NUTTXNAME = nuttx
+BIN = $(NUTTXNAME)$(EXEEXT)
all: $(BIN)
-.PHONY: context clean_context check_context configenv config oldconfig menuconfig export subdir_clean clean subdir_distclean distclean apps_clean apps_distclean
+.PHONY: dirlinks context clean_context check_context configenv config oldconfig menuconfig export subdir_clean clean subdir_distclean distclean apps_clean apps_distclean
# Target used to copy include\nuttx\math.h. If CONFIG_ARCH_MATH_H is
# defined, then there is an architecture specific math.h header file
@@ -275,19 +276,6 @@ tools\mkdeps$(HOSTEXEEXT):
# setting up symbolic links with 'generic' directory names to specific,
# configured directories.
#
-# Link the apps\include directory to include\apps
-
-include\apps: Make.defs
-ifneq ($(APPDIR),)
- @echo LN: include\apps $(APPDIR)\include
-ifeq ($(CONFIG_WINDOWS_MKLINK),y)
- $(Q) /user:administrator mklink /d include\apps $(APPDIR)\include
-else
- $(Q) xcopy $(APPDIR)\include include\apps /c /q /s /e /y /i
- $(Q) echo FAKELNK > include\apps\.fakelnk
-endif
-endif
-
# Link the arch\\include directory to include\arch
include\arch: Make.defs
@@ -347,7 +335,9 @@ else
endif
endif
-dirlinks: include\arch include\arch\board include\arch\chip $(ARCH_SRC)\board $(ARCH_SRC)\chip include\apps
+dirlinks: include\arch include\arch\board include\arch\chip $(ARCH_SRC)\board $(ARCH_SRC)\chip
+ $(Q) $(MAKE) -C configs dirlinks TOPDIR="$(TOPDIR)"
+ $(Q) $(MAKE) -C $(CONFIG_APPS_DIR) dirlinks TOPDIR="$(TOPDIR)"
# context
#
@@ -374,7 +364,6 @@ clean_context:
$(call DELDIR, include\arch)
$(call DELDIR, $(ARCH_SRC)\board)
$(call DELDIR, $(ARCH_SRC)\chip)
- $(call DELDIR, include\apps)
# check_context
#
@@ -428,20 +417,20 @@ pass2deps: pass2dep $(NUTTXLIBS)
pass2: pass2deps
$(Q) $(MAKE) -C $(ARCH_SRC) TOPDIR="$(TOPDIR)" EXTRA_OBJS="$(EXTRA_OBJS)" LINKLIBS="$(LINKLIBS)" EXTRADEFINES=$(KDEFINE) $(BIN)
ifeq ($(CONFIG_RRLOAD_BINARY),y)
- @echo "MK: $(BIN).rr"
- $(Q) $(TOPDIR)\tools\mkimage.sh --Prefix $(CROSSDEV) $(BIN) $(BIN).rr
+ @echo "MK: $(NUTTXNAME).rr"
+ $(Q) $(TOPDIR)\tools\mkimage.sh --Prefix $(CROSSDEV) $(BIN) $(NUTTXNAME).rr
endif
ifeq ($(CONFIG_INTELHEX_BINARY),y)
- @echo "CP: $(BIN).hex"
- $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex $(BIN) $(BIN).hex
+ @echo "CP: $(NUTTXNAME).hex"
+ $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O ihex $(BIN) $(NUTTXNAME).hex
endif
ifeq ($(CONFIG_MOTOROLA_SREC),y)
- @echo "CP: $(BIN).srec"
- $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec $(BIN) $(BIN).srec
+ @echo "CP: $(NUTTXNAME).srec"
+ $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O srec $(BIN) $(NUTTXNAME).srec
endif
ifeq ($(CONFIG_RAW_BINARY),y)
- @echo "CP: $(BIN).bin"
- $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary $(BIN) $(BIN).bin
+ @echo "CP: $(NUTTXNAME).bin"
+ $(Q) $(OBJCOPY) $(OBJCOPYARGS) -O binary $(BIN) $(NUTTXNAME).bin
endif
# $(BIN)
@@ -480,18 +469,26 @@ pass2dep: context tools\mkdeps$(HOSTEXEEXT)
# location: http://ymorin.is-a-geek.org/projects/kconfig-frontends. See
# misc\tools\README.txt for additional information.
-config: apps_preconfig
+do_config: dirlinks apps_preconfig
$(Q) set APPSDIR=$(patsubst "%",%,${CONFIG_APPS_DIR})& kconfig-conf Kconfig
-oldconfig: apps_preconfig
+config: do_config clean_context
+
+do_oldconfig: dirlinks apps_preconfig
$(Q) set APPSDIR=$(patsubst "%",%,${CONFIG_APPS_DIR})& kconfig-conf --oldconfig Kconfig
-olddefconfig: apps_preconfig
+oldconfig: do_oldconfig clean_context
+
+do_olddefconfig: dirlinks apps_preconfig
$(Q) set APPSDIR=$(patsubst "%",%,${CONFIG_APPS_DIR})& kconfig-conf --olddefconfig Kconfig
-menuconfig: configenv apps_preconfig
+olddefconfig: do_olddefconfig clean_context
+
+do_menuconfig: dirlinks configenv apps_preconfig
$(Q) set APPSDIR=$(patsubst "%",%,${CONFIG_APPS_DIR})& kconfig-mconf Kconfig
+menuconfig: do_menuconfig clean_context
+
# export
#
# The export target will package the NuttX libraries and header files into
diff --git a/ProtectedLibs.mk b/ProtectedLibs.mk
index 70185eacf47162a4f850a36919d398786f3f97b2..4f2e2c6072d35fc34030967de75fa7fe93434c5d 100644
--- a/ProtectedLibs.mk
+++ b/ProtectedLibs.mk
@@ -45,6 +45,12 @@
NUTTXLIBS = lib$(DELIM)libsched$(LIBEXT)
USERLIBS =
+# Driver support. Generally depends on file descriptor support but there
+# are some components in the drivers directory that are needed even if file
+# descriptors are not supported.
+
+NUTTXLIBS += lib$(DELIM)libdrivers$(LIBEXT)
+
# Add libraries for board support
NUTTXLIBS += lib$(DELIM)libconfigs$(LIBEXT)
@@ -89,11 +95,8 @@ ifeq ($(CONFIG_NFILE_DESCRIPTORS),0)
ifneq ($(CONFIG_NSOCKET_DESCRIPTORS),0)
NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT)
endif
-ifeq ($(CONFIG_NET),y)
-NUTTXLIBS += lib$(DELIM)libdrivers$(LIBEXT)
-endif
else
-NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT) lib$(DELIM)libdrivers$(LIBEXT) lib$(DELIM)libbinfmt$(LIBEXT)
+NUTTXLIBS += lib$(DELIM)libfs$(LIBEXT) lib$(DELIM)libbinfmt$(LIBEXT)
endif
# Add libraries for the NX graphics sub-system
diff --git a/README.txt b/README.txt
index db0e5e6c10b2e3f515978c38b7a3223be767639c..ed3d41c30f8420f294941b1eb721d996ca277999 100644
--- a/README.txt
+++ b/README.txt
@@ -1,8 +1,10 @@
README
^^^^^^
- o Installation
+ o Environments
- Installing Cygwin
+ - Ubuntu Bash under Windows 10
+ o Installation
- Download and Unpack
- Semi-Optional apps/ Package
- Installation Directories with Spaces in the Path
@@ -15,6 +17,7 @@ README
- NuttX Configuration Tool
- Finding Selections in the Configuration Menus
- Reveal Hidden Configuration Options
+ - Make Sure that You on on the Right Platform
- Comparing Two Configurations
- Incompatibilities with Older Configurations
- NuttX Configuration Tool under DOS
@@ -33,21 +36,49 @@ README
- Window Native Toolchain Issues
o Documentation
-INSTALLATION
+ENVIRONMENTS
^^^^^^^^^^^^
- NuttX may be installed and built on a Linux system or on a Windows
- system if Cygwin is installed. The MSYS environment is an option
- to Cygwin on the Windows platform. However, I have little experience
- that that configuration and it will not be discussed in this README
- file.
-
- Instructions for installation of Cygwin on Windows system are provided
- in the following paragraph.
-
- NuttX can also be installed and built on a native Windows system, but
- with some potential tool-related issues (see the discussion "Native
- Windows Build" below).
+ NuttX requires a POSIX development environment such as you would find under
+ Linux or OSX. NuttX may be also be installed and built on Windows system
+ if you also provde such a POSIX development environment. Options for a
+ POSIX development environment under Windows include:
+
+ - An installation of Linux on a virtual machine (VM) in Windows. I have
+ not been happy using a VM myself. I have had stability problems with
+ open source VMs and commercial VMs cost more than I want to spend.
+ Sharing files with Linux running in a VM is awkward; sharing devices
+ connected to the Windows box with Linux in a VM is, at the very least,
+ confusing; Using Windows tools (such as Segger J-Link) with files
+ built under the Linux VM is not a possibility.
+
+ - The Cygwin environment. Instructions for installation of Cygwin on a
+ Windows system are provided in the following paragraph, "Installing
+ Cygwin". Cygwin is a mature, well-tested, and very convenient
+ environment. It is especially expecially convenient if you need to
+ integrate with Windows tools and files. Downsides are that the
+ installation time is very long and the compile times are slow.
+
+ - Ubuntu/Bash shell under Windows 10. This is a new option under
+ Windows 10. See the section "Ubuntu Bash under Windows 10" below.
+ This is an improvement over Cygwin if your concern is compile time;
+ its build performance is comparable to native Linux, certainly better
+ than the Cygwin build time. It also installs in a tiny fraction of
+ the time as Cygwin, perhaps 20 minutes for the basic Ubuntu install
+ (vs. more than a day for the complete Cygwin install).
+
+ - The MSYS environment. I have no experience using the MSYS environment
+ and that configuration will not be discussed in this README file.
+ See http://www.mingw.org/wiki/MSYS if you are interested in
+ using MSYS. People report to me that they have used MSYS
+ successfully. I suppose that the advantages of the MSYS environemnt
+ is that it is closer to a native Windows environment and uses only a
+ minimal of add-on POSIX-land tools.
+
+ - NuttX can also be installed and built on a native Windows system, but
+ with some potential tool-related issues (see the discussion "Native
+ Windows Build" under "Building NuttX" below). GNUWin32 is used to
+ provide compatible native windows tools.
Installing Cygwin
-----------------
@@ -83,6 +114,9 @@ Installing Cygwin
"Publishing". You can try omitting KDE, Gnome, GTK, and other
graphics packages if you don't plan to use them.
+ Perhaps a minimum set would be those packages listed below for the
+ "Ubuntu Bash under Windows 10" installation?
+
After installing Cygwin, you will get lots of links for installed
tools and shells. I use the RXVT native shell. It is fast and reliable
and does not require you to run the Cygwin X server (which is neither
@@ -94,6 +128,136 @@ Installing Cygwin
about 5GiB. The server I selected was also very slow so it took
over a day to do the whole install!
+Ubuntu Bash under Windows 10
+----------------------------
+
+ A better version of a command-line only Ubuntu under Windows 10 (beta)
+ has recently been made available from Microsoft.
+
+ Installation
+ ------------
+ Installation instructions abound on the Internet complete with screen
+ shots. I will attempt to duplicate those instructions in full here.
+ Here are the simplified installation steps:
+
+ - Open "Settings".
+ - Click on "Update & security".
+ - Click on "For Developers".
+ - Under "Use developer features", select the "Developer mode" option to
+ setup the environment to install Bash.
+ - A message box should pop up. Click "Yes" to turn on developer mode.
+ - After the necessary components install, you'll need to restart your
+ computer.
+
+ Once your computer reboots:
+
+ - Open "Control Panel".
+ - Click on "Programs".
+ - Click on "Turn Windows features on or off".
+ - A list of features will pop up, check the "Windows Subsystem for Linux
+ (beta)" option.
+ - Click OK.
+ - Once the components installed on your computer, click the "Restart
+ now" button to complete the task.
+
+ After your computer restarts, you will notice that Bash will not appear in
+ the "Recently added" list of apps, this is because Bash isn't actually
+ installed yet. Now that you have setup the necessary components, use the
+ following steps to complete the installation of Bash:
+
+ - Open "Start", do a search for bash.exe, and press "Enter".
+ - On the command prompt, type y and press Enter to download and install
+ Bash from the Windows Store. This will take awhile.
+ - Then you'll need to create a default UNIX user account. This account
+ doesn't have to be the same as your Windows account. Enter the
+ username in the required field and press Enter (you can't use the
+ username "admin").
+ - Close the "bash.exe" command prompt.
+
+ Now that you completed the installation and setup, you can open the Bash
+ tool from the Start menu like you would with any other app.
+
+ Accessing Windows Files from Ubuntu
+ -----------------------------------
+ File sysems will be mounted under "/mnt" so for example "C:\Program Files"
+ appears at "/mnt/c/Program Files". This is as opposed to Cgwin where
+ the same directory would appear at "/cygdrive/c/Program Files".
+
+ With these differences (perhaps a few other Windows quirks) the Ubuntu
+ install works just like Ubuntu running natively on your PC.
+
+ Accessing Ubuntu Files From Windows
+ -----------------------------------
+ In Ubuntu Userspace for Windows, the Ubuntu file system root directory is
+ at:
+
+ %localappdata%\lxss\rootfs
+
+ Or
+
+ C:\Users\Username\AppData\Local\lxss\rootfs
+
+ Install Linux Software.
+ -----------------------
+ Use "sudo apt-get install ". As examples, this is how
+ you would get GIT:
+
+ $ sudo apt-get install git
+
+ This will get you a compiler for your host PC:
+
+ $ sudo apt-get install gcc
+
+ This will get you an ARM compiler for your target:
+
+ $ sudo apt-get install gcc-arm-none-eabi
+
+ NOTE: That is just an example. I am not sure if apt-get will give you a
+ current or usable compiler. You should carefully select your toolchain
+ for the needs of your project.]
+
+ You will also need to the get the kconfig-frontends configuration as
+ described below under "NuttX Configuration tool". In order build the
+ kconfig-frontends configuration tool you will also need: make, gperf,
+ flex, bison, and libncurses-dev.
+
+ That is enough to do a basic NuttX build.
+
+ Integrating with Windows Tools
+ ------------------------------
+ If you want to integrate with Windows native tools, then you would need
+ deal with the same kind of craziness as with integrating Cygwin with
+ native toolchains, see the section "Cygwin Build Problems" below.
+
+ However, there is currently no build support for using Windows native
+ tools with Ubuntu under Windows. This tool combination is made to work
+ with Cygwin through the use of the 'cygpath -w' tool that converts paths
+ from say '/cydrive/c/Program Files' to 'C:\Program Files'. There is,
+ however, no corresponding tool to convert '/mnt/c/Program Files' in the
+ Ubuntu environment.
+
+ Graphics Support
+ ----------------
+ The Ubuntu version support by Microsoft is a command-line only version.
+ There is no support for Linux graphics utilities.
+
+ This limititation is not a limitation of Ubuntu, however, only in what
+ Microsoft is willing to support. If you install a X-Server, then you
+ can also use basic graphics utilities. See for example:
+
+ http://www.howtogeek.com/261575/how-to-run-graphical-linux-desktop-applications-from-windows-10s-bash-shell/
+
+ Many Linux graphics programs would, however, also require a graphics
+ framework like GTK or Qt. So this might be a trip down the rabbit hole.
+
+INSTALLATION
+^^^^^^^^^^^^
+
+ There are two ways to get NuttX: You may download released, stable
+ tarballs from wither the Bitbucket or Sourceforge download locations.
+ Or you may get NuttX by cloning the Bitbucket GIT repositories. Let's
+ consider the released tarballs first:
+
Download and Unpack
-------------------
@@ -104,6 +268,11 @@ Download and Unpack
match the various instructions in the documentation and some scripts
in the source tree.
+ Download locations:
+
+ https://bitbucket.org/nuttx/nuttx/downloads
+ https://sourceforge.net/projects/nuttx/files/nuttx/
+
Semi-Optional apps/ Package
---------------------------
@@ -321,13 +490,13 @@ Notes about Header Files
If you have a custom, architecture specific math.h header file, then
that header file should be placed at arch//include/math.h. There
- is a stub math.h header file located at include/nuttx/math.h. This stub
+ is a stub math.h header file located at include/nuttx/lib/math.h. This stub
header file can be used to "redirect" the inclusion to an architecture-
specific math.h header file. If you add an architecture specific math.h
header file then you should also define CONFIG_ARCH_MATH_H=y in your
NuttX Configuration file. If CONFIG_ARCH_MATH_H is selected, then the
top-level Makefile will copy the stub math.h header file from
- include/nuttx/math.h to include/math.h where it will become the system
+ include/nuttx/lib/math.h to include/math.h where it will become the system
math.h header file. The stub math.h header file does nothing other
than to include that architecture-specific math.h header file as the
system math.h header file.
@@ -576,6 +745,38 @@ Reveal Hidden Configuration Options
cannot be selected and has no value). About all you do is to select
the option to see what the dependencies are.
+Make Sure that You on on the Right Platform
+-------------------------------------------
+
+ Saved configurations may run on Linux, Cygwin (32- or 64-bit), or other
+ platforms. The platform characteristics can be changed use 'make
+ menuconfig'. Sometimes this can be confusing due to the differences
+ between the platforms. Enter sethost.sh
+
+ sethost.sh is a simple script that changes a configuration to your
+ host platform. This can greatly simplify life if you use many different
+ configurations. For example, if you are running on Linux and you
+ configure like this:
+
+ $ cd tools
+ $ ./configure.sh board/configuration
+ $ cd ..
+
+ The you can use the following command to both (1) make sure that the
+ configuration is up to date, AND (2) the configuration is set up
+ correctly for Linux:
+
+ $ tools/sethost.sh -l
+
+ Or, if you are on a Windows/Cygwin 64-bit platform:
+
+ $ tools/sethost.sh -w
+
+ Other options are available from the help option built into the
+ script. You can see all options with:
+
+ $ tools/sethost.sh -h
+
Comparing Two Configurations
----------------------------
@@ -948,8 +1149,12 @@ Native Windows Build
--------------------
The beginnings of a Windows native build are in place but still not often
- used as of this writing. The windows native build logic initiated
- if CONFIG_WINDOWS_NATIVE=y is defined in the NuttX configuration file:
+ used as of this writing. The build was functional but because of lack of
+ use may find some issues to be resolved with this build configuration.
+
+ The windows native build logic initiated if CONFIG_WINDOWS_NATIVE=y is
+ defined in the NuttX configuration file:
+
This build:
@@ -960,10 +1165,13 @@ Native Windows Build
In this build, you cannot use a Cygwin or MSYS shell. Rather the build must
be performed in a Windows console window. Here is a better terminal than the
standard issue, CMD.exe terminal: ConEmu which can be downloaded from:
- http://code.google.com/p/conemu-maximus5/
+ https://sourceforge.net/projects/conemu/ or https://conemu.github.io/ .
Build Tools. The build still relies on some Unix-like commands. I use
- the GNUWin32 tools that can be downloaded from http://gnuwin32.sourceforge.net/.
+ the GNUWin32 tools that can be downloaded from http://gnuwin32.sourceforge.net/
+ using the 'Download all' selection. Individual packages can be download
+ instead if you know what you are doing and want a faster download (No, I
+ can't tell you which packages you should or should not download).
Host Compiler: I use the MingGW GCC compiler which can be downloaded from
http://www.mingw.org/. If you are using GNUWin32, then it is recommended
@@ -971,12 +1179,13 @@ Native Windows Build
This capability should still be considered a work in progress because:
- (1) It has not been verified on all targets and tools, and
- (2) it still lacks some of the creature-comforts of the more mature environments.
+ (1) It has not been verified on all targets and tools, and
+ (2) it still lacks some of the creature-comforts of the more mature
+ environments.
- There is an alternative to the setenv.sh script available for the Windows
- native environment: tools/configure.bat. See tools/README.txt for additional
- information.
+ There is an alternative to the setenv.sh script available for the Windows
+ native environment: tools/configure.bat. See tools/README.txt for additional
+ information.
Installing GNUWin32
-------------------
@@ -1209,7 +1418,7 @@ nuttx/
| |- arm/
| | `- src
| | `- lpc214x/README.txt
- | |- sh/
+ | |- renesas/
| | |- include/
| | | `-README.txt
| | |- src/
@@ -1238,18 +1447,14 @@ nuttx/
| | `- README.txt
| |- avr32dev1/
| | `- README.txt
+ | |- bambino-200e/
+ | | `- README.txt
| |- c5471evm/
| | `- README.txt
| |- cc3200-launchpad/
| | `- README.txt
| |- cloudctrl
| | `- README.txt
- | |- compal_e86
- | | `- README.txt
- | |- compal_e88
- | | `- README.txt
- | |- compal_e99
- | | `- README.txt
| |- demo0s12ne64/
| | `- README.txt
| |- dk-tm4c129x/
@@ -1279,6 +1484,10 @@ nuttx/
| | `- README.txt
| |- fire-stm32v2/
| | `- README.txt
+ | |- freedom-k64f/
+ | | `- README.txt
+ | |- freedom-k66f/
+ | | `- README.txt
| |- freedom-kl25z/
| | `- README.txt
| |- freedom-kl26z/
@@ -1321,7 +1530,7 @@ nuttx/
| | `- README.txt
| |- mirtoo/
| | `- README.txt
- | |- mt-db-x3/
+ | |- misoc/
| | `- README.txt
| |- moteino-mega/
| | `- README.txt
@@ -1354,6 +1563,8 @@ nuttx/
| | `- README.txt
| |- olimex-stm32-p207/
| | `- README.txt
+ | |- olimex-stm32-p407/
+ | | `- README.txt
| |- olimex-strp711/
| | `- README.txt
| |- open1788/
@@ -1370,12 +1581,8 @@ nuttx/
| | `- README.txt
| |- pic32mz-starterkit/
| | `- README.txt
- | |- pirelli_dpl10/
- | | `- README.txt
| |- qemu-i486/
| | `- README.txt
- | |- rgmp/
- | | `- README.txt
| |- sabre-6quad/
| | `- README.txt
| |- sama5d2-xult/
@@ -1394,6 +1601,8 @@ nuttx/
| | `- README.txt
| |- sam3u-ek/
| | `- README.txt
+ | |- sam4cmp-db
+ | | `- README.txt
| |- sam4e-ek/
| | `- README.txt
| |- sam4l-xplained/
@@ -1440,6 +1649,8 @@ nuttx/
| | `- README.txt
| |- stm32f746g-disco/
| | `- README.txt
+ | |- stm32l476-mdk/
+ | | `- README.txt
| |- stm32l476vg-disco/
| | `- README.txt
| |- stm32ldiscovery/
@@ -1460,6 +1671,8 @@ nuttx/
| | `- README.txt
| |- twr-k60n512/
| | `- README.txt
+ | |- twr-k64f120m/
+ | | `- README.txt
| |- u-blox-co27/
| | `- README.txt
| |- ubw32/
@@ -1497,8 +1710,6 @@ nuttx/
| | `- README.txt
| |- sensors/
| | `- README.txt
- | |- sercomm/
- | | `- README.txt
| |- syslog/
| | `- README.txt
| `- README.txt
@@ -1520,6 +1731,8 @@ nuttx/
|- lib/
| `- README.txt
|- libc/
+ | |- zoneinfo
+ | | `- README.txt
| `- README.txt
|- libnx/
| `- README.txt
@@ -1548,7 +1761,8 @@ apps/
|- gpsutils/
| `- minmea/README.txt
|- graphics/
- | `- tiff/README.txt
+ | |- tiff/README.txt
+ | `- traveler/tools/tcledit/README.txt
|- interpreters/
| |- bas
| | `- README.txt
@@ -1586,9 +1800,7 @@ apps/
| | `- README.txt
| |- usbmsc
| | `- README.txt
- | |- zmodem
- | | `- README.txt
- | `- zoneinfo
+ | `- zmodem
| `- README.txt
`- README.txt
diff --git a/ReleaseNotes b/ReleaseNotes
index 89cf4119a4d6c8e6d8c3d67735711e75b99d81fd..ed69375e61034f336d44cee9ce212b69711c422b 100644
--- a/ReleaseNotes
+++ b/ReleaseNotes
@@ -2570,7 +2570,7 @@ New features and extended functionality:
particular for a CDC/ACM with MSC USB composite driver).
Added a new RAM logging driver. This will allow debug output into
- a RAM buffer associated with a character driver at /dev/syslog.
+ a RAM buffer associated with a character driver at /dev/ramlog.
Added the new command 'dmesg' to NSH that can be used to dump the
current contents of the log. This is useful for systems that do not
have the usual serial console (for example, if you only have a
@@ -5303,7 +5303,8 @@ Additional new features and extended functionality:
can be re-enabled if needed via configuration option.
- NXFFS: Make the start up scan of the media a configuration option.
It just takes to long and is not really necessary! Those rare cases
- where the scan was helpful can be fixed using flash_eraseall().
+ where the scan was helpful can be fixed using MDIOC_BULKERASE IOCTL
+ command.
* General Drivers:
@@ -8904,25 +8905,25 @@ Additional new features and extended functionality:
This is based on the similar SAMD20 Xplained Pro board.
* Freescale/NXP KL:
-
+
- KL25Z64: Added support for the KL25Z64. The KL25Z64 is a lower
memory variant of the KL25Z128 and is used on the Teensy LC. From
Michael as SourceForge patch 50.
* Freescale/NXP KL Boards:
-
+
- Teensy-LC: Add board support for the Teensy LC board. Support is
based off the Freedom KL25Z board. LED, PWM, and UART0 have been
tested. The SPI pins are mapped correctly but have not yet been
tested. From Michael Hope as SourceForge patch 51.
* NXP LPC111x:
-
+
- LPC111x: Support for the LPC11xx family (the LPC1115 MCU in
particular). Contributed by Alan Carvalho de Assis.
* NXP LPC111x Boards:
-
+
- LPCXpresso LPC1115: Support for the LPCXpression LPC1115
board. Contributed by Alan Carvalho de Assis.
@@ -8990,7 +8991,7 @@ Additional new features and extended functionality:
* Applications: apps/system:
- - apps/system/zoneinfo: Add logic to build a ROMFS file system
+ - nuttx/zoneinfo: Add logic to build a ROMFS file system
containing the timezone data.
* Applications: apps/nshlib:
@@ -9062,7 +9063,7 @@ detailed bugfix information):
for mq_setattr() and mq_getattr(). This is necessary in protected
and kernel builds because in those cases the message queue
structure is protected and cannot be accessed directly from user
- mode code. Noted by Jouko Holopainen.
+ mode code.
* File Systems/Block Drivers/MTD:
@@ -9157,7 +9158,7 @@ detailed bugfix information):
- LPC17 USB OHCI: Correct some initialization of data structures.
When hub support is enabled, it would overwrite the end of an array
and clobber some OS data structures.
- - LPC17xx Ethernet: Review, update, and modify the Ethernet driver so
+ - LPC17xx Ethernet: Review, update, and modify the Ethernet driver so
that it works better with CONFIG_NET_NOINTS=y. Also, update all
LPC17xx networking configurations so that they have
CONFIG_NET_NOTINTS=y selected.
@@ -9584,7 +9585,7 @@ detailed bugfix information):
* ARMv7-A:
- Cortex-A5 vfork(): Fix a Cortex-A compilation error when system
- calls are enabled in modes other than CONFIG_BUILD_KERNEL.
+ calls are enabled in modes other than CONFIG_BUILD_KERNEL.
* Atmel SAMA5 Drivers:
@@ -10098,7 +10099,7 @@ Additional new features and extended functionality:
- ps command: The 'ps' command now uses /proc// to obtain task
status information. A consequence of this is that you cannot use
the 'ps' command if the procfs is not enabled and mounted at /proc.
-
+
* Applications: apps/system:
- apps/system/hexed: Port the hexed command line hexadeciamal editor
@@ -10143,7 +10144,7 @@ detailed bugfix information):
* Graphics/Graphic Drivers:
- - ILI9432: Fixed errors in orientation. Portrait, RPortrait, and
+ - ILI9432: Fixed errors in orientation. Portrait, RPortrait, and
Landscript should work correly now. They were displayed mirrored.
From Marco Krahl.
@@ -10320,7 +10321,7 @@ Additional new features and extended functionality:
pointer indicates that the referenced object may reside either in
flash or in RAM. The compiler automatically makes 32-bit pointer
with flag indicating whether referenced object is in flash or RAM
- and generates code to access either in run-time. Thus, any function
+ and generates code to access either in run-time. Thus, any function
hat accepts __memx object can transparently work with RAM and flash
objects.
For platforms with a Harvard architecture and a very small RAM like
@@ -10349,7 +10350,7 @@ Additional new features and extended functionality:
dependencies generated by a Windows compiler so that they can be
used with the Cygwin make.
- tools/mkwindeps.sh: A script that coordinates use of cnvwindeps.exe.
- Dependencies now work on the Cygwin platform when using a Windows
+ Dependencies now work on the Cygwin platform when using a Windows
ative toolchain.
* Applications: NSH
@@ -10515,7 +10516,7 @@ Additional new features and extended functionality:
implemented via ioctl calls. However, it does not yet implement
the standard ADC interface. From Alexander Entinger.
- U-Blox Modem: Add an upper half driver for the U-Blox Modem. From
- Vladimir Komendantskiy.
+ Vladimir Komendantskiy.
- I2C: Add an I2C, "upper half", character drivers to support raw I2C
data transfers for test applications.
- RGB LED: Add a driver to manage a RGB LED via PWM. From Alan
@@ -10716,3 +10717,2832 @@ detailed bugfix information):
- Moved C++ initialization logic out of the RTOS and into the
application space, specifically to apps/platform/board, where it
belongs.
+
+NuttX-7.16 Release Notes
+------------------------
+
+The 116th release of NuttX, Version 7.16, was made on June 1, 2016,
+and is available for download from the Bitbucket.org website. Note
+that release consists of two tarballs: nuttx-7.16.tar.gz and
+apps-7.16.tar.gz. These are available from:
+
+ https://bitbucket.org/nuttx/nuttx/downloads
+ https://bitbucket.org/nuttx/apps/downloads
+
+Both may be needed (see the top-level nuttx/README.txt file for build
+information).
+
+Additional new features and extended functionality:
+
+ * Core OS:
+
+ - Power Management: Add activity domain to all PM interfaces and
+ driver callbacks. If CONFIG_PM_NDOMAINS == 1, then the legacy
+ behavior is preserved. If CONFIG_PM_NDOMAINS > 1, then multiple
+ PM domains are supported. This will allow separate control for
+ certain power management groups. For example, a network can be
+ shut down without affect an ongoing UI (and vice versa).
+ - board_app_initialize(): board_app_initialize() now accepts an
+ argument that may be used to support initialization in different
+ configurations.
+
+ * File System and Block and MTD Drivers:
+
+ - N25Qxxx: Add MTD support for Micron N25Qxxx family of QSPI flash.
+ From Dave (ziggurat29).
+ - SST26F: Add an MTD driver for SST26F spi/qspi flash devices (SPI
+ mode only). From Sebastien Lorquet.
+ - File Descriptor Detach: Add logic to detach a file structure from a
+ file descriptor. This is for use only within the OS. It permits an
+ open file or driver to be used across multiple threads.
+
+ * Networking and Network Drivers:
+
+ - listen()/accept(): Separate out psock_listen() and psock_accepti()
+ for internal, thread independent OS usage (i.e., without a socket
+ descriptor).
+ - VNC Server: Add support for a VNC server. This logic is code
+ complete and functional, but not well tested.
+
+ * Graphics and Graphic Drivers:
+
+ - Framebuffer driver: Add a display number to each interface in order
+ to support multiple display devices.
+ - VNC Server: Add support for a VNC server. This logic is code
+ complete and functional, but not well tested.
+ - LCD Backpack: Add support for PCF8574 LCD Backpack driver. This
+ driver supports an interface board that is based on the PCF8574 I/O
+ expander and supports the HD44780-based (or compatible) LCD modules.
+ There are a myriad of different vendors of such, but they are
+ principally the same, save wiring and minor features like jumpers
+ for I2C addresses. This driver supports known and unknown variants.
+ From Dave (ziggurat29).
+
+ * Common Device Drivers:
+
+ - RTC: Simplify the RTC interface. The old interface was way too
+ complex and was not fully implemented anywhere.
+ - BH1750FVI: Add a character driver for Rohm Ambient Light Sensor
+ BH1750FVI. From Alan Carvalho de Assis.
+ - CAN: Improve CAN error reporting. From Frank Benkert.
+ - aes.h: Modifications to the crypto API needed for LPC43xx. From
+ Alexander Vasiljev.
+ - ADC: Interface no longer uses global adc_receive() call. Added a
+ new bind() method to the ADC interface. Now the ADC upper half
+ driver will register its receipt-of-data callback. This change
+ allows the ADC lower half driver to be used with a differ ADC upper
+ half.
+
+ * Simulation Platform:
+
+ - Linux Host Networking: Enhance networking support for the
+ simulation under Linux. Includes updated support for Linux TUN/TAP,
+ and the addition of support for Linux bridge devices. From Steve.
+
+ * ARMv7-A, ARMv7-R, and ARMv7-M:
+
+ - ARMv7-M: Convert more assembly language files for use with the IAR
+ toolchain. From Kha Vo.
+ - ARMv7-A: Complete re-design of SMP-related logic to initialize each
+ CPUn, n > 0, when CONFIG_SMP=y.
+
+ * Atmel SAMV7:
+
+ - Add a JTAG config and ERASE config to Kconfig to set the
+ CCFG_SYSIO SYSIO Pins. From David Sidrane.
+ - System Reset: Add the up_systemreset interface to the samv7 arch. The
+ approach is slightly different in that: 1) It enables ARCH_HAVE_RESET
+ and allows the user to set if, and for how long, to drive External
+ nRST signal. It also does not contain a default board_reset, as that
+ really should be done in the config's src if CONFIG_BOARDCTL_RESET
+ is defined. From David Sidrane.
+
+ * Atmel SAMV7 Boards:
+
+ - SAMV71-XULT: Add configuration(s) that were be used to verify VNC
+ graphics output as well as mouse and keyboard input.
+
+ * NXP Freescale i.MX6 Boards:
+
+ - Sabre-6Quad: The basic i.MX6 port is complete. This is a minimal
+ port at present and probably still has some as-of-yet-undiscovered
+ issues.
+ - Sabre-6Quad: Basic SMP NSH configuration is now working. But this
+ is probably only because the SMP test case does not stress the
+ logic. There are know outstanding SMP issues as noted in the
+ Sabre-6Quad README.txt file.
+
+ * NXP Freescale LPC43xx:
+
+ - LPC4337jet100: Add definitions for the LPC4337jet100 chip. From
+ Alexander Vasiljev.
+
+ * NXP Freescale LPC43xx Drivers:
+
+ - AES: Add AES support. From Alexander Vasiljev.
+
+ * STMicro STM32:
+
+ - STM32 L4: Add configuration options to allow SRAM2 to be used for
+ heap, or not at all, and to zero-initialize it on OS start, or not
+ at all. From Dave dev@ziggurat29.com.
+ - STM32 L4: Add support for HSE and MSI clocks, and auto trim of MSI
+ to LSE (needed for USB). From Dave (ziggurat29)
+ - STM32 L4: Add support for unique id function to arch; modified board
+ to support unique id boardctl. From Dave (ziggurat29)
+
+ * STMicro STM32 Drivers:
+
+ - STM32 F4 RTC: Add a custom RTC driver with support for alarms. From
+ Neil Hancock.
+ - STM32 L4 QSPI: Add a QSPI driver with DMA support and (optional
+ memory mapped mode support. From Dave ziggurat29).
+ - STM32, STM32 L4, and STM32 F7 Serial: Add support for compliant
+ SD-style breaks. From David Sidrane.
+ - STM32 L4 CAN: Add CAN support for STM32L4. From Sebastien Lorquet.
+ - STM32 1-Wire: Add support for a custom 1-wire driver. The serial
+ driver already supports a 1-wire interface, but this driver uses the
+ same serial logic to implement a lower half driver much like the
+ I2C lower half driver. From Aleksandr Vyhovanec.
+ - STM32 L4 SPI: Add support for SPI 4 and 5 on stm32f411 chips. From
+ Konstantin Berezenko.
+ - STM32 ADC: Allow omitting use of channels in a lower part of PWM.
+ From Pierre-noel Bouteville.
+ - STM32 L4 I2C: Get I2C working for STM32L4. From Dave (ziggurat29).
+
+ * STMicro STM32 Boards:
+
+ - STM3220G-EVAL: Add support for both the IAR and uVision GCC IDEs.
+ From Kha Vo.
+ - STM32F429I Discovery: Add support for the uVision GCC IDE. From
+ Kha Vo.
+ - STM32F4 Discovery: Integrate BH1750FVI driver in the STM32F4 Discovery
+ board. From Alan Carvalho de Assis.
+ - STM32L476VG Discovery: Add support for QSPI based N25Qxxx flash.
+ From Dave (ziggurat29)
+ - STM32L476VG Discovery: Add board ioctls for allowing user application
+ to cause QSPI memory mapped mode to be engaged and disengaged. Also
+ partitioned QSPI flash for file system and other (eventually xip).
+ From Dave (ziggurat29)
+ - Nucleo-144: Basic port for the Nucleo-144 board with the STM32F746ZG
+ MCU. From Kconstantin Berezenko.
+ - STM32F103 Minimum: Add support for this minimual STM32F103CBT6 "blue"
+ board. From Alan Carvalho de Assis.
+ - STM32F411E Discovery: Add basic configuration for stm32f411e-disco
+ board with STM32F411VE chip. From Konstantin Berezenko.
+
+ * Build/Configuration System:
+
+ - Moved NuttX repository to https://bitbucket.org/nuttx/nuttx.
+ Eliminated use of sub-modules.
+ - Add support for the IAR toolchain for the limited case of the ARMv7-M
+ architecture and the STM32 chip. From Aleksandr Vyhovanec.
+ - make export: Pass top-level make to the script to allow -j greater
+ than 1. From David Sidrane.
+ - fs/Kconfig: Allow CONFIG_FS_WRITABLE to be manually selectable. This
+ is needed when there are no writable file systems, but write support
+ is still needed in BCH or FTL.
+ - arch/*/Makefile: Add definitions that can be overrided to use GCC
+ instead of LD in the final link. From Paul Alexander Patience .
+
+ * Applications: apps/netutils:
+
+ - apps/netutils/esp8266: ESP8266 driver application. From Pierre-noel
+ Bouteville.
+
+ * Applications: apps/examples:
+
+ - apps/examples/alarm: Add a simple test of the ALARM iotcl calls of
+ the RTC driver.
+ - apps/examples/nximage: Add a configuration option to select
+ greyscale.
+
+ * Platforms: apps/platform:
+
+ - apps/platform/nucleo-144: Add platform files for NUCLEO-144
+ (NUCLEO-F746ZG). From Mark Olsson.
+ - apps/examples/media: You can now override the default device driver
+ path by providing an alternal path on the command line. From
+ Sbastien Lorquet.
+
+Works-In-Progress:
+
+ * IEEE802.14.5/6LowPAN. Hooks and framework for this effort were
+ introduced in NuttX-7.15. Work has continued on this effort on
+ forks from the main repositories, albeit with many interruptions.
+ The completion of this wireless feature will postponed until at
+ least NuttX-7.17.
+
+ * i.MX6 SMP. Partially functional, but there is more that still
+ needs to be done.
+
+Bugfixes. Only the most critical bugfixes are listed here (see the
+ChangeLog for the complete list of bugfixes and for additional, more
+detailed bugfix information):
+
+ * Core OS:
+
+ - Various places: Search for places where a stray semicolon following
+ an if condition cause the if body to be executed unconditionally.
+ Fixes in all SAM DMA logic, unionfs, OS signalling logic, and others.
+ - enter/leave_critical_section() may attempt to access task lists
+ before they have been initialized in the SMP configuration.
+
+ * File System/Block Drivers:
+
+ - SMART MTD: Return code of smart_scan not checked, can cause success
+ result in failure case, leading to 'dev' pointer being invalid. From
+ Dave (ziggurat29)
+ - mount: Fix a backward debug assertion. Noted by David Sidrane.
+
+ * Common Drivers:
+
+ - NRF24L01: Fix backward calculation of relative frequency. Noted by
+ Henry Zhang.
+ - PCA9555 I/O expander: Fix an error in the PCA9555 driver: Under
+ certain error conditions, interrupts were not being re-enabled.
+ Sebastien Lorquet.
+ - ADS1255: Must not do SPI access from interrupt handler. Use the
+ worker thread instead. Must also lock the SPI bus before using it.
+ - Several SPI-based drivers modified. All drivers that use SPI must
+ call SPI_LOCK and SPI_UNLOCK. This is not optional.
+ - MS583730: Fix a bug in crc computation for ms583730. Implement
+ POSIX read.
+
+ * Atmel SAMV7:
+
+ - Fix typo in MATRIX register definitions. From Stefan Kolb.
+ - SAMV7 Tickless Mode: This is a fix to a problem in the handling of
+ the oneshot timer. Due to a wrong assumption concerning the behavior
+ directly after the start of the timer/counter the function
+ sam_oneshot_cancel() calculates the wrong remaining time. The code
+ assumes that the counter register is zero directly after the start
+ of the timer, but this is not true. To start the time/counter a
+ software trigger is invoked, this trigger starts the timer/count and
+ sets the counter register to zero, but the reset of the counter
+ register is not performed instantly. According to the datasheet:
+ "The counter can be reset by a trigger. In this case, the counter
+ value passes to zero on the next valid edge of the selected clock."
+ Thus the counter is set to zero between 0 and USEC_PER_TICK
+ microseconds after the clock was started.
+ In my fix I use the freerun count value to determine if at least one
+ tick passed since the start of the timer and thus if the value of
+ the oneshot counter is correct. I also tried to use the function
+ up_timer_gettime() to achieve this but, at least if compiled with
+ no optimization the problem vanishes without using the value of the
+ function, the function call takes too long.
+ Another problem treated in the fix is that if the oneshot timer/counter
+ is canceled, we only know the remaining time with a precision of
+ USEC_PER_TICK microseconds. This means the calculated remaining time
+ is between 0 and USEC_PER_TICK microseconds too long. To fix this I
+ subtract one tick if the calculated remaining time is greater than
+ one tick and otherwise set the remaining time to zero. By doing so
+ the measured times are much more precise as without it. From Stefan
+ Kolb.
+
+ * Atmel SAMA5:
+
+ - SAMA5: Stefan Kolb's change to the SAMV7 Oneshot Timer should also
+ be applied to the SAMA5 oneshot time since the drivers are identical.
+
+ * Atmel SAM3/4:
+
+ - SAM3/4: Stefan Kolb's change to the SAMV7 Oneshot Timer should also
+ be applied to the SAM3/4 oneshot time since the drivers are identical.
+
+ * Atmel SAMV7 Drivers:
+
+ - SAMV7 TWIHS (as well as SAM3/4 and SAMA5: Ensure that the TWIHS
+ (i2c) hw get's its clock set when the sequence of
+ sam_i2cbus_initialize(), sam_i2cbus_uninitialize(), then
+ sam_i2cbus_initialize() or twi_reset() is called. I found this a
+ while back in the stm32 family, so there may be more arch-es with
+ this sort of bug. I suppose any driver that has the notion of "do
+ not set the freq if it is already set" could be suspect. From David
+ Sidrane.
+ - USBHS Device: Remove disabling of whole USB on suspend of USBHS.
+ This fix removes the disabling of the whole USB peripheral on
+ suspend interrupt. Its enough to freeze the clock instead. When
+ disabling the whole peripheral, the next wakeup-interrupt comes up
+ with an disabled clocking. The unfreeze clock has no effect, because
+ the master clock is disabled. This makes all registers, including
+ the IDR unwriteable and the IRQ falls in an endless loop blocking
+ the whole system. Furthermore the disabling of the peripheral clock
+ prevents hotplugging or reconnecting the USB. From Frank Benkert.
+ - MCAN: Fix missing unlock of device in MCAN mcan_txempty(). From
+ Frank Benkert.
+
+ * STMicro STM32:
+
+ - STM32 L4 Clocking: Problem with resetting backup domain clears
+ clocking options set up before in *rcc.c use INITS flag to avoid
+ magic reg value to detect power up reset state of RTC correct a
+ problem clearing interrupt flags (they weren't) which prevented an
+ alarm from ever being used more than once per reset cycle. From
+ Dave (ziggurat29)
+
+ * STMicro STM32 Drivers:
+
+ - STM32L4 SPI: That STM32Lr SPI driver is quite different. They now
+ handle frames of arbitrary size between 4 and 16 bits. It was broken
+ before a new bit has to be set (RX fifo threshold) to handle <= 8-bit
+ transactions. If not set, the default is 16-bit packed >=8-bit
+ frames and the RXNE bit is never set (it is set when 16-bits are
+ received). weird things as always. This also add 8-bit access
+ routines to the data register, because a 16-bit access to the data
+ register when the frame size is below 9 bits is interpreted as a
+ packed dual frame exchange. Sebastien Lorquet.
+ - STM32: Correct some bad commits that broke the LTDC display example.
+ From Marco Krahl.
+ - STM32 F4 RTC: Fix logic in F4 RTCC driver that prevent ALARM
+ interrupt. From Neil Hancock.
+ - STM32 F1 ADC: Fix STM32 ValueLine ADC IRQ number selection. From
+ David Sidrane.
+
+ * STMicro STM32 Boards:
+
+ - STM32F429I Discovery: Correct some bad commits that broke the LTDC
+ display example. From Marco Krahl.
+
+ * TI Tiva:
+
+ - GPIO Interrupts: Fix a bug of GPIO falling-edge interrupt for tiva.
+ From Young.
+
+ * C Library:
+
+ - math: Add a NAN test on 'x' in asin function of lib_asin.c. Suggested
+ by Pierre-noel Bouteville.
+
+ * Build/Configuration System:
+
+ - Several Makefiles: Add .PHONY definitions to prevent 'clean up to date'
+ message weirdness when 'make clean' is done with no .config or
+ Make.defs file.
+
+NuttX-7.17 Release Notes
+------------------------
+
+The 117th release of NuttX, Version 7.17, was made on July 25, 2016,
+and is available for download from the Bitbucket.org website. Note
+that release consists of two tarballs: nuttx-7.17.tar.gz and
+apps-7.17.tar.gz. These are available from:
+
+ https://bitbucket.org/nuttx/nuttx/downloads
+ https://bitbucket.org/nuttx/apps/downloads
+
+Both may be needed (see the top-level nuttx/README.txt file for build
+information).
+
+Additional new features and extended functionality:
+
+ * File System and Block and MTD Drivers:
+
+ - drivers/mtd: Add a driver of IS25xP SPI flash devices. Based on
+ sst25xx driver. From Marten Svanfeldt.
+
+ * Networking and Network Drivers:
+
+ - Break out internal interface psock_ioctl().
+
+ * Common Device Drivers:
+
+ - PTYs: Added support for pseduo-terminals: Device drivers that can be
+ used for communications between tasks (usually with re-directed I/O).
+ Based on existing pipe logic.
+ - Button upper half driver: Added support for poll().
+ - CAN: Add support for poll. From Paul Alexander Patience.
+ - GPIO: Add support for a simple GPIO driver. It supports only pre-
+ configured input, output, and interrupting pins with basic input and
+ output operations. Interrupt events can lead to notification via a
+ signal.
+ - I/O Expander: Shadow-Mode: The output- and configuration registers of
+ the IO-Expander are held in the microcontrollers memory and only
+ written to the IO-Expander. This reduces bus traffic and is more
+ error-proof than the normal read-modify-write operation. Retry Mode:
+ If enabled and an error occurs while writing to the IO-Expander the
+ current transmission is automatically repeated once. From Michael
+ Spahlinger.
+ - Pipes/FIFOs: Add support to allocating different sizes for pipe and
+ fifo buffers. Adds mkfifo2() and pipe2() which are just like mkfifo()
+ and pipe(), but allow control of the size of the underlying, in-memory
+ circular buffer. Move pipe() and mkpipe() to the C library, they are
+ no longer core OS interfaces. Capability currenty used only by PTY
+ logic to support, configurable, smaller buffers for PTYs.
+
+ * SYSLOG/Debug Output:
+
+ - SYSLOG: Consolidated all SYSLOG logic in drivers/syslog. Added an
+ abstraction layer that supports: (1) redirection of SYSLOG outpout.
+ This is usually so that you can boot with one SYSLOG output but
+ transition to another SYSLOG output when the OS has initialialized,
+ (2) adds common serialization of interrupt output as a configuration
+ option. Without this configuration setting, interrupt level output
+ will be asynchronous. And (3) vsyslog is now a system call and is
+ usable with other-than-FLAT builds.
+ - SYSLOG: syslog() will now automatically redirect output to
+ lowsyslog() if called from an interrupt handler.
+ - Extended SYSLOG logic so that we can send SYSLOG output to a file.
+ - SYSLOG character device channel will now expand LF to CR-LF.
+ Controllable with a configuration option.
+ - Add a SYSLOG character device that can be used to re-direct output
+ to the SYSLOG channel (Not be be confused the the SYSLGO output to a
+ character device).
+ - Debug features are now enabled separately from debug output.
+ (1) CONFIG_DEBUG is gone. It is replaced with CONFIG_DEBUG_FEATURES.
+ (2) The macros dbg() and vdbg() have renamed as _err() and _info(),
+ respectively. This also applies to all of the variants as well,
+ XXdbg() and XXvdbg(). (3) Add a new debug level, _warn() (and
+ all variants XXwarn(), XXvwarn(), etc.). (4) Debug assertions can
+ now be enabled separately from debug output. (5) You can now enable
+ subsystem/device driver debug output at different output levels. For
+ example, CONFIG_DEBUG_FS no longer enables file system debug output
+ It enables general file system debug logic and enables selection of
+ CONFIG_DEBUG_FS_ERROR, CONFIG_DEBUG_FS_WARN, and CONFIG_DEBUG_FS_INFO.
+ - Since the SYSLOG layer now automatically handles low-level vs.
+ high-level output, the low-level (ll) variants of the debug macros
+ were eliminated.
+ - Reviewed all uses of *err(). These macro family should indicate
+ only error conditions. Convert *err() to either *info() or add
+ ERROR:, depending on if an error is reported.
+ - _alert(): New debug macro: _alert(). This is high priority,
+ unconditional output and is used to simplify and standardize crash
+ error reporting.
+ - Many CONFIG_DEBUG_* options did not have matching macros defined in
+ include/debug.h. Rather, there were various definitions scattered
+ throughout the sourse tree. These were collected together and
+ centralized with single macro definitions in include/debug.h
+
+ * Simulation Platform:
+
+ - Added the simulated QSPI (N25Q) flash to the simulation and extened
+ flash simulation capabilities to run with MTD drivers based on config
+ options (currently m25p, sst26 and w25). From Ken Pettit.
+
+ * Atmel SAMV7 Drivers:
+
+ - SPI: SPI-Freq. 40MHz; VARSELECT; hw-features This change adds the
+ following improvements:
+
+ o Increase the allowed SPI-Frequency from 20 to 40 MHz.
+ o Correct and rename the "VARSELECT" option This option was
+ included in the code as "CONFIG_SPI_VARSELECT" but nowhere
+ defined in a Kconfig file. The change renames it to
+ "CONFIG_SAMV7_SPI_VARSELECT" and corrects the implementation
+ according the datasheet of Atmel. In short, this option
+ switches the processor from "fixed peripheral selection"
+ (single device) to "variable peripheral selection" (multiple
+ devices on the bus).
+ o Add a new Function to the interface to control the timing and
+ delays of the chip according the ChipSelect lines. This function
+ can control the delay between the assertion of the ChipSelect and
+ the first bit, between the last bit and the de-assertion of the
+ ChipSelect and between two ChipSelects. This is needed to tune
+ the transfer according the specification of the connected devices.
+ o Add three "hw-features" for the SAMV7, which controls the behavior
+ of the ChipSelect:
+ - force CS inactive after transfer: this forces a (short) de-
+ assertion of the CS after a transfer, even if more data is
+ available in time
+ - force CS active after transfer: this forces the CS to stay
+ active after a transfer, even if the chip runs out of data.
+ Btw.: this is a prerequisit to make the LASTXFER bit working
+ at all.
+ - escape LASTXFER: this suppresses the LASTXFER bit at the end
+ of the next transfer. The "escape"-Flag is reset automatically.
+
+ From Frank Benkert
+ - TWISHS: Driver improvements from Michael Spahlinger.
+ - GPIO-Driver fixed for Open-Drain Pins:
+
+ o sam_gpioread: Now the actual line level from the pin is read
+ back. This is extremely important for Open-Drain Pins, which
+ can be used bidirectionally
+ o Re-Implemented twi_reset-function and enhanced it so it can be
+ called from inside the driver (see next point)
+ o Glitch-Filter: Added a configuration option to enable the twi-
+ built-in glitch filter
+ o Added a "Single Master Mode": In EMC Testing the TWI-Bus got
+ stuck because the TWI-Master detected a Multi-Master access (but
+ there is no second master). With the option "Single Master" we
+ detect these events and automatically trigger a twi_reset. We
+ also do an automatic recovery if a slave got stuck (SDA stays
+ low).
+
+ With the above changes IC-Bus reliability in harsh environments (eg.
+ EMC) is greatly improved. The small change in the GPIO-Driver was
+ necessary because otherwise you cannot read back the correct line
+ status of Open-Drain Outputs and this is needed by the twi_reset
+ function. From Michael Spahlinger
+
+ * NXP Freescale LPC43xx Drivers:
+
+ - EMC: Extend LPC43xx EMC code to support SDRAM on a dynamic memory
+ interface. From Vytautas Lukenskas.
+
+ * NXP Freescale Kinetis:
+
+ - Kinetis K64: Add basic support for the K64 family. I leveraged the
+ changes from https://github.com/jmacintyre/nuttx-k64f and merged
+ into the existing kinetis code with a lot of changes and additions
+ (like pin multiplexing definitions).
+
+ * NXP Freescale Kinetis Drivers:
+
+ - Add a KinetisUSB device controller driver. Derived from the pic32mx
+ usb driver, which uses the same usb controller. From kfazz.
+ - Kinetis pwm support, based on the KL pwm driver. From kfazz.
+ - Kinetis Ethernet: Add support for the KSZ8081 PHY.
+ - Kinetis Ethernet: Modified Ethernet driver to try all PHY addresses
+ and then only fail if the driver cannot find a usable PHY address.
+ This means that you no longer have to specific the PHY address in
+ advance.
+ - Kinetis Ethernet: Add support for CONFIG_NET_NOINTS. The driver no
+ longer runs the networking at interrupt level but can defer interrupt
+ work to the high-priority work queue.
+
+ * NXP Freescale Kinetis Boards:
+
+ - Teensy-3.x: Add USB support and a usbnsh configuration.
+ From kfazz (2016-06).
+ - Freedom-K64F: Add support for the NXP Freedom-K64F board at 120MHz.
+ This is primarily the work of Jordan Macintyre. I leveraged this
+ code from https://github.com/jmacintyre/nuttx-k64f which was, itself,
+ a leverage from the old K60 TWR configuration. This includes
+ significant corrections (LEDs, buttons, README, etc) and extensions
+ and updates to match more recent BSPs.
+ - Freedom-K64F: Added a configuration that supports networking.
+
+ * STMicro STM32:
+
+ - STM32 F1-4: Added support for the STM32F105R. From Konstantin
+ Berezenko.
+ - STM32 F4: Added support for the STM32FF76xxx and STM32FF7xx
+ families. From David Sidrane.
+ - STM32 F1-4: Add support for Tickless mode (two timer
+ implementation). From Max Neklyudov.
+ - STM32 L4: Add support for tickless OS, and incidentally timers,
+ PWM, oneshot, free-running.... From ziggurat29.
+
+ * STMicro STM32 Drivers:
+
+ - STM32 F1-4: Add the up_getc() function to STM32 in order to support
+ the minnsh configuration. From Alan Carvalho de Assis.
+ - STM32 F7: Add SPI driver. From David Sidrane.
+ - STM32 F7: Add SPI, I2C, and ADC drivers. From Lok Tep.
+ - STM32 L4: Add ioctls to set/get CAN bit timing in stm32l4. Add
+ ioctl hooks to allow future management of can id filters. From
+ Sebastien Lorquet.
+ - STM32 L4: Add some CAN mode IOCTL calls. These will be useful for
+ device autotest when the application boots. They are redundant
+ with the CONFIG_CAN_LOOPBACK option, which can now just be
+ interpreted as a default setting. From Sebastien Lorquet.
+ - STM32 F1-4: Port STM32L4 CAN IOCTLs to STM32. From Sebastien Lorquet.
+ - STM32 L4: Implementation of loopback IOCTLs. From Sebastien
+ Lorquet.
+ - STM32 F7: Added SDMMC1 support for stm32F7 74-75. From Lok Tep.
+ - STM32 F7: Add USB support. From Lok Tep.
+ - STM32 F7: Added PWR, RTC, and BBSRAM support for stm32f7. From David
+ Sidrane.
+ - STM32 F7: Added STMF7xxx RTC. From David Sidrane.
+ - STM32 F7: Added STM32F7 DBGMCU. From David Sidrane.
+ - STM32 L4: Port support for both RX FIFOs from STM32 CAN. From Paul
+ Alexander Patience.
+
+ * STMicro STM32 Boards:
+
+ - Added a minnsh configuration for the STM32F103-Minimum board. From
+ Alan Carvalho de Assis .
+ - Added support for the Nucleo-F767ZI board. From David Sidrane.
+ - Nucleo-144/Nucleo-F767ZI: Add test for STM32 F7 SPI. From David
+ Sidrane.
+ - Nucleo-144: Added SDMMC support to Nucleo-144. From David Sidrane.
+ - Olimex STM32-E4077: Add support for Olimex STM32 E407 board. From
+ Mateusz Szafoni.
+ - Nucleo-144: Added USB OTG device to Nucleo-144. From David Sidrane.
+ - Nucleo-144: Added bbsram test to Nucleo-144. From David Sidrane.
+ - STM32F4 Disovery: add CAN support for STM32F4 Discovery. From
+ Matthias Renner.
+ - STM32F4 Disovery: added a canard configuration files. From
+ Matthias Renner.
+ - STM32F4 Discovery: Add FPU support for ostest for the STM32F4
+ Disovery platform. From David Alessio.
+ - STM32L476 Discovery: Update stm32l476 disco to include init code for
+ smartfs and nxffs for cases where those fs are included in build.
+ From ziggurat29.
+
+ * C Library/Header Files:
+
+ - include/assert.h: Check if NDEBUG is defined. From Paul Alexander
+ Patience.
+ - assert.h: Define static assert for C++ usage. From Paul Alexander
+ Patience.
+ - Add crc64 support. From Paul Alexander Patience.
+ - hex2bin: Move the portable library portion of apps/system/hex2bin
+ the C library with the OS internals. It is used in certain internal
+ boot-loader builds.
+ - Add raise().
+ - libm: This change should significantly improve the performance of
+ single precision floating point math library functions. The vast
+ majority of changes have to do with preventing the compiler from
+ needlessly promoting floats to doubles, performing the calculation
+ with doubles, only to demote the result to float. These changes only
+ affect the math lib functions that return float. From David Alessio.
+ - printf(): If there are no streams, let printf() fall back to use
+ syslog() for output.
+ - Move pipe() and mkpipe() to nuttx/libc, they are no
+ longer core OS interfaces. Capability currenty used only by PTY logi
+ to support, configurable, smaller buffers for PTYs.
+ - Move driver-related files from include/nuttx to include/nuttx/drivers.
+ Move driver related prototypes out of include/nuttx/fs/fs.h and into
+ new include/drivers/drivers.h.
+ - include /nuttx/lib: Move library-related files from include/nuttx to
+ include/nuttx/lib.
+
+ * Build/Configuration System:
+
+ - Custom Board Configuration: Add logic to support custom board
+ directories that include a Kconfig file. During the context phase
+ of the build, any Kconfig file in the custom board directory is
+ copied into configs/dummy, replacing the existing Kconfig file with
+ the target Kconfig file.
+ - Remove the includes/apps link to apps/include. It is no longer
+ used. From Sebastien Lorquet.
+
+ * Tools:
+
+ - tools/tesbuild.sh will now build NxWM configurations.
+
+ * Appplication Build/Configuration System:
+
+ - Change to the way that apps/ Kconfig files are generated in
+ order to better support reuse of the apps/ directory in NuttX
+ products. Changes include: Make the full tree use wildcards
+ make.defs, Add empty preconfig rules to 'leaf' makefiles, Use
+ directory.mk for recursive dir makefiles, Individual app kconfig
+ fixes, Recursive Kconfig autogeneration, Add kconfig files for
+ pcode and tiff, and fix a gitignore rule, From Sbastien Lorquet.
+ - apps/include directory structure reorganized. There are no longer
+ any header files in the apps/include/. directory. Rather, sub-
+ directories were added to match the partitioning of apps/ sub-
+ directories and the header files were moved into the appropriate
+ sub-directory. This change is intended to help with some changes
+ being considered by Sbastien Lorquet.
+ - Call all includes from to "bla/bla.h". From Sebastien
+ Lorquet.
+ - Add apps/include to include path in top-level Make.defs file.
+
+ * Applications: apps/nshlib:
+
+ - Make NSH net-initialization be a configuration option. From Marten
+ Svanfeld.
+ - Add NTP client initialization in NSH network startup logic. From
+ David S. Alessio .
+ - 'ps' command now prints out the stack usage if stack coloration is
+ enabled. From Frank Benkert.
+ - Allow stack usage to be disabled on constrained systems. From David
+ Sidrane.
+
+ * Applications: apps/netutils:
+
+ - NTP Client: Add retries. From David S. Alessio.
+ - NTP Client: The NTP client will now optionally use pool.ntp.org as
+ the NTP server; and reset the retry count upon success -- more robust.
+ From David Alessio.
+ - ESP8266: Add logic to set the BAUD rate. From Pierre-noel Bouteville.
+ - ESP8266: In Kconfig, select ARCH_HAVE_NET when NETUTILS_ESP8266 is
+ selected. This allows, among other things, support for network debug
+ output. From Pierre-noel Bouteville.
+
+ * Applications: apps/fsutils:
+
+ - flash_eraseall: IOCTL wrapper for MDCIO_BULKERASE command. Was in
+ nuttx/drivers/mtd. Moved to apps/fsutils because the call directly into
+ the OS was incorrect.
+
+ * Applications: apps/canutils:
+
+ - canlib: Basic CAN utility library. From Sebastien Lorquet.
+
+ * Platforms: apps/system:
+
+ - flash_eraseall: Now uses the IOCTL wrapper at apps/fsutils/flash_eraseall.
+
+ * Platforms: apps/platform:
+
+ - Add platform files for Olimex STM32 E407. From Mateusz Szafoni.
+
+ * Applications: apps/examples:
+
+ - apps/examples/canard: Add canard example application. From
+ Matthias Renner.
+ - apps/examples/pty_test: PTY test program. From Alan Carvalho de
+ Assis.
+
+Works-In-Progress:
+
+ * IEEE802.14.5/6LowPAN. Hooks and framework for this effort were
+ introduced in NuttX-7.15. Work has continued on this effort on
+ forks from the main repositories, albeit with many interruptions.
+ The completion of this wireless feature will postponed until at
+ least NuttX-7.18.
+
+ * i.MX6 SMP. Partially functional, but there is more that still
+ needs to be done.
+
+Bugfixes. Only the most critical bugfixes are listed here (see the
+ChangeLog for the complete list of bugfixes and for additional, more
+detailed bugfix information):
+
+ * Core OS:
+
+ - semaphores: Need to set errno to EINVAL on errors in sem_post()
+ and sem_wait(). From Paul Alexander Patience.
+
+ * File System/Block Drivers/MTD Drivers:
+
+ - Several MTD FLASH drivers nullify the freed 'priv' structure and
+ failed to return NULL as stated in the comments. Result, will
+ operate on a NULL pointer later. Noted by David Sidrane.
+ - VFS ioctl(). Per comments from David Sidrane, file_ioctl() should
+ not return succeed if the ioctl method is not supported. It
+ probably should return ENOTTY in that case.
+ - SST26 Driver: Before accessing the sst26 flash, the "Global Unlock"
+ command must me executed, which I do in the sst26 driver. BUT re-
+ reading the datasheet, the WREN instruction is required to enable
+ the execution of this command. This was not done. I have no idea how
+ the driver currently works except by chance. The writes should never
+ happen at all, the flash is half-enabled! From Sebastien Lorquet.
+ - N25Qxx Driver: Alter the notion of 'blocksize' to be equivalent to
+ 'flash write page size' in order to align with assumptions in the
+ smartfs driver (at least, maybe other things do as well). Correct a
+ bug that was previously masked by having blocksize=eraseblocksize
+ which would cause buffer overflows and delicious hardfaults.
+ Trivial spelling changes in comments, etc. From ziggurat29.
+ - SmartFS: Fix a 32-byte memory leak. From Ken Pettit.
+ - SMART MTD layer: Fixes freesector logic error when sectorsPerBlk=256,
+ adds DEBUGASSERT for invalid geometry and additional memory debug
+ logic. Also fixes the dangling pointer on error bug. From Ken
+ Pettit.
+
+ * Common Drivers:
+
+ - USB CDC/ACM Device Class: cdcacm_unbind leaks write request objects.
+ This arises due to freeing the bulk IN endpoint before the loop
+ that frees the requests via cdcasm_freereq. That function checks
+ the parameters and skips the freeing if either is NULL. Freeing
+ the bulk IN enpoint will cause the first param to be NULL, thereby
+ bypassing the free operation. To fix, I moved the release of the
+ bulk IN endpoint until after to loop (much as was the case for the
+ OUT and read requests, which did not exhibit the problem). From
+ ziggurat29.
+ - Pipes and FIFOs: Add missing configuration for pipe ring buffer
+ size. From Frank Benkert.
+ - UART 16550: Handle when CONFIG_SERIAL_UART_ARCH_IOCTL is not
+ enabled. From Heath Petersen.
+ - Common Serial Upper Half: Fix a race condition noted by Stefan
+ Kolb. Between the test if the TX buffer is full and entering a
+ critical section, bytes may be removed from the TX buffer making
+ the wait unnecessary. The unnecessary wait is an inefficiency,
+ but not really a problem. But with USB CDC/ACM it can be a problem
+ because the entire TX buffer may be emptied when we lose the race.
+ If that happens that uart_putxmitchar() can hang waiting for data
+ to be removed from an empty TX buffer.
+ - USB MSC Device Class: Add locks when removing request from queue.
+ From Wolfgang Reissnegger.
+ - USB MSC Device Class: Fix reversed logic on waiting for SCSI thread
+ start. The scsi thread was waiting for the wrong condition.
+ However, this was masked by the fact that the code creating the
+ scsi thread was also holding usbmsc_scsi_lock(priv) while
+ initializing data, hence this lock synchronized the scsi thread
+ start with init completion. From Wolfgang Reissnegger.
+
+ * Graphics and Graphic Drivers:
+
+ - Correct conditional compilation in ST7565 LCD driver. From Pierre-
+ noel Bouteville
+
+ * Networking:
+
+ - In both IPv6 and IPv4 incoming logic: (1) Should check if the
+ packet size is large enough before trying to access the packet
+ length in the IP header. (2) In the comparison between the IP
+ length and the full packet length, need to subtract the size of
+ he link layer header before making the comparison or we will get
+ false positives (i.e., the packet is really too small)
+ - TCP Networking: While working with version 7.10 I discovered a
+ problem in TCP stack that could be observed on high network load.
+ Generally speaking, the problem is that RST flag is set in
+ unnecessary case, in which between loss of some TCP packet and its
+ proper retransmission, another packets had been successfully sent.
+ The scenario is as follows: NuttX did not receive ACK for some sent
+ packet, so it has been probably lost somewhere. But before its
+ retransmission starts, NuttX is correctly issuing next TCP packets,
+ with sequence numbers increasing properly. When the retransmission
+ of previously lost packet finally succeeds, tcp_input receives the
+ accumulated ACK value, which acknowledges also the packets sent in
+ the meantime (i.e. between unsuccessful sending of lost packet and
+ its proper retransmission). However, variable unackseq is still set
+ to conn->isn + conn->sent, which is truth only if no further
+ packets transmission occurred in the meantime. Because of incorrect
+ (in such specific case) unackseq value, few lines further condition
+ if (ackseq <= unackseq)is not met, and, as a result, we are going to
+ reset label. From Jakub Lagwa.
+
+ * ARMv7-M:
+
+ - ARM stack check: Fix double fault on IDLE task with stack size = 0.
+ From David Sidrane.
+
+ * Atmel SAMV7 Drivers:
+
+ - CAN: CAN Message Filtering fixed: (1) stdfilters didn't work because
+ the filter was never enabled (wrong number of bits to shift), and
+ (2) Filters were never used because the configuration register
+ cannot be written without using the initialization mode. Both bugs
+ are fixed by this change. Filtering has been tested with both
+ standard and extended identifiers and is now working properly. From
+ Michael Spahlinger.
+
+ * Atmel SAMA5:
+
+
+ * Atmel SAM3/4 Drivers:
+
+ - Fix some errors in AFEC header file. From OrbitalFox.
+ - DAC: DACC_WPMR_WPKEY_MASK -> DACC_WPMR_WPKEY. From Wolfgang
+ Reissnegge.
+ - Timer: Fix ops check in TCIOC_STOP. From Wolfgang Reissnegge.
+ - I2C: Fix reversed logic in twi_startmessage(). From Wolfgang
+ Reissnegger.
+ - SAM3/4 UDP: Fix handling of endpoint RX FIFO banks. This fixes
+ a race condition where the HW fills a FIFO bank while the SW is
+ busy, resulting in out of sequence USB packets.
+
+ * Atmel SAMV7 Drivers:
+
+ - USBHS Device: This change solves a problem which causes data loss
+ while sending data via USB. This problem is caused by an incorrect
+ handling of the endpoint state in the USB driver sam_usbdevhs. This
+ leads under some circumstances to situations in which an DMA
+ transfer is setup while a previous DMA transfer is currently active.
+ Amongst other things I introduced the new endpoint state
+ USBHS_EPSTATE_SENDING_DMA for the fix. To reproduce the problem, I
+ used a program which send as many data as possible via a CDC/ACM
+ device and verified the received data on the PC. From Stefan Kolb.
+
+ * NXP Freescale Kinetis Drivers:
+
+ - Timers: Support up to 8 channels per timer. From kfazz.
+
+ * NXP Freescale Kinetis Boards:
+
+ - Teensy 3.x clock fixes: The High Gain bit in MCG_C1 was preventing
+ teensy from booting except after a programming session. The second
+ change doesn't appear to change any functionality, but complies with
+ restrictions in the k20 family reference manual on FEI -> FBE clock
+ transiions. From kfazz.
+
+ * NXP Freescale LPC17xx Drivers:
+
+ - LPC17 Ethernet: Needs to correctly ignore PHYID2 revision number
+ when comparing PHY IDs.
+
+ * NXP Freescale LPC43xx Drivers:
+
+ - Fix errors in GPIO interrupt logic. From v01d (phreakuencies)
+ - Ethernet: Correct auto-negotiation mode in the LPC43xx Ethernet.
+ From Alexander Vasiljev
+ - Writing zero to NVIC_IRQ_ENABLE has no effect. Disable interrupts
+ with NVIC_IRQ_CLEAR. From Paul Alexander Patience.
+ - SPIFI: If CONFIG_SPIFI_SECTOR512 undefined, lpc43_bwrite doesn't do
+ actual write (probably copy/paste errors). Still not sure about
+ current state of lpc43_spifi implementation, but for me NXFFS works
+ with this change. From Vytautas Lukenskas.
+
+ * Qemu-i486:
+
+ - Fix qemu-i486/ostest/Make.defs test for M32. From Heath Petersen.
+
+ * SiLabs EFM32 Drivers:
+
+ - Fix EFM32 FLASH conditional compilation. From Pierre-noel
+ Bouteville
+ - Writing zero to NVIC_IRQ_ENABLE has no effect. Disable interrupts
+ with NVIC_IRQ_CLEAR. From Paul Alexander Patience.
+
+ * STMicro STM32:
+
+ - STM32 F1-F4: In PWM driver, just update duty if frequency is not
+ changed and PSM started. This removeis glitch or blinking when
+ only duty is frequently changed. From Pierre-noel Bouteville.
+
+ * STMicro STM32 Drivers:
+
+ - STM32 F7: Fixed STM32F7 DMA stm32_dmacapable. DMA working on SDMMC.
+ From David Sidrane.
+ - STM32 F1-F4 Timer Driver: Change calculation of per- timer pre-scaler
+ value. Add support for all timers
+ - STM32 F1-F4: Correct conditional compilation in STM32 timer capture
+ logic. From Pierre-noel Bouteville
+ - STM32 F1-F4: Fix STM32 DMA code and configuration for STM32F37X chips.
+ From Marten Svanfeldt.
+ - STM32 F1-F4: Fix compilation errors in debug mode of stm32_pwm.c.
+ From Konstantin Berezenko.
+ - STM32 F1-F4: Correct the CAN2 RX IRQ number for stm32f10xx chips.
+ From Konstantin Berezenko.
+ - STM32 F1-F4: Move backup domain reset to to earlier in the
+ initialization sequence (stm32_rcc.c() in order to avoid disabling
+ LSE during RTC initialiation. From Alan Carvalho de Assis.
+ - STM32 F1-F4: When configuring a GPIO via stm32_configgpio() the
+ function will first set the mode to output and then set the initial
+ state of the gpio later on. If you have an application with an
+ externaly pulled-up pin, this would lead to a glitch on the line
+ that may be dangerous in some applications (e.G. Reset Line for
+ other chips, etc). This changes sets the output state before
+ configuring the pin as an output. From Pascal Speck .
+ - STM32 F7: Apply Pascal Speck's GPIO STM32 change to STM32 L4.
+ - STM32 L4: Apply Pascal Speck's GPIO STM32 change to STM32 L4.
+ From Sebastien Lorquet.
+ - STM32 F7: BUGFIX: PLLs IS2 and SAI P Calculation. From David
+ Sidrane.
+ - STM32 L4: STM32 CAN fixes need to be backported to STM32L4 as well.
+ - STM32 F1-F4 and L4: Writing zero to NVIC_IRQ_ENABLE has no effect.
+ Disable interrupts with NVIC_IRQ_CLEAR. From Paul Alexander
+ Patience.
+ - STM32 F7: STMF7xxx RTC: (1) Remove proxy #defines, (2) Ensure the
+ LSE(ON) etal are set and remembered in a) A cold start (RTC_MAGIC
+ invalid) of the RTC, and b) A warm start (RTC_MAGIC valid) of the
+ RTC but a clock change. The change was needed because in bench
+ testing a merge of the latest's STM32 53ec3ca (and friends) it
+ became apparent that the sequence of operation is wrong in the
+ reset of the Backup Domain in the RCC code. PWR is required before
+ the Backup Domain can be futzed with. !!!This Code should be tested
+ on STM32 and if needed rippled to the STM32 families. From David
+ Sidrane.
+ - STM32 F1-F4: STM32 BBSRAM fixed (and formatted) flags. From David
+ Sidrane.
+ - STM32 F7: STM32F7 BBSRAM fixed (and formatted) flags. From David
+ Sidrane.
+ - STM32 L4: Fix incorrect clock setup for LPTIM1. From ziggurat29.
+ - STM32 F4/L4 RTC ALARM: were enabling interrupts too early in the
+ power-up sequence, BEFORE the interrupt system was being
+ initialized.
+
+ * STMicro STM32 Boards:
+
+ - STM32 board.h: Fix STM32 timer input clock definitions. From David
+ Sidrane.
+
+ * TI Tiva Drivers:
+
+ - Bug Fix in tiva_serial.c - UART5, UART6 and UART7 were not being
+ configured as TTYS0 for printing over serial console. From Shirshak
+ Sengupta.
+
+ * C Library/Header Files:
+
+ - include/signal.h: Change type of SIG_ERR, SIG_IGN, ... to
+ _sa_handler_t. The type void does not work with the IAR toolchain.
+ From Aleksandr Vyhovanec.
+ - crc16: fix error. From Paul Alexander Patience.
+ - strtoul() and strtoull(): Fix errno settings required by function
+ definition. Resolved Bitbucket Issue #1. From Sebastien Lorquet.
+
+ * Build/Configuration System:
+
+ - Build system: This change fixes a build problem that only occurs
+ when reconfiguring from Linux to Windows or vice-versa. It is a
+ problem that was present but not usually experienced until two
+ things happened: (1) The pre_config target was added to run before
+ the menconfig operation and (2) the context target was added before
+ the pre_config target in order to set up the correct symbolic links
+ (in the apps/platform directory) needed by the pre_config target.
+ But then now if you start with a Linux system and run 'make
+ menuconfig' to switch to Linux, the context target will execute
+ first and set up POSIX style symbolic links before doing the
+ menuconfig. Then after the menuconfig, the make will fail on
+ Windows if you are using a Windows native toolchain because that
+ native toolchain cannot follow the Cygwin- style symbolic links.
+ The fix here is to also execute the clean_context AFTER executing
+ menuconfig. A lot more happens now: It used to be that doing
+ 'make menuconfig' only did the menuconfig operation. Now it does
+ context, pre_config, menuconfig, clean_context. Not nearly as
+ snappy as it used to be.
+ - Need to build the drivers/ directory even it file descriptors are
+ not supported. There are things in the drivers/ directory that are
+ still needed (like SYSLOG logic).
+ - Remove all inclusion of header files from the apps/include
+ directory from NuttX core logic. There should be no dependency on
+ logic within NuttX on logic within apps/. This caused a lot of
+ reshuffling of logic: binfmt pcode support, usbmonitor is now a
+ kernel thread, TZ/Olson database moved to libc/zoneinfo.
+
+ * Application Build/Configuration System:
+
+ - Make sure that APPNAME is defined in all Makefiles that generate
+ applications. From Sebastien Lorquet.
+
+ * apps/builtins:
+
+ - apps/builtins: exec_builtin was not using the provided open flags.
+ As a result >> redirection was not working; it was treated the same
+ as >.
+
+ * apps/nshlib:
+
+ - apps/nshilib: PS Command: When Priority Inheritance is enabled, the
+ format of /proc//status changes to show both the current
+ priority and the threads base priority. This messes up the format
+ of cmd_ps. From David Alessio.
+
+ * apps/netutils:
+
+ - apps/netutils, uIP webserver: Fix a data declaration in a header
+ file.
+
+ * apps/canutils:
+
+ - apps/canutils/libuavcan: Fix for recent change to STM32 timer
+ frequency definiitions.
+
+ * apps/examples:
+
+ - apps/examples/alarm: ioctl call was clobbering file descriptor.
+ - apps/examples/can: Some variables were not declared in all required
+ cases. From Sebastien Lorquet.
+ - apps/examples/media: media example was intended to take either a
+ command line argument, or a compiled-in default value from config.
+ However, the default was ignored, leading to confusing error
+ messages. From ziggurat29.
+
+NuttX-7.18 Release Notes
+------------------------
+
+The 118th release of NuttX, Version 7.18, was made on October 8, 2016,
+and is available for download from the Bitbucket.org website. Note
+that release consists of two tarballs: nuttx-7.18.tar.gz and
+apps-7.18.tar.gz. These are available from:
+
+ https://bitbucket.org/nuttx/nuttx/downloads
+ https://bitbucket.org/nuttx/apps/downloads
+
+Both may be needed (see the top-level nuttx/README.txt file for build
+information).
+
+Additional new features and extended functionality:
+
+ * Core OS:
+
+ - Add standard adjtime() interface and basic timekeeping support.
+ Normally used with an NTP client to keep system time in
+ synchronization. From Max Neklyudov.
+ - Use the oneshot timer with optional entropy to measure CPU load if
+ so configured.
+
+ * File System and Block and MTD Drivers:
+
+ - Add Fujistu MB85RS256B ramtron support. From Beat Kng.
+ - SPI-based MTD driver for Macronix MX25L3233F or MX25L6433F. From
+ Aleksandr Vyhovanec.
+
+ * Graphics/Display Drivers:
+
+ - SH1106 0.96 OLED module support (SSD1306 compatible) + I2C fixes.
+ From v01d (phreakuencies).
+
+ * Sensor Drivers:
+
+ - Add KXTJ9 Accelerometer driver from the Motorola Moto Z MDK.
+ - Add MFRC522 RFID ISO14443 and Mifare transceiver driver. From Alan
+ Carvalho de Assis.
+ - Add driver for the LIS3MDL 3 axis magnetometer. From Alexander
+ Entinger.
+ - Add driver for the MLX90393 3 axis magnetometer. From Alexander
+ Entinger.
+ - Add driver for the LIS3DSH 3 axis accelerometer. From Alexander
+ Entinger.
+ - Add driver for the Bosch BMG160 3 axis gyroscope. From Alexander
+ Entinger.
+ - Add support for the Sensixs XEN1210 3D-board. This sensor is used
+ on NANOSATC-BR2 a Brazillian CUBESAT project. From Alan Carvalho
+ de Assis.
+ - Add a new ioctl command (set MAXPOS) for Tiva QEI. From Young.
+
+ * Other Common Device Drivers:
+
+ - I/O Expander: Remove hard-coded PCA9555 fields from ioexpander.h
+ definitons. Add support for an attach() method that may be used
+ when any subset of pin interrupts occur.
+ - I/O Expander Interface: Encode and extend I/O expander options to
+ include interrupt configuration.
+ - PCA9555 Driver: Replace the signalling logic with a simple callback
+ using the new definitons of ioexpander.h. This repartitioning of
+ functionality is necessary because (1) the I/O expander driver is
+ the lower-lower part of any driver that uses GPIOs (include the GPIO
+ driver itself) and should not be interacting directly with the much
+ higher level application layer. And (2) in order to be compatible
+ with the GPIO driver (and any arbitrary upper half driver), the
+ PCA9555 should not directly signal, but should call back into the
+ upper half. The upper half driver that interacts directly with the
+ application is the appropriate place to be generating signal.
+ - Add a skeleton I/O Expander driver (based on the PCA9555 driver).
+ - Add PCF8574 I/O Expander driver.
+ - GPIO driver: Add IOCTLs to get the pin type and to unregister a
+ signal handler.
+ - Add a GPIO lower-half driver that can be used to register a GPIO
+ character driver for accessing pins on an I/O expander.
+ - Add an SPI helper function that encapsulates and manages a sequence
+ of SPI transfers.
+ - Add an SPI character driver that will permit access to the SPI bus
+ for testing purposes.
+ - Add oneshot timer lower half interface definition.
+ - Add an upper-half, oneshot timer character driver.
+ - Add Audio Tone Generator for NuttX. From Alan Carvalho de Assis.
+ - Add USB host support for composite devices. This feature is not
+ well tested.
+ - drivers/ioexpander: Add an (untested) TCA64XX I/O Expander driver
+ leveraged from Project Ara.
+
+ * Simulation Platform:
+
+ - Add a simulated I/O Expander driver.
+ - Add simulator-based test support for apps/examples/gpio.
+ - Add a configuration useful for testing Mini Basic.
+ - Add a simulated oneshot lowerhalf driver.
+
+ * Atmel SAM3/4 Drivers:
+
+ - SAM4CM: Add option to support oneshot timer without free-running
+ timer. Add oneshot lower half driver.
+
+ * Atmel SAMA5 Drivers:
+
+ - SAMA5D: Add option to support oneshot timer without free-running
+ timer. Add oneshot lower half driver.
+
+ * Atmel SAMV7 Drivers:
+
+ - SAMV71/SAME70: Add option to support oneshot timer without
+ free-running timer. Add oneshot lower half driver.
+ - Add support for SAMV7 DACC module. From Piotr Mienkowski.
+
+ * NXP Freescale Kinetis Drivers:
+
+ - Add support for I2C and RTC. From v01d (phreakuencies).
+
+ * NXP Freescale Kinetis Boards:
+
+ - Add teensy 3.x I2C support. From v01d (phreakuencies).
+
+ * STMicro STM32:
+
+ - Add IAR-style STM32F1xx vectors. Tested on STM32F103RB and
+ STM32F107RC. From Aleksandr Vyhovanec.
+
+ * STMicro STM32 Drivers:
+
+ - Add timekeeping support for the STM32 tickless mode. From Max
+ Neklyudov.
+ - Add a oneshot, lower-half driver for STM32.
+ - STM32 L4: Add oneshot lower half driver for STM32 L4.
+ - STM32 L4: Add support for quadrature encoders on STM32L4. Sebastien
+ Lorquet.
+
+ * STMicro STM32 Boards:
+
+ - stm32f103-minimum: Add board support to MFRC522 driver. From Alan
+ Carvalho de Assis.
+ - Add oneshot board initialization to stm32f103-minimum. From Alan
+ Carvalho de Assis.
+ - stm32f103-minimum: Add board configuration to initialize Audio Tone
+ Generator. From Alan Carvalho de Assis.
+ - stm32bufferfly2: Add support for the Kamami stm32butterfly2
+ development board with optional ETH phy. From Michal Lyszczek.
+ - stm32f103-minimum: Add board config support to SPI LCD module
+ JLX12864G-086. From Alan Carvalho de Assis.
+ - stm32l476-mdk: Support basic booting and nsh on Motorola MDK. The
+ Motorola MDK is based off of an earlier version of NuttX.
+ This only provides a basic NSH shell. From Jim Wylder.
+ - STM32 F4 Discovery: Add support for XEN1210 3D-board. From Alan
+ Carvalho de Assis.
+ - stm32f103-minimum: Add stm32_bringup support and userled example to
+ STM32F103 Minimum board. From Alan Carvalho de Assis.
+ - Add support for qencoders on various nucleo boards. From Sebastien
+ Lorquet.
+ - olimex-stm32-e407: Add some networking configurations. From Mateusz
+ Szafoni.
+
+ * TI Tiva Drivers:
+
+ - Add tiva PWM lower-half driver implementation. From Young.
+ - Tiva QEI: Add QEI lower-half driver for Tiva series chip. From
+ Young.
+
+ * C Library/Header Files:
+
+ - Separate XorShift128 PRNG from /dev/urandom and make it generally
+ available.
+ - Add POSIX type sig_atomic_t. From Sebastien Lorquet.
+ - Add the difftime() function. The function depends on the toolchain-
+ dependent CONFIG_HAVE_DOUBLE so is not available on tiny platforms.
+ From Sebastien Lorquet.
+ - Add support for remove(). From Sebastien Lorquet.
+ - Add system() to stdlib.h. Actual implementation is in
+ apps/system/system.
+
+ * Build/Configuration System:
+
+ - Rename arch/sh to arch/renesas.
+ - Remove contactless drivers from drivers/wireless to drivers
+ contactless. From Sebastien Lorquet.
+ - Move all modem-related IOCTL commands to a common file to assure
+ that they will be unique.
+
+ * Tools:
+
+ - Add sethost.sh. This is a script that you can use to quickly
+ change the host platform from Linux to Windows/Cygwin. Might save
+ you a lot of headaches.
+
+ * Applications: apps/nshlib:
+
+ - Add logic to support an NSH-specific system command.
+ - Add printf command to NSH, e.g., controlling /dev/userleds from
+ command line: nsh> printf \x01 > /dev/userleds. From Alan Carvalho
+ de Assis.
+
+ * Platforms: apps/system:
+
+ - Port tee command from NetBSD.
+ - Add a generic system command. Current implentation cannot use
+ /bin/sh and spawns the custom NSH system command directly.
+
+ * Platforms: apps/platform:
+
+ - Add C++ support for STM32L476-MDK.
+
+ * Platforms: apps/interpreters:
+
+ - Add a port of Mini Basic, version 1.0, written by Malcom McLean and
+ released under the Creative Commons Attribution license.
+
+ * Applications: apps/examples:
+
+ - Add a simple test of the GPIO driver.
+ - Add RFID_READUID sample application. From Alan Carvalho de Assis.
+ - Add Oneshot timer example.
+ - Add a simple test of the system command.
+
+Works-In-Progress:
+
+ * IEEE802.14.5/6LowPAN. Hooks and framework for this effort were
+ introduced in NuttX-7.15. Work has continued on this effort on
+ forks from the main repositories, albeit with many interruptions.
+ The completion of this wireless feature will postponed until at
+ least NuttX-7.19.
+
+Bugfixes. Only the most critical bugfixes are listed here (see the
+ChangeLog for the complete list of bugfixes and for additional, more
+detailed bugfix information):
+
+ * Core OS:
+
+ - Explicitly initialize the group tg_exitsem with sem_init(). The
+ existing logic worked because the correct initialization value is
+ all zero, but it is better to initialize the semaphore explicitly.
+ - The TCB nchildren field should not be incremented when pthreads are
+ created.
+ - Move fields related to parent/child task relationship out of TCB
+ into group structure where they belong. Child is a group, not a
+ thread.
+ - mq_send() was not setting the errno value on certain failures to
+ allocate a message.
+ - Define 'group' even if HAVE_GROUPID is not set. From Mateusz
+ Szafoni.
+ - Vector table should have dimension NR_IRQS, not NR_IRQS+1. From
+ Sagitta Li.
+ - pthreads: When a pthread is started, there is a small bit
+ of logic that will run on the thread of execution of the new
+ pthread. In the case where the new pthread has a lower
+ priority than the parent thread, then this could cause both the
+ parent thread and the new pthread to be blocked at the priority of
+ the lower priority pthread (assuming that CONFIG_PRIORITY_INHERITANCE
+ is not selected). This change temporarily boosts the priority of the
+ new pthread to at least the priority of the new pthread to at least
+ the priority of the parent thread. When that bit of logic has
+ executed on the thread of execution of the new pthread, it will then
+ drop to the correct priority (if necessary) before calling into the
+ new pthread's entry point.
+
+ * File System/Block Drivers/MTD Drivers:
+
+ - FAT performance improvement. In large files, seeking to a
+ position from the beginning of the file can be very time consuming.
+ ftell does lssek(fd, 0, SET_CURR). In that case, that is wasted
+ time since we are going to seek to the same position. This fix
+ short-circuits fat_seek() in all cases where we attempt to seek to
+ current position. Suggested by Nate Weibley.
+ - MTD: Fixed cloned typos in several FLASH drivers. From Aleksandr
+ Vyhovanec.
+ - mount: Corrects a bad assertion noted by Pierre-noel Bouteville.
+ Also fixes a reference counting problem in an error condition:
+ When the mountpoint inode is found but is not an appropriate
+ mountpoint, the reference count on the inode was not being
+ decremented.
+
+ * Common Drivers:
+
+ - Various serial drivers: Fix FIONWRITE and add FIONSPACE. All
+ implementations of FIONWRITE were wrong. FIONWRITE should return
+ the number of bytes waiting in the outgoing send queue, not the free
+ space. Rather, FIONSPACE should return the free space in the send
+ queue.
+ - Add missing prototype for btn_lower_initialize().
+ - Make DAC sample structure packed. From Marc Recht.
+
+ * Networking:
+
+ - TCP: tcp_ipvX_bind() not actually using the port selected with
+ port==0. Also removes duplicate call to pkt_input(). Issues noted
+ by Pascal Speck.
+ - drivers/net: NET_TUN=y => NET_MULTIBUFFER=y. From Vladimir
+ Komendantskiy.
+ - slip driver: Fix calculations using MSEC_PER_TICK. If
+ USEC_PER_TICK is less than 1000, then MSEC_PER_TICK will be
+ zero. It will be inaccurate in any case.
+
+ * Atmel SAM3/4 Drivers:
+
+ - SAM3/4 GPIO: Enable peripheral clock for GPIO port when GPIO is
+ configured as input. The value of a GPIO input is only sampled when
+ the peripheral clock for the port controller the GPIO resides in is
+ enabled. Therefore we need to enable the clock even when polling a
+ GPIO. From Wolfgang Reissnegger.
+ - All SAM Ethernet Drivers: Add support so that the drivers can be
+ built with CONFIG_NET_MULTIBUFFER=y.
+ - SAM3/4: Fix GPIO pull-up/down code. Enabling the pull-down resistor
+ while the pull-up resistor is still enabled is not possible. In this
+ case, the write of PIO_PPDER for the relevant I/O line is discarded.
+ Likewise, enabling the pull-up resistor while the pull-down resistor
+ is still enabled is not possible. In this case, the write of
+ PIO_PUER for the relevant I/O line is discarded. From Wolfgang
+ Reinegger.
+
+ * Atmel SAMV7 Drivers:
+
+ - All SAM Ethernet Drivers: Add support so that the drivers can be
+ built with CONFIG_NET_MULTIBUFFER=y.
+ - SAM GPIO: Apply Wolfgang's change for SAM3/4 to SAMA5 and SAMV7.
+
+ * Atmel SAMA5:
+
+ - Add missing oneshot max_delay method.
+ - All SAM Ethernet Drivers: Add support so that the drivers can be
+ built with CONFIG_NET_MULTIBUFFER=y.
+ - SAM GPIO: Apply Wolfgang's change for SAM3/4 to SAMA5 and SAMV7.
+
+ * NXP Freescale LPC43xx Drivers:
+
+ - LPC43xx serial: Fix typos in LPC43 serial driver. Found by Vytautas
+ Lukenskas.
+ - LPC43xx Serial: There are some small problems in LPC43xx RS485 mode
+ configuration. In particular: (1) UART0,2,3 do not have DTR pins
+ (different from UART1), so, Kconfig needs to be adjusted. (2)
+ lpc43_uart.c in RS485 mode only configures DIR pin, but doesn't
+ enable pin output for UART0,2,3. (3) should be option to reverse DIR
+ control pin output polarity. (4) lpc43xx/chip/lpc43_uart.h doesn't
+ have USART3 definitions. NOTE: I didn't modified and didn't tested
+ USART1, as it has different hardware. From Vytautas Lukenskas.
+ From Vytautas Lukenskas.
+
+ * SiLabs EFM32 Drivers:
+
+ - EFM32 SPI drivers adopted incompatible conventions (See STM32 for
+ details of the issue).
+
+ * STMicro STM32 Drivers:
+
+ - STM32, STM32 L4, and EFM32 SPI drivers adopted incompatible
+ conventions somewhere along the line. They set the number of bits
+ to negative when calling SPI_SETBITS which had the magical side-
+ effect of setting LSB first order of bit transmission. This is not
+ only a hokey way to pass control information but is supported by no
+ other SPI drivers. This change three things: (1) It adds
+ HWFEAT_LSBFIRST as a new H/W feature. (2) It changes the
+ implementations of SPI_SETBITS in the STM32 and EFM32 drivers so
+ that negated bit numbers are simply errors and it adds the
+ SPI_HWFEATURES method that can set the LSB bit order, and
+ (3) It changes all calls with negative number of bits from all
+ drivers: The number of bits is now always positive and
+ SPI_HWFEATURES is called with HWFEAT_LSBFIRST to set the bit order.
+ - Add missing SPI2 and SPI3 support for STM32F3F3. Add STM32F37XX DMA
+ channel configuration. For STM32F37XX, SYSCFG_EXTICR_PORTE defined
+ twice. From Alan Carvalho de Assis.
+ - STM32: Make stm32_pwr_enablebkp thread safe. From Max Neklyudov.
+ - Fix bad pllmul values for STM32F1XX connectivity line. STM32F1XX
+ connectivity line supports only x4, x5, x6, x7, x8, x9 and x6.5
+ values. From Michal Lyszczek.
+ - STM32F3 SPI: Fix the number of bit setting for the F3. That and
+ data packing work differently on the STM32F3 than for other STM32
+ parts.
+ - STM32 and STM32 L4: Enabling SPI DMA loses other bits in CR2.
+ - STM32F3 SPI: Cannot write always 16-bit value to DR register
+ because of how the F3 implements data packing.
+ - STM32F411 and STM32F446 map i2c2_sda_4 to different alternate
+ function numbers. From Konstantin Berezenko.
+ - STM32 DMA Fix: Change stm32 adc dma callback to send channel
+ number instead of index. From Konstantin Berezenko.
+ - STM32 OTGFS device: Fix for lost first word from FIFO
+
+ 1) Do not overwrite Reserved Bits in GINTSTS (per ref manual)*
+ 2) Acknowledge all pending int on entry to ISR that are Only rc_w1*
+ 3) Do not disable RXFVL*
+ 4) Loop until RXFVL is cleared*
+ 5) Only clear the NAK on the endpoint on the OTGFS_GRXSTSD_PKTSTS_SETUPDONE to not loose the first WORD of FIFO all the data (Bug Fix)
+
+ Changed marked *are just driver clean up and ensure ints are not lost. The bug fix is #5
+
+ Test case open putty and observer the Set/Get LineCoding. Without this fix #5 the Get will not match the Set, and in fact the data might be skewed by 4 bytes, that are lost from the FIFO if the OTGFS_DOEPCTL0_CNAK bit is set in the OTGFS_GRXSTSD_PKTSTS_SETUPRECVD as opposed to the OTGFS_GRXSTSD_PKTSTS_SETUPDONE
+
+ Set Line Coding DATA1: 4B | 00 c2 01 00 00 00 08 | c8 1B
+ Get Line Coding DATA1: 4B | .. .. .. .. 00 00 08 c8 .. 00 00 07 | 7a 72
+
+ From David Sidrane.
+ - STM32 L4 OTGFS device: Apply stm32 fix to stm32l4. From Sebastien
+ Lorquet.
+ - STM32 F7: Remove duplicate call to pkt_input from Ethernet driver.
+ Issues noted by Pascal Speck.
+ - STM32 L4: Add support for USART3-USART5. For STM32L4 parts, the
+ higher number USART ports supported varies. Add the HAVE_USARTx
+ definitions to the configuration to allow enabling the higher
+ numbered USART ports. From Jim Wylder.
+ - STM32 USB: Set USB address to avoid a failed assertion. From
+ Pierre-noel Bouteville.
+ - STM32 L4 and L7 USB: Pierre's assertion-avoidance change should
+ also be applied to STM32 F7 and L4.
+ - STM32, L4, and F7: Remove GPIO_ETH_RMII_TX_CLK. TX_CLK is not
+ present in RMII. Mateusz Szafoni.
+ - STM32 Ethernet: Correct typo in conditional logic. From Neil
+ Hancock.
+ - STM32 L4 USB Device: Fixed L4 USB Driver by avoiding SETUPDONE and
+ EPOUT_SETUP. From David Sidrane.
+ - STM32 SPI: stm32_modifycr2 should be available on all platforms if
+ DMA is enabled.
+ - STM32 DMA2D: fix an error in up_dma2dcreatelayer where an invalid
+ pointer was returned when a certain underlying function failed.
+ From Jens Grf.
+
+ * TI Tiva Drivers:
+
+ - Fix two bugs of tiva pwm lower-half driver implementation. From
+ Young.
+ - Tiva Ethernet: Needs support for CONFIG_NET_MULTIBUFFER=y.
+
+ * C Library/Header Files:
+
+ - lib_dumpbuffer() now prints a large on-stack buffer first to avoid
+ problems when the syslog output is prefixed with time. From
+ Pierre-noel Bouteville.
+ - libc/math: This fixes the following libc/math issues: (1) asin[f l]()
+ use Newtons method to converge on a solution. But Newtons method
+ converges very slowly (> 500,000 iterations) for values of x close to
+ 1.0; and, in the case of asinl(), sometimes fails to converge (loops
+ forever). The attached patch uses an trig identity for values of
+ x > sqrt(2). The resultant functions converge in no more than 5
+ iterations, 6 for asinl(). (2) The NuttX erf[f l]() functions are
+ based on Chebyshev fitting to a good guess. The problem theres a
+ bug in the implementation that causes the functions to blow up with
+ x near -3.0. This patch fixes that problem. It should be noted that
+ this method returns the error function erf(x) with fractional error
+ less than 1.2E-07 and thats fine for the float version erff(), but
+ the same method is used for double and long double version which
+ will yield only slightly better precision. This patch doesn't
+ address the issue of lower precision for erf() and erfl(). (3) a
+ faster version of copysignf() for floats is included. From David S.
+ Alessio.
+ - strtod() was not returning endptr on error conditions.
+ - libc/math: floor(), floorf(), and floorl(): Fix logic error. Was
+ not correctly handling negative integral value.
+ - isatty() should be prototyped in unstid.h, not termios.h. From
+ Sebastien Lorquet.
+ - nxglib: Fix handling of near-horizontal lines of width 1 in
+ nxgl_splitline(). Missing handling for degenerate condition caused
+ width 1 lines such as (0, 0) - (100, 10) to have gaps in the
+ drawing. From Petteri Aimonen.
+
+ * Build/Configuration System:
+
+ - Top-Level Makefiles: Fix a chicken-and-egg problem. In the menuconfig
+ target, the context dependency was executed before kconfig-mconf. That
+ was necessary because the link at apps/platform/board needed to be set
+ up before creating the apps/Kconfig file. Otherwise, the platform
+ Kconfig files would not be included. But this introduces the chicken-
+ and-egg problem in some configurations. In particular: (1) An NX
+ graphics configuration is used that requires auto-generation of
+ source files using cpp, (2) the configuration is set for Linux, but
+ (3) we are running under Cygwin with (4) a Windows native toolchain.
+ In this case, POSIX-style symbolic links are set up but the Windows
+ native toolchain cannot follow them. The reason we are running
+ 'make menuconfig' is to change from Linux to Cygwin, but the target
+ fails. During the context phase, NX runs CPP to generate source files
+ but that fails because the Windows native toolchain cannot follow
+ the links. Checkmate. This was fixed by changing all of the make
+ menuconfig (and related) targets. They no longer depend on context
+ being run. Instead, they depend only on the dirlinks target. The
+ dirlinks target only sets up the directory links but does not try
+ to run all of the context setup; the compiler is never invoked; no
+ code is autogenerated and things work.
+ - CXXFLAGS: add -fcheck-new whenever -fno-exceptions is used. From
+ Beat Kng.
+
+ * Tools
+
+ - tools/refresh.sh: Recent complexities added to apps/ means that
+ configuration needs the correct Make.defs file in place in order to
+ configure properly.
+ - tools/kconfig2html.c: Update to handle absolute paths when sourcing
+ Kconfig files.
+ - tools/mkfsdata.pl was still generating the old-style apps/include
+ inclusion paths.
+
+ * Application Build/Configuration System:
+
+ - Add DIRLINK and DIRUNLINK tool definitions to apps/Make.defs.
+
+ * apps/nshlib:
+
+ - Fix FIFO_SIZE vs PIPE_SIZE.
+ - Fix hex representation of IP address in Kconfig. Noted by Michal
+ Lyszczek.
+ - nsh_syscmds.c: missing semicolon. From Mateusz Szafoni.
+ - In system command, don't try to flush output streams if stdio
+ buffered I/O is not supported.
+
+ * apps/canutils:
+
+ - libuavcan: Under certain circumstances, DELIM is not be defined in
+ Makefile.
+ - Add definition for APPNAME in apps/canutils/canlib. From Sebastien
+ Lorquet.
+
+ * apps/gpsutils:
+
+ - Fix an error minmea. From Aleksandr Vyhovanec.
+
+ * apps/examples:
+
+ - apps/examples/oneshot: If the requested delay is > max_delay, then
+ break the delay up into several pieces.
+
+NuttX-7.19 Release Notes
+------------------------
+
+The 119th release of NuttX, Version 7.19, was made on December 26, 2016,
+and is available for download from the Bitbucket.org website. Note
+that release consists of two tarballs: nuttx-7.19.tar.gz and
+apps-7.19.tar.gz. These are available from:
+
+ https://bitbucket.org/nuttx/nuttx/downloads
+ https://bitbucket.org/nuttx/apps/downloads
+
+Both may be needed (see the top-level nuttx/README.txt file for build
+information).
+
+Additional new features and extended functionality:
+
+ * Core OS:
+
+ - sched/semaphore, sched/phread/, libc/semaphore, libc/pthread: Add
+ pthread_mutexattr_get/set_protocol and non-standard
+ sem_get/set_protocol. These may use to enable or disable priority
+ inheritance on a single semaphore.
+ - Spinlocks: Added capability to provide architecture-specific memory
+ barriers.
+ - SMP: Add spin_trylock(). Use this in conditions where other CPUs need
+ to stopped but we cannot call enter_critical_section().
+ - sched note: Extend OS instrumentation to include some SMP events.
+ Also add spinlock instrumentation; In SMP configurations, add a
+ filter mask to log only notes from certain CPUs.
+ - sched note: Permit spinlock and critical section notes in in-memory
+ buffer iff sched_not_get() interfaces is disabled.
+ - sched note: Add additional note to see if/when CPU is started in SMP
+ mode.
+ - sched note: Record ID enumeration now results on constant values; ID
+ values do not change with configuration. This makes writing post-processing software much easier.
+ - boardctl: Add new boardctl() command, BOARDIOC_NX_START, to start the
+ NX server as a kernel thread.
+ - pthreads: Add pthread_cleanup_push() and pthread_cleanup_pop().
+ - pthreads: Added pthread_setcanceltype() and pthread_testcancel().
+ - pthreads: Add support for cancellation points.
+ - task_delete() now obeys all cancellation point semantics.
+ - Add task_setcancelstate(), task_setcanceltype(), and
+ task_testcancel(). These are non-standard interfaces analogous to the
+ correponding pthread_ interfaces that provide cancellation controls
+ for tasks.
+
+ * Graphics/Display Drivers:
+
+ - boardctl: Add new boardctl() command, BOARDIOC_NX_START, to start the
+ NX server as a kernel thread.
+
+ * Networking/Network Drivers:
+
+ - Network drivers: Add option to use low-priority work queue to all
+ Ethernet and MAC level drivers.
+ - Network Drivers: Adapt all Ethernet (and other MAC) drivers to work
+ as though CONFIG_NET_MULTIBUFFER were set. Remove all references to
+ CONFIG_NET_MULTIBUFFER.
+ - Eliminate CONFIG_NO_NOINTS. There is no longer any support for
+ interrupt level processing of the network stack. Lots of files changed.
+
+ * Other Common Device Drivers:
+
+ - Vishay VEML6070: Add Vishay VEML6070 driver. From Alan Carvalho de
+ Assis.
+
+ * ARMv7-A
+
+ - ARMv7-A/i.MX6: Add SCU register definitions. Add some controls to
+ enable SMP cache coherency in SMP mode. Makes no difference, however
+ -- cache still incoherent on i.MX6.
+ - ARMv7 GIC: SGIs are non-maskable but go through the same path as
+ other, maskable interrupts. Added logic to serialize SGI processing
+ when necessary.
+
+ * Atmel SAM3/4:
+
+ - SAM3/4: Add SMP support for the dual-core SAM4CM. From Masayuki
+ Ishikawa.
+
+ * Atmel SAM3/4 Drivers:
+
+ - Add support for the SAM5CMP-DB board. From Masayuki Ishikawa.
+
+ * Atmel SAM3/4 Boards:
+
+ - SAM4CMP-DB: Add support for the Atmel SAM4CMP-DB board running in an
+ SMP configuration. From Masayuki Ishikawa.
+ - SAM4CMP-DB: Add hooks to auto-mount the procfs file system on startup
+ in board bring-up logic.
+
+ * Atmel SAMV7 Drivers:
+
+ - SAMv7: Register the watchdog device at the configured device path
+ CONFIG_WATCHDOG_DEVPATH vs. hard-coded /dev/wdt. From Frank Benkert.
+
+ * Calypso
+
+ - Calyps: Remove all Calypso board configurations. Remove Calypso
+ architecture support and support for Calypso SERCOMM driver.
+
+ * Misoc LM32:
+
+ - Misoc LM32: Adds basic support for the Misoc procoessors and the LM32
+ in particular. From Ramtin Amin.
+ - Misoc LM32: Add signal handling logic. From Ramtin Amin.
+ - Misoc LM32: Add logic to flush/invalidate caches. From Ramtin Amin.
+
+ * Misoc LM32 Drivers:
+
+ - Misoc LM32 Serial: Add interrupting Misoc serial driver. From Ramtin
+ Amin.
+ - Misoc LM32 Timer: Add timer driver. From Ramtin Amin.
+ - Misoc LM32: Add Misoc Ethernet driver From Ramtin Amin.
+
+ * Misoc LM32 Boards:
+
+ - Misoc LM32 Qemu: Board support for testing Misoc LM32 with Qemu. From
+ Ramtin Amin.
+ - Misoc LM32 Qemu: Integrate network support into configs/misoc/hello.
+ From Ramtin Amin.
+ - Misoc LM32 Qemu: Remove configs/misoc/include/generated directory. I
+ suppose the the intent now is that this is a symbolic link? DANGER!
+ This means that you cannot compile this code with first generating
+ these files a providing a symbolic link to this location! There is a
+ sample directory containing generated sources. This is really only
+ useful for performing test builds. You really must generate the Misoc
+ architecture for a real-life build. From Ramtin Amin.
+
+ * NXP Freescale i.MX6 Drivers:
+
+ - i.MX6: Add an untested SPI driver taken directly from the i.MX1 port.
+
+ * NXP Freescale Kinetis:
+
+ - Kinetis: Added missing headers. Kinetis broke out SPI to
+ kinetis/kinetis_spi.h. Broke out DMA to use the modern Nuttx chip
+ inclusion - still STUBS. Add Kinetis support for ARMV7-M Common
+ Vector and FPU. Allow CONFIG_ARMV7M_CMNVECTOR,
+ CONFIG_STACK_COLORATION, CONFIG_ARCH_FPU. Fix i2c driver offset
+ swapped for value in kinetis_i2c_putreg. From David Sidrane.
+
+ * NXP Freescale Kinetis Drivers:
+
+ - Kinetis: Add UID Unique ID. From Neil Hancock.
+
+ * NXP Freescale Kinetis Boards:
+
+ - Freedom-K64F board: Add support for UID Unique ID. From Neil Hancock.
+
+ * NXP Freescale LPC17xx Boards:
+
+ - Olimex-LPC1766-STK: Enable procfs in NSH configuration. Automount
+ /proc on startup.
+
+ * NXP Freescale LPC43xx Drivers:
+
+ - LPC43xx: Add timer driver: From Alan Carvalho de Assis.
+ - LPC43xx GPDMA driver: The GPDMA block is basically the same as the
+ LPC17xx. Only the clock configuration is different and LPC43xx has
+ four different DMA request sources, where LPC17xx has only two. From
+ Alan Carvalho de Assis.
+
+ * NXP Freescale LPC43xx Boards:
+
+ - Bambino 200E: Add basic support to Micromint Bambino 200E board.
+ This includes contributions from Jim Wolfman. From Alan Carvalho de
+ Assis.
+ - Bambino 200E: Add support for timer driver. From Alan Carvalho de
+ Assis.
+
+ * RGMP:
+
+ - Remove RGMP and RGMP drivers.
+
+ * RISC-V:
+
+ - RISC-V: Add support for the RISC-V architecture and
+ configs/nr5m100-nexys4 board. The board support on this is pretty
+ thin, but it seems like maybe a good idea to get the base RISC-V stuff
+ in since there are people interested in it. From Ken Pettit.
+
+ * STMicro STM32 Drivers:
+
+ - STM32 F3: Implemention of the STM32 F37xx SDADC module. There are
+ also changes to ADC, DAC modules. SDADC has only been tested in DMA
+ mode and does not support external TIMER triggers. This is a work in
+ progress. From Marc Recht.
+ - STM32 F3: Add PWM driver support for STMF37xx. The changes have been
+ tested successfuly for TIM4 and TIM17 (different IPs). From Marc
+ Recht.
+ - STM32 F4: Support oversampling by 8 for the STM32 F4. From David
+ Sidrane.
+ - STM32 F4: Added Timers 2-5 and control of SAI and I2S PLLs. Added
+ support for stmf469 SAI and I2S PLL configuration and STM446 fixes.
+ From David Sidrane.
+ - STM32 F4: Expanded OTGFS support to stm32F469 and stm32f446. Added
+ missing bit definitions, Used stm32F469 and stm32f446 bit
+ definitions, Removed unsed header file. From David Sidrane.
+ - STM32 F4: Allow dma in 1 bit mode in STM32F4xxx. From David Sidrane.
+ - STM32 F7: Allow the config to override the clock edge setting. From
+ David Sidrane.
+ - STM32 L4: Support Complementary PWM outputs on STM32L4. From
+ Sebastien Lorquet.
+ - STM32 L4: Add implementation of dumpgpio for stm32l4, was required
+ for pwm debug. From Sebastien Lorquet.
+
+ * STMicro STM32 Boards:
+
+ - STM32F103 Minimum: Add button support. From Alan Carvalho de Assis.
+ - STM32F103 Minimum: Add support to PWM on STM32F103-Minimum board.
+ From Alan Carvalho de Assis.
+ - STM32F103 Minimum: Add RGB LED support on STM32F103 Minimum board.
+ From Alan Carvalho de Assis.
+ - STM32F103 Minimum: Add Vishay VEML6070 driver support to the
+ STM32F103-Minimum board. From Alan Carvalho de Assis.
+ - Nucleo-F303RE: Add STM32 F303RE hello configuration. From Marc
+ Recht.
+ - Nucleo-L476: Support PWM testing on board Nucleo L476. From
+ Sebastien Lorquet.
+ - Nucleo L476: Add support for timers to Nucleo L476. From Sebastien
+ Lorquet.
+ - Hymini STM32v: Enable CONFIG_RTC in the hymini-stm32v/nsh2
+ (kitchensink) config. From Maciej Wjcik.
+ - Olimex STM32-p407: Add support for the Olimex STM32 P407 board.
+
+ * TI Tiva Drivers:
+
+ - Tiva PWM: Support PWM_PULSECOUNT feature for TI tiva. From Young.Mu.
+
+ * Xtensa/ESP32
+
+ - Xtensa ESP32: Basic architectural support for Xtensa processors and
+ the Expressif. ESP32 added.
+ - Xtensa ESP32: Add EXPERIMENTAL hooks to support lazy Xtensa
+ co-processor state restore in the future.
+ - Xtensa ESP32: Basic port is function in both single CPU and dual CPU
+ SMP configurations. There is an NSH configuration for each CPU
+ configuration. Outstanding issues include missing clock configuration
+ logic, missing partition tables to support correct configuration from
+ FLASH, and some serial driver pin configuration issues.
+ - Xtensa ESP32: Add stack checking logic.
+
+ * Xtensa/ESP32 Boards:
+
+ - ESP32 Core v2: Basic support for Expressif ESP32 Core v2 board
+ added. The initial release includes an NSH and an SMP test
+ configuration.
+ - ESP32 Core v2: Add configuration to support linking NuttX for
+ execution out of IRAM.
+ - ESP32 Core v2: Automatically mount /proc at start-up.
+ - ESP32 Core v2: Add an OS test to verify the port.
+
+ * C Library/Header Files:
+
+ - libc/locale: Add a dummy setlocale() function to avoid drawing the
+ function from newlib. Add clocale header file.
+ - include/locale.h: Modify locale.h to add localeconv() and lconv
+ structure. From Alan Carvalho de Assis.
+ - libc/locale: Allows c++ code to compile with or without
+ CONFIG_LIBC_LOCALE and will generate a link error if
+ CONFIG_LIBC_LOCALE is not defined and setlocale is referenced. With
+ CONFIG_LIBC_LOCALE defined setlocale will act as if MB string is not
+ supported and return "C" for POSIX. C and "". From David Sidrane.
+ - libc/wchar: Add wcslen, wmemchr, wmemcmp, wmemcpy wmemset, btowc,
+ mbrtowc, mbtowc, wcscmp, wcscoll, and wmemmove to NuttX. From Alan
+ Carvalho de Assis.
+ - libc/wctype: Add functions wcrtomb, wcslcpy, wcsxfrm, wctob, wctomb,
+ wctype, localeconv, strcoll, strxfrm, swctype, towlower, towupper and
+ wcsftime. Add wctype.h; Move lib_wctype.c to libc/wctype. From Alan
+ Carvalho de Assis.
+ - include/ctype.h : Add isblank() macro to ctype.h. From Alan Carvalho
+ de Assis.
+ - lic/stdlib: Add strtof() and strtold() as simply a copy of strtod
+ with types and limits changed.
+ - sscanf(): Use strtof() instead of strtod() if a short floating point
+ value was requested. The should help performance with MCUs with
+ 32-bit FPU support with some additional code size.
+ - sscanf(): Add scansets to the scanf function. Enabled
+ CONFIG_LIBC_SCANSET option. From Aleksandr Vyhovanec.
+ - include/inttypes.h: Add architecture-specific inttypes.h. From Paul
+ A. Patience.
+ - C Library: Allow option to enable IP address conversions even when
+ the IP address family is not supported.
+
+ * Build/Configuration System:
+
+ - The Smoothie project needs to compile C++ inside config/boardname/src/
+ to use with High Priority Interruption, then I modified the board
+ configs Makefile to support it. It works fine for the first time
+ compilation, but if we execute "touch config/boardname/src/Pin.cxx"
+ and execute "make" it will not detect that Pin.cxx was modified. I
+ think there is some other place I should modify, but I didn't find
+ it. From Alan Carvalho de Assis.
+
+ * Tools:
+
+ - tools/: Add tools/showsize.sh.
+
+ * NSH: apps/nshlib:
+
+ - NSH: dd command will show statistics. From Masayuki Ishikawa.
+
+ * Applications: apps/system:
+
+ - apps/system/sched_note: Extend to include additions to instumentation
+ for SMP.
+ - apps/system/sched_note: Add support for spinlock notes.
+ - apps/system/sched_note: Add support for new scheduler instrumentation.
+
+ * Platforms: apps/platform:
+
+ - ESP32 Core v2: Add platform support for the ESP32 core v2 board.
+ - Olimex STM32-p407: Add platform support for the Olimex STM32 P407.
+
+ * Graphics: apps/graphics
+
+ - graphics/traveler/tcledit and libwld: Add an X11 Tcl/Tk tool that can
+ be used to edit Traveler world files.
+ - Graphics: Remove all NX server taks. Instead, call boardctl() to the
+ NX server kernel thread.
+
+ * Applications: apps/examples:
+
+ - examples/buttons: Add a new buttons example that uses the button
+ character driver instead of the architecture buttons directly. From
+ Alan Carvalho de Assis.
+ - examples/cctype: Add an example to verify cctype functions.
+ - Remove RGMP example.
+ - examples/ostest: Extend the pthread cancellation test to exercise
+ pthread_cleanup_push() (and pthread_cleanup_pop() indirectly via
+ pthread_cancel() and pthread_exit().
+ - examples/ostest: enhance pthread cancellation test some.
+
+Works-In-Progress:
+
+ * IEEE802.14.5/6LowPAN. Hooks and framework for this effort were
+ introduced in NuttX-7.15. Work has continued on this effort on
+ forks from the main repositories, albeit with many interruptions.
+ The completion of this wireless feature will postponed until at
+ least NuttX-7.20.
+
+Bugfixes. Only the most critical bugfixes are listed here (see the
+ChangeLog for the complete list of bugfixes and for additional, more
+detailed bugfix information):
+
+ * Core OS:
+
+ - sched/semaphore: Within the OS, when a thread obtains a semaphore
+ count it must call sem_addholder() if CONFIG_PRIORITY_INHERITANCE is
+ enabled. If a count is available, then sem_wait() calls
+ sem_addholder(), otherwise it waited for the semaphore and called
+ sem_addholder() when it eventually received the count. This caused a
+ problem when the thread calling sem_wait() was very low priority.
+ When it received the count, there may be higher priority threads
+ "hogging" the CPU that prevent the lower priority task from running
+ and, as a result, the sem_addholder() may be delayed indefinitely.
+ The fix was to have sem_post() call sem_addholder() just before
+ restarting the thread waiting for the semaphore count. This problem
+ was noted by Benix Vincent who also suggested the solution.
+ - Many files: Make sure that priority inheritance is not enabled for
+ semaphores whose primary use is signaling (vs locking of resources) by
+ calling sem_setprotocol().
+ - sched/semaphore: sem_trywait() no longer modifies the errno value
+ UNLESS an error occurs. This allows these functions to be used
+ internally without clobbering the errno value. From Freddie Chopin.
+ - sched/clock: Correct clock initialization. The correct range for the
+ month is 0-11 but is entered as 1-12 in the .config file. Add ranges
+ to START_YEAR, MONTH, and DAY in sched/Kconfig.
+ - sched/clock: Correct calculation for the case of Tickless mode with a
+ 32-bit timer. In that case, the calculation was returning millisecond
+ accuracy. That is not good when the timer accuracy is < 1 msec. From
+ Rajan Gill.
+ - Work Queue: When queuing new LP work, don't signal any threads if
+ they are all busy. From Heesub Shin.
+ - Work Queue: Signal sent from work_signal() may interrupt the low
+ priority worker thread that is already running. For example, the
+ worker thread that is waiting for a semaphore could be woken up by the
+ signal and break any synchronization assumption as a result. It also
+ does not make any sense to send signal if it is already running and
+ busy. This change fixes it. From Heesub Shin.
+ - Fix DEBUGASSERT() in group_signal.c. From Masayuki Ishikawa.
+ - Eliminate bad boardctl() commands: Remove all references to
+ BOARDIOC_PWMSETUP and board_pwm_setup(). Remove all references to
+ BOARDIOC_ADCSETUP and board_adc_setup(). Remove
+ BOARDIOC_CAN_INITIALIZE. CAN initialization is now done in the board
+ initialization logic just like every other device driver.
+ - pthreads: Fix an error in pthread_mutex_destroy(). An error could
+ occur while destroying a mutex after a pthread has been canceled while
+ holding the mutex.
+ - task_restart: Make sure new task starts with pre-emption disabled and
+ not in a critical section.
+ - Enter/leave Critical Sections. Major redeign to
+ enter/leave_critical_section logic to deal with the case where
+ interrupts are disabled only on the local CPU. In this case, some
+ rather complex spinlocks must be used to maintain the critical section
+ accross all CPUs.
+ - SMP Critical Sections: Fixes for the SMP case: (1) Change order for
+ SMP case in enter_critical_section: (1) Disable local interrupts
+ BEFORE taking spinlock and (2) If SMP is enabled, if any interrupt
+ handler calls enter_critical_section(), it should take the spinlock.
+ - SMP wdogs: Wdog timers use a tasking interface that to manipulate
+ wdogs, and a different interface in the timer interrupt handling logic
+ to manage wdog expirations. In the single CPU case, this is fine.
+ Since the tasking level code calls enter_critical_section, interrupts
+ are disabled and no conflicts can occur. But that may not be the case
+ in the SMP case. Most architectures do not permit disabling
+ interrupts on other CPUs so enter_critical_section must work
+ differently: Locks are required to protect code. this change adds
+ locking (via enter_critical section) to wdog expiration logic for the
+ the case if the SMP configuration.
+ - SMP vfork(): Fix a race condition in the SMP case. Existing logic
+ depended on the fact that the child would not run until waitpid was
+ called because the child had the same priority as the parent. BUT in
+ the SMP case that is not true... the child may run immediately on a
+ different CPU.
+ - SMP: This change adds a new internal interfaces and fixes a problem
+ with three APIs in the SMP configuration. The new internal interface
+ is sched_cpu_pause(tcb). This function will pause a CPU if the task
+ associated with 'tcb' is running on that CPU. This allows a different
+ CPU to modify that OS data stuctures associated with the CPU. When
+ the other CPU is resumed, those modifications can safely take place.
+ The three fixes are to handle cases in the SMP configuration where one
+ CPU does need to make modifications to TCB and data structures on a
+ task that could be running running on another CPU. Those three cases
+ are task_delete(), task_restart(), and execution of signal handlers.
+ In all three cases the solutions is basically the same: (1) Call
+ sched_cpu_pause(tcb) to pause the CPU on which the task is running,
+ (2) perform the necessary operations, then (3) call up_cpu_resume() to
+ restart the paused CPU.
+ - SMP: Add logic to avoid a deadlock condition when CPU1 is hung waiting
+ for g_cpu_irqlock with interrupts interrupts and CPU0 is waiting for
+ g_cpu_paused.
+ - SMP: Enforce this rule: Tasks which are normally restored when
+ sched_unlock() is called must remain pending (1) if we are in a
+ critical section, i.e., g_cpu_irqlock is locked , or (2) other CPUs
+ still have pre-emption disabled, i.e., g_cpu_schedlock is locked. In
+ those cases, the release of the pending tasks must be deferred until
+ those conditions are met.
+
+ * File System/Block Drivers/MTD Drivers:
+
+ - AT24XX EEPROM MTD driver: Added EEPROM timeout. Fromo Aleksandr
+ Vyhovanec.
+ - fs/procfs: Fix procfs status for SMP case.
+
+ * Graphics/Graphic Drivers:
+
+ - Fonts: Correct some default font IDs. From Pierre-Noel Bouteville.
+
+ * Common Drivers:
+
+ - usbhost/enumerate: Fix possible buffer overwrite. From Janne Rosberg.
+ - usbhost/composite: Fix compile; missing semicolons. From Jann Rosberg.
+ - syslog: Fixes required for file syslog output. From Max Kriegleder.
+ - SPI configuration: Fix Kconfig warning. This change moves the
+ ARCH_HAVE_SPI options outside the check for SPI. Those options don't
+ depend on SPI, and Kconfig files in arch/ enable them even if SPI
+ isn't enabled. Source the driver's Kconfig in drivers/Kconfig only
+ if support for the driver is enabled prevents us from defining these
+ ARCH_HAVE options in the driver's Kconfig. We should probably remove
+ the other checks in drivers/Kconfig and check if the drivers are
+ enabled only in their Kconfig. From Paul A. Patience.
+ - drivers/timer: Remove the timer driver TIOC_SETHANDLER IOCTL call.
+ This calls directly from the timer driver into application code. That
+ is non-standard, non-portable, and cannot be supported. Instead, add
+ timer driver hooks to support signal notification of timer
+ expiration. Signal notification logic added by Sebastien Lorquet.
+ - All timer lower half drivers. Port Sebastien's changes to all other
+ implementations of the timer lower half.
+ - USB MSC Device: Fix length of mode6 sense reply packet. From
+ Wolfgang Reinegger.
+ - USB Composite Host: Fix end offset in usbhost_copyinterface(). From
+ Janne Rosberg.
+ - USB CDC/ACM Host: Add CDC_SUBCLASS_ACM and CDC_PROTO_ATM to
+ supported class and proto. From Janne Rosberg.
+ - SSD1306: Fix errors in SPI mode configuration. From Gong Darcy.
+ - CDC/ACM Device Class: uart_ops_s portion of cdcacm will not be
+ initalized with correct functions if CONFIG_SERIAL_DMA is selected.
+
+ * Networking/Network Drivers:
+
+ - drivers/net/tun.c: Fix bug in TUN interface driver. From Max Nekludov.
+
+ * ARMv7-A:
+
+ - ARMv7-A SMP: Add SMP logic to signal handling.
+
+ * ARMv7-M:
+
+ - ARMv7-M: Fix double allocation of MPU region in mmu.h.
+
+ * ARMv7-R:
+
+ - ARMv7-R: Fix compilation error. This change fixes compilation errors
+ on MPU support for ARMv7-R. From Heesub Shin.
+ - ARMv7-R: fix invalid drbar handling. In ARMv7-R, [31:5] bits of DRBAR
+ is physical base address and other bits are reserved and SBZ. Thus,
+ there is no point in passing other than the base address. From Heesub
+ Shin.
+ - ARMv7-R: Remove the redundant update on SCTLR. mpu_control() is
+ invoking cp15_wrsctlr() around SCTLR update redundantly. From Heesub
+ Shin.
+ - ARMv7-R: add new Kconfig entries for d/i-cache. Unlike in ARMv7-A/M,
+ Kconfig entries for data and instruction caches are currently missing
+ in ARMv7-R. This change adds those missing Kconfig entries. Actual
+ implmenetation for those functions will be added in the subsequent
+ patches. From Heesub Shin.
+ - ARMv7-R: Add cache handling functions. This change adds functions for
+ enabling and disabling d/i-caches which were missing for ARMv7-R.
+ From Heesub Shin.
+ - ARMv7-R: Fix typo in mpu support. s/ARMV7M/ARMV7R/g. From Heesub Shin.
+ - ARMv7-R: Fix CPSR corruption after exception handling. A sporadic
+ hang with consequent crash was observed when booting. It seemed to be
+ caused by the corrupted or wrong CPSR restored on return from
+ exception. NuttX restores the context using code like this: msr spsr,
+ r1. GCC translates this to: msr spsr_fc, r1. As a result, not all
+ SPSR fields are updated on exception return. This should be: msr
+ spsr_fsxc, r1. On some evaluation boards, spsr_svc may have totally
+ invalid value at power-on-reset. As it is not initialized at boot, the
+ code above may result in the corruption of cpsr and thus unexpected
+ behavior. From Heesub Shin.
+ - ARMv7-R: Fix to restore the Thumb flag in CPSR. Thumb flag in CPSR is
+ not restored back when the context switch occurs while executing thumb
+ instruction. From Heesub Shin.
+
+ * Atmel SAM3/4 Drivers:
+
+ - SAM3/4 UDP: Add delay between setting and clearing the endpoint RESET
+ bit in sam_ep_resume(). We need to add a delay between setting and
+ clearing the endpoint reset bit in SAM_UDP_RSTEP. Without the delay
+ the USB controller will (may?) not reset the endpoint. If the
+ endpoint is not being reset, the Data Toggle (DTGLE) bit will not to
+ be cleared which will cause the next transaction to fail if DTGLE is
+ 1. If that happens the host will time-out and reset the bus. Adding
+ this delay may also fix the USBMSC_STALL_RACEWAR in usbmsc_scsi.c,
+ however this has not been verified yet. From Wolfgang Reinegger.
+ - SAM3/4: Remove unused 'halted' flag from UDP driver. From Wolfgang
+ Reinegger.
+ - SAM3/4: Remove 'stalled' flag from the UDP driver. This flag is not
+ necessary because the state of the endpoint can be determined using
+ 'epstate' instead. From Wolfgang Reinegger.
+
+ * Atmel SAM3/4 Boards:
+
+ - SAM4S Xplained Pro: Configuration uses old, improper timer interface.
+ CONFIG_TIMER disabled in configuration. Remove obsolete timer
+ initialization logic.
+
+ * Atmel SAMV7 Drivers:
+
+ - SAMv7 USBDEVHS: A problem occurred with the SAMV7 USBDEVHS driver if
+ the USB cable is unplugged while a large amount of data is send over
+ an IN endpoint using DMA. If the USB cable is plugged in again after a
+ few seconds it is not possible to send data over this IN endpoint
+ again, all other endpoints work as expected. The problem occurs
+ because if the USB cable is unplugged while an DMA transfer is in
+ flight the transfer is canceled but the register SAM_USBHS_DEVDMACTRL
+ is left in an undefined state. The problem was fixed the problem by
+ resetting the register SAM_USBHS_DEVDMACTRL to a known state.
+ Additionally all pending interrupts are cleared. From Stefan Kolb.
+ - SAMV7 MCAN: Prevent Interrupt-Flooding of ACKE when not connected to
+ CAN-BUS. An Acknowledge-Error will occur every time no other CAN Node
+ acknowledges the message sent. This will also occur if the device is
+ not connected to the can-bus. The CAN-Standard declares, that the Chip
+ has to retry a given message as long as it is not sent successfully
+ (or it is not cancelled by the application). Every time the chip tries
+ to resend the message an Acknowledge-Error-Interrupt is generated. At
+ high baud rates this can lead in extremely high CPU load just for
+ handling the interrupts (and possibly the error handling in the
+ application). To prevent this Interrupt-Flooding we disable the ACKE
+ once it is seen as long we didn't transfer at least one message
+ successfully. From Frank Benkert.
+ - SAMV7 MCAN: Make delete_filter functions more robust. From Frank
+ Benkert.
+
+ * Atmel SAMA5 Drivers:
+
+ - SAMA5 PWM: Driver does not build when executing from SDRAM before
+ board frequencies are not constant. Rather, the bootloader configures
+ the clocking and we must derive the clocking from the MCK left by the
+ bootloader. This means lots more computations. This is untested on
+ initial change because I don't have a good PWM test setup right now.
+
+ * Misoc LM32:
+
+ - Misoc LM32: Corrects a bug that never occured in qemu on simulation or
+ real fpga. The error was that the r1 register was being modified out
+ of context switching and not restoring it. From Ramtin Amin
+
+ * NXP Freescale i.MX6:
+
+ - i.MX6 interrupt handling: Additional logic needed to handle nested
+ interrupts when an interrupt stack is used. Nesting can occur because
+ SGI interrupts are non-maskable.
+
+ * NXP Freescale LPC43xx Drivers:
+
+ - LPC43xx serial: Fix a typo in ioctl TIOCSRS485 ioctl. From Vytautas
+ Lukenskas.
+ - LPC43xx serial: Restore RS485 mode on serial port open (if RS485 is
+ enabled via menuconfig). From Vytautas Lukenskas.
+ - LPC43xx SD/MMC: Correct some definitions on SMMC control register in
+ lpc43_sdmmc.h. From Alan Carvalho de Assis.
+ - LPC43xx SD card: Correct pin configuration options needed for SD card
+ pins. From Alan Carvalho de Assis.
+
+ * SiLabs EFM32:
+
+ - EFM32: Fix a compilation error. From Pierre-noel Bouteville.
+
+ * STMicro STM32 Drivers:
+
+ - STM32 CHxN channels are always outputs. From Sebastien Lorquet.
+ - STM32 DAC: Fix shift value whenever there are is a DAC2 and, hence,
+ up to three interfaces. From Marc Recht.
+ - STM32 F1: Add TIM8 to STM32F103V pinmap. From Maciej Wjcik.
+ - STM32 F1: Fix for F1 RTC Clock, tested on F103. From Maciej Wjcik.
+ - STM32 F3: STM32F303xB and STM32F303xC chips have 4 ADCs. From Paul
+ A. Patience.
+ - STM32 F4: A new implementation of the STM32 F4 I2C bottom half. The
+ common I2C as this did not handled correctly in the current
+ implementation (see also https://github.com/PX4/NuttX/issues/54). The
+ changes almost exclusively affect the ISR. From Max Kriegleder.
+ - STM32 F4 OTGHS Host: If STM32F446 increase number of channels to
+ 16. From Janne Rosberg.
+ - STM32 F4: I think, that Size is (highest address+1 - Base address).
+ Base address has been removed and if address+count >= size we are
+ outside of the Flash. From David Sidrane.
+ - STM32 F4: Fix ADC compilation error when DMA isn't enabled. From Paul
+ A. Patience.
+ - STM32 F4: STM32F427 was rebooting. Over reached family. From David
+ Sidrane.
+ - STM32 F4: Added STM32F469 RAM size and deliberated STM32F446 size.
+ From David Sidrane.
+ - STM32 F4: Typo in stm32f76xxxx_pinmap.h edited online with
+ Bitbucket. From David Sidrane.
+ - STM32 F7: stm32_i2c.c Dejavu. Fixes a bug previously found in the
+ F4. From David Sidrane.
+ - STM32 F7: OTGDEV fixed typo. From David Sidrane.
+ - STM32 F7: Fix to SPI-Master driver. Without this the chip select
+ decoding feature will not work properly. From Michael Spahlinger.
+ - STM32 F7: STM32F7 SD/MMC driver depends on CONFIG_SDIO_DMA which is
+ only defined in stm32/Kconfig. Changed to CONFIG_STM32F7_SDMMC_DMA
+ and defined in stm32f7/Kconfig.
+ - STM32 F7: Fix some STM32F7 copy paste errors. From David Sidrane.
+ - STM32 L4: Complementary PWM outputs on STM32L4" (1) too many
+ parentheses when calculating max chan count and (2) channel 4 does not
+ have a complementary output. From Sebastien Lorquet.
+ - STM32 L4: Fix I2C devices RCC registers. From Sebastien Lorquet.
+ - STM32 L4: Enable and renaming for 32l4 UARTs 4 and 5. From Sebastien
+ Lorquet.
+ - STM32 L4: Change the way to configure quadrature encoder prescalers.
+ From Sebastien Lorquet.
+ - STM32 L4: Correct USART1/2 definitions. Use default mbed UART4
+ settings. From Sebastien Lorquet.
+
+ * STMicro STM32 Boards:
+
+ - STM32F103 Minimum: Fix Timers 2 to 7 clock frequencies. From Alan
+ Carvalho de Assis.
+ - Nucleo-F303RE: Remove duplicate setting from board.h. From Marc
+ Recht.
+ - Nucleo F303RE: Various fixes to get the ADC configuration building
+ again after PR. Refresh all configurations.
+ - Nucleo L476RG: Add better selection of timer.
+
+ * TI Tiva Boards:
+
+ - DK-TM4C129x: Typo fix. From Wolfgang Reinegger.
+
+ * Xtensa ESP32:
+
+ - ESP32 core v2: Flush the UART TX buffer in the esp32 serial shutdown
+ routine. The ROM bootloader does not flush the FIFO before handing
+ over to user code, so some of this output is not currently seen when
+ the UART is reconfigured in early stages of startup. From Angus
+ Gratton.
+ - Xtensa ESP32: Corrects a problem with dispatching to signal
+ handlers: Cannot vector directly to the signal handling function as
+ in other ABIs under the Xtensa Window ABI. In that case, we need to
+ go through a tiny hook when performs the correct window call (call4)
+ otherwise registers will be scrambled in the signal handler.
+
+ * Xtensa ESP32 Boards:
+
+ - ESP32 core v2: Changes the openocd config file's default flash
+ voltage from 1.8V to 3.3V. This is not necessary right now, but may
+ save some hard-to-debug moments down the track (3.3V-only flash
+ running at 1.8V often half-works and does weird things...). From
+ Angus Gratton.
+
+ * C Library/Header Files:
+
+ - libc/stdio: Fixes sscanf() %sn where strlen(data) < n. From David
+ Sidrane.
+ - libc/stdio: Include wchar.h in lib_libvsprintf.c to fix compilation
+ error. From Alan Carvalho de Assis.
+ - include/sys/time.h: timersub macro modified per recommendations of
+ phreakuencies.
+ - include/ctype.h and cxx/cctype: Implement ctype.h functions as inline
+ if possible. cctype can then properly select namespace.
+ - include/: Fix a number of header files with mismatched 'extern C {'
+ and '}'.
+ - libc/unisted: Change brings strtol() and related functions more
+ conformant with POSIX. Corner cases like strtol(-2147483648, NULL,
+ 10) now pass clang -fsanitize=integer without warnings. From Juha
+ Niskanen.
+ - libc/unistd: sleep() was returning remaining nanoseconds (kind of),
+ instead the remaining seconds. From Eunbong Song.
+ - termios.h: Fix CRTSCTS define to include input and output flow. From
+ Lorenz Meier.
+
+ * Build/Configuration System:
+
+ - configs/*/defconfig: The buttons example was changed to archbuttons.
+ As a result all of the button configurations are broken and need some
+ renaming in the defconfig files. Noted by Frank Berkert.
+ - config/*/defconfgs: More fallout from name change of
+ apps/examples/buttons to archbuttons.
+ - configs: All QE encoder files. Last change made timer hard-coded to
+ 3. Make configurable.
+ - configs: Remove all traces of the no-longer existent ARCHBUTTONS
+ example. Remove all button configurations that depended on the
+ obsoleted ARCHBUTTON example.
+ - minnsh Configurations: Remove minnsh configurations and support
+ logic: up_getc() and lowinstream. This was an interesting exercise
+ to see just how small you could get NuttX, but otherwise it was not
+ useful: (1) the NSH code violated the OS interface layer by callup
+ up_getc() and up_putc() directly, and (2) while waiting for character
+ input, NSH would call up_getc() which would hog all of the CPU. Not a
+ reasonable solution other than as a proof of concept.
+
+ * Application Build/Configuration System:
+
+ - Make.defs: Using wrong link script if native window tool used with
+ Cygwin.
+
+ * apps/platform:
+
+ - ESP32 Core v2 Platform: Fix some naming that prevented building the
+ C++ support.
+
+ * apps/nshlib:
+
+ - NSH Library: nsh_getdirpath(), use snprint instead of sprintf to
+ avoid possibility of buffer overrun. Noted by Chung Hwan Kim.
+
+ * apps/system:
+
+ - Remove std_readline(). This called up_getc() and up_putc() directly,
+ violating the POSIX OS interface.
+
+ * apps/netutils:
+
+ - FTPD: Fixed bug that didn't free ftpd ressources on exit. From Pascal
+ Speck.
+ - NTP client: Fix missing left parenthesis. From Pierre-Noel Bouteville.
+ - cJSON: Import patch to fix:cJSON_PrintUnformatted() behaves unexpected
+ if an empty array shall be printed to text. from Jerome Lang
+ 2012-04-19. From Pierre-Noel Bouteville.
+ - esp8266 update cosmetic and many bug fix. From Pierre-Noel Bouteville.
+ - FTPD: Fix bug un ftpd file or socket may be not closed. From
+ Pierre-Noel Bouteville.
+
+ * apps/modbus:
+
+ - Modbus Master is missing many files and doesn't compile at all. More
+ details in
+ https://groups.yahoo.com/neo/groups/nuttx/conversations/topics/13734.
+ From Vytautas Lukenskas.
+
+ * apps/examples:
+
+ - The examples/qencoder app was trying to init the encoder by a direct
+ call into the board, cheating in a local header to declare the
+ normally unavailable function prototype. From Sebastien Lorquet.
+ - apps/examples/timer: Should detach signal handler before exiting.
+ - examples/qencode: The examples/qencoder app was trying to init the
+ encoder by a direct call into the board, cheating in a local header to
+ declare the normally unavailable function prototype. From Sebastien
+ Lorquet.
+ - apps/examples/archbuttons: Removed becaue it violates OS interface
+ principles.
+ - examples/adc, pwm, can: Remove all usage of BOARDIOC_ADCTEST_SETUP,
+ BIOARDIOC_PWMSETUP. Remove BOARDIOC_CAN_INITIALIZE. CAN
+ initialization is now done in the board initialization logic just like
+ every other device driver.
+ - examples/ostest: Add some delays to the pthread cancellation test.
+ With deferred cancellation enabled, things happen more asynchronously.
+
+NuttX-7.20 Release Notes
+------------------------
+
+The 120th release of NuttX, Version 7.20, was made on March 8, 2017,
+and is available for download from the Bitbucket.org website. Note
+that release consists of two tarballs: nuttx-7.20.tar.gz and
+apps-7.20.tar.gz. These are available from:
+
+ https://bitbucket.org/nuttx/nuttx/downloads
+ https://bitbucket.org/nuttx/apps/downloads
+
+Both may be needed (see the top-level nuttx/README.txt file for build
+information).
+
+Additional new features and extended functionality:
+
+ * Core OS:
+
+ - Kernel Modules: Module initializer may now return a symbol table.
+ - Modules: Extend the module interface so that we can access symbols
+ exported by the module.
+ - Shared Libraries: In the FLAT build mode, kernel modules may be
+ used to provide minimal shared library functionality.
+ - Modules/Shared Libraries: Add support for dependencies between
+ modules.
+ - Module Library: Add build a configuration logic for a shared module
+ library.
+ - Shared Libraries: Implement module based shared libraries for the
+ PROTECTED mode build.
+ - Interrupt handling: irq_attach() now includes an argument of type
+ xcpt_t that retained with the handler address. That argument is
+ then provided to the interrupt handler when the interrupt occurs.
+ The common parameter passing replaces the ad hoc parmater passing
+ implemented in current drivers. From Mark Schulte.
+ - Adapt many drivers to utilize the IRQ argument feature.
+ - All functions that used to return an xcpt_t old handler value, now
+ return an int error code. The oldhandler value is no longer useful
+ with the recent changes to the interrupt argument passing. Some of
+ the functions effected include board_button_irq(), arch_phy_irq(),
+ STM32 EXTI functions (Alarm, COMP, PVD), GPIO interrupt logic like
+ kinetis_pinirq(), stm32_gpiosetevent(), and others.
+ - IRQ subsystem: Add support for smaller interrupt tables as
+ described at
+ http://www.nuttx.org/doku.php?id=wiki:howtos:smallvectors . This
+ is partially the work of Mark Schulte.
+
+ * File Systems/Block and MTD Drivers
+
+ - Pseudo File System: Add support for soft links in the top-level
+ psuedo file system.
+ - Soft links: Add an implementation of readlink().
+ - Add fstat() support. Implement fstat() method in binfs, romfs,
+ unionfs, tmpfs, nxffs, nfx, hostfs, procfs, and smartfs.
+ - fstat: Add fstat() support to FAT. From Alan Carvalho de Assis.
+
+ * Graphics/Display Drivers:
+
+ - Fonts: Add support for Tom Thumb small mono-space font. From Alan
+ Carvalho de Assis.
+ - Graphics: Separated of font cache from graphics/nxterm. Now in
+ libnx/nxfronts where it can be shared with other grapics
+ applications.
+
+ * Networking/Network Drivers:
+
+ - Ethernet drivers: Add framework for serialization in the case where
+ multiple low-priority work queues are used.
+
+ * Other Common Device Drivers:
+
+ - Add capabilities() method to SDIO interface. Remove
+ CONFIG_SDIO_WIDTH_D1_ONLY. That should not be a global propertie,
+ but rather a capability/limitation of single slot when there may be
+ multiple slots.
+ - Removed dmasupported() method from the SDIO interface. That is now
+ a bit in the capability set.
+ - drivers/sensors: Add driver for the ST L3GD20 3 axis gyro. From
+ raiden00.
+
+ * Atmel SAM3/4:
+
+ - SAM3/4: Add support for ATSAM4S4C. From Wolfgang Reinegger.
+
+ * NXP Freescale i.MX6 Boards:
+
+ - Sabre 6quad: Enable examples/smp test in i.MX6 SMP/NSH
+ configurations.
+
+ * NXP Freescale Kinetis:
+
+ - Kinetis: Added support for CHIP_MK60FN1M0VLQ12 chip. From Maciej
+ Skrzypek.
+ - Kinetis: Add support for K64/K66 RTC lower half driver. From Neil
+ Hancock.
+ - Kinetis: Extensive modification of MCG support based feature
+ configuration. From David Sidrane.
+ - Kinetis: Add support for K66 family. From David Sidrane.
+ - Kinetis: Created a kinetis SIM versioning scheme pulled in by
+ Kinetis chip.h. From David Sidrane.
+ - Created a kinetis PMC versioning scheme pulled in by Kinetis
+ chip.h. From David Sidrane.
+ - Kinetis: Extend clock configuration logic. Refactor
+ implementation. From David Sidrane.
+
+ * NXP Freescale Kinetis Drivers:
+
+ - Kinetis Ethernet: Kinetis Support RMII clock source select. This
+ defined the RMII clock source select bits and allows the selection
+ to be made via Kconfig. From David Sidrane. Freedom-K66F uses
+ ENET_1588_CLKIN as RMII clock
+ - Kinetis Serial: Added configurable 1|2 stop bits.
+ HAVE_SERIAL_CONSOLE -> HAVE_UART_CONSOLE to be consistent with
+ HAVE_LPUART_CONSOLE naming. From David Sidrane.
+ - Kinetis LPserial: Add LPUART serial driver and Clock
+ configuartaion to freedom-k66f board. From David Sidrane.
+ - Kinetis USB device: Refactor clocking in kinetis_usbdev. From
+ David Sidrane.
+
+ * NXP Freescale Kinetis Boards:
+
+ - Add support for NXP Freedom-k66f development board. From David
+ Sidrane.
+ - Kinetis Freedom K66F: Add Ethernet support. From David Sidrane.
+ - Add twr-k64f120m config. From Marc Recht.
+
+ * NXP Freescale LPC43xx Boards:
+
+ - Bamboo-200E: Add netnsh configuration. From Alan Carvalho de Assis.
+ - Add usbnsh config to Bambino 200E board. From Alan Carvalho de
+ Assis.
+
+ * STMicro STM32:
+
+ - STM32 F7: Allow board to configure HSE clock in bypass-mode. This
+ is needed to enable HSE with Nucleo-F746ZG board. From Jussi
+ Kivilinna.
+ - STM32 F7: stm32_allocateheap: allow use DTCM memory for heap.
+ STM32F7 has up to 128KiB of DTCM memory that is currently left
+ unused. This change adds DTCM to main heap if
+ CONFIG_STM32F7_DTCMEXCLUDE is not enabled. From Jussi Kivilinna.
+ - Add basic support for the STM32F334. From Mateusz Szafoni.
+ - STM32F33XX DAC, OPAMP, COMP, ADC, HRTIM headers. From Mateusz
+ Szafoni.
+
+ * STMicro STM32 Drivers:
+
+ - STM32 F7 SDMMC: Add support for single bit operation on SDMMC2.
+ - STM32 L4: Port STM32L4 SAI driver from MDK.
+ - STM32 L4: Bring power management logic from Motrola MDK into NuttX.
+ - STM32 L4: Bring LPTIM driver in from the Motorola MDK.
+ - STM32 L4 COMP: Port from Motorola MDK.
+
+ * STMicro STM32 Boards:
+
+ - STM32F429i Discovery: Add support for NxWM on STM32F429i-Disco
+ board. From Alan Carvalho de Assis.
+ - STM32F103 Minimum: Add support for nRF24 on STM32F103-Minimum
+ board. From Alan Carvalho de Assis.
+ - Olimex STM32 P407: Add a NSH protected build configuration; Enable
+ procfs/ in all configurations.
+ - Olimex STM32 P407: Add support for on-board microSD slot.
+ - STM32F429i Discovery: add support for the L3GD20 driver. From
+ raiden00.
+ - STM32F103 Minimum: Add support to QEncoder on STM32F103 Minimum
+ board. From Alan Carvalho de Assis.
+ - Olimex STM32 P407: Add external SRAM support.
+ - Add basic support for the Nucleo F334R8 board. From Mateusz
+ Szafoni.
+ - STM32F103 Minimum: Add SDCard support over SPI on STM32F103-Minimum
+ board. From Alan Carvalho de Assis.
+ - STM32F103 Minimum: Add support to USB Device on STM32F103-Minimum
+ board. From Alan Carvalho de Assis.
+
+ * C Library/Header Files:
+
+ - compiler.h: packed_struct replaced by begin_packed_struct and
+ end_packed_struct. Now support IAR style packed structures. From
+ Aleksandr Vyhovanec.
+ - Math library: Leverage optimized ARMv8-M functions from BSD license
+ ARM file.
+ - Shared libraries: Add a non-standard dllfnc.h function to set the
+ symbol table.
+ - C Library: Add a support for setvbuf(). This is a collaborative
+ effort. Alan Carvalho de Assis did the initial prototype.
+ - C Library: Add setbuf() which is a trivial wrapper around setvbuf().
+ - C library: Add swab().
+ - C library: Add strtoimax and strtoumax.
+ - C library: Add ffs(), rindex(), an index(). Add strings.h. Move
+ strcasecmp, strncasecmp, bzero, bcmp, and bcopy to where they
+ belong in strings.h.h, not string.h. bzero, bcmp, and bcopy are
+ legacy functions; the contemporary counterparts should be used
+ instead.
+ - C library: Add fstatfs().
+ - Update cwchar. Add cwctype.
+
+ * Build/Configuration System:
+
+ - Add configuration support for builds with Ubuntu under Windows 10.
+
+ * Tools:
+
+ - tools/noteinfo.c: A hack tool that I use to analyze some sched_note
+ output. Needs a home and may be useful to others.
+ - tools/mkconfig.c: Add logic to keep all of the buffering options in
+ sync.
+
+ * NSH: apps/nshlib:
+
+ - NSH: Add support for the 'ln' command.
+ - NSH ls command: if node is a symobolic link, use readlink() to get
+ and the display the target of the symblic link.
+ - NSH: Add readlink command.
+
+ * Applications: apps/examples:
+
+ - apps/examples/nxtext: Make line spacing configurable.
+ - apps/system/zmodem/host/nuttx/compiler.h synchronized with
+ nuttx/nuttx/include/nuttx/compiler.h. From Aleksandr Vyhovanec.
+ - apps/examples/sotest: Add a test for shared libraries.
+ - apps/examples/ostest: Add a test of setvbuf().
+ - apps/examples/stat: Add a simple test for stat(), fstat(),
+ statfs(), and fstatfs().
+
+Works-In-Progress:
+
+ * IEEE802.14.5/6LowPAN. Hooks and framework for this effort were
+ introduced in NuttX-7.15. Work has continued on this effort on
+ forks from the main repositories, albeit with many interruptions.
+ The completion of this wireless feature will postponed until at
+ least NuttX-7.21.
+
+Bugfixes. Only the most critical bugfixes are listed here (see the
+ChangeLog for the complete list of bugfixes and for additional, more
+detailed bugfix information):
+
+ * Core OS:
+
+ - SMP: There were certain conditions that we must avoid by preventing
+ the release of the pending tasks while withn a critical section.
+ But this logic was incomplete; there was no logic to prevent other
+ CPUs from adding new, running tasks while on CPU is in a critical
+ section. This commit corrects this. This is matching logic in
+ sched_addreadytorun to avoid starting new tasks within the critical
+ section (unless the CPU is the holder of the lock). The holder of
+ the IRQ lock must be permitted to do whatever it needs to do.
+ - SMP: Make checks for CPU lock set more robust. There are certain
+ conditions early in initialization on during interrupt handling
+ where things need to be done a little differently.
+ - sched_cpulocked: Avoid use of spinlock. That has been reported to
+ cause a deadlock (2016-12-28).
+ - SMP: Fix a gap where we may try to make modifications to the task
+ lists without being in a critical sections. That permits
+ concurrent access to the tasks lists and many subtle problems.
+ This fix just remains in the critical section throughout the
+ operation (and possible until the task is restore in the event of a
+ context switch). Makes a big difference in stability.
+ - SMP: Fix an error in critical section logic when performing a
+ context switch from an interrupt handler. The g_cpu_irqset bit was
+ not being set for the CPU so other CPUs did not know about the
+ critical section.
+ - SMP Signals: Fix some SMP signal delivery logic. Was not handling
+ some critical sections correctly and was missing logic to signal
+ tasks running on other CPUs.
+ - SMP: Fix timer related issues: Round robin and sporadic
+ scheduling were only being performed for tasks running on the CPU
+ that processes the system timer interrupt. Similary, CPU load
+ measurements were only be processed for running on the CPU that
+ receives the sampling interrupt.
+ - sched_note: Fix spinlock instrumentation. From Masayuki Ishikawa.
+ - In all implementations of _exit(), use enter_critical_section() vs.
+ disabling local interrupts.
+ - sigtimedwait: When timer expires, up_unblock_task() is called.
+ This is okay in the single CPU case because interrupts are disable
+ in the timer interrupt handler. But it is insufficient in the SMP
+ case. enter_ and leave_critical_section() must be called in order
+ to manage spinlocks correctly.
+ - Fix a compile error: in sched_cpuload.c:Line136, the variables ts
+ and secs are not defined if CONFIG_CPULOAD_ONESHOT_ENTROPY = 0.
+ However, these variables are used regardless of
+ CONFIG_CPULOAD_ONESHOT_ENTROPY at lines~180:onwards. From rg.
+ - CPU load: Correct computation of the nominal period to use when the
+ source is a oneshot timer.
+ - Cancellation points: Fix some backward logic in conditional
+ compilation.
+ - Remove an unused variable when calling sigwaitinfo() and
+ sigtimedwait(). From Masayuki Ishikawa.
+
+ * File System/Block and MTD Drivers:
+
+ - procfs: Correct to snprintf-related errors in fs_procfsproc.c.
+ Resolves issue #24.
+ - Add logic to VFS rename: If target of rename exists and is a
+ directory, then the source file should be moved 'under' the target
+ directory. POSIX also requires that if the target is a file, then
+ that old file must be deleted.
+ - Fix open() a block device with
+ CONFIG_DISABLE_PSEUDOFS_OPERATIONS=y. From Masayuki Ishikawa.
+ - File System: Don't build block driver proxy if PSEUDOFS_OPERATIONS
+ are disabled.
+ - sendfile(): Fix error introduced with commit
+ ff73be870e38959b0aaee5961dc47b4b58dc2d86. Noted by Maciej Wjcik.
+
+ * Graphics/Graphic Drivers:
+
+ - NxWM configurations. If using a 7-bit character set, then the
+ cursor character cannot be 137 (graphic block). Use 95
+ (underscore) instead.
+ - NX server: Correct message queue names. Should not be at /dev,
+ but rather relative to /var/mqueue.
+
+ * Common Drivers:
+
+ - MMCSD_SDIO: Only wait for card ejected if card detection is
+ supported. From Alan Carvalho de Assis.
+ - Typos withim mtd/ with Macronix MX25L. In
+ NuttX/drivers/mtd/Make.defs letters X between M and 25 are
+ missing. Noted by Oleg Evseev.
+ - USBMSC: Always set LUN readonly flag. From Wolfgang Reinegger.
+ - drivers/lcd: ssd1306_configspi() must have global scope.
+ - MMC/SD SDIO: Some drivers need to start DMA before sending CMD24
+ and some AFTER. From Alan Carvalho de Assis.
+ - drivers/tone.c: Handle configuration with multiple PWM channels.
+ This resolves issue #30: Audio Tone Generator and PWM Multiple
+ Output Channel options.
+ - drivers/tone.c: 50% duty needs to be expressed a a fixed precision
+ number.
+ - drivers/spi/Kconfig: There is too much SPI in the configuration
+ menu; SPI Driver Support menu is empty. From Maciej Wjcik.
+ - option to enable Memory Card debug output was hidden with SD cards
+ connected through SPI. From Maciej Wjcik.
+ - usbhost_cdcacm: fix tx outbuffer overflow and remove now invalid
+ assert. From Janne Rosberg.
+
+ * Networking/Network Drivers:
+
+ - Networking: Fixed some issues that prevented IPv6 from working with
+ IPv4 enabled. From Pascal Speck.
+ - Networking: fixed a nullptr-dereference on iob_clone. From Pascal
+ Speck.
+ - Ethernet: Need two work structures (minimum) in all Ethernet
+ drivers so that pending poll work is not lost when an interrupt
+ occurs.
+
+ * ARMv7-R:
+
+ - I found an issue inside the cp15_coherent_dcache function: The
+ "mcr CP15_BPIALLIS(r0)" should only be used with SMP
+ configurationa. In non-SMP configuration this instruction could
+ become undefined. From Manohara HK.
+
+ * Atmel SAM3/4 Drivers:
+
+ - SAM3/4: GPIO bit numbering typo fixes. From Wolfgang Reinegger.
+
+ * Atmel SAM3/4 Boards:
+
+ - Add missing sched_note_*() calls in sam4cm SMP functions.
+
+ * NXP/Freescale Kinetis:
+
+ - Kinetis: Fixed wrong MCG VDIV calculation on new NXP K60. From
+ Maciej Skrzypek.
+ - Kinetis: Need to set HAVE_UART_DEVICE when UART4 is selected. From
+ Maciej Skrzypek.
+ - Kinetis MCG: Wrong FRDIV set in MCG_C1. From Maciej Skrzypek.
+
+ * NXP/Freescale Kinetis Drivers:
+
+ - Kinetis Serial: Fixed compile error when UART5 is selected. From
+ Maciej Skrzypek.
+ - Kinetis SDHC - Enable clock after selected. From David Sidrane.
+ - Kinetis: Correct some SPI and I2C configuration issues. From
+ David Sidrane.
+ - Kinetis Ethernet: Add #define for number of loops for auto
+ negotiation to complete. From Marc Recht.
+ - Kinetis Werial: Fixed up_rxint - did not disable the RX
+ interuppts. There was an OR where and AND NOT was needed. From
+ David Sidrane.
+
+ * NXP/Freescale LPC43xx:
+
+ - LPC43 pinset definitions: Add more 1 bit to pinset to reach
+ SFSCLK0-SFSCLK3. Remove PINCONFIG_DIGITAL. From Alan Carvalho de
+ Assis.
+
+ * NXP/Freescale LPC43xx Drivers:
+
+ - LPC43 serial: Correct conditional logic that selects /dev/ttySN.
+ Problem noted by Alan Carvalho de Assis.
+
+ * NXP/Freescale i.MX6:
+
+ - i.MX6: Fix clearing GPT status register. From Masayuki Ishikawa.
+
+ * STMicro STM32:
+
+ - STM32, STM32L4 Oneshot: Fix logic so that it can support multiple
+ oneshot timers.
+ - STM32 F7: Added missing ARCH_HAVE_RESET for F7. From David Sidrane.
+ - STM32: Add missing STM32_BKP_BASE. From David Sidrane.
+ - STM32 and STM32F7: Fixes the BKP reference counter issue. From
+ David Sidrane.
+
+ * STMicro STM32 Drivers:
+
+ - Fix for SAMv7 SPI: DLYBS value was calculated, but never written to
+ any registers. This led to incorrect timings on the bus. From
+ Michael Spahlinger.
+ - STM32 QEncoder: Fix QEncoder driver, based on STM32L4 driver. From
+ Alan Carvalho de Assis.
+ - STM32 QEncoder: Enable clocking to the timer on QE setup; disable
+ clock on QE teardown.
+ - STM32 Ethernet: Need two work structures so that pending poll work
+ is not lost when an interrupt occurs. This change has also been
+ ported to all all other effected Ethernet drivers.
+ - STM32 OTGHS host: stm32_in_transfer() fails and returns NAK if a
+ short transfer is received. This causes problems from class
+ drivers like CDC/ACM where short packets are expected. In those
+ protocols, any transfer may be terminated by sending short or NUL
+ packet. From Janne Rosberg. Adapted Janne Rosberg's patch to
+ STM32 OTGHS host to OTGFS host, and to similar USB host
+ implementations for STM32 L4 and F7.
+
+ * STMicro STM32 Boards:
+
+ - STM32F4 Discovery: Fix issues with QEncoder support. From Alan
+ Carvalho de Assis.
+
+ * C Library/Header Files:
+
+ - Add debug assertion in libdtoa to catch attempts to use floating
+ point output formats from within an interrupt handler. That will
+ cause assertions or crashes downstream because __dtoa will attempt
+ to allocate memory. From Pierre-noel Bouteville.
+ - libc: Fix ARMv7-A/R memcpy assembly.
+ - Fix return value if x is NaN. From Aleksandr Vyhovanec.
+
+ * apps/nshlib:
+
+ - NSH: Eliminate a warning when all memory inspection commands are disabled.
+
+ * apps/graphics:
+
+ - apps/graphics/traveler/tools: Fix linkage issue. The -lm should
+ come after -o binname. From Alan Carvalho de Assis.
+
+ * apps/netutils:
+
+ - The CONFIG_NETUTILS_HTTPD_PATH constant is used by httpd_mmap.c and
+ httpd_sendfile.c but It was not present in Kconfig menu. From
+ Maciej Wjcik.
+
+ * apps/examples:
+
+ - Configurations that enable OSTEST must not disable signals.
+ - apps/examples/ostest: Was ignoring
+ CONFIG_EXAMPLES_OSTEST_FPUTESTDISABLE.
+ - In apps/examples/mtdpart/mtdpart_main.c where
+ CONFIG_EXAMPLES_MTDPART_NPARTITIONS defining is checked should be
+ #ifndef instead of #ifdef. Noted by Oleg Evseev.
diff --git a/TODO b/TODO
index b131d0205e52500f8192b35c3a4046186fa27dee..8ab2b48b50f3d3d42c1e06db1cc40abd99411c31 100644
--- a/TODO
+++ b/TODO
@@ -1,4 +1,4 @@
-NuttX TODO List (Last updated May 28, 2016)
+NuttX TODO List (Last updated March 7, 2017)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
This file summarizes known NuttX bugs, limitations, inconsistencies with
@@ -9,28 +9,30 @@ issues related to each board port.
nuttx/:
- (13) Task/Scheduler (sched/)
+ (10) Task/Scheduler (sched/)
+ (1) SMP
(1) Memory Management (mm/)
+ (0) Power Management (drivers/pm)
(3) Signals (sched/signal, arch/)
(2) pthreads (sched/pthread)
(0) Message Queues (sched/mqueue)
- (9) Kernel/Protected Build
+ (8) Kernel/Protected Build
(3) C++ Support
(6) Binary loaders (binfmt/)
- (12) Network (net/, drivers/net)
+ (13) Network (net/, drivers/net)
(4) USB (drivers/usbdev, drivers/usbhost)
(0) Other drivers (drivers/)
- (11) Libraries (libc/, libm/)
- (11) File system/Generic drivers (fs/, drivers/)
- (8) Graphics subsystem (graphics/)
- (1) Build system / Toolchains
+ (12) Libraries (libc/, libm/)
+ (10) File system/Generic drivers (fs/, drivers/)
+ (9) Graphics Subsystem (graphics/)
+ (2) Build system / Toolchains
(3) Linux/Cywgin simulation (arch/sim)
(4) ARM (arch/arm/)
apps/ and other Add-Ons:
- (3) Network Utilities (apps/netutils/)
- (2) NuttShell (NSH) (apps/nshlib)
+ (2) Network Utilities (apps/netutils/)
+ (1) NuttShell (NSH) (apps/nshlib)
(1) System libraries apps/system (apps/system)
(1) Pascal add-on (pcode/)
(4) Other Applications & Tests (apps/examples/)
@@ -99,16 +101,37 @@ o Task/Scheduler (sched/)
Status: Open
Priority: Medium Low for now
- Title: ISSUES WITH atexit() AND on_exit()
+ Title: ISSUES WITH atexit(), on_exit(), AND pthread_cleanup_pop()
Description: These functions execute with the following bad properties:
1. They run with interrupts disabled,
2. They run in supervisor mode (if applicable), and
3. They do not obey any setup of PIC or address
environments. Do they need to?
+ 4. In the case of task_delete() and pthread_cancel(), these
+ callbacks will run on the thread of execution and address
+ context of the caller of task. That is very bad!
The fix for all of these issues it to have the callbacks
- run on the caller's thread (as with signal handlers).
+ run on the caller's thread as is currently done with
+ signal handlers. Signals are delivered differently in
+ PROTECTED and KERNEL modes: The deliver is involes a
+ signal handling trampoline function in the user address
+ space and two signal handlers: One to call the signal
+ handler trampoline in user mode (SYS_signal_handler) and
+ on in with the signal handler trampoline to return to
+ supervisor mode (SYS_signal_handler_return)
+
+ The primary difference is in the location of the signal
+ handling trampoline:
+
+ - In PROTECTED mode, there is on a single user space blob
+ with a header at the beginning of the block (at a well-
+ known location. There is a pointer to the signal handler
+ trampoline function in that header.
+ - In the KERNEL mode, a special process signal handler
+ trampoline is used at a well-known location in every
+ process address space (ARCH_DATA_RESERVE->ar_sigtramp).
Status: Open
Priority: Medium Low. This is an important change to some less
important interfaces. For the average user, these
@@ -142,84 +165,11 @@ o Task/Scheduler (sched/)
incompatibilities could show up in porting some code).
Priority: Low
- Title: REMOVE TASK_DELETE
- Description: Need to remove or fix task delete. This interface is non-
- standard and not safe. Arbitrary deleting tasks can cause
- serious problems such as memory leaks. Better to remove it
- than to retain it as a latent bug.
-
- Currently used within the OS and also part of the
- implementation of pthread_cancel() and task_restart() (which
- should also go for the same reasons). It is used in
- NxWM::CNxConsole to terminate console tasks and also in
- apps/netutils/thttpd to kill CGI tasks that timeout.
- Status: Open
- Priority: Low and not easily removable.
-
- Title: RELEASE SEMAPHORES HELD BY CANCELED THREADS:
- Description: Commit: fecb9040d0e54baf14b729e556a832febfe8229e: "In
- case a thread is doing a blocking operation (e.g. read())
- on a serial device, while it is being terminated by
- pthread_cancel(), then uart_close() gets called, but
- the semaphore (dev->recv.sem in the above example) is
- still blocked.
-
- "This means that once the serial device is opened next
- time, data will arrive on the serial port (and driver
- interrupts handled as normal), but the received characters
- never arrive in the reader thread.
-
- This patch addresses the problem by re-initializing the
- semaphores on the last uart_close() on the device."
-
- Yahoo! Groups message 7726: "I think that the system
- should be required to handle pthread_cancel safely in
- all cases. In the NuttX model, a task is like a Unix
- process and a pthread is like a Unix thread. Canceling
- threads should always be safe (or at least as unsafe) as
- under Unix because the model is complete for pthreads...
-
- "So, in my opinion, this is a generic system issue, not
- specific to the serial driver. I could also implement
- logic to release all semaphores held by a thread when
- it exits -- but only if priority inheritance is enabled;
- because only in that case does the code have any memory
- of which threads actually hold the semaphore.
-
- "The patch I just incorporated is also insufficient. It
- works only if the serial driver is shut down when the
- thread is canceled. But what if there are other open
- references to the driver? Then the driver will not be
- shut down, the semaphores will not be re-initialized, and
- the semaphore counts will still be off by one.
-
- "I think that the system needs to automatically release any
- semaphores held by a thread being killed asynchronously?
- It seems necessary to me."
-
- UPDATE; The logic enabled when priority inheritance is
- enabled for this purpose is insufficient. It provides
- hooks so that given a semaphore it can traverse all
- holders. What is needed would be logic so that given
- a task, you can traverse all semaphores held by the task,
- releasing each semaphore count held by the exiting task.
- Nothing like this exists now so that solution is not
- imminent.
-
- UPDATE: The basic fix to release the semaphore count if
- a thread is killed via pthread_cancel() or task_delete()
- has been implemented (2014-12-13). See the new file:
- sched/semaphore/sem_recover.c However, the general
- issue of freeing semaphores when a thread exists still
- exists.
- Status: Open
- Priority: Medium-ish
-
Title: SCALABILITY
Description: Task control information is retained in simple lists. This
is completely appropriate for small embedded systems where
the number of tasks, N, is relatively small. Most list
- operations are O(N). This could become as issue if N gets
+ operations are O(N). This could become an issue if N gets
very large.
In that case, these simple lists should be replaced with
@@ -235,6 +185,37 @@ o Task/Scheduler (sched/)
Priority: Low. Things are just the way that we want them for the way
that NuttX is used today.
+o SMP
+ ^^^
+
+ Title: SMP AND DATA CACHES
+ Description: When spinlocks, semaphores, etc. are used in an SMP system with
+ a data cache, then there may be problems with cache coherency
+ in some CPU architectures: When one CPU modifies the shared
+ object, the changes may not be visible to another CPU if it
+ does not share the data cache. That would cause failure in
+ the IPC logic.
+
+ Flushing the D-cache on writes and invalidating before a read is
+ not really an option. That would essentially effect every memory
+ access and there may be side-effects due to cache line sizes
+ and alignment.
+
+ For the same reason a separate, non-cacheable memory region is
+ not an option. Essentially all data would have to go in the
+ non-cached region and you would have no benefit from the data
+ cache.
+
+ On ARM Cortex-A, each CPU has a separate data cache. However,
+ the MPCore's Snoop Controller Unit supports coherency among
+ the different caches. The SCU is enabled by the SCU control
+ register and each CPU participates in the SMP coherency by
+ setting the ACTLR_SMP bit in the auxiliary control register
+ (ACTLR).
+
+ Status: Closed
+ Priority: High on platforms that may have the issue.
+
o Memory Management (mm/)
^^^^^^^^^^^^^^^^^^^^^^^
@@ -306,7 +287,7 @@ o Memory Management (mm/)
So in this case, NuttX work just link Linux or or *nix systems:
All memory allocated by processes or threads in processes will
- be recovered when the process exists.
+ be recovered when the process exits.
But not for the flat memory build. In that case, the issues
above do apply. There is no safe way to recover the memory in
@@ -319,16 +300,21 @@ o Memory Management (mm/)
it is inherently unsafe, I would never incorporate anything
like that into NuttX.
- Status: Open. No changes are planned.
+ Status: Open. No changes are planned. NOTE: This applies to the FLAT
+ and PROTECTED builds only. There is no such leaking of memory
+ in the KERNEL build mode.
Priority: Medium/Low, a good feature to prevent memory leaks but would
have negative impact on memory usage and code size.
+o Power Management (drivers/pm)
+ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+
o Signals (sched/signal, arch/)
^^^^^^^^^^^^^^^^^^^^^^^
Title: STANDARD SIGNALS
Description: 'Standard' signals and signal actions are not supported.
- (e.g., SIGINT, SIGSEGV, etc).
+ (e.g., SIGINT, SIGSEGV, etc). Default is only SIG_IGN.
Update: SIGCHLD is supported if so configured.
Status: Open. No further changes are planned.
@@ -362,29 +348,27 @@ o Signals (sched/signal, arch/)
o pthreads (sched/pthreads)
^^^^^^^^^^^^^^^^^
- Title: CANCELLATION POINTS
- Description: pthread_cancel(): Should implement cancellation points and
- pthread_testcancel()
- Status: Open. No changes are planned.
- Priority: Low, probably not that useful
-
Title: PTHREAD_PRIO_PROTECT
- Description: Extended pthread_mutexattr_setprotocol() support PTHREAD_PRIO_PROTECT:
+ Description: Extend pthread_mutexattr_setprotocol(). It should support
+ PTHREAD_PRIO_PROTECT (and so should its non-standard counterpart
+ sem_setproto()).
+
"When a thread owns one or more mutexes initialized with the
PTHREAD_PRIO_PROTECT protocol, it shall execute at the higher of its
priority or the highest of the priority ceilings of all the mutexes
owned by this thread and initialized with this attribute, regardless of
whether other threads are blocked on any of these mutexes or not.
- "While a thread is holding a mutex which has been initialized with
+ "While a thread is holding a mutex which has been initialized with
the PTHREAD_PRIO_INHERIT or PTHREAD_PRIO_PROTECT protocol attributes,
it shall not be subject to being moved to the tail of the scheduling queue
at its priority in the event that its original priority is changed,
such as by a call to sched_setparam(). Likewise, when a thread unlocks
a mutex that has been initialized with the PTHREAD_PRIO_INHERIT or
PTHREAD_PRIO_PROTECT protocol attributes, it shall not be subject to
- being moved to the tail of the scheduling queue at its priority in the
+ being moved to the tail of the scheduling queue at its priority in the
event that its original priority is changed."
+
Status: Open. No changes planned.
Priority: Low -- about zero, probably not that useful. Priority inheritance is
already supported and is a much better solution. And it turns out
@@ -392,39 +376,77 @@ o pthreads (sched/pthreads)
Excerpted from my post in a Linked-In discussion:
"I started to implement this HLS/"PCP" semaphore in an RTOS that I
- work with (http://www.nuttx.org) and I discovered after doing the
- analysis and basic code framework that a complete solution for the
- case of a counting semaphore is still quite complex -- essentially
- as complex as is priority inheritance.
+ work with (http://www.nuttx.org) and I discovered after doing the
+ analysis and basic code framework that a complete solution for the
+ case of a counting semaphore is still quite complex -- essentially
+ as complex as is priority inheritance.
"For example, suppose that a thread takes 3 different HLS semaphores
- A, B, and C. Suppose that they are prioritized in that order with
- A the lowest and C the highest. Suppose the thread takes 5 counts
- from A, 3 counts from B, and 2 counts from C. What priority should
- it run at? It would have to run at the priority of the highest
- priority semaphore C. This means that the RTOS must maintain
- internal information of the priority of every semaphore held by
- the thread.
+ A, B, and C. Suppose that they are prioritized in that order with
+ A the lowest and C the highest. Suppose the thread takes 5 counts
+ from A, 3 counts from B, and 2 counts from C. What priority should
+ it run at? It would have to run at the priority of the highest
+ priority semaphore C. This means that the RTOS must maintain
+ internal information of the priority of every semaphore held by
+ the thread.
"Now suppose it releases one count on semaphore B. How does the
- RTOS know that it still holds 2 counts on B? With some complex
- internal data structure. The RTOS would have to maintain internal
- information about how many counts from each semaphore are held
- by each thread.
+ RTOS know that it still holds 2 counts on B? With some complex
+ internal data structure. The RTOS would have to maintain internal
+ information about how many counts from each semaphore are held
+ by each thread.
"How does the RTOS know that it should not decrement the priority
- from the priority of C? Again, only with internal complexity. It
- would have to know the priority of every semaphore held by
- every thread.
+ from the priority of C? Again, only with internal complexity. It
+ would have to know the priority of every semaphore held by
+ every thread.
"Providing the HLS capability on a simple pthread mutex would not
- be such quite such a complex job if you allow only one mutex per
- thread. However, the more general case seems almost as complex
- as priority inheritance. I decided that the implementation does
- not have value to me. I only wanted it for its reduced
- complexity; in all other ways I believe that it is the inferior
- solution. So I discarded a few hours of programming. Not a
- big loss from the experience I gained."
+ be such quite such a complex job if you allow only one mutex per
+ thread. However, the more general case seems almost as complex
+ as priority inheritance. I decided that the implementation does
+ not have value to me. I only wanted it for its reduced
+ complexity; in all other ways I believe that it is the inferior
+ solution. So I discarded a few hours of programming. Not a
+ big loss from the experience I gained."
+
+ Title: ISSUES WITH CANCELLATION POINTS
+ Description: According to POIX cancellation points must occur when a thread is executing
+ the following functions. There are some execptions as noted:
+
+ accept() mq_timedsend() NA putpmsg() sigtimedwait()
+ 04 aio_suspend() NA msgrcv() pwrite() NA sigwait()
+ NA clock_nanosleep() NA msgsnd() read() sigwaitinfo()
+ close() NA msync() NA readv() 01 sleep()
+ connect() nanosleep() recv() 02 system()
+ -- creat() open() recvfrom() NA tcdrain()
+ fcntl() pause() NA recvmsg() 01 usleep()
+ NA fdatasync() poll() select() -- wait()
+ fsync() pread() sem_timedwait() waitid()
+ NA getmsg() NA pselect() sem_wait() waitpid()
+ NA getpmsg() pthread_cond_timedwait() send() write()
+ NA lockf() pthread_cond_wait() NA sendmsg() NA writev()
+ mq_receive() pthread_join() sendto()
+ mq_send() pthread_testcancel() 03 sigpause()
+ mq_timedreceive() NA putmsg() sigsuspend()
+
+ NA Not supported
+ -- Doesn't need instrumentation. Handled by lower level calls.
+ nn See note nn
+
+ NOTE 01: sleep() and usleep() are user-space functions in the C library and cannot
+ serve as cancellation points. They are, however, simple wrappers around nanosleep
+ which is a true cancellation point.
+ NOTE 02: system() is actually implemented in apps/ as part of NSH. It cannot be
+ a cancellation point.
+ NOTE 03: sigpause() is a user-space function in the C library and cannot serve as
+ cancellation points. It is, however, a simple wrapper around sigsuspend()
+ which is a true cancellation point.
+ NOTE 04: aio_suspend() is a user-space function in the C library and cannot serve as
+ cancellation points. It does call around sigtimedwait() which is a true cancellation
+ point.
+ Status: Not really open. This is just the way it is.
+ Priority: Nothing additional is planned.
o Message Queues (sched/mqueue)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -447,6 +469,7 @@ o Kernel/Protected Build
mkfatfs mkfatfs
mkrd ramdisk_register()
ping icmp_ping()
+ mount foreach_mountpoint()
The busybox mkfatfs does not involve any OS calls; it does
its job by simply opening the block driver (using open/xopen)
@@ -583,14 +606,6 @@ o Kernel/Protected Build
improvement. However, there is no strong motivation now do
do that partitioning work.
- Title: TIMER INTERRUPT CALLBACK
- Description: The timer upper half driver at drivers/timers/timer.c performs
- interrupt level callbacks into applications. This, of course,
- will never work in anything but a non-secure, flat build.
- Status: Open
- Priority: Medium. The driver is only usable with all of its features
- in a FLAT build.
-
Title: USER MODE TASKS CAN MODIFY PRIVILEGED TASKS
Description: Certain interfaces, such as sched_setparam(),
sched_setscheduler(), etc. can be used by user mode tasks to
@@ -818,7 +833,7 @@ o Binary loaders (binfmt/)
"Read-Only Data in RAM" at
http://nuttx.org/Documentation/NuttXNxFlat.html#limitations).
- The newer 4.6.3compiler generated PC relative relocations to the strings:
+ The newer 4.6.3 compiler generated PC relative relocations to the strings:
.L2:
.word .LC0-(.LPIC0+4)
@@ -919,40 +934,18 @@ o Network (net/, drivers/net)
Priority: Medium. Important on slow applications that will not accept
connections promptly.
- Title: INTERRUPT LEVEL PROCESSING IN ETHERNET DRIVERS
- Description: Too many Ethernet drivers do interrupt-level processing with
- the network stack. The network stack supports either interrupt
- level processing or normal task level processing (depending on
- CONFIG_NET_NOINTS). This is really a very bad use of CPU
- resources; All of the network stack processing should be
- modified to use a work queue (and, all use of CONFIG_NET_NOINTS=n
- should be eliminated). This applies to almost all Ethernet
- drivers:
-
- ARCHITECTURE CONFIG_NET_NOINTS? ADDRESS FILTER SUPPORT?
- C5471 NO NO
- STM32 YES YES
- STM32F7 YES YES
- TIVA ----------------------- ------
- LM3S NO NO
- TM4C YES YES
- eZ80 NO NO
- LPC17xx YES YES (not tested)
- DMxxx NIC NO NO
- PIC32 NO NO
- RGMP ??? ???
- SAM3/4 YES YES
- SAMA5D ----------------------- ------
- EMACA NO YES (not tested)
- EMACB YES YES
- GMAC NO YES (not tested)
- SAMV7 YES YES
- SIM N/A (No interrupts) NO
-
- The general outline of how this might be done is included in
- drivers/net/skeleton.c
- Status: Open
- Priority: Pretty high if you want a well behaved system.
+ Title: IPv6 REQUIRES ADDRESS FILTER SUPPORT
+ Description: IPv6 requires that the Ethernet driver support NuttX address
+ filter interfaces. Several Ethernet drivers do support there,
+ however. Others support the address filtering interfaces but
+ have never been verifed:
+
+ C5471, LM3X, ez80, DM0x90 NIC, PIC: Do not support address
+ filteringing.
+ Kinetis, LPC17xx, LPC43xx: Untested address filter support
+
+ Status: Open
+ Priority: Pretty high if you want a to use IPv6 on these platforms.
Title: UDP MULTICAST RECEPTION
Description: The logic in udp_input() expects either a single receive socket or
@@ -1030,6 +1023,48 @@ o Network (net/, drivers/net)
Status: Open
Priority: Low
+ Title: REMOVE CONFIG_NET_MULTIBUFFER
+ Description: The CONFIG_NET_MULTIBUFFER controls some details in the layout
+ of the network device structure. This is really a unnecessary
+ complexity and should be removed. The cost for those network
+ drivers that currently do not support CONFIG_NET_MULTIBUFFER
+ is the size of one pointer.
+ Status: Open
+ Priority: Low
+
+ Title: ETHERNET WITH MULTIPLE LPWORK THREADS
+ Description: Recently, Ethernet drivers were modified to support multiple
+ work queue structures. The question was raised: "My only
+ reservation would be, how would this interact in the case of having CONFIG_STM32_ETHMAC_LPWORK and CONFIG_SCHED_LPNTHREADS
+ > 1? Can it be guaranteed that one work item won't be
+ interrupted and execution switched to another? I think so but
+ am not 100% confident."
+
+ I suspect that you right. There are probably vulnerabilities
+ in the CONFIG_STM32_ETHMAC_LPWORK with CONFIG_SCHED_LPNTHREADS
+ > 1 case. But that really doesn't depend entirely upon the
+ change to add more work queue structures. Certainly with only
+ work queue structure you would have concurrent Ethernet
+ operations in that multiple LP threads; just because the work
+ structure is available, does not mean that there is not dequeued
+ work in progress. The multiple structures probably widens the
+ window for that concurrency, but does not create it.
+
+ The current Ethernet designs depend upon a single work queue to
+ serialize data. In the case of muliple LP threads, some
+ additional mechanism would have to be added to enforce that
+ serialization.
+
+ NOTE: Most drivers will call net_lock() and net_unlock() around
+ the critical portions of the driver work. In that case, all work
+ will be properly serialized. This issue only applies to drivers
+ that may perform operations that require protection outside of
+ the net_lock'ed region. Sometimes, this may require extending
+ the netlock() to be beginning of the driver work function.
+
+ Status: Open
+ Priority: High if you happen to be using Ethernet in this configuration.
+
o USB (drivers/usbdev, drivers/usbhost)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -1161,7 +1196,7 @@ o USB (drivers/usbdev, drivers/usbhost)
from being usable:
- The driver works fine when configured for reduced or bulk-
- only protocol.
+ only protocol on the Olimex LPC1766STK.
- Testing has not been performed with the interrupt IN channel
enabled (ie., I have not enabled FLOW control nor do I have
@@ -1186,6 +1221,32 @@ o USB (drivers/usbdev, drivers/usbhost)
Apparently the host driver is trashing memory on receipt
of data.
+ UPDATE: This behavior needs to be retested with:
+ commit ce2845c5c3c257d081f624857949a6afd4a4668a
+ Author: Janne Rosberg
+ Date: Tue Mar 7 06:58:32 2017 -0600
+
+ usbhost_cdcacm: fix tx outbuffer overflow and remove now
+ invalid assert
+
+ commit 3331e9c49aaaa6dcc3aefa6a9e2c80422ffedcd3
+ Author: Janne Rosberg
+ Date: Tue Mar 7 06:57:06 2017 -0600
+
+ STM32 OTGHS host: stm32_in_transfer() fails and returns NAK
+ if a short transfer is received. This causes problems from
+ class drivers like CDC/ACM where short packets are expected.
+ In those protocols, any transfer may be terminated by sending
+ short or NUL packet.
+
+ commit 0631c1aafa76dbaa41b4c37e18db98be47b60481
+ Author: Gregory Nutt
+ Date: Tue Mar 7 07:17:24 2017 -0600
+
+ STM32 OTGFS, STM32 L4 and F7: Adapt Janne Rosberg's patch to
+ STM32 OTGHS host to OTGFS host, and to similar implements for
+ L4 and F7.
+
- The SAMA5D EHCI and the LPC31 EHCI drivers both take semaphores
in the cancel method. The current CDC/ACM class driver calls
the cancel() method from an interrupt handler. This will
@@ -1199,15 +1260,18 @@ o USB (drivers/usbdev, drivers/usbhost)
configurations if you use it.
That all being said, I know of know no issues with the current
- CDC/ACM driver if the interrupt IN endpoint is not used, i.e.,
- in "reduced" mode. The only loss of functionality is output
- flow control.
+ CDC/ACM driver on the Olimex LPC1766STK platform if the interrupt
+ IN endpoint is not used, i.e., in "reduced" mode. The only loss
+ of functionality is output flow control.
+
+ UPDATE: The CDC/ACM class driver may also now be functional on
+ the STM32. That needs to be verified.
Status: Open
Priority: Medium-Low unless you really need host CDC/ACM support.
-o Libraries (libc/)
- ^^^^^^^^^^^^^^^^^
+o Libraries (libc/, libm/)
+ ^^^^^^^^^^^^^^^^^^^^^^^^
Title: SIGNED time_t
Description: The NuttX time_t is type uint32_t. I think this is consistent
@@ -1291,8 +1355,8 @@ o Libraries (libc/)
Priority: ??
Title: FLOATING POINT FORMATS
- Description: Only the %f floating point format is supported. Others are accepted
- but treated like %f.
+ Description: Only the %f floating point format is supported. Others are
+ accepted but treated like %f.
Status: Open
Priority: Medium (this might important to someone).
@@ -1337,24 +1401,80 @@ o Libraries (libc/)
UPDATE: 2015-09-01: A fix for the noted problems with asin()
has been applied.
+ 2016-07-30: Numerous fixes and performance improvements from
+ David Alessio.
-Status: Open
-Priority: Low for casual users but clearly high if you need care about
+ Status: Open
+ Priority: Low for casual users but clearly high if you need care about
these incorrect corner case behaviors in the math libraries.
+ Title: REPARTITION LIBC FUNCTIONALITY
+ Description: There are many things implemented within the kernel (for example
+ under sched/pthread) that probably should be migrated in the
+ C library where it belongs.
+
+ I would really like to see a little flavor of a micro-kernel
+ at the OS interface: I would like to see more primitive OS
+ system calls with more higher level logic in the C library.
+
+ One awkward thing is the incompatibility of KERNEL vs FLAT
+ builds: In the kernel build, it would be nice to move many
+ of the thread-specific data items out of the TCB and into
+ the process address environment where they belong. It is
+ difficult to make this compatible with the FLAT build,
+ however.
+ Status: Open
+ Priority: Low
+
o File system / Generic drivers (fs/, drivers/)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
NOTE: The NXFFS file system has its own TODO list at nuttx/fs/nxffs/README.txt
- Title: CHMOD(), TRUNCATE(), AND FSTAT()
- Description: Implement chmod(), truncate(), and fstat().
- Status: Open
- Priority: Low
+ Title: MISSING FILE SYSTEM FEATURES
+ Description: Implement missing file system features:
+
+ chmod() is probably not relevant since file modes are not
+ currently supported.
+
+ File privileges would also be good to support. But this is
+ really a small part of a much larger feature. NuttX has no
+ user IDs, there are no groups, there are no privileges
+ associated with either. User's don't need credentials.
+ This is really a system wide issues of which chmod is only
+ a small part.
+
+ User privileges never seemed important to me since NuttX is
+ intended for deeply embedded environments where there are
+ not multiple users with varying levels of trust.
+
+ truncate - The standard way of setting a fixed file size.
+ Often used with random access, data base files. There is no
+ simple way of doing that now (other than just writing data
+ to the file).
+
+ link, unlink, softlink, readlink - For symbolic links. Only
+ the ROMFS file system currently supports hard and soft links,
+ so this is not too important.
+
+ File locking
+
+ Special files - NuttX support special files only in the top-
+ level pseudo file system. Unix systems support many
+ different special files via mknod(). This would be
+ important only if it is an objective of NuttX to become a
+ true Unix OS. Again only supported by ROMFS.
+
+ True inodes - Standard Unix inodes. Currently only supported
+ by ROMFs.
+
+ The primary obstacle to all these is that each would require
+ changes to all existing file systems. That number is pretty
+ large. The number of file system implementations that would
+ need to be reviewed and modified As of this writing this
+ would include binfs, fat, hostfs, nfs, nxffs, procfs, romfs,
+ tmpfs, unionfs, plus pseduo-file system support.
- Title: CAN POLL SUPPORT
- Description: At present, the CAN driver does not support the poll() method.
- See drivers/can.c
Status: Open
Priority: Low
@@ -1403,6 +1523,15 @@ o File system / Generic drivers (fs/, drivers/)
socket structures. There really should be one array that
is a union of file and socket descriptors. Then socket and
file descriptors could lie in the same range.
+
+ Another example of how the current implementation limits
+ functionality: I recently started to implement of the FILEMAX
+ (using pctl() instead sysctl()). My objective was to be able
+ to control the number of available file descriptors on a task-
+ by-task basis. The complexity due to the partitioning of
+ desciptor space in a range for file descriptors and a range
+ for socket descriptors made this feature nearly impossible to
+ implement.
Status: Open
Priority: Low
@@ -1428,15 +1557,6 @@ o File system / Generic drivers (fs/, drivers/)
Status: Open
Priority: Low
- Title: FAT LONG FILENAME COMPATIBILITY
- Description: Recently there have been reports that file with long file
- names created by NuttX don't have long file names when viewed
- on Windows. The long file name support has been around for a
- long time and I don't ever having seen this before so I am
- suspecting that some evil has crept in.
- Status: Open
- Priority: Medium
-
Title: MISSING FILES IN NSH 'LS' OF A DIRECTORY
Description: I have seen cases where (1) long file names are enabled,
but (2) a short file name is created like:
@@ -1494,7 +1614,7 @@ o File system / Generic drivers (fs/, drivers/)
ignored by readder() logic. This the file does not
appear in the 'ls'.
-o Graphics subsystem (graphics/)
+o Graphics Subsystem (graphics/)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
See also the NxWidgets TODO list file for related issues.
@@ -1537,18 +1657,6 @@ o Graphics subsystem (graphics/)
Status: Open
Priority: Medium low
- Title: IMPROVED NxTERM FONT CACHING
- Description: Now each NxTerm instance has its own private font cache
- whose size is determined by CONFIG_NXTERM_MXCHARS. If there
- are multiple NxTerm instances using the same font, each will
- have a separate font cache. This is inefficient and wasteful
- of memory: Each NxTerm instance should share a common font
- cache.
- Status: Open
- Priority: Medium. Not important for day-to-day testing but would be
- a critical improvement if NxTerm were to be used in a
- product.
-
Title: NxTERM VT100 SUPPORT
Description: If the NxTerm will be used with the Emacs-like command line
editor (CLE), then it will need to support VT100 cursor control
@@ -1585,6 +1693,37 @@ o Graphics subsystem (graphics/)
Priority: Low, not a serious issue but worth noting. There is no plan
to change this behavior.
+ Title: REMOVE SINGLE USER MODE
+ Description: NX graphics supports two modes: A simple single user mode and
+ more complex multi-user mode selected with CONFIG_NX_MULTIUSER=y.
+ In this configuration, an application can start the NX server
+ with boardctrl(BOARDIOC_NX_START); After that, all graphic
+ interactions are via a thin layer in libnx/. The OS
+ interface is only via messages sent and received using POSIX
+ message queues. So this is good code and respects all of the
+ POSIX interfacing rules. Hence, it works well in all build
+ modes (FLAT, PROTECTED, and KERNEL builds).
+
+ But without CONFIG_NX_MULTIUSER, the single user applications
+ violate all of the rules and calls internal NX functions
+ directly. This includes all calls to internal OSfunctions
+ with names like, nx_open, up_fbinitialize, board_lcd_*, and
+ others. This is a violation of interfacing standard in all
+ cases and can only be made to work in the FLAT build mode.
+
+ The single user mode does have some desirable properties: It
+ is lighter weight and so more suitable for very resource limited
+ platforms. But I think that in the long run the only reasonable
+ solution is to eliminate the single user mode and provide only
+ the multi-user mode with the message queue interface.
+ Status: Open
+ Priority: Low-Medium, not a serious issue but worth noting. Single user
+ mode is a blemish on the OS and not compatible with the RTOS
+ roadmap. But neither is there any critical necessity to
+ remove the offending code immediately. Be aware: If you use
+ the single user mode, it will be yanked out from under your
+ feet in the not-so-distant future.
+
o Build system
^^^^^^^^^^^^
@@ -1601,6 +1740,19 @@ o Build system
Status: Open
Priority: Low.
+ Title: NATIVE WINDOWS BUILD BROKEN
+ Description: The way that apps/ now generates Kmenu files depends on changes added
+ to apps/tools/mkkconfig.sh. Similar changes need to be made to
+ apps/tools/mkkconfig.bat to restore the Windows Native build.
+ UPDATE: The mkkconfig.bat script has been updated and appears to work.
+ A native build has still not been attempted and there could likely be
+ issues the carriage returns in Kconfig files. There are also some
+ issues the interpreters/ficl and bas directories during 'make menuconfig'
+ that still need to be investigated.
+ Status: Open
+ Priority: Low, since I am not aware of anyone using the Windows Native build.
+ But, of course, very high if you want to use it.
+
o Other drivers (drivers/)
^^^^^^^^^^^^^^^^^^^^^^^^
@@ -1716,7 +1868,7 @@ o ARM (arch/arm/)
upon return. This could be improved as well: If there is no
context switch, then the static registers need not be restored
because they will not be modified by the called C code.
- (see arch/sh/src/sh1/sh1_vector.S for example)
+ (see arch/renesas/src/sh1/sh1_vector.S for example)
Status: Open
Priority: Low
@@ -1787,19 +1939,13 @@ o Network Utilities (apps/netutils/)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
Title: UNVERIFIED THTTPD FEATURES
- Description: Not all THTTPD features/options have been verified. In particular, there is no
- test case of a CGI program receiving POST input. Only the configuration of
- apps/examples/thttpd has been tested.
+ Description: Not all THTTPD features/options have been verified. In
+ particular, there is no test case of a CGI program receiving
+ POST input. Only the configuration of apps/examples/thttpd
+ has been tested.
Status: Open
Priority: Medium
- Title: THTTPD WARNINGS
- Description: If the network is enabled, but THTTPD is not configured, it spews out lots
- of pointless warnings. This is kind of annoying and unprofessional; needs to
- be fixed someday.
- Status: Open. An annoyance, but not a real problem.
- Priority: Low
-
Title: NETWORK MONITOR NOT GENERALLY AVAILABLE
Description: The NSH network management logic has general applicability
but is currently useful only because it is embedded in the NSH
@@ -1819,11 +1965,6 @@ o NuttShell (NSH) (apps/nshlib)
Status: Open
Priority: Low
- Title: ARPPING COMMAND
- Description: Add an arping command
- Status: Open
- Priority: Low (enhancement)
-
o System libraries apps/system (apps/system)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
@@ -1879,7 +2020,12 @@ o Other Applications & Tests (apps/examples/)
it stops rendering. This is not a problem for the examples/nx
code because it uses so few fonts, but if the logic were
leveraged for more general purposes, it would be a problem.
+
Update: see examples/nxtext for some improved font cache handling.
+ Update: The NXTERM font cache has been generalized and is now
+ offered as the standard, common font cache for all applications.
+ both the nx and nxtext examples should be modified to use this
+ common font cache. See interfaces defined in nxfonts.h.
Status: Open
Priority: Low. This is not really a problem because examples/nx works
fine with its bogus font caching.
@@ -1893,3 +2039,4 @@ o Other Applications & Tests (apps/examples/)
the artifact is larger.
Status: Open
Priority: Medium.
+
diff --git a/arch/Kconfig b/arch/Kconfig
index fd61f2fbf55f96b6af107d6dc625c9454d389d94..6fac6fd310b679ec458384978ddab7e298c78faf 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -39,25 +39,34 @@ config ARCH_MIPS
---help---
MIPS architectures (PIC32)
-config ARCH_RGMP
- bool "RGMP"
+config ARCH_MISOC
+ bool "MISOC"
+ select ARCH_HAVE_INTERRUPTSTACK
+ select ARCH_HAVE_CUSTOMOPT
---help---
- RTOS and GPOS on Multi-Processor (RGMP) architecture. See
- http://rgmp.sourceforge.net/wiki/index.php/Main_Page.
+ MISOC
-config ARCH_SH
+config ARCH_RENESAS
bool "Renesas"
select ARCH_NOINTC
select ARCH_HAVE_INTERRUPTSTACK
---help---
Renesas architectures (SH and M16C).
+config ARCH_RISCV
+ bool "RISC-V"
+ select ARCH_HAVE_INTERRUPTSTACK
+ select ARCH_HAVE_CUSTOMOPT
+ ---help---
+ RISC-V 32 and 64-bit RV32 / RV64 architectures.
+
config ARCH_SIM
bool "Simulation"
select ARCH_HAVE_MULTICPU
select ARCH_HAVE_TLS
select ARCH_HAVE_TICKLESS
select ARCH_HAVE_POWEROFF
+ select SERIAL_CONSOLE
---help---
Linux/Cywgin user-mode simulation.
@@ -66,6 +75,13 @@ config ARCH_X86
---help---
Intel x86 architectures.
+config ARCH_XTENSA
+ bool "Xtensa"
+ select ARCH_HAVE_STACKCHECK
+ select ARCH_HAVE_CUSTOMOPT
+ ---help---
+ Cadence® Tensilica® Xtensa® actictures.
+
config ARCH_Z16
bool "ZNEO"
select ARCH_HAVE_HEAP2
@@ -82,25 +98,29 @@ endchoice
config ARCH
string
- default "arm" if ARCH_ARM
- default "avr" if ARCH_AVR
- default "hc" if ARCH_HC
- default "mips" if ARCH_MIPS
- default "rgmp" if ARCH_RGMP
- default "sh" if ARCH_SH
- default "sim" if ARCH_SIM
- default "x86" if ARCH_X86
- default "z16" if ARCH_Z16
- default "z80" if ARCH_Z80
+ default "arm" if ARCH_ARM
+ default "avr" if ARCH_AVR
+ default "hc" if ARCH_HC
+ default "mips" if ARCH_MIPS
+ default "misoc" if ARCH_MISOC
+ default "renesas" if ARCH_RENESAS
+ default "risc-v" if ARCH_RISCV
+ default "sim" if ARCH_SIM
+ default "x86" if ARCH_X86
+ default "xtensa" if ARCH_XTENSA
+ default "z16" if ARCH_Z16
+ default "z80" if ARCH_Z80
source arch/arm/Kconfig
source arch/avr/Kconfig
source arch/hc/Kconfig
source arch/mips/Kconfig
-source arch/rgmp/Kconfig
-source arch/sh/Kconfig
+source arch/misoc/Kconfig
+source arch/renesas/Kconfig
+source arch/risc-v/Kconfig
source arch/sim/Kconfig
source arch/x86/Kconfig
+source arch/xtensa/Kconfig
source arch/z16/Kconfig
source arch/z80/Kconfig
@@ -525,6 +545,7 @@ config ARCH_IRQPRIO
config ARCH_STACKDUMP
bool "Dump stack on assertions"
default n
+ select DEBUG_ALERT
---help---
Enable to do stack dumps after assertions
@@ -538,6 +559,7 @@ config ARCH_USBDUMP
config ENDIAN_BIG
bool "Big Endian Architecture"
default n
+ depends on !ARCH_RISCV
---help---
Select if architecture operates using big-endian byte ordering.
@@ -599,6 +621,44 @@ config ARCH_RAMVECTORS
If ARCH_RAMVECTORS is defined, then the architecture will support
modifiable vectors in a RAM-based vector table.
+config ARCH_MINIMAL_VECTORTABLE
+ bool "Minimal RAM usage for vector table"
+ default n
+ ---help---
+ Use a minimum amount of RAM for the vector table.
+
+ Instead of allowing irq_attach() to work for all interrupt vectors,
+ restrict to only working for a select few (defined in your board
+ configuration). This can dramatically reduce the amount of RAM used
+ be your vector table.
+
+ To use this setting, you must have a file in your board config that
+ provides:
+
+ #include
+ const irq_mapped_t g_irqmap[NR_IRQS] =
+ {
+ ... IRQ to index mapping values ...
+ };
+
+ This table is index by the hardware IRQ number and provides a value
+ in the range of 0 to CONFIG_ARCH_NUSER_INTERRUPTS that is the new,
+ mapped index into the vector table. Unused, unmapped interrupts
+ should be set to IRQMAPPED_MAX. So, for example, if g_irqmap[37]
+ == 24, then the hardware interrupt vector 37 will be mapped to the
+ interrupt vector table at index 24. if g_irqmap[42] ==
+ IRQMAPPED_MAX, then hardware interrupt vector 42 is not used and
+ if it occurs will result in an unexpected interrupt crash.
+
+config ARCH_NUSER_INTERRUPTS
+ int "Number of interrupts"
+ default 0
+ depends on ARCH_MINIMAL_VECTORTABLE
+ ---help---
+ If CONFIG_ARCH_MINIMAL_VECTORTABLE is defined, then this setting
+ defines the actual number of valid, mapped interrupts in g_irqmap.
+ This number will be the new size of the OS vector table
+
comment "Board Settings"
config BOARD_LOOPSPERMSEC
diff --git a/arch/README.txt b/arch/README.txt
index 114f2f6f1e7e430067cf244458edbc5a37ffada5..a0f604e4affe695ed956fb33191c3e1bb5e94b6a 100644
--- a/arch/README.txt
+++ b/arch/README.txt
@@ -150,13 +150,14 @@ arch/arm - ARM-based micro-controllers
Architecture Support
arch/arm/include and arch/arm/src/common
arch/arm/src/arm and arch/arm/include/arm
+ arch/arm/src/armv7-a and arch/arm/include/armv6-m
arch/arm/src/armv7-a and arch/arm/include/armv7-a
arch/arm/src/armv7-m and arch/arm/include/armv7-m
- arch/arm/src/armv7-r and arch/arm/include/armv7-4
+ arch/arm/src/armv7-r and arch/arm/include/armv7-r
MCU support
+ arch/arm/include/a1x and arch/arm/src/a1x
arch/arm/include/c5471 and arch/arm/src/c5471
- arch/arm/include/calypso and arch/arm/src/calypso
arch/arm/include/dm320 and arch/arm/src/dm320
arch/arm/include/efm32 and arch/arm/src/efm32
arch/arm/include/imx1 and arch/arm/src/imx1
@@ -210,25 +211,24 @@ arch/mips
arch/mips/include/pic32mx and arch/mips/src/pic32mx
arch/mips/include/pic32mz and arch/mips/src/pic32mz
-arch/rgmp
+arch/renesas - Support for Renesas and legacy Hitachi microcontrollers.
+ This include SuperH and M16C.
- RGMP stands for RTOS and GPOS on Multi-Processor. RGMP is a project
- for running GPOS and RTOS simultaneously on multi-processor platforms.
- You can port your favorite RTOS to RGMP together with an unmodified
- Linux to form a hybrid operating system. This makes your application
- able to use both RTOS and GPOS features.
+ Architecture Support
+ arch/renesas/include and arch/renesas/src/common
- See http://rgmp.sourceforge.net/wiki/index.php/Main_Page for further
- information about RGMP.
+ MCU support
+ arch/renesas/include/m16c and arch/renesas/src/m16c
+ arch/renesas/include/sh1 and arch/renesas/src/sh1
-arch/sh - SuperH and related Hitachi/Renesas microcontrollers
+arch/risc-v
+ This directory is dedicated to ports to the RISC-V family.
Architecture Support
- arch/sh/include and arch/sh/src/common
+ arch/risc-v/include/rv32im
MCU support
- arch/sh/include/m16c and arch/sh/src/m16c
- arch/sh/include/sh1 and arch/sh/src/sh1
+ arch/risc-v/include/nr5m100
arch/x86 - Intel x86 architectures
This directory holds related, 32- and 64-bit architectures from Intel.
@@ -241,6 +241,21 @@ arch/x86 - Intel x86 architectures
arch/x86/include/i486 and arch/x86/src/i486
arch/x86/include/qemu and arch/x86/src/qemu
+arch/xtensa
+
+ Implementations based on the Cadence® Tensilica® Xtensa® processors,
+ such as the Xtensa LX6 dataplane processing units (DPUs). At
+ present, this includes the following subdirectories:
+
+ Common XTENSA support:
+ arch/xtensa/include and arch/xtensa/src/common
+
+ LX6 DPU support:
+ arch/xtensa/include/lx6 and arch/xtensa/xtensa/lx6
+
+ Expressif ESP32 implemenation of the LX6 DPU:
+ arch/xtensa/include/esp32 and arch/xtensa/xtensa/esp32
+
arch/z16 - ZiLOG 16-bit processors
This directory holds related, 16-bit architectures from ZiLOG. At
present, this includes the following subdirectories:
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 6b6c046060d4e3ba2d7233c2a90d9f18b1c401f0..fd44dcff0775e5506d35eebbe4a922167106e031 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -31,16 +31,6 @@ config ARCH_CHIP_C5471
---help---
TI TMS320 C5471, A180, or DA180 (ARM7TDMI)
-config ARCH_CHIP_CALYPSO
- bool "Calypso"
- select ARCH_ARM7TDMI
- select ARCH_HAVE_HEAP2
- select ARCH_HAVE_LOWVECTORS
- select OTHER_UART_SERIALDRIVER
- select ARCH_HAVE_POWEROFF
- ---help---
- TI Calypso-based cell phones (ARM7TDMI)
-
config ARCH_CHIP_DM320
bool "TMS320 DM320"
select ARCH_ARM926EJS
@@ -51,6 +41,7 @@ config ARCH_CHIP_DM320
config ARCH_CHIP_EFM32
bool "Energy Micro"
select ARCH_HAVE_CMNVECTOR
+ select ARCH_HAVE_SPI_BITORDER
select ARMV7M_CMNVECTOR
---help---
Energy Micro EFM32 microcontrollers (ARM Cortex-M).
@@ -84,6 +75,7 @@ config ARCH_CHIP_KINETIS
select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_FPU
select ARCH_HAVE_RAMFUNCS
+ select ARCH_HAVE_CMNVECTOR
---help---
Freescale Kinetis Architectures (ARM Cortex-M4)
@@ -206,12 +198,14 @@ config ARCH_CHIP_SAM34
config ARCH_CHIP_SAMV7
bool "Atmel SAMV7"
select ARCH_HAVE_CMNVECTOR
- select ARMV7M_CMNVECTOR
select ARCH_CORTEXM7
select ARCH_HAVE_MPU
- select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_RAMFUNCS
select ARCH_HAVE_TICKLESS
+ select ARCH_HAVE_I2CRESET
+ select ARCH_HAVE_SPI_CS_CONTROL
+ select ARM_HAVE_MPU_UNIFIED
+ select ARMV7M_CMNVECTOR
select ARMV7M_HAVE_STACKCHECK
---help---
Atmel SAMV7 (ARM Cortex-M7) architectures
@@ -220,9 +214,12 @@ config ARCH_CHIP_STM32
bool "STMicro STM32 F1/F2/F3/F4"
select ARCH_HAVE_CMNVECTOR
select ARCH_HAVE_MPU
- select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
+ select ARCH_HAVE_TICKLESS
+ select ARCH_HAVE_TIMEKEEPING
+ select ARCH_HAVE_SPI_BITORDER
+ select ARM_HAVE_MPU_UNIFIED
select ARMV7M_HAVE_STACKCHECK
---help---
STMicro STM32 architectures (ARM Cortex-M3/4).
@@ -230,12 +227,13 @@ config ARCH_CHIP_STM32
config ARCH_CHIP_STM32F7
bool "STMicro STM32 F7"
select ARCH_HAVE_CMNVECTOR
- select ARMV7M_CMNVECTOR
select ARCH_CORTEXM7
select ARCH_HAVE_MPU
- select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
+ select ARCH_HAVE_SPI_BITORDER
+ select ARM_HAVE_MPU_UNIFIED
+ select ARMV7M_CMNVECTOR
select ARMV7M_HAVE_STACKCHECK
---help---
STMicro STM32 architectures (ARM Cortex-M7).
@@ -243,12 +241,14 @@ config ARCH_CHIP_STM32F7
config ARCH_CHIP_STM32L4
bool "STMicro STM32 L4"
select ARCH_HAVE_CMNVECTOR
- select ARMV7M_CMNVECTOR
select ARCH_CORTEXM4
select ARCH_HAVE_MPU
- select ARM_HAVE_MPU_UNIFIED
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
+ select ARCH_HAVE_TICKLESS
+ select ARCH_HAVE_SPI_BITORDER
+ select ARM_HAVE_MPU_UNIFIED
+ select ARMV7M_CMNVECTOR
select ARMV7M_HAVE_STACKCHECK
---help---
STMicro STM32 architectures (ARM Cortex-M4).
@@ -302,6 +302,10 @@ config ARCH_CORTEXM0
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_RESET
+config ARCH_CORTEXM23
+ bool
+ default n
+
config ARCH_CORTEXM3
bool
default n
@@ -310,6 +314,10 @@ config ARCH_CORTEXM3
select ARCH_HAVE_HIPRI_INTERRUPT
select ARCH_HAVE_RESET
+config ARCH_CORTEXM33
+ bool
+ default n
+
config ARCH_CORTEXM4
bool
default n
@@ -325,6 +333,7 @@ config ARCH_CORTEXM7
select ARCH_HAVE_IRQPRIO
select ARCH_HAVE_RAMVECTORS
select ARCH_HAVE_HIPRI_INTERRUPT
+ select ARCH_HAVE_RESET
select ARCH_HAVE_COHERENT_DCACHE if ELF || MODULE
config ARCH_CORTEXA5
@@ -399,7 +408,6 @@ config ARCH_CHIP
string
default "a1x" if ARCH_CHIP_A1X
default "c5471" if ARCH_CHIP_C5471
- default "calypso" if ARCH_CHIP_CALYPSO
default "dm320" if ARCH_CHIP_DM320
default "efm32" if ARCH_CHIP_EFM32
default "imx1" if ARCH_CHIP_IMX1
@@ -588,7 +596,7 @@ config ARCH_ROMPGTABLE
config DEBUG_HARDFAULT
bool "Verbose Hard-Fault Debug"
default n
- depends on DEBUG && (ARCH_CORTEXM3 || ARCH_CORTEXM4 || ARCH_CORTEXM7)
+ depends on DEBUG_FEATURES && (ARCH_CORTEXM3 || ARCH_CORTEXM4 || ARCH_CORTEXM7)
---help---
Enables verbose debug output when a hard fault is occurs. This verbose
output is sometimes helpful when debugging difficult hard fault problems,
@@ -615,9 +623,6 @@ endif
if ARCH_CHIP_C5471
source arch/arm/src/c5471/Kconfig
endif
-if ARCH_CHIP_CALYPSO
-source arch/arm/src/calypso/Kconfig
-endif
if ARCH_CHIP_DM320
source arch/arm/src/dm320/Kconfig
endif
diff --git a/arch/rgmp/src/arm/sigentry.S b/arch/arm/include/arm/spinlock.h
similarity index 80%
rename from arch/rgmp/src/arm/sigentry.S
rename to arch/arm/include/arm/spinlock.h
index 1e413450bf6573c61f7215f23eb366fe0c38fa06..ee3db052cf0002db9f13b0b8a547196ec97e2aad 100644
--- a/arch/rgmp/src/arm/sigentry.S
+++ b/arch/arm/include/arm/spinlock.h
@@ -1,12 +1,8 @@
/****************************************************************************
- * arch/rgmp/src/arm/sigentry.S
+ * arch/arm/include/armv7-a/spinlock.h
*
- * Copyright (C) 2011 Yu Qiang. All rights reserved.
- * Author: Yu Qiang
- *
- * This file is a part of NuttX:
- *
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -37,13 +33,7 @@
*
****************************************************************************/
- .globl up_sigentry
-up_sigentry:
- sub sp, sp, #68 @ 68 is the size of Trapframe
- mov r0, sp
- bl up_sigdeliver
- add sp, sp, #4 @ skip current_task
- pop {r0-r12, lr}
- rfefd sp!
+#ifndef __ARCH_ARM_INCLUDE_ARM_SPINLOCK_H
+#define __ARCH_ARM_INCLUDE_ARM_SPINLOCK_H
-
\ No newline at end of file
+#endif /* __ARCH_ARM_INCLUDE_ARM_SPINLOCK_H */
diff --git a/arch/rgmp/include/arm/arch/subarch/arch.h b/arch/arm/include/armv6-m/spinlock.h
similarity index 78%
rename from arch/rgmp/include/arm/arch/subarch/arch.h
rename to arch/arm/include/armv6-m/spinlock.h
index e5f3fff10f93ad6892b0c744442d0956407c60cd..c1d154b37001652e6624c535d113ed7519cce219 100644
--- a/arch/rgmp/include/arm/arch/subarch/arch.h
+++ b/arch/arm/include/armv6-m/spinlock.h
@@ -1,12 +1,8 @@
/****************************************************************************
- * arch/rgmp/include/arm/arch/subarch/arch.h
+ * arch/arm/include/armv7-a/spinlock.h
*
- * Copyright (C) 2011 Yu Qiang. All rights reserved.
- * Author: Yu Qiang
- *
- * This file is a part of NuttX:
- *
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -37,22 +33,7 @@
*
****************************************************************************/
-#ifndef __RGMP_ARCH_SUBARCH_ARCH_H
-#define __RGMP_ARCH_SUBARCH_ARCH_H
-
-#ifndef __ASSEMBLY__
-
-
-static inline void up_mdelay(uint32_t msec)
-{
-
-}
-
-static inline void up_udelay(uint32_t usec)
-{
-
-}
-
-#endif /* !__ASSEMBLY__ */
+#ifndef __ARCH_ARM_INCLUDE_ARMV6_M_SPINLOCK_H
+#define __ARCH_ARM_INCLUDE_ARMV6_M_SPINLOCK_H
-#endif
+#endif /* __ARCH_ARM_INCLUDE_ARMV6_M_SPINLOCK_H */
diff --git a/arch/rgmp/src/x86/sigentry.S b/arch/arm/include/armv7-a/spinlock.h
similarity index 75%
rename from arch/rgmp/src/x86/sigentry.S
rename to arch/arm/include/armv7-a/spinlock.h
index 77214e8114a58a94fb22ba469d558e049b3e9245..764a96ecef3104a8f27e6dde4c816cd7afb0864f 100644
--- a/arch/rgmp/src/x86/sigentry.S
+++ b/arch/arm/include/armv7-a/spinlock.h
@@ -1,12 +1,8 @@
/****************************************************************************
- * arch/rgmp/src/x86/sigentry.S
+ * arch/arm/include/armv7-a/spinlock.h
*
- * Copyright (C) 2011 Yu Qiang. All rights reserved.
- * Author: Yu Qiang
- *
- * This file is a part of NuttX:
- *
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -37,19 +33,7 @@
*
****************************************************************************/
- .globl up_sigentry
-up_sigentry:
- subl $172, %esp # 172 is the size of Trapframe without cross ring part
- pushl %esp
- movl %esp, %eax
- call up_sigdeliver
- addl $8, %esp # skip parameter and tf_curregs
- frstor 0(%esp)
- addl $108, %esp
- popal
- popl %es
- popl %ds
- addl $0x8, %esp # trapno and errcode
- iret
+#ifndef __ARCH_ARM_INCLUDE_ARMV7_A_SPINLOCK_H
+#define __ARCH_ARM_INCLUDE_ARMV7_A_SPINLOCK_H
-
\ No newline at end of file
+#endif /* __ARCH_ARM_INCLUDE_ARMV7_A_SPINLOCK_H */
diff --git a/arch/arm/include/armv7-m/spinlock.h b/arch/arm/include/armv7-m/spinlock.h
new file mode 100644
index 0000000000000000000000000000000000000000..79a06b4173f94731d24c8379f0999dc9e07c1183
--- /dev/null
+++ b/arch/arm/include/armv7-m/spinlock.h
@@ -0,0 +1,39 @@
+/****************************************************************************
+ * arch/arm/include/armv7-a/spinlock.h
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_INCLUDE_ARMV7_M_SPINLOCK_H
+#define __ARCH_ARM_INCLUDE_ARMV7_M_SPINLOCK_H
+
+#endif /* __ARCH_ARM_INCLUDE_ARMV7_M_SPINLOCK_H */
diff --git a/arch/arm/include/armv7-r/spinlock.h b/arch/arm/include/armv7-r/spinlock.h
new file mode 100644
index 0000000000000000000000000000000000000000..ab7900fa7337d90291c62b4cbfd716559e2a474c
--- /dev/null
+++ b/arch/arm/include/armv7-r/spinlock.h
@@ -0,0 +1,39 @@
+/****************************************************************************
+ * arch/arm/include/armv7-r/spinlock.h
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_INCLUDE_ARMV7_R_SPINLOCK_H
+#define __ARCH_ARM_INCLUDE_ARMV7_R_SPINLOCK_H
+
+#endif /* __ARCH_ARM_INCLUDE_ARMV7_R_SPINLOCK_H */
diff --git a/arch/arm/include/calypso/clock.h b/arch/arm/include/calypso/clock.h
deleted file mode 100644
index abcfde1d449d947a14904a36f100e5bfea0b95a8..0000000000000000000000000000000000000000
--- a/arch/arm/include/calypso/clock.h
+++ /dev/null
@@ -1,67 +0,0 @@
-#ifndef _CALYPSO_CLK_H
-#define _CALYPSO_CLK_H
-
-#include
-
-#define CALYPSO_PLL26_52_MHZ ((2 << 8) | 0)
-#define CALYPSO_PLL26_86_7_MHZ ((10 << 8) | 2)
-#define CALYPSO_PLL26_87_MHZ ((3 << 8) | 0)
-#define CALYPSO_PLL13_104_MHZ ((8 << 8) | 0)
-
-enum mclk_div {
- _ARM_MCLK_DIV_1 = 0,
- ARM_MCLK_DIV_1 = 1,
- ARM_MCLK_DIV_2 = 2,
- ARM_MCLK_DIV_3 = 3,
- ARM_MCLK_DIV_4 = 4,
- ARM_MCLK_DIV_5 = 5,
- ARM_MCLK_DIV_6 = 6,
- ARM_MCLK_DIV_7 = 7,
- ARM_MCLK_DIV_1_5 = 0x80 | 1,
- ARM_MCLK_DIV_2_5 = 0x80 | 2,
-};
-
-void calypso_clock_set(uint8_t vtcxo_div2, uint16_t inp, enum mclk_div mclk_div);
-void calypso_pll_set(uint16_t inp);
-void calypso_clk_dump(void);
-
-/* CNTL_RST */
-enum calypso_rst {
- RESET_DSP = (1 << 1),
- RESET_EXT = (1 << 2),
- RESET_WDOG = (1 << 3),
-};
-
-void calypso_reset_set(enum calypso_rst calypso_rst, int active);
-int calypso_reset_get(enum calypso_rst);
-
-enum calypso_bank {
- CALYPSO_nCS0 = 0,
- CALYPSO_nCS1 = 2,
- CALYPSO_nCS2 = 4,
- CALYPSO_nCS3 = 6,
- CALYPSO_nCS7 = 8,
- CALYPSO_CS4 = 0xa,
- CALYPSO_nCS6 = 0xc,
-};
-
-enum calypso_mem_width {
- CALYPSO_MEM_8bit = 0,
- CALYPSO_MEM_16bit = 1,
- CALYPSO_MEM_32bit = 2,
-};
-
-void calypso_mem_cfg(enum calypso_bank bank, uint8_t ws,
- enum calypso_mem_width width, int we);
-
-/* Enable or disable the internal bootrom mapped to 0x0000'0000 */
-void calypso_bootrom(int enable);
-
-/* Enable or disable the debug unit */
-void calypso_debugunit(int enable);
-
-/* configure the RHEA bus bridge[s] */
-void calypso_rhea_cfg(uint8_t fac0, uint8_t fac1, uint8_t timeout,
- uint8_t ws_h, uint8_t ws_l, uint8_t w_en0, uint8_t w_en1);
-
-#endif /* _CALYPSO_CLK_H */
diff --git a/arch/arm/include/calypso/debug.h b/arch/arm/include/calypso/debug.h
deleted file mode 100644
index 8c7b9aabfbdd132ae439b765f0d4318ec31c4144..0000000000000000000000000000000000000000
--- a/arch/arm/include/calypso/debug.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef _DEBUG_H
-#define _DEBUG_H
-
-#ifndef ARRAY_SIZE
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-#endif
-
-/*
- * Check at compile time that something is of a particular type.
- * Always evaluates to 1 so you may use it easily in comparisons.
- */
-#define typecheck(type,x) \
-({ type __dummy; \
- typeof(x) __dummy2; \
- (void)(&__dummy == &__dummy2); \
- 1; \
-})
-
-#ifdef DEBUG
-#define dputchar(x) putchar(x)
-#define dputs(x) puts(x)
-#define dphex(x,y) phex(x,y)
-#define printd(x, ...) printf(x, ##__VA_ARGS__)
-#else
-#define dputchar(x)
-#define dputs(x)
-#define dphex(x,y)
-#define printd(x, args ...)
-#endif
-
-#endif /* _DEBUG_H */
diff --git a/arch/arm/include/calypso/defines.h b/arch/arm/include/calypso/defines.h
deleted file mode 100644
index 3c8732f92f8c086b825e70d7d51c980e41a79e40..0000000000000000000000000000000000000000
--- a/arch/arm/include/calypso/defines.h
+++ /dev/null
@@ -1,18 +0,0 @@
-
-#ifndef _DEFINES_H
-#define _DEFINES_H
-
-#define __attribute_const__ __attribute__((__const__))
-
-/* type properties */
-#define __packed __attribute__((packed))
-#define __aligned(alignment) __attribute__((aligned(alignment)))
-#define __unused __attribute__((unused))
-
-/* linkage */
-#define __section(name) __attribute__((section(name)))
-
-/* force placement in zero-waitstate memory */
-#define __ramtext __section(".ramtext")
-
-#endif /* !_DEFINES_H */
diff --git a/arch/arm/include/calypso/irq.h b/arch/arm/include/calypso/irq.h
deleted file mode 100644
index baea3de5a3f690f6b2a6411e6adfb12f03290325..0000000000000000000000000000000000000000
--- a/arch/arm/include/calypso/irq.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/****************************************************************************
- * arch/arm/include/calypso/irq.h
- * Driver for Calypso IRQ controller
- *
- * (C) 2010 by Harald Welte
- * (C) 2011 by Stefan Richter
- *
- * This source code is derivated from Osmocom-BB project and was
- * relicensed as BSD with permission from original authors.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-#ifndef __INCLUDE_NUTTX_IRQ_H
-#error "This file should never be included directly! Use "
-#endif
-
-#ifndef _CALYPSO_IRQ_H
-#define _CALYPSO_IRQ_H
-
-#ifndef __ASSEMBLY__
-
-enum irq_nr {
- IRQ_WATCHDOG = 0,
- IRQ_TIMER1 = 1,
- IRQ_TIMER2 = 2,
- IRQ_TSP_RX = 3,
- IRQ_TPU_FRAME = 4,
- IRQ_TPU_PAGE = 5,
- IRQ_SIMCARD = 6,
- IRQ_UART_MODEM = 7,
- IRQ_KEYPAD_GPIO = 8,
- IRQ_RTC_TIMER = 9,
- IRQ_RTC_ALARM_I2C = 10,
- IRQ_ULPD_GAUGING = 11,
- IRQ_EXTERNAL = 12,
- IRQ_SPI = 13,
- IRQ_DMA = 14,
- IRQ_API = 15,
- IRQ_SIM_DETECT = 16,
- IRQ_EXTERNAL_FIQ = 17,
- IRQ_UART_IRDA = 18,
- IRQ_ULPD_GSM_TIMER = 19,
- IRQ_GEA = 20,
- _NR_IRQS
-};
-
-#endif /* __ASSEMBLY__ */
-
-/* Don't use _NR_IRQS!!! Won't work in preprocessor... */
-#define NR_IRQS 21
-
-#define IRQ_SYSTIMER IRQ_TIMER2
-
-#endif /* _CALYPSO_IRQ_H */
diff --git a/arch/arm/include/calypso/memory.h b/arch/arm/include/calypso/memory.h
deleted file mode 100644
index b0a0490cec1c3f8d44714ef9826fed115163be02..0000000000000000000000000000000000000000
--- a/arch/arm/include/calypso/memory.h
+++ /dev/null
@@ -1,28 +0,0 @@
-#ifndef _MEMORY_H
-#define _MEMORY_H
-
-#define __arch_getb(a) (*(volatile unsigned char *)(a))
-#define __arch_getw(a) (*(volatile unsigned short *)(a))
-#define __arch_getl(a) (*(volatile unsigned int *)(a))
-
-#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v))
-#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v))
-#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v))
-
-#define __raw_writeb(v,a) __arch_putb(v,a)
-#define __raw_writew(v,a) __arch_putw(v,a)
-#define __raw_writel(v,a) __arch_putl(v,a)
-
-#define __raw_readb(a) __arch_getb(a)
-#define __raw_readw(a) __arch_getw(a)
-#define __raw_readl(a) __arch_getl(a)
-
-#define writeb(v,a) __arch_putb(v,a)
-#define writew(v,a) __arch_putw(v,a)
-#define writel(v,a) __arch_putl(v,a)
-
-#define readb(a) __arch_getb(a)
-#define readw(a) __arch_getw(a)
-#define readl(a) __arch_getl(a)
-
-#endif /* _MEMORY_H */
diff --git a/arch/arm/include/calypso/timer.h b/arch/arm/include/calypso/timer.h
deleted file mode 100644
index 694e4ebc92efb1d4031508354f4366f9079df243..0000000000000000000000000000000000000000
--- a/arch/arm/include/calypso/timer.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef _CAL_TIMER_H
-#define _CAL_TIMER_H
-
-/* Enable or Disable a timer */
-void hwtimer_enable(int num, int on);
-
-/* Configure pre-scaler and if timer is auto-reload */
-void hwtimer_config(int num, uint8_t pre_scale, int auto_reload);
-
-/* Load a timer with the given value */
-void hwtimer_load(int num, uint16_t val);
-
-/* Read the current timer value */
-uint16_t hwtimer_read(int num);
-
-/* Enable or disable the watchdog */
-void wdog_enable(int on);
-
-/* Reset cpu using watchdog */
-void wdog_reset(void);
-
-/* power up the timers */
-void hwtimer_init(void);
-
-#endif /* _CAL_TIMER_H */
diff --git a/arch/arm/include/calypso/uwire.h b/arch/arm/include/calypso/uwire.h
deleted file mode 100644
index 19a277bccb5754cb938ce3593e8abe5492936068..0000000000000000000000000000000000000000
--- a/arch/arm/include/calypso/uwire.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _CALYPSO_UWIRE_H
-#define _CALYPSO_UWIRE_H
-void uwire_init(void);
-int uwire_xfer(int cs, int bitlen, const void *dout, void *din);
-#endif
-
diff --git a/arch/arm/include/efm32/irq.h b/arch/arm/include/efm32/irq.h
index 7bd0449d621d225ad6408ea8d6422c28f71e4781..a5f2eff8e47850dc2826a75f7887f0bbe7461022 100644
--- a/arch/arm/include/efm32/irq.h
+++ b/arch/arm/include/efm32/irq.h
@@ -60,7 +60,7 @@
/* Processor Exceptions (vectors 0-15) */
-#define EFM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+#define EFM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define EFM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
diff --git a/arch/arm/include/inttypes.h b/arch/arm/include/inttypes.h
new file mode 100644
index 0000000000000000000000000000000000000000..280d4a5ecaf93f67556b3aca5f7924a98edc8262
--- /dev/null
+++ b/arch/arm/include/inttypes.h
@@ -0,0 +1,245 @@
+/****************************************************************************
+ * arch/arm/include/inttypes.h
+ *
+ * Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
+ * Author: Paul Alexander Patience
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_INCLUDE_INTTYPES_H
+#define __ARCH_ARM_INCLUDE_INTTYPES_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define PRId8 "d"
+#define PRId16 "d"
+#define PRId32 "d"
+#define PRId64 "lld"
+
+#define PRIdLEAST8 "d"
+#define PRIdLEAST16 "d"
+#define PRIdLEAST32 "d"
+#define PRIdLEAST64 "lld"
+
+#define PRIdFAST8 "d"
+#define PRIdFAST16 "d"
+#define PRIdFAST32 "d"
+#define PRIdFAST64 "lld"
+
+#define PRIdMAX "lld"
+#define PRIdPTR "d"
+
+#define PRIi8 "i"
+#define PRIi16 "i"
+#define PRIi32 "i"
+#define PRIi64 "lli"
+
+#define PRIiLEAST8 "i"
+#define PRIiLEAST16 "i"
+#define PRIiLEAST32 "i"
+#define PRIiLEAST64 "lli"
+
+#define PRIiFAST8 "i"
+#define PRIiFAST16 "i"
+#define PRIiFAST32 "i"
+#define PRIiFAST64 "lli"
+
+#define PRIiMAX "lli"
+#define PRIiPTR "i"
+
+#define PRIo8 "o"
+#define PRIo16 "o"
+#define PRIo32 "o"
+#define PRIo64 "llo"
+
+#define PRIoLEAST8 "o"
+#define PRIoLEAST16 "o"
+#define PRIoLEAST32 "o"
+#define PRIoLEAST64 "llo"
+
+#define PRIoFAST8 "o"
+#define PRIoFAST16 "o"
+#define PRIoFAST32 "o"
+#define PRIoFAST64 "llo"
+
+#define PRIoMAX "llo"
+#define PRIoPTR "o"
+
+#define PRIu8 "u"
+#define PRIu16 "u"
+#define PRIu32 "u"
+#define PRIu64 "llu"
+
+#define PRIuLEAST8 "u"
+#define PRIuLEAST16 "u"
+#define PRIuLEAST32 "u"
+#define PRIuLEAST64 "llu"
+
+#define PRIuFAST8 "u"
+#define PRIuFAST16 "u"
+#define PRIuFAST32 "u"
+#define PRIuFAST64 "llu"
+
+#define PRIuMAX "llu"
+#define PRIuPTR "u"
+
+#define PRIx8 "x"
+#define PRIx16 "x"
+#define PRIx32 "x"
+#define PRIx64 "llx"
+
+#define PRIxLEAST8 "x"
+#define PRIxLEAST16 "x"
+#define PRIxLEAST32 "x"
+#define PRIxLEAST64 "llx"
+
+#define PRIxFAST8 "x"
+#define PRIxFAST16 "x"
+#define PRIxFAST32 "x"
+#define PRIxFAST64 "llx"
+
+#define PRIxMAX "llx"
+#define PRIxPTR "x"
+
+#define PRIX8 "X"
+#define PRIX16 "X"
+#define PRIX32 "X"
+#define PRIX64 "llX"
+
+#define PRIXLEAST8 "X"
+#define PRIXLEAST16 "X"
+#define PRIXLEAST32 "X"
+#define PRIXLEAST64 "llX"
+
+#define PRIXFAST8 "X"
+#define PRIXFAST16 "X"
+#define PRIXFAST32 "X"
+#define PRIXFAST64 "llX"
+
+#define PRIXMAX "llX"
+#define PRIXPTR "X"
+
+#define SCNd8 "hhd"
+#define SCNd16 "hd"
+#define SCNd32 "d"
+#define SCNd64 "lld"
+
+#define SCNdLEAST8 "hhd"
+#define SCNdLEAST16 "hd"
+#define SCNdLEAST32 "d"
+#define SCNdLEAST64 "lld"
+
+#define SCNdFAST8 "hhd"
+#define SCNdFAST16 "hd"
+#define SCNdFAST32 "d"
+#define SCNdFAST64 "lld"
+
+#define SCNdMAX "lld"
+#define SCNdPTR "d"
+
+#define SCNi8 "hhi"
+#define SCNi16 "hi"
+#define SCNi32 "i"
+#define SCNi64 "lli"
+
+#define SCNiLEAST8 "hhi"
+#define SCNiLEAST16 "hi"
+#define SCNiLEAST32 "i"
+#define SCNiLEAST64 "lli"
+
+#define SCNiFAST8 "hhi"
+#define SCNiFAST16 "hi"
+#define SCNiFAST32 "i"
+#define SCNiFAST64 "lli"
+
+#define SCNiMAX "lli"
+#define SCNiPTR "i"
+
+#define SCNo8 "hho"
+#define SCNo16 "ho"
+#define SCNo32 "o"
+#define SCNo64 "llo"
+
+#define SCNoLEAST8 "hho"
+#define SCNoLEAST16 "ho"
+#define SCNoLEAST32 "o"
+#define SCNoLEAST64 "llo"
+
+#define SCNoFAST8 "hho"
+#define SCNoFAST16 "ho"
+#define SCNoFAST32 "o"
+#define SCNoFAST64 "llo"
+
+#define SCNoMAX "llo"
+#define SCNoPTR "o"
+
+#define SCNu8 "hhu"
+#define SCNu16 "hu"
+#define SCNu32 "u"
+#define SCNu64 "llu"
+
+#define SCNuLEAST8 "hhu"
+#define SCNuLEAST16 "hu"
+#define SCNuLEAST32 "u"
+#define SCNuLEAST64 "llu"
+
+#define SCNuFAST8 "hhu"
+#define SCNuFAST16 "hu"
+#define SCNuFAST32 "u"
+#define SCNuFAST64 "llu"
+
+#define SCNuMAX "llu"
+#define SCNuPTR "u"
+
+#define SCNx8 "hhx"
+#define SCNx16 "hx"
+#define SCNx32 "x"
+#define SCNx64 "llx"
+
+#define SCNxLEAST8 "hhx"
+#define SCNxLEAST16 "hx"
+#define SCNxLEAST32 "x"
+#define SCNxLEAST64 "llx"
+
+#define SCNxFAST8 "hhx"
+#define SCNxFAST16 "hx"
+#define SCNxFAST32 "x"
+#define SCNxFAST64 "llx"
+
+#define SCNxMAX "llx"
+#define SCNxPTR "x"
+
+#endif /* __ARCH_ARM_INCLUDE_INTTYPES_H */
diff --git a/arch/arm/include/kinetis/chip.h b/arch/arm/include/kinetis/chip.h
index dd8582e564fc8e78472ed6b53c9e4eaf200d10a1..5c6cc76a0822deb212292e76d37e72dc737e7d55 100644
--- a/arch/arm/include/kinetis/chip.h
+++ b/arch/arm/include/kinetis/chip.h
@@ -1,8 +1,9 @@
/************************************************************************************
* arch/arm/include/kinetis/chip.h
*
- * Copyright (C) 2011, 2013, 2015 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt
+ * Copyright (C) 2011, 2013, 2015-2017 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt
+ * David Sidrane
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -41,6 +42,9 @@
************************************************************************************/
#include
+#include
+#include
+#include
/************************************************************************************
* Pre-processor Definitions
@@ -69,9 +73,11 @@
defined(CONFIG_ARCH_CHIP_MK20DN128VLH5) || \
defined(CONFIG_ARCH_CHIP_MK20DX128VLH5)
-# define KINETIS_K20 1 /* Kinetics K20 family */
-# undef KINETIS_K40 /* Not Kinetics K40 family */
+# define KINETIS_K20 1 /* Kinetis K20 family */
+# undef KINETIS_K40 /* Not Kinetis K40 family */
# undef KINETIS_K60 /* Not Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
+# undef KINETIS_K66 /* Not Kinetis K66 family */
#if defined(CONFIG_ARCH_CHIP_MK20DN32VLH5)
# define KINETIS_FLASH_SIZE (64*1024) /* 32Kb */
@@ -150,103 +156,108 @@
defined(CONFIG_ARCH_CHIP_MK20DX128VLH7) || \
defined(CONFIG_ARCH_CHIP_MK20DX256VLH7)
-# define KINETIS_K20 1 /* Kinetics K20 family */
-# undef KINETIS_K40 /* Not Kinetics K40 family */
-# undef KINETIS_K60 /* Not Kinetis K60 family */
+# define KINETIS_K20 1 /* Kinetis K20 family */
+# undef KINETIS_K40 /* Not Kinetis K40 family */
+# undef KINETIS_K60 /* Not Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
+# undef KINETIS_K66 /* Not Kinetis K66 family */
#if defined(CONFIG_ARCH_CHIP_MK20DX64VLH7)
-# define KINETIS_FLASH_SIZE (64*1024) /* 64Kb */
-# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */
-# define KINETIS_SRAM_SIZE (16*1024) /* 16Kb */
+# define KINETIS_FLASH_SIZE (64*1024) /* 64Kb */
+# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */
+# define KINETIS_SRAM_SIZE (16*1024) /* 16Kb */
#elif defined(CONFIG_ARCH_CHIP_MK20DX128VLH7)
-# define KINETIS_FLASH_SIZE (128*1024) /* 128Kb */
-# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */
-# define KINETIS_SRAM_SIZE (32*1024) /* 32Kb */
+# define KINETIS_FLASH_SIZE (128*1024) /* 128Kb */
+# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */
+# define KINETIS_SRAM_SIZE (32*1024) /* 32Kb */
#else /* if defined(CONFIG_ARCH_CHIP_MK20DX256VLH7) */
-# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
-# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */
-# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */
+# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
+# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */
+# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */
#endif
-# undef KINETIS_MPU /* No memory protection unit */
-# undef KINETIS_EXTBUS /* No external bus interface */
-# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
-# undef KINETIS_NENET /* No Ethernet controller */
-# define KINETIS_NUSBHOST 1 /* One USB host controller */
-# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
-# define KINETIS_NUSBDEV 1 /* One USB device controller */
-# undef KINETIS_NSDHC /* No SD host controller */
-# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */
-# define KINETIS_NI2C 2 /* Two I2C modules */
-# undef KINETIS_NISO7816 /* No UART with ISO-786 */
-# define KINETIS_NUART 3 /* Three UARTs */
-# define KINETIS_NSPI 1 /* One SPI module */
-# define KINETIS_NCAN 1 /* Two CAN controller */
-# define KINETIS_NI2S 1 /* One I2S module */
-# undef KINETIS_NSLCD /* No segment LCD interface */
-# define KINETIS_NADC16 2 /* Two 16-bit ADC */
-# undef KINETIS_NADC12 /* No 12-channel ADC */
-# undef KINETIS_NADC13 /* No 13-channel ADC */
-# undef KINETIS_NADC15 /* No 15-channel ADC */
-# undef KINETIS_NADC18 /* No 18-channel ADC */
-# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */
-# define KINETIS_NCMP 3 /* Three analog comparators */
-# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
-# define KINETIS_NDAC12 1 /* One 12-bit DAC */
-# define KINETIS_NVREF 1 /* Voltage reference */
-# define KINETIS_NTIMERS12 2 /* Two 12 channel timers */
-# undef KINETIS_NTIMERS20 /* No 20 channel timers */
-# undef KINETIS_NRNG /* No random number generator */
-# define KINETIS_NRTC 1 /* Real time clock */
-# undef KINETIS_NMMCAU /* No hardware encryption */
-# undef KINETIS_NTAMPER /* No tamper detect */
-# undef KINETIS_NCRC /* No CRC */
+# undef KINETIS_MPU /* No memory protection unit */
+# undef KINETIS_EXTBUS /* No external bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# undef KINETIS_NENET /* No Ethernet controller */
+# define KINETIS_NUSBHOST 1 /* One USB host controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# undef KINETIS_NSDHC /* No SD host controller */
+# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */
+# define KINETIS_NI2C 2 /* Two I2C modules */
+# undef KINETIS_NISO7816 /* No UART with ISO-786 */
+# define KINETIS_NUART 3 /* Three UARTs */
+# define KINETIS_NSPI 1 /* One SPI module */
+# define KINETIS_NCAN 1 /* Two CAN controller */
+# define KINETIS_NI2S 1 /* One I2S module */
+# undef KINETIS_NSLCD /* No segment LCD interface */
+# define KINETIS_NADC16 2 /* Two 16-bit ADC */
+# undef KINETIS_NADC12 /* No 12-channel ADC */
+# undef KINETIS_NADC13 /* No 13-channel ADC */
+# undef KINETIS_NADC15 /* No 15-channel ADC */
+# undef KINETIS_NADC18 /* No 18-channel ADC */
+# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
+# define KINETIS_NDAC12 1 /* One 12-bit DAC */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# define KINETIS_NTIMERS12 2 /* Two 12 channel timers */
+# undef KINETIS_NTIMERS20 /* No 20 channel timers */
+# undef KINETIS_NRNG /* No random number generator */
+# define KINETIS_NRTC 1 /* Real time clock */
+# undef KINETIS_NMMCAU /* No hardware encryption */
+# undef KINETIS_NTAMPER /* No tamper detect */
+# undef KINETIS_NCRC /* No CRC */
#elif defined(CONFIG_ARCH_CHIP_MK40X64VFX50) || defined(CONFIG_ARCH_CHIP_MK40X64VLH50) || \
defined(CONFIG_ARCH_CHIP_MK40X64VLK50) || defined(CONFIG_ARCH_CHIP_MK40X64VMB50)
-# undef KINETIS_K20 /* Not Kinetis K20 family */
-# define KINETIS_K40 1 /* Kinetics K40 family */
-# undef KINETIS_K60 /* Not Kinetis K60 family */
-# define KINETIS_FLASH_SIZE (64*1024) /* 64Kb */
-# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */
-# define KINETIS_SRAM_SIZE (16*1024) /* 16Kb */
-# undef KINETIS_MPU /* No memory protection unit */
-# undef KINETIS_EXTBUS /* No external bus interface */
-# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
-# undef KINETIS_NENET /* No Ethernet controller */
-# define KINETIS_NUSBHOST 1 /* One USB host controller */
-# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
-# define KINETIS_NUSBDEV 1 /* One USB device controller */
-# undef KINETIS_NSDHC /* No SD host controller */
-# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */
-# define KINETIS_NI2C 2 /* Two I2C modules */
-# undef KINETIS_NISO7816 /* No UART with ISO-786 */
-# define KINETIS_NUART 6 /* Six UARTs */
-# define KINETIS_NSPI 3 /* Three SPI modules */
+# undef KINETIS_K20 /* Not Kinetis K20 family */
+# define KINETIS_K40 1 /* Kinetis K40 family */
+# undef KINETIS_K60 /* Not Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
+# undef KINETIS_K66 /* Not Kinetis K66 family */
+
+# define KINETIS_FLASH_SIZE (64*1024) /* 64Kb */
+# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */
+# define KINETIS_SRAM_SIZE (16*1024) /* 16Kb */
+# undef KINETIS_MPU /* No memory protection unit */
+# undef KINETIS_EXTBUS /* No external bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# undef KINETIS_NENET /* No Ethernet controller */
+# define KINETIS_NUSBHOST 1 /* One USB host controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# undef KINETIS_NSDHC /* No SD host controller */
+# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */
+# define KINETIS_NI2C 2 /* Two I2C modules */
+# undef KINETIS_NISO7816 /* No UART with ISO-786 */
+# define KINETIS_NUART 6 /* Six UARTs */
+# define KINETIS_NSPI 3 /* Three SPI modules */
# if defined(CONFIG_ARCH_CHIP_MK40X64VLK50) || defined(CONFIG_ARCH_CHIP_MK40X64VMB50)
-# define KINETIS_NCAN 2 /* Two CAN controllers */
+# define KINETIS_NCAN 2 /* Two CAN controllers */
# else
-# undef KINETIS_NCAN /* No CAN in 64-pin chips */
+# undef KINETIS_NCAN /* No CAN in 64-pin chips */
# endif
-# define KINETIS_NI2S 1 /* One I2S module */
-# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 25x8/29x4) */
-# define KINETIS_NADC16 4 /* Four 16-bit ADC */
-# undef KINETIS_NADC12 /* No 12-channel ADC */
-# undef KINETIS_NADC13 /* No 13-channel ADC */
-# undef KINETIS_NADC15 /* No 15-channel ADC */
-# undef KINETIS_NADC18 /* No 18-channel ADC */
-# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */
-# define KINETIS_NCMP 3 /* Three analog comparators */
-# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
-# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
-# define KINETIS_NVREF 1 /* Voltage reference */
-# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
-# undef KINETIS_NTIMERS20 /* No 20 channel timers */
-# undef KINETIS_NRNG /* No random number generator */
-# define KINETIS_NRTC 1 /* Real time clock */
-# undef KINETIS_NMMCAU /* No hardware encryption */
-# undef KINETIS_NTAMPER /* No tamper detect */
-# define KINETIS_NCRC 1 /* CRC */
+# define KINETIS_NI2S 1 /* One I2S module */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 25x8/29x4) */
+# define KINETIS_NADC16 4 /* Four 16-bit ADC */
+# undef KINETIS_NADC12 /* No 12-channel ADC */
+# undef KINETIS_NADC13 /* No 13-channel ADC */
+# undef KINETIS_NADC15 /* No 15-channel ADC */
+# undef KINETIS_NADC18 /* No 18-channel ADC */
+# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
+# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
+# undef KINETIS_NTIMERS20 /* No 20 channel timers */
+# undef KINETIS_NRNG /* No random number generator */
+# define KINETIS_NRTC 1 /* Real time clock */
+# undef KINETIS_NMMCAU /* No hardware encryption */
+# undef KINETIS_NTAMPER /* No tamper detect */
+# define KINETIS_NCRC 1 /* CRC */
#elif defined(CONFIG_ARCH_CHIP_MK40X128VFX50) || defined(CONFIG_ARCH_CHIP_MK40X128VLH50) || \
defined(CONFIG_ARCH_CHIP_MK40X128VLK50) || defined(CONFIG_ARCH_CHIP_MK40X128VMB50) || \
@@ -254,742 +265,1185 @@
defined(CONFIG_ARCH_CHIP_MK40X128VFX72) || defined(CONFIG_ARCH_CHIP_MK40X128VLH72) || \
defined(CONFIG_ARCH_CHIP_MK40X128VLK72) || defined(CONFIG_ARCH_CHIP_MK40X128VMB72) || \
defined(CONFIG_ARCH_CHIP_MK40X128VLL72) || defined(CONFIG_ARCH_CHIP_MK40X128VML72)
-# undef KINETIS_K20 /* Not Kinetis K20 family */
-# define KINETIS_K40 1 /* Kinetics K40 family */
-# undef KINETIS_K60 /* Not Kinetis K60 family */
-# define KINETIS_FLASH_SIZE (128*1024) /* 128Kb */
-# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */
-# define KINETIS_SRAM_SIZE (32*1024) /* 32Kb */
-# undef KINETIS_MPU /* No memory protection unit */
-# undef KINETIS_EXTBUS /* No external bus interface */
-# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
-# undef KINETIS_NENET /* No Ethernet controller */
-# define KINETIS_NUSBHOST 1 /* One USB host controller */
-# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
-# define KINETIS_NUSBDEV 1 /* One USB device controller */
-# undef KINETIS_NSDHC /* No SD host controller */
-# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */
-# define KINETIS_NI2C 2 /* Two I2C modules */
-# undef KINETIS_NISO7816 /* No UART with ISO-786 */
-# define KINETIS_NUART 6 /* Six UARTs */
-# define KINETIS_NSPI 3 /* Three SPI modules */
-# define KINETIS_NCAN 2 /* Two CAN controllers */
-# define KINETIS_NI2S 1 /* One I2S module */
-# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
-# define KINETIS_NADC16 4 /* Four 16-bit ADC */
-# undef KINETIS_NADC12 /* No 12-channel ADC */
-# undef KINETIS_NADC13 /* No 13-channel ADC */
-# undef KINETIS_NADC15 /* No 15-channel ADC */
-# undef KINETIS_NADC18 /* No 18-channel ADC */
-# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */
-# define KINETIS_NCMP 3 /* Three analog comparators */
-# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
-# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
-# define KINETIS_NVREF 1 /* Voltage reference */
-# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
-# undef KINETIS_NTIMERS20 /* No 20 channel timers */
-# define KINETIS_NRTC 1 /* Real time clock */
-# undef KINETIS_NRNG /* No random number generator */
-# undef KINETIS_NMMCAU /* No hardware encryption */
-# undef KINETIS_NTAMPER /* No tamper detect */
-# define KINETIS_NCRC 1 /* CRC */
+# undef KINETIS_K20 /* Not Kinetis K20 family */
+# define KINETIS_K40 1 /* Kinetis K40 family */
+# undef KINETIS_K60 /* Not Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
+# undef KINETIS_K66 /* Not Kinetis K66 family */
+
+# define KINETIS_FLASH_SIZE (128*1024) /* 128Kb */
+# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */
+# define KINETIS_SRAM_SIZE (32*1024) /* 32Kb */
+# undef KINETIS_MPU /* No memory protection unit */
+# undef KINETIS_EXTBUS /* No external bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# undef KINETIS_NENET /* No Ethernet controller */
+# define KINETIS_NUSBHOST 1 /* One USB host controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# undef KINETIS_NSDHC /* No SD host controller */
+# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */
+# define KINETIS_NI2C 2 /* Two I2C modules */
+# undef KINETIS_NISO7816 /* No UART with ISO-786 */
+# define KINETIS_NUART 6 /* Six UARTs */
+# define KINETIS_NSPI 3 /* Three SPI modules */
+# define KINETIS_NCAN 2 /* Two CAN controllers */
+# define KINETIS_NI2S 1 /* One I2S module */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
+# define KINETIS_NADC16 4 /* Four 16-bit ADC */
+# undef KINETIS_NADC12 /* No 12-channel ADC */
+# undef KINETIS_NADC13 /* No 13-channel ADC */
+# undef KINETIS_NADC15 /* No 15-channel ADC */
+# undef KINETIS_NADC18 /* No 18-channel ADC */
+# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
+# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
+# undef KINETIS_NTIMERS20 /* No 20 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# undef KINETIS_NRNG /* No random number generator */
+# undef KINETIS_NMMCAU /* No hardware encryption */
+# undef KINETIS_NTAMPER /* No tamper detect */
+# define KINETIS_NCRC 1 /* CRC */
#elif defined(CONFIG_ARCH_CHIP_MK40X256VLK72) || defined(CONFIG_ARCH_CHIP_MK40X256VMB72) || \
defined(CONFIG_ARCH_CHIP_MK40X256VLL72) || defined(CONFIG_ARCH_CHIP_MK40X256VML72)
-# undef KINETIS_K20 /* Not Kinetis K20 family */
-# define KINETIS_K40 1 /* Kinetics K40 family */
-# undef KINETIS_K60 /* Not Kinetis K60 family */
-# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
-# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */
-# define KINETIS_SRAM_SIZE (32*1024) /* 64Kb */
-# undef KINETIS_MPU /* No memory protection unit */
-# undef KINETIS_EXTBUS /* No external bus interface */
-# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
-# undef KINETIS_NENET /* No Ethernet controller */
-# define KINETIS_NUSBHOST 1 /* One USB host controller */
-# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
-# define KINETIS_NUSBDEV 1 /* One USB device controller */
-# undef KINETIS_NSDHC /* No SD host controller */
-# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */
-# define KINETIS_NI2C 2 /* Two I2C modules */
-# undef KINETIS_NISO7816 /* No UART with ISO-786 */
-# define KINETIS_NUART 6 /* Six UARTs */
-# define KINETIS_NSPI 3 /* Three SPI modules */
-# define KINETIS_NCAN 2 /* Two CAN controllers */
-# define KINETIS_NI2S 1 /* One I2S module */
-# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
-# define KINETIS_NADC16 4 /* Four 16-bit ADC */
-# undef KINETIS_NADC12 /* No 12-channel ADC */
-# undef KINETIS_NADC13 /* No 13-channel ADC */
-# undef KINETIS_NADC15 /* No 15-channel ADC */
-# undef KINETIS_NADC18 /* No 18-channel ADC */
-# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */
-# define KINETIS_NCMP 3 /* Three analog comparators */
-# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
-# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
-# define KINETIS_NVREF 1 /* Voltage reference */
-# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
-# undef KINETIS_NTIMERS20 /* No 20 channel timers */
-# define KINETIS_NRTC 1 /* Real time clock */
-# undef KINETIS_NRNG /* No random number generator */
-# undef KINETIS_NMMCAU /* No hardware encryption */
-# undef KINETIS_NTAMPER /* No tamper detect */
-# define KINETIS_NCRC 1 /* CRC */
+# undef KINETIS_K20 /* Not Kinetis K20 family */
+# define KINETIS_K40 1 /* Kinetis K40 family */
+# undef KINETIS_K60 /* Not Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
+# undef KINETIS_K66 /* Not Kinetis K66 family */
+
+# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
+# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */
+# define KINETIS_SRAM_SIZE (32*1024) /* 64Kb */
+# undef KINETIS_MPU /* No memory protection unit */
+# undef KINETIS_EXTBUS /* No external bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# undef KINETIS_NENET /* No Ethernet controller */
+# define KINETIS_NUSBHOST 1 /* One USB host controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# undef KINETIS_NSDHC /* No SD host controller */
+# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */
+# define KINETIS_NI2C 2 /* Two I2C modules */
+# undef KINETIS_NISO7816 /* No UART with ISO-786 */
+# define KINETIS_NUART 6 /* Six UARTs */
+# define KINETIS_NSPI 3 /* Three SPI modules */
+# define KINETIS_NCAN 2 /* Two CAN controllers */
+# define KINETIS_NI2S 1 /* One I2S module */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
+# define KINETIS_NADC16 4 /* Four 16-bit ADC */
+# undef KINETIS_NADC12 /* No 12-channel ADC */
+# undef KINETIS_NADC13 /* No 13-channel ADC */
+# undef KINETIS_NADC15 /* No 15-channel ADC */
+# undef KINETIS_NADC18 /* No 18-channel ADC */
+# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
+# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
+# undef KINETIS_NTIMERS20 /* No 20 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# undef KINETIS_NRNG /* No random number generator */
+# undef KINETIS_NMMCAU /* No hardware encryption */
+# undef KINETIS_NTAMPER /* No tamper detect */
+# define KINETIS_NCRC 1 /* CRC */
#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100)
-# undef KINETIS_K20 /* Not Kinetis K20 family */
-# define KINETIS_K40 1 /* Kinetics K40 family */
-# undef KINETIS_K60 /* Not Kinetis K60 family */
-# define KINETIS_FLASH_SIZE (128*1024) /* 128Kb */
-# define KINETIS_FLEXMEM_SIZE (128*1024) /* 128Kb */
-# define KINETIS_SRAM_SIZE (32*1024) /* 32Kb */
-# define KINETIS_MPU 1 /* Memory protection unit */
-# define KINETIS_EXTBUS 1 /* External bus interface */
-# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
-# undef KINETIS_NENET /* No Ethernet controller */
-# define KINETIS_NUSBHOST 1 /* One USB host controller */
-# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
-# define KINETIS_NUSBDEV 1 /* One USB device controller */
-# define KINETIS_NSDHC 1 /* One SD host controller */
-# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */
-# define KINETIS_NI2C 2 /* Two I2C modules */
-# undef KINETIS_NISO7816 /* No UART with ISO-786 */
-# define KINETIS_NUART 6 /* Six UARTs */
-# define KINETIS_NSPI 3 /* Three SPI modules */
-# define KINETIS_NCAN 2 /* Two CAN controllers */
-# define KINETIS_NI2S 1 /* One I2S module */
-# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 40x8/44x4)*/
-# define KINETIS_NADC16 4 /* Four 16-bit ADC */
-# undef KINETIS_NADC12 /* No 12-channel ADC */
-# undef KINETIS_NADC13 /* No 13-channel ADC */
-# undef KINETIS_NADC15 /* No 15-channel ADC */
-# undef KINETIS_NADC18 /* No 18-channel ADC */
-# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */
-# define KINETIS_NCMP 3 /* Three analog comparators */
-# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
-# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
-# define KINETIS_NVREF 1 /* Voltage reference */
-# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
-# undef KINETIS_NTIMERS20 /* No 20 channel timers */
-# define KINETIS_NRTC 1 /* Real time clock */
-# undef KINETIS_NRNG /* No random number generator */
-# undef KINETIS_NMMCAU /* No hardware encryption */
-# undef KINETIS_NTAMPER /* No tamper detect */
-# define KINETIS_NCRC 1 /* CRC */
+# undef KINETIS_K20 /* Not Kinetis K20 family */
+# define KINETIS_K40 1 /* Kinetis K40 family */
+# undef KINETIS_K60 /* Not Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
+# undef KINETIS_K66 /* Not Kinetis K66 family */
+
+# define KINETIS_FLASH_SIZE (128*1024) /* 128Kb */
+# define KINETIS_FLEXMEM_SIZE (128*1024) /* 128Kb */
+# define KINETIS_SRAM_SIZE (32*1024) /* 32Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# undef KINETIS_NENET /* No Ethernet controller */
+# define KINETIS_NUSBHOST 1 /* One USB host controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* One SD host controller */
+# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */
+# define KINETIS_NI2C 2 /* Two I2C modules */
+# undef KINETIS_NISO7816 /* No UART with ISO-786 */
+# define KINETIS_NUART 6 /* Six UARTs */
+# define KINETIS_NSPI 3 /* Three SPI modules */
+# define KINETIS_NCAN 2 /* Two CAN controllers */
+# define KINETIS_NI2S 1 /* One I2S module */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 40x8/44x4)*/
+# define KINETIS_NADC16 4 /* Four 16-bit ADC */
+# undef KINETIS_NADC12 /* No 12-channel ADC */
+# undef KINETIS_NADC13 /* No 13-channel ADC */
+# undef KINETIS_NADC15 /* No 15-channel ADC */
+# undef KINETIS_NADC18 /* No 18-channel ADC */
+# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
+# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
+# undef KINETIS_NTIMERS20 /* No 20 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# undef KINETIS_NRNG /* No random number generator */
+# undef KINETIS_NMMCAU /* No hardware encryption */
+# undef KINETIS_NTAMPER /* No tamper detect */
+# define KINETIS_NCRC 1 /* CRC */
#elif defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100)
-# undef KINETIS_K20 /* Not Kinetis K20 family */
-# define KINETIS_K40 1 /* Kinetics K40 family */
-# undef KINETIS_K60 /* Not Kinetis K60 family */
-# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
-# define KINETIS_FLEXMEM_SIZE (256*1024) /* 256Kb */
-# define KINETIS_SRAM_SIZE (64*1024) /* 32Kb */
-# define KINETIS_MPU 1 /* Memory protection unit */
-# define KINETIS_EXTBUS 1 /* External bus interface */
-# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
-# undef KINETIS_NENET /* No Ethernet controller */
-# define KINETIS_NUSBHOST 1 /* One USB host controller */
-# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
-# define KINETIS_NUSBDEV 1 /* One USB device controller */
-# define KINETIS_NSDHC 1 /* One SD host controller */
-# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */
-# define KINETIS_NI2C 2 /* Two I2C modules */
-# undef KINETIS_NISO7816 /* No UART with ISO-786 */
-# define KINETIS_NUART 6 /* Six UARTs */
-# define KINETIS_NSPI 3 /* Three SPI modules */
-# define KINETIS_NCAN 2 /* Two CAN controllers */
-# define KINETIS_NI2S 1 /* One I2S module */
-# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 40x8/44x4)*/
-# define KINETIS_NADC16 4 /* Four 16-bit ADC */
-# undef KINETIS_NADC12 /* No 12-channel ADC */
-# undef KINETIS_NADC13 /* No 13-channel ADC */
-# undef KINETIS_NADC15 /* No 15-channel ADC */
-# undef KINETIS_NADC18 /* No 18-channel ADC */
-# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */
-# define KINETIS_NCMP 3 /* Three analog comparators */
-# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
-# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
-# define KINETIS_NVREF 1 /* Voltage reference */
-# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
-# undef KINETIS_NTIMERS20 /* No 20 channel timers */
-# define KINETIS_NRTC 1 /* Real time clock */
-# undef KINETIS_NRNG /* No random number generator */
-# undef KINETIS_NMMCAU /* No hardware encryption */
-# undef KINETIS_NTAMPER /* No tamper detect */
-# define KINETIS_NCRC 1 /* CRC */
+# undef KINETIS_K20 /* Not Kinetis K20 family */
+# define KINETIS_K40 1 /* Kinetis K40 family */
+# undef KINETIS_K60 /* Not Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
+# undef KINETIS_K66 /* Not Kinetis K66 family */
+
+# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
+# define KINETIS_FLEXMEM_SIZE (256*1024) /* 256Kb */
+# define KINETIS_SRAM_SIZE (64*1024) /* 32Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# undef KINETIS_NENET /* No Ethernet controller */
+# define KINETIS_NUSBHOST 1 /* One USB host controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* One SD host controller */
+# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */
+# define KINETIS_NI2C 2 /* Two I2C modules */
+# undef KINETIS_NISO7816 /* No UART with ISO-786 */
+# define KINETIS_NUART 6 /* Six UARTs */
+# define KINETIS_NSPI 3 /* Three SPI modules */
+# define KINETIS_NCAN 2 /* Two CAN controllers */
+# define KINETIS_NI2S 1 /* One I2S module */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 40x8/44x4)*/
+# define KINETIS_NADC16 4 /* Four 16-bit ADC */
+# undef KINETIS_NADC12 /* No 12-channel ADC */
+# undef KINETIS_NADC13 /* No 13-channel ADC */
+# undef KINETIS_NADC15 /* No 15-channel ADC */
+# undef KINETIS_NADC18 /* No 18-channel ADC */
+# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
+# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
+# undef KINETIS_NTIMERS20 /* No 20 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# undef KINETIS_NRNG /* No random number generator */
+# undef KINETIS_NMMCAU /* No hardware encryption */
+# undef KINETIS_NTAMPER /* No tamper detect */
+# define KINETIS_NCRC 1 /* CRC */
#elif defined(CONFIG_ARCH_CHIP_MK40N512VLK100) || defined(CONFIG_ARCH_CHIP_MK40N512VMB100) || \
defined(CONFIG_ARCH_CHIP_MK40N512VLL100) || defined(CONFIG_ARCH_CHIP_MK40N512VML100) || \
defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100)
-# undef KINETIS_K20 /* Not Kinetis K20 family */
-# define KINETIS_K40 1 /* Kinetics K40 family */
-# undef KINETIS_K60 /* Not Kinetis K60 family */
-# define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */
-# undef KINETIS_FLEXMEM_SIZE /* No FlexMemory */
-# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */
-# define KINETIS_MPU 1 /* Memory protection unit */
-# define KINETIS_EXTBUS 1 /* External bus interface */
-# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
-# undef KINETIS_NENET /* No Ethernet controller */
-# define KINETIS_NUSBHOST 1 /* One USB host controller */
-# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
-# define KINETIS_NUSBDEV 1 /* One USB device controller */
-# define KINETIS_NSDHC 1 /* One SD host controller */
-# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */
-# define KINETIS_NI2C 2 /* Two I2C modules */
-# undef KINETIS_NISO7816 /* No UART with ISO-786 */
-# define KINETIS_NUART 6 /* Six UARTs */
-# define KINETIS_NSPI 3 /* Three SPI modules */
-# define KINETIS_NCAN 2 /* Two CAN controllers */
-# define KINETIS_NI2S 1 /* One I2S module */
-# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 40x8/44x4)*/
-# define KINETIS_NADC16 4 /* Four 16-bit ADC */
-# undef KINETIS_NADC12 /* No 12-channel ADC */
-# undef KINETIS_NADC13 /* No 13-channel ADC */
-# undef KINETIS_NADC15 /* No 15-channel ADC */
-# undef KINETIS_NADC18 /* No 18-channel ADC */
-# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */
-# define KINETIS_NCMP 3 /* Three analog comparators */
-# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
-# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
-# define KINETIS_NVREF 1 /* Voltage reference */
-# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
-# undef KINETIS_NTIMERS20 /* No 20 channel timers */
-# define KINETIS_NRTC 1 /* Real time clock */
-# undef KINETIS_NRNG /* No random number generator */
-# undef KINETIS_NMMCAU /* No hardware encryption */
-# undef KINETIS_NTAMPER /* No tamper detect */
-# define KINETIS_NCRC 1 /* CRC */
+# undef KINETIS_K20 /* Not Kinetis K20 family */
+# define KINETIS_K40 1 /* Kinetis K40 family */
+# undef KINETIS_K60 /* Not Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
+# undef KINETIS_K66 /* Not Kinetis K66 family */
+
+# define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */
+# undef KINETIS_FLEXMEM_SIZE /* No FlexMemory */
+# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# undef KINETIS_NENET /* No Ethernet controller */
+# define KINETIS_NUSBHOST 1 /* One USB host controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* One SD host controller */
+# undef KINETIS_NTOUCHIF /* Xtrinsic touch sensing interface */
+# define KINETIS_NI2C 2 /* Two I2C modules */
+# undef KINETIS_NISO7816 /* No UART with ISO-786 */
+# define KINETIS_NUART 6 /* Six UARTs */
+# define KINETIS_NSPI 3 /* Three SPI modules */
+# define KINETIS_NCAN 2 /* Two CAN controllers */
+# define KINETIS_NI2S 1 /* One I2S module */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 40x8/44x4)*/
+# define KINETIS_NADC16 4 /* Four 16-bit ADC */
+# undef KINETIS_NADC12 /* No 12-channel ADC */
+# undef KINETIS_NADC13 /* No 13-channel ADC */
+# undef KINETIS_NADC15 /* No 15-channel ADC */
+# undef KINETIS_NADC18 /* No 18-channel ADC */
+# define KINETIS_NPGA 2 /* Two Programmable Gain Amplifiers */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
+# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
+# undef KINETIS_NTIMERS20 /* No 20 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# undef KINETIS_NRNG /* No random number generator */
+# undef KINETIS_NMMCAU /* No hardware encryption */
+# undef KINETIS_NTAMPER /* No tamper detect */
+# define KINETIS_NCRC 1 /* CRC */
#elif defined(CONFIG_ARCH_CHIP_MK60N256VLL100)
-# undef KINETIS_K20 /* Not Kinetis K20 family */
-# undef KINETIS_K40 /* Not Kinetics K40 family */
-# define KINETIS_K60 1 /* Kinetis K60 family */
-# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
-# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
-# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
-# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */
-# define KINETIS_MPU 1 /* Memory protection unit */
-# define KINETIS_EXTBUS 1 /* External bus interface */
-# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
-# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
-# define KINETIS_NUSBHOST 1 /* One USB host controller */
-# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
-# define KINETIS_NUSBDEV 1 /* One USB device controller */
-# define KINETIS_NSDHC 1 /* SD host controller */
-# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
-# define KINETIS_NI2C 3 /* Three I2C modules */
-# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
-# define KINETIS_NUART 4 /* Four additional UARTs */
-# define KINETIS_NSPI 3 /* Three SPI modules */
-# define KINETIS_NCAN 2 /* Two CAN controllers */
-# define KINETIS_NI2S 2 /* Two I2S modules */
-# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
-# define KINETIS_NADC16 4 /* Four 16-bit ADC */
-# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/
-# define KINETIS_NADC13 1 /* No 13-channel ADC (ADC1) */
-# undef KINETIS_NADC15 /* No 15-channel ADC */
-# undef KINETIS_NADC18 /* No 18-channel ADC */
-# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
-# define KINETIS_NCMP 3 /* Three analog comparators */
-# undef KINETIS_NDAC6 /* No 6-bit DAC */
-# define KINETIS_NDAC12 1 /* One 12-bit DAC */
-# define KINETIS_NVREF 1 /* Voltage reference */
-# undef KINETIS_NTIMERS12 /* No 12 channel timers */
-# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
-# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
-# undef KINETIS_NTIMERS20 /* No 20 channel timers */
-# define KINETIS_NRTC 1 /* Real time clock */
-# undef KINETIS_NRNG /* No random number generator */
-# undef KINETIS_NMMCAU /* No hardware encryption */
-# undef KINETIS_NTAMPER /* No tamper detect */
-# define KINETIS_NCRC 1 /* CRC */
+# undef KINETIS_K20 /* Not Kinetis K20 family */
+# undef KINETIS_K40 /* Not Kinetis K40 family */
+# define KINETIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
+# undef KINETIS_K66 /* Not Kinetis K66 family */
+
+# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
+# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
+# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
+# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
+# define KINETIS_NUSBHOST 1 /* One USB host controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* SD host controller */
+# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
+# define KINETIS_NI2C 3 /* Three I2C modules */
+# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
+# define KINETIS_NUART 4 /* Four additional UARTs */
+# define KINETIS_NSPI 3 /* Three SPI modules */
+# define KINETIS_NCAN 2 /* Two CAN controllers */
+# define KINETIS_NI2S 2 /* Two I2S modules */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
+# define KINETIS_NADC16 4 /* Four 16-bit ADC */
+# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/
+# define KINETIS_NADC13 1 /* No 13-channel ADC (ADC1) */
+# undef KINETIS_NADC15 /* No 15-channel ADC */
+# undef KINETIS_NADC18 /* No 18-channel ADC */
+# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# undef KINETIS_NDAC6 /* No 6-bit DAC */
+# define KINETIS_NDAC12 1 /* One 12-bit DAC */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# undef KINETIS_NTIMERS12 /* No 12 channel timers */
+# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
+# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
+# undef KINETIS_NTIMERS20 /* No 20 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# undef KINETIS_NRNG /* No random number generator */
+# undef KINETIS_NMMCAU /* No hardware encryption */
+# undef KINETIS_NTAMPER /* No tamper detect */
+# define KINETIS_NCRC 1 /* CRC */
#elif defined(CONFIG_ARCH_CHIP_MK60X256VLL100)
-# undef KINETIS_K20 /* Not Kinetis K20 family */
-# undef KINETIS_K40 /* Not Kinetics K40 family */
-# define KINETIS_K60 1 /* Kinetis K60 family */
-# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
-# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */
-# define KINETIS_FLEXRAM_SIZE (4*1024) /* 32Kb */
-# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */
-# define KINETIS_MPU 1 /* Memory protection unit */
-# define KINETIS_EXTBUS 1 /* External bus interface */
-# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
-# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
-# define KINETIS_NUSBHOST 1 /* One USB host controller */
-# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
-# define KINETIS_NUSBDEV 1 /* One USB device controller */
-# define KINETIS_NSDHC 1 /* SD host controller */
-# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
-# define KINETIS_NI2C 3 /* Three I2C modules */
-# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
-# define KINETIS_NUART 4 /* Four additional UARTs */
-# define KINETIS_NSPI 3 /* Three SPI modules */
-# define KINETIS_NCAN 2 /* Two CAN controllers */
-# define KINETIS_NI2S 2 /* Two I2S modules */
-# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
-# define KINETIS_NADC16 4 /* Four 16-bit ADC */
-# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/
-# define KINETIS_NADC13 1 /* No 13-channel ADC (ADC1) */
-# undef KINETIS_NADC15 /* No 15-channel ADC */
-# undef KINETIS_NADC18 /* No 18-channel ADC */
-# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
-# define KINETIS_NCMP 3 /* Three analog comparators */
-# undef KINETIS_NDAC6 /* No 6-bit DAC */
-# define KINETIS_NDAC12 1 /* One 12-bit DAC */
-# define KINETIS_NVREF 1 /* Voltage reference */
-# undef KINETIS_NTIMERS12 /* No 12 channel timers */
-# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
-# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
-# undef KINETIS_NTIMERS20 /* No 20 channel timers */
-# define KINETIS_NRTC 1 /* Real time clock */
-# undef KINETIS_NRNG /* No random number generator */
-# undef KINETIS_NMMCAU /* No hardware encryption */
-# undef KINETIS_NTAMPER /* No tamper detect */
-# define KINETIS_NCRC 1 /* CRC */
+# undef KINETIS_K20 /* Not Kinetis K20 family */
+# undef KINETIS_K40 /* Not Kinetis K40 family */
+# define KINETIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
+# undef KINETIS_K66 /* Not Kinetis K66 family */
+
+# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
+# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */
+# define KINETIS_FLEXRAM_SIZE (4*1024) /* 32Kb */
+# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
+# define KINETIS_NUSBHOST 1 /* One USB host controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* SD host controller */
+# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
+# define KINETIS_NI2C 3 /* Three I2C modules */
+# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
+# define KINETIS_NUART 4 /* Four additional UARTs */
+# define KINETIS_NSPI 3 /* Three SPI modules */
+# define KINETIS_NCAN 2 /* Two CAN controllers */
+# define KINETIS_NI2S 2 /* Two I2S modules */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
+# define KINETIS_NADC16 4 /* Four 16-bit ADC */
+# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/
+# define KINETIS_NADC13 1 /* No 13-channel ADC (ADC1) */
+# undef KINETIS_NADC15 /* No 15-channel ADC */
+# undef KINETIS_NADC18 /* No 18-channel ADC */
+# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# undef KINETIS_NDAC6 /* No 6-bit DAC */
+# define KINETIS_NDAC12 1 /* One 12-bit DAC */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# undef KINETIS_NTIMERS12 /* No 12 channel timers */
+# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
+# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
+# undef KINETIS_NTIMERS20 /* No 20 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# undef KINETIS_NRNG /* No random number generator */
+# undef KINETIS_NMMCAU /* No hardware encryption */
+# undef KINETIS_NTAMPER /* No tamper detect */
+# define KINETIS_NCRC 1 /* CRC */
#elif defined(CONFIG_ARCH_CHIP_MK60N512VLL100)
-# undef KINETIS_K20 /* Not Kinetis K20 family */
-# undef KINETIS_K40 /* Not Kinetics K40 family */
-# define KINETIS_K60 1 /* Kinetis K60 family */
-# define KINETIS_FLASH_SIZE (512*1024) /* 256Kb */
-# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
-# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
-# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */
-# define KINETIS_MPU 1 /* Memory protection unit */
-# define KINETIS_EXTBUS 1 /* External bus interface */
-# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
-# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
-# define KINETIS_ENET_HAS_DBSWAP /* MAC-NET supports DBSWP bit */
-# define KINETIS_NUSBHOST 1 /* One USB host controller */
-# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
-# define KINETIS_NUSBDEV 1 /* One USB device controller */
-# define KINETIS_NSDHC 1 /* SD host controller */
-# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
-# define KINETIS_NI2C 3 /* Three I2C modules */
-# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
-# define KINETIS_NUART 4 /* Four additional UARTs */
-# define KINETIS_NSPI 3 /* Three SPI modules */
-# define KINETIS_NCAN 2 /* Two CAN controllers */
-# define KINETIS_NI2S 2 /* Two I2S modules */
-# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
-# define KINETIS_NADC16 4 /* Four 16-bit ADC */
-# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/
-# define KINETIS_NADC13 1 /* No 13-channel ADC (ADC1) */
-# undef KINETIS_NADC15 /* No 15-channel ADC */
-# undef KINETIS_NADC18 /* No 18-channel ADC */
-# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
-# define KINETIS_NCMP 3 /* Three analog comparators */
-# undef KINETIS_NDAC6 /* No 6-bit DAC */
-# define KINETIS_NDAC12 1 /* One 12-bit DAC */
-# define KINETIS_NVREF 1 /* Voltage reference */
-# undef KINETIS_NTIMERS12 /* No 12 channel timers */
-# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
-# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
-# undef KINETIS_NTIMERS20 /* No 20 channel timers */
-# define KINETIS_NRTC 1 /* Real time clock */
-# undef KINETIS_NRNG /* No random number generator */
-# undef KINETIS_NMMCAU /* No hardware encryption */
-# undef KINETIS_NTAMPER /* No tamper detect */
-# define KINETIS_NCRC 1 /* CRC */
+# undef KINETIS_K20 /* Not Kinetis K20 family */
+# undef KINETIS_K40 /* Not Kinetis K40 family */
+# define KINETIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
+# undef KINETIS_K66 /* Not Kinetis K66 family */
+
+# define KINETIS_FLASH_SIZE (512*1024) /* 256Kb */
+# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
+# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
+# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
+# define KINETIS_ENET_HAS_DBSWAP /* MAC-NET supports DBSWP bit */
+# define KINETIS_NUSBHOST 1 /* One USB host controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* SD host controller */
+# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
+# define KINETIS_NI2C 3 /* Three I2C modules */
+# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
+# define KINETIS_NUART 4 /* Four additional UARTs */
+# define KINETIS_NSPI 3 /* Three SPI modules */
+# define KINETIS_NCAN 2 /* Two CAN controllers */
+# define KINETIS_NI2S 2 /* Two I2S modules */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
+# define KINETIS_NADC16 4 /* Four 16-bit ADC */
+# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/
+# define KINETIS_NADC13 1 /* No 13-channel ADC (ADC1) */
+# undef KINETIS_NADC15 /* No 15-channel ADC */
+# undef KINETIS_NADC18 /* No 18-channel ADC */
+# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# undef KINETIS_NDAC6 /* No 6-bit DAC */
+# define KINETIS_NDAC12 1 /* One 12-bit DAC */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# undef KINETIS_NTIMERS12 /* No 12 channel timers */
+# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
+# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
+# undef KINETIS_NTIMERS20 /* No 20 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# undef KINETIS_NRNG /* No random number generator */
+# undef KINETIS_NMMCAU /* No hardware encryption */
+# undef KINETIS_NTAMPER /* No tamper detect */
+# define KINETIS_NCRC 1 /* CRC */
#elif defined(CONFIG_ARCH_CHIP_MK60N256VML100)
-# undef KINETIS_K20 /* Not Kinetis K20 family */
-# undef KINETIS_K40 /* Not Kinetics K40 family */
-# define KINETIS_K60 1 /* Kinetis K60 family */
-# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
-# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
-# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
-# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */
-# define KINETIS_MPU 1 /* Memory protection unit */
-# define KINETIS_EXTBUS 1 /* External bus interface */
-# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
-# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
-# define KINETIS_NUSBHOST 1 /* One USB host controller */
-# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
-# define KINETIS_NUSBDEV 1 /* One USB device controller */
-# define KINETIS_NSDHC 1 /* SD host controller */
-# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
-# define KINETIS_NI2C 3 /* Three I2C modules */
-# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
-# define KINETIS_NUART 4 /* Four additional UARTs */
-# define KINETIS_NSPI 3 /* Three SPI modules */
-# define KINETIS_NCAN 2 /* Two CAN controllers */
-# define KINETIS_NI2S 2 /* Two I2S modules */
-# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
-# define KINETIS_NADC16 4 /* Four 16-bit ADC */
-# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/
-# undef KINETIS_NADC13 /* No 13-channel ADC */
-# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC1) */
-# undef KINETIS_NADC18 /* No 18-channel ADC */
-# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
-# define KINETIS_NCMP 3 /* Three analog comparators */
-# undef KINETIS_NDAC6 /* No 6-bit DAC */
-# define KINETIS_NDAC12 1 /* One 12-bit DAC */
-# define KINETIS_NVREF 1 /* Voltage reference */
-# undef KINETIS_NTIMERS12 /* No 12 channel timers */
-# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
-# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
-# undef KINETIS_NTIMERS20 /* No 20 channel timers */
-# define KINETIS_NRTC 1 /* Real time clock */
-# undef KINETIS_NRNG /* No random number generator */
-# undef KINETIS_NMMCAU /* No hardware encryption */
-# undef KINETIS_NTAMPER /* No tamper detect */
-# define KINETIS_NCRC 1 /* CRC */
+# undef KINETIS_K20 /* Not Kinetis K20 family */
+# undef KINETIS_K40 /* Not Kinetis K40 family */
+# define KINETIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
+# undef KINETIS_K66 /* Not Kinetis K66 family */
+
+# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
+# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
+# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
+# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
+# define KINETIS_NUSBHOST 1 /* One USB host controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* SD host controller */
+# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
+# define KINETIS_NI2C 3 /* Three I2C modules */
+# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
+# define KINETIS_NUART 4 /* Four additional UARTs */
+# define KINETIS_NSPI 3 /* Three SPI modules */
+# define KINETIS_NCAN 2 /* Two CAN controllers */
+# define KINETIS_NI2S 2 /* Two I2S modules */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
+# define KINETIS_NADC16 4 /* Four 16-bit ADC */
+# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/
+# undef KINETIS_NADC13 /* No 13-channel ADC */
+# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC1) */
+# undef KINETIS_NADC18 /* No 18-channel ADC */
+# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# undef KINETIS_NDAC6 /* No 6-bit DAC */
+# define KINETIS_NDAC12 1 /* One 12-bit DAC */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# undef KINETIS_NTIMERS12 /* No 12 channel timers */
+# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
+# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
+# undef KINETIS_NTIMERS20 /* No 20 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# undef KINETIS_NRNG /* No random number generator */
+# undef KINETIS_NMMCAU /* No hardware encryption */
+# undef KINETIS_NTAMPER /* No tamper detect */
+# define KINETIS_NCRC 1 /* CRC */
#elif defined(CONFIG_ARCH_CHIP_MK60X256VML100)
-# undef KINETIS_K20 /* Not Kinetis K20 family */
-# undef KINETIS_K40 /* Not Kinetics K40 family */
-# define KINETIS_K60 1 /* Kinetis K60 family */
-# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
-# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */
-# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
-# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */
-# define KINETIS_MPU 1 /* Memory protection unit */
-# define KINETIS_EXTBUS 1 /* External bus interface */
-# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
-# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
-# define KINETIS_NUSBHOST 1 /* One USB host controller */
-# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
-# define KINETIS_NUSBDEV 1 /* One USB device controller */
-# define KINETIS_NSDHC 1 /* SD host controller */
-# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
-# define KINETIS_NI2C 3 /* Three I2C modules */
-# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
-# define KINETIS_NUART 4 /* Four additional UARTs */
-# define KINETIS_NSPI 3 /* Three SPI modules */
-# define KINETIS_NCAN 2 /* Two CAN controllers */
-# define KINETIS_NI2S 2 /* Two I2S modules */
-# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
-# define KINETIS_NADC16 4 /* Four 16-bit ADC */
-# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/
-# undef KINETIS_NADC13 /* No 13-channel ADC */
-# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC1) */
-# undef KINETIS_NADC18 /* No 18-channel ADC */
-# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
-# define KINETIS_NCMP 3 /* Three analog comparators */
-# undef KINETIS_NDAC6 /* No 6-bit DAC */
-# define KINETIS_NDAC12 1 /* One 12-bit DAC */
-# define KINETIS_NVREF 1 /* Voltage reference */
-# undef KINETIS_NTIMERS12 /* No 12 channel timers */
-# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
-# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
-# undef KINETIS_NTIMERS20 /* No 20 channel timers */
-# define KINETIS_NRTC 1 /* Real time clock */
-# undef KINETIS_NRNG /* No random number generator */
-# undef KINETIS_NMMCAU /* No hardware encryption */
-# undef KINETIS_NTAMPER /* No tamper detect */
-# define KINETIS_NCRC 1 /* CRC */
+# undef KINETIS_K20 /* Not Kinetis K20 family */
+# undef KINETIS_K40 /* Not Kinetis K40 family */
+# define KINETIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
+# undef KINETIS_K66 /* Not Kinetis K66 family */
+
+# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
+# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */
+# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
+# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
+# define KINETIS_NUSBHOST 1 /* One USB host controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* SD host controller */
+# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
+# define KINETIS_NI2C 3 /* Three I2C modules */
+# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
+# define KINETIS_NUART 4 /* Four additional UARTs */
+# define KINETIS_NSPI 3 /* Three SPI modules */
+# define KINETIS_NCAN 2 /* Two CAN controllers */
+# define KINETIS_NI2S 2 /* Two I2S modules */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
+# define KINETIS_NADC16 4 /* Four 16-bit ADC */
+# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/
+# undef KINETIS_NADC13 /* No 13-channel ADC */
+# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC1) */
+# undef KINETIS_NADC18 /* No 18-channel ADC */
+# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# undef KINETIS_NDAC6 /* No 6-bit DAC */
+# define KINETIS_NDAC12 1 /* One 12-bit DAC */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# undef KINETIS_NTIMERS12 /* No 12 channel timers */
+# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
+# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
+# undef KINETIS_NTIMERS20 /* No 20 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# undef KINETIS_NRNG /* No random number generator */
+# undef KINETIS_NMMCAU /* No hardware encryption */
+# undef KINETIS_NTAMPER /* No tamper detect */
+# define KINETIS_NCRC 1 /* CRC */
#elif defined(CONFIG_ARCH_CHIP_MK60N512VML100)
-# undef KINETIS_K20 /* Not Kinetis K20 family */
-# undef KINETIS_K40 /* Not Kinetics K40 family */
-# define KINETIS_K60 1 /* Kinetis K60 family */
-# define KINETIS_FLASH_SIZE (512*1024) /* 256Kb */
-# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
-# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
-# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */
-# define KINETIS_MPU 1 /* Memory protection unit */
-# define KINETIS_EXTBUS 1 /* External bus interface */
-# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
-# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
-# define KINETIS_NUSBHOST 1 /* One USB host controller */
-# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
-# define KINETIS_NUSBDEV 1 /* One USB device controller */
-# define KINETIS_NSDHC 1 /* SD host controller */
-# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
-# define KINETIS_NI2C 3 /* Three I2C modules */
-# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
-# define KINETIS_NUART 4 /* Four additional UARTs */
-# define KINETIS_NSPI 3 /* Three SPI modules */
-# define KINETIS_NCAN 2 /* Two CAN controllers */
-# define KINETIS_NI2S 2 /* Two I2S modules */
-# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
-# define KINETIS_NADC16 4 /* Four 16-bit ADC */
-# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/
-# undef KINETIS_NADC13 /* No 13-channel ADC */
-# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC1) */
-# undef KINETIS_NADC18 /* No 18-channel ADC */
-# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
-# define KINETIS_NCMP 3 /* Three analog comparators */
-# undef KINETIS_NDAC6 /* No 6-bit DAC */
-# define KINETIS_NDAC12 1 /* One 12-bit DAC */
-# define KINETIS_NVREF 1 /* Voltage reference */
-# undef KINETIS_NTIMERS12 /* No 12 channel timers */
-# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
-# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
-# undef KINETIS_NTIMERS20 /* No 20 channel timers */
-# define KINETIS_NRTC 1 /* Real time clock */
-# undef KINETIS_NRNG /* No random number generator */
-# undef KINETIS_NMMCAU /* No hardware encryption */
-# undef KINETIS_NTAMPER /* No tamper detect */
-# define KINETIS_NCRC 1 /* CRC */
+# undef KINETIS_K20 /* Not Kinetis K20 family */
+# undef KINETIS_K40 /* Not Kinetis K40 family */
+# define KINETIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
+# undef KINETIS_K66 /* Not Kinetis K66 family */
+
+# define KINETIS_FLASH_SIZE (512*1024) /* 256Kb */
+# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
+# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
+# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
+# define KINETIS_NUSBHOST 1 /* One USB host controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* SD host controller */
+# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
+# define KINETIS_NI2C 3 /* Three I2C modules */
+# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
+# define KINETIS_NUART 4 /* Four additional UARTs */
+# define KINETIS_NSPI 3 /* Three SPI modules */
+# define KINETIS_NCAN 2 /* Two CAN controllers */
+# define KINETIS_NI2S 2 /* Two I2S modules */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
+# define KINETIS_NADC16 4 /* Four 16-bit ADC */
+# define KINETIS_NADC12 1 /* One 12-channel ADC (ADC0)*/
+# undef KINETIS_NADC13 /* No 13-channel ADC */
+# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC1) */
+# undef KINETIS_NADC18 /* No 18-channel ADC */
+# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# undef KINETIS_NDAC6 /* No 6-bit DAC */
+# define KINETIS_NDAC12 1 /* One 12-bit DAC */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# undef KINETIS_NTIMERS12 /* No 12 channel timers */
+# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
+# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
+# undef KINETIS_NTIMERS20 /* No 20 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# undef KINETIS_NRNG /* No random number generator */
+# undef KINETIS_NMMCAU /* No hardware encryption */
+# undef KINETIS_NTAMPER /* No tamper detect */
+# define KINETIS_NCRC 1 /* CRC */
#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100)
-# undef KINETIS_K20 /* Not Kinetis K20 family */
-# undef KINETIS_K40 /* Not Kinetics K40 family */
-# define KINETIS_K60 1 /* Kinetis K60 family */
-# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
-# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
-# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
-# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */
-# define KINETIS_MPU 1 /* Memory protection unit */
-# define KINETIS_EXTBUS 1 /* External bus interface */
-# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
-# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
-# define KINETIS_NUSBHOST 1 /* One USB host controller */
-# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
-# define KINETIS_NUSBDEV 1 /* One USB device controller */
-# define KINETIS_NSDHC 1 /* SD host controller */
-# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
-# define KINETIS_NI2C 3 /* Three I2C modules */
-# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
-# define KINETIS_NUART 5 /* Five additional UARTs */
-# define KINETIS_NSPI 3 /* Three SPI modules */
-# define KINETIS_NCAN 2 /* Two CAN controllers */
-# define KINETIS_NI2S 2 /* Two I2S modules */
-# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
-# define KINETIS_NADC16 4 /* Four 16-bit ADC */
-# undef KINETIS_NADC12 /* No 12-channel ADC */
-# undef KINETIS_NADC13 /* No 13-channel ADC */
-# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */
-# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */
-# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
-# define KINETIS_NCMP 3 /* Three analog comparators */
-# undef KINETIS_NDAC6 /* No 6-bit DAC */
-# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */
-# define KINETIS_NVREF 1 /* Voltage reference */
-# undef KINETIS_NTIMERS12 /* No 12 channel timers */
-# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
-# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
-# undef KINETIS_NTIMERS20 /* No 20 channel timers */
-# define KINETIS_NRTC 1 /* Real time clock */
-# undef KINETIS_NRNG /* No random number generator */
-# undef KINETIS_NMMCAU /* No hardware encryption */
-# undef KINETIS_NTAMPER /* No tamper detect */
-# define KINETIS_NCRC 1 /* CRC */
+# undef KINETIS_K20 /* Not Kinetis K20 family */
+# undef KINETIS_K40 /* Not Kinetis K40 family */
+# define KINETIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
+# undef KINETIS_K66 /* Not Kinetis K66 family */
+
+# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
+# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
+# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
+# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
+# define KINETIS_NUSBHOST 1 /* One USB host controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* SD host controller */
+# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
+# define KINETIS_NI2C 3 /* Three I2C modules */
+# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
+# define KINETIS_NUART 5 /* Five additional UARTs */
+# define KINETIS_NSPI 3 /* Three SPI modules */
+# define KINETIS_NCAN 2 /* Two CAN controllers */
+# define KINETIS_NI2S 2 /* Two I2S modules */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
+# define KINETIS_NADC16 4 /* Four 16-bit ADC */
+# undef KINETIS_NADC12 /* No 12-channel ADC */
+# undef KINETIS_NADC13 /* No 13-channel ADC */
+# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */
+# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */
+# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# undef KINETIS_NDAC6 /* No 6-bit DAC */
+# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# undef KINETIS_NTIMERS12 /* No 12 channel timers */
+# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
+# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
+# undef KINETIS_NTIMERS20 /* No 20 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# undef KINETIS_NRNG /* No random number generator */
+# undef KINETIS_NMMCAU /* No hardware encryption */
+# undef KINETIS_NTAMPER /* No tamper detect */
+# define KINETIS_NCRC 1 /* CRC */
#elif defined(CONFIG_ARCH_CHIP_MK60X256VLQ100)
-# undef KINETIS_K20 /* Not Kinetis K20 family */
-# undef KINETIS_K40 /* Not Kinetics K40 family */
-# define KINETIS_K60 1 /* Kinetis K60 family */
-# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
-# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */
-# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
-# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */
-# define KINETIS_MPU 1 /* Memory protection unit */
-# define KINETIS_EXTBUS 1 /* External bus interface */
-# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
-# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
-# define KINETIS_NUSBHOST 1 /* One USB host controller */
-# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
-# define KINETIS_NUSBDEV 1 /* One USB device controller */
-# define KINETIS_NSDHC 1 /* SD host controller */
-# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
-# define KINETIS_NI2C 3 /* Three I2C modules */
-# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
-# define KINETIS_NUART 5 /* Five additional UARTs */
-# define KINETIS_NSPI 3 /* Three SPI modules */
-# define KINETIS_NCAN 2 /* Two CAN controllers */
-# define KINETIS_NI2S 2 /* Two I2S modules */
-# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
-# define KINETIS_NADC16 4 /* Four 16-bit ADC */
-# undef KINETIS_NADC12 /* No 12-channel ADC */
-# undef KINETIS_NADC13 /* No 13-channel ADC */
-# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */
-# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */
-# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
-# define KINETIS_NCMP 3 /* Three analog comparators */
-# undef KINETIS_NDAC6 /* No 6-bit DAC */
-# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */
-# define KINETIS_NVREF 1 /* Voltage reference */
-# undef KINETIS_NTIMERS12 /* No 12 channel timers */
-# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
-# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
-# undef KINETIS_NTIMERS20 /* No 20 channel timers */
-# define KINETIS_NRTC 1 /* Real time clock */
-# undef KINETIS_NRNG /* No random number generator */
-# undef KINETIS_NMMCAU /* No hardware encryption */
-# undef KINETIS_NTAMPER /* No tamper detect */
-# define KINETIS_NCRC 1 /* CRC */
+# undef KINETIS_K20 /* Not Kinetis K20 family */
+# undef KINETIS_K40 /* Not Kinetis K40 family */
+# define KINETIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
+# undef KINETIS_K66 /* Not Kinetis K66 family */
+
+# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
+# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */
+# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
+# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
+# define KINETIS_NUSBHOST 1 /* One USB host controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* SD host controller */
+# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
+# define KINETIS_NI2C 3 /* Three I2C modules */
+# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
+# define KINETIS_NUART 5 /* Five additional UARTs */
+# define KINETIS_NSPI 3 /* Three SPI modules */
+# define KINETIS_NCAN 2 /* Two CAN controllers */
+# define KINETIS_NI2S 2 /* Two I2S modules */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
+# define KINETIS_NADC16 4 /* Four 16-bit ADC */
+# undef KINETIS_NADC12 /* No 12-channel ADC */
+# undef KINETIS_NADC13 /* No 13-channel ADC */
+# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */
+# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */
+# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# undef KINETIS_NDAC6 /* No 6-bit DAC */
+# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# undef KINETIS_NTIMERS12 /* No 12 channel timers */
+# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
+# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
+# undef KINETIS_NTIMERS20 /* No 20 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# undef KINETIS_NRNG /* No random number generator */
+# undef KINETIS_NMMCAU /* No hardware encryption */
+# undef KINETIS_NTAMPER /* No tamper detect */
+# define KINETIS_NCRC 1 /* CRC */
#elif defined(CONFIG_ARCH_CHIP_MK60N512VLQ100)
-# undef KINETIS_K20 /* Not Kinetis K20 family */
-# undef KINETIS_K40 /* Not Kinetics K40 family */
-# define KINETIS_K60 1 /* Kinetis K60 family */
-# define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */
-# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
-# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
-# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */
-# define KINETIS_MPU 1 /* Memory protection unit */
-# define KINETIS_EXTBUS 1 /* External bus interface */
-# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
-# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
-# define KINETIS_NUSBHOST 1 /* One USB host controller */
-# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
-# define KINETIS_NUSBDEV 1 /* One USB device controller */
-# define KINETIS_NSDHC 1 /* SD host controller */
-# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
-# define KINETIS_NI2C 3 /* Three I2C modules */
-# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
-# define KINETIS_NUART 5 /* Five additional UARTs */
-# define KINETIS_NSPI 3 /* Three SPI modules */
-# define KINETIS_NCAN 2 /* Two CAN controllers */
-# define KINETIS_NI2S 2 /* Two I2S modules */
-# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
-# define KINETIS_NADC16 4 /* Four 16-bit ADC */
-# undef KINETIS_NADC12 /* No 12-channel ADC */
-# undef KINETIS_NADC13 /* No 13-channel ADC */
-# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */
-# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */
-# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
-# define KINETIS_NCMP 3 /* Three analog comparators */
-# undef KINETIS_NDAC6 /* No 6-bit DAC */
-# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */
-# define KINETIS_NVREF 1 /* Voltage reference */
-# undef KINETIS_NTIMERS12 /* No 12 channel timers */
-# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
-# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
-# undef KINETIS_NTIMERS20 /* No 20 channel timers */
-# define KINETIS_NRTC 1 /* Real time clock */
-# undef KINETIS_NRNG /* No random number generator */
-# undef KINETIS_NMMCAU /* No hardware encryption */
-# undef KINETIS_NTAMPER /* No tamper detect */
-# define KINETIS_NCRC 1 /* CRC */
+# undef KINETIS_K20 /* Not Kinetis K20 family */
+# undef KINETIS_K40 /* Not Kinetis K40 family */
+# define KINETIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
+# undef KINETIS_K66 /* Not Kinetis K66 family */
+
+# define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */
+# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
+# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
+# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
+# define KINETIS_NUSBHOST 1 /* One USB host controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* SD host controller */
+# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
+# define KINETIS_NI2C 3 /* Three I2C modules */
+# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
+# define KINETIS_NUART 5 /* Five additional UARTs */
+# define KINETIS_NSPI 3 /* Three SPI modules */
+# define KINETIS_NCAN 2 /* Two CAN controllers */
+# define KINETIS_NI2S 2 /* Two I2S modules */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
+# define KINETIS_NADC16 4 /* Four 16-bit ADC */
+# undef KINETIS_NADC12 /* No 12-channel ADC */
+# undef KINETIS_NADC13 /* No 13-channel ADC */
+# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */
+# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */
+# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# undef KINETIS_NDAC6 /* No 6-bit DAC */
+# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# undef KINETIS_NTIMERS12 /* No 12 channel timers */
+# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
+# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
+# undef KINETIS_NTIMERS20 /* No 20 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# undef KINETIS_NRNG /* No random number generator */
+# undef KINETIS_NMMCAU /* No hardware encryption */
+# undef KINETIS_NTAMPER /* No tamper detect */
+# define KINETIS_NCRC 1 /* CRC */
#elif defined(CONFIG_ARCH_CHIP_MK60N256VMD100)
-# undef KINETIS_K20 /* Not Kinetis K20 family */
-# undef KINETIS_K40 /* Not Kinetics K40 family */
-# define KINETIS_K60 1 /* Kinetis K60 family */
-# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
-# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
-# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
-# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */
-# define KINETIS_MPU 1 /* Memory protection unit */
-# define KINETIS_EXTBUS 1 /* External bus interface */
-# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
-# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
-# define KINETIS_NUSBHOST 1 /* One USB host controller */
-# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
-# define KINETIS_NUSBDEV 1 /* One USB device controller */
-# define KINETIS_NSDHC 1 /* SD host controller */
-# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
-# define KINETIS_NI2C 3 /* Three I2C modules */
-# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
-# define KINETIS_NUART 5 /* Five additional UARTs */
-# define KINETIS_NSPI 3 /* Three SPI modules */
-# define KINETIS_NCAN 2 /* Two CAN controllers */
-# define KINETIS_NI2S 2 /* Two I2S modules */
-# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
-# define KINETIS_NADC16 4 /* Four 16-bit ADC */
-# undef KINETIS_NADC12 /* No 12-channel ADC */
-# undef KINETIS_NADC13 /* No 13-channel ADC */
-# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */
-# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */
-# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
-# define KINETIS_NCMP 3 /* Three analog comparators */
-# undef KINETIS_NDAC6 /* No 6-bit DAC */
-# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */
-# define KINETIS_NVREF 1 /* Voltage reference */
-# undef KINETIS_NTIMERS12 /* No 12 channel timers */
-# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
-# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
-# undef KINETIS_NTIMERS20 /* No 20 channel timers */
-# define KINETIS_NRTC 1 /* Real time clock */
-# undef KINETIS_NRNG /* No random number generator */
-# undef KINETIS_NMMCAU /* No hardware encryption */
-# undef KINETIS_NTAMPER /* No tamper detect */
-# define KINETIS_NCRC 1 /* CRC */
+# undef KINETIS_K20 /* Not Kinetis K20 family */
+# undef KINETIS_K40 /* Not Kinetis K40 family */
+# define KINETIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
+# undef KINETIS_K66 /* Not Kinetis K66 family */
+
+# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
+# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
+# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
+# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
+# define KINETIS_NUSBHOST 1 /* One USB host controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* SD host controller */
+# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
+# define KINETIS_NI2C 3 /* Three I2C modules */
+# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
+# define KINETIS_NUART 5 /* Five additional UARTs */
+# define KINETIS_NSPI 3 /* Three SPI modules */
+# define KINETIS_NCAN 2 /* Two CAN controllers */
+# define KINETIS_NI2S 2 /* Two I2S modules */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
+# define KINETIS_NADC16 4 /* Four 16-bit ADC */
+# undef KINETIS_NADC12 /* No 12-channel ADC */
+# undef KINETIS_NADC13 /* No 13-channel ADC */
+# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */
+# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */
+# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# undef KINETIS_NDAC6 /* No 6-bit DAC */
+# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# undef KINETIS_NTIMERS12 /* No 12 channel timers */
+# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
+# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
+# undef KINETIS_NTIMERS20 /* No 20 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# undef KINETIS_NRNG /* No random number generator */
+# undef KINETIS_NMMCAU /* No hardware encryption */
+# undef KINETIS_NTAMPER /* No tamper detect */
+# define KINETIS_NCRC 1 /* CRC */
#elif defined(CONFIG_ARCH_CHIP_MK60X256VMD100)
-# undef KINETIS_K20 /* Not Kinetis K20 family */
-# undef KINETIS_K40 /* Not Kinetics K40 family */
-# define KINETIS_K60 1 /* Kinetis K60 family */
-# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
-# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */
-# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
-# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */
-# define KINETIS_MPU 1 /* Memory protection unit */
-# define KINETIS_EXTBUS 1 /* External bus interface */
-# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
-# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
-# define KINETIS_NUSBHOST 1 /* One USB host controller */
-# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
-# define KINETIS_NUSBDEV 1 /* One USB device controller */
-# define KINETIS_NSDHC 1 /* SD host controller */
-# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
-# define KINETIS_NI2C 3 /* Three I2C modules */
-# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
-# define KINETIS_NUART 5 /* Five additional UARTs */
-# define KINETIS_NSPI 3 /* Three SPI modules */
-# define KINETIS_NCAN 2 /* Two CAN controllers */
-# define KINETIS_NI2S 2 /* Two I2S modules */
-# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
-# define KINETIS_NADC16 4 /* Four 16-bit ADC */
-# undef KINETIS_NADC12 /* No 12-channel ADC */
-# undef KINETIS_NADC13 /* No 13-channel ADC */
-# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */
-# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */
-# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
-# define KINETIS_NCMP 3 /* Three analog comparators */
-# undef KINETIS_NDAC6 /* No 6-bit DAC */
-# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */
-# define KINETIS_NVREF 1 /* Voltage reference */
-# undef KINETIS_NTIMERS12 /* No 12 channel timers */
-# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
-# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
-# undef KINETIS_NTIMERS20 /* No 20 channel timers */
-# define KINETIS_NRTC 1 /* Real time clock */
-# undef KINETIS_NRNG /* No random number generator */
-# undef KINETIS_NMMCAU /* No hardware encryption */
-# undef KINETIS_NTAMPER /* No tamper detect */
-# define KINETIS_NCRC 1 /* CRC */
+# undef KINETIS_K20 /* Not Kinetis K20 family */
+# undef KINETIS_K40 /* Not Kinetis K40 family */
+# define KINETIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
+# undef KINETIS_K66 /* Not Kinetis K66 family */
+
+# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
+# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */
+# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
+# define KINETIS_SRAM_SIZE (64*1024) /* 64Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
+# define KINETIS_NUSBHOST 1 /* One USB host controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* SD host controller */
+# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
+# define KINETIS_NI2C 3 /* Three I2C modules */
+# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
+# define KINETIS_NUART 5 /* Five additional UARTs */
+# define KINETIS_NSPI 3 /* Three SPI modules */
+# define KINETIS_NCAN 2 /* Two CAN controllers */
+# define KINETIS_NI2S 2 /* Two I2S modules */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
+# define KINETIS_NADC16 4 /* Four 16-bit ADC */
+# undef KINETIS_NADC12 /* No 12-channel ADC */
+# undef KINETIS_NADC13 /* No 13-channel ADC */
+# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */
+# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */
+# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# undef KINETIS_NDAC6 /* No 6-bit DAC */
+# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# undef KINETIS_NTIMERS12 /* No 12 channel timers */
+# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
+# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
+# undef KINETIS_NTIMERS20 /* No 20 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# undef KINETIS_NRNG /* No random number generator */
+# undef KINETIS_NMMCAU /* No hardware encryption */
+# undef KINETIS_NTAMPER /* No tamper detect */
+# define KINETIS_NCRC 1 /* CRC */
#elif defined(CONFIG_ARCH_CHIP_MK60N512VMD100)
-# undef KINETIS_K20 /* Not Kinetis K20 family */
-# undef KINETIS_K40 /* Not Kinetics K40 family */
-# define KINETIS_K60 1 /* Kinetis K60 family */
-# define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */
-# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
-# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
-# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */
-# define KINETIS_MPU 1 /* Memory protection unit */
-# define KINETIS_EXTBUS 1 /* External bus interface */
-# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
-# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
-# define KINETIS_NUSBHOST 1 /* One USB host controller */
-# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
-# define KINETIS_NUSBDEV 1 /* One USB device controller */
-# define KINETIS_NSDHC 1 /* SD host controller */
-# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
-# define KINETIS_NI2C 3 /* Three I2C modules */
-# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
-# define KINETIS_NUART 5 /* Five additional UARTs */
-# define KINETIS_NSPI 3 /* Three SPI modules */
-# define KINETIS_NCAN 2 /* Two CAN controllers */
-# define KINETIS_NI2S 2 /* Two I2S modules */
-# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
-# define KINETIS_NADC16 4 /* Four 16-bit ADC */
-# undef KINETIS_NADC12 /* No 12-channel ADC */
-# undef KINETIS_NADC13 /* No 13-channel ADC */
-# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */
-# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */
-# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
-# define KINETIS_NCMP 3 /* Three analog comparators */
-# undef KINETIS_NDAC6 /* No 6-bit DAC */
-# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */
-# define KINETIS_NVREF 1 /* Voltage reference */
-# undef KINETIS_NTIMERS12 /* No 12 channel timers */
-# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
-# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
-# undef KINETIS_NTIMERS20 /* No 20 channel timers */
-# define KINETIS_NRTC 1 /* Real time clock */
-# undef KINETIS_NRNG /* No random number generator */
-# undef KINETIS_NMMCAU /* No hardware encryption */
-# undef KINETIS_NTAMPER /* No tamper detect */
-# define KINETIS_NCRC 1 /* CRC */
+# undef KINETIS_K20 /* Not Kinetis K20 family */
+# undef KINETIS_K40 /* Not Kinetis K40 family */
+# define KINETIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
+# undef KINETIS_K66 /* Not Kinetis K66 family */
+
+# define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */
+# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
+# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
+# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
+# define KINETIS_NUSBHOST 1 /* One USB host controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* SD host controller */
+# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
+# define KINETIS_NI2C 3 /* Three I2C modules */
+# define KINETIS_NISO7816 1 /* One UART with ISO-786 */
+# define KINETIS_NUART 5 /* Five additional UARTs */
+# define KINETIS_NSPI 3 /* Three SPI modules */
+# define KINETIS_NCAN 2 /* Two CAN controllers */
+# define KINETIS_NI2S 2 /* Two I2S modules */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
+# define KINETIS_NADC16 4 /* Four 16-bit ADC */
+# undef KINETIS_NADC12 /* No 12-channel ADC */
+# undef KINETIS_NADC13 /* No 13-channel ADC */
+# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */
+# define KINETIS_NADC18 1 /* One 18-channel ADC (ADC1) */
+# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# undef KINETIS_NDAC6 /* No 6-bit DAC */
+# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# undef KINETIS_NTIMERS12 /* No 12 channel timers */
+# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
+# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
+# undef KINETIS_NTIMERS20 /* No 20 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# undef KINETIS_NRNG /* No random number generator */
+# undef KINETIS_NMMCAU /* No hardware encryption */
+# undef KINETIS_NTAMPER /* No tamper detect */
+# define KINETIS_NCRC 1 /* CRC */
+
+#elif defined(CONFIG_ARCH_CHIP_MK60FN1M0VLQ12)
+# undef KINETIS_K20 /* Not Kinetis K20 family */
+# undef KINETIS_K40 /* Not Kinetis K40 family */
+# define KINETIS_K60 1 /* Kinetis K60 family */
+# define KINETIS_NEW_MCG 1 /* Kinetis New MCG - different VDIV */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
+# undef KINETIS_K66 /* Not Kinetis K66 family */
+
+# define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */
+# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
+# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
+# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 32 /* Up to 32 DMA channels */
+# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
+# define KINETIS_NUSBHOST 1 /* One USB host controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* SD host controller */
+# define KINETIS_NTOUCHIF 1 /* Xtrinsic touch sensing interface */
+# define KINETIS_NI2C 3 /* Three I2C modules */
+# define KINETIS_NUART 6 /* Five additional UARTs */
+# define KINETIS_NSPI 3 /* Three SPI modules */
+# define KINETIS_NCAN 2 /* Two CAN controllers */
+# define KINETIS_NI2S 2 /* Two I2S modules */
+# define KINETIS_NADC16 4 /* Four 16-bit ADC */
+# define KINETIS_NADC15 1 /* One 15-channel ADC (ADC0) */
+# define KINETIS_NPGA 4 /* Four Programmable Gain Amplifiers */
+# define KINETIS_NCMP 4 /* Four analog comparators */
+# undef KINETIS_NDAC6 4 /* Four 6-bit DAC */
+# define KINETIS_NDAC12 2 /* Twp 12-bit DACs */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# define KINETIS_NTIMERS8 2 /* Two 8 channel timers */
+# define KINETIS_NTIMERS20 4 /* Four 20 channel timers */
+# define KINETIS_NTIMERS12 3 /* Three 12 channel timers */
+# define KINETIS_NTIMERS2 2 /* Two 2 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# define KINETIS_NRNG 1 /* Random number generator */
+# define KINETIS_NMMCAU 1 /* Hardware encryption */
+# undef KINETIS_NTAMPER /* No tamper detect */
+# define KINETIS_NCRC 1 /* CRC */
+#elif defined(CONFIG_ARCH_CHIP_MK64FN1M0VLL12)
+# undef KINETIS_K20 /* Not Kinetis K20 family */
+# undef KINETIS_K40 /* Not Kinetis K40 family */
+# undef KINETIS_K60 /* Not Kinetis K60 family */
+# define KINETIS_K64 1 /* Kinetis K64 family */
+# undef KINETIS_K66 /* Not Kinetis K66 family */
+
+# define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */
+# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
+# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
+# define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* SD host controller */
+# define KINETIS_NI2C 3 /* Three I2C modules */
+# define KINETIS_NUART 6 /* Six UART modues */
+# define KINETIS_NSPI 3 /* Three SPI modules */
+# define KINETIS_NCAN 1 /* One CAN controllers */
+# define KINETIS_NI2S 1 /* One I2S modules */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
+# define KINETIS_NADC16 2 /* Four 16-bit ADC */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
+# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# define KINETIS_NTIMERS8 2 /* Two 8 channel timers */
+# define KINETIS_NTIMERS2 2 /* Two 2 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# define KINETIS_NRNG 1 /* Random number generator */
+# define KINETIS_NMMCAU 1 /* Hardware encryption */
+# define KINETIS_NCRC 1 /* CRC */
+
+#elif defined(CONFIG_ARCH_CHIP_MK64FX512VLL12)
+# undef KINETIS_K20 /* Not Kinetis K20 family */
+# undef KINETIS_K40 /* Not Kinetis K40 family */
+# undef KINETIS_K60 /* Not Kinetis K60 family */
+# define KINETIS_K64 1 /* Kinetis K64 family */
+# undef KINETIS_K66 /* Not Kinetis K66 family */
+
+# define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */
+# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
+# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
+# define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* SD host controller */
+# define KINETIS_NI2C 3 /* Three I2C modules */
+# define KINETIS_NUART 6 /* Six UART modues */
+# define KINETIS_NSPI 3 /* Three SPI modules */
+# define KINETIS_NCAN 1 /* One CAN controllers */
+# define KINETIS_NI2S 1 /* One I2S modules */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
+# define KINETIS_NADC16 2 /* Four 16-bit ADC */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
+# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# define KINETIS_NTIMERS8 2 /* Two 8 channel timers */
+# define KINETIS_NTIMERS2 2 /* Two 2 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# define KINETIS_NRNG 1 /* Random number generator */
+# define KINETIS_NMMCAU 1 /* Hardware encryption */
+# define KINETIS_NCRC 1 /* CRC */
+
+#elif defined(CONFIG_ARCH_CHIP_MK64FX512VDC12)
+# undef KINETIS_K20 /* Not Kinetis K20 family */
+# undef KINETIS_K40 /* Not Kinetis K40 family */
+# undef KINETIS_K60 /* Not Kinetis K60 family */
+# define KINETIS_K64 1 /* Kinetis K64 family */
+# undef KINETIS_K66 /* Not Kinetis K66 family */
+
+# define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */
+# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
+# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
+# define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* SD host controller */
+# define KINETIS_NI2C 3 /* Three I2C modules */
+# define KINETIS_NUART 6 /* Six UART modues */
+# define KINETIS_NSPI 3 Three SPI modules
+# define KINETIS_NCAN 1 /* One CAN controllers */
+# define KINETIS_NI2S 1 /* One I2S modules */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
+# define KINETIS_NADC16 2 /* Four 16-bit ADC */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
+# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# define KINETIS_NTIMERS8 2 /* Two 8 channel timers */
+# define KINETIS_NTIMERS2 2 /* Two 2 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# define KINETIS_NRNG 1 /* Random number generator */
+# define KINETIS_NMMCAU 1 /* Hardware encryption */
+# define KINETIS_NCRC 1 /* CRC */
+
+#elif defined(CONFIG_ARCH_CHIP_MK64FN1M0VDC12)
+# undef KINETIS_K20 /* Not Kinetis K20 family */
+# undef KINETIS_K40 /* Not Kinetis K40 family */
+# undef KINETIS_K60 /* Not Kinetis K60 family */
+# define KINETIS_K64 1 /* Kinetis K64 family */
+# undef KINETIS_K66 /* Not Kinetis K66 family */
+
+# define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */
+# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
+# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
+# define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* SD host controller */
+# define KINETIS_NI2C 3 /* Three I2C modules */
+# define KINETIS_NUART 6 /* Six UART modues */
+# define KINETIS_NSPI 3 Three SPI modules
+# define KINETIS_NCAN 1 /* One CAN controllers */
+# define KINETIS_NI2S 1 /* One I2S modules */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
+# define KINETIS_NADC16 2 /* Four 16-bit ADC */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
+# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# define KINETIS_NTIMERS8 2 /* Two 8 channel timers */
+# define KINETIS_NTIMERS2 2 /* Two 2 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# define KINETIS_NRNG 1 /* Random number generator */
+# define KINETIS_NMMCAU 1 /* Hardware encryption */
+# define KINETIS_NCRC 1 /* CRC */
+
+#elif defined(CONFIG_ARCH_CHIP_MK64FX512VLQ12)
+# undef KINETIS_K20 /* Not Kinetis K20 family */
+# undef KINETIS_K40 /* Not Kinetis K40 family */
+# undef KINETIS_K60 /* Not Kinetis K60 family */
+# define KINETIS_K64 1 /* Kinetis K64 family */
+# undef KINETIS_K66 /* Not Kinetis K66 family */
+
+# define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */
+# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
+# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
+# define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* SD host controller */
+# define KINETIS_NI2C 3 /* Three I2C modules */
+# define KINETIS_NUART 6 /* Six UART modues */
+# define KINETIS_NSPI 3 /* Three SPI modules */
+# define KINETIS_NCAN 1 /* One CAN controllers */
+# define KINETIS_NI2S 1 /* One I2S modules */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
+# define KINETIS_NADC16 2 /* Four 16-bit ADC */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
+# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# define KINETIS_NTIMERS8 2 /* Two 8 channel timers */
+# define KINETIS_NTIMERS2 2 /* Two 2 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# define KINETIS_NRNG 1 /* Random number generator */
+# define KINETIS_NMMCAU 1 /* Hardware encryption */
+# define KINETIS_NCRC 1 /* CRC */
+
+#elif defined(CONFIG_ARCH_CHIP_MK64FN1M0VLQ12)
+# undef KINETIS_K20 /* Not Kinetis K20 family */
+# undef KINETIS_K40 /* Not Kinetis K40 family */
+# undef KINETIS_K60 /* Not Kinetis K60 family */
+# define KINETIS_K64 1 /* Kinetis K64 family */
+# undef KINETIS_K66 /* Not Kinetis K66 family */
+
+# define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */
+# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
+# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
+# define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* SD host controller */
+# define KINETIS_NI2C 3 /* Three I2C modules */
+# define KINETIS_NUART 6 /* Six UART modues */
+# define KINETIS_NSPI 3 /* Three SPI modules */
+# define KINETIS_NCAN 1 /* One CAN controllers */
+# define KINETIS_NI2S 1 /* One I2S modules */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
+# define KINETIS_NADC16 2 /* Four 16-bit ADC */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
+# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# define KINETIS_NTIMERS8 2 /* Two 8 channel timers */
+# define KINETIS_NTIMERS2 2 /* Two 2 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# define KINETIS_NRNG 1 /* Random number generator */
+# define KINETIS_NMMCAU 1 /* Hardware encryption */
+# define KINETIS_NCRC 1 /* CRC */
+
+#elif defined(CONFIG_ARCH_CHIP_MK64FX512VMD12)
+# undef KINETIS_K20 /* Not Kinetis K20 family */
+# undef KINETIS_K40 /* Not Kinetis K40 family */
+# undef KINETIS_K60 /* Not Kinetis K60 family */
+# define KINETIS_K64 1 /* Kinetis K64 family */
+# undef KINETIS_K66 /* Not Kinetis K66 family */
+
+# define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */
+# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
+# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
+# define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* SD host controller */
+# define KINETIS_NI2C 3 /* Three I2C modules */
+# define KINETIS_NUART 6 /* Six UART modues */
+# define KINETIS_NSPI 3 /* Three SPI modules */
+# define KINETIS_NCAN 1 /* One CAN controllers */
+# define KINETIS_NI2S 1 /* One I2S modules */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
+# define KINETIS_NADC16 2 /* Four 16-bit ADC */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
+# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# define KINETIS_NTIMERS8 2 /* Two 8 channel timers */
+# define KINETIS_NTIMERS2 2 /* Two 2 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# define KINETIS_NRNG 1 /* Random number generator */
+# define KINETIS_NMMCAU 1 /* Hardware encryption */
+# define KINETIS_NCRC 1 /* CRC */
+
+#elif defined(CONFIG_ARCH_CHIP_MK64FN1M0VMD12)
+# undef KINETIS_K20 /* Not Kinetis K20 family */
+# undef KINETIS_K40 /* Not Kinetis K40 family */
+# undef KINETIS_K60 /* Not Kinetis K60 family */
+# define KINETIS_K64 1 /* Kinetis K64 family */
+# undef KINETIS_K66 /* Not Kinetis K66 family */
+
+# define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */
+# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
+# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
+# define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */
+# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* SD host controller */
+# define KINETIS_NI2C 3 /* Three I2C modules */
+# define KINETIS_NUART 6 /* Six UART modues */
+# define KINETIS_NSPI 3 /* Three SPI modules */
+# define KINETIS_NCAN 1 /* One CAN controllers */
+# define KINETIS_NI2S 1 /* One I2S modules */
+# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */
+# define KINETIS_NADC16 2 /* Four 16-bit ADC */
+# define KINETIS_NCMP 3 /* Three analog comparators */
+# define KINETIS_NDAC6 3 /* Three 6-bit DAC */
+# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# define KINETIS_NTIMERS8 2 /* Two 8 channel timers */
+# define KINETIS_NTIMERS2 2 /* Two 2 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# define KINETIS_NRNG 1 /* Random number generator */
+# define KINETIS_NMMCAU 1 /* Hardware encryption */
+# define KINETIS_NCRC 1 /* CRC */
+
+/* MK66F N/X 1M0/2M0 V MD/LQ 18
+ *
+ * --------------- ------- --- ------- ------- ------ ------ ------ -----
+ * PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO
+ * FREQ CNT FLASH FLASH
+ * --------------- ------- --- ------- ------- ------ ------ ------ -----
+ * MK66FN2M0VMD18 180 MHz 144 MAPBGA 2 MB — — KB 260 KB 100
+ * MK66FX1M0VMD18 180 MHz 144 MAPBGA 1.25 MB 1 MB 4 KB 256 KB 100
+ * MK66FN2M0VLQ18 180 MHz 144 LQFP 2 MB — — KB 260 KB 100
+ * MK66FX1M0VLQ18 180 MHz 144 LQFP 1.25 MB 1 MB 4 KB 256 KB 100
+ */
+
+#elif defined(CONFIG_ARCH_CHIP_MK66FN2M0VMD18) || \
+ defined(CONFIG_ARCH_CHIP_MK66FX1M0VMD18) || \
+ defined(CONFIG_ARCH_CHIP_MK66FN2M0VLQ18) || \
+ defined(CONFIG_ARCH_CHIP_MK66FX1M0VLQ18)
+# undef KINETIS_K20 /* Not Kinetis K20 family */
+# undef KINETIS_K40 /* Not Kinetis K40 family */
+# undef KINETIS_K60 /* Not Kinetis K60 family */
+# undef KINETIS_K64 /* Not Kinetis K64 family */
+# define KINETIS_K66 1 /* Kinetis K66 family */
+
+# if defined(CONFIG_ARCH_CHIP_MK66FX1M0VMD18) || \
+ defined(CONFIG_ARCH_CHIP_MK66FX1M0VLQ18)
+# define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */
+# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */
+# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
+# define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */
+# endif
+# if defined(CONFIG_ARCH_CHIP_MK66FN2M0VMD18) || \
+ defined(CONFIG_ARCH_CHIP_MK66FN2M0VLQ18)
+# define KINETIS_FLASH_SIZE (2048*1024) /* 2Mb */
+# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
+# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
+# define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */
+# endif
+# define KINETIS_MPU 1 /* Memory protection unit */
+# define KINETIS_EXTBUS 1 /* External bus interface */
+# define KINETIS_NDMACH 32 /* Up to 32 DMA channels */
+# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */
+# define KINETIS_NUSBOTG 1 /* With USB OTG controller */
+# define KINETIS_NUSBDEV 1 /* One USB device controller */
+# define KINETIS_NSDHC 1 /* SD host controller */
+# define KINETIS_NI2C 4 /* Four I2C modules */
+# define KINETIS_NUART 5 /* Five UART modules */
+# define KINETIS_NLPUART 1 /* One LPUART modules */
+# define KINETIS_NSPI 3 /* Three SPI modules */
+# define KINETIS_NCAN 2 /* Two CAN controllers */
+# define KINETIS_NI2S 1 /* One I2S modules */
+# undef KINETIS_NSLCD /* No segment LCD interface */
+# define KINETIS_NADC16 2 /* Four 16-bit ADC */
+# define KINETIS_NCMP 4 /* Four analog comparators */
+# define KINETIS_NDAC6 4 /* Four 6-bit DAC */
+# define KINETIS_NDAC12 2 /* Two 12-bit DAC */
+# define KINETIS_NVREF 1 /* Voltage reference */
+# define KINETIS_NTIMERS8 2 /* ? Two 8 channel timers */
+# define KINETIS_NTIMERS2 2 /* ? Two 2 channel timers */
+# define KINETIS_NRTC 1 /* Real time clock */
+# define KINETIS_NRNG 1 /* Random number generator */
+# define KINETIS_NMMCAU 1 /* Hardware encryption */
+# define KINETIS_NCRC 1 /* CRC */
#else
# error "Unsupported Kinetis chip"
#endif
diff --git a/arch/arm/include/kinetis/irq.h b/arch/arm/include/kinetis/irq.h
index 3355f29b02cf2dcaa2570722632ddea9bd1c57a9..6eb5f00a7ce5329430ab475a43c6dde2ecc817f6 100644
--- a/arch/arm/include/kinetis/irq.h
+++ b/arch/arm/include/kinetis/irq.h
@@ -1,8 +1,9 @@
-/************************************************************************************
+/****************************************************************************
* arch/arm/include/kinetis/irq.h
*
- * Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt
+ * Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt
+ * David Sidrane
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -31,10 +32,10 @@
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
- ************************************************************************************/
+ ****************************************************************************/
-/* This file should never be included directed but, rather, only indirectly through
- * nuttx/irq.h
+/* This file should never be included directed but, rather, only indirectly
+ * through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_KINETIS_IRQ_H
@@ -50,15 +51,15 @@
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
-/* IRQ numbers **********************************************************************/
-/* The IRQ numbers corresponds directly to vector numbers and hence map directly to
+
+/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in the IRQ
* to handle mapping tables.
*/
/* Processor Exceptions (vectors 0-15) */
-#define KINETIS_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+#define KINETIS_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define KINETIS_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
@@ -73,316 +74,20 @@
#define KINETIS_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define KINETIS_IRQ_SYSTICK (15) /* Vector 15: System tick */
-/* External interrupts (vectors >= 16) */
-
-#define KINETIS_IRQ_EXTINT (16)
-
-/* K20 Family ***********************************************************************
- *
- * The interrupt vectors for the following parts is defined in Freescale document
- * K20P64M72SF1RM
- */
-
-#if defined(CONFIG_ARCH_CHIP_MK20DX256VLH7)
-# define KINETIS_IRQ_DMACH0 (16) /* Vector 16: DMA channel 0 transfer complete */
-# define KINETIS_IRQ_DMACH1 (17) /* Vector 17: DMA channel 1 transfer complete */
-# define KINETIS_IRQ_DMACH2 (18) /* Vector 18: DMA channel 2 transfer complete */
-# define KINETIS_IRQ_DMACH3 (19) /* Vector 19: DMA channel 3 transfer complete */
-# define KINETIS_IRQ_DMACH4 (20) /* Vector 20: DMA channel 4 transfer complete */
-# define KINETIS_IRQ_DMACH5 (21) /* Vector 21: DMA channel 5 transfer complete */
-# define KINETIS_IRQ_DMACH6 (22) /* Vector 22: DMA channel 6 transfer complete */
-# define KINETIS_IRQ_DMACH7 (23) /* Vector 23: DMA channel 7 transfer complete */
-# define KINETIS_IRQ_DMACH8 (24) /* Vector 24: DMA channel 8 transfer complete */
-# define KINETIS_IRQ_DMACH9 (25) /* Vector 25: DMA channel 9 transfer complete */
-# define KINETIS_IRQ_DMACH10 (26) /* Vector 26: DMA channel 10 transfer complete */
-# define KINETIS_IRQ_DMACH11 (27) /* Vector 27: DMA channel 11 transfer complete */
-# define KINETIS_IRQ_DMACH12 (28) /* Vector 28: DMA channel 12 transfer complete */
-# define KINETIS_IRQ_DMACH13 (29) /* Vector 29: DMA channel 13 transfer complete */
-# define KINETIS_IRQ_DMACH14 (30) /* Vector 30: DMA channel 14 transfer complete */
-# define KINETIS_IRQ_DMACH15 (31) /* Vector 31: DMA channel 15 transfer complete */
-# define KINETIS_IRQ_DMAERR (32) /* Vector 32: DMA error interrupt channels 0-15 */
-# define KINETIS_IRQ_FLASHCC (34) /* Vector 34: Flash memory command complete */
-# define KINETIS_IRQ_FLASHRC (35) /* Vector 35: Flash memory read collision */
-# define KINETIS_IRQ_SMCLVD (36) /* Vector 36: Mode Controller low-voltage
- * detect, low-voltage warning */
-# define KINETIS_IRQ_LLWU (37) /* Vector 37: LLWU Normal Low Leakage Wakeup */
-# define KINETIS_IRQ_WDOG (38) /* Vector 38: Watchdog */
-# define KINETIS_IRQ_I2C0 (40) /* Vector 40: I2C0 */
-# define KINETIS_IRQ_I2C1 (41) /* Vector 41: I2C1 */
-# define KINETIS_IRQ_SPI0 (42) /* Vector 42: SPI0 all sources */
-# define KINETIS_IRQ_SPI1 (43) /* Vector 43: SPI1 all sources */
-# define KINETIS_IRQ_CAN0MB (45) /* Vector 45: CAN0 OR'ed Message buffer (0-15) */
-# define KINETIS_IRQ_CAN0BO (46) /* Vector 46: CAN0 Bus Off */
-# define KINETIS_IRQ_CAN0ERR (47) /* Vector 47: CAN0 Error */
-# define KINETIS_IRQ_CAN0TW (48) /* Vector 48: CAN0 Transmit Warning */
-# define KINETIS_IRQ_CAN0RW (49) /* Vector 49: CAN0 Receive Warning */
-# define KINETIS_IRQ_CAN0WU (50) /* Vector 50: CAN0 Wake UP */
-//TODO UART0_LON
-# define KINETIS_IRQ_UART0S (61) /* Vector 61: UART0 status */
-# define KINETIS_IRQ_UART0E (62) /* Vector 62: UART0 error */
-# define KINETIS_IRQ_UART1S (63) /* Vector 63: UART1 status */
-# define KINETIS_IRQ_UART1E (64) /* Vector 64: UART1 error */
-# define KINETIS_IRQ_UART2S (65) /* Vector 65: UART2 status */
-# define KINETIS_IRQ_UART2E (66) /* Vector 66: UART2 error */
-# define KINETIS_IRQ_ADC0 (73) /* Vector 73: ADC0 */
-# define KINETIS_IRQ_ADC1 (74) /* Vector 74: ADC1 */
-# define KINETIS_IRQ_CMP0 (75) /* Vector 75: CMP0 */
-# define KINETIS_IRQ_CMP1 (76) /* Vector 76: CMP1 */
-# define KINETIS_IRQ_CMP2 (77) /* Vector 77: CMP2 */
-# define KINETIS_IRQ_FTM0 (78) /* Vector 78: FTM0 all sources */
-# define KINETIS_IRQ_FTM1 (79) /* Vector 79: FTM1 all sources */
-# define KINETIS_IRQ_FTM2 (80) /* Vector 80: FTM2 all sources */
-# define KINETIS_IRQ_CMT (81) /* Vector 81: CMT */
-# define KINETIS_IRQ_RTC (82) /* Vector 82: RTC alarm interrupt */
-//TODO RTC_SECOND
-# define KINETIS_IRQ_PITCH0 (84) /* Vector 84: PIT channel 0 */
-# define KINETIS_IRQ_PITCH1 (85) /* Vector 85: PIT channel 1 */
-# define KINETIS_IRQ_PITCH2 (86) /* Vector 86: PIT channel 2 */
-# define KINETIS_IRQ_PITCH3 (87) /* Vector 87: PIT channel 3 */
-# define KINETIS_IRQ_PDB (88) /* Vector 88: PDB */
-# define KINETIS_IRQ_USBOTG (89) /* Vector 88: USB OTG */
-# define KINETIS_IRQ_USBCD (90) /* Vector 90: USB charger detect */
-# define KINETIS_IRQ_DAC0 (97) /* Vector 97: DAC0 */
-# define KINETIS_IRQ_TSI (99) /* Vector 97: TSI all sources */
-# define KINETIS_IRQ_MCG (100) /* Vector 100: MCG */
-# define KINETIS_IRQ_LPT (101) /* Vector 101: Low power timer */
-# define KINETIS_IRQ_PORTA (103) /* Vector 103: Pin detect port A */
-# define KINETIS_IRQ_PORTB (104) /* Vector 104: Pin detect port B */
-# define KINETIS_IRQ_PORTC (105) /* Vector 105: Pin detect port C */
-# define KINETIS_IRQ_PORTD (106) /* Vector 106: Pin detect port D */
-# define KINETIS_IRQ_PORTE (107) /* Vector 107: Pin detect port E */
-# define KINETIS_IRQ_SWI (110) /* Vector 110: Software interrupt */
-
-# define NR_VECTORS (111) /* 111 vectors */
-# define NR_IRQS (111) /* 94 interrupts but 111 IRQ numbers */
-
-/* K40 Family ***********************************************************************
- *
- * The interrupt vectors for the following parts is defined in Freescale document
- * K40P144M100SF2RM
- */
-
-#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) || \
- defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100) || \
- defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100)
-
-# define KINETIS_IRQ_DMACH0 (16) /* Vector 16: DMA channel 0 transfer complete */
-# define KINETIS_IRQ_DMACH1 (17) /* Vector 17: DMA channel 1 transfer complete */
-# define KINETIS_IRQ_DMACH2 (18) /* Vector 18: DMA channel 2 transfer complete */
-# define KINETIS_IRQ_DMACH3 (19) /* Vector 19: DMA channel 3 transfer complete */
-# define KINETIS_IRQ_DMACH4 (20) /* Vector 20: DMA channel 4 transfer complete */
-# define KINETIS_IRQ_DMACH5 (21) /* Vector 21: DMA channel 5 transfer complete */
-# define KINETIS_IRQ_DMACH6 (22) /* Vector 22: DMA channel 6 transfer complete */
-# define KINETIS_IRQ_DMACH7 (23) /* Vector 23: DMA channel 7 transfer complete */
-# define KINETIS_IRQ_DMACH8 (24) /* Vector 24: DMA channel 8 transfer complete */
-# define KINETIS_IRQ_DMACH9 (25) /* Vector 25: DMA channel 9 transfer complete */
-# define KINETIS_IRQ_DMACH10 (26) /* Vector 26: DMA channel 10 transfer complete */
-# define KINETIS_IRQ_DMACH11 (27) /* Vector 27: DMA channel 11 transfer complete */
-# define KINETIS_IRQ_DMACH12 (28) /* Vector 28: DMA channel 12 transfer complete */
-# define KINETIS_IRQ_DMACH13 (29) /* Vector 29: DMA channel 13 transfer complete */
-# define KINETIS_IRQ_DMACH14 (30) /* Vector 30: DMA channel 14 transfer complete */
-# define KINETIS_IRQ_DMACH15 (31) /* Vector 31: DMA channel 15 transfer complete */
-# define KINETIS_IRQ_DMAERR (32) /* Vector 32: DMA error interrupt channels 0-15 */
-# define KINETIS_IRQ_MCM (33) /* Vector 33: MCM Normal interrupt */
-# define KINETIS_IRQ_FLASHCC (34) /* Vector 34: Flash memory command complete */
-# define KINETIS_IRQ_FLASHRC (35) /* Vector 35: Flash memory read collision */
-# define KINETIS_IRQ_SMCLVD (36) /* Vector 36: Mode Controller low-voltage
- * detect, low-voltage warning */
-# define KINETIS_IRQ_LLWU (37) /* Vector 37: LLWU Normal Low Leakage Wakeup */
-# define KINETIS_IRQ_WDOG (38) /* Vector 38: Watchdog */
- /* Vector 39: Reserved */
-# define KINETIS_IRQ_I2C0 (40) /* Vector 40: I2C0 */
-# define KINETIS_IRQ_I2C1 (41) /* Vector 41: I2C1 */
-# define KINETIS_IRQ_SPI0 (42) /* Vector 42: SPI0 all sources */
-# define KINETIS_IRQ_SPI1 (43) /* Vector 43: SPI1 all sources */
-# define KINETIS_IRQ_SPI2 (44) /* Vector 44: SPI2 all sources */
-# define KINETIS_IRQ_CAN0MB (45) /* Vector 45: CAN0 OR'ed Message buffer (0-15) */
-# define KINETIS_IRQ_CAN0BO (46) /* Vector 46: CAN0 Bus Off */
-# define KINETIS_IRQ_CAN0ERR (47) /* Vector 47: CAN0 Error */
-# define KINETIS_IRQ_CAN0TW (48) /* Vector 48: CAN0 Transmit Warning */
-# define KINETIS_IRQ_CAN0RW (49) /* Vector 49: CAN0 Receive Warning */
-# define KINETIS_IRQ_CAN0WU (50) /* Vector 50: CAN0 Wake UP */
- /* Vectors 51-52: Reserved */
-# define KINETIS_IRQ_CAN1MB (53) /* Vector 53: CAN1 OR'ed Message buffer (0-15) */
-# define KINETIS_IRQ_CAN1BO (54) /* Vector 54: CAN1 Bus Off */
-# define KINETIS_IRQ_CAN1ERR (55) /* Vector 55: CAN1 Error */
-# define KINETIS_IRQ_CAN1TW (56) /* Vector 56: CAN1 Transmit Warning */
-# define KINETIS_IRQ_CAN1RW (57) /* Vector 57: CAN1 Receive Warning */
-# define KINETIS_IRQ_CAN1WU (58) /* Vector 58: CAN1 Wake UP */
- /* Vectors 59-60: Reserved */
-# define KINETIS_IRQ_UART0S (61) /* Vector 61: UART0 status */
-# define KINETIS_IRQ_UART0E (62) /* Vector 62: UART0 error */
-# define KINETIS_IRQ_UART1S (63) /* Vector 63: UART1 status */
-# define KINETIS_IRQ_UART1E (64) /* Vector 64: UART1 error */
-# define KINETIS_IRQ_UART2S (65) /* Vector 65: UART2 status */
-# define KINETIS_IRQ_UART2E (66) /* Vector 66: UART2 error */
-# define KINETIS_IRQ_UART3S (67) /* Vector 67: UART3 status */
-# define KINETIS_IRQ_UART3E (68) /* Vector 68: UART3 error */
-# define KINETIS_IRQ_UART4S (69) /* Vector 69: UART4 status */
-# define KINETIS_IRQ_UART4E (70) /* Vector 70: UART4 error */
-# define KINETIS_IRQ_UART5S (71) /* Vector 71: UART5 status */
-# define KINETIS_IRQ_UART5E (72) /* Vector 72: UART5 error */
-# define KINETIS_IRQ_ADC0 (73) /* Vector 73: ADC0 */
-# define KINETIS_IRQ_ADC1 (74) /* Vector 74: ADC1 */
-# define KINETIS_IRQ_CMP0 (75) /* Vector 75: CMP0 */
-# define KINETIS_IRQ_CMP1 (76) /* Vector 76: CMP1 */
-# define KINETIS_IRQ_CMP2 (77) /* Vector 77: CMP2 */
-# define KINETIS_IRQ_FTM0 (78) /* Vector 78: FTM0 all sources */
-# define KINETIS_IRQ_FTM1 (79) /* Vector 79: FTM1 all sources */
-# define KINETIS_IRQ_FTM2 (80) /* Vector 80: FTM2 all sources */
-# define KINETIS_IRQ_CMT (81) /* Vector 81: CMT */
-# define KINETIS_IRQ_RTC (82) /* Vector 82: RTC alarm interrupt */
- /* Vector 83: Reserved */
-# define KINETIS_IRQ_PITCH0 (84) /* Vector 84: PIT channel 0 */
-# define KINETIS_IRQ_PITCH1 (85) /* Vector 85: PIT channel 1 */
-# define KINETIS_IRQ_PITCH2 (86) /* Vector 86: PIT channel 2 */
-# define KINETIS_IRQ_PITCH3 (87) /* Vector 87: PIT channel 3 */
-# define KINETIS_IRQ_PDB (88) /* Vector 88: PDB */
-# define KINETIS_IRQ_USBOTG (89) /* Vector 88: USB OTG */
-# define KINETIS_IRQ_USBCD (90) /* Vector 90: USB charger detect */
- /* Vectors 91-94: Reserved */
-# define KINETIS_IRQ_I2S0 (95) /* Vector 95: I2S0 */
-# define KINETIS_IRQ_SDHC (96) /* Vector 96: SDHC */
-# define KINETIS_IRQ_DAC0 (97) /* Vector 97: DAC0 */
-# define KINETIS_IRQ_DAC1 (98) /* Vector 98: DAC1 */
-# define KINETIS_IRQ_TSI (99) /* Vector 97: TSI all sources */
-# define KINETIS_IRQ_MCG (100) /* Vector 100: MCG */
-# define KINETIS_IRQ_LPT (101) /* Vector 101: Low power timer */
-# define KINETIS_IRQ_SLCD (102) /* Vector 102: Segment LCD all sources */
-# define KINETIS_IRQ_PORTA (103) /* Vector 103: Pin detect port A */
-# define KINETIS_IRQ_PORTB (104) /* Vector 104: Pin detect port B */
-# define KINETIS_IRQ_PORTC (105) /* Vector 105: Pin detect port C */
-# define KINETIS_IRQ_PORTD (106) /* Vector 106: Pin detect port D */
-# define KINETIS_IRQ_PORTE (107) /* Vector 107: Pin detect port E */
- /* Vectors 108-109: Reserved */
-# define KINETIS_IRQ_SWI (110) /* Vector 110: Software interrupt */
-
-/* Note that the total number of IRQ numbers supported is equal to the number of
- * valid interrupt vectors. This is wasteful in that certain tables are sized by
- * this value. There are only 94 valid interrupts so, potentially the numver of
- * IRQs to could be reduced to 94. However, equating IRQ numbers with vector numbers
- * also simplifies operations on NVIC registers and (at least in my state of mind
- * now) seems to justify the waste.
- */
-
-# define NR_VECTORS (111) /* 111 vectors */
-# define NR_IRQS (111) /* 94 interrupts but 111 IRQ numbers */
-
-/* K60 Family ***********************************************************************
- *
- * The memory map for the following parts is defined in Freescale document
- * K60P144M100SF2RM
- */
-
-#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100) || defined(CONFIG_ARCH_CHIP_MK60X256VLQ100) || \
- defined(CONFIG_ARCH_CHIP_MK60N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK60N256VMD100) || \
- defined(CONFIG_ARCH_CHIP_MK60X256VMD100) || defined(CONFIG_ARCH_CHIP_MK60N512VMD100) || \
- defined(CONFIG_ARCH_CHIP_MK60N512VLL100)
-
-# define KINETIS_IRQ_DMACH0 (16) /* Vector 16: DMA channel 0 transfer complete */
-# define KINETIS_IRQ_DMACH1 (17) /* Vector 17: DMA channel 1 transfer complete */
-# define KINETIS_IRQ_DMACH2 (18) /* Vector 18: DMA channel 2 transfer complete */
-# define KINETIS_IRQ_DMACH3 (19) /* Vector 19: DMA channel 3 transfer complete */
-# define KINETIS_IRQ_DMACH4 (20) /* Vector 20: DMA channel 4 transfer complete */
-# define KINETIS_IRQ_DMACH5 (21) /* Vector 21: DMA channel 5 transfer complete */
-# define KINETIS_IRQ_DMACH6 (22) /* Vector 22: DMA channel 6 transfer complete */
-# define KINETIS_IRQ_DMACH7 (23) /* Vector 23: DMA channel 7 transfer complete */
-# define KINETIS_IRQ_DMACH8 (24) /* Vector 24: DMA channel 8 transfer complete */
-# define KINETIS_IRQ_DMACH9 (25) /* Vector 25: DMA channel 9 transfer complete */
-# define KINETIS_IRQ_DMACH10 (26) /* Vector 26: DMA channel 10 transfer complete */
-# define KINETIS_IRQ_DMACH11 (27) /* Vector 27: DMA channel 11 transfer complete */
-# define KINETIS_IRQ_DMACH12 (28) /* Vector 28: DMA channel 12 transfer complete */
-# define KINETIS_IRQ_DMACH13 (29) /* Vector 29: DMA channel 13 transfer complete */
-# define KINETIS_IRQ_DMACH14 (30) /* Vector 30: DMA channel 14 transfer complete */
-# define KINETIS_IRQ_DMACH15 (31) /* Vector 31: DMA channel 15 transfer complete */
-# define KINETIS_IRQ_DMAERR (32) /* Vector 32: DMA error interrupt channels 0-15 */
-# define KINETIS_IRQ_MCM (33) /* Vector 33: MCM Normal interrupt */
-# define KINETIS_IRQ_FLASHCC (34) /* Vector 34: Flash memory command complete */
-# define KINETIS_IRQ_FLASHRC (35) /* Vector 35: Flash memory read collision */
-# define KINETIS_IRQ_SMCLVD (36) /* Vector 36: Mode Controller low-voltage
- * detect, low-voltage warning */
-# define KINETIS_IRQ_LLWU (37) /* Vector 37: LLWU Normal Low Leakage Wakeup */
-# define KINETIS_IRQ_WDOG (38) /* Vector 38: Watchdog */
-# define KINETIS_IRQ_RNGB (39) /* Vector 39: Random number generator */
-# define KINETIS_IRQ_I2C0 (40) /* Vector 40: I2C0 */
-# define KINETIS_IRQ_I2C1 (41) /* Vector 41: I2C1 */
-# define KINETIS_IRQ_SPI0 (42) /* Vector 42: SPI0 all sources */
-# define KINETIS_IRQ_SPI1 (43) /* Vector 43: SPI1 all sources */
-# define KINETIS_IRQ_SPI2 (44) /* Vector 44: SPI2 all sources */
-# define KINETIS_IRQ_CAN0MB (45) /* Vector 45: CAN0 OR'ed Message buffer (0-15) */
-# define KINETIS_IRQ_CAN0BO (46) /* Vector 46: CAN0 Bus Off */
-# define KINETIS_IRQ_CAN0ERR (47) /* Vector 47: CAN0 Error */
-# define KINETIS_IRQ_CAN0TW (48) /* Vector 48: CAN0 Transmit Warning */
-# define KINETIS_IRQ_CAN0RW (49) /* Vector 49: CAN0 Receive Warning */
-# define KINETIS_IRQ_CAN0WU (50) /* Vector 50: CAN0 Wake UP */
- /* Vectors 51-52: Reserved */
-# define KINETIS_IRQ_CAN1MB (53) /* Vector 53: CAN1 OR'ed Message buffer (0-15) */
-# define KINETIS_IRQ_CAN1BO (54) /* Vector 54: CAN1 Bus Off */
-# define KINETIS_IRQ_CAN1ERR (55) /* Vector 55: CAN1 Error */
-# define KINETIS_IRQ_CAN1TW (56) /* Vector 56: CAN1 Transmit Warning */
-# define KINETIS_IRQ_CAN1RW (57) /* Vector 57: CAN1 Receive Warning */
-# define KINETIS_IRQ_CAN1WU (58) /* Vector 58: CAN1 Wake UP */
- /* Vectors 59-60: Reserved */
-# define KINETIS_IRQ_UART0S (61) /* Vector 61: UART0 status */
-# define KINETIS_IRQ_UART0E (62) /* Vector 62: UART0 error */
-# define KINETIS_IRQ_UART1S (63) /* Vector 63: UART1 status */
-# define KINETIS_IRQ_UART1E (64) /* Vector 64: UART1 error */
-# define KINETIS_IRQ_UART2S (65) /* Vector 65: UART2 status */
-# define KINETIS_IRQ_UART2E (66) /* Vector 66: UART2 error */
-# define KINETIS_IRQ_UART3S (67) /* Vector 67: UART3 status */
-# define KINETIS_IRQ_UART3E (68) /* Vector 68: UART3 error */
-# define KINETIS_IRQ_UART4S (69) /* Vector 69: UART4 status */
-# define KINETIS_IRQ_UART4E (70) /* Vector 70: UART4 error */
-# define KINETIS_IRQ_UART5S (71) /* Vector 71: UART5 status */
-# define KINETIS_IRQ_UART5E (72) /* Vector 72: UART5 error */
-# define KINETIS_IRQ_ADC0 (73) /* Vector 73: ADC0 */
-# define KINETIS_IRQ_ADC1 (74) /* Vector 74: ADC1 */
-# define KINETIS_IRQ_CMP0 (75) /* Vector 75: CMP0 */
-# define KINETIS_IRQ_CMP1 (76) /* Vector 76: CMP1 */
-# define KINETIS_IRQ_CMP2 (77) /* Vector 77: CMP2 */
-# define KINETIS_IRQ_FTM0 (78) /* Vector 78: FTM0 all sources */
-# define KINETIS_IRQ_FTM1 (79) /* Vector 79: FTM1 all sources */
-# define KINETIS_IRQ_FTM2 (80) /* Vector 80: FTM2 all sources */
-# define KINETIS_IRQ_CMT (81) /* Vector 81: CMT */
-# define KINETIS_IRQ_RTC (82) /* Vector 82: RTC alarm interrupt */
- /* Vector 83: Reserved */
-# define KINETIS_IRQ_PITCH0 (84) /* Vector 84: PIT channel 0 */
-# define KINETIS_IRQ_PITCH1 (85) /* Vector 85: PIT channel 1 */
-# define KINETIS_IRQ_PITCH2 (86) /* Vector 86: PIT channel 2 */
-# define KINETIS_IRQ_PITCH3 (87) /* Vector 87: PIT channel 3 */
-# define KINETIS_IRQ_PDB (88) /* Vector 88: PDB */
-# define KINETIS_IRQ_USBOTG (89) /* Vector 88: USB OTG */
-# define KINETIS_IRQ_USBCD (90) /* Vector 90: USB charger detect */
-# define KINETIS_IRQ_EMACTMR (91) /* Vector 91: Ethernet MAC IEEE 1588 timer interrupt */
-# define KINETIS_IRQ_EMACTX (92) /* Vector 92: Ethernet MAC transmit interrupt */
-# define KINETIS_IRQ_EMACRX (93) /* Vector 93: Ethernet MAC receive interrupt */
-# define KINETIS_IRQ_EMACMISC (94) /* Vector 94: Ethernet MAC error and misc interrupt */
-# define KINETIS_IRQ_I2S0 (95) /* Vector 95: I2S0 */
-# define KINETIS_IRQ_SDHC (96) /* Vector 96: SDHC */
-# define KINETIS_IRQ_DAC0 (97) /* Vector 97: DAC0 */
-# define KINETIS_IRQ_DAC1 (98) /* Vector 98: DAC1 */
-# define KINETIS_IRQ_TSI (99) /* Vector 97: TSI all sources */
-# define KINETIS_IRQ_MCG (100) /* Vector 100: MCG */
-# define KINETIS_IRQ_LPT (101) /* Vector 101: Low power timer */
- /* Vector 102: Reserved */
-# define KINETIS_IRQ_PORTA (103) /* Vector 103: Pin detect port A */
-# define KINETIS_IRQ_PORTB (104) /* Vector 104: Pin detect port B */
-# define KINETIS_IRQ_PORTC (105) /* Vector 105: Pin detect port C */
-# define KINETIS_IRQ_PORTD (106) /* Vector 106: Pin detect port D */
-# define KINETIS_IRQ_PORTE (107) /* Vector 107: Pin detect port E */
- /* Vectors 108-119: Reserved */
-
-/* Note that the total number of IRQ numbers supported is equal to the number of
- * valid interrupt vectors. This is wasteful in that certain tables are sized by
- * this value. There are only 97 valid interrupts so, potentially the number of
- * IRQs to could be reduced to 97. However, equating IRQ numbers with vector numbers
- * also simplifies operations on NVIC registers and (at least in my state of mind
- * now) seems to justify the waste.
- */
+/* External interrupts (vectors >= 16). These definitions are chip-specific */
-# define NR_VECTORS (120) /* 120 vectors */
-# define NR_IRQS (108) /* 120 interrupts but 108 IRQ numbers */
+#define KINETIS_IRQ_FIRST (16) /* Vector number of the first external interrupt */
+#if defined(CONFIG_ARCH_FAMILY_K20)
+# include
+#elif defined(CONFIG_ARCH_FAMILY_K40)
+# include
+#elif defined(CONFIG_ARCH_FAMILY_K60)
+# include
+#elif defined(CONFIG_ARCH_FAMILY_K64)
+# include
+#elif defined(CONFIG_ARCH_FAMILY_K66)
+# include
#else
/* The interrupt vectors for other parts are defined in other documents and may or
* may not be the same as above (the family members are all very similar) This
@@ -390,7 +95,7 @@
* if the vectors are the same.
*/
-# error "No IRQ numbers for this Kinetis part"
+# error "No IRQ numbers for this Kinetis K part"
#endif
/************************************************************************************
diff --git a/arch/arm/include/kinetis/kinetis_k20irq.h b/arch/arm/include/kinetis/kinetis_k20irq.h
new file mode 100644
index 0000000000000000000000000000000000000000..a5bb3068a655f27e97e048d2a6cfd15a2ca576a1
--- /dev/null
+++ b/arch/arm/include/kinetis/kinetis_k20irq.h
@@ -0,0 +1,200 @@
+/*****************************************************************************
+ * arch/arm/include/kinetis/kinetis_k20irq.h
+ *
+ * Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt
+ * David Sidrane
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_K20IRQ_H
+#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_K20IRQ_H
+
+/*****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+/*****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* IRQ numbers. The IRQ number corresponds vector number and hence map
+ * directly to bits in the NVIC. This does, however, waste several words of
+ * memory in the IRQ to handle mapping tables.
+ *
+ * Processor Exceptions (vectors 0-15). These common definitions can be found
+ * in the file nuttx/arch/arm/include/kinets/irq.h which includes this file
+ *
+ * External interrupts (vectors >= 16)
+ *
+ * K20 Family ****************************************************************
+ *
+ * The interrupt vectors for the following parts is defined in Freescale
+ * document K20P64M72SF1RM
+ */
+
+#define KINETIS_IRQ_DMACH0 (KINETIS_IRQ_FIRST+0) /* 0: DMA channel 0 transfer complete */
+#define KINETIS_IRQ_DMACH1 (KINETIS_IRQ_FIRST+1) /* 1: DMA channel 1 transfer complete */
+#define KINETIS_IRQ_DMACH2 (KINETIS_IRQ_FIRST+2) /* 2: DMA channel 2 transfer complete */
+#define KINETIS_IRQ_DMACH3 (KINETIS_IRQ_FIRST+3) /* 3: DMA channel 3 transfer complete */
+#define KINETIS_IRQ_DMACH4 (KINETIS_IRQ_FIRST+4) /* 4: DMA channel 4 transfer complete */
+#define KINETIS_IRQ_DMACH5 (KINETIS_IRQ_FIRST+5) /* 5: DMA channel 5 transfer complete */
+#define KINETIS_IRQ_DMACH6 (KINETIS_IRQ_FIRST+6) /* 6: DMA channel 6 transfer complete */
+#define KINETIS_IRQ_DMACH7 (KINETIS_IRQ_FIRST+7) /* 7: DMA channel 7 transfer complete */
+#define KINETIS_IRQ_DMACH8 (KINETIS_IRQ_FIRST+8) /* 8: DMA channel 8 transfer complete */
+#define KINETIS_IRQ_DMACH9 (KINETIS_IRQ_FIRST+9) /* 9: DMA channel 9 transfer complete */
+#define KINETIS_IRQ_DMACH10 (KINETIS_IRQ_FIRST+10) /* 10: DMA channel 10 transfer complete */
+#define KINETIS_IRQ_DMACH11 (KINETIS_IRQ_FIRST+11) /* 11: DMA channel 11 transfer complete */
+#define KINETIS_IRQ_DMACH12 (KINETIS_IRQ_FIRST+12) /* 12: DMA channel 12 transfer complete */
+#define KINETIS_IRQ_DMACH13 (KINETIS_IRQ_FIRST+13) /* 13: DMA channel 13 transfer complete */
+#define KINETIS_IRQ_DMACH14 (KINETIS_IRQ_FIRST+14) /* 14: DMA channel 14 transfer complete */
+#define KINETIS_IRQ_DMACH15 (KINETIS_IRQ_FIRST+15) /* 15: DMA channel 15 transfer complete */
+#define KINETIS_IRQ_DMAERR (KINETIS_IRQ_FIRST+16) /* 16: DMA error interrupt channels 0-15 */
+#define KINETIS_IRQ_RESVD17 (KINETIS_IRQ_FIRST+17) /* 17: Reserved */
+#define KINETIS_IRQ_FLASHCC (KINETIS_IRQ_FIRST+18) /* 18: Flash memory command complete */
+#define KINETIS_IRQ_FLASHRC (KINETIS_IRQ_FIRST+19) /* 19: Flash memory read collision */
+#define KINETIS_IRQ_SMCLVD (KINETIS_IRQ_FIRST+20) /* 20: Mode Controller low-voltage
+ * detect, low-voltage warning */
+#define KINETIS_IRQ_LLWU (KINETIS_IRQ_FIRST+21) /* 21: LLWU Normal Low Leakage Wakeup */
+#define KINETIS_IRQ_WDOG (KINETIS_IRQ_FIRST+22) /* 22: Watchdog */
+#define KINETIS_IRQ_RESVD23 (KINETIS_IRQ_FIRST+23) /* 23: Reserved */
+#define KINETIS_IRQ_I2C0 (KINETIS_IRQ_FIRST+24) /* 24: I2C0 */
+#define KINETIS_IRQ_I2C1 (KINETIS_IRQ_FIRST+25) /* 25: I2C1 */
+#define KINETIS_IRQ_SPI0 (KINETIS_IRQ_FIRST+26) /* 26: SPI0 all sources */
+#define KINETIS_IRQ_SPI1 (KINETIS_IRQ_FIRST+27) /* 27: SPI1 all sources */
+#define KINETIS_IRQ_RESVD28 (KINETIS_IRQ_FIRST+28) /* 28: Reserved */
+#define KINETIS_IRQ_CAN0MB (KINETIS_IRQ_FIRST+29) /* 29: CAN0 OR'ed Message buffer (0-15) */
+#define KINETIS_IRQ_CAN0BO (KINETIS_IRQ_FIRST+30) /* 30: CAN0 Bus Off */
+#define KINETIS_IRQ_CAN0ERR (KINETIS_IRQ_FIRST+31) /* 31: CAN0 Error */
+#define KINETIS_IRQ_CAN0TW (KINETIS_IRQ_FIRST+32) /* 32: CAN0 Transmit Warning */
+#define KINETIS_IRQ_CAN0RW (KINETIS_IRQ_FIRST+33) /* 33: CAN0 Receive Warning */
+#define KINETIS_IRQ_CAN0WU (KINETIS_IRQ_FIRST+34) /* 34: CAN0 Wake UP */
+#define KINETIS_IRQ_I2S0TX (KINETIS_IRQ_FIRST+35) /* 35: I2S0 Transmit */
+#define KINETIS_IRQ_I2S0TX (KINETIS_IRQ_FIRST+36) /* 36: I2S0 Receive */
+#define KINETIS_IRQ_RESVD37 (KINETIS_IRQ_FIRST+37) /* 37: Reserved */
+#define KINETIS_IRQ_RESVD38 (KINETIS_IRQ_FIRST+38) /* 38: Reserved */
+#define KINETIS_IRQ_RESVD39 (KINETIS_IRQ_FIRST+39) /* 39: Reserved */
+#define KINETIS_IRQ_RESVD40 (KINETIS_IRQ_FIRST+40) /* 40: Reserved */
+#define KINETIS_IRQ_RESVD41 (KINETIS_IRQ_FIRST+41) /* 41: Reserved */
+#define KINETIS_IRQ_RESVD42 (KINETIS_IRQ_FIRST+42) /* 42: Reserved */
+#define KINETIS_IRQ_RESVD43 (KINETIS_IRQ_FIRST+43) /* 43: Reserved */
+#define KINETIS_IRQ_UART0L (KINETIS_IRQ_FIRST+44) /* 44: UART0 LON */
+#define KINETIS_IRQ_UART0S (KINETIS_IRQ_FIRST+45) /* 45: UART0 status */
+#define KINETIS_IRQ_UART0E (KINETIS_IRQ_FIRST+46) /* 46: UART0 error */
+#define KINETIS_IRQ_UART1S (KINETIS_IRQ_FIRST+47) /* 47: UART1 status */
+#define KINETIS_IRQ_UART1E (KINETIS_IRQ_FIRST+48) /* 48: UART1 error */
+#define KINETIS_IRQ_UART2S (KINETIS_IRQ_FIRST+49) /* 49: UART2 status */
+#define KINETIS_IRQ_UART2E (KINETIS_IRQ_FIRST+50) /* 50: UART2 error */
+#define KINETIS_IRQ_RESVD51 (KINETIS_IRQ_FIRST+51) /* 51: Reserved */
+#define KINETIS_IRQ_RESVD52 (KINETIS_IRQ_FIRST+52) /* 52: Reserved */
+#define KINETIS_IRQ_RESVD53 (KINETIS_IRQ_FIRST+53) /* 53: Reserved */
+#define KINETIS_IRQ_RESVD54 (KINETIS_IRQ_FIRST+54) /* 54: Reserved */
+#define KINETIS_IRQ_RESVD55 (KINETIS_IRQ_FIRST+55) /* 55: Reserved */
+#define KINETIS_IRQ_RESVD56 (KINETIS_IRQ_FIRST+56) /* 56: Reserved */
+#define KINETIS_IRQ_ADC0 (KINETIS_IRQ_FIRST+57) /* 57: ADC0 */
+#define KINETIS_IRQ_ADC1 (KINETIS_IRQ_FIRST+58) /* 58: ADC1 */
+#define KINETIS_IRQ_CMP0 (KINETIS_IRQ_FIRST+59) /* 59: CMP0 */
+#define KINETIS_IRQ_CMP1 (KINETIS_IRQ_FIRST+60) /* 60: CMP1 */
+#define KINETIS_IRQ_CMP2 (KINETIS_IRQ_FIRST+61) /* 61: CMP2 */
+#define KINETIS_IRQ_FTM0 (KINETIS_IRQ_FIRST+62) /* 62: FTM0 all sources */
+#define KINETIS_IRQ_FTM1 (KINETIS_IRQ_FIRST+63) /* 63: FTM1 all sources */
+#define KINETIS_IRQ_FTM2 (KINETIS_IRQ_FIRST+64) /* 64: FTM2 all sources */
+#define KINETIS_IRQ_CMT (KINETIS_IRQ_FIRST+65) /* 65: CMT */
+#define KINETIS_IRQ_RTC (KINETIS_IRQ_FIRST+66) /* 66: RTC alarm interrupt */
+#define KINETIS_IRQ_RTCS (KINETIS_IRQ_FIRST+67) /* 67: RTC Seconds interrupt */
+#define KINETIS_IRQ_PITCH0 (KINETIS_IRQ_FIRST+68) /* 68: PIT channel 0 */
+#define KINETIS_IRQ_PITCH1 (KINETIS_IRQ_FIRST+69) /* 69: PIT channel 1 */
+#define KINETIS_IRQ_PITCH2 (KINETIS_IRQ_FIRST+70) /* 70: PIT channel 2 */
+#define KINETIS_IRQ_PITCH3 (KINETIS_IRQ_FIRST+71) /* 71: PIT channel 3 */
+#define KINETIS_IRQ_PDB (KINETIS_IRQ_FIRST+72) /* 72: PDB */
+#define KINETIS_IRQ_USBOTG (KINETIS_IRQ_FIRST+73) /* 73: USB OTG */
+#define KINETIS_IRQ_USBCD (KINETIS_IRQ_FIRST+74) /* 74: USB charger detect */
+#define KINETIS_IRQ_RESVD75 (KINETIS_IRQ_FIRST+75) /* 75: Reserved */
+#define KINETIS_IRQ_RESVD76 (KINETIS_IRQ_FIRST+76) /* 76: Reserved */
+#define KINETIS_IRQ_RESVD77 (KINETIS_IRQ_FIRST+77) /* 77: Reserved */
+#define KINETIS_IRQ_RESVD78 (KINETIS_IRQ_FIRST+78) /* 78: Reserved */
+#define KINETIS_IRQ_RESVD79 (KINETIS_IRQ_FIRST+79) /* 79: Reserved */
+#define KINETIS_IRQ_RESVD80 (KINETIS_IRQ_FIRST+80) /* 80: Reserved */
+#define KINETIS_IRQ_DAC0 (KINETIS_IRQ_FIRST+81) /* 81: DAC0 */
+#define KINETIS_IRQ_RESVD82 (KINETIS_IRQ_FIRST+82) /* 82: Reserved */
+#define KINETIS_IRQ_TSI (KINETIS_IRQ_FIRST+83) /* 83: TSI all sources */
+#define KINETIS_IRQ_MCG (KINETIS_IRQ_FIRST+84) /* 84: MCG */
+#define KINETIS_IRQ_LPT (KINETIS_IRQ_FIRST+85) /* 85: Low power timer */
+#define KINETIS_IRQ_RESVD86 (KINETIS_IRQ_FIRST+86) /* 86: Reserved */
+#define KINETIS_IRQ_PORTA (KINETIS_IRQ_FIRST+87) /* 87: Pin detect port A */
+#define KINETIS_IRQ_PORTB (KINETIS_IRQ_FIRST+88) /* 88: Pin detect port B */
+#define KINETIS_IRQ_PORTC (KINETIS_IRQ_FIRST+89) /* 89: Pin detect port C */
+#define KINETIS_IRQ_PORTD (KINETIS_IRQ_FIRST+90) /* 90: Pin detect port D */
+#define KINETIS_IRQ_PORTE (KINETIS_IRQ_FIRST+91) /* 91: Pin detect port E */
+#define KINETIS_IRQ_RESVD92 (KINETIS_IRQ_FIRST+92) /* 92: Reserved */
+#define KINETIS_IRQ_RESVD93 (KINETIS_IRQ_FIRST+93) /* 93: Reserved */
+#define KINETIS_IRQ_SWI (KINETIS_IRQ_FIRST+94) /* 94: Software interrupt */
+
+#define NR_INTERRUPTS 95 /* 95 Non core IRQs*/
+#define NR_VECTORS (KINETIS_IRQ_FIRST+NR_INTERRUPTS) /* 111 vectors */
+
+/* EXTI interrupts (Do not use IRQ numbers) */
+
+#define NR_IRQS NR_VECTORS
+
+/*****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/*****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_KINETIS_KINETIS_K20IRQ_H */
diff --git a/arch/arm/include/kinetis/kinetis_k40irq.h b/arch/arm/include/kinetis/kinetis_k40irq.h
new file mode 100644
index 0000000000000000000000000000000000000000..4156b321f94ea3a229f3a467626bc000b4b72c00
--- /dev/null
+++ b/arch/arm/include/kinetis/kinetis_k40irq.h
@@ -0,0 +1,200 @@
+/*****************************************************************************
+ * arch/arm/include/kinetis/kinetis_k40irq.h
+ *
+ * Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt
+ * David Sidrane
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_40KIRQ_H
+#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_40KIRQ_H
+
+/*****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+/*****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* IRQ numbers. The IRQ number corresponds vector number and hence map
+ * directly to bits in the NVIC. This does, however, waste several words of
+ * memory in the IRQ to handle mapping tables.
+ *
+ * Processor Exceptions (vectors 0-15). These common definitions can be found
+ * in the file nuttx/arch/arm/include/kinets/irq.h which includes this file
+ *
+ * External interrupts (vectors >= 16)
+ *
+ * K40 Family ****************************************************************
+ *
+ * The interrupt vectors for the following parts is defined in Freescale
+ * document K40P144M100SF2RM
+ */
+
+#define KINETIS_IRQ_DMACH0 (KINETIS_IRQ_FIRST+0) /* 0: DMA channel 0 transfer complete */
+#define KINETIS_IRQ_DMACH1 (KINETIS_IRQ_FIRST+1) /* 1: DMA channel 1 transfer complete */
+#define KINETIS_IRQ_DMACH2 (KINETIS_IRQ_FIRST+2) /* 2: DMA channel 2 transfer complete */
+#define KINETIS_IRQ_DMACH3 (KINETIS_IRQ_FIRST+3) /* 3: DMA channel 3 transfer complete */
+#define KINETIS_IRQ_DMACH4 (KINETIS_IRQ_FIRST+4) /* 4: DMA channel 4 transfer complete */
+#define KINETIS_IRQ_DMACH5 (KINETIS_IRQ_FIRST+5) /* 5: DMA channel 5 transfer complete */
+#define KINETIS_IRQ_DMACH6 (KINETIS_IRQ_FIRST+6) /* 6: DMA channel 6 transfer complete */
+#define KINETIS_IRQ_DMACH7 (KINETIS_IRQ_FIRST+7) /* 7: DMA channel 7 transfer complete */
+#define KINETIS_IRQ_DMACH8 (KINETIS_IRQ_FIRST+8) /* 8: DMA channel 8 transfer complete */
+#define KINETIS_IRQ_DMACH9 (KINETIS_IRQ_FIRST+9) /* 9: DMA channel 9 transfer complete */
+#define KINETIS_IRQ_DMACH10 (KINETIS_IRQ_FIRST+10) /* 10: DMA channel 10 transfer complete */
+#define KINETIS_IRQ_DMACH11 (KINETIS_IRQ_FIRST+11) /* 11: DMA channel 11 transfer complete */
+#define KINETIS_IRQ_DMACH12 (KINETIS_IRQ_FIRST+12) /* 12: DMA channel 12 transfer complete */
+#define KINETIS_IRQ_DMACH13 (KINETIS_IRQ_FIRST+13) /* 13: DMA channel 13 transfer complete */
+#define KINETIS_IRQ_DMACH14 (KINETIS_IRQ_FIRST+14) /* 14: DMA channel 14 transfer complete */
+#define KINETIS_IRQ_DMACH15 (KINETIS_IRQ_FIRST+15) /* 15: DMA channel 15 transfer complete */
+#define KINETIS_IRQ_DMAERR (KINETIS_IRQ_FIRST+16) /* 16: DMA error interrupt channels 0-15 */
+#define KINETIS_IRQ_MCM (KINETIS_IRQ_FIRST+17) /* 17: MCM Normal interrupt */
+#define KINETIS_IRQ_FLASHCC (KINETIS_IRQ_FIRST+18) /* 18: Flash memory command complete */
+#define KINETIS_IRQ_FLASHRC (KINETIS_IRQ_FIRST+19) /* 19: Flash memory read collision */
+#define KINETIS_IRQ_SMCLVD (KINETIS_IRQ_FIRST+20) /* 20: Mode Controller low-voltage
+ * detect, low-voltage warning */
+#define KINETIS_IRQ_LLWU (KINETIS_IRQ_FIRST+21) /* 21: LLWU Normal Low Leakage Wakeup */
+#define KINETIS_IRQ_WDOG (KINETIS_IRQ_FIRST+22) /* 22: Watchdog */
+#define KINETIS_IRQ_RESVD23 (KINETIS_IRQ_FIRST+23) /* 23: Reserved */
+#define KINETIS_IRQ_I2C0 (KINETIS_IRQ_FIRST+24) /* 24: I2C0 */
+#define KINETIS_IRQ_I2C1 (KINETIS_IRQ_FIRST+25) /* 25: I2C1 */
+#define KINETIS_IRQ_SPI0 (KINETIS_IRQ_FIRST+26) /* 26: SPI0 all sources */
+#define KINETIS_IRQ_SPI1 (KINETIS_IRQ_FIRST+27) /* 27: SPI1 all sources */
+#define KINETIS_IRQ_SPI2 (KINETIS_IRQ_FIRST+28) /* 28: SPI2 all sources */
+#define KINETIS_IRQ_CAN0MB (KINETIS_IRQ_FIRST+29) /* 29: CAN0 OR'ed Message buffer (0-15) */
+#define KINETIS_IRQ_CAN0BO (KINETIS_IRQ_FIRST+30) /* 30: CAN0 Bus Off */
+#define KINETIS_IRQ_CAN0ERR (KINETIS_IRQ_FIRST+31) /* 31: CAN0 Error */
+#define KINETIS_IRQ_CAN0TW (KINETIS_IRQ_FIRST+32) /* 32: CAN0 Transmit Warning */
+#define KINETIS_IRQ_CAN0RW (KINETIS_IRQ_FIRST+33) /* 33: CAN0 Receive Warning */
+#define KINETIS_IRQ_CAN0WU (KINETIS_IRQ_FIRST+34) /* 34: CAN0 Wake UP */
+#define KINETIS_IRQ_RESVD35 (KINETIS_IRQ_FIRST+35) /* 35: Reserved */
+#define KINETIS_IRQ_RESVD36 (KINETIS_IRQ_FIRST+36) /* 36: Reserved */
+#define KINETIS_IRQ_CAN1MB (KINETIS_IRQ_FIRST+37) /* 37: CAN1 OR'ed Message buffer (0-15) */
+#define KINETIS_IRQ_CAN1BO (KINETIS_IRQ_FIRST+38) /* 38: CAN1 Bus Off */
+#define KINETIS_IRQ_CAN1ERR (KINETIS_IRQ_FIRST+39) /* 39: CAN1 Error */
+#define KINETIS_IRQ_CAN1TW (KINETIS_IRQ_FIRST+40) /* 40: CAN1 Transmit Warning */
+#define KINETIS_IRQ_CAN1RW (KINETIS_IRQ_FIRST+41) /* 41: CAN1 Receive Warning */
+#define KINETIS_IRQ_CAN1WU (KINETIS_IRQ_FIRST+42) /* 42: CAN1 Wake UP */
+#define KINETIS_IRQ_RESVD43 (KINETIS_IRQ_FIRST+43) /* 43: Reserved */
+#define KINETIS_IRQ_RESVD44 (KINETIS_IRQ_FIRST+44) /* 44: Reserved */
+#define KINETIS_IRQ_UART0S (KINETIS_IRQ_FIRST+45) /* 45: UART0 status */
+#define KINETIS_IRQ_UART0E (KINETIS_IRQ_FIRST+46) /* 46: UART0 error */
+#define KINETIS_IRQ_UART1S (KINETIS_IRQ_FIRST+47) /* 47: UART1 status */
+#define KINETIS_IRQ_UART1E (KINETIS_IRQ_FIRST+48) /* 48: UART1 error */
+#define KINETIS_IRQ_UART2S (KINETIS_IRQ_FIRST+49) /* 49: UART2 status */
+#define KINETIS_IRQ_UART2E (KINETIS_IRQ_FIRST+50) /* 50: UART2 error */
+#define KINETIS_IRQ_UART3S (KINETIS_IRQ_FIRST+51) /* 51: UART3 status */
+#define KINETIS_IRQ_UART3E (KINETIS_IRQ_FIRST+52) /* 52: UART3 error */
+#define KINETIS_IRQ_UART4S (KINETIS_IRQ_FIRST+53) /* 53: UART4 status */
+#define KINETIS_IRQ_UART4E (KINETIS_IRQ_FIRST+54) /* 54: UART4 error */
+#define KINETIS_IRQ_UART5S (KINETIS_IRQ_FIRST+55) /* 55: UART5 status */
+#define KINETIS_IRQ_UART5E (KINETIS_IRQ_FIRST+56) /* 56: UART5 error */
+#define KINETIS_IRQ_ADC0 (KINETIS_IRQ_FIRST+57) /* 57: ADC0 */
+#define KINETIS_IRQ_ADC1 (KINETIS_IRQ_FIRST+58) /* 58: ADC1 */
+#define KINETIS_IRQ_CMP0 (KINETIS_IRQ_FIRST+59) /* 59: CMP0 */
+#define KINETIS_IRQ_CMP1 (KINETIS_IRQ_FIRST+60) /* 60: CMP1 */
+#define KINETIS_IRQ_CMP2 (KINETIS_IRQ_FIRST+61) /* 61: CMP2 */
+#define KINETIS_IRQ_FTM0 (KINETIS_IRQ_FIRST+62) /* 62: FTM0 all sources */
+#define KINETIS_IRQ_FTM1 (KINETIS_IRQ_FIRST+63) /* 63: FTM1 all sources */
+#define KINETIS_IRQ_FTM2 (KINETIS_IRQ_FIRST+64) /* 64: FTM2 all sources */
+#define KINETIS_IRQ_CMT (KINETIS_IRQ_FIRST+65) /* 65: CMT */
+#define KINETIS_IRQ_RTC (KINETIS_IRQ_FIRST+66) /* 66: RTC alarm interrupt */
+#define KINETIS_IRQ_RESVD67 (KINETIS_IRQ_FIRST+67) /* 67: Reserved */
+#define KINETIS_IRQ_PITCH0 (KINETIS_IRQ_FIRST+68) /* 68: PIT channel 0 */
+#define KINETIS_IRQ_PITCH1 (KINETIS_IRQ_FIRST+69) /* 69: PIT channel 1 */
+#define KINETIS_IRQ_PITCH2 (KINETIS_IRQ_FIRST+70) /* 70: PIT channel 2 */
+#define KINETIS_IRQ_PITCH3 (KINETIS_IRQ_FIRST+71) /* 71: PIT channel 3 */
+#define KINETIS_IRQ_PDB (KINETIS_IRQ_FIRST+72) /* 72: PDB */
+#define KINETIS_IRQ_USBOTG (KINETIS_IRQ_FIRST+73) /* 73: USB OTG */
+#define KINETIS_IRQ_USBCD (KINETIS_IRQ_FIRST+74) /* 74: USB charger detect */
+#define KINETIS_IRQ_RESVD75 (KINETIS_IRQ_FIRST+75) /* 75: Reserved */
+#define KINETIS_IRQ_RESVD76 (KINETIS_IRQ_FIRST+76) /* 76: Reserved */
+#define KINETIS_IRQ_RESVD77 (KINETIS_IRQ_FIRST+77) /* 77: Reserved */
+#define KINETIS_IRQ_RESVD78 (KINETIS_IRQ_FIRST+78) /* 78: Reserved */
+#define KINETIS_IRQ_I2S0 (KINETIS_IRQ_FIRST+79) /* 79: I2S0 */
+#define KINETIS_IRQ_SDHC (KINETIS_IRQ_FIRST+80) /* 80: SDHC */
+#define KINETIS_IRQ_DAC0 (KINETIS_IRQ_FIRST+81) /* 81: DAC0 */
+#define KINETIS_IRQ_DAC1 (KINETIS_IRQ_FIRST+82) /* 82: DAC1 */
+#define KINETIS_IRQ_TSI (KINETIS_IRQ_FIRST+83) /* 83: TSI all sources */
+#define KINETIS_IRQ_MCG (KINETIS_IRQ_FIRST+84) /* 84: MCG */
+#define KINETIS_IRQ_LPT (KINETIS_IRQ_FIRST+85) /* 85: Low power timer */
+#define KINETIS_IRQ_SLCD (KINETIS_IRQ_FIRST+86) /* 86: Segment LCD all sources */
+#define KINETIS_IRQ_PORTA (KINETIS_IRQ_FIRST+87) /* 87: Pin detect port A */
+#define KINETIS_IRQ_PORTB (KINETIS_IRQ_FIRST+88) /* 88: Pin detect port B */
+#define KINETIS_IRQ_PORTC (KINETIS_IRQ_FIRST+89) /* 89: Pin detect port C */
+#define KINETIS_IRQ_PORTD (KINETIS_IRQ_FIRST+90) /* 90: Pin detect port D */
+#define KINETIS_IRQ_PORTE (KINETIS_IRQ_FIRST+91) /* 91: Pin detect port E */
+#define KINETIS_IRQ_RESVD92 (KINETIS_IRQ_FIRST+92) /* 92: Reserved */
+#define KINETIS_IRQ_RESVD93 (KINETIS_IRQ_FIRST+93) /* 93: Reserved */
+#define KINETIS_IRQ_SWI (KINETIS_IRQ_FIRST+94) /* 94: Software interrupt */
+
+#define NR_INTERRUPTS 95 /* 95 Non core IRQs*/
+#define NR_VECTORS (KINETIS_IRQ_FIRST+NR_INTERRUPTS) /* 111 vectors */
+
+/* EXTI interrupts (Do not use IRQ numbers) */
+
+#define NR_IRQS NR_VECTORS
+
+/*****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/*****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_KINETIS_KINETIS_40KIRQ_H */
diff --git a/arch/arm/include/kinetis/kinetis_k60irq.h b/arch/arm/include/kinetis/kinetis_k60irq.h
new file mode 100644
index 0000000000000000000000000000000000000000..b2e3a79b83c656f0a106ec14f9dc4f54b06891d9
--- /dev/null
+++ b/arch/arm/include/kinetis/kinetis_k60irq.h
@@ -0,0 +1,200 @@
+/*****************************************************************************
+ * arch/arm/include/kinetis/kinetis_k60irq.h
+ *
+ * Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt
+ * David Sidrane
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_60KIRQ_H
+#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_60KIRQ_H
+
+/*****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+/*****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* IRQ numbers. The IRQ number corresponds vector number and hence map
+ * directly to bits in the NVIC. This does, however, waste several words of
+ * memory in the IRQ to handle mapping tables.
+ *
+ * Processor Exceptions (vectors 0-15). These common definitions can be found
+ * in the file nuttx/arch/arm/include/kinets/irq.h which includes this file
+ *
+ * External interrupts (vectors >= 16)
+ *
+ * K60 Family ****************************************************************
+ *
+ * The interrupt vectors for the following parts is defined in Freescale
+ * document K60P144M100SF2RM
+ */
+
+#define KINETIS_IRQ_DMACH0 (KINETIS_IRQ_FIRST+0) /* 0: DMA channel 0 transfer complete */
+#define KINETIS_IRQ_DMACH1 (KINETIS_IRQ_FIRST+1) /* 1: DMA channel 1 transfer complete */
+#define KINETIS_IRQ_DMACH2 (KINETIS_IRQ_FIRST+2) /* 2: DMA channel 2 transfer complete */
+#define KINETIS_IRQ_DMACH3 (KINETIS_IRQ_FIRST+3) /* 3: DMA channel 3 transfer complete */
+#define KINETIS_IRQ_DMACH4 (KINETIS_IRQ_FIRST+4) /* 4: DMA channel 4 transfer complete */
+#define KINETIS_IRQ_DMACH5 (KINETIS_IRQ_FIRST+5) /* 5: DMA channel 5 transfer complete */
+#define KINETIS_IRQ_DMACH6 (KINETIS_IRQ_FIRST+6) /* 6: DMA channel 6 transfer complete */
+#define KINETIS_IRQ_DMACH7 (KINETIS_IRQ_FIRST+7) /* 7: DMA channel 7 transfer complete */
+#define KINETIS_IRQ_DMACH8 (KINETIS_IRQ_FIRST+8) /* 8: DMA channel 8 transfer complete */
+#define KINETIS_IRQ_DMACH9 (KINETIS_IRQ_FIRST+9) /* 9: DMA channel 9 transfer complete */
+#define KINETIS_IRQ_DMACH10 (KINETIS_IRQ_FIRST+10) /* 10: DMA channel 10 transfer complete */
+#define KINETIS_IRQ_DMACH11 (KINETIS_IRQ_FIRST+11) /* 11: DMA channel 11 transfer complete */
+#define KINETIS_IRQ_DMACH12 (KINETIS_IRQ_FIRST+12) /* 12: DMA channel 12 transfer complete */
+#define KINETIS_IRQ_DMACH13 (KINETIS_IRQ_FIRST+13) /* 13: DMA channel 13 transfer complete */
+#define KINETIS_IRQ_DMACH14 (KINETIS_IRQ_FIRST+14) /* 14: DMA channel 14 transfer complete */
+#define KINETIS_IRQ_DMACH15 (KINETIS_IRQ_FIRST+15) /* 15: DMA channel 15 transfer complete */
+#define KINETIS_IRQ_DMAERR (KINETIS_IRQ_FIRST+16) /* 16: DMA error interrupt channels 0-15 */
+#define KINETIS_IRQ_MCM (KINETIS_IRQ_FIRST+17) /* 17: MCM Normal interrupt */
+#define KINETIS_IRQ_FLASHCC (KINETIS_IRQ_FIRST+18) /* 18: Flash memory command complete */
+#define KINETIS_IRQ_FLASHRC (KINETIS_IRQ_FIRST+19) /* 19: Flash memory read collision */
+#define KINETIS_IRQ_SMCLVD (KINETIS_IRQ_FIRST+20) /* 20: Mode Controller low-voltage
+ * detect, low-voltage warning */
+#define KINETIS_IRQ_LLWU (KINETIS_IRQ_FIRST+21) /* 21: LLWU Normal Low Leakage Wakeup */
+#define KINETIS_IRQ_WDOG (KINETIS_IRQ_FIRST+22) /* 22: Watchdog */
+#define KINETIS_IRQ_RNGB (KINETIS_IRQ_FIRST+23) /* 23: Random number generator */
+#define KINETIS_IRQ_I2C0 (KINETIS_IRQ_FIRST+24) /* 24: I2C0 */
+#define KINETIS_IRQ_I2C1 (KINETIS_IRQ_FIRST+25) /* 25: I2C1 */
+#define KINETIS_IRQ_SPI0 (KINETIS_IRQ_FIRST+26) /* 26: SPI0 all sources */
+#define KINETIS_IRQ_SPI1 (KINETIS_IRQ_FIRST+27) /* 27: SPI1 all sources */
+#define KINETIS_IRQ_SPI2 (KINETIS_IRQ_FIRST+28) /* 28: SPI2 all sources */
+#define KINETIS_IRQ_CAN0MB (KINETIS_IRQ_FIRST+29) /* 29: CAN0 OR'ed Message buffer (0-15) */
+#define KINETIS_IRQ_CAN0BO (KINETIS_IRQ_FIRST+30) /* 30: CAN0 Bus Off */
+#define KINETIS_IRQ_CAN0ERR (KINETIS_IRQ_FIRST+31) /* 31: CAN0 Error */
+#define KINETIS_IRQ_CAN0TW (KINETIS_IRQ_FIRST+32) /* 32: CAN0 Transmit Warning */
+#define KINETIS_IRQ_CAN0RW (KINETIS_IRQ_FIRST+33) /* 33: CAN0 Receive Warning */
+#define KINETIS_IRQ_CAN0WU (KINETIS_IRQ_FIRST+34) /* 34: CAN0 Wake UP */
+#define KINETIS_IRQ_RESVD35 (KINETIS_IRQ_FIRST+35) /* 35: Reserved */
+#define KINETIS_IRQ_RESVD36 (KINETIS_IRQ_FIRST+36) /* 36: Reserved */
+#define KINETIS_IRQ_CAN1MB (KINETIS_IRQ_FIRST+37) /* 37: CAN1 OR'ed Message buffer (0-15) */
+#define KINETIS_IRQ_CAN1BO (KINETIS_IRQ_FIRST+38) /* 38: CAN1 Bus Off */
+#define KINETIS_IRQ_CAN1ERR (KINETIS_IRQ_FIRST+39) /* 39: CAN1 Error */
+#define KINETIS_IRQ_CAN1TW (KINETIS_IRQ_FIRST+40) /* 40: CAN1 Transmit Warning */
+#define KINETIS_IRQ_CAN1RW (KINETIS_IRQ_FIRST+41) /* 41: CAN1 Receive Warning */
+#define KINETIS_IRQ_CAN1WU (KINETIS_IRQ_FIRST+42) /* 42: CAN1 Wake UP */
+#define KINETIS_IRQ_RESVD43 (KINETIS_IRQ_FIRST+43) /* 43: Reserved */
+#define KINETIS_IRQ_RESVD44 (KINETIS_IRQ_FIRST+44) /* 44: Reserved */
+#define KINETIS_IRQ_UART0S (KINETIS_IRQ_FIRST+45) /* 45: UART0 status */
+#define KINETIS_IRQ_UART0E (KINETIS_IRQ_FIRST+46) /* 46: UART0 error */
+#define KINETIS_IRQ_UART1S (KINETIS_IRQ_FIRST+47) /* 47: UART1 status */
+#define KINETIS_IRQ_UART1E (KINETIS_IRQ_FIRST+48) /* 48: UART1 error */
+#define KINETIS_IRQ_UART2S (KINETIS_IRQ_FIRST+49) /* 49: UART2 status */
+#define KINETIS_IRQ_UART2E (KINETIS_IRQ_FIRST+50) /* 50: UART2 error */
+#define KINETIS_IRQ_UART3S (KINETIS_IRQ_FIRST+51) /* 51: UART3 status */
+#define KINETIS_IRQ_UART3E (KINETIS_IRQ_FIRST+52) /* 52: UART3 error */
+#define KINETIS_IRQ_UART4S (KINETIS_IRQ_FIRST+53) /* 53: UART4 status */
+#define KINETIS_IRQ_UART4E (KINETIS_IRQ_FIRST+54) /* 54: UART4 error */
+#define KINETIS_IRQ_UART5S (KINETIS_IRQ_FIRST+55) /* 55: UART5 status */
+#define KINETIS_IRQ_UART5E (KINETIS_IRQ_FIRST+56) /* 56: UART5 error */
+#define KINETIS_IRQ_ADC0 (KINETIS_IRQ_FIRST+57) /* 57: ADC0 */
+#define KINETIS_IRQ_ADC1 (KINETIS_IRQ_FIRST+58) /* 58: ADC1 */
+#define KINETIS_IRQ_CMP0 (KINETIS_IRQ_FIRST+59) /* 59: CMP0 */
+#define KINETIS_IRQ_CMP1 (KINETIS_IRQ_FIRST+60) /* 60: CMP1 */
+#define KINETIS_IRQ_CMP2 (KINETIS_IRQ_FIRST+61) /* 61: CMP2 */
+#define KINETIS_IRQ_FTM0 (KINETIS_IRQ_FIRST+62) /* 62: FTM0 all sources */
+#define KINETIS_IRQ_FTM1 (KINETIS_IRQ_FIRST+63) /* 63: FTM1 all sources */
+#define KINETIS_IRQ_FTM2 (KINETIS_IRQ_FIRST+64) /* 64: FTM2 all sources */
+#define KINETIS_IRQ_CMT (KINETIS_IRQ_FIRST+65) /* 65: CMT */
+#define KINETIS_IRQ_RTC (KINETIS_IRQ_FIRST+66) /* 66: RTC alarm interrupt */
+#define KINETIS_IRQ_RESVD67 (KINETIS_IRQ_FIRST+67) /* 67: Reserved */
+#define KINETIS_IRQ_PITCH0 (KINETIS_IRQ_FIRST+68) /* 68: PIT channel 0 */
+#define KINETIS_IRQ_PITCH1 (KINETIS_IRQ_FIRST+69) /* 69: PIT channel 1 */
+#define KINETIS_IRQ_PITCH2 (KINETIS_IRQ_FIRST+70) /* 70: PIT channel 2 */
+#define KINETIS_IRQ_PITCH3 (KINETIS_IRQ_FIRST+71) /* 71: PIT channel 3 */
+#define KINETIS_IRQ_PDB (KINETIS_IRQ_FIRST+72) /* 72: PDB */
+#define KINETIS_IRQ_USBOTG (KINETIS_IRQ_FIRST+73) /* 73: USB OTG */
+#define KINETIS_IRQ_USBCD (KINETIS_IRQ_FIRST+74) /* 74: USB charger detect */
+#define KINETIS_IRQ_EMACTMR (KINETIS_IRQ_FIRST+75) /* 75: Ethernet MAC IEEE 1588 timer interrupt */
+#define KINETIS_IRQ_EMACTX (KINETIS_IRQ_FIRST+76) /* 76: Ethernet MAC transmit interrupt */
+#define KINETIS_IRQ_EMACRX (KINETIS_IRQ_FIRST+77) /* 77: Ethernet MAC receive interrupt */
+#define KINETIS_IRQ_EMACMISC (KINETIS_IRQ_FIRST+78) /* 78: Ethernet MAC error and misc interrupt */
+#define KINETIS_IRQ_I2S0 (KINETIS_IRQ_FIRST+79) /* 79: I2S0 */
+#define KINETIS_IRQ_SDHC (KINETIS_IRQ_FIRST+80) /* 80: SDHC */
+#define KINETIS_IRQ_DAC0 (KINETIS_IRQ_FIRST+81) /* 81: DAC0 */
+#define KINETIS_IRQ_DAC1 (KINETIS_IRQ_FIRST+82) /* 82: DAC1 */
+#define KINETIS_IRQ_TSI (KINETIS_IRQ_FIRST+83) /* 83: TSI all sources */
+#define KINETIS_IRQ_MCG (KINETIS_IRQ_FIRST+84) /* 84: MCG */
+#define KINETIS_IRQ_LPT (KINETIS_IRQ_FIRST+85) /* 85: Low power timer */
+#define KINETIS_IRQ_RESVD86 (KINETIS_IRQ_FIRST+86) /* 86: Reserved */
+#define KINETIS_IRQ_PORTA (KINETIS_IRQ_FIRST+87) /* 87: Pin detect port A */
+#define KINETIS_IRQ_PORTB (KINETIS_IRQ_FIRST+88) /* 88: Pin detect port B */
+#define KINETIS_IRQ_PORTC (KINETIS_IRQ_FIRST+89) /* 89: Pin detect port C */
+#define KINETIS_IRQ_PORTD (KINETIS_IRQ_FIRST+90) /* 90: Pin detect port D */
+#define KINETIS_IRQ_PORTE (KINETIS_IRQ_FIRST+91) /* 91: Pin detect port E */
+#define KINETIS_IRQ_RESVD92 (KINETIS_IRQ_FIRST+92) /* 92: Reserved */
+#define KINETIS_IRQ_RESVD93 (KINETIS_IRQ_FIRST+93) /* 93: Reserved */
+#define KINETIS_IRQ_SWI (KINETIS_IRQ_FIRST+94) /* 94: Software interrupt */
+
+#define NR_INTERRUPTS 95 /* 95 Non core IRQs*/
+#define NR_VECTORS (KINETIS_IRQ_FIRST+NR_INTERRUPTS) /* 111 vectors */
+
+/* EXTI interrupts (Do not use IRQ numbers) */
+
+#define NR_IRQS NR_VECTORS
+
+/*****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/*****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_KINETIS_KINETIS_60KIRQ_H */
diff --git a/arch/arm/include/kinetis/kinetis_k64irq.h b/arch/arm/include/kinetis/kinetis_k64irq.h
new file mode 100644
index 0000000000000000000000000000000000000000..c97c4b25122b98494383b851541c1ddc969519f3
--- /dev/null
+++ b/arch/arm/include/kinetis/kinetis_k64irq.h
@@ -0,0 +1,190 @@
+/*****************************************************************************
+ * arch/arm/include/kinetis/kinetis_k64irq.h
+ *
+ * Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt
+ * David Sidrane
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_64KIRQ_H
+#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_64KIRQ_H
+
+/*****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+/*****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* IRQ numbers. The IRQ number corresponds vector number and hence map
+ * directly to bits in the NVIC. This does, however, waste several words of
+ * memory in the IRQ to handle mapping tables.
+ *
+ * Processor Exceptions (vectors 0-15). These common definitions can be found
+ * in the file nuttx/arch/arm/include/kinets/irq.h which includes this file
+ *
+ * External interrupts (vectors >= 16)
+ *
+ * K60 Family ****************************************************************
+ *
+ * The interrupt vectors for the following parts is defined in Freescale
+ * document K64P144M120SF5RM.pdf
+ */
+#define KINETIS_IRQ_DMACH0 (KINETIS_IRQ_FIRST+0) /* 0: DMA channel 0 transfer complete */
+#define KINETIS_IRQ_DMACH1 (KINETIS_IRQ_FIRST+1) /* 1: DMA channel 1 transfer complete */
+#define KINETIS_IRQ_DMACH2 (KINETIS_IRQ_FIRST+2) /* 2: DMA channel 2 transfer complete */
+#define KINETIS_IRQ_DMACH3 (KINETIS_IRQ_FIRST+3) /* 3: DMA channel 3 transfer complete */
+#define KINETIS_IRQ_DMACH4 (KINETIS_IRQ_FIRST+4) /* 4: DMA channel 4 transfer complete */
+#define KINETIS_IRQ_DMACH5 (KINETIS_IRQ_FIRST+5) /* 5: DMA channel 5 transfer complete */
+#define KINETIS_IRQ_DMACH6 (KINETIS_IRQ_FIRST+6) /* 6: DMA channel 6 transfer complete */
+#define KINETIS_IRQ_DMACH7 (KINETIS_IRQ_FIRST+7) /* 7: DMA channel 7 transfer complete */
+#define KINETIS_IRQ_DMACH8 (KINETIS_IRQ_FIRST+8) /* 8: DMA channel 8 transfer complete */
+#define KINETIS_IRQ_DMACH9 (KINETIS_IRQ_FIRST+9) /* 9: DMA channel 9 transfer complete */
+#define KINETIS_IRQ_DMACH10 (KINETIS_IRQ_FIRST+10) /* 10: DMA channel 10 transfer complete */
+#define KINETIS_IRQ_DMACH11 (KINETIS_IRQ_FIRST+11) /* 11: DMA channel 11 transfer complete */
+#define KINETIS_IRQ_DMACH12 (KINETIS_IRQ_FIRST+12) /* 12: DMA channel 12 transfer complete */
+#define KINETIS_IRQ_DMACH13 (KINETIS_IRQ_FIRST+13) /* 13: DMA channel 13 transfer complete */
+#define KINETIS_IRQ_DMACH14 (KINETIS_IRQ_FIRST+14) /* 14: DMA channel 14 transfer complete */
+#define KINETIS_IRQ_DMACH15 (KINETIS_IRQ_FIRST+15) /* 15: DMA channel 15 transfer complete */
+#define KINETIS_IRQ_DMAERR (KINETIS_IRQ_FIRST+16) /* 16: DMA error interrupt channels 0-15 */
+#define KINETIS_IRQ_MCM (KINETIS_IRQ_FIRST+17) /* 17: MCM Normal interrupt */
+#define KINETIS_IRQ_FLASHCC (KINETIS_IRQ_FIRST+18) /* 18: Flash memory command complete */
+#define KINETIS_IRQ_FLASHRC (KINETIS_IRQ_FIRST+19) /* 19: Flash memory read collision */
+#define KINETIS_IRQ_SMCLVD (KINETIS_IRQ_FIRST+20) /* 20: Mode Controller low-voltage
+ * detect, low-voltage warning */
+#define KINETIS_IRQ_LLWU (KINETIS_IRQ_FIRST+21) /* 21: LLWU Normal Low Leakage Wakeup */
+#define KINETIS_IRQ_WDOG (KINETIS_IRQ_FIRST+22) /* 22: Watchdog or EWM */
+#define KINETIS_IRQ_RNGB (KINETIS_IRQ_FIRST+23) /* 23: Random number generator */
+#define KINETIS_IRQ_I2C0 (KINETIS_IRQ_FIRST+24) /* 24: I2C0 */
+#define KINETIS_IRQ_I2C1 (KINETIS_IRQ_FIRST+25) /* 25: I2C1 */
+#define KINETIS_IRQ_SPI0 (KINETIS_IRQ_FIRST+26) /* 26: SPI0 all sources */
+#define KINETIS_IRQ_SPI1 (KINETIS_IRQ_FIRST+27) /* 27: SPI1 all sources */
+#define KINETIS_IRQ_I2S0 (KINETIS_IRQ_FIRST+28) /* 28: 12S0 Transmit */
+#define KINETIS_IRQ_I2S1 (KINETIS_IRQ_FIRST+29) /* 29: 12S0 Receive */
+#define KINETIS_IRQ_RESVD30 (KINETIS_IRQ_FIRST+30) /* 30: Reserved */
+#define KINETIS_IRQ_UART0S (KINETIS_IRQ_FIRST+31) /* 31: UART0 status */
+#define KINETIS_IRQ_UART0E (KINETIS_IRQ_FIRST+32) /* 32: UART0 error */
+#define KINETIS_IRQ_UART1S (KINETIS_IRQ_FIRST+33) /* 33: UART1 status */
+#define KINETIS_IRQ_UART1E (KINETIS_IRQ_FIRST+34) /* 34: UART1 error */
+#define KINETIS_IRQ_UART2S (KINETIS_IRQ_FIRST+35) /* 35: UART2 status */
+#define KINETIS_IRQ_UART2E (KINETIS_IRQ_FIRST+36) /* 36: UART2 error */
+#define KINETIS_IRQ_UART3S (KINETIS_IRQ_FIRST+37) /* 37: UART3 status */
+#define KINETIS_IRQ_UART3E (KINETIS_IRQ_FIRST+38) /* 38: UART3 error */
+#define KINETIS_IRQ_ADC0 (KINETIS_IRQ_FIRST+39) /* 39: ADC0 */
+#define KINETIS_IRQ_CMP0 (KINETIS_IRQ_FIRST+40) /* 40: CMP0 */
+#define KINETIS_IRQ_CMP1 (KINETIS_IRQ_FIRST+41) /* 41: CMP1 */
+#define KINETIS_IRQ_FTM0 (KINETIS_IRQ_FIRST+42) /* 42: FTM0 all sources */
+#define KINETIS_IRQ_FTM1 (KINETIS_IRQ_FIRST+43) /* 43: FTM1 all sources */
+#define KINETIS_IRQ_FTM2 (KINETIS_IRQ_FIRST+44) /* 44: FTM2 all sources */
+#define KINETIS_IRQ_CMT (KINETIS_IRQ_FIRST+45) /* 45: CMT */
+#define KINETIS_IRQ_RTC (KINETIS_IRQ_FIRST+46) /* 46: RTC alarm interrupt */
+#define KINETIS_IRQ_RTCS (KINETIS_IRQ_FIRST+47) /* 47: RTC seconds interrupt */
+#define KINETIS_IRQ_PITCH0 (KINETIS_IRQ_FIRST+48) /* 48: PIT channel 0 */
+#define KINETIS_IRQ_PITCH1 (KINETIS_IRQ_FIRST+49) /* 49: PIT channel 1 */
+#define KINETIS_IRQ_PITCH2 (KINETIS_IRQ_FIRST+50) /* 50: PIT channel 2 */
+#define KINETIS_IRQ_PITCH3 (KINETIS_IRQ_FIRST+51) /* 51: PIT channel 3 */
+#define KINETIS_IRQ_PDB (KINETIS_IRQ_FIRST+52) /* 52: PDB */
+#define KINETIS_IRQ_USBOTG (KINETIS_IRQ_FIRST+53) /* 53: USB OTG */
+#define KINETIS_IRQ_USBCD (KINETIS_IRQ_FIRST+54) /* 54: USB charger detect */
+#define KINETIS_IRQ_RESVD55 (KINETIS_IRQ_FIRST+55) /* 55: Reserved */
+#define KINETIS_IRQ_DAC0 (KINETIS_IRQ_FIRST+56) /* 56: DAC0 */
+#define KINETIS_IRQ_MCG (KINETIS_IRQ_FIRST+57) /* 57: MCG */
+#define KINETIS_IRQ_LPT (KINETIS_IRQ_FIRST+58) /* 58: Low power timer */
+#define KINETIS_IRQ_PORTA (KINETIS_IRQ_FIRST+59) /* 59: Pin detect port A */
+#define KINETIS_IRQ_PORTB (KINETIS_IRQ_FIRST+60) /* 60: Pin detect port B */
+#define KINETIS_IRQ_PORTC (KINETIS_IRQ_FIRST+61) /* 61: Pin detect port C */
+#define KINETIS_IRQ_PORTD (KINETIS_IRQ_FIRST+62) /* 62: Pin detect port D */
+#define KINETIS_IRQ_PORTE (KINETIS_IRQ_FIRST+63) /* 63: Pin detect port E */
+#define KINETIS_IRQ_SWI (KINETIS_IRQ_FIRST+64) /* 64: Software interrupt */
+#define KINETIS_IRQ_SPI2 (KINETIS_IRQ_FIRST+65) /* 65: SPI2 all sources */
+#define KINETIS_IRQ_UART4S (KINETIS_IRQ_FIRST+66) /* 66: UART4 status */
+#define KINETIS_IRQ_UART4E (KINETIS_IRQ_FIRST+67) /* 67: UART4 error */
+#define KINETIS_IRQ_UART5S (KINETIS_IRQ_FIRST+68) /* 68: UART5 status */
+#define KINETIS_IRQ_UART5E (KINETIS_IRQ_FIRST+69) /* 69: UART5 error */
+#define KINETIS_IRQ_CMP2 (KINETIS_IRQ_FIRST+70) /* 70: CMP2 */
+#define KINETIS_IRQ_FTM3 (KINETIS_IRQ_FIRST+71) /* 71: FTM3 all sources */
+#define KINETIS_IRQ_DAC1 (KINETIS_IRQ_FIRST+72) /* 72: DAC1 */
+#define KINETIS_IRQ_ADC1 (KINETIS_IRQ_FIRST+73) /* 73: ADC1 */
+#define KINETIS_IRQ_I2C2 (KINETIS_IRQ_FIRST+74) /* 74: I2C2 */
+#define KINETIS_IRQ_CAN0MB (KINETIS_IRQ_FIRST+75) /* 75: CAN0 OR'ed Message buffer (0-15) */
+#define KINETIS_IRQ_CAN0BO (KINETIS_IRQ_FIRST+76) /* 76: CAN0 Bus Off */
+#define KINETIS_IRQ_CAN0ERR (KINETIS_IRQ_FIRST+77) /* 77: CAN0 Error */
+#define KINETIS_IRQ_CAN0TW (KINETIS_IRQ_FIRST+78) /* 78: CAN0 Transmit Warning */
+#define KINETIS_IRQ_CAN0RW (KINETIS_IRQ_FIRST+79) /* 79: CAN0 Receive Warning */
+#define KINETIS_IRQ_CAN0WU (KINETIS_IRQ_FIRST+80) /* 80: CAN0 Wake UP */
+#define KINETIS_IRQ_SDHC (KINETIS_IRQ_FIRST+81) /* 81: SDHC */
+#define KINETIS_IRQ_EMACTMR (KINETIS_IRQ_FIRST+82) /* 82: Ethernet MAC IEEE 1588 timer interrupt */
+#define KINETIS_IRQ_EMACTX (KINETIS_IRQ_FIRST+83) /* 83: Ethernet MAC transmit interrupt */
+#define KINETIS_IRQ_EMACRX (KINETIS_IRQ_FIRST+84) /* 84: Ethernet MAC receive interrupt */
+#define KINETIS_IRQ_EMACMISC (KINETIS_IRQ_FIRST+85) /* 85: Ethernet MAC error and misc interrupt */
+
+#define NR_INTERRUPTS 86 /* 86 Non core IRQs*/
+#define NR_VECTORS (KINETIS_IRQ_FIRST+NR_INTERRUPTS) /* 102 vectors */
+
+/* EXTI interrupts (Do not use IRQ numbers) */
+
+#define NR_IRQS NR_VECTORS
+
+/*****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/*****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_KINETIS_KINETIS_64KIRQ_H */
diff --git a/arch/arm/include/kinetis/kinetis_k66irq.h b/arch/arm/include/kinetis/kinetis_k66irq.h
new file mode 100644
index 0000000000000000000000000000000000000000..bbf0903f5a627587e5880f4fefa57bd056d9bcad
--- /dev/null
+++ b/arch/arm/include/kinetis/kinetis_k66irq.h
@@ -0,0 +1,206 @@
+/*****************************************************************************
+ * arch/arm/include/kinetis/kinetis_k66irq.h
+ *
+ * Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt
+ * David Sidrane
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_66KIRQ_H
+#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_66KIRQ_H
+
+/*****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+/*****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* IRQ numbers. The IRQ number corresponds vector number and hence map
+ * directly to bits in the NVIC. This does, however, waste several words of
+ * memory in the IRQ to handle mapping tables.
+ *
+ * Processor Exceptions (vectors 0-15). These common definitions can be found
+ * in the file nuttx/arch/arm/include/kinets/irq.h which includes this file
+ *
+ * External interrupts (vectors >= 16)
+ *
+ * K66 Family ****************************************************************
+ *
+ * The interrupt vectors for the following parts is defined in Freescale
+ * document K66P144M180SF5RMV2
+ */
+
+#define KINETIS_IRQ_DMACH0 (KINETIS_IRQ_FIRST+0) /* 0: DMA channel 0, 16 transfer complete */
+#define KINETIS_IRQ_DMACH1 (KINETIS_IRQ_FIRST+1) /* 1: DMA channel 1, 17 transfer complete */
+#define KINETIS_IRQ_DMACH2 (KINETIS_IRQ_FIRST+2) /* 2: DMA channel 2, 18 transfer complete */
+#define KINETIS_IRQ_DMACH3 (KINETIS_IRQ_FIRST+3) /* 3: DMA channel 3, 19 transfer complete */
+#define KINETIS_IRQ_DMACH4 (KINETIS_IRQ_FIRST+4) /* 4: DMA channel 4, 20 transfer complete */
+#define KINETIS_IRQ_DMACH5 (KINETIS_IRQ_FIRST+5) /* 5: DMA channel 5, 21 transfer complete */
+#define KINETIS_IRQ_DMACH6 (KINETIS_IRQ_FIRST+6) /* 6: DMA channel 6, 11 transfer complete */
+#define KINETIS_IRQ_DMACH7 (KINETIS_IRQ_FIRST+7) /* 7: DMA channel 7, 23 transfer complete */
+#define KINETIS_IRQ_DMACH8 (KINETIS_IRQ_FIRST+8) /* 8: DMA channel 8, 24 transfer complete */
+#define KINETIS_IRQ_DMACH9 (KINETIS_IRQ_FIRST+9) /* 9: DMA channel 9, 25 transfer complete */
+#define KINETIS_IRQ_DMACH10 (KINETIS_IRQ_FIRST+10) /* 10: DMA channel 10, 26 transfer complete */
+#define KINETIS_IRQ_DMACH11 (KINETIS_IRQ_FIRST+11) /* 11: DMA channel 11, 27 transfer complete */
+#define KINETIS_IRQ_DMACH12 (KINETIS_IRQ_FIRST+12) /* 12: DMA channel 12, 28 transfer complete */
+#define KINETIS_IRQ_DMACH13 (KINETIS_IRQ_FIRST+13) /* 13: DMA channel 13, 29 transfer complete */
+#define KINETIS_IRQ_DMACH14 (KINETIS_IRQ_FIRST+14) /* 14: DMA channel 14, 30 transfer complete */
+#define KINETIS_IRQ_DMACH15 (KINETIS_IRQ_FIRST+15) /* 15: DMA channel 15, 31 transfer complete */
+#define KINETIS_IRQ_DMAERR (KINETIS_IRQ_FIRST+16) /* 16: DMA error interrupt channels 0-31 */
+#define KINETIS_IRQ_MCM (KINETIS_IRQ_FIRST+17) /* 17: MCM Normal interrupt */
+#define KINETIS_IRQ_FLASHCC (KINETIS_IRQ_FIRST+18) /* 18: Flash memory command complete */
+#define KINETIS_IRQ_FLASHRC (KINETIS_IRQ_FIRST+19) /* 19: Flash memory read collision */
+#define KINETIS_IRQ_SMCLVD (KINETIS_IRQ_FIRST+20) /* 20: Mode Controller low-voltage
+ * detect, low-voltage warning */
+#define KINETIS_IRQ_LLWU (KINETIS_IRQ_FIRST+21) /* 21: LLWU Normal Low Leakage Wakeup */
+#define KINETIS_IRQ_WDOG (KINETIS_IRQ_FIRST+22) /* 22: Watchdog or EWM */
+#define KINETIS_IRQ_RNGB (KINETIS_IRQ_FIRST+23) /* 23: Random number generator */
+#define KINETIS_IRQ_I2C0 (KINETIS_IRQ_FIRST+24) /* 24: I2C0 */
+#define KINETIS_IRQ_I2C1 (KINETIS_IRQ_FIRST+25) /* 25: I2C1 */
+#define KINETIS_IRQ_SPI0 (KINETIS_IRQ_FIRST+26) /* 26: SPI0 all sources */
+#define KINETIS_IRQ_SPI1 (KINETIS_IRQ_FIRST+27) /* 27: SPI1 all sources */
+#define KINETIS_IRQ_I2S0 (KINETIS_IRQ_FIRST+28) /* 28: 12S0 Transmit */
+#define KINETIS_IRQ_I2S1 (KINETIS_IRQ_FIRST+29) /* 29: 12S0 Receive */
+#define KINETIS_IRQ_RESVD30 (KINETIS_IRQ_FIRST+30) /* 30: Reserved */
+#define KINETIS_IRQ_UART0S (KINETIS_IRQ_FIRST+31) /* 31: UART0 status */
+#define KINETIS_IRQ_UART0E (KINETIS_IRQ_FIRST+32) /* 32: UART0 error */
+#define KINETIS_IRQ_UART1S (KINETIS_IRQ_FIRST+33) /* 33: UART1 status */
+#define KINETIS_IRQ_UART1E (KINETIS_IRQ_FIRST+34) /* 34: UART1 error */
+#define KINETIS_IRQ_UART2S (KINETIS_IRQ_FIRST+35) /* 35: UART2 status */
+#define KINETIS_IRQ_UART2E (KINETIS_IRQ_FIRST+36) /* 36: UART2 error */
+#define KINETIS_IRQ_UART3S (KINETIS_IRQ_FIRST+37) /* 37: UART3 status */
+#define KINETIS_IRQ_UART3E (KINETIS_IRQ_FIRST+38) /* 38: UART3 error */
+#define KINETIS_IRQ_ADC0 (KINETIS_IRQ_FIRST+39) /* 39: ADC0 */
+#define KINETIS_IRQ_CMP0 (KINETIS_IRQ_FIRST+40) /* 40: CMP0 */
+#define KINETIS_IRQ_CMP1 (KINETIS_IRQ_FIRST+41) /* 41: CMP1 */
+#define KINETIS_IRQ_FTM0 (KINETIS_IRQ_FIRST+42) /* 42: FTM0 all sources */
+#define KINETIS_IRQ_FTM1 (KINETIS_IRQ_FIRST+43) /* 43: FTM1 all sources */
+#define KINETIS_IRQ_FTM2 (KINETIS_IRQ_FIRST+44) /* 44: FTM2 all sources */
+#define KINETIS_IRQ_CMT (KINETIS_IRQ_FIRST+45) /* 45: CMT */
+#define KINETIS_IRQ_RTC (KINETIS_IRQ_FIRST+46) /* 46: RTC alarm interrupt */
+#define KINETIS_IRQ_RTCS (KINETIS_IRQ_FIRST+47) /* 47: RTC seconds interrupt */
+#define KINETIS_IRQ_PITCH0 (KINETIS_IRQ_FIRST+48) /* 48: PIT channel 0 */
+#define KINETIS_IRQ_PITCH1 (KINETIS_IRQ_FIRST+49) /* 49: PIT channel 1 */
+#define KINETIS_IRQ_PITCH2 (KINETIS_IRQ_FIRST+50) /* 50: PIT channel 2 */
+#define KINETIS_IRQ_PITCH3 (KINETIS_IRQ_FIRST+51) /* 51: PIT channel 3 */
+#define KINETIS_IRQ_PDB (KINETIS_IRQ_FIRST+52) /* 52: PDB */
+#define KINETIS_IRQ_USBOTG (KINETIS_IRQ_FIRST+53) /* 53: USB OTG */
+#define KINETIS_IRQ_USBCD (KINETIS_IRQ_FIRST+54) /* 54: USB charger detect */
+#define KINETIS_IRQ_RESVD55 (KINETIS_IRQ_FIRST+55) /* 55: Reserved */
+#define KINETIS_IRQ_DAC0 (KINETIS_IRQ_FIRST+56) /* 56: DAC0 */
+#define KINETIS_IRQ_MCG (KINETIS_IRQ_FIRST+57) /* 57: MCG */
+#define KINETIS_IRQ_LPT (KINETIS_IRQ_FIRST+58) /* 58: Low power timer */
+#define KINETIS_IRQ_PORTA (KINETIS_IRQ_FIRST+59) /* 59: Pin detect port A */
+#define KINETIS_IRQ_PORTB (KINETIS_IRQ_FIRST+60) /* 60: Pin detect port B */
+#define KINETIS_IRQ_PORTC (KINETIS_IRQ_FIRST+61) /* 61: Pin detect port C */
+#define KINETIS_IRQ_PORTD (KINETIS_IRQ_FIRST+62) /* 62: Pin detect port D */
+#define KINETIS_IRQ_PORTE (KINETIS_IRQ_FIRST+63) /* 63: Pin detect port E */
+#define KINETIS_IRQ_SWI (KINETIS_IRQ_FIRST+64) /* 64: Software interrupt */
+#define KINETIS_IRQ_SPI2 (KINETIS_IRQ_FIRST+65) /* 65: SPI2 all sources */
+#define KINETIS_IRQ_UART4S (KINETIS_IRQ_FIRST+66) /* 66: UART4 status */
+#define KINETIS_IRQ_UART4E (KINETIS_IRQ_FIRST+67) /* 67: UART4 error */
+#define KINETIS_IRQ_RESVD68 (KINETIS_IRQ_FIRST+68) /* 68: Reserved */
+#define KINETIS_IRQ_RESVD69 (KINETIS_IRQ_FIRST+69) /* 69: Reserved */
+#define KINETIS_IRQ_CMP2 (KINETIS_IRQ_FIRST+70) /* 70: CMP2 */
+#define KINETIS_IRQ_FTM3 (KINETIS_IRQ_FIRST+71) /* 71: FTM3 all sources */
+#define KINETIS_IRQ_DAC1 (KINETIS_IRQ_FIRST+72) /* 72: DAC1 */
+#define KINETIS_IRQ_ADC1 (KINETIS_IRQ_FIRST+73) /* 73: ADC1 */
+#define KINETIS_IRQ_I2C2 (KINETIS_IRQ_FIRST+74) /* 74: I2C2 */
+#define KINETIS_IRQ_CAN0MB (KINETIS_IRQ_FIRST+75) /* 75: CAN0 OR'ed Message buffer (0-15) */
+#define KINETIS_IRQ_CAN0BO (KINETIS_IRQ_FIRST+76) /* 76: CAN0 Bus Off */
+#define KINETIS_IRQ_CAN0ERR (KINETIS_IRQ_FIRST+77) /* 77: CAN0 Error */
+#define KINETIS_IRQ_CAN0TW (KINETIS_IRQ_FIRST+78) /* 78: CAN0 Transmit Warning */
+#define KINETIS_IRQ_CAN0RW (KINETIS_IRQ_FIRST+79) /* 79: CAN0 Receive Warning */
+#define KINETIS_IRQ_CAN0WU (KINETIS_IRQ_FIRST+80) /* 80: CAN0 Wake UP */
+#define KINETIS_IRQ_SDHC (KINETIS_IRQ_FIRST+81) /* 81: SDHC */
+#define KINETIS_IRQ_EMACTMR (KINETIS_IRQ_FIRST+82) /* 82: Ethernet MAC IEEE 1588 timer interrupt */
+#define KINETIS_IRQ_EMACTX (KINETIS_IRQ_FIRST+83) /* 83: Ethernet MAC transmit interrupt */
+#define KINETIS_IRQ_EMACRX (KINETIS_IRQ_FIRST+84) /* 84: Ethernet MAC receive interrupt */
+#define KINETIS_IRQ_EMACMISC (KINETIS_IRQ_FIRST+85) /* 85: Ethernet MAC error and misc interrupt */
+#define KINETIS_IRQ_LPUART0 (KINETIS_IRQ_FIRST+86) /* 86: LPUART0 Status and error */
+#define KINETIS_IRQ_TSI0 (KINETIS_IRQ_FIRST+87) /* 87: TSI0 */
+#define KINETIS_IRQ_TPM1 (KINETIS_IRQ_FIRST+88) /* 88: TPM1 */
+#define KINETIS_IRQ_TPM2 (KINETIS_IRQ_FIRST+89) /* 89: TPM2 */
+#define KINETIS_IRQ_USBHSDCD (KINETIS_IRQ_FIRST+90) /* 90: shared by USBHS DCD & USBHS Phy modules */
+#define KINETIS_IRQ_I2C3 (KINETIS_IRQ_FIRST+91) /* 91: I2C3 */
+#define KINETIS_IRQ_CMP3 (KINETIS_IRQ_FIRST+92) /* 92: CMP3 */
+#define KINETIS_IRQ_USBHSOTG (KINETIS_IRQ_FIRST+93) /* 93: USBHS OTG*/
+#define KINETIS_IRQ_CAN1MB (KINETIS_IRQ_FIRST+94) /* 94: CAN1 OR'ed Message buffer (0-15) */
+#define KINETIS_IRQ_CAN1BO (KINETIS_IRQ_FIRST+95) /* 95: CAN1 Bus Off */
+#define KINETIS_IRQ_CAN1ERR (KINETIS_IRQ_FIRST+96) /* 96: CAN1 Error */
+#define KINETIS_IRQ_CAN1TW (KINETIS_IRQ_FIRST+97) /* 97: CAN1 Transmit Warning */
+#define KINETIS_IRQ_CAN1RW (KINETIS_IRQ_FIRST+98) /* 98: CAN1 Receive Warning */
+#define KINETIS_IRQ_CAN1WU (KINETIS_IRQ_FIRST+99) /* 99: CAN1 Wake UP */
+
+
+#define NR_INTERRUPTS 100 /* 100 Non core IRQs*/
+#define NR_VECTORS (KINETIS_IRQ_FIRST+NR_INTERRUPTS) /* 116 vectors */
+
+/* EXTI interrupts (Do not use IRQ numbers) */
+
+#define NR_IRQS NR_VECTORS
+
+/*****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/*****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/*****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_KINETIS_KINETIS_66KIRQ_H */
diff --git a/arch/arm/include/kinetis/kinetis_mcg.h b/arch/arm/include/kinetis/kinetis_mcg.h
new file mode 100644
index 0000000000000000000000000000000000000000..bca6b18883685629929e957abd2643176b3337e4
--- /dev/null
+++ b/arch/arm/include/kinetis/kinetis_mcg.h
@@ -0,0 +1,620 @@
+/************************************************************************************
+ * arch/arm/include/kinetis/kinetis_mcg.h
+ *
+ * Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt
+ * David Sidrane
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_MCG_H
+#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_MCG_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Note: It is envisioned that in the long term as a chip is added. The author of
+ * the new chip definitions will either find the exact configuration in an existing
+ * chip define and add the new chip to it Or add the MCG feature configuration
+ * #defines to the chip ifdef list below. In either case the author should mark
+ * it as "Verified to Document Number:" taken from the reference manual.
+ *
+ * To maintain backward compatibility to the version of NuttX prior to
+ * 2/5/2017, the catch all KINETIS_MCG_VERSION_UKN configuration is assigned
+ * to all the chips that did not have any conditional compilation based on
+ * NEW_MCG or KINETIS_K64. This is a "No worse" than the original code solution.
+ * N.B. Each original chip "if"definitions have been left intact so that the
+ * complete legacy definitions prior to 2/5/2017 may be filled in completely when
+ * vetted.
+ */
+
+/* MCG Configuration Parameters
+ *
+ * KINETIS_MCG_PLL_REF_MIN - OSCCLK/PLL_R minimum
+ * KINETIS_MCG_PLL_REF_MAX - OSCCLK/PLL_R maximum
+ * KINETIS_MCG_PLL_INTERNAL_DIVBY - The PLL clock is divided by n before VCO divider
+ * KINETIS_MCG_HAS_PLL_EXTRA_DIVBY - Is PLL clock divided by n before MCG PLL/FLL
+ * clock selection in the SIM module
+ * KINETIS_MCG_FFCLK_DIVBY - MCGFFCLK divided by n
+ * KINETIS_MCG_HAS_IRC_48M - Has 48MHz internal oscillator
+ * KINETIS_MCG_HAS_LOW_FREQ_IRC - Has LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]
+ * KINETIS_MCG_HAS_HIGH_FREQ_IRC - Has HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]
+ * KINETIS_MCG_HAS_PLL_INTERNAL_MODE - Has PEI mode or PBI mode
+ * KINETIS_MCG_HAS_RESET_IS_BLPI - Has Reset clock mode is BLPI
+ *
+ * MCG Register Configuration
+ *
+ * KINETIS_MCG_HAS_C1 - SoC has C1 Register
+ * KINETIS_MCG_HAS_C1_IREFS - SoC has C1[IREFS]
+ * KINETIS_MCG_HAS_C1_FRDIV - SoC has C1[FRDIV]
+ * KINETIS_MCG_C1_FRDIV_MAX - C1[FRDIV] maximum value 5=1024, 6=1280 7=1536
+ * KINETIS_MCG_HAS_C2 - SoC has C2 Register
+ * KINETIS_MCG_HAS_C2_HGO - SoC has C2[HGO]
+ * KINETIS_MCG_HAS_C2_RANGE - SoC has C2[RANG]
+ * KINETIS_MCG_HAS_C2_FCFTRIM - SoC has C2[FCFTRIM]
+ * KINETIS_MCG_HAS_C2_LOCRE0 - SoC has C2[LOCRE0]
+ * KINETIS_MCG_HAS_C3 - SoC has C3 Register
+ * KINETIS_MCG_HAS_C4 - SoC has C4 Register
+ * KINETIS_MCG_HAS_C5 - SoC has C5 Register
+ * KINETIS_MCG_HAS_C5_PRDIV - SoC has C5[PRDIV]
+ * KINETIS_MCG_C5_PRDIV_BASE - PRDIV base value corresponding to 0 in C5[PRDIV]
+ * KINETIS_MCG_C5_PRDIV_MAX - The Maximum value of C5[PRVDIV])
+ * KINETIS_MCG_C5_PRDIV_BITS - Has n bits of phase-locked loop (PLL) PRDIV (register C5[PRDIV]
+ * KINETIS_MCG_HAS_C5_PLLREFSEL0 - SoC has C5[PLLREFSEL0]
+ * KINETIS_MCG_HAS_C6 - SoC has C6 Register
+ * KINETIS_MCG_HAS_C6_VDIV - SoC has C6[VDIV]
+ * KINETIS_MCG_C6_VDIV_BASE - VDIV base value corresponding to 0 in C6[VDIV]
+ * KINETIS_MCG_C6_VDIV_MAX - The Maximum value of C6[VDIV]
+ * KINETIS_MCG_HAS_C6_CME - SoC has C6[CME]
+ * KINETIS_MCG_HAS_C6_PLLS - SoC has C6[PLLS]
+ * KINETIS_MCG_HAS_C6_LOLIE0 - SoC has C6[LOLIE0]
+ * KINETIS_MCG_HAS_S - SoC has S Register
+ * KINETIS_MCG_HAS_S_PLLST - SoC has S[PLLST]
+ * KINETIS_MCG_HAS_S_LOCK0 - SoC has S[LOCK0]
+ * KINETIS_MCG_HAS_S_LOLS - SoC has S[LOLS]
+ * KINETIS_MCG_HAS_ATC - SoC has ATC Register
+ * KINETIS_MCG_HAS_ATCVH - SoC has ATCVH Register
+ * KINETIS_MCG_HAS_ATCVL - SoC has ATCVL Register
+ * KINETIS_MCG_HAS_SC - SoC has SC Register
+ * KINETIS_MCG_HAS_SC_ATMS - SoC has SC[ATMS]
+ * KINETIS_MCG_HAS_SC_ATMF - SoC has SC[ATMF]
+ * KINETIS_MCG_HAS_SC_ATME - SoC has SC[ATME]
+ * KINETIS_MCG_HAS_C7 - SoC has C7 Register
+ * KINETIS_MCG_HAS_C7_OSCSEL - SoC has C7[OSCSEL]
+ * KINETIS_MCG_C7_OSCSEL_BITS - C7[OSCSEL] is n bits wide
+ * KINETIS_MCG_HAS_C8 - SoC has C8 Register
+ * KINETIS_MCG_HAS_C8_LOCS1 - SoC has C8[LOCS1]
+ * KINETIS_MCG_HAS_C8_CME1 - SoC has C8[CME1]
+ * KINETIS_MCG_HAS_C8_LOLRE - SoC has C8[LOLRE]
+ * KINETIS_MCG_HAS_C8_LOCRE1 - SoC has C8[LOCRE1]
+ * KINETIS_MCG_HAS_C9 - SoC has C9 Register
+ * KINETIS_MCG_HAS_C9_EXT_PLL_LOCS - SoC has C9_EXT_PLL[LOCS]
+ * KINETIS_MCG_HAS_C9_PLL_LOCRE - SoC has C9_PLL[LOCRE]
+ * KINETIS_MCG_HAS_C9_PLL_CME - SoC has C9_PLL[CME]
+ * KINETIS_MCG_HAS_C10 - SoC has C10 Register
+ * KINETIS_MCG_HAS_C10_LOCS1 - SoC has C10[LOCS1]
+ * KINETIS_MCG_HAS_C11 - SoC has C11 Register
+ * KINETIS_MCG_HAS_C11_PLL1OSC1 - SoC has C1[PRDIV1], C11[PLLSTEN1], C11[PLLCLKEN1], C11[PLLREFSEL1],
+ * KINETIS_MCG_HAS_C11_PLLCS - SoC has C11[PLLCS]
+ * KINETIS_MCG_HAS_C11_PLLREFSEL1 - SoC has C11[PLLREFSEL1]
+ * KINETIS_MCG_HAS_C12 - SoC has C12 Register
+ * KINETIS_MCG_HAS_S2 - SoC has S2 Register
+ * KINETIS_MCG_HAS_S2_PLL1OSC1 - SoC has S2[LOCS2], S2[OSCINIT1], S2[LOCK1], S2[LOLS1]
+ * KINETIS_MCG_HAS_S2_PLLCST - SoC has S2[PLLCST]
+ */
+
+/* Describe the version of the MCG
+ *
+ * These defines are not related to any NXP reference but are merely
+ * a way to label the versions we are using
+ */
+
+#define KINETIS_MCG_VERSION_UKN -1 /* What was in nuttx prior to 2/5/2017 */
+#define KINETIS_MCG_VERSION_01 1 /* The addition of MK60FN1M0VLQ12 Previously known as KINETIS_NEW_MCG
+ * Verified Document Number: K60P144M150SF3RM Rev. 3, November 2014 */
+#define KINETIS_MCG_VERSION_04 4 /* Verified to Document Number: K64P144M120SF5RM Rev. 2, January 2014 */
+#define KINETIS_MCG_VERSION_06 6 /* Verified to Document Number: K66P144M180SF5RMV2 Rev. 2, May 2015 */
+
+/* MK20DX/DN---VLH5
+ *
+ * ------------- ------ --- ------- ------ ------- ------ ----- ----
+ * PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO
+ * FREQ CNT FLASH FLASH
+ * ------------- ------ --- ------- ------ ------- ------ ----- ----
+ * MK20DN32VLH5 50 MHz 64 LQFP 32 KB 32 KB — 8 KB 40
+ * MK20DX32VLH5 50 MHz 64 LQFP 64 KB 32 KB 2 KB 8 KB 40
+ * MK20DN64VLH5 50 MHz 64 LQFP 64 KB 64 KB — 16 KB 40
+ * MK20DX64VLH5 50 MHz 64 LQFP 96 KB 64 KB 2 KB 16 KB 40
+ * MK20DN128VLH5 50 MHz 64 LQFP 128 KB 128 KB — 16 KB 40
+ * MK20DX128VLH5 50 MHz 64 LQFP 160 KB 128 KB 2 KB 16 KB 40
+ */
+
+#if defined(CONFIG_ARCH_CHIP_MK20DN32VLH5) || \
+ defined(CONFIG_ARCH_CHIP_MK20DX32VLH5) || \
+ defined(CONFIG_ARCH_CHIP_MK20DN64VLH5) || \
+ defined(CONFIG_ARCH_CHIP_MK20DX64VLH5) || \
+ defined(CONFIG_ARCH_CHIP_MK20DN128VLH5) || \
+ defined(CONFIG_ARCH_CHIP_MK20DX128VLH5)
+
+# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
+
+/* MK20DX---VLH7
+ *
+ * ------------- ------ --- ------- ------ ------- ------ ----- ----
+ * PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO
+ * FREQ CNT FLASH FLASH
+ * ------------- ------ --- ------- ------ ------- ------ ----- ----
+ * MK20DX64VLH7 72 MHz 64 LQFP 96 KB 64 KB 2 KB 16 KB 40
+ * MK20DX128VLH7 72 MHz 64 LQFP 160 KB 128 KB 2 KB 32 KB 40
+ * MK20DX256VLH7 72 MHz 64 LQFP 288 KB 256 KB 2 KB 64 KB 40
+ * ------------- ------ --- ------- ------ ------- ------ ----- ----
+ */
+
+#elif defined(CONFIG_ARCH_CHIP_MK20DX64VLH7) || defined(CONFIG_ARCH_CHIP_MK20DX128VLH7) || \
+ defined(CONFIG_ARCH_CHIP_MK20DX256VLH7)
+
+# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK40X64VFX50) || defined(CONFIG_ARCH_CHIP_MK40X64VLH50) || \
+ defined(CONFIG_ARCH_CHIP_MK40X64VLK50) || defined(CONFIG_ARCH_CHIP_MK40X64VMB50)
+
+# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK40X128VFX50) || defined(CONFIG_ARCH_CHIP_MK40X128VLH50) || \
+ defined(CONFIG_ARCH_CHIP_MK40X128VLK50) || defined(CONFIG_ARCH_CHIP_MK40X128VMB50) || \
+ defined(CONFIG_ARCH_CHIP_MK40X128VLL50) || defined(CONFIG_ARCH_CHIP_MK40X128VML50) || \
+ defined(CONFIG_ARCH_CHIP_MK40X128VFX72) || defined(CONFIG_ARCH_CHIP_MK40X128VLH72) || \
+ defined(CONFIG_ARCH_CHIP_MK40X128VLK72) || defined(CONFIG_ARCH_CHIP_MK40X128VMB72) || \
+ defined(CONFIG_ARCH_CHIP_MK40X128VLL72) || defined(CONFIG_ARCH_CHIP_MK40X128VML72)
+
+# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK40X256VLK72) || defined(CONFIG_ARCH_CHIP_MK40X256VMB72) || \
+ defined(CONFIG_ARCH_CHIP_MK40X256VLL72) || defined(CONFIG_ARCH_CHIP_MK40X256VML72)
+
+# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100)
+
+# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100)
+
+# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK40N512VLK100) || defined(CONFIG_ARCH_CHIP_MK40N512VMB100) || \
+ defined(CONFIG_ARCH_CHIP_MK40N512VLL100) || defined(CONFIG_ARCH_CHIP_MK40N512VML100) || \
+ defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100)
+
+# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60N256VLL100)
+
+# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60X256VLL100)
+
+# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60N512VLL100)
+
+# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60N256VML100)
+
+# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60X256VML100)
+
+# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60N512VML100)
+
+# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100)
+
+# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60X256VLQ100)
+
+# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60N512VLQ100)
+
+# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60N256VMD100)
+
+# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60X256VMD100)
+
+# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60N512VMD100)
+
+# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60FN1M0VLQ12)
+
+/* Verified to Document Number: K60P144M100SF2V2RM Rev. 2 Jun 2012 */
+
+# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_01
+
+/* MCG Configuration Parameters */
+
+# define KINETIS_MCG_PLL_REF_MIN 8000000 /* OSCCLK/PLL_R minimum */
+# define KINETIS_MCG_PLL_REF_MAX 16000000 /* OSCCLK/PLL_R maximum */
+# define KINETIS_MCG_PLL_INTERNAL_DIVBY 2 /* The PLL clock is divided by 2 before VCO divider */
+# define KINETIS_MCG_HAS_PLL_EXTRA_DIVBY 2 /* Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module */
+# define KINETIS_MCG_FFCLK_DIVBY 2 /* MCGFFCLK divided by 2 */
+# undef KINETIS_MCG_HAS_IRC_48M /* Has no 48MHz internal oscillator */
+# undef KINETIS_MCG_HAS_LOW_FREQ_IRC /* Has LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2] */
+# undef KINETIS_MCG_HAS_HIGH_FREQ_IRC /* Has HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN] */
+# undef KINETIS_MCG_HAS_PLL_INTERNAL_MODE /* Has PEI mode or PBI mode */
+# undef KINETIS_MCG_HAS_RESET_IS_BLPI /* Has Reset clock mode is BLPI */
+
+/* MCG Register Configuration */
+
+# define KINETIS_MCG_HAS_C1 1 /* SoC has C1 Register */
+# define KINETIS_MCG_HAS_C1_IREFS 1 /* SoC has C1[IREFS] */
+# define KINETIS_MCG_HAS_C1_FRDIV 1 /* SoC has C1[FRDIV] */
+# define KINETIS_MCG_C1_FRDIV_MAX 7 /* C1[FRDIV] maximum value 5=1024, 6=1280 7=1536 */
+# define KINETIS_MCG_HAS_C2 1 /* SoC has C2 Register */
+# define KINETIS_MCG_HAS_C2_HGO 1 /* SoC has C2[HGO] */
+# define KINETIS_MCG_HAS_C2_RANGE 1 /* SoC has C2[RANGE] */
+# undef KINETIS_MCG_HAS_C2_FCFTRIM /* SoC has C2[FCFTRIM] */
+# define KINETIS_MCG_HAS_C2_LOCRE0 1 /* SoC has C2[LOCRE0] */
+# define KINETIS_MCG_HAS_C3 1 /* SoC has C3 Register */
+# define KINETIS_MCG_HAS_C4 1 /* SoC has C4 Register */
+# define KINETIS_MCG_HAS_C5 1 /* SoC has C5 Register */
+# define KINETIS_MCG_HAS_C5_PRDIV 1 /* SoC has C5[PRDIV] */
+# define KINETIS_MCG_C5_PRDIV_BASE 1 /* PRDIV base value corresponding to 0 in C5[PRDIV] */
+# define KINETIS_MCG_C5_PRDIV_MAX 8 /* The Maximum value of C5[PRVDIV]) */
+# define KINETIS_MCG_C5_PRDIV_BITS 3 /* Has 3 bits of phase-locked loop (PLL) PRDIV (register C5[PRDIV] */
+# define KINETIS_MCG_HAS_C5_PLLREFSEL0 1 /* SoC has C5[PLLREFSEL0] */
+# define KINETIS_MCG_HAS_C6 1 /* SoC has C6 Register */
+# define KINETIS_MCG_HAS_C6_VDIV 1 /* SoC has C6[VDIV] */
+# define KINETIS_MCG_C6_VDIV_BASE 16 /* VDIV base value corresponding to 0 in C6[VDIV] */
+# define KINETIS_MCG_C6_VDIV_MAX 47 /* The Maximum value of C6[VDIV] */
+# define KINETIS_MCG_HAS_C6_CME 1 /* SoC has C6[CME] */
+# define KINETIS_MCG_HAS_C6_PLLS 1 /* SoC has C6[PLLS] */
+# define KINETIS_MCG_HAS_C6_LOLIE0 1 /* SoC has C6[LOLIE0] */
+# define KINETIS_MCG_HAS_S 1 /* SoC has S Register */
+# define KINETIS_MCG_HAS_S_PLLST 1 /* SoC has S[PLLST] */
+# define KINETIS_MCG_HAS_S_LOCK0 1 /* SoC has S[LOCK0] */
+# define KINETIS_MCG_HAS_S_LOLS 1 /* SoC has S[LOLS] */
+# undef KINETIS_MCG_HAS_ATC /* SoC has ATC Register */
+# define KINETIS_MCG_HAS_ATCVH 1 /* SoC has ATCVH Register */
+# define KINETIS_MCG_HAS_ATCVL 1 /* SoC has ATCVL Register */
+# define KINETIS_MCG_HAS_SC 1 /* SoC has SC Register */
+# define KINETIS_MCG_HAS_SC_ATMS 1 /* SoC has SC[ATMS] */
+# define KINETIS_MCG_HAS_SC_ATMF 1 /* SoC has SC[ATMF] */
+# define KINETIS_MCG_HAS_SC_ATME 1 /* SoC has SC[ATME] */
+# define KINETIS_MCG_HAS_C7 1 /* SoC has C7 Register */
+# define KINETIS_MCG_HAS_C7_OSCSEL 1 /* SoC has C7[OSCSEL] */
+# define KINETIS_MCG_C7_OSCSEL_BITS 1 /* C7[OSCSEL] is n bits wide */
+# define KINETIS_MCG_HAS_C8 1 /* SoC has C8 Register */
+# define KINETIS_MCG_HAS_C8_LOCS1 1 /* SoC has C8[LOCS1] */
+# define KINETIS_MCG_HAS_C8_CME1 1 /* SoC has C8[CME1] */
+# undef KINETIS_MCG_HAS_C8_LOLRE /* SoC has C8[LOLRE] */
+# define KINETIS_MCG_HAS_C8_LOCRE1 1 /* SoC has C8[LOCRE1] */
+# undef KINETIS_MCG_HAS_C9 1 /* SoC has C9 Register */
+# undef KINETIS_MCG_HAS_C9_EXT_PLL_LOCS 1 /* SoC has C9_EXT_PLL[LOCS] */
+# undef KINETIS_MCG_HAS_C9_PLL_LOCRE 1 /* SoC has C9_PLL[LOCRE] */
+# undef KINETIS_MCG_HAS_C9_PLL_CME 1 /* SoC has C9_PLL[CME] */
+# define KINETIS_MCG_HAS_C10 /* SoC has C10 Register */
+# undef KINETIS_MCG_HAS_C10_LOCS1 /* SoC has C10[LOCS1] */
+# define KINETIS_MCG_HAS_C11 /* SoC has C11 Register */
+# define KINETIS_MCG_HAS_C11_PLL1OSC1 1 /* SoC has C1[PRDIV1], C11[PLLSTEN1], C11[PLLCLKEN1], C11[PLLREFSEL1] */
+# define KINETIS_MCG_HAS_C11_PLLCS /* SoC has C11[PLLCS] */
+# define KINETIS_MCG_HAS_C11_PLLREFSEL1 1 /* SoC has C11[PLLREFSEL1] */
+# define KINETIS_MCG_HAS_C12 /* SoC has C12 Register */
+# define KINETIS_MCG_HAS_S2 /* SoC has S2 Register */
+# define KINETIS_MCG_HAS_S2_PLL1OSC1 1 /* SoC has S2[LOCS2], S2[OSCINIT1], S2[LOCK1], S2[LOLS1] */
+# define KINETIS_MCG_HAS_S2_PLLCST /* SoC has S2[PLLCST] */
+
+#elif defined(CONFIG_ARCH_CHIP_MK64FN1M0VLL12) || defined(CONFIG_ARCH_CHIP_MK64FX512VLL12) || \
+ defined(CONFIG_ARCH_CHIP_MK64FX512VDC12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VDC12) || \
+ defined(CONFIG_ARCH_CHIP_MK64FX512VLQ12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VLQ12) || \
+ defined(CONFIG_ARCH_CHIP_MK64FX512VMD12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VMD12)
+
+/* Verified to Document Number: K64P144M120SF5RM Rev. 2, January 2014 */
+
+# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_04
+
+/* MCG Configuration Parameters */
+
+# define KINETIS_MCG_PLL_REF_MIN 2000000 /* OSCCLK/PLL_R minimum */
+# define KINETIS_MCG_PLL_REF_MAX 4000000 /* OSCCLK/PLL_R maximum */
+# define KINETIS_MCG_PLL_INTERNAL_DIVBY 1 /* The PLL clock is divided by 1 before VCO divider */
+# define KINETIS_MCG_HAS_PLL_EXTRA_DIVBY 1 /* Is PLL clock divided by 1 before MCG PLL/FLL clock selection in the SIM module */
+# define KINETIS_MCG_FFCLK_DIVBY 2 /* MCGFFCLK divided by 2 */
+# define KINETIS_MCG_HAS_IRC_48M 1 /* Has 48MHz internal oscillator */
+# undef KINETIS_MCG_HAS_LOW_FREQ_IRC /* Has LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2] */
+# undef KINETIS_MCG_HAS_HIGH_FREQ_IRC /* Has HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN] */
+# undef KINETIS_MCG_HAS_PLL_INTERNAL_MODE /* Has PEI mode or PBI mode */
+# undef KINETIS_MCG_HAS_RESET_IS_BLPI /* Has Reset clock mode is BLPI */
+
+/* MCG Register Configuration */
+
+# define KINETIS_MCG_HAS_C1 1 /* SoC has C1 Register */
+# define KINETIS_MCG_HAS_C1_IREFS 1 /* SoC has C1[IREFS] */
+# define KINETIS_MCG_HAS_C1_FRDIV 1 /* SoC has C1[FRDIV] */
+# define KINETIS_MCG_C1_FRDIV_MAX 7 /* C1[FRDIV] maximum value 5=1024, 6=1280 7=1536 */
+# define KINETIS_MCG_HAS_C2 1 /* SoC has C2 Register */
+# define KINETIS_MCG_HAS_C2_HGO 1 /* SoC has C2[HGO] */
+# define KINETIS_MCG_HAS_C2_RANGE 1 /* SoC has C2[RANGE] */
+# define KINETIS_MCG_HAS_C2_FCFTRIM 1 /* SoC has C2[FCFTRIM] */
+# define KINETIS_MCG_HAS_C2_LOCRE0 1 /* SoC has C2[LOCRE0] */
+# define KINETIS_MCG_HAS_C3 1 /* SoC has C3 Register */
+# define KINETIS_MCG_HAS_C4 1 /* SoC has C4 Register */
+# define KINETIS_MCG_HAS_C5 1 /* SoC has C5 Register */
+# define KINETIS_MCG_HAS_C5_PRDIV 1 /* SoC has C5[PRDIV] */
+# define KINETIS_MCG_C5_PRDIV_BASE 1 /* PRDIV base value corresponding to 0 in C5[PRDIV] */
+# define KINETIS_MCG_C5_PRDIV_MAX 25 /* The Maximum value of C5[PRVDIV]) */
+# define KINETIS_MCG_C5_PRDIV_BITS 5 /* Has 5 bits of phase-locked loop (PLL) PRDIV (register C5[PRDIV] */
+# undef KINETIS_MCG_HAS_C5_PLLREFSEL0 /* SoC has C5[PLLREFSEL0] */
+# define KINETIS_MCG_HAS_C6 1 /* SoC has C6 Register */
+# define KINETIS_MCG_HAS_C6_VDIV 1 /* SoC has C6[VDIV] */
+# define KINETIS_MCG_C6_VDIV_BASE 24 /* VDIV base value corresponding to 0 in C6[VDIV] */
+# define KINETIS_MCG_C6_VDIV_MAX 55 /* The Maximum value of C6[VDIV] */
+# define KINETIS_MCG_HAS_C6_CME 1 /* SoC has C6[CME] */
+# define KINETIS_MCG_HAS_C6_PLLS 1 /* SoC has C6[PLLS] */
+# define KINETIS_MCG_HAS_C6_LOLIE0 1 /* SoC has C6[LOLIE0] */
+# define KINETIS_MCG_HAS_S 1 /* SoC has S Register */
+# define KINETIS_MCG_HAS_S_PLLST 1 /* SoC has S[PLLST] */
+# define KINETIS_MCG_HAS_S_LOCK0 1 /* SoC has S[LOCK0] */
+# define KINETIS_MCG_HAS_S_LOLS 1 /* SoC has S[LOLS] */
+# undef KINETIS_MCG_HAS_ATC /* SoC has ATC Register */
+# define KINETIS_MCG_HAS_ATCVH 1 /* SoC has ATCVH Register */
+# define KINETIS_MCG_HAS_ATCVL 1 /* SoC has ATCVL Register */
+# define KINETIS_MCG_HAS_SC 1 /* SoC has SC Register */
+# define KINETIS_MCG_HAS_SC_ATMS 1 /* SoC has SC[ATMS] */
+# define KINETIS_MCG_HAS_SC_ATMF 1 /* SoC has SC[ATMF] */
+# define KINETIS_MCG_HAS_SC_ATME 1 /* SoC has SC[ATME] */
+# define KINETIS_MCG_HAS_C7 1 /* SoC has C7 Register */
+# define KINETIS_MCG_HAS_C7_OSCSEL 1 /* SoC has C7[OSCSEL] */
+# define KINETIS_MCG_C7_OSCSEL_BITS 2 /* C7[OSCSEL] is n bits wide */
+# define KINETIS_MCG_HAS_C8 1 /* SoC has C8 Register */
+# define KINETIS_MCG_HAS_C8_LOCS1 1 /* SoC has C8[LOCS1] */
+# define KINETIS_MCG_HAS_C8_CME1 1 /* SoC has C8[CME1] */
+# define KINETIS_MCG_HAS_C8_LOLRE 1 /* SoC has C8[LOLRE] */
+# define KINETIS_MCG_HAS_C8_LOCRE1 1 /* SoC has C8[LOCRE1] */
+# undef KINETIS_MCG_HAS_C9 /* SoC has C9 Register */
+# undef KINETIS_MCG_HAS_C9_EXT_PLL_LOCS /* SoC has C9_EXT_PLL[LOCS] */
+# undef KINETIS_MCG_HAS_C9_PLL_LOCRE /* SoC has C9_PLL[LOCRE] */
+# undef KINETIS_MCG_HAS_C9_PLL_CME /* SoC has C9_PLL[CME] */
+# undef KINETIS_MCG_HAS_C10 /* SoC has C10 Register */
+# undef KINETIS_MCG_HAS_C10_LOCS1 /* SoC has C10[LOCS1] */
+# undef KINETIS_MCG_HAS_C11 /* SoC has C11 Register */
+# undef KINETIS_MCG_HAS_C11_PLL1OSC1 /* SoC has C1[PRDIV1], C11[PLLSTEN1], C11[PLLCLKEN1], C11[PLLREFSEL1] */
+# undef KINETIS_MCG_HAS_C11_PLLCS /* SoC has C11[PLLCS] */
+# undef KINETIS_MCG_HAS_C11_PLLREFSEL1 /* SoC has C11[PLLREFSEL1] */
+# undef KINETIS_MCG_HAS_C12 /* SoC has C12 Register */
+# undef KINETIS_MCG_HAS_S2 /* SoC has S2 Register */
+# undef KINETIS_MCG_HAS_S2_PLL1OSC1 /* SoC has S2[LOCS2], S2[OSCINIT1], S2[LOCK1], S2[LOLS1] */
+# undef KINETIS_MCG_HAS_S2_PLLCST /* SoC has S2[PLLCST] */
+
+/* MK66F N/X 1M0/2M0 V MD/LQ 18
+ *
+ * --------------- ------- --- ------- ------- ------ ------ ------ -----
+ * PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO
+ * FREQ CNT FLASH FLASH
+ * --------------- ------- --- ------- ------- ------ ------ ------ -----
+ * MK66FN2M0VMD18 180 MHz 144 MAPBGA 2 MB — — KB 260 KB 100
+ * MK66FX1M0VMD18 180 MHz 144 MAPBGA 1.25 MB 1 MB 4 KB 256 KB 100
+ * MK66FN2M0VLQ18 180 MHz 144 LQFP 2 MB — — KB 260 KB 100
+ * MK66FX1M0VLQ18 180 MHz 144 LQFP 1.25 MB 1 MB 4 KB 256 KB 100
+ */
+
+#elif defined(CONFIG_ARCH_CHIP_MK66FN2M0VMD18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VMD18) || \
+ defined(CONFIG_ARCH_CHIP_MK66FN2M0VLQ18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VLQ18)
+
+/* Verified to Document Number: Document Number: K66P144M180SF5RMV2 Rev. 2, May 2015 */
+
+# define KINETIS_MCG_VERSION KINETIS_MCG_VERSION_06
+
+/* MCG Configuration Parameters */
+
+# define KINETIS_MCG_PLL_REF_MIN 8000000 /* OSCCLK/PLL_R minimum */
+# define KINETIS_MCG_PLL_REF_MAX 16000000 /* OSCCLK/PLL_R maximum */
+# define KINETIS_MCG_PLL_INTERNAL_DIVBY 2 /* The PLL clock is divided by 2 before VCO divider */
+# define KINETIS_MCG_HAS_PLL_EXTRA_DIVBY 1 /* Is PLL clock divided by 1 before MCG PLL/FLL clock selection in the SIM module */
+# define KINETIS_MCG_FFCLK_DIVBY 2 /* MCGFFCLK divided by 2 */
+# define KINETIS_MCG_HAS_IRC_48M 1 /* Has 48MHz internal oscillator */
+# undef KINETIS_MCG_HAS_LOW_FREQ_IRC /* Has LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2] */
+# undef KINETIS_MCG_HAS_HIGH_FREQ_IRC /* Has HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN] */
+# undef KINETIS_MCG_HAS_PLL_INTERNAL_MODE /* Has PEI mode or PBI mode */
+# undef KINETIS_MCG_HAS_RESET_IS_BLPI /* Has Reset clock mode is BLPI */
+
+/* MCG Register Configuration */
+
+# define KINETIS_MCG_HAS_C1 1 /* SoC has C1 Register */
+# define KINETIS_MCG_HAS_C1_IREFS 1 /* SoC has C1[IREFS] */
+# define KINETIS_MCG_HAS_C1_FRDIV 1 /* SoC has C1[FRDIV] */
+# define KINETIS_MCG_C1_FRDIV_MAX 7 /* C1[FRDIV] maximum value 5=1024, 6=1280 7=1536 */
+# define KINETIS_MCG_HAS_C2 1 /* SoC has C2 Register */
+# define KINETIS_MCG_HAS_C2_HGO 1 /* SoC has C2[HGO] */
+# define KINETIS_MCG_HAS_C2_RANGE 1 /* SoC has C2[RANGE] */
+# define KINETIS_MCG_HAS_C2_FCFTRIM 1 /* SoC has C2[FCFTRIM] */
+# define KINETIS_MCG_HAS_C2_LOCRE0 1 /* SoC has C2[LOCRE0] */
+# define KINETIS_MCG_HAS_C3 1 /* SoC has C3 Register */
+# define KINETIS_MCG_HAS_C4 1 /* SoC has C4 Register */
+# define KINETIS_MCG_HAS_C5 1 /* SoC has C5 Register */
+# define KINETIS_MCG_HAS_C5_PRDIV 1 /* SoC has C5[PRDIV] */
+# define KINETIS_MCG_C5_PRDIV_BASE 1 /* PRDIV base value corresponding to 0 in C5[PRDIV] */
+# define KINETIS_MCG_C5_PRDIV_MAX 8 /* The Maximum value of C5[PRVDIV]) */
+# define KINETIS_MCG_C5_PRDIV_BITS 3 /* Has 3 bits of phase-locked loop (PLL) PRDIV (register C5[PRDIV] */
+# undef KINETIS_MCG_HAS_C5_PLLREFSEL0 /* SoC has C5[PLLREFSEL0] */
+# define KINETIS_MCG_HAS_C6 1 /* SoC has C6 Register */
+# define KINETIS_MCG_HAS_C6_VDIV 1 /* SoC has C6[VDIV] */
+# define KINETIS_MCG_C6_VDIV_BASE 16 /* VDIV base value corresponding to 0 in C6[VDIV] */
+# define KINETIS_MCG_C6_VDIV_MAX 47 /* The Maximum value of C6[VDIV] */
+# define KINETIS_MCG_HAS_C6_CME 1 /* SoC has C6[CME] */
+# define KINETIS_MCG_HAS_C6_PLLS 1 /* SoC has C6[PLLS] */
+# define KINETIS_MCG_HAS_C6_LOLIE0 1 /* SoC has C6[LOLIE0] */
+# define KINETIS_MCG_HAS_S 1 /* SoC has S Register */
+# define KINETIS_MCG_HAS_S_PLLST 1 /* SoC has S[PLLST] */
+# define KINETIS_MCG_HAS_S_LOCK0 1 /* SoC has S[LOCK0] */
+# define KINETIS_MCG_HAS_S_LOLS 1 /* SoC has S[LOLS] */
+# undef KINETIS_MCG_HAS_ATC /* SoC has ATC Register */
+# define KINETIS_MCG_HAS_ATCVH 1 /* SoC has ATCVH Register */
+# define KINETIS_MCG_HAS_ATCVL 1 /* SoC has ATCVL Register */
+# define KINETIS_MCG_HAS_SC 1 /* SoC has SC Register */
+# define KINETIS_MCG_HAS_SC_ATMS 1 /* SoC has SC[ATMS] */
+# define KINETIS_MCG_HAS_SC_ATMF 1 /* SoC has SC[ATMF] */
+# define KINETIS_MCG_HAS_SC_ATME 1 /* SoC has SC[ATME] */
+# define KINETIS_MCG_HAS_C7 1 /* SoC has C7 Register */
+# define KINETIS_MCG_HAS_C7_OSCSEL 1 /* SoC has C7[OSCSEL] */
+# define KINETIS_MCG_C7_OSCSEL_BITS 2 /* C7[OSCSEL] is n bits wide */
+# define KINETIS_MCG_HAS_C8 1 /* SoC has C8 Register */
+# define KINETIS_MCG_HAS_C8_LOCS1 1 /* SoC has C8[LOCS1] */
+# define KINETIS_MCG_HAS_C8_CME1 1 /* SoC has C8[CME1] */
+# define KINETIS_MCG_HAS_C8_LOLRE 1 /* SoC has C8[LOLRE] */
+# define KINETIS_MCG_HAS_C8_LOCRE1 1 /* SoC has C8[LOCRE1] */
+# define KINETIS_MCG_HAS_C9 1 /* SoC has C9 Register */
+# define KINETIS_MCG_HAS_C9_EXT_PLL_LOCS 1 /* SoC has C9_EXT_PLL[LOCS] */
+# define KINETIS_MCG_HAS_C9_PLL_LOCRE 1 /* SoC has C9_PLL[LOCRE] */
+# define KINETIS_MCG_HAS_C9_PLL_CME 1 /* SoC has C9_PLL[CME] */
+# undef KINETIS_MCG_HAS_C10 /* SoC has C10 Register */
+# undef KINETIS_MCG_HAS_C10_LOCS1 /* SoC has C10[LOCS1] */
+# define KINETIS_MCG_HAS_C11 /* SoC has C11 Register */
+# undef KINETIS_MCG_HAS_C11_PLL1OSC1 /* SoC has C1[PRDIV1], C11[PLLSTEN1], C11[PLLCLKEN1], C11[PLLREFSEL1] */
+# define KINETIS_MCG_HAS_C11_PLLCS /* SoC has C11[PLLCS] */
+# undef KINETIS_MCG_HAS_C11_PLLREFSEL1 /* SoC has C11[PLLREFSEL1] */
+# undef KINETIS_MCG_HAS_C12 /* SoC has C12 Register */
+# define KINETIS_MCG_HAS_S2 /* SoC has S2 Register */
+# undef KINETIS_MCG_HAS_S2_PLL1OSC1 /* SoC has S2[LOCS2], S2[OSCINIT1], S2[LOCK1], S2[LOLS1] */
+# define KINETIS_MCG_HAS_S2_PLLCST /* SoC has S2[PLLCST] */
+
+#else
+# error "Unsupported Kinetis chip"
+#endif
+
+/* Use the catch all configuration for the MCG based on the implementations in nuttx prior 2/3/2017 */
+
+#if KINETIS_MCG_VERSION == KINETIS_MCG_VERSION_UKN
+
+/* MCG Configuration Parameters */
+
+# define KINETIS_MCG_PLL_REF_MIN 2000000 /* OSCCLK/PLL_R minimum */
+# define KINETIS_MCG_PLL_REF_MAX 4000000 /* OSCCLK/PLL_R maximum */
+# define KINETIS_MCG_PLL_INTERNAL_DIVBY 1 /* The PLL clock is divided by 1 before VCO divider */
+# define KINETIS_MCG_HAS_PLL_EXTRA_DIVBY 1 /* Is PLL clock divided by 1 before MCG PLL/FLL clock selection in the SIM module */
+# define KINETIS_MCG_FFCLK_DIVBY 1 /* MCGFFCLK divided by 1 */
+# undef KINETIS_MCG_HAS_IRC_48M /* Has 48MHz internal oscillator */
+# undef KINETIS_MCG_HAS_LOW_FREQ_IRC /* Has LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2] */
+# undef KINETIS_MCG_HAS_HIGH_FREQ_IRC /* Has HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN] */
+# undef KINETIS_MCG_HAS_PLL_INTERNAL_MODE /* Has PEI mode or PBI mode */
+# undef KINETIS_MCG_HAS_RESET_IS_BLPI /* Has Reset clock mode is BLPI */
+
+/* MCG Register Configuration */
+
+# define KINETIS_MCG_HAS_C1 1 /* SoC has C1 Register */
+# define KINETIS_MCG_HAS_C1_IREFS 1 /* SoC has C1[IREFS] */
+# define KINETIS_MCG_HAS_C1_FRDIV 1 /* SoC has C1[FRDIV] */
+# define KINETIS_MCG_C1_FRDIV_MAX 5 /* C1[FRDIV] maximum value 5=1024, 6=1280 7=1536 */
+# define KINETIS_MCG_HAS_C2 1 /* SoC has C2 Register */
+# define KINETIS_MCG_HAS_C2_HGO 1 /* SoC has C2[HGO] */
+# define KINETIS_MCG_HAS_C2_RANGE 1 /* SoC has C2[RANGE] */
+# undef KINETIS_MCG_HAS_C2_FCFTRIM /* SoC has C2[FCFTRIM] */
+# undef KINETIS_MCG_HAS_C2_LOCRE0 /* SoC has C2[LOCRE0] */
+# define KINETIS_MCG_HAS_C3 1 /* SoC has C3 Register */
+# define KINETIS_MCG_HAS_C4 1 /* SoC has C4 Register */
+# define KINETIS_MCG_HAS_C5 1 /* SoC has C5 Register */
+# define KINETIS_MCG_HAS_C5_PRDIV 1 /* SoC has C5[PRDIV] */
+# define KINETIS_MCG_C5_PRDIV_BASE 1 /* PRDIV base value corresponding to 0 in C5[PRDIV] */
+# define KINETIS_MCG_C5_PRDIV_MAX 25 /* The Maximum value of C5[PRVDIV]) */
+# define KINETIS_MCG_C5_PRDIV_BITS 5 /* Has 5 bits of phase-locked loop (PLL) PRDIV (register C5[PRDIV] */
+# undef KINETIS_MCG_HAS_C5_PLLREFSEL0 /* SoC has C5[PLLREFSEL0] */
+# define KINETIS_MCG_HAS_C6 1 /* SoC has C6 Register */
+# define KINETIS_MCG_HAS_C6_VDIV 1 /* SoC has C6[VDIV] */
+# define KINETIS_MCG_C6_VDIV_BASE 24 /* VDIV base value corresponding to 0 in C6[VDIV] */
+# define KINETIS_MCG_C6_VDIV_MAX 55 /* The Maximum value of C6[VDIV] */
+# define KINETIS_MCG_HAS_C6_CME 1 /* SoC has C6[CME] */
+# define KINETIS_MCG_HAS_C6_PLLS 1 /* SoC has C6[PLLS] */
+# define KINETIS_MCG_HAS_C6_LOLIE0 1 /* SoC has C6[LOLIE0] */
+# define KINETIS_MCG_HAS_S 1 /* SoC has S Register */
+# define KINETIS_MCG_HAS_S_PLLST 1 /* SoC has S[PLLST] */
+# define KINETIS_MCG_HAS_S_LOCK0 1 /* SoC has S[LOCK0] */
+# define KINETIS_MCG_HAS_S_LOLS 1 /* SoC has S[LOLS] */
+# define KINETIS_MCG_HAS_ATC 1 /* SoC has ATC Register */
+# define KINETIS_MCG_HAS_ATCVH 1 /* SoC has ATCVH Register */
+# define KINETIS_MCG_HAS_ATCVL 1 /* SoC has ATCVL Register */
+# undef KINETIS_MCG_HAS_SC /* SoC has SC Register */
+# undef KINETIS_MCG_HAS_SC_ATMS /* SoC has SC[ATMS] */
+# undef KINETIS_MCG_HAS_SC_ATMF /* SoC has SC[ATMF] */
+# undef KINETIS_MCG_HAS_SC_ATME /* SoC has SC[ATME] */
+# undef KINETIS_MCG_HAS_C7 /* SoC has C7 Register */
+# undef KINETIS_MCG_HAS_C7_OSCSEL /* SoC has C7[OSCSEL] */
+# undef KINETIS_MCG_C7_OSCSEL_BITS /* C7[OSCSEL] is n bits wide */
+# undef KINETIS_MCG_HAS_C8 /* SoC has C8 Register */
+# undef KINETIS_MCG_HAS_C8_LOCS1 /* SoC has C8[LOCS1] */
+# undef KINETIS_MCG_HAS_C8_CME1 /* SoC has C8[CME1] */
+# undef KINETIS_MCG_HAS_C8_LOLRE /* SoC has C8[LOLRE] */
+# undef KINETIS_MCG_HAS_C8_LOCRE1 /* SoC has C8[LOCRE1] */
+# undef KINETIS_MCG_HAS_C9 /* SoC has C9 Register */
+# undef KINETIS_MCG_HAS_C9_EXT_PLL_LOCS /* SoC has C9_EXT_PLL[LOCS] */
+# undef KINETIS_MCG_HAS_C9_PLL_LOCRE /* SoC has C9_PLL[LOCRE] */
+# undef KINETIS_MCG_HAS_C9_PLL_CME /* SoC has C9_PLL[CME] */
+# undef KINETIS_MCG_HAS_C10 /* SoC has C10 Register */
+# undef KINETIS_MCG_HAS_C10_LOCS1 /* SoC has C10[LOCS1] */
+# undef KINETIS_MCG_HAS_C11 /* SoC has C11 Register */
+# undef KINETIS_MCG_HAS_C11_PLL1OSC1 /* SoC has C1[PRDIV1], C11[PLLSTEN1], C11[PLLCLKEN1], C11[PLLREFSEL1] */
+# undef KINETIS_MCG_HAS_C11_PLLCS /* SoC has C11[PLLCS] */
+# undef KINETIS_MCG_HAS_C11_PLLREFSEL1 /* SoC has C11[PLLREFSEL1] */
+# undef KINETIS_MCG_HAS_C12 /* SoC has C12 Register */
+# undef KINETIS_MCG_HAS_S2 /* SoC has S2 Register */
+# undef KINETIS_MCG_HAS_S2_PLL1OSC1 /* SoC has S2[LOCS2], S2[OSCINIT1], S2[LOCK1], S2[LOLS1] */
+# undef KINETIS_MCG_HAS_S2_PLLCST /* SoC has S2[PLLCST] */
+#endif
+
+#if !defined(KINETIS_MCG_VERSION)
+# error "No KINETIS_MCG_VERSION defined!"
+#endif
+
+#if defined(KINETIS_MCG_HAS_C5_PRDIV)
+# define KINETIS_MCG_C5_PRDIV_MASK ((1 << (KINETIS_MCG_C5_PRDIV_BITS))-1)
+#endif
+
+#if defined(KINETIS_MCG_HAS_C7_OSCSEL)
+# define KINETIS_MCG_C7_OSCSEL_MASK ((1 << (KINETIS_MCG_C7_OSCSEL_BITS))-1)
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_KINETIS_KINETIS_MCG_H */
diff --git a/arch/arm/include/kinetis/kinetis_pmc.h b/arch/arm/include/kinetis/kinetis_pmc.h
new file mode 100644
index 0000000000000000000000000000000000000000..03bc8958426d38b07d1d5646e66b2561456f973f
--- /dev/null
+++ b/arch/arm/include/kinetis/kinetis_pmc.h
@@ -0,0 +1,324 @@
+/************************************************************************************
+ * arch/arm/include/kinetis/kinetis_pmc.h
+ *
+ * Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt
+ * David Sidrane
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_PMC_H
+#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_PMC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Note: It is envisioned that in the long term as a chip is added. The author of
+ * the new chip definitions will either find the exact configuration in an existing
+ * chip define and add the new chip to it Or add the PMC feature configuration
+ * #defines to the chip ifdef list below. In either case the author should mark
+ * it as "Verified to Document Number:" taken from the reference manual.
+ *
+ * To maintain backward compatibility to the version of NuttX prior to
+ * 2/22/2017, the catch all KINETIS_PMC_VERSION_UKN configuration is assigned
+ * to all the chips that did not have any conditional compilation based on
+ * KINETIS_K64 or KINETIS_K66. This is a "No worse" than the original code solution.
+ * N.B. Each original chip "if"definitions have been left intact so that the
+ * complete legacy definitions prior to 2/22/2017 may be filled in completely when
+ * vetted.
+ */
+
+/* PMC Register Configuration
+ *
+ * KINETIS_PMC_HAS_REGSC - SoC has REGSC Register
+ * KINETIS_PMC_HAS_REGSC_ACKISO - SoC has REGSC[ACKISO]
+ * KINETIS_PMC_HAS_REGSC_VLPRS - SoC has REGSC[VLPRS]
+ * KINETIS_PMC_HAS_REGSC_VLPO - SoC has REGSC[VLPO]
+ * KINETIS_PMC_HAS_REGSC_REGFPM - SoC has REGSC[REGFPM]
+ * KINETIS_PMC_HAS_REGSC_BGEN - SoC has REGSC[BGEN]
+ * KINETIS_PMC_HAS_REGSC_TRAMPO - SoC has REGSC[TRAMPO]
+ * KINETIS_PMC_HAS_REGSC_REGONS - SoC has REGSC[REGONS]
+ */
+
+/* Describe the version of the PMC
+ *
+ * These defines are not related to any NXP reference but are merely
+ * a way to label the versions we are using
+ */
+
+#define KINETIS_PMC_VERSION_UKN -1 /* What was in nuttx prior to 2/22/2017 */
+#define KINETIS_PMC_VERSION_01 1 /* Verified Document Number: K60P144M150SF3RM Rev. 3, November 2014 */
+#define KINETIS_PMC_VERSION_04 4 /* Verified to Document Numbers:
+ * K20P64M72SF1RM Rev. 1.1, Dec 2012
+ * K64P144M120SF5RM Rev. 2, January 2014
+ * K66P144M180SF5RMV2 Rev. 2, May 2015 */
+
+/* MK20DX/DN---VLH5
+ *
+ * ------------- ------ --- ------- ------ ------- ------ ----- ----
+ * PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO
+ * FREQ CNT FLASH FLASH
+ * ------------- ------ --- ------- ------ ------- ------ ----- ----
+ * MK20DN32VLH5 50 MHz 64 LQFP 32 KB 32 KB — 8 KB 40
+ * MK20DX32VLH5 50 MHz 64 LQFP 64 KB 32 KB 2 KB 8 KB 40
+ * MK20DN64VLH5 50 MHz 64 LQFP 64 KB 64 KB — 16 KB 40
+ * MK20DX64VLH5 50 MHz 64 LQFP 96 KB 64 KB 2 KB 16 KB 40
+ * MK20DN128VLH5 50 MHz 64 LQFP 128 KB 128 KB — 16 KB 40
+ * MK20DX128VLH5 50 MHz 64 LQFP 160 KB 128 KB 2 KB 16 KB 40
+ */
+
+#if defined(CONFIG_ARCH_CHIP_MK20DN32VLH5) || \
+ defined(CONFIG_ARCH_CHIP_MK20DX32VLH5) || \
+ defined(CONFIG_ARCH_CHIP_MK20DN64VLH5) || \
+ defined(CONFIG_ARCH_CHIP_MK20DX64VLH5) || \
+ defined(CONFIG_ARCH_CHIP_MK20DN128VLH5) || \
+ defined(CONFIG_ARCH_CHIP_MK20DX128VLH5)
+
+# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
+
+/* MK20DX---VLH7
+ *
+ * ------------- ------ --- ------- ------ ------- ------ ----- ----
+ * PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO
+ * FREQ CNT FLASH FLASH
+ * ------------- ------ --- ------- ------ ------- ------ ----- ----
+ * MK20DX64VLH7 72 MHz 64 LQFP 96 KB 64 KB 2 KB 16 KB 40
+ * MK20DX128VLH7 72 MHz 64 LQFP 160 KB 128 KB 2 KB 32 KB 40
+ * MK20DX256VLH7 72 MHz 64 LQFP 288 KB 256 KB 2 KB 64 KB 40
+ * ------------- ------ --- ------- ------ ------- ------ ----- ----
+ */
+
+#elif defined(CONFIG_ARCH_CHIP_MK20DX64VLH7) || defined(CONFIG_ARCH_CHIP_MK20DX128VLH7) || \
+ defined(CONFIG_ARCH_CHIP_MK20DX256VLH7)
+
+/* Verified to Document Number: K20P64M72SF1RM Rev. 1.1, Dec 2012 */
+
+# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_04
+
+/* PMC Register Configuration */
+
+# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */
+# define KINETIS_PMC_HAS_REGSC_ACKISO 1 /* SoC has REGSC[ACKISO] */
+# undef KINETIS_PMC_HAS_REGSC_VLPRS /* SoC has REGSC[VLPRS] */
+# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */
+# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */
+# define KINETIS_PMC_HAS_REGSC_BGEN 1 /* SoC has REGSC[BGEN] */
+# undef KINETIS_PMC_HAS_REGSC_TRAMPO /* SoC has REGSC[TRAMPO] */
+# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */
+
+#elif defined(CONFIG_ARCH_CHIP_MK40X64VFX50) || defined(CONFIG_ARCH_CHIP_MK40X64VLH50) || \
+ defined(CONFIG_ARCH_CHIP_MK40X64VLK50) || defined(CONFIG_ARCH_CHIP_MK40X64VMB50)
+
+# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK40X128VFX50) || defined(CONFIG_ARCH_CHIP_MK40X128VLH50) || \
+ defined(CONFIG_ARCH_CHIP_MK40X128VLK50) || defined(CONFIG_ARCH_CHIP_MK40X128VMB50) || \
+ defined(CONFIG_ARCH_CHIP_MK40X128VLL50) || defined(CONFIG_ARCH_CHIP_MK40X128VML50) || \
+ defined(CONFIG_ARCH_CHIP_MK40X128VFX72) || defined(CONFIG_ARCH_CHIP_MK40X128VLH72) || \
+ defined(CONFIG_ARCH_CHIP_MK40X128VLK72) || defined(CONFIG_ARCH_CHIP_MK40X128VMB72) || \
+ defined(CONFIG_ARCH_CHIP_MK40X128VLL72) || defined(CONFIG_ARCH_CHIP_MK40X128VML72)
+
+# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK40X256VLK72) || defined(CONFIG_ARCH_CHIP_MK40X256VMB72) || \
+ defined(CONFIG_ARCH_CHIP_MK40X256VLL72) || defined(CONFIG_ARCH_CHIP_MK40X256VML72)
+
+# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100)
+
+# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100)
+
+# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK40N512VLK100) || defined(CONFIG_ARCH_CHIP_MK40N512VMB100) || \
+ defined(CONFIG_ARCH_CHIP_MK40N512VLL100) || defined(CONFIG_ARCH_CHIP_MK40N512VML100) || \
+ defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100)
+
+# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60N256VLL100)
+
+# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60X256VLL100)
+
+# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60N512VLL100)
+
+# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60N256VML100)
+
+# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60X256VML100)
+
+# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60N512VML100)
+
+# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100)
+
+# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60X256VLQ100)
+
+# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60N512VLQ100)
+
+# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60N256VMD100)
+
+# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60X256VMD100)
+
+# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60N512VMD100)
+
+# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60FN1M0VLQ12)
+
+/* Verified to Document Number: K60P144M100SF2V2RM Rev. 2 Jun 2012 */
+
+# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_01
+
+/* PMC Register Configuration */
+
+# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */
+# define KINETIS_PMC_HAS_REGSC_ACKISO 1 /* SoC has REGSC[ACKISO] */
+# undef KINETIS_PMC_HAS_REGSC_VLPRS /* SoC has REGSC[VLPRS] */
+# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */
+# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */
+# undef KINETIS_PMC_HAS_REGSC_BGEN /* SoC has REGSC[BGEN] */
+# undef KINETIS_PMC_HAS_REGSC_TRAMPO /* SoC has REGSC[TRAMPO] */
+# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */
+
+#elif defined(CONFIG_ARCH_CHIP_MK64FN1M0VLL12) || defined(CONFIG_ARCH_CHIP_MK64FX512VLL12) || \
+ defined(CONFIG_ARCH_CHIP_MK64FX512VDC12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VDC12) || \
+ defined(CONFIG_ARCH_CHIP_MK64FX512VLQ12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VLQ12) || \
+ defined(CONFIG_ARCH_CHIP_MK64FX512VMD12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VMD12)
+
+/* Verified to Document Number: K64P144M120SF5RM Rev. 2, January 2014 */
+
+# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_04
+
+/* PMC Register Configuration */
+
+# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */
+# define KINETIS_PMC_HAS_REGSC_ACKISO 1 /* SoC has REGSC[ACKISO] */
+# undef KINETIS_PMC_HAS_REGSC_VLPRS /* SoC has REGSC[VLPRS] */
+# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */
+# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */
+# define KINETIS_PMC_HAS_REGSC_BGEN 1 /* SoC has REGSC[BGEN] */
+# undef KINETIS_PMC_HAS_REGSC_TRAMPO /* SoC has REGSC[TRAMPO] */
+# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */
+
+/* MK66F N/X 1M0/2M0 V MD/LQ 18
+ *
+ * --------------- ------- --- ------- ------- ------ ------ ------ -----
+ * PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO
+ * FREQ CNT FLASH FLASH
+ * --------------- ------- --- ------- ------- ------ ------ ------ -----
+ * MK66FN2M0VMD18 180 MHz 144 MAPBGA 2 MB — — KB 260 KB 100
+ * MK66FX1M0VMD18 180 MHz 144 MAPBGA 1.25 MB 1 MB 4 KB 256 KB 100
+ * MK66FN2M0VLQ18 180 MHz 144 LQFP 2 MB — — KB 260 KB 100
+ * MK66FX1M0VLQ18 180 MHz 144 LQFP 1.25 MB 1 MB 4 KB 256 KB 100
+ */
+
+#elif defined(CONFIG_ARCH_CHIP_MK66FN2M0VMD18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VMD18) || \
+ defined(CONFIG_ARCH_CHIP_MK66FN2M0VLQ18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VLQ18)
+
+/* Verified to Document Number: Document Number: K66P144M180SF5RMV2 Rev. 2, May 2015 */
+
+# define KINETIS_PMC_VERSION KINETIS_PMC_VERSION_04
+
+/* PMC Register Configuration */
+
+# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */
+# define KINETIS_PMC_HAS_REGSC_ACKISO 1 /* SoC has REGSC[ACKISO] */
+# undef KINETIS_PMC_HAS_REGSC_VLPRS /* SoC has REGSC[VLPRS] */
+# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */
+# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */
+# define KINETIS_PMC_HAS_REGSC_BGEN 1 /* SoC has REGSC[BGEN] */
+# undef KINETIS_PMC_HAS_REGSC_TRAMPO /* SoC has REGSC[TRAMPO] */
+# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */
+
+#else
+# error "Unsupported Kinetis chip"
+#endif
+
+/* Use the catch all configuration for the PMC based on the implementations in nuttx prior 2/3/2017 */
+
+#if KINETIS_PMC_VERSION == KINETIS_PMC_VERSION_UKN
+
+/* PMC Register Configuration */
+
+# define KINETIS_PMC_HAS_REGSC 1 /* SoC has REGSC Register */
+# undef KINETIS_PMC_HAS_REGSC_ACKISO /* SoC has REGSC[ACKISO] */
+# define KINETIS_PMC_HAS_REGSC_VLPRS 1 /* SoC has REGSC[VLPRS] */
+# undef KINETIS_PMC_HAS_REGSC_VLPO /* SoC has REGSC[VLPO] */
+# undef KINETIS_PMC_HAS_REGSC_REGFPM /* SoC has REGSC[REGFPM] */
+# undef KINETIS_PMC_HAS_REGSC_BGEN /* SoC has REGSC[BGEN] */
+# define KINETIS_PMC_HAS_REGSC_TRAMPO 1 /* SoC has REGSC[TRAMPO] */
+# define KINETIS_PMC_HAS_REGSC_REGONS 1 /* SoC has REGSC[REGONS] */
+
+#endif
+
+#if !defined(KINETIS_PMC_VERSION)
+# error "No KINETIS_PMC_VERSION defined!"
+#endif
+
+#if defined(KINETIS_PMC_HAS_C5_PRDIV)
+# define KINETIS_PMC_C5_PRDIV_MASK ((1 << (KINETIS_PMC_C5_PRDIV_BITS))-1)
+#endif
+
+#if defined(KINETIS_PMC_HAS_C7_OSCSEL)
+# define KINETIS_PMC_C7_OSCSEL_MASK ((1 << (KINETIS_PMC_C7_OSCSEL_BITS))-1)
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_KINETIS_KINETIS_PMC_H */
diff --git a/arch/arm/include/kinetis/kinetis_sim.h b/arch/arm/include/kinetis/kinetis_sim.h
new file mode 100644
index 0000000000000000000000000000000000000000..224e8b0d787835c6f74b7f2e6855f6dfdff251f7
--- /dev/null
+++ b/arch/arm/include/kinetis/kinetis_sim.h
@@ -0,0 +1,1322 @@
+/************************************************************************************
+ * arch/arm/include/kinetis/kinetis_sim.h
+ *
+ * Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt
+ * David Sidrane
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_INCLUDE_KINETIS_KINETIS_SIM_H
+#define __ARCH_ARM_INCLUDE_KINETIS_KINETIS_SIM_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Note: It is envisioned that in the long term as a chip is added. The author of
+ * the new chip definitions will either find the exact configuration in an existing
+ * chip define and add the new chip to it Or add the SIM feature configuration
+ * #defines to the chip ifdef list below. In either case the author should mark
+ * it as "Verified to Document Number:" taken from the reference manual.
+ *
+ * To maintain backward compatibility to the version of NuttX prior to
+ * 2/16/2017, the catch all KINETIS_SIM_VERSION_UKN configuration is assigned
+ * to all the chips that did not have any conditional compilation based on
+ * KINETIS_K64 or KINETIS_K66. This is a "No worse" than the original code solution.
+ * N.B. Each original chip "if"definitions have been left intact so that the
+ * complete legacy definitions prior to 2/16/2017 may be filled in completely when
+ * vetted.
+ */
+
+/* SIM Register Configuration
+ *
+ * KINETIS_SIM_HAS_SOPT1 - SoC has SOPT1 Register
+ * KINETIS_SIM_HAS_SOPT1_OSC32KOUT - SoC has SOPT1[OSC32KOUT]
+ * KINETIS_SIM_HAS_SOPT1_OSC32KSEL - SoC has SOPT1[OSC32KSEL]
+ * KINETIS_SIM_HAS_SOPT1_OSC32KSEL_BITS - SoC has n bits SOPT1[OSC32KSEL]
+ * KINETIS_SIM_HAS_SOPT1_RAMSIZE - SoC has SOPT1[RAMSIZE]
+ * KINETIS_SIM_HAS_SOPT1_USBREGEN - SoC has SOPT1[USBREGEN]
+ * KINETIS_SIM_HAS_SOPT1_USBSSTBY - SoC has SOPT1[USBSSTBY]
+ * KINETIS_SIM_HAS_SOPT1_USBVSTBY - SoC has SOPT1[USBVSTBY]
+ * KINETIS_SIM_HAS_SOPT1CFG - SoC has SOPT1CFG Register
+ * KINETIS_SIM_HAS_SOPT1CFG_URWE - SoC has SOPT1CFG[URWE]
+ * KINETIS_SIM_HAS_SOPT1CFG_USSWE - SoC has SOPT1CFG[USSWE]
+ * KINETIS_SIM_HAS_SOPT1CFG_UVSWE - SoC has SOPT1CFG[UVSWE]
+ * KINETIS_SIM_HAS_USBPHYCTL - SoC has USBPHYCTL Register
+ * KINETIS_SIM_HAS_USBPHYCTL_USB3VOUTTRG - SoC has USBPHYCTL[USB3VOUTTRG]
+ * KINETIS_SIM_HAS_USBPHYCTL_USBDISILIM - SoC has USBPHYCTL[USBDISILIM]
+ * KINETIS_SIM_HAS_USBPHYCTL_USBVREGPD - SoC has USBPHYCTL[USBVREGPD]
+ * KINETIS_SIM_HAS_USBPHYCTL_USBVREGSEL - SoC has USBPHYCTL[USBVREGSEL]
+ * KINETIS_SIM_HAS_SOPT2 - SoC has SOPT2 Register
+ * KINETIS_SIM_HAS_SOPT2_CMTUARTPAD - SoC has SOPT2[CMTUARTPAD]
+ * KINETIS_SIM_HAS_SOPT2_FBSL - SoC has SOPT2[FBSL]
+ * KINETIS_SIM_HAS_SOPT2_FLEXIOSRC - SoC has SOPT2[FLEXIOSRC]
+ * KINETIS_SIM_HAS_SOPT2_LPUARTSRC - SoC has SOPT2[LPUARTSRC]
+ * KINETIS_SIM_HAS_SOPT2_PLLFLLSEL - SoC has SOPT2[PLLFLLSEL]
+ * KINETIS_SIM_HAS_SOPT2_PLLFLLSEL_BITS - SoC has n bits SOPT2[PLLFLLSEL]
+ * KINETIS_SIM_HAS_SOPT2_PTD7PAD - SoC has SOPT2[PTD7PAD]
+ * KINETIS_SIM_HAS_SOPT2_RMIISRC - SoC has SOPT2[RMIISRC]
+ * KINETIS_SIM_HAS_SOPT2_RTCCLKOUTSEL - SoC has SOPT2[RTCCLKOUTSEL]
+ * KINETIS_SIM_HAS_SOPT2_CLKOUTSEL - SoC has SOPT2[CLKOUTSEL]
+ * KINETIS_SIM_HAS_SOPT2_SDHCSRC - SoC has SOPT2[SDHCSRC]
+ * KINETIS_SIM_HAS_SOPT2_NFCSRC - SoC has SOPT2[NFCSRC]
+ * KINETIS_SIM_HAS_SOPT2_I2SSRC - SoC has SOPT2[I2SSRC]
+ * KINETIS_SIM_HAS_SOPT2_TIMESRC - SoC has SOPT2[TIMESRC]
+ * KINETIS_SIM_HAS_SOPT2_TPMSRC - SoC has SOPT2[TPMSRC]
+ * KINETIS_SIM_HAS_SOPT2_USBFSRC - SoC has SOPT2[USBFSRC]
+ * KINETIS_SIM_HAS_SOPT2_TRACECLKSEL - SoC has SOPT2[TRACECLKSEL]
+ * KINETIS_SIM_HAS_SOPT2_USBREGEN - SoC has SOPT2[USBREGEN]
+ * KINETIS_SIM_HAS_SOPT2_USBSLSRC - SoC has SOPT2[USBSLSRC]
+ * KINETIS_SIM_HAS_SOPT2_USBHSRC - SoC has SOPT2[USBHSRC]
+ * KINETIS_SIM_HAS_SOPT2_USBSRC - SoC has SOPT2[USBSRC]
+ * KINETIS_SIM_HAS_SOPT2_MCGCLKSEL - SoC has SOPT2[MCGCLKSEL]
+ * KINETIS_SIM_HAS_SOPT4 - SoC has SOPT4 Register
+ * KINETIS_SIM_HAS_SOPT4_FTM0FLT0 - SoC has SOPT4[FTM0FLT0]
+ * KINETIS_SIM_HAS_SOPT4_FTM0FLT1 - SoC has SOPT4[FTM0FLT1]
+ * KINETIS_SIM_HAS_SOPT4_FTM0FLT2 - SoC has SOPT4[FTM0FLT2]
+ * KINETIS_SIM_HAS_SOPT4_FTM0FLT3 - SoC has SOPT4[FTM0FLT3]
+ * KINETIS_SIM_HAS_SOPT4_FTM0TRG0SRC - SoC has SOPT4[FTM0TRG0SRC]
+ * KINETIS_SIM_HAS_SOPT4_FTM0TRG1SRC - SoC has SOPT4[FTM0TRG1SRC]
+ * KINETIS_SIM_HAS_SOPT4_FTM1CH0SRC - SoC has SOPT4[FTM1CH0SRC] 1, 3 if SOF
+ * KINETIS_SIM_HAS_SOPT4_FTM1FLT0 - SoC has SOPT4[FTM1FLT0]
+ * KINETIS_SIM_HAS_SOPT4_FTM1FLT1 - SoC has SOPT4[FTM1FLT1]
+ * KINETIS_SIM_HAS_SOPT4_FTM1FLT2 - SoC has SOPT4[FTM1FLT2]
+ * KINETIS_SIM_HAS_SOPT4_FTM1FLT3 - SoC has SOPT4[FTM1FLT3]
+ * KINETIS_SIM_HAS_SOPT4_FTM2CH0SRC - SoC has SOPT4[FTM2CH0SRC]
+ * KINETIS_SIM_HAS_SOPT4_FTM2CH1SRC - SoC has SOPT4[FTM2CH1SRC]
+ * KINETIS_SIM_HAS_SOPT4_FTM2FLT0 - SoC has SOPT4[FTM2FLT0]
+ * KINETIS_SIM_HAS_SOPT4_FTM2FLT1 - SoC has SOPT4[FTM2FLT1]
+ * KINETIS_SIM_HAS_SOPT4_FTM2FLT2 - SoC has SOPT4[FTM2FLT2]
+ * KINETIS_SIM_HAS_SOPT4_FTM2FLT3 - SoC has SOPT4[FTM2FLT3]
+ * KINETIS_SIM_HAS_SOPT4_FTM3CH0SRC - SoC has SOPT4[FTM3CH0SRC]
+ * KINETIS_SIM_HAS_SOPT4_FTM3FLT0 - SoC has SOPT4[FTM3FLT0]
+ * KINETIS_SIM_HAS_SOPT4_FTM3FLT1 - SoC has SOPT4[FTM3FLT1]
+ * KINETIS_SIM_HAS_SOPT4_FTM3FLT2 - SoC has SOPT4[FTM3FLT2]
+ * KINETIS_SIM_HAS_SOPT4_FTM3FLT3 - SoC has SOPT4[FTM3FLT3]
+ * KINETIS_SIM_HAS_SOPT4_FTM3TRG0SRC - SoC has SOPT4[FTM3TRG0SRC]
+ * KINETIS_SIM_HAS_SOPT4_FTM3TRG1SRC - SoC has SOPT4[FTM3TRG1SRC]
+ * KINETIS_SIM_HAS_SOPT4_TPM0CLKSEL - SoC has SOPT4[TPM0CLKSEL]
+ * KINETIS_SIM_HAS_SOPT4_TPM1CH0SRC - SoC has SOPT4[TPM1CH0SRC]
+ * KINETIS_SIM_HAS_SOPT4_TPM1CLKSEL - SoC has SOPT4[TPM1CLKSEL]
+ * KINETIS_SIM_HAS_SOPT4_TPM2CH0SRC - SoC has SOPT4[TPM2CH0SRC]
+ * KINETIS_SIM_HAS_SOPT4_TPM2CLKSEL - SoC has SOPT4[TPM2CLKSEL]
+ * KINETIS_SIM_HAS_SOPT5 - SoC has SOPT5 Register
+ * KINETIS_SIM_HAS_SOPT5_LPUART0RXSRC - SoC has SOPT5[LPUART0RXSRC]
+ * KINETIS_SIM_HAS_SOPT5_LPUART0TXSRC - SoC has SOPT5[LPUART0TXSRC]
+ * KINETIS_SIM_HAS_SOPT6 - SoC has SOPT6 Register
+ * KINETIS_SIM_HAS_SOPT6_MCC - SoC has SOPT6[MCC]
+ * KINETIS_SIM_HAS_SOPT6_PCR - SoC has SOPT6[PCR]
+ * KINETIS_SIM_HAS_SOPT6_RSTFLTSEL - SoC has SOPT6[RSTFLTSEL]
+ * KINETIS_SIM_HAS_SOPT6_RSTFLTEN - SoC has SOPT6[RSTFLTEN]
+ * KINETIS_SIM_HAS_SOPT7 - SoC has SOPT7 Register
+ * KINETIS_SIM_HAS_SOPT7_ADC0ALTTRGSEL - SoC has SOPT7[ADC0ALTTRGSEL]
+ * KINETIS_SIM_HAS_SOPT7_ADC1ALTTRGSEL - SoC has SOPT7[ADC1ALTTRGSEL]
+ * KINETIS_SIM_HAS_SOPT7_ADC0PRETRGSEL - SoC has SOPT7[ADC0PRETRGSEL]
+ * KINETIS_SIM_HAS_SOPT7_ADC1PRETRGSEL - SoC has SOPT7[ADC1PRETRGSEL]
+ * KINETIS_SIM_HAS_SOPT7_ADC2PRETRGSEL - SoC has SOPT7[ADC2PRETRGSEL]
+ * KINETIS_SIM_HAS_SOPT7_ADC3PRETRGSEL - SoC has SOPT7[ADC3PRETRGSEL]
+ * KINETIS_SIM_HAS_SOPT7_ADC0TRGSEL - SoC has n SOPT7[ADC0TRGSEL]
+ * KINETIS_SIM_HAS_SOPT7_ADC1TRGSEL - SoC has n SOPT7[ADC1TRGSEL]
+ * KINETIS_SIM_HAS_SOPT7_ADC2TRGSEL - SoC has n SOPT7[ADC2TRGSEL]
+ * KINETIS_SIM_HAS_SOPT7_ADC3TRGSEL - SoC has n SOPT7[ADC3TRGSEL]
+ * KINETIS_SIM_SOPT7_ADC0ALTTRGEN - SoC has ADC0 alternate trigger enable
+ * KINETIS_SIM_SOPT7_ADC1ALTTRGEN - SoC has ADC1 alternate trigger enable
+ * KINETIS_SIM_SOPT7_ADC2ALTTRGEN - SoC has ADC2 alternate trigger enable
+ * KINETIS_SIM_SOPT7_ADC3ALTTRGEN - SoC has ADC3 alternate trigger enable
+ * KINETIS_SIM_HAS_SOPT8 - SoC has SOPT8 Register
+ * KINETIS_SIM_HAS_SOPT8_FTM0SYNCBIT - SoC has SOPT8[FTM0SYNCBIT]
+ * KINETIS_SIM_HAS_SOPT8_FTM1SYNCBIT - SoC has SOPT8[FTM1SYNCBIT]
+ * KINETIS_SIM_HAS_SOPT8_FTM2SYNCBIT - SoC has SOPT8[FTM2SYNCBIT]
+ * KINETIS_SIM_HAS_SOPT8_FTM3SYNCBIT - SoC has SOPT8[FTM3SYNCBIT]
+ * KINETIS_SIM_HAS_SOPT8_FTM0OCH0SRC - SoC has SOPT8[FTM0OCH0SRC]
+ * KINETIS_SIM_HAS_SOPT8_FTM0OCH1SRC - SoC has SOPT8[FTM0OCH1SRC]
+ * KINETIS_SIM_HAS_SOPT8_FTM0OCH2SRC - SoC has SOPT8[FTM0OCH2SRC]
+ * KINETIS_SIM_HAS_SOPT8_FTM0OCH3SRC - SoC has SOPT8[FTM0OCH3SRC]
+ * KINETIS_SIM_HAS_SOPT8_FTM0OCH4SRC - SoC has SOPT8[FTM0OCH4SRC]
+ * KINETIS_SIM_HAS_SOPT8_FTM0OCH5SRC - SoC has SOPT8[FTM0OCH5SRC]
+ * KINETIS_SIM_HAS_SOPT8_FTM0OCH6SRC - SoC has SOPT8[FTM0OCH6SRC]
+ * KINETIS_SIM_HAS_SOPT8_FTM0OCH7SRC - SoC has SOPT8[FTM0OCH7SRC]
+ * KINETIS_SIM_HAS_SOPT8_FTM3OCH0SRC - SoC has SOPT8[FTM3OCH0SRC]
+ * KINETIS_SIM_HAS_SOPT8_FTM3OCH1SRC - SoC has SOPT8[FTM3OCH1SRC]
+ * KINETIS_SIM_HAS_SOPT8_FTM3OCH2SRC - SoC has SOPT8[FTM3OCH2SRC]
+ * KINETIS_SIM_HAS_SOPT8_FTM3OCH3SRC - SoC has SOPT8[FTM3OCH3SRC]
+ * KINETIS_SIM_HAS_SOPT8_FTM3OCH4SRC - SoC has SOPT8[FTM3OCH4SRC]
+ * KINETIS_SIM_HAS_SOPT8_FTM3OCH5SRC - SoC has SOPT8[FTM3OCH5SRC]
+ * KINETIS_SIM_HAS_SOPT8_FTM3OCH6SRC - SoC has SOPT8[FTM3OCH6SRC]
+ * KINETIS_SIM_HAS_SOPT8_FTM3OCH7SRC - SoC has SOPT8[FTM3OCH7SRC]
+ * KINETIS_SIM_HAS_SOPT9 - SoC has SOPT9 Register
+ * KINETIS_SIM_HAS_SOPT9_TPM1CH0SRC - SoC has SOPT9[TPM1CH0SRC]
+ * KINETIS_SIM_HAS_SOPT9_TPM2CH0SRC - SoC has SOPT9[TPM2CH0SRC]
+ * KINETIS_SIM_HAS_SOPT9_TPM1CLKSEL - SoC has SOPT9[TPM1CLKSEL]
+ * KINETIS_SIM_HAS_SOPT9_TPM2CLKSEL - SoC has SOPT9[TPM2CLKSEL]
+ * KINETIS_SIM_HAS_SDID - SoC has SDID Register
+ * KINETIS_SIM_HAS_SDID_DIEID - SoC has SDID[DIEID]
+ * KINETIS_SIM_HAS_SDID_FAMID - SoC has SDID[FAMID]
+ * KINETIS_SIM_HAS_SDID_FAMILYID - SoC has SDID[FAMILYID]
+ * KINETIS_SIM_HAS_SDID_SERIESID - SoC has SDID[SERIESID]
+ * KINETIS_SIM_HAS_SDID_SRAMSIZE - SoC has SDID[SRAMSIZE]
+ * KINETIS_SIM_HAS_SDID_SUBFAMID - SoC has SDID[SUBFAMID]
+ * KINETIS_SIM_HAS_SCGC1 - SoC has _SCGC1 Register
+ * KINETIS_SIM_HAS_SCGC1_UART5 - SoC has SCGC1[UART5]
+ * KINETIS_SIM_HAS_SCGC1_UART4 - SoC has SCGC1[UART4]
+ * KINETIS_SIM_HAS_SCGC1_I2C3 - SoC has SCGC1[I2C3]
+ * KINETIS_SIM_HAS_SCGC1_I2C2 - SoC has SCGC1[I2C2]
+ * KINETIS_SIM_HAS_SCGC1_OSC1 - SoC has SCGC1[OSC1]
+ * KINETIS_SIM_HAS_SCGC2 - SoC has SCGC2 Register
+ * KINETIS_SIM_HAS_SCGC2_ENET - SoC has SCGC2[ENET]
+ * KINETIS_SIM_HAS_SCGC2_LPUART0 - SoC has SCGC2[LPUART0]
+ * KINETIS_SIM_HAS_SCGC2_TPM1 - SoC has SCGC2[TPM1]
+ * KINETIS_SIM_HAS_SCGC2_TPM2 - SoC has SCGC2[TPM2]
+ * KINETIS_SIM_HAS_SCGC3 - SoC has SCGC3 Register
+ * KINETIS_SIM_HAS_SCGC3 - SoC has SCGC3 Register
+ * KINETIS_SIM_HAS_SCGC3_RNGA - SoC has SCGC3[RNGA]
+ * KINETIS_SIM_HAS_SCGC3_USBHS - SoC has SCGC3[USBHS]
+ * KINETIS_SIM_HAS_SCGC3_USBHSPHY - SoC has SCGC3[USBHSPHY]
+ * KINETIS_SIM_HAS_SCGC3_USBHSDCD - SoC has SCGC3[USBHSDCD]
+ * KINETIS_SIM_HAS_SCGC3_FLEXCAN1 - SoC has SCGC3[FLEXCAN1]
+ * KINETIS_SIM_HAS_SCGC3_NFC - SoC has SCGC3[NFC]
+ * KINETIS_SIM_HAS_SCGC3_SPI2 - SoC has SCGC3[SPI2]
+ * KINETIS_SIM_HAS_SCGC3_SAI1 - SoC has SCGC3[SAI1]
+ * KINETIS_SIM_HAS_SCGC3_SDHC - SoC has SCGC3[SDHC]
+ * KINETIS_SIM_HAS_SCGC3_FTM2 - SoC has SCGC3[FTM2]
+ * KINETIS_SIM_HAS_SCGC3_FTM3 - SoC has SCGC3[FTM3]
+ * KINETIS_SIM_HAS_SCGC3_ADC1 - SoC has SCGC3[ADC1]
+ * KINETIS_SIM_HAS_SCGC3_ADC3 - SoC has SCGC3[ADC3]
+ * KINETIS_SIM_HAS_SCGC3_SLCD - SoC has SCGC3[SLCD]
+ * KINETIS_SIM_HAS_SCGC4 - SoC has SCGC4 Register
+ * KINETIS_SIM_HAS_SCGC4_LLWU - SoC has SCGC4[LLWU] clock gate
+ * KINETIS_SIM_HAS_SCGC4_UART0 - SoC has SCGC4[UART0]
+ * KINETIS_SIM_HAS_SCGC4_UART1 - SoC has SCGC4[UART1]
+ * KINETIS_SIM_HAS_SCGC4_UART2 - SoC has SCGC4[UART2]
+ * KINETIS_SIM_HAS_SCGC4_UART3 - SoC has SCGC4[UART3]
+ * KINETIS_SIM_HAS_SCGC5 - SoC has _SCGC5 Register
+ * KINETIS_SIM_HAS_SCGC5_REGFILE - SoC has SCGC5[REGFILE]
+ * KINETIS_SIM_HAS_SCGC5_TSI - SoC has SCGC5[TSI]
+ * KINETIS_SIM_HAS_SCGC5_PORTF - SoC has SCGC5[PORTf]
+ * KINETIS_SIM_HAS_SCGC6 - SoC has SCGC6 Register
+ * KINETIS_SIM_HAS_SCGC6_FTFL - SoC has SCGC6[FTFL]
+ * KINETIS_SIM_HAS_SCGC6_DMAMUX1 - SoC has SCGC6[DEMUX1]
+ * KINETIS_SIM_HAS_SCGC6_USBHS - SoC has SCGC6[USBHS]
+ * KINETIS_SIM_HAS_SCGC6_RNGA - SoC has SCGC6[RNGA]
+ * KINETIS_SIM_HAS_SCGC6_FTM2 - SoC has SCGC6[FTM2]
+ * KINETIS_SIM_HAS_SCGC6_ADC2 - SoC has SCGC6[ADC2]
+ * KINETIS_SIM_HAS_SCGC6_DAC0 - SoC has SCGC6[DAC0]
+ * KINETIS_SIM_HAS_SCGC7 - SoC has SCGC7 Register
+ * KINETIS_SIM_HAS_SCGC7_FLEXBUS - SoC has SCGC7[FLEXBUS]
+ * KINETIS_SIM_HAS_SCGC7_DMA - SoC has SCGC7[DMS]
+ * KINETIS_SIM_HAS_SCGC7_MPU - SoC has SCGC7[MPU]
+ * KINETIS_SIM_HAS_SCGC7_SDRAMC - SoC has SCGC7[SDRAMC]
+ * KINETIS_SIM_HAS_CLKDIV1 - SoC has CLKDIV1 Register
+ * KINETIS_SIM_HAS_CLKDIV1_OUTDIV2 - SoC has CLKDIV1[OUTDIV2]
+ * KINETIS_SIM_HAS_CLKDIV1_OUTDIV3 - SoC has CLKDIV1[OUTDIV3]
+ * KINETIS_SIM_HAS_CLKDIV1_OUTDIV4 - SoC has CLKDIV1[OUTDIV4]
+ * KINETIS_SIM_HAS_CLKDIV1_OUTDIV5 - SoC has CLKDIV1[OUTDIV5]
+ * KINETIS_SIM_HAS_CLKDIV2 - SoC has CLKDIV2 Register
+ * KINETIS_SIM_HAS_CLKDIV2_USBDIV - SoC has CLKDIV2[USBDIV]
+ * KINETIS_SIM_HAS_CLKDIV2_USBFRAC - SoC has CLKDIV2[USBFRAC]
+ * KINETIS_SIM_HAS_CLKDIV2_I2SDIV - SoC has CLKDIV2[I2SDIV]
+ * KINETIS_SIM_HAS_CLKDIV2_I2SFRAC - SoC has CLKDIV2[I2SFRAC]
+ * KINETIS_SIM_HAS_CLKDIV2_USBHSDIV - SoC has CLKDIV2[USBHSDIV]
+ * KINETIS_SIM_HAS_CLKDIV2_USBHSFRAC - SoC has CLKDIV2[USBHSFRAC]
+ * KINETIS_SIM_HAS_FCFG1 - SoC has FCFG1 Register
+ * KINETIS_SIM_HAS_FCFG1_DEPART - SoC has FCFG1[DEPART]
+ * KINETIS_SIM_HAS_FCFG1_EESIZE - SoC has FCFG1[EESIZE]
+ * KINETIS_SIM_HAS_FCFG1_FLASHDIS - SoC has FCFG1[FLASHDIS]
+ * KINETIS_SIM_HAS_FCFG1_FLASHDOZE - SoC has FCFG1[FLASHDOZE]
+ * KINETIS_SIM_HAS_FCFG1_FTFDIS - SoC has FCFG1[FTFDIS]
+ * KINETIS_SIM_HAS_FCFG1_NVMSIZE - SoC has FCFG1[NVMSIZE]
+ * KINETIS_SIM_HAS_FCFG2 - SoC has FCFG2 Register
+ * KINETIS_SIM_HAS_FCFG2_MAXADDR0 - SoC has n bit of FCFG2[MAXADDR0]
+ * KINETIS_SIM_HAS_FCFG2_MAXADDR1 - SoC has n bit of FCFG2[MAXADDR1]
+ * KINETIS_SIM_HAS_FCFG2_PFLSH - SoC has FCFG2[PFLSH]
+ * KINETIS_SIM_HAS_FCFG2_SWAPPFLSH - SoC has FCFG2[SWAPPFLSH]
+ * KINETIS_SIM_HAS_UIDH - SoC has UIDH Register
+ * KINETIS_SIM_HAS_UIDMH - SoC has UIDMH Register
+ * KINETIS_SIM_HAS_UIDML - SoC has UIDML Register
+ * KINETIS_SIM_HAS_UIDL - SoC has UIDL Register
+ * KINETIS_SIM_HAS_CLKDIV3 - SoC has CLKDIV3 Register
+ * KINETIS_SIM_HAS_CLKDIV3_PLLFLLDIV - SoC has CLKDIV3[PLLFLLDIV]
+ * KINETIS_SIM_HAS_CLKDIV3_PLLFLLFRAC - SoC has CLKDIV3[PLLFLLFRAC]
+ * KINETIS_SIM_HAS_CLKDIV4 - SoC has CLKDIV4 Register
+ * KINETIS_SIM_HAS_CLKDIV4_TRACEDIV - SoC has CLKDIV4[TRACEDIV]
+ * KINETIS_SIM_HAS_CLKDIV4_TRACEFRAC - SoC has CLKDIV4[TRACEFRAC]
+ * KINETIS_SIM_HAS_CLKDIV4_NFCEDIV - SoC has CLKDIV4[NFCDIV]
+ * KINETIS_SIM_HAS_CLKDIV4_NFCFRAC - SoC has CLKDIV4[NFCFRAC]
+ * KINETIS_SIM_HAS_MCR - SoC has MCR Register
+ */
+
+/* Describe the version of the SIM
+ *
+ * These defines are not related to any NXP reference but are merely
+ * a way to label the versions we are using
+ */
+
+#define KINETIS_SIM_VERSION_UKN -1 /* What was in nuttx prior to 2/16/2017 */
+#define KINETIS_SIM_VERSION_01 1 /* Verified Document Number: K60P144M150SF3RM Rev. 3, November 2014 */
+#define KINETIS_SIM_VERSION_04 4 /* Verified to Document Number: K64P144M120SF5RM Rev. 2, January 2014 */
+#define KINETIS_SIM_VERSION_06 6 /* Verified to Document Number: K66P144M180SF5RMV2 Rev. 2, May 2015 */
+
+/* MK20DX/DN---VLH5
+ *
+ * ------------- ------ --- ------- ------ ------- ------ ----- ----
+ * PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO
+ * FREQ CNT FLASH FLASH
+ * ------------- ------ --- ------- ------ ------- ------ ----- ----
+ * MK20DN32VLH5 50 MHz 64 LQFP 32 KB 32 KB — 8 KB 40
+ * MK20DX32VLH5 50 MHz 64 LQFP 64 KB 32 KB 2 KB 8 KB 40
+ * MK20DN64VLH5 50 MHz 64 LQFP 64 KB 64 KB — 16 KB 40
+ * MK20DX64VLH5 50 MHz 64 LQFP 96 KB 64 KB 2 KB 16 KB 40
+ * MK20DN128VLH5 50 MHz 64 LQFP 128 KB 128 KB — 16 KB 40
+ * MK20DX128VLH5 50 MHz 64 LQFP 160 KB 128 KB 2 KB 16 KB 40
+ */
+
+#if defined(CONFIG_ARCH_CHIP_MK20DN32VLH5) || \
+ defined(CONFIG_ARCH_CHIP_MK20DX32VLH5) || \
+ defined(CONFIG_ARCH_CHIP_MK20DN64VLH5) || \
+ defined(CONFIG_ARCH_CHIP_MK20DX64VLH5) || \
+ defined(CONFIG_ARCH_CHIP_MK20DN128VLH5) || \
+ defined(CONFIG_ARCH_CHIP_MK20DX128VLH5)
+
+# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN
+
+/* MK20DX---VLH7
+ *
+ * ------------- ------ --- ------- ------ ------- ------ ----- ----
+ * PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO
+ * FREQ CNT FLASH FLASH
+ * ------------- ------ --- ------- ------ ------- ------ ----- ----
+ * MK20DX64VLH7 72 MHz 64 LQFP 96 KB 64 KB 2 KB 16 KB 40
+ * MK20DX128VLH7 72 MHz 64 LQFP 160 KB 128 KB 2 KB 32 KB 40
+ * MK20DX256VLH7 72 MHz 64 LQFP 288 KB 256 KB 2 KB 64 KB 40
+ * ------------- ------ --- ------- ------ ------- ------ ----- ----
+ */
+
+#elif defined(CONFIG_ARCH_CHIP_MK20DX64VLH7) || defined(CONFIG_ARCH_CHIP_MK20DX128VLH7) || \
+ defined(CONFIG_ARCH_CHIP_MK20DX256VLH7)
+
+# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK40X64VFX50) || defined(CONFIG_ARCH_CHIP_MK40X64VLH50) || \
+ defined(CONFIG_ARCH_CHIP_MK40X64VLK50) || defined(CONFIG_ARCH_CHIP_MK40X64VMB50)
+
+# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK40X128VFX50) || defined(CONFIG_ARCH_CHIP_MK40X128VLH50) || \
+ defined(CONFIG_ARCH_CHIP_MK40X128VLK50) || defined(CONFIG_ARCH_CHIP_MK40X128VMB50) || \
+ defined(CONFIG_ARCH_CHIP_MK40X128VLL50) || defined(CONFIG_ARCH_CHIP_MK40X128VML50) || \
+ defined(CONFIG_ARCH_CHIP_MK40X128VFX72) || defined(CONFIG_ARCH_CHIP_MK40X128VLH72) || \
+ defined(CONFIG_ARCH_CHIP_MK40X128VLK72) || defined(CONFIG_ARCH_CHIP_MK40X128VMB72) || \
+ defined(CONFIG_ARCH_CHIP_MK40X128VLL72) || defined(CONFIG_ARCH_CHIP_MK40X128VML72)
+
+# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK40X256VLK72) || defined(CONFIG_ARCH_CHIP_MK40X256VMB72) || \
+ defined(CONFIG_ARCH_CHIP_MK40X256VLL72) || defined(CONFIG_ARCH_CHIP_MK40X256VML72)
+
+# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100)
+
+# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100)
+
+# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK40N512VLK100) || defined(CONFIG_ARCH_CHIP_MK40N512VMB100) || \
+ defined(CONFIG_ARCH_CHIP_MK40N512VLL100) || defined(CONFIG_ARCH_CHIP_MK40N512VML100) || \
+ defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100)
+
+# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60N256VLL100)
+
+# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60X256VLL100)
+
+# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60N512VLL100)
+
+# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60N256VML100)
+
+# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60X256VML100)
+
+# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60N512VML100)
+
+# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100)
+
+# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60X256VLQ100)
+
+# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60N512VLQ100)
+
+# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60N256VMD100)
+
+# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60X256VMD100)
+
+# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60N512VMD100)
+
+# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_UKN
+
+#elif defined(CONFIG_ARCH_CHIP_MK60FN1M0VLQ12)
+
+/* Verified to Document Number: K60P144M100SF2V2RM Rev. 2 Jun 2012 */
+
+# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_01
+
+/* SIM Register Configuration */
+
+# define KINETIS_SIM_HAS_SOPT1 1 /* SoC has SOPT1 Register */
+# undef KINETIS_SIM_HAS_SOPT1_OSC32KOUT /* SoC has SOPT1[OSC32KOUT] */
+# define KINETIS_SIM_HAS_SOPT1_OSC32KSEL 1 /* SoC has SOPT1[OSC32KSEL] */
+# define KINETIS_SIM_HAS_SOPT1_OSC32KSEL_BITS 1 /* SoC has 1 bit SOPT1[OSC32KSEL] */
+# define KINETIS_SIM_HAS_SOPT1_RAMSIZE 1 /* SoC has SOPT1[RAMSIZE] */
+# define KINETIS_SIM_HAS_SOPT1_USBREGEN 1 /* SoC has SOPT1[USBREGEN] */
+# define KINETIS_SIM_HAS_SOPT1_USBSSTBY 1 /* SoC has SOPT1[USBSSTBY] */
+# define KINETIS_SIM_HAS_SOPT1_USBVSTBY 1 /* SoC has SOPT1[USBVSTBY] */
+# define KINETIS_SIM_HAS_SOPT1CFG /* SoC has SOPT1CFG Register */
+# define KINETIS_SIM_HAS_SOPT1CFG_URWE 1 /* SoC has SOPT1CFG[URWE] */
+# define KINETIS_SIM_HAS_SOPT1CFG_USSWE 1 /* SoC has SOPT1CFG[USSWE] */
+# define KINETIS_SIM_HAS_SOPT1CFG_UVSWE 1 /* SoC has SOPT1CFG[UVSWE] */
+# undef KINETIS_SIM_HAS_USBPHYCTL /* SoC has USBPHYCTL Register */
+# undef KINETIS_SIM_HAS_USBPHYCTL_USB3VOUTTRG /* SoC has USBPHYCTL[USB3VOUTTRG] */
+# undef KINETIS_SIM_HAS_USBPHYCTL_USBDISILIM /* SoC has USBPHYCTL[USBDISILIM] */
+# undef KINETIS_SIM_HAS_USBPHYCTL_USBVREGPD /* SoC has USBPHYCTL[USBVREGPD] */
+# undef KINETIS_SIM_HAS_USBPHYCTL_USBVREGSEL /* SoC has USBPHYCTL[USBVREGSEL] */
+# define KINETIS_SIM_HAS_SOPT2 1 /* SoC has SOPT2 Register */
+# define KINETIS_SIM_HAS_SOPT2_FBSL 1 /* SoC has SOPT2[FBSL] */
+# define KINETIS_SIM_HAS_SOPT2_CMTUARTPAD 1 /* SoC has SOPT2[CMTUARTPAD] */
+# define KINETIS_SIM_HAS_SOPT2_FLEXIOSRC 1 /* SoC has SOPT2[FLEXIOSRC] */
+# undef KINETIS_SIM_HAS_SOPT2_LPUARTSRC /* SoC has SOPT2[LPUARTSRC] */
+# define KINETIS_SIM_HAS_SOPT2_PLLFLLSEL 1 /* SoC has SOPT2[PLLFLLSEL] */
+# define KINETIS_SIM_HAS_SOPT2_PLLFLLSEL_BITS 2 /* SoC has 2 bits of SOPT2[PLLFLLSEL] */
+# undef KINETIS_SIM_HAS_SOPT2_PTD7PAD /* SoC has SOPT2[PTD7PAD] */
+# undef KINETIS_SIM_HAS_SOPT2_RMIISRC /* SoC has SOPT2[RMIISRC] */
+# define KINETIS_SIM_HAS_SOPT2_RTCCLKOUTSEL 1 /* SoC has SOPT2[RTCCLKOUTSEL] */
+# define KINETIS_SIM_HAS_SOPT2_CLKOUTSEL 1 /* SoC has SOPT2[CLKOUTSEL] */
+# define KINETIS_SIM_HAS_SOPT2_SDHCSRC 1 /* SoC has SOPT2[SDHCSRC] */
+# define KINETIS_SIM_HAS_SOPT2_NFCSRC 1 /* SoC has SOPT2[NFCSRC] */
+# undef KINETIS_SIM_HAS_SOPT2_I2SSRC /* SoC has SOPT2[I2SSRC] */
+# define KINETIS_SIM_HAS_SOPT2_TIMESRC 1 /* SoC has SOPT2[TIMESRC] */
+# undef KINETIS_SIM_HAS_SOPT2_TPMSRC /* SoC has SOPT2[TPMSRC] */
+# define KINETIS_SIM_HAS_SOPT2_USBFSRC 1 /* SoC has SOPT2[USBFSRC] */
+# define KINETIS_SIM_HAS_SOPT2_TRACECLKSEL 1 /* SoC has SOPT2[TRACECLKSEL] */
+# undef KINETIS_SIM_HAS_SOPT2_USBREGEN /* SoC has SOPT2[USBREGEN] */
+# undef KINETIS_SIM_HAS_SOPT2_USBSLSRC /* SoC has SOPT2[USBSLSRC] */
+# define KINETIS_SIM_HAS_SOPT2_USBHSRC 1 /* SoC has SOPT2[USBHSRC] */
+# define KINETIS_SIM_HAS_SOPT2_USBSRC 1 /* SoC has SOPT2[USBSRC] */
+# undef KINETIS_SIM_HAS_SOPT2_MCGCLKSEL /* SoC has SOPT2[MCGCLKSEL] */
+# define KINETIS_SIM_HAS_SOPT4 1 /* SoC has SOPT4 Register */
+# define KINETIS_SIM_HAS_SOPT4_FTM0FLT0 1 /* SoC has SOPT4[FTM0FLT0] */
+# define KINETIS_SIM_HAS_SOPT4_FTM0FLT1 1 /* SoC has SOPT4[FTM0FLT1] */
+# define KINETIS_SIM_HAS_SOPT4_FTM0FLT2 1 /* SoC has SOPT4[FTM0FLT2] */
+# define KINETIS_SIM_HAS_SOPT4_FTM0FLT3 1 /* SoC has SOPT4[FTM0FLT3] */
+# define KINETIS_SIM_HAS_SOPT4_FTM0TRG0SRC 1 /* SoC has SOPT4[FTM0TRG0SRC] */
+# define KINETIS_SIM_HAS_SOPT4_FTM0TRG1SRC 1 /* SoC has SOPT4[FTM0TRG1SRC] */
+# define KINETIS_SIM_HAS_SOPT4_FTM1CH0SRC 3 /* SoC has SOPT4[FTM1CH0SRC] 1, 3 if SOF */
+# define KINETIS_SIM_HAS_SOPT4_FTM1FLT0 1 /* SoC has SOPT4[FTM1FLT0] */
+# define KINETIS_SIM_HAS_SOPT4_FTM1FLT1 1 /* SoC has SOPT4[FTM1FLT1] */
+# define KINETIS_SIM_HAS_SOPT4_FTM1FLT2 1 /* SoC has SOPT4[FTM1FLT2] */
+# define KINETIS_SIM_HAS_SOPT4_FTM1FLT3 1 /* SoC has SOPT4[FTM1FLT3] */
+# define KINETIS_SIM_HAS_SOPT4_FTM2CH0SRC 1 /* SoC has SOPT4[FTM2CH0SRC] */
+# undef KINETIS_SIM_HAS_SOPT4_FTM2CH1SRC /* SoC has SOPT4[FTM2CH1SRC] */
+# define KINETIS_SIM_HAS_SOPT4_FTM2FLT0 1 /* SoC has SOPT4[FTM2FLT0] */
+# define KINETIS_SIM_HAS_SOPT4_FTM2FLT1 1 /* SoC has SOPT4[FTM2FLT1] */
+# define KINETIS_SIM_HAS_SOPT4_FTM2FLT2 1 /* SoC has SOPT4[FTM2FLT2] */
+# define KINETIS_SIM_HAS_SOPT4_FTM2FLT3 1 /* SoC has SOPT4[FTM2FLT3] */
+# define KINETIS_SIM_HAS_SOPT4_FTM3CH0SRC 1 /* SoC has SOPT4[FTM3CH0SRC] */
+# define KINETIS_SIM_HAS_SOPT4_FTM3FLT0 1 /* SoC has SOPT4[FTM3FLT0] */
+# define KINETIS_SIM_HAS_SOPT4_FTM3FLT1 1 /* SoC has SOPT4[FTM3FLT1] */
+# define KINETIS_SIM_HAS_SOPT4_FTM3FLT2 1 /* SoC has SOPT4[FTM3FLT2] */
+# define KINETIS_SIM_HAS_SOPT4_FTM3FLT3 1 /* SoC has SOPT4[FTM3FLT3] */
+# define KINETIS_SIM_HAS_SOPT4_FTM3TRG0SRC 1 /* SoC has SOPT4[FTM3TRG0SRC] */
+# define KINETIS_SIM_HAS_SOPT4_FTM3TRG1SRC 1 /* SoC has SOPT4[FTM3TRG1SRC] */
+# define KINETIS_SIM_HAS_SOPT4_TPM0CLKSEL 1 /* SoC has SOPT4[TPM0CLKSEL] */
+# define KINETIS_SIM_HAS_SOPT4_TPM1CH0SRC 1 /* SoC has SOPT4[TPM1CH0SRC] */
+# define KINETIS_SIM_HAS_SOPT4_TPM1CLKSEL 1 /* SoC has SOPT4[TPM1CLKSEL] */
+# define KINETIS_SIM_HAS_SOPT4_TPM2CH0SRC 1 /* SoC has SOPT4[TPM2CH0SRC] */
+# define KINETIS_SIM_HAS_SOPT4_TPM2CLKSEL 1 /* SoC has SOPT4[TPM2CLKSEL] */
+# define KINETIS_SIM_HAS_SOPT5 1 /* SoC has SOPT5 Register */
+# undef KINETIS_SIM_HAS_SOPT5_LPUART0RXSRC /* SoC has SOPT5[LPUART0RXSRC] */
+# undef KINETIS_SIM_HAS_SOPT5_LPUART0TXSRC /* SoC has SOPT5[LPUART0TXSRC] */
+# define KINETIS_SIM_HAS_SOPT6 1 /* SoC has SOPT6 Register */
+# define KINETIS_SIM_HAS_SOPT6_MCC 1 /* SoC has SOPT6[MCC] */
+# define KINETIS_SIM_HAS_SOPT6_PCR 1 /* SoC has SOPT6[PCR] */
+# undef KINETIS_SIM_HAS_SOPT6_RSTFLTSEL /* SoC has SOPT6[RSTFLTSEL] */
+# undef KINETIS_SIM_HAS_SOPT6_RSTFLTEN /* SoC has SOPT6[RSTFLTEN] */
+# define KINETIS_SIM_HAS_SOPT7 1 /* SoC has SOPT7 Register */
+# define KINETIS_SIM_HAS_SOPT7_ADC0ALTTRGSEL 1 /* SoC has SOPT7[ADC0ALTTRGSEL] */
+# define KINETIS_SIM_HAS_SOPT7_ADC1ALTTRGSEL 1 /* SoC has SOPT7[ADC1ALTTRGSEL] */
+# define KINETIS_SIM_HAS_SOPT7_ADC0PRETRGSEL 1 /* SoC has SOPT7[ADC0PRETRGSEL] */
+# define KINETIS_SIM_HAS_SOPT7_ADC1PRETRGSEL 1 /* SoC has SOPT7[ADC1PRETRGSEL] */
+# define KINETIS_SIM_HAS_SOPT7_ADC2PRETRGSEL 1 /* SoC has SOPT7[ADC2PRETRGSEL] */
+# define KINETIS_SIM_HAS_SOPT7_ADC3PRETRGSEL 1 /* SoC has SOPT7[ADC3PRETRGSEL] */
+# define KINETIS_SIM_HAS_SOPT7_ADC0TRGSEL 15 /* SoC has 15 SOPT7[ADC0TRGSEL] */
+# define KINETIS_SIM_HAS_SOPT7_ADC1TRGSEL 15 /* SoC has 15 SOPT7[ADC1TRGSEL] */
+# define KINETIS_SIM_HAS_SOPT7_ADC2TRGSEL 15 /* SoC has 15 SOPT7[ADC2TRGSEL] */
+# define KINETIS_SIM_HAS_SOPT7_ADC3TRGSEL 15 /* SoC has 15 SOPT7[ADC3TRGSEL] */
+# define KINETIS_SIM_SOPT7_ADC0ALTTRGEN 1 /* ADC0 alternate trigger enable */
+# define KINETIS_SIM_SOPT7_ADC1ALTTRGEN 1 /* ADC1 alternate trigger enable */
+# define KINETIS_SIM_SOPT7_ADC2ALTTRGEN 1 /* ADC2 alternate trigger enable */
+# define KINETIS_SIM_SOPT7_ADC3ALTTRGEN 1 /* ADC3 alternate trigger enable */
+# undef KINETIS_SIM_HAS_SOPT8 /* SoC has SOPT8 Register */
+# undef KINETIS_SIM_HAS_SOPT8_FTM0SYNCBIT /* SoC has SOPT8[FTM0SYNCBIT] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM1SYNCBIT /* SoC has SOPT8[FTM1SYNCBIT] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM2SYNCBIT /* SoC has SOPT8[FTM2SYNCBIT] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM3SYNCBIT /* SoC has SOPT8[FTM3SYNCBIT] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH0SRC /* SoC has SOPT8[FTM0OCH0SRC] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH1SRC /* SoC has SOPT8[FTM0OCH1SRC] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH2SRC /* SoC has SOPT8[FTM0OCH2SRC] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH3SRC /* SoC has SOPT8[FTM0OCH3SRC] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH4SRC /* SoC has SOPT8[FTM0OCH4SRC] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH5SRC /* SoC has SOPT8[FTM0OCH5SRC] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH6SRC /* SoC has SOPT8[FTM0OCH6SRC] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH7SRC /* SoC has SOPT8[FTM0OCH7SRC] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH0SRC /* SoC has SOPT8[FTM3OCH0SRC] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH1SRC /* SoC has SOPT8[FTM3OCH1SRC] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH2SRC /* SoC has SOPT8[FTM3OCH2SRC] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH3SRC /* SoC has SOPT8[FTM3OCH3SRC] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH4SRC /* SoC has SOPT8[FTM3OCH4SRC] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH5SRC /* SoC has SOPT8[FTM3OCH5SRC] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH6SRC /* SoC has SOPT8[FTM3OCH6SRC] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH7SRC /* SoC has SOPT8[FTM3OCH7SRC] */
+# undef KINETIS_SIM_HAS_SOPT9 /* SoC has SOPT9 Register */
+# undef KINETIS_SIM_HAS_SOPT9_TPM1CH0SRC /* SoC has SOPT9[TPM1CH0SRC] */
+# undef KINETIS_SIM_HAS_SOPT9_TPM2CH0SRC /* SoC has SOPT9[TPM2CH0SRC] */
+# undef KINETIS_SIM_HAS_SOPT9_TPM1CLKSEL /* SoC has SOPT9[TPM1CLKSEL] */
+# undef KINETIS_SIM_HAS_SOPT9_TPM2CLKSEL /* SoC has SOPT9[TPM2CLKSEL] */
+# define KINETIS_SIM_HAS_SDID 1 /* SoC has SDID Register */
+# undef KINETIS_SIM_HAS_SDID_DIEID /* SoC has SDID[DIEID] */
+# define KINETIS_SIM_HAS_SDID_FAMID 1 /* SoC has SDID[FAMID] */
+# undef KINETIS_SIM_HAS_SDID_FAMILYID /* SoC has SDID[FAMILYID] */
+# undef KINETIS_SIM_HAS_SDID_SERIESID /* SoC has SDID[SERIESID] */
+# undef KINETIS_SIM_HAS_SDID_SRAMSIZE /* SoC has SDID[SRAMSIZE] */
+# undef KINETIS_SIM_HAS_SDID_SUBFAMID /* SoC has SDID[SUBFAMID] */
+# define KINETIS_SIM_HAS_SCGC1 1 /* SoC has _SCGC1 Register */
+# define KINETIS_SIM_HAS_SCGC1_UART5 1 /* SoC has SCGC1[UART5] */
+# define KINETIS_SIM_HAS_SCGC1_UART4 1 /* SoC has SCGC1[UART4] */
+# undef KINETIS_SIM_HAS_SCGC1_I2C3 /* SoC has SCGC1[I2C3] */
+# undef KINETIS_SIM_HAS_SCGC1_I2C2 /* SoC has SCGC1[I2C2] */
+# define KINETIS_SIM_HAS_SCGC1_OSC1 1 /* SoC has SCGC1[OSC1] */
+# define KINETIS_SIM_HAS_SCGC2 1 /* SoC has _SCGC2 Register */
+# define KINETIS_SIM_HAS_SCGC2 1 /* SoC has SCGC2 Register */
+# define KINETIS_SIM_HAS_SCGC2_ENET 1 /* SoC has SCGC2[ENET] */
+# undef KINETIS_SIM_HAS_SCGC2_LPUART0 /* SoC has SCGC2[LPUART0] */
+# undef KINETIS_SIM_HAS_SCGC2_TPM1 /* SoC has SCGC2[TPM1] */
+# undef KINETIS_SIM_HAS_SCGC2_TPM2 /* SoC has SCGC2[TPM2] */
+# define KINETIS_SIM_HAS_SCGC3 1 /* SoC has SCGC3 Register */
+# define KINETIS_SIM_HAS_SCGC3_RNGA 1 /* SoC has SCGC3[RNGA] */
+# undef KINETIS_SIM_HAS_SCGC3_USBHS /* SoC has SCGC3[USBHS] */
+# undef KINETIS_SIM_HAS_SCGC3_USBHSPHY /* SoC has SCGC3[USBHSPHY] */
+# undef KINETIS_SIM_HAS_SCGC3_USBHSDCD /* SoC has SCGC3[USBHSDCD] */
+# define KINETIS_SIM_HAS_SCGC3_FLEXCAN1 1 /* SoC has SCGC3[FLEXCAN1] */
+# define KINETIS_SIM_HAS_SCGC3_NFC 1 /* SoC has SCGC3[NFC] */
+# define KINETIS_SIM_HAS_SCGC3_SPI2 1 /* SoC has SCGC3[SPI2] */
+# define KINETIS_SIM_HAS_SCGC3_SAI1 1 /* SoC has SCGC3[SAI1] */
+# define KINETIS_SIM_HAS_SCGC3_SDHC 1 /* SoC has SCGC3[SDHC] */
+# define KINETIS_SIM_HAS_SCGC3_FTM2 1 /* SoC has SCGC3[FTM2] */
+# define KINETIS_SIM_HAS_SCGC3_FTM3 1 /* SoC has SCGC3[FTM3] */
+# define KINETIS_SIM_HAS_SCGC3_ADC1 1 /* SoC has SCGC3[ADC1] */
+# define KINETIS_SIM_HAS_SCGC3_ADC3 1 /* SoC has SCGC3[ADC3] */
+# undef KINETIS_SIM_HAS_SCGC3_SLCD /* SoC has SCGC3[SLCD] */
+# define KINETIS_SIM_HAS_SCGC4 1 /* SoC has SCGC4 Register */
+# define KINETIS_SIM_HAS_SCGC4_LLWU 1 /* SoC has SCGC4[LLWU] clock gate */
+# define KINETIS_SIM_HAS_SCGC4_UART0 1 /* SoC has SCGC4[UART0] */
+# define KINETIS_SIM_HAS_SCGC4_UART1 1 /* SoC has SCGC4[UART1] */
+# define KINETIS_SIM_HAS_SCGC4_UART2 1 /* SoC has SCGC4[UART2] */
+# define KINETIS_SIM_HAS_SCGC4_UART3 1 /* SoC has SCGC4[UART3] */
+# define KINETIS_SIM_HAS_SCGC5 1 /* SoC has _SCGC5 Register */
+# undef KINETIS_SIM_HAS_SCGC5_REGFILE /* SoC has SCGC5[REGFILE] */
+# define KINETIS_SIM_HAS_SCGC5_TSI 1 /* SoC has SCGC5[TSI] */
+# define KINETIS_SIM_HAS_SCGC5_PORTF 1 /* SoC has SCGC5[PORTF] */
+# define KINETIS_SIM_HAS_SCGC6 1 /* SoC has SCGC6 Register */
+# undef KINETIS_SIM_HAS_SCGC6_FTFL /* SoC has SCGC6[FTFL] */
+# define KINETIS_SIM_HAS_SCGC6_DMAMUX1 1 /* SoC has SCGC6[DEMUX1] */
+# define KINETIS_SIM_HAS_SCGC6_USBHS 1 /* SoC has SCGC6[USBHS] */
+# define KINETIS_SIM_HAS_SCGC6_RNGA 1 /* SoC has SCGC6[RNGA] */
+# undef KINETIS_SIM_HAS_SCGC6_FTM2 /* SoC has SCGC6[FTM2] */
+# define KINETIS_SIM_HAS_SCGC6_ADC2 1 /* SoC has SCGC6[ADC2] */
+# undef KINETIS_SIM_HAS_SCGC6_DAC0 /* SoC has SCGC6[DAC0] */
+# define KINETIS_SIM_HAS_SCGC7 1 /* SoC has SCGC7 Register */
+# define KINETIS_SIM_HAS_SCGC7_FLEXBUS 1 /* SoC has SCGC7[FLEXBUS] */
+# define KINETIS_SIM_HAS_SCGC7_DMA 1 /* SoC has SCGC7[DMS] */
+# define KINETIS_SIM_HAS_SCGC7_MPU 1 /* SoC has SCGC7[MPU] */
+# undef KINETIS_SIM_HAS_SCGC7_SDRAMC /* SoC has SCGC7[SDRAMC] */
+# define KINETIS_SIM_HAS_CLKDIV1 1 /* SoC has CLKDIV1 Register */
+# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV2 1 /* SoC has CLKDIV1[OUTDIV2] */
+# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV3 1 /* SoC has CLKDIV1[OUTDIV3] */
+# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV4 1 /* SoC has CLKDIV1[OUTDIV4] */
+# undef KINETIS_SIM_HAS_CLKDIV1_OUTDIV5 /* SoC has CLKDIV1[OUTDIV5] */
+# define KINETIS_SIM_HAS_CLKDIV2 1 /* SoC has CLKDIV2 Register */
+# define KINETIS_SIM_HAS_CLKDIV2_USBDIV 1 /* SoC has CLKDIV2[USBDIV] */
+# define KINETIS_SIM_HAS_CLKDIV2_USBFRAC 1 /* SoC has CLKDIV2[USBFRAC] */
+# undef KINETIS_SIM_HAS_CLKDIV2_USBFSDIV /* SoC has CLKDIV2[USBFSDIV] */
+# undef KINETIS_SIM_HAS_CLKDIV2_USBFSFRAC /* SoC has CLKDIV2[USBFSFRAC] */
+# define KINETIS_SIM_HAS_CLKDIV2_USBHSDIV 1 /* SoC has CLKDIV2[USBHSDIV] */
+# define KINETIS_SIM_HAS_CLKDIV2_USBHSFRAC 1 /* SoC has CLKDIV2[USBHSFRAC] */
+# undef KINETIS_SIM_HAS_CLKDIV2_I2SDIV /* SoC has CLKDIV2[I2SDIV] */
+# undef KINETIS_SIM_HAS_CLKDIV2_I2SFRAC /* SoC has CLKDIV2[I2SFRAC] */
+# define KINETIS_SIM_HAS_FCFG1 1 /* SoC has FCFG1 Register */
+# define KINETIS_SIM_HAS_FCFG1_DEPART 1 /* SoC has FCFG1[DEPART] */
+# define KINETIS_SIM_HAS_FCFG1_EESIZE 1 /* SoC has FCFG1[EESIZE] */
+# undef KINETIS_SIM_HAS_FCFG1_FLASHDIS /* SoC has FCFG1[FLASHDIS] */
+# undef KINETIS_SIM_HAS_FCFG1_FLASHDOZE /* SoC has FCFG1[FLASHDOZE] */
+# define KINETIS_SIM_HAS_FCFG1_FTFDIS 1 /* SoC has FCFG1[FTFDIS] */
+# define KINETIS_SIM_HAS_FCFG1_NVMSIZE 1 /* SoC has FCFG1[NVMSIZE] */
+# define KINETIS_SIM_HAS_FCFG2 1 /* SoC has FCFG2 Register */
+# define KINETIS_SIM_HAS_FCFG2_MAXADDR0 6 /* SoC has n bit of FCFG2[MAXADDR0] */
+# define KINETIS_SIM_HAS_FCFG2_MAXADDR1 6 /* SoC has n bit of FCFG2[MAXADDR1] */
+# define KINETIS_SIM_HAS_FCFG2_PFLSH 1 /* SoC has FCFG2[PFLSH] */
+# define KINETIS_SIM_HAS_FCFG2_SWAPPFLSH 1 /* SoC has FCFG2[SWAPPFLSH] */
+# define KINETIS_SIM_HAS_UIDH 1 /* SoC has UIDH Register */
+# define KINETIS_SIM_HAS_UIDMH 1 /* SoC has UIDMH Register */
+# define KINETIS_SIM_HAS_UIDML 1 /* SoC has UIDML Register */
+# define KINETIS_SIM_HAS_UIDL 1 /* SoC has UIDL Register */
+# undef KINETIS_SIM_HAS_CLKDIV3 /* SoC has CLKDIV3 Register */
+# undef KINETIS_SIM_HAS_CLKDIV3_PLLFLLDIV /* SoC has CLKDIV3[PLLFLLDIV] */
+# undef KINETIS_SIM_HAS_CLKDIV3_PLLFLLFRAC /* SoC has CLKDIV3[PLLFLLFRAC] */
+# define KINETIS_SIM_HAS_CLKDIV4 1 /* SoC has CLKDIV4 Register */
+# define KINETIS_SIM_HAS_CLKDIV4_TRACEDIV 1 /* SoC has CLKDIV4[TRACEDIV] */
+# define KINETIS_SIM_HAS_CLKDIV4_TRACEFRAC 1 /* SoC has CLKDIV4[TRACEFRAC] */
+# define KINETIS_SIM_HAS_CLKDIV4_NFCDIV 1 /* SoC has CLKDIV4[NFCDIV] */
+# define KINETIS_SIM_HAS_CLKDIV4_NFCFRAC 1 /* SoC has CLKDIV4[NFCFRAC] */
+# define KINETIS_SIM_HAS_MCR 1 /* SoC has MCR Register */
+
+#elif defined(CONFIG_ARCH_CHIP_MK64FN1M0VLL12) || defined(CONFIG_ARCH_CHIP_MK64FX512VLL12) || \
+ defined(CONFIG_ARCH_CHIP_MK64FX512VDC12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VDC12) || \
+ defined(CONFIG_ARCH_CHIP_MK64FX512VLQ12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VLQ12) || \
+ defined(CONFIG_ARCH_CHIP_MK64FX512VMD12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VMD12)
+
+/* Verified to Document Number: K64P144M120SF5RM Rev. 2, January 2014 */
+
+# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_04
+
+/* SIM Register Configuration */
+
+# define KINETIS_SIM_HAS_SOPT1 1 /* SoC has SOPT1 Register */
+# undef KINETIS_SIM_HAS_SOPT1_OSC32KOUT /* SoC has SOPT1[OSC32KOUT] */
+# define KINETIS_SIM_HAS_SOPT1_OSC32KSEL 1 /* SoC has SOPT1[OSC32KSEL] */
+# define KINETIS_SIM_HAS_SOPT1_OSC32KSEL_BITS 2 /* SoC has 2 bits of SOPT1[OSC32KSEL] */
+# define KINETIS_SIM_HAS_SOPT1_RAMSIZE 1 /* SoC has SOPT1[RAMSIZE] */
+# define KINETIS_SIM_HAS_SOPT1_USBREGEN 1 /* SoC has SOPT1[USBREGEN] */
+# define KINETIS_SIM_HAS_SOPT1_USBSSTBY 1 /* SoC has SOPT1[USBSSTBY] */
+# define KINETIS_SIM_HAS_SOPT1_USBVSTBY 1 /* SoC has SOPT1[USBVSTBY] */
+# define KINETIS_SIM_HAS_SOPT1CFG /* SoC has SOPT1CFG Register */
+# define KINETIS_SIM_HAS_SOPT1CFG_URWE 1 /* SoC has SOPT1CFG[URWE] */
+# define KINETIS_SIM_HAS_SOPT1CFG_USSWE 1 /* SoC has SOPT1CFG[USSWE] */
+# define KINETIS_SIM_HAS_SOPT1CFG_UVSWE 1 /* SoC has SOPT1CFG[UVSWE] */
+# undef KINETIS_SIM_HAS_USBPHYCTL /* SoC has USBPHYCTL Register */
+# undef KINETIS_SIM_HAS_USBPHYCTL_USB3VOUTTRG /* SoC has USBPHYCTL[USB3VOUTTRG] */
+# undef KINETIS_SIM_HAS_USBPHYCTL_USBDISILIM /* SoC has USBPHYCTL[USBDISILIM] */
+# undef KINETIS_SIM_HAS_USBPHYCTL_USBVREGPD /* SoC has USBPHYCTL[USBVREGPD] */
+# undef KINETIS_SIM_HAS_USBPHYCTL_USBVREGSEL /* SoC has USBPHYCTL[USBVREGSEL] */
+# define KINETIS_SIM_HAS_SOPT2 1 /* SoC has SOPT2 Register */
+# define KINETIS_SIM_HAS_SOPT2_FBSL 1 /* SoC has SOPT2[FBSL] */
+# undef KINETIS_SIM_HAS_SOPT2_CMTUARTPAD /* SoC has SOPT2[CMTUARTPAD] */
+# define KINETIS_SIM_HAS_SOPT2_FLEXIOSRC 1 /* SoC has SOPT2[FLEXIOSRC] */
+# undef KINETIS_SIM_HAS_SOPT2_LPUARTSRC /* SoC has SOPT2[LPUARTSRC] */
+# define KINETIS_SIM_HAS_SOPT2_PLLFLLSEL 1 /* SoC has SOPT2[PLLFLLSEL] */
+# define KINETIS_SIM_HAS_SOPT2_PLLFLLSEL_BITS 2 /* SoC has 2 bits of SOPT2[PLLFLLSEL] */
+# define KINETIS_SIM_HAS_SOPT2_PTD7PAD 1 /* SoC has SOPT2[PTD7PAD] */
+# define KINETIS_SIM_HAS_SOPT2_RMIISRC 1 /* SoC has SOPT2[RMIISRC] */
+# define KINETIS_SIM_HAS_SOPT2_RTCCLKOUTSEL 1 /* SoC has SOPT2[RTCCLKOUTSEL] */
+# define KINETIS_SIM_HAS_SOPT2_CLKOUTSEL 1 /* SoC has SOPT2[CLKOUTSEL] */
+# define KINETIS_SIM_HAS_SOPT2_SDHCSRC 1 /* SoC has SOPT2[SDHCSRC] */
+# undef KINETIS_SIM_HAS_SOPT2_NFCSRC /* SoC has SOPT2[NFCSRC] */
+# undef KINETIS_SIM_HAS_SOPT2_I2SSRC /* SoC has SOPT2[I2SSRC] */
+# define KINETIS_SIM_HAS_SOPT2_TIMESRC 1 /* SoC has SOPT2[TIMESRC] */
+# undef KINETIS_SIM_HAS_SOPT2_TPMSRC /* SoC has SOPT2[TPMSRC] */
+# undef KINETIS_SIM_HAS_SOPT2_USBFSRC /* SoC has SOPT2[USBFSRC] */
+# define KINETIS_SIM_HAS_SOPT2_TRACECLKSEL 1 /* SoC has SOPT2[TRACECLKSEL] */
+# undef KINETIS_SIM_HAS_SOPT2_USBREGEN /* SoC has SOPT2[USBREGEN] */
+# undef KINETIS_SIM_HAS_SOPT2_USBSLSRC /* SoC has SOPT2[USBSLSRC] */
+# undef KINETIS_SIM_HAS_SOPT2_USBHSRC /* SoC has SOPT2[USBHSRC] */
+# define KINETIS_SIM_HAS_SOPT2_USBSRC 1 /* SoC has SOPT2[USBSRC] */
+# undef KINETIS_SIM_HAS_SOPT2_MCGCLKSEL /* SoC has SOPT2[MCGCLKSEL] */
+# define KINETIS_SIM_HAS_SOPT4 1 /* SoC has SOPT4 Register */
+# define KINETIS_SIM_HAS_SOPT4_FTM0FLT0 1 /* SoC has SOPT4[FTM0FLT0] */
+# define KINETIS_SIM_HAS_SOPT4_FTM0FLT1 1 /* SoC has SOPT4[FTM0FLT1] */
+# define KINETIS_SIM_HAS_SOPT4_FTM0FLT2 1 /* SoC has SOPT4[FTM0FLT2] */
+# undef KINETIS_SIM_HAS_SOPT4_FTM0FLT3 /* SoC has SOPT4[FTM0FLT3] */
+# define KINETIS_SIM_HAS_SOPT4_FTM0TRG0SRC 1 /* SoC has SOPT4[FTM0TRG0SRC] */
+# define KINETIS_SIM_HAS_SOPT4_FTM0TRG1SRC 1 /* SoC has SOPT4[FTM0TRG1SRC] */
+# define KINETIS_SIM_HAS_SOPT4_FTM1CH0SRC 3 /* SoC has SOPT4[FTM1CH0SRC] 1, 3 if SOF */
+# define KINETIS_SIM_HAS_SOPT4_FTM1FLT0 1 /* SoC has SOPT4[FTM1FLT0] */
+# define KINETIS_SIM_HAS_SOPT4_FTM1FLT1 1 /* SoC has SOPT4[FTM1FLT1] */
+# define KINETIS_SIM_HAS_SOPT4_FTM1FLT2 1 /* SoC has SOPT4[FTM1FLT2] */
+# define KINETIS_SIM_HAS_SOPT4_FTM1FLT3 1 /* SoC has SOPT4[FTM1FLT3] */
+# define KINETIS_SIM_HAS_SOPT4_FTM2CH0SRC 1 /* SoC has SOPT4[FTM2CH0SRC] */
+# undef KINETIS_SIM_HAS_SOPT4_FTM2CH1SRC /* SoC has SOPT4[FTM2CH1SRC] */
+# define KINETIS_SIM_HAS_SOPT4_FTM2FLT0 1 /* SoC has SOPT4[FTM2FLT0] */
+# define KINETIS_SIM_HAS_SOPT4_FTM2FLT1 1 /* SoC has SOPT4[FTM2FLT1] */
+# define KINETIS_SIM_HAS_SOPT4_FTM2FLT2 1 /* SoC has SOPT4[FTM2FLT2] */
+# define KINETIS_SIM_HAS_SOPT4_FTM2FLT3 1 /* SoC has SOPT4[FTM2FLT3] */
+# define KINETIS_SIM_HAS_SOPT4_FTM3CH0SRC 1 /* SoC has SOPT4[FTM3CH0SRC] */
+# define KINETIS_SIM_HAS_SOPT4_FTM3FLT0 1 /* SoC has SOPT4[FTM3FLT0] */
+# define KINETIS_SIM_HAS_SOPT4_FTM3FLT1 1 /* SoC has SOPT4[FTM3FLT1] */
+# define KINETIS_SIM_HAS_SOPT4_FTM3FLT2 1 /* SoC has SOPT4[FTM3FLT2] */
+# define KINETIS_SIM_HAS_SOPT4_FTM3FLT3 1 /* SoC has SOPT4[FTM3FLT3] */
+# define KINETIS_SIM_HAS_SOPT4_FTM3TRG0SRC 1 /* SoC has SOPT4[FTM3TRG0SRC] */
+# define KINETIS_SIM_HAS_SOPT4_FTM3TRG1SRC 1 /* SoC has SOPT4[FTM3TRG1SRC] */
+# define KINETIS_SIM_HAS_SOPT4_TPM0CLKSEL 1 /* SoC has SOPT4[TPM0CLKSEL] */
+# define KINETIS_SIM_HAS_SOPT4_TPM1CH0SRC 1 /* SoC has SOPT4[TPM1CH0SRC] */
+# define KINETIS_SIM_HAS_SOPT4_TPM1CLKSEL 1 /* SoC has SOPT4[TPM1CLKSEL] */
+# define KINETIS_SIM_HAS_SOPT4_TPM2CH0SRC 1 /* SoC has SOPT4[TPM2CH0SRC] */
+# define KINETIS_SIM_HAS_SOPT4_TPM2CLKSEL 1 /* SoC has SOPT4[TPM2CLKSEL] */
+# define KINETIS_SIM_HAS_SOPT5 1 /* SoC has SOPT5 Register */
+# undef KINETIS_SIM_HAS_SOPT5_LPUART0RXSRC /* SoC has SOPT5[LPUART0RXSRC] */
+# undef KINETIS_SIM_HAS_SOPT5_LPUART0TXSRC /* SoC has SOPT5[LPUART0TXSRC] */
+# undef KINETIS_SIM_HAS_SOPT6 /* SoC has SOPT6 Register */
+# undef KINETIS_SIM_HAS_SOPT6_MCC /* SoC has SOPT6[MCC] */
+# undef KINETIS_SIM_HAS_SOPT6_PCR /* SoC has SOPT6[PCR] */
+# undef KINETIS_SIM_HAS_SOPT6_RSTFLTSEL /* SoC has SOPT6[RSTFLTSEL] */
+# undef KINETIS_SIM_HAS_SOPT6_RSTFLTEN /* SoC has SOPT6[RSTFLTEN] */
+# define KINETIS_SIM_HAS_SOPT7 1 /* SoC has SOPT7 Register */
+# define KINETIS_SIM_HAS_SOPT7_ADC0ALTTRGSEL 1 /* SoC has SOPT7[ADC0ALTTRGSEL] */
+# define KINETIS_SIM_HAS_SOPT7_ADC1ALTTRGSEL 1 /* SoC has SOPT7[ADC1ALTTRGSEL] */
+# define KINETIS_SIM_HAS_SOPT7_ADC0PRETRGSEL 1 /* SoC has SOPT7[ADC0PRETRGSEL] */
+# define KINETIS_SIM_HAS_SOPT7_ADC1PRETRGSEL 1 /* SoC has SOPT7[ADC1PRETRGSEL] */
+# undef KINETIS_SIM_HAS_SOPT7_ADC2PRETRGSEL /* SoC has SOPT7[ADC2PRETRGSEL] */
+# undef KINETIS_SIM_HAS_SOPT7_ADC3PRETRGSEL /* SoC has SOPT7[ADC3PRETRGSEL] */
+# define KINETIS_SIM_HAS_SOPT7_ADC0TRGSEL 14 /* SoC has 10 SOPT7[ADC0TRGSEL] */
+# define KINETIS_SIM_HAS_SOPT7_ADC1TRGSEL 14 /* SoC has 10 SOPT7[ADC1TRGSEL] */
+# undef KINETIS_SIM_HAS_SOPT7_ADC2TRGSEL /* SoC has 10 SOPT7[ADC2TRGSEL] */
+# undef KINETIS_SIM_HAS_SOPT7_ADC3TRGSEL /* SoC has 10 SOPT7[ADC3TRGSEL] */
+# define KINETIS_SIM_SOPT7_ADC0ALTTRGEN 1 /* ADC0 alternate trigger enable */
+# define KINETIS_SIM_SOPT7_ADC1ALTTRGEN 1 /* ADC1 alternate trigger enable */
+# undef KINETIS_SIM_SOPT7_ADC2ALTTRGEN /* ADC2 alternate trigger enable */
+# undef KINETIS_SIM_SOPT7_ADC3ALTTRGEN /* ADC3 alternate trigger enable */
+# undef KINETIS_SIM_HAS_SOPT8 /* SoC has SOPT8 Register */
+# undef KINETIS_SIM_HAS_SOPT8_FTM0SYNCBIT /* SoC has SOPT8[FTM0SYNCBIT] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM1SYNCBIT /* SoC has SOPT8[FTM1SYNCBIT] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM2SYNCBIT /* SoC has SOPT8[FTM2SYNCBIT] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM3SYNCBIT /* SoC has SOPT8[FTM3SYNCBIT] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH0SRC /* SoC has SOPT8[FTM0OCH0SRC] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH1SRC /* SoC has SOPT8[FTM0OCH1SRC] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH2SRC /* SoC has SOPT8[FTM0OCH2SRC] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH3SRC /* SoC has SOPT8[FTM0OCH3SRC] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH4SRC /* SoC has SOPT8[FTM0OCH4SRC] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH5SRC /* SoC has SOPT8[FTM0OCH5SRC] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH6SRC /* SoC has SOPT8[FTM0OCH6SRC] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM0OCH7SRC /* SoC has SOPT8[FTM0OCH7SRC] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH0SRC /* SoC has SOPT8[FTM3OCH0SRC] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH1SRC /* SoC has SOPT8[FTM3OCH1SRC] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH2SRC /* SoC has SOPT8[FTM3OCH2SRC] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH3SRC /* SoC has SOPT8[FTM3OCH3SRC] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH4SRC /* SoC has SOPT8[FTM3OCH4SRC] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH5SRC /* SoC has SOPT8[FTM3OCH5SRC] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH6SRC /* SoC has SOPT8[FTM3OCH6SRC] */
+# undef KINETIS_SIM_HAS_SOPT8_FTM3OCH7SRC /* SoC has SOPT8[FTM3OCH7SRC] */
+# undef KINETIS_SIM_HAS_SOPT9 /* SoC has SOPT9 Register */
+# undef KINETIS_SIM_HAS_SOPT9_TPM1CH0SRC /* SoC has SOPT9[TPM1CH0SRC] */
+# undef KINETIS_SIM_HAS_SOPT9_TPM2CH0SRC /* SoC has SOPT9[TPM2CH0SRC] */
+# undef KINETIS_SIM_HAS_SOPT9_TPM1CLKSEL /* SoC has SOPT9[TPM1CLKSEL] */
+# undef KINETIS_SIM_HAS_SOPT9_TPM2CLKSEL /* SoC has SOPT9[TPM2CLKSEL] */
+# define KINETIS_SIM_HAS_SDID 1 /* SoC has SDID Register */
+# define KINETIS_SIM_HAS_SDID_DIEID 1 /* SoC has SDID[DIEID] */
+# define KINETIS_SIM_HAS_SDID_FAMID 1 /* SoC has SDID[FAMID] */
+# define KINETIS_SIM_HAS_SDID_FAMILYID 1 /* SoC has SDID[FAMILYID] */
+# define KINETIS_SIM_HAS_SDID_SERIESID 1 /* SoC has SDID[SERIESID] */
+# undef KINETIS_SIM_HAS_SDID_SRAMSIZE /* SoC has SDID[SRAMSIZE] */
+# define KINETIS_SIM_HAS_SDID_SUBFAMID 1 /* SoC has SDID[SUBFAMID] */
+# define KINETIS_SIM_HAS_SCGC1 1 /* SoC has _SCGC1 Register */
+# define KINETIS_SIM_HAS_SCGC1_UART5 1 /* SoC has SCGC1[UART5] */
+# define KINETIS_SIM_HAS_SCGC1_UART4 1 /* SoC has SCGC1[UART4] */
+# undef KINETIS_SIM_HAS_SCGC1_I2C3 /* SoC has SCGC1[I2C3] */
+# define KINETIS_SIM_HAS_SCGC1_I2C2 1 /* SoC has SCGC1[I2C2] */
+# undef KINETIS_SIM_HAS_SCGC1_OSC1 /* SoC has SCGC1[OSC1] */
+# define KINETIS_SIM_HAS_SCGC2 1 /* SoC has _SCGC2 Register */
+# define KINETIS_SIM_HAS_SCGC2 1 /* SoC has SCGC2 Register */
+# define KINETIS_SIM_HAS_SCGC2_ENET 1 /* SoC has SCGC2[ENET] */
+# undef KINETIS_SIM_HAS_SCGC2_LPUART0 /* SoC has SCGC2[LPUART0] */
+# undef KINETIS_SIM_HAS_SCGC2_TPM1 /* SoC has SCGC2[TPM1] */
+# undef KINETIS_SIM_HAS_SCGC2_TPM2 /* SoC has SCGC2[TPM2] */
+# define KINETIS_SIM_HAS_SCGC3 1 /* SoC has SCGC3 Register */
+# define KINETIS_SIM_HAS_SCGC3_RNGA 1 /* SoC has SCGC3[RNGA] */
+# undef KINETIS_SIM_HAS_SCGC3_USBHS /* SoC has SCGC3[USBHS] */
+# undef KINETIS_SIM_HAS_SCGC3_USBHSPHY /* SoC has SCGC3[USBHSPHY] */
+# undef KINETIS_SIM_HAS_SCGC3_USBHSDCD /* SoC has SCGC3[USBHSDCD] */
+# undef KINETIS_SIM_HAS_SCGC3_FLEXCAN1 /* SoC has SCGC3[FLEXCAN1] */
+# undef KINETIS_SIM_HAS_SCGC3_NFC /* SoC has SCGC3[NFC] */
+# define KINETIS_SIM_HAS_SCGC3_SPI2 1 /* SoC has SCGC3[SPI2] */
+# undef KINETIS_SIM_HAS_SCGC3_SAI1 /* SoC has SCGC3[SAI1] */
+# define KINETIS_SIM_HAS_SCGC3_SDHC 1 /* SoC has SCGC3[SDHC] */
+# define KINETIS_SIM_HAS_SCGC3_FTM2 1 /* SoC has SCGC3[FTM2] */
+# define KINETIS_SIM_HAS_SCGC3_FTM3 1 /* SoC has SCGC3[FTM3] */
+# define KINETIS_SIM_HAS_SCGC3_ADC1 1 /* SoC has SCGC3[ADC1] */
+# undef KINETIS_SIM_HAS_SCGC3_ADC3 /* SoC has SCGC3[ADC3] */
+# undef KINETIS_SIM_HAS_SCGC3_SLCD /* SoC has SCGC3[SLCD] */
+# define KINETIS_SIM_HAS_SCGC4 1 /* SoC has SCGC4 Register */
+# undef KINETIS_SIM_HAS_SCGC4_LLWU /* SoC has SCGC4[LLWU] clock gate */
+# define KINETIS_SIM_HAS_SCGC4_UART0 1 /* SoC has SCGC4[UART0] */
+# define KINETIS_SIM_HAS_SCGC4_UART1 1 /* SoC has SCGC4[UART1] */
+# define KINETIS_SIM_HAS_SCGC4_UART2 1 /* SoC has SCGC4[UART2] */
+# define KINETIS_SIM_HAS_SCGC4_UART3 1 /* SoC has SCGC4[UART3] */
+# define KINETIS_SIM_HAS_SCGC5 1 /* SoC has _SCGC5 Register */
+# undef KINETIS_SIM_HAS_SCGC5_REGFILE /* SoC has SCGC5[REGFILE] */
+# undef KINETIS_SIM_HAS_SCGC5_TSI /* SoC has SCGC5[TSI] */
+# undef KINETIS_SIM_HAS_SCGC5_PORTF /* SoC has SCGC5[PORTF] */
+# define KINETIS_SIM_HAS_SCGC6 1 /* SoC has SCGC6 Register */
+# define KINETIS_SIM_HAS_SCGC6_FTFL 1 /* SoC has SCGC6[FTFL] */
+# undef KINETIS_SIM_HAS_SCGC6_DMAMUX1 /* SoC has SCGC6[DEMUX1] */
+# undef KINETIS_SIM_HAS_SCGC6_USBHS /* SoC has SCGC6[USBHS] */
+# define KINETIS_SIM_HAS_SCGC6_RNGA 1 /* SoC has SCGC6[RNGA] */
+# define KINETIS_SIM_HAS_SCGC6_FTM2 1 /* SoC has SCGC6[FTM2] */
+# undef KINETIS_SIM_HAS_SCGC6_ADC2 /* SoC has SCGC6[ADC2] */
+# define KINETIS_SIM_HAS_SCGC6_DAC0 1 /* SoC has SCGC6[DAC0] */
+# define KINETIS_SIM_HAS_SCGC7 1 /* SoC has SCGC7 Register */
+# define KINETIS_SIM_HAS_SCGC7_FLEXBUS 1 /* SoC has SCGC7[FLEXBUS] */
+# define KINETIS_SIM_HAS_SCGC7_DMA 1 /* SoC has SCGC7[DMS] */
+# define KINETIS_SIM_HAS_SCGC7_MPU 1 /* SoC has SCGC7[MPU] */
+# undef KINETIS_SIM_HAS_SCGC7_SDRAMC /* SoC has SCGC7[SDRAMC] */
+# define KINETIS_SIM_HAS_CLKDIV1 1 /* SoC has CLKDIV1 Register */
+# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV2 1 /* SoC has CLKDIV1[OUTDIV2] */
+# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV3 1 /* SoC has CLKDIV1[OUTDIV3] */
+# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV4 1 /* SoC has CLKDIV1[OUTDIV4] */
+# undef KINETIS_SIM_HAS_CLKDIV1_OUTDIV5 /* SoC has CLKDIV1[OUTDIV5] */
+# define KINETIS_SIM_HAS_CLKDIV2 1 /* SoC has CLKDIV2 Register */
+# define KINETIS_SIM_HAS_CLKDIV2_USBDIV 1 /* SoC has CLKDIV2[USBDIV] */
+# define KINETIS_SIM_HAS_CLKDIV2_USBFRAC 1 /* SoC has CLKDIV2[USBFRAC] */
+# undef KINETIS_SIM_HAS_CLKDIV2_USBFSDIV /* SoC has CLKDIV2[USBFSDIV] */
+# undef KINETIS_SIM_HAS_CLKDIV2_USBFSFRAC /* SoC has CLKDIV2[USBFSFRAC] */
+# undef KINETIS_SIM_HAS_CLKDIV2_USBHSDIV /* SoC has CLKDIV2[USBHSDIV] */
+# undef KINETIS_SIM_HAS_CLKDIV2_USBHSFRAC /* SoC has CLKDIV2[USBHSFRAC] */
+# undef KINETIS_SIM_HAS_CLKDIV2_I2SDIV /* SoC has CLKDIV2[I2SDIV] */
+# undef KINETIS_SIM_HAS_CLKDIV2_I2SFRAC /* SoC has CLKDIV2[I2SFRAC] */
+# define KINETIS_SIM_HAS_FCFG1 1 /* SoC has FCFG1 Register */
+# define KINETIS_SIM_HAS_FCFG1_DEPART 1 /* SoC has FCFG1[DEPART] */
+# define KINETIS_SIM_HAS_FCFG1_EESIZE 1 /* SoC has FCFG1[EESIZE] */
+# define KINETIS_SIM_HAS_FCFG1_FLASHDIS 1 /* SoC has FCFG1[FLASHDIS] */
+# define KINETIS_SIM_HAS_FCFG1_FLASHDOZE 1 /* SoC has FCFG1[FLASHDOZE] */
+# undef KINETIS_SIM_HAS_FCFG1_FTFDIS /* SoC has FCFG1[FTFDIS] */
+# define KINETIS_SIM_HAS_FCFG1_NVMSIZE 1 /* SoC has FCFG1[NVMSIZE] */
+# define KINETIS_SIM_HAS_FCFG2 1 /* SoC has FCFG2 Register */
+# define KINETIS_SIM_HAS_FCFG2_MAXADDR0 7 /* SoC has n bit of FCFG2[MAXADDR0] */
+# define KINETIS_SIM_HAS_FCFG2_MAXADDR1 7 /* SoC has n bit of FCFG2[MAXADDR1] */
+# define KINETIS_SIM_HAS_FCFG2_PFLSH 1 /* SoC has FCFG2[PFLSH] */
+# undef KINETIS_SIM_HAS_FCFG2_SWAPPFLSH /* SoC has FCFG2[SWAPPFLSH] */
+# define KINETIS_SIM_HAS_UIDH 1 /* SoC has UIDH Register */
+# define KINETIS_SIM_HAS_UIDMH 1 /* SoC has UIDMH Register */
+# define KINETIS_SIM_HAS_UIDML 1 /* SoC has UIDML Register */
+# define KINETIS_SIM_HAS_UIDL 1 /* SoC has UIDL Register */
+# undef KINETIS_SIM_HAS_CLKDIV3 /* SoC has CLKDIV3 Register */
+# undef KINETIS_SIM_HAS_CLKDIV3_PLLFLLDIV /* SoC has CLKDIV3[PLLFLLDIV] */
+# undef KINETIS_SIM_HAS_CLKDIV3_PLLFLLFRAC /* SoC has CLKDIV3[PLLFLLFRAC] */
+# undef KINETIS_SIM_HAS_CLKDIV4 /* SoC has CLKDIV4 Register */
+# undef KINETIS_SIM_HAS_CLKDIV4_TRACEDIV /* SoC has CLKDIV4[TRACEDIV] */
+# undef KINETIS_SIM_HAS_CLKDIV4_TRACEFRAC /* SoC has CLKDIV4[TRACEFRAC] */
+# undef KINETIS_SIM_HAS_CLKDIV4_NFCDIV /* SoC has CLKDIV4[NFCDIV] */
+# undef KINETIS_SIM_HAS_CLKDIV4_NFCFRAC /* SoC has CLKDIV4[NFCFRAC] */
+# undef KINETIS_SIM_HAS_MCR /* SoC has MCR Register */
+
+/* MK66F N/X 1M0/2M0 V MD/LQ 18
+ *
+ * --------------- ------- --- ------- ------- ------ ------ ------ -----
+ * PART NUMBER CPU PIN PACKAGE TOTAL PROGRAM EEPROM SRAM GPIO
+ * FREQ CNT FLASH FLASH
+ * --------------- ------- --- ------- ------- ------ ------ ------ -----
+ * MK66FN2M0VMD18 180 MHz 144 MAPBGA 2 MB — — KB 260 KB 100
+ * MK66FX1M0VMD18 180 MHz 144 MAPBGA 1.25 MB 1 MB 4 KB 256 KB 100
+ * MK66FN2M0VLQ18 180 MHz 144 LQFP 2 MB — — KB 260 KB 100
+ * MK66FX1M0VLQ18 180 MHz 144 LQFP 1.25 MB 1 MB 4 KB 256 KB 100
+ */
+
+#elif defined(CONFIG_ARCH_CHIP_MK66FN2M0VMD18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VMD18) || \
+ defined(CONFIG_ARCH_CHIP_MK66FN2M0VLQ18) || defined(CONFIG_ARCH_CHIP_MK66FX1M0VLQ18)
+
+/* Verified to Document Number: Document Number: K66P144M180SF5RMV2 Rev. 2, May 2015 */
+
+# define KINETIS_SIM_VERSION KINETIS_SIM_VERSION_06
+
+/* SIM Register Configuration */
+
+# define KINETIS_SIM_HAS_SOPT1 1 /* SoC has SOPT1 Register */
+# undef KINETIS_SIM_HAS_SOPT1_OSC32KOUT /* SoC has SOPT1[OSC32KOUT] */
+# define KINETIS_SIM_HAS_SOPT1_OSC32KSEL 1 /* SoC has SOPT1[OSC32KSEL] */
+# define KINETIS_SIM_HAS_SOPT1_OSC32KSEL_BITS 2 /* SoC has 1 bit SOPT1[OSC32KSEL] */
+# define KINETIS_SIM_HAS_SOPT1_RAMSIZE 1 /* SoC has SOPT1[RAMSIZE] */
+# define KINETIS_SIM_HAS_SOPT1_USBREGEN 1 /* SoC has SOPT1[USBREGEN] */
+# define KINETIS_SIM_HAS_SOPT1_USBSSTBY 1 /* SoC has SOPT1[USBSSTBY] */
+# define KINETIS_SIM_HAS_SOPT1_USBVSTBY 1 /* SoC has SOPT1[USBVSTBY] */
+# define KINETIS_SIM_HAS_SOPT1CFG /* SoC has SOPT1CFG Register */
+# define KINETIS_SIM_HAS_SOPT1CFG_URWE 1 /* SoC has SOPT1CFG[URWE] */
+# define KINETIS_SIM_HAS_SOPT1CFG_USSWE 1 /* SoC has SOPT1CFG[USSWE] */
+# define KINETIS_SIM_HAS_SOPT1CFG_UVSWE 1 /* SoC has SOPT1CFG[UVSWE] */
+# define KINETIS_SIM_HAS_USBPHYCTL 1 /* SoC has USBPHYCTL Register */
+# define KINETIS_SIM_HAS_USBPHYCTL_USB3VOUTTRG 1 /* SoC has USBPHYCTL[USB3VOUTTRG] */
+# define KINETIS_SIM_HAS_USBPHYCTL_USBDISILIM 1 /* SoC has USBPHYCTL[USBDISILIM] */
+# define KINETIS_SIM_HAS_USBPHYCTL_USBVREGPD 1 /* SoC has USBPHYCTL[USBVREGPD] */
+# define KINETIS_SIM_HAS_USBPHYCTL_USBVREGSEL 1 /* SoC has USBPHYCTL[USBVREGSEL] */
+# define KINETIS_SIM_HAS_SOPT2 1 /* SoC has SOPT2 Register */
+# define KINETIS_SIM_HAS_SOPT2_FBSL 1 /* SoC has SOPT2[FBSL] */
+# undef KINETIS_SIM_HAS_SOPT2_CMTUARTPAD /* SoC has SOPT2[CMTUARTPAD] */
+# define KINETIS_SIM_HAS_SOPT2_FLEXIOSRC 1 /* SoC has SOPT2[FLEXIOSRC] */
+# define KINETIS_SIM_HAS_SOPT2_LPUARTSRC 1 /* SoC has SOPT2[LPUARTSRC] */
+# define KINETIS_SIM_HAS_SOPT2_PLLFLLSEL 1 /* SoC has SOPT2[PLLFLLSEL] */
+# define KINETIS_SIM_HAS_SOPT2_PLLFLLSEL_BITS 2 /* SoC has 2 bits of SOPT2[PLLFLLSEL] */
+# undef KINETIS_SIM_HAS_SOPT2_PTD7PAD /* SoC has SOPT2[PTD7PAD] */
+# define KINETIS_SIM_HAS_SOPT2_RMIISRC 1 /* SoC has SOPT2[RMIISRC] */
+# define KINETIS_SIM_HAS_SOPT2_RTCCLKOUTSEL 1 /* SoC has SOPT2[RTCCLKOUTSEL] */
+# define KINETIS_SIM_HAS_SOPT2_CLKOUTSEL 1 /* SoC has SOPT2[CLKOUTSEL] */
+# define KINETIS_SIM_HAS_SOPT2_SDHCSRC 1 /* SoC has SOPT2[SDHCSRC] */
+# undef KINETIS_SIM_HAS_SOPT2_NFCSRC /* SoC has SOPT2[NFCSRC] */
+# undef KINETIS_SIM_HAS_SOPT2_I2SSRC /* SoC has SOPT2[I2SSRC] */
+# define KINETIS_SIM_HAS_SOPT2_TIMESRC 1 /* SoC has SOPT2[TIMESRC] */
+# define KINETIS_SIM_HAS_SOPT2_TPMSRC 1 /* SoC has SOPT2[TPMSRC] */
+# undef KINETIS_SIM_HAS_SOPT2_USBFSRC /* SoC has SOPT2[USBFSRC] */
+# define KINETIS_SIM_HAS_SOPT2_TRACECLKSEL 1 /* SoC has SOPT2[TRACECLKSEL] */
+# define KINETIS_SIM_HAS_SOPT2_USBREGEN 1 /* SoC has SOPT2[USBREGEN] */
+# define KINETIS_SIM_HAS_SOPT2_USBSLSRC 1 /* SoC has SOPT2[USBSLSRC] */
+# undef KINETIS_SIM_HAS_SOPT2_USBHSRC /* SoC has SOPT2[USBHSRC] */
+# define KINETIS_SIM_HAS_SOPT2_USBSRC 1 /* SoC has SOPT2[USBSRC] */
+# undef KINETIS_SIM_HAS_SOPT2_MCGCLKSEL /* SoC has SOPT2[MCGCLKSEL] */
+# define KINETIS_SIM_HAS_SOPT4 1 /* SoC has SOPT4 Register */
+# define KINETIS_SIM_HAS_SOPT4_FTM0FLT0 1 /* SoC has SOPT4[FTM0FLT0] */
+# define KINETIS_SIM_HAS_SOPT4_FTM0FLT1 1 /* SoC has SOPT4[FTM0FLT1] */
+# define KINETIS_SIM_HAS_SOPT4_FTM0FLT2 1 /* SoC has SOPT4[FTM0FLT2] */
+# define KINETIS_SIM_HAS_SOPT4_FTM0FLT3 1 /* SoC has SOPT4[FTM0FLT3] */
+# define KINETIS_SIM_HAS_SOPT4_FTM0TRG0SRC 1 /* SoC has SOPT4[FTM0TRG0SRC] */
+# define KINETIS_SIM_HAS_SOPT4_FTM0TRG1SRC 1 /* SoC has SOPT4[FTM0TRG1SRC] */
+# define KINETIS_SIM_HAS_SOPT4_FTM1CH0SRC 3 /* SoC has SOPT4[FTM1CH0SRC] 1, 3 if SOF */
+# define KINETIS_SIM_HAS_SOPT4_FTM1FLT0 1 /* SoC has SOPT4[FTM1FLT0] */
+# define KINETIS_SIM_HAS_SOPT4_FTM1FLT1 1 /* SoC has SOPT4[FTM1FLT1] */
+# define KINETIS_SIM_HAS_SOPT4_FTM1FLT2 1 /* SoC has SOPT4[FTM1FLT2] */
+# define KINETIS_SIM_HAS_SOPT4_FTM1FLT3 1 /* SoC has SOPT4[FTM1FLT3] */
+# define KINETIS_SIM_HAS_SOPT4_FTM2CH0SRC 1 /* SoC has SOPT4[FTM2CH0SRC] */
+# define KINETIS_SIM_HAS_SOPT4_FTM2CH1SRC 1 /* SoC has SOPT4[FTM2CH1SRC] */
+# define KINETIS_SIM_HAS_SOPT4_FTM2FLT0 1 /* SoC has SOPT4[FTM2FLT0] */
+# define KINETIS_SIM_HAS_SOPT4_FTM2FLT1 1 /* SoC has SOPT4[FTM2FLT1] */
+# define KINETIS_SIM_HAS_SOPT4_FTM2FLT2 1 /* SoC has SOPT4[FTM2FLT2] */
+# define KINETIS_SIM_HAS_SOPT4_FTM2FLT3 1 /* SoC has SOPT4[FTM2FLT3] */
+# define KINETIS_SIM_HAS_SOPT4_FTM3CH0SRC 1 /* SoC has SOPT4[FTM3CH0SRC] */
+# define KINETIS_SIM_HAS_SOPT4_FTM3FLT0 1 /* SoC has SOPT4[FTM3FLT0] */
+# define KINETIS_SIM_HAS_SOPT4_FTM3FLT1 1 /* SoC has SOPT4[FTM3FLT1] */
+# define KINETIS_SIM_HAS_SOPT4_FTM3FLT2 1 /* SoC has SOPT4[FTM3FLT2] */
+# define KINETIS_SIM_HAS_SOPT4_FTM3FLT3 1 /* SoC has SOPT4[FTM3FLT3] */
+# define KINETIS_SIM_HAS_SOPT4_FTM3TRG0SRC 1 /* SoC has SOPT4[FTM3TRG0SRC] */
+# define KINETIS_SIM_HAS_SOPT4_FTM3TRG1SRC 1 /* SoC has SOPT4[FTM3TRG1SRC] */
+# define KINETIS_SIM_HAS_SOPT4_TPM0CLKSEL 1 /* SoC has SOPT4[TPM0CLKSEL] */
+# define KINETIS_SIM_HAS_SOPT4_TPM1CH0SRC 1 /* SoC has SOPT4[TPM1CH0SRC] */
+# define KINETIS_SIM_HAS_SOPT4_TPM1CLKSEL 1 /* SoC has SOPT4[TPM1CLKSEL] */
+# define KINETIS_SIM_HAS_SOPT4_TPM2CH0SRC 1 /* SoC has SOPT4[TPM2CH0SRC] */
+# define KINETIS_SIM_HAS_SOPT4_TPM2CLKSEL 1 /* SoC has SOPT4[TPM2CLKSEL] */
+# define KINETIS_SIM_HAS_SOPT5 1 /* SoC has SOPT5 Register */
+# define KINETIS_SIM_HAS_SOPT5_LPUART0RXSRC 1 /* SoC has SOPT5[LPUART0RXSRC] */
+# define KINETIS_SIM_HAS_SOPT5_LPUART0TXSRC 1 /* SoC has SOPT5[LPUART0TXSRC] */
+# undef KINETIS_SIM_HAS_SOPT6 /* SoC has SOPT6 Register */
+# undef KINETIS_SIM_HAS_SOPT6_MCC /* SoC has SOPT6[MCC] */
+# undef KINETIS_SIM_HAS_SOPT6_PCR /* SoC has SOPT6[PCR] */
+# undef KINETIS_SIM_HAS_SOPT6_RSTFLTSEL /* SoC has SOPT6[RSTFLTSEL] */
+# undef KINETIS_SIM_HAS_SOPT6_RSTFLTEN /* SoC has SOPT6[RSTFLTEN] */
+# define KINETIS_SIM_HAS_SOPT7 1 /* SoC has SOPT7 Register */
+# define KINETIS_SIM_HAS_SOPT7_ADC0ALTTRGSEL 1 /* SoC has SOPT7[ADC0ALTTRGSEL] */
+# define KINETIS_SIM_HAS_SOPT7_ADC1ALTTRGSEL 1 /* SoC has SOPT7[ADC1ALTTRGSEL] */
+# define KINETIS_SIM_HAS_SOPT7_ADC0PRETRGSEL 1 /* SoC has SOPT7[ADC0PRETRGSEL] */
+# define KINETIS_SIM_HAS_SOPT7_ADC1PRETRGSEL 1 /* SoC has SOPT7[ADC1PRETRGSEL] */
+# undef KINETIS_SIM_HAS_SOPT7_ADC2PRETRGSEL /* SoC has SOPT7[ADC2PRETRGSEL] */
+# undef KINETIS_SIM_HAS_SOPT7_ADC3PRETRGSEL /* SoC has SOPT7[ADC3PRETRGSEL] */
+# define KINETIS_SIM_HAS_SOPT7_ADC0TRGSEL 15 /* SoC has 10 SOPT7[ADC0TRGSEL] */
+# define KINETIS_SIM_HAS_SOPT7_ADC1TRGSEL 15 /* SoC has 10 SOPT7[ADC1TRGSEL] */
+# undef KINETIS_SIM_HAS_SOPT7_ADC2TRGSEL /* SoC has 10 SOPT7[ADC2TRGSEL] */
+# undef KINETIS_SIM_HAS_SOPT7_ADC3TRGSEL /* SoC has 10 SOPT7[ADC3TRGSEL] */
+# define KINETIS_SIM_SOPT7_ADC0ALTTRGEN 1 /* ADC0 alternate trigger enable */
+# define KINETIS_SIM_SOPT7_ADC1ALTTRGEN 1 /* ADC1 alternate trigger enable */
+# undef KINETIS_SIM_SOPT7_ADC2ALTTRGEN /* ADC2 alternate trigger enable */
+# undef KINETIS_SIM_SOPT7_ADC3ALTTRGEN /* ADC3 alternate trigger enable */
+# define KINETIS_SIM_HAS_SOPT8 1 /* SoC has SOPT8 Register */
+# define KINETIS_SIM_HAS_SOPT8_FTM0SYNCBIT 1 /* SoC has SOPT8[FTM0SYNCBIT] */
+# define KINETIS_SIM_HAS_SOPT8_FTM1SYNCBIT 1 /* SoC has SOPT8[FTM1SYNCBIT] */
+# define KINETIS_SIM_HAS_SOPT8_FTM2SYNCBIT 1 /* SoC has SOPT8[FTM2SYNCBIT] */
+# define KINETIS_SIM_HAS_SOPT8_FTM3SYNCBIT 1 /* SoC has SOPT8[FTM3SYNCBIT] */
+# define KINETIS_SIM_HAS_SOPT8_FTM0OCH0SRC 1 /* SoC has SOPT8[FTM0OCH0SRC] */
+# define KINETIS_SIM_HAS_SOPT8_FTM0OCH1SRC 1 /* SoC has SOPT8[FTM0OCH1SRC] */
+# define KINETIS_SIM_HAS_SOPT8_FTM0OCH2SRC 1 /* SoC has SOPT8[FTM0OCH2SRC] */
+# define KINETIS_SIM_HAS_SOPT8_FTM0OCH3SRC 1 /* SoC has SOPT8[FTM0OCH3SRC] */
+# define KINETIS_SIM_HAS_SOPT8_FTM0OCH4SRC 1 /* SoC has SOPT8[FTM0OCH4SRC] */
+# define KINETIS_SIM_HAS_SOPT8_FTM0OCH5SRC 1 /* SoC has SOPT8[FTM0OCH5SRC] */
+# define KINETIS_SIM_HAS_SOPT8_FTM0OCH6SRC 1 /* SoC has SOPT8[FTM0OCH6SRC] */
+# define KINETIS_SIM_HAS_SOPT8_FTM0OCH7SRC 1 /* SoC has SOPT8[FTM0OCH7SRC] */
+# define KINETIS_SIM_HAS_SOPT8_FTM3OCH0SRC 1 /* SoC has SOPT8[FTM3OCH0SRC] */
+# define KINETIS_SIM_HAS_SOPT8_FTM3OCH1SRC 1 /* SoC has SOPT8[FTM3OCH1SRC] */
+# define KINETIS_SIM_HAS_SOPT8_FTM3OCH2SRC 1 /* SoC has SOPT8[FTM3OCH2SRC] */
+# define KINETIS_SIM_HAS_SOPT8_FTM3OCH3SRC 1 /* SoC has SOPT8[FTM3OCH3SRC] */
+# define KINETIS_SIM_HAS_SOPT8_FTM3OCH4SRC 1 /* SoC has SOPT8[FTM3OCH4SRC] */
+# define KINETIS_SIM_HAS_SOPT8_FTM3OCH5SRC 1 /* SoC has SOPT8[FTM3OCH5SRC] */
+# define KINETIS_SIM_HAS_SOPT8_FTM3OCH6SRC 1 /* SoC has SOPT8[FTM3OCH6SRC] */
+# define KINETIS_SIM_HAS_SOPT8_FTM3OCH7SRC 1 /* SoC has SOPT8[FTM3OCH7SRC] */
+# define KINETIS_SIM_HAS_SOPT9 1 /* SoC has SOPT9 Register */
+# define KINETIS_SIM_HAS_SOPT9_TPM1CH0SRC 1 /* SoC has SOPT9[TPM1CH0SRC] */
+# define KINETIS_SIM_HAS_SOPT9_TPM2CH0SRC 1 /* SoC has SOPT9[TPM2CH0SRC] */
+# define KINETIS_SIM_HAS_SOPT9_TPM1CLKSEL 1 /* SoC has SOPT9[TPM1CLKSEL] */
+# define KINETIS_SIM_HAS_SOPT9_TPM2CLKSEL 1 /* SoC has SOPT9[TPM2CLKSEL] */
+# define KINETIS_SIM_HAS_SDID 1 /* SoC has SDID Register */
+# define KINETIS_SIM_HAS_SDID_DIEID 1 /* SoC has SDID[DIEID] */
+# define KINETIS_SIM_HAS_SDID_FAMID 1 /* SoC has SDID[FAMID] */
+# define KINETIS_SIM_HAS_SDID_FAMILYID 1 /* SoC has SDID[FAMILYID] */
+# define KINETIS_SIM_HAS_SDID_SERIESID 1 /* SoC has SDID[SERIESID] */
+# undef KINETIS_SIM_HAS_SDID_SRAMSIZE /* SoC has SDID[SRAMSIZE] */
+# define KINETIS_SIM_HAS_SDID_SUBFAMID 1 /* SoC has SDID[SUBFAMID] */
+# define KINETIS_SIM_HAS_SCGC1 1 /* SoC has _SCGC1 Register */
+# undef KINETIS_SIM_HAS_SCGC1_UART5 /* SoC has SCGC1[UART5] */
+# define KINETIS_SIM_HAS_SCGC1_UART4 1 /* SoC has SCGC1[UART4] */
+# define KINETIS_SIM_HAS_SCGC1_I2C3 1 /* SoC has SCGC1[I2C3] */
+# define KINETIS_SIM_HAS_SCGC1_I2C2 1 /* SoC has SCGC1[I2C2] */
+# undef KINETIS_SIM_HAS_SCGC1_OSC1 /* SoC has SCGC1[OSC1] */
+# define KINETIS_SIM_HAS_SCGC2 1 /* SoC has _SCGC2 Register */
+# define KINETIS_SIM_HAS_SCGC2 1 /* SoC has SCGC2 Register */
+# define KINETIS_SIM_HAS_SCGC2_ENET 1 /* SoC has SCGC2[ENET] */
+# define KINETIS_SIM_HAS_SCGC2_LPUART0 1 /* SoC has SCGC2[LPUART0] */
+# define KINETIS_SIM_HAS_SCGC2_TPM1 1 /* SoC has SCGC2[TPM1] */
+# define KINETIS_SIM_HAS_SCGC2_TPM2 1 /* SoC has SCGC2[TPM2] */
+# define KINETIS_SIM_HAS_SCGC3 1 /* SoC has SCGC3 Register */
+# define KINETIS_SIM_HAS_SCGC3_RNGA 1 /* SoC has SCGC3[RNGA] */
+# define KINETIS_SIM_HAS_SCGC3_USBHS 1 /* SoC has SCGC3[USBHS] */
+# define KINETIS_SIM_HAS_SCGC3_USBHSPHY 1 /* SoC has SCGC3[USBHSPHY] */
+# define KINETIS_SIM_HAS_SCGC3_USBHSDCD 1 /* SoC has SCGC3[USBHSDCD] */
+# define KINETIS_SIM_HAS_SCGC3_FLEXCAN1 1 /* SoC has SCGC3[FLEXCAN1] */
+# undef KINETIS_SIM_HAS_SCGC3_NFC /* SoC has SCGC3[NFC] */
+# define KINETIS_SIM_HAS_SCGC3_SPI2 1 /* SoC has SCGC3[SPI2] */
+# undef KINETIS_SIM_HAS_SCGC3_SAI1 /* SoC has SCGC3[SAI1] */
+# define KINETIS_SIM_HAS_SCGC3_SDHC 1 /* SoC has SCGC3[SDHC] */
+# define KINETIS_SIM_HAS_SCGC3_FTM2 1 /* SoC has SCGC3[FTM2] */
+# define KINETIS_SIM_HAS_SCGC3_FTM3 1 /* SoC has SCGC3[FTM3] */
+# define KINETIS_SIM_HAS_SCGC3_ADC1 1 /* SoC has SCGC3[ADC1] */
+# undef KINETIS_SIM_HAS_SCGC3_ADC3 /* SoC has SCGC3[ADC3] */
+# undef KINETIS_SIM_HAS_SCGC3_SLCD /* SoC has SCGC3[SLCD] */
+# define KINETIS_SIM_HAS_SCGC4 1 /* SoC has SCGC4 Register */
+# undef KINETIS_SIM_HAS_SCGC4_LLWU /* SoC has SCGC4[LLWU] clock gate */
+# define KINETIS_SIM_HAS_SCGC4_UART0 1 /* SoC has SCGC4[UART0] */
+# define KINETIS_SIM_HAS_SCGC4_UART1 1 /* SoC has SCGC4[UART1] */
+# define KINETIS_SIM_HAS_SCGC4_UART2 1 /* SoC has SCGC4[UART2] */
+# define KINETIS_SIM_HAS_SCGC4_UART3 1 /* SoC has SCGC4[UART3] */
+# define KINETIS_SIM_HAS_SCGC5 1 /* SoC has _SCGC5 Register */
+# undef KINETIS_SIM_HAS_SCGC5_REGFILE /* SoC has SCGC5[REGFILE] */
+# define KINETIS_SIM_HAS_SCGC5_TSI 1 /* SoC has SCGC5[TSI] */
+# undef KINETIS_SIM_HAS_SCGC5_PORTF /* SoC has SCGC5[PORTF] */
+# define KINETIS_SIM_HAS_SCGC6 1 /* SoC has SCGC6 Register */
+# define KINETIS_SIM_HAS_SCGC6_FTFL 1 /* SoC has SCGC6[FTFL] */
+# undef KINETIS_SIM_HAS_SCGC6_DMAMUX1 /* SoC has SCGC6[DEMUX1] */
+# undef KINETIS_SIM_HAS_SCGC6_USBHS /* SoC has SCGC6[USBHS] */
+# define KINETIS_SIM_HAS_SCGC6_RNGA 1 /* SoC has SCGC6[RNGA] */
+# define KINETIS_SIM_HAS_SCGC6_FTM2 1 /* SoC has SCGC6[FTM2] */
+# undef KINETIS_SIM_HAS_SCGC6_ADC2 /* SoC has SCGC6[ADC2] */
+# define KINETIS_SIM_HAS_SCGC6_DAC0 1 /* SoC has SCGC6[DAC0] */
+# define KINETIS_SIM_HAS_SCGC7 1 /* SoC has SCGC7 Register */
+# define KINETIS_SIM_HAS_SCGC7_FLEXBUS 1 /* SoC has SCGC7[FLEXBUS] */
+# define KINETIS_SIM_HAS_SCGC7_DMA 1 /* SoC has SCGC7[DMS] */
+# define KINETIS_SIM_HAS_SCGC7_MPU 1 /* SoC has SCGC7[MPU] */
+# define KINETIS_SIM_HAS_SCGC7_SDRAMC 1 /* SoC has SCGC7[SDRAMC] */
+# define KINETIS_SIM_HAS_CLKDIV1 1 /* SoC has CLKDIV1 Register */
+# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV2 1 /* SoC has CLKDIV1[OUTDIV2] */
+# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV3 1 /* SoC has CLKDIV1[OUTDIV3] */
+# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV4 1 /* SoC has CLKDIV1[OUTDIV4] */
+# undef KINETIS_SIM_HAS_CLKDIV1_OUTDIV5 /* SoC has CLKDIV1[OUTDIV5] */
+# define KINETIS_SIM_HAS_CLKDIV2 1 /* SoC has CLKDIV2 Register */
+# define KINETIS_SIM_HAS_CLKDIV2_USBDIV 1 /* SoC has CLKDIV2[USBDIV] */
+# define KINETIS_SIM_HAS_CLKDIV2_USBFRAC 1 /* SoC has CLKDIV2[USBFRAC] */
+# undef KINETIS_SIM_HAS_CLKDIV2_USBFSDIV /* SoC has CLKDIV2[USBFSDIV] */
+# undef KINETIS_SIM_HAS_CLKDIV2_USBFSFRAC /* SoC has CLKDIV2[USBFSFRAC] */
+# undef KINETIS_SIM_HAS_CLKDIV2_USBHSDIV /* SoC has CLKDIV2[USBHSDIV] */
+# undef KINETIS_SIM_HAS_CLKDIV2_USBHSFRAC /* SoC has CLKDIV2[USBHSFRAC] */
+# undef KINETIS_SIM_HAS_CLKDIV2_I2SDIV /* SoC has CLKDIV2[I2SDIV] */
+# undef KINETIS_SIM_HAS_CLKDIV2_I2SFRAC /* SoC has CLKDIV2[I2SFRAC] */
+# define KINETIS_SIM_HAS_FCFG1 1 /* SoC has FCFG1 Register */
+# define KINETIS_SIM_HAS_FCFG1_DEPART 1 /* SoC has FCFG1[DEPART] */
+# define KINETIS_SIM_HAS_FCFG1_EESIZE 1 /* SoC has FCFG1[EESIZE] */
+# define KINETIS_SIM_HAS_FCFG1_FLASHDIS 1 /* SoC has FCFG1[FLASHDIS] */
+# define KINETIS_SIM_HAS_FCFG1_FLASHDOZE 1 /* SoC has FCFG1[FLASHDOZE] */
+# undef KINETIS_SIM_HAS_FCFG1_FTFDIS /* SoC has FCFG1[FTFDIS] */
+# define KINETIS_SIM_HAS_FCFG1_NVMSIZE 1 /* SoC has FCFG1[NVMSIZE] */
+# define KINETIS_SIM_HAS_FCFG2 1 /* SoC has FCFG2 Register */
+# define KINETIS_SIM_HAS_FCFG2_MAXADDR0 7 /* SoC has n bit of FCFG2[MAXADDR0] */
+# define KINETIS_SIM_HAS_FCFG2_MAXADDR1 7 /* SoC has n bit of FCFG2[MAXADDR1] */
+# define KINETIS_SIM_HAS_FCFG2_PFLSH 1 /* SoC has FCFG2[PFLSH] */
+# define KINETIS_SIM_HAS_FCFG2_SWAPPFLSH 1 /* SoC has FCFG2[SWAPPFLSH] */
+# define KINETIS_SIM_HAS_UIDH 1 /* SoC has UIDH Register */
+# define KINETIS_SIM_HAS_UIDMH 1 /* SoC has UIDMH Register */
+# define KINETIS_SIM_HAS_UIDML 1 /* SoC has UIDML Register */
+# define KINETIS_SIM_HAS_UIDL 1 /* SoC has UIDL Register */
+# define KINETIS_SIM_HAS_CLKDIV3 1 /* SoC has CLKDIV3 Register */
+# define KINETIS_SIM_HAS_CLKDIV3_PLLFLLDIV 1 /* SoC has CLKDIV3[PLLFLLDIV] */
+# define KINETIS_SIM_HAS_CLKDIV3_PLLFLLFRAC 1 /* SoC has CLKDIV3[PLLFLLFRAC] */
+# define KINETIS_SIM_HAS_CLKDIV4 1 /* SoC has CLKDIV4 Register */
+# define KINETIS_SIM_HAS_CLKDIV4_TRACEDIV 1 /* SoC has CLKDIV4[TRACEDIV] */
+# define KINETIS_SIM_HAS_CLKDIV4_TRACEFRAC 1 /* SoC has CLKDIV4[TRACEFRAC] */
+# undef KINETIS_SIM_HAS_CLKDIV4_NFCDIV /* SoC has CLKDIV4[NFCDIV] */
+# undef KINETIS_SIM_HAS_CLKDIV4_NFCFRAC /* SoC has CLKDIV4[NFCFRAC] */
+# undef KINETIS_SIM_HAS_MCR /* SoC has MCR Register */
+#else
+# error "Unsupported Kinetis chip"
+#endif
+
+/* Use the catch all configuration for the SIM based on the implementations in nuttx prior 2/16/2017 */
+
+#if KINETIS_SIM_VERSION == KINETIS_SIM_VERSION_UKN
+
+/* SIM Register Configuration */
+
+# define KINETIS_SIM_HAS_SOPT1 1 /* SoC has SOPT1 Register */
+# undef KINETIS_SIM_HAS_SOPT1_OSC32KOUT /* SoC has SOPT1[OSC32KOUT] */
+# define KINETIS_SIM_HAS_SOPT1_OSC32KSEL 1 /* SoC has SOPT1[OSC32KSEL] */
+# define KINETIS_SIM_HAS_SOPT1_OSC32KSEL_BITS 1 /* SoC has 1 bit SOPT1[OSC32KSEL] */
+# define KINETIS_SIM_HAS_SOPT1_RAMSIZE 1 /* SoC has SOPT1[RAMSIZE] */
+# define KINETIS_SIM_HAS_SOPT1_USBREGEN 1 /* SoC has SOPT1[USBREGEN] */
+# define KINETIS_SIM_HAS_SOPT1_USBSSTBY 1 /* SoC has SOPT1[USBSSTBY] */
+# undef KINETIS_SIM_HAS_SOPT1_USBVSTBY /* SoC has SOPT1[USBVSTBY] */
+# undef KINETIS_SIM_HAS_SOPT1CFG /* SoC has SOPT1CFG Register */
+# undef KINETIS_SIM_HAS_SOPT1CFG_URWE /* SoC has SOPT1CFG[URWE] */
+# undef KINETIS_SIM_HAS_SOPT1CFG_USSWE /* SoC has SOPT1CFG[USSWE] */
+# undef KINETIS_SIM_HAS_SOPT1CFG_UVSWE /* SoC has SOPT1CFG[UVSWE] */
+# undef KINETIS_SIM_HAS_USBPHYCTL /* SoC has USBPHYCTL Register */
+# undef KINETIS_SIM_HAS_USBPHYCTL_USB3VOUTTRG /* SoC has USBPHYCTL[USB3VOUTTRG] */
+# undef KINETIS_SIM_HAS_USBPHYCTL_USBDISILIM /* SoC has USBPHYCTL[USBDISILIM] */
+# undef KINETIS_SIM_HAS_USBPHYCTL_USBVREGPD /* SoC has USBPHYCTL[USBVREGPD] */
+# undef KINETIS_SIM_HAS_USBPHYCTL_USBVREGSEL /* SoC has USBPHYCTL[USBVREGSEL] */
+# define KINETIS_SIM_HAS_SOPT2 1 /* SoC has SOPT2 Register */
+# define KINETIS_SIM_HAS_SOPT2_CMTUARTPAD 1 /* SoC has SOPT2[CMTUARTPAD] */
+# define KINETIS_SIM_HAS_SOPT2_FBSL 1 /* SoC has SOPT2[FBSL] */
+# undef KINETIS_SIM_HAS_SOPT2_FLEXIOSRC /* SoC has SOPT2[FLEXIOSRC] */
+# undef KINETIS_SIM_HAS_SOPT2_LPUARTSRC /* SoC has SOPT2[LPUARTSRC] */
+# define KINETIS_SIM_HAS_SOPT2_PLLFLLSEL 1 /* SoC has SOPT2[PLLFLLSEL] */
+# define KINETIS_SIM_HAS_SOPT2_PLLFLLSEL_BITS 1 /* SoC has 1 bit of SOPT2[PLLFLLSEL] */
+# undef KINETIS_SIM_HAS_SOPT2_PTD7PAD /* SoC has SOPT2[PTD7PAD] */
+# undef KINETIS_SIM_HAS_SOPT2_RMIISRC /* SoC has SOPT2[RMIISRC] */
+# undef KINETIS_SIM_HAS_SOPT2_RTCCLKOUTSEL /* SoC has SOPT2[RTCCLKOUTSEL] */
+# undef KINETIS_SIM_HAS_SOPT2_CLKOUTSEL /* SoC has SOPT2[CLKOUTSEL] */
+# define KINETIS_SIM_HAS_SOPT2_SDHCSRC 1 /* SoC has SOPT2[SDHCSRC] */
+# define KINETIS_SIM_HAS_SOPT2_TIMESRC 1 /* SoC has SOPT2[TIMESRC] */
+# undef KINETIS_SIM_HAS_SOPT2_TPMSRC /* SoC has SOPT2[TPMSRC] */
+# undef KINETIS_SIM_HAS_SOPT2_USBFSRC /* SoC has SOPT2[USBFSRC] */
+# define KINETIS_SIM_HAS_SOPT2_I2SSRC 1 /* SoC has SOPT2[I2SSRC] */
+# define KINETIS_SIM_HAS_SOPT2_TRACECLKSEL 1 /* SoC has SOPT2[TRACECLKSEL] */
+# undef KINETIS_SIM_HAS_SOPT2_USBREGEN /* SoC has SOPT2[USBREGEN] */
+# undef KINETIS_SIM_HAS_SOPT2_USBSLSRC /* SoC has SOPT2[USBSLSRC] */
+# undef KINETIS_SIM_HAS_SOPT2_USBHSRC /* SoC has SOPT2[USBHSRC] */
+# define KINETIS_SIM_HAS_SOPT2_USBSRC 1 /* SoC has SOPT2[USBSRC] */
+# define KINETIS_SIM_HAS_SOPT2_MCGCLKSEL 1 /* SoC has SOPT2[MCGCLKSEL] */
+# define KINETIS_SIM_HAS_SOPT4 1 /* SoC has SOPT4 Register */
+# define KINETIS_SIM_HAS_SOPT4_FTM0FLT0 1 /* SoC has SOPT4[FTM0FLT0] */
+# define KINETIS_SIM_HAS_SOPT4_FTM0FLT1 1 /* SoC has SOPT4[FTM0FLT1] */
+# define KINETIS_SIM_HAS_SOPT4_FTM0FLT2 1 /* SoC has SOPT4[FTM0FLT2] */
+# undef KINETIS_SIM_HAS_SOPT4_FTM0FLT3 /* SoC has SOPT4[FTM0FLT3] */
+# undef KINETIS_SIM_HAS_SOPT4_FTM0TRG0SRC /* SoC has SOPT4[FTM0TRG0SRC] */
+# undef KINETIS_SIM_HAS_SOPT4_FTM0TRG1SRC /* SoC has SOPT4[FTM0TRG1SRC] */
+# define KINETIS_SIM_HAS_SOPT4_FTM1CH0SRC 1 /* SoC has SOPT4[FTM1CH0SRC] No OF */
+# undef KINETIS_SIM_HAS_SOPT4_FTM1FLT0 /* SoC has SOPT4[FTM1FLT0] */
+# undef KINETIS_SIM_HAS_SOPT4_FTM1FLT1 /* SoC has SOPT4[FTM1FLT1] */
+# undef KINETIS_SIM_HAS_SOPT4_FTM1FLT2 /* SoC has SOPT4[FTM1FLT2] */
+# undef KINETIS_SIM_HAS_SOPT4_FTM1FLT3 /* SoC has SOPT4[FTM1FLT3] */
+# define KINETIS_SIM_HAS_SOPT4_FTM2CH0SRC 1 /* SoC has SOPT4[FTM2CH0SRC] */
+# undef KINETIS_SIM_HAS_SOPT4_FTM2CH1SRC /* SoC has SOPT4[FTM2CH1SRC] */
+# undef KINETIS_SIM_HAS_SOPT4_FTM2FLT0 /* SoC has SOPT4[FTM2FLT0] */
+# undef KINETIS_SIM_HAS_SOPT4_FTM2FLT1 /* SoC has SOPT4[FTM2FLT1] */
+# undef KINETIS_SIM_HAS_SOPT4_FTM2FLT2 /* SoC has SOPT4[FTM2FLT2] */
+# undef KINETIS_SIM_HAS_SOPT4_FTM2FLT3 /* SoC has SOPT4[FTM2FLT3] */
+# undef KINETIS_SIM_HAS_SOPT4_FTM3CH0SRC /* SoC has SOPT4[FTM3CH0SRC] */
+# undef KINETIS_SIM_HAS_SOPT4_FTM3FLT0 /* SoC has SOPT4[FTM3FLT0] */
+# undef KINETIS_SIM_HAS_SOPT4_FTM3FLT1 /* SoC has SOPT4[FTM3FLT1] */
+# undef KINETIS_SIM_HAS_SOPT4_FTM3FLT2 /* SoC has SOPT4[FTM3FLT2] */
+# undef KINETIS_SIM_HAS_SOPT4_FTM3FLT3 /* SoC has SOPT4[FTM3FLT3] */
+# undef KINETIS_SIM_HAS_SOPT4_FTM3TRG0SRC /* SoC has SOPT4[FTM3TRG0SRC] */
+# undef KINETIS_SIM_HAS_SOPT4_FTM3TRG1SRC /* SoC has SOPT4[FTM3TRG1SRC] */
+# undef KINETIS_SIM_HAS_SOPT4_TPM0CLKSEL /* SoC has SOPT4[TPM0CLKSEL] */
+# undef KINETIS_SIM_HAS_SOPT4_TPM1CH0SRC /* SoC has SOPT4[TPM1CH0SRC] */
+# undef KINETIS_SIM_HAS_SOPT4_TPM1CLKSEL /* SoC has SOPT4[TPM1CLKSEL] */
+# undef KINETIS_SIM_HAS_SOPT4_TPM2CH0SRC /* SoC has SOPT4[TPM2CH0SRC] */
+# undef KINETIS_SIM_HAS_SOPT4_TPM2CLKSEL /* SoC has SOPT4[TPM2CLKSEL] */
+# define KINETIS_SIM_HAS_SOPT5 /* SoC has SOPT5 Register */
+# undef KINETIS_SIM_HAS_SOPT5_LPUART0RXSRC /* SoC has SOPT5[LPUART0RXSRC] */
+# undef KINETIS_SIM_HAS_SOPT5_LPUART0TXSRC /* SoC has SOPT5[LPUART0TXSRC] */
+# define KINETIS_SIM_HAS_SOPT6 1 /* SoC has SOPT6 Register */
+# undef KINETIS_SIM_HAS_SOPT6_MCC /* SoC has SOPT6[MCC] */
+# undef KINETIS_SIM_HAS_SOPT6_PCR /* SoC has SOPT6[PCR] */
+# define KINETIS_SIM_HAS_SOPT6_RSTFLTSEL 1 /* SoC has SOPT6[RSTFLTSEL] */
+# define KINETIS_SIM_HAS_SOPT6_RSTFLTEN 1 /* SoC has SOPT6[RSTFLTEN] */
+# define KINETIS_SIM_HAS_SOPT7 1 /* SoC has SOPT7 Register */
+# define KINETIS_SIM_HAS_SOPT7_ADC0ALTTRGSEL 1 /* SoC has SOPT7[ADC0ALTTRGSEL] */
+# define KINETIS_SIM_HAS_SOPT7_ADC1ALTTRGSEL 1 /* SoC has SOPT7[ADC1ALTTRGSEL] */
+# define KINETIS_SIM_HAS_SOPT7_ADC0PRETRGSEL 1 /* SoC has SOPT7[ADC0PRETRGSEL] */
+# define KINETIS_SIM_HAS_SOPT7_ADC1PRETRGSEL 1 /* SoC has SOPT7[ADC1PRETRGSEL] */
+# undef KINETIS_SIM_HAS_SOPT7_ADC2PRETRGSEL /* SoC has SOPT7[ADC2PRETRGSEL] */
+# undef KINETIS_SIM_HAS_SOPT7_ADC3PRETRGSEL /* SoC has SOPT7[ADC3PRETRGSEL] */
+# define KINETIS_SIM_HAS_SOPT7_ADC0TRGSEL 14 /* SoC has 10 SOPT7[ADC0TRGSEL] */
+# define KINETIS_SIM_HAS_SOPT7_ADC1TRGSEL 14 /* SoC has 10 SOPT7[ADC1TRGSEL] */
+# undef KINETIS_SIM_HAS_SOPT7_ADC2TRGSEL /* SoC has 10 SOPT7[ADC2TRGSEL] */
+# undef KINETIS_SIM_HAS_SOPT7_ADC3TRGSEL /* SoC has 10 SOPT7[ADC3TRGSEL] */
+# define KINETIS_SIM_SOPT7_ADC0ALTTRGEN 1 /* ADC0 alternate trigger enable */
+# define KINETIS_SIM_SOPT7_ADC1ALTTRGEN 1 /* ADC1 alternate trigger enable */
+# undef KINETIS_SIM_SOPT7_ADC2ALTTRGEN /* ADC2 alternate trigger enable */
+# undef KINETIS_SIM_SOPT7_ADC3ALTTRGEN /* ADC3 alternate trigger enable */
+# undef KINETIS_SIM_HAS_SOPT8 /* SoC has SOPT8 Register */
+# undef KINETIS_SIM_HAS_SOPT9 /* SoC has SOPT9 Register */
+# define KINETIS_SIM_HAS_SDID 1 /* SoC has SDID Register */
+# undef KINETIS_SIM_HAS_SDID_DIEID /* SoC has SDID[DIEID] */
+# define KINETIS_SIM_HAS_SDID_FAMID 1 /* SoC has SDID[FAMID] */
+# undef KINETIS_SIM_HAS_SDID_FAMILYID /* SoC has SDID[FAMILYID] */
+# undef KINETIS_SIM_HAS_SDID_SERIESID /* SoC has SDID[SERIESID] */
+# undef KINETIS_SIM_HAS_SDID_SRAMSIZE /* SoC has SDID[SRAMSIZE] */
+# undef KINETIS_SIM_HAS_SDID_SUBFAMID /* SoC has SDID[SUBFAMID] */
+# define KINETIS_SIM_HAS_SCGC1 1 /* SoC has SCGC1 Register */
+# define KINETIS_SIM_HAS_SCGC1_UART5 1 /* SoC has SCGC1[UART5] */
+# define KINETIS_SIM_HAS_SCGC1_UART4 1 /* SoC has SCGC1[UART4] */
+# undef KINETIS_SIM_HAS_SCGC1_I2C3 /* SoC has SCGC1[I2C3] */
+# undef KINETIS_SIM_HAS_SCGC1_I2C2 /* SoC has SCGC1[I2C2] */
+# undef KINETIS_SIM_HAS_SCGC1_OSC1 /* SoC has SCGC1[OSC1] */
+# define KINETIS_SIM_HAS_SCGC2 1 /* SoC has SCGC2 Register */
+# define KINETIS_SIM_HAS_SCGC2_ENET 1 /* SoC has SCGC2[ENET] */
+# undef KINETIS_SIM_HAS_SCGC2_LPUART0 /* SoC has SCGC2[LPUART0] */
+# undef KINETIS_SIM_HAS_SCGC2_TPM1 /* SoC has SCGC2[TPM1] */
+# undef KINETIS_SIM_HAS_SCGC2_TPM2 /* SoC has SCGC2[TPM2] */
+# define KINETIS_SIM_HAS_SCGC3 1 /* SoC has SCGC3 Register */
+# define KINETIS_SIM_HAS_SCGC3_RNGA 1 /* SoC has SCGC3[RNGA] */
+# undef KINETIS_SIM_HAS_SCGC3_USBHS /* SoC has SCGC3[USBHS] */
+# undef KINETIS_SIM_HAS_SCGC3_USBHSPHY /* SoC has SCGC3[USBHSPHY] */
+# undef KINETIS_SIM_HAS_SCGC3_USBHSDCD /* SoC has SCGC3[USBHSDCD] */
+# define KINETIS_SIM_HAS_SCGC3_FLEXCAN1 1 /* SoC has SCGC3[FLEXCAN1] */
+# undef KINETIS_SIM_HAS_SCGC3_NFC /* SoC has SCGC3[NFC] */
+# define KINETIS_SIM_HAS_SCGC3_SPI2 1 /* SoC has SCGC3[SPI2] */
+# undef KINETIS_SIM_HAS_SCGC3_SAI1 /* SoC has SCGC3[SAI1] */
+# define KINETIS_SIM_HAS_SCGC3_SDHC 1 /* SoC has SCGC3[SDHC] */
+# define KINETIS_SIM_HAS_SCGC3_FTM2 1 /* SoC has SCGC3[FTM2] */
+# define KINETIS_SIM_HAS_SCGC3_FTM3 1 /* SoC has SCGC3[FTM3] */
+# define KINETIS_SIM_HAS_SCGC3_ADC1 1 /* SoC has SCGC3[ADC1] */
+# undef KINETIS_SIM_HAS_SCGC3_ADC3 /* SoC has SCGC3[ADC3] */
+# define KINETIS_SIM_HAS_SCGC3_SLCD 1 /* SoC has SCGC3[SLCD] */
+# define KINETIS_SIM_HAS_SCGC4 1 /* SoC has SCGC4 Register */
+# define KINETIS_SIM_HAS_SCGC4_LLWU 1 /* SoC has SCGC4[LLWU] clock gate */
+# define KINETIS_SIM_HAS_SCGC4_UART0 1 /* SoC has SCGC4[UART0] */
+# define KINETIS_SIM_HAS_SCGC4_UART1 1 /* SoC has SCGC4[UART1] */
+# define KINETIS_SIM_HAS_SCGC4_UART2 1 /* SoC has SCGC4[UART2] */
+# define KINETIS_SIM_HAS_SCGC4_UART3 1 /* SoC has SCGC4[UART3] */
+# define KINETIS_SIM_HAS_SCGC5 1 /* SoC has SCGC5 Register */
+# define KINETIS_SIM_HAS_SCGC5_REGFILE 1 /* SoC has SCGC5[REGFILE] */
+# define KINETIS_SIM_HAS_SCGC5_TSI 1 /* SoC has SCGC5[TSI] */
+# undef KINETIS_SIM_HAS_SCGC5_PORTF /* SoC has SCGC5[PORTF] */
+# define KINETIS_SIM_HAS_SCGC6 1 /* SoC has SCGC6 Register */
+# define KINETIS_SIM_HAS_SCGC6_FTFL 1 /* SoC has SCGC6[FTFL] */
+# undef KINETIS_SIM_HAS_SCGC6_DMAMUX1 /* SoC has SCGC6[DEMUX1] */
+# undef KINETIS_SIM_HAS_SCGC6_USBHS /* SoC has SCGC6[USBHS] */
+# undef KINETIS_SIM_HAS_SCGC6_RNGA /* SoC has SCGC6[RNGA] */
+# undef KINETIS_SIM_HAS_SCGC6_FTM2 /* SoC has SCGC6[FTM2] */
+# undef KINETIS_SIM_HAS_SCGC6_ADC2 /* SoC has SCGC6[ADC2] */
+# undef KINETIS_SIM_HAS_SCGC6_DAC0 /* SoC has SCGC6[DAC0] */
+# define KINETIS_SIM_HAS_SCGC7 1 /* SoC has SCGC7 Register */
+# define KINETIS_SIM_HAS_SCGC7_FLEXBUS 1 /* SoC has SCGC7[FLEXBUS] */
+# define KINETIS_SIM_HAS_SCGC7_DMA 1 /* SoC has SCGC7[DMS] */
+# define KINETIS_SIM_HAS_SCGC7_MPU 1 /* SoC has SCGC7[MPU] */
+# undef KINETIS_SIM_HAS_SCGC7_SDRAMC /* SoC has SCGC7[SDRAMC] */
+# define KINETIS_SIM_HAS_CLKDIV1 1 /* SoC has CLKDIV1 Register */
+# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV2 1 /* SoC has CLKDIV1[OUTDIV2] */
+# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV3 1 /* SoC has CLKDIV1[OUTDIV3] */
+# define KINETIS_SIM_HAS_CLKDIV1_OUTDIV4 1 /* SoC has CLKDIV1[OUTDIV4] */
+# undef KINETIS_SIM_HAS_CLKDIV1_OUTDIV5 /* SoC has CLKDIV1[OUTDIV5] */
+# define KINETIS_SIM_HAS_CLKDIV2 1 /* SoC has CLKDIV2 Register */
+# define KINETIS_SIM_HAS_CLKDIV2_USBDIV 1 /* SoC has CLKDIV2[USBDIV] */
+# define KINETIS_SIM_HAS_CLKDIV2_USBFRAC 1 /* SoC has CLKDIV2[USBFRAC] */
+# undef KINETIS_SIM_HAS_CLKDIV2_USBFSDIV /* SoC has CLKDIV2[USBFSDIV] */
+# undef KINETIS_SIM_HAS_CLKDIV2_USBFSFRAC /* SoC has CLKDIV2[USBFSFRAC] */
+# undef KINETIS_SIM_HAS_CLKDIV2_USBHSDIV /* SoC has CLKDIV2[USBHSDIV] */
+# undef KINETIS_SIM_HAS_CLKDIV2_USBHSFRAC /* SoC has CLKDIV2[USBHSFRAC] */
+# define KINETIS_SIM_HAS_CLKDIV2_I2SDIV 1 /* SoC has CLKDIV2[I2SDIV] */
+# define KINETIS_SIM_HAS_CLKDIV2_I2SFRAC 1 /* SoC has CLKDIV2[I2SFRAC] */
+# define KINETIS_SIM_HAS_FCFG1 1 /* SoC has FCFG1 Register */
+# define KINETIS_SIM_HAS_FCFG1_DEPART 1 /* SoC has FCFG1[DEPART] */
+# define KINETIS_SIM_HAS_FCFG1_EESIZE 1 /* SoC has FCFG1[EESIZE] */
+# undef KINETIS_SIM_HAS_FCFG1_FLASHDIS /* SoC has FCFG1[FLASHDIS] */
+# undef KINETIS_SIM_HAS_FCFG1_FLASHDOZE /* SoC has FCFG1[FLASHDOZE] */
+# undef KINETIS_SIM_HAS_FCFG1_FTFDIS /* SoC has FCFG1[FTFDIS] */
+# define KINETIS_SIM_HAS_FCFG1_NVMSIZE 1 /* SoC has FCFG1[NVMSIZE] */
+# define KINETIS_SIM_HAS_FCFG2 1 /* SoC has FCFG2 Register */
+# define KINETIS_SIM_HAS_FCFG2_MAXADDR0 6 /* SoC has n bit of FCFG2[MAXADDR0] */
+# define KINETIS_SIM_HAS_FCFG2_MAXADDR1 6 /* SoC has n bit of FCFG2[MAXADDR1] */
+# define KINETIS_SIM_HAS_FCFG2_PFLSH 1 /* SoC has FCFG2[PFLSH] */
+# define KINETIS_SIM_HAS_FCFG2_SWAPPFLSH 1 /* SoC has FCFG2[SWAPPFLSH] */
+# define KINETIS_SIM_HAS_UIDH 1 /* SoC has UIDH Register */
+# define KINETIS_SIM_HAS_UIDMH 1 /* SoC has UIDMH Register */
+# define KINETIS_SIM_HAS_UIDML 1 /* SoC has UIDML Register */
+# define KINETIS_SIM_HAS_UIDL 1 /* SoC has UIDL Register */
+# undef KINETIS_SIM_HAS_CLKDIV3 /* SoC has CLKDIV3 Register */
+# undef KINETIS_SIM_HAS_CLKDIV3_PLLFLLDIV /* SoC has CLKDIV3[PLLFLLDIV] */
+# undef KINETIS_SIM_HAS_CLKDIV3_PLLFLLFRAC /* SoC has CLKDIV3[PLLFLLFRAC] */
+# undef KINETIS_SIM_HAS_CLKDIV4 /* SoC has CLKDIV4 Register */
+# undef KINETIS_SIM_HAS_CLKDIV4_TRACEDIV /* SoC has CLKDIV4[TRACEDIV] */
+# undef KINETIS_SIM_HAS_CLKDIV4_TRACEFRAC /* SoC has CLKDIV4[TRACEFRAC] */
+# undef KINETIS_SIM_HAS_CLKDIV4_NFCDIV /* SoC has CLKDIV4[NFCDIV] */
+# undef KINETIS_SIM_HAS_CLKDIV4_NFCFRAC /* SoC has CLKDIV4[NFCFRAC] */
+# undef KINETIS_SIM_HAS_MCR /* SoC has MCR Register */
+#endif
+
+#if !defined(KINETIS_SIM_VERSION)
+# error "No KINETIS_SIM_VERSION defined!"
+#endif
+
+#if defined(KINETIS_SIM_HAS_SOPT1_OSC32KSEL)
+# define KINETIS_SIM_SOPT1_OSC32KSEL_MASK ((1 << (KINETIS_SIM_HAS_SOPT1_OSC32KSEL_BITS))-1)
+#endif
+
+#if defined(KINETIS_SIM_HAS_SOPT2_PLLFLLSEL)
+# define KINETIS_SIM_SOPT2_PLLFLLSEL_MASK ((1 << (KINETIS_SIM_HAS_SOPT2_PLLFLLSEL_BITS))-1)
+#endif
+
+#if defined(KINETIS_SIM_HAS_FCFG2_MAXADDR0)
+# define KINETIS_SIM_FCFG2_MAXADDR0_MASK ((1 << (KINETIS_SIM_HAS_FCFG2_MAXADDR0))-1)
+#endif
+
+#if defined(KINETIS_SIM_HAS_FCFG2_MAXADDR1)
+# define KINETIS_SIM_FCFG2_MAXADDR1_MASK ((1 << (KINETIS_SIM_HAS_FCFG2_MAXADDR1))-1)
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_KINETIS_KINETIS_SIM_H */
diff --git a/arch/arm/include/kl/chip.h b/arch/arm/include/kl/chip.h
index df1029eecb4d5b47f64a3360b12d5791575ee033..8be3b2029fd514ae54adc178768ec994ca0c427e 100644
--- a/arch/arm/include/kl/chip.h
+++ b/arch/arm/include/kl/chip.h
@@ -50,7 +50,7 @@
#if defined(CONFIG_ARCH_CHIP_MKL25Z64)
-# define KL_Z64 1 /* Kinetics KL25Z128 family */
+# define KL_Z64 1 /* Kinetis KL25Z128 family */
# define KL_FLASH_SIZE (64*1024) /* 64Kb */
# define KL_SRAM_SIZE (8*1024) /* 8Kb */
# undef KL_MPU /* No memory protection unit */
@@ -88,7 +88,7 @@
#elif defined(CONFIG_ARCH_CHIP_MKL25Z128)
-# define KL_Z128 1 /* Kinetics KL25Z128 family */
+# define KL_Z128 1 /* Kinetis KL25Z128 family */
# define KL_FLASH_SIZE (128*1024) /* 64Kb */
# define KL_SRAM_SIZE (16*1024) /* 16Kb */
# undef KL_MPU /* No memory protection unit */
@@ -127,7 +127,7 @@
#elif defined(CONFIG_ARCH_CHIP_MKL26Z128)
-# define KL_Z128 1 /* Kinetics KL25Z128 family */
+# define KL_Z128 1 /* Kinetis KL25Z128 family */
# define KL_FLASH_SIZE (128*1024) /* 64Kb */
# define KL_SRAM_SIZE (16*1024) /* 16Kb */
# undef KL_MPU /* No memory protection unit */
diff --git a/arch/arm/include/kl/irq.h b/arch/arm/include/kl/irq.h
index 27ba8575f52d023f7c9324244a967c05075b6d1c..93021827300d09f52eb1c91b7518cbe43a6d123c 100644
--- a/arch/arm/include/kl/irq.h
+++ b/arch/arm/include/kl/irq.h
@@ -58,7 +58,7 @@
/* Processor Exceptions (vectors 0-15) */
-#define KL_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+#define KL_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define KL_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
diff --git a/arch/arm/include/lpc11xx/irq.h b/arch/arm/include/lpc11xx/irq.h
index caac7c3e170c1d858882bbf13a32ae10bb6741fd..46ff7d27cac9225a98bca731e1a287dff5beb9ab 100644
--- a/arch/arm/include/lpc11xx/irq.h
+++ b/arch/arm/include/lpc11xx/irq.h
@@ -59,7 +59,7 @@
/* Common Processor Exceptions (vectors 0-15) */
-#define LPC11_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+#define LPC11_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define LPC11_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
diff --git a/arch/arm/include/lpc17xx/irq.h b/arch/arm/include/lpc17xx/irq.h
index 6af683225ca64dbcad3a639e1f64714018f68976..99bffe17ebbd38510bc10b734fcd1623d480e010 100644
--- a/arch/arm/include/lpc17xx/irq.h
+++ b/arch/arm/include/lpc17xx/irq.h
@@ -59,7 +59,7 @@
/* Common Processor Exceptions (vectors 0-15) */
-#define LPC17_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+#define LPC17_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define LPC17_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
diff --git a/arch/arm/include/lpc17xx/lpc176x_irq.h b/arch/arm/include/lpc17xx/lpc176x_irq.h
index 248c5c47d66070842bed5b0dda851ec236a2b7dd..b844b33d652abd27ccaf2ae87a2b01359cd77c89 100644
--- a/arch/arm/include/lpc17xx/lpc176x_irq.h
+++ b/arch/arm/include/lpc17xx/lpc176x_irq.h
@@ -147,7 +147,7 @@
* 42
*/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
# define LPC17_VALID_GPIOINT0 (0x7fff8ffful) /* GPIO port 0 interrupt set */
# define LPC17_VALID_GPIOINT2 (0x00003ffful) /* GPIO port 2 interrupt set */
diff --git a/arch/arm/include/lpc17xx/lpc178x_irq.h b/arch/arm/include/lpc17xx/lpc178x_irq.h
index 76c749045282f80dac2bf2be47d93fee0f991c99..52ed1731a5ceb6fa7af3c93ddaeb0b2fc13007bb 100644
--- a/arch/arm/include/lpc17xx/lpc178x_irq.h
+++ b/arch/arm/include/lpc17xx/lpc178x_irq.h
@@ -166,7 +166,7 @@
* 42
*/
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_LPC17_GPIOIRQ
# define LPC17_VALID_GPIOINT0 (0xfffffffful) /* GPIO port 0 interrupt set */
# define LPC17_VALID_GPIOINT2 (0xfffffffful) /* GPIO port 2 interrupt set */
diff --git a/arch/arm/include/lpc214x/irq.h b/arch/arm/include/lpc214x/irq.h
index a4737c38d4bade9651ecb5304accf205dd9ae6bf..852dd0c6495f4dd1993c979bf523100b2170f650 100644
--- a/arch/arm/include/lpc214x/irq.h
+++ b/arch/arm/include/lpc214x/irq.h
@@ -37,8 +37,8 @@
* only indirectly through nuttx/irq.h
*/
-#ifndef __ARCH_LPC214X_IRQ_H
-#define __ARCH_LPC214X_IRQ_H
+#ifndef __ARCH_ARM_INCLUDE_LPC214X_IRQ_H
+#define __ARCH_ARM_INCLUDE_LPC214X_IRQ_H
/****************************************************************************
* Included Files
@@ -127,5 +127,5 @@ void up_detach_vector(int vector);
#endif
#endif
-#endif /* __ARCH_LPC214X_IRQ_H */
+#endif /* __ARCH_ARM_INCLUDE_LPC214X_IRQ_H */
diff --git a/arch/arm/include/lpc2378/irq.h b/arch/arm/include/lpc2378/irq.h
index 18ef58604b737fa269dc9dbba6febcf9dab137ba..8fa2067fc970ca1be862b1967ca2e02544a32758 100644
--- a/arch/arm/include/lpc2378/irq.h
+++ b/arch/arm/include/lpc2378/irq.h
@@ -43,8 +43,8 @@
* only indirectly through nuttx/irq.h
*/
-#ifndef __ARCH_LPC2378_IRQ_H
-#define __ARCH_LPC2378_IRQ_H
+#ifndef __ARCH_ARM_INCLUDE_LPC2378_IRQ_H
+#define __ARCH_ARM_INCLUDE_LPC2378_IRQ_H
/****************************************************************************
* Included Files
@@ -149,4 +149,4 @@ void up_detach_vector(int vector);
#endif
#endif
-#endif /* __ARCH_LPC2378_IRQ_H */
+#endif /* __ARCH_ARM_INCLUDE_LPC2378_IRQ_H */
diff --git a/arch/arm/include/lpc43xx/chip.h b/arch/arm/include/lpc43xx/chip.h
index 4592117de184bb059bacd774145714233b1c4e17..3729ff8f81f5556c26b8511d09643a52b77af2be 100644
--- a/arch/arm/include/lpc43xx/chip.h
+++ b/arch/arm/include/lpc43xx/chip.h
@@ -347,6 +347,32 @@
# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
# undef LPC43_NADC12 /* No 12-bit ADC controllers */
+#elif defined(CONFIG_ARCH_CHIP_LPC4337FET256)
+# define LPC43_FLASH_BANKA_SIZE (512*1024) /* 1024Kb FLASH */
+# define LPC43_FLASH_BANKB_SIZE (512*1024)
+# define LPC43_LOCSRAM_BANK0_SIZE (32*1024) /* 72Kb Local SRAM */
+# define LPC43_LOCSRAM_BANK1_SIZE (40*1024)
+# define LPC43_AHBSRAM_BANK0_SIZE (48*1024) /* 64Kb AHB SRAM */
+# define LPC43_AHBSRAM_BANK1_SIZE (0)
+# define LPC43_AHBSRAM_BANK2_SIZE (16*1024)
+# define LPC43_EEPROM_SIZE (16*1024) /* 16Kb EEPROM */
+# undef LPC43_NLCD /* No LCD controller */
+# define LPC43_ETHERNET (1) /* One Ethernet controller */
+# define LPC43_USB0 (1) /* Have USB0 (Host, Device, OTG) */
+# define LPC43_USB1 (1) /* Have USB1 (Host, Device) */
+# define LPC43_USB1_ULPI (1) /* Have USB1 (Host, Device) with ULPI I/F */
+# define LPC43_MCPWM (1) /* One PWM interface */
+# define LPC43_QEI (1) /* One Quadrature Encoder interface */
+# define LPC43_NUSARTS (4) /* Three USARTs + 1 UART */
+# define LPC43_NSSP (2) /* Two SSP controllers */
+# define LPC43_NTIMERS (4) /* Four Timers */
+# define LPC43_NI2C (2) /* Two I2C controllers */
+# define LPC43_NI2S (2) /* Two I2S controllers */
+# define LPC43_NCAN (2) /* Two CAN controllers */
+# define LPC43_NDAC (1) /* One 10-bit DAC */
+# define LPC43_NADC10 (2) /* Two 10-bit ADC controllers */
+# define LPC43_NADC10_CHANNELS (8) /* Eight ADC channels */
+# undef LPC43_NADC12 /* No 12-bit ADC controllers */
#elif defined(CONFIG_ARCH_CHIP_LPC4350FBD208)
# define LPC43_FLASH_BANKA_SIZE (0) /* Flashless */
# define LPC43_FLASH_BANKB_SIZE (0)
diff --git a/arch/arm/include/lpc43xx/irq.h b/arch/arm/include/lpc43xx/irq.h
index 9b103e97185005d00d3e254fee0d6ca03ccf3fce..dd9790ab10774093de24bfce479ecf4ee39f4103 100644
--- a/arch/arm/include/lpc43xx/irq.h
+++ b/arch/arm/include/lpc43xx/irq.h
@@ -59,7 +59,7 @@
/* Processor Exceptions (vectors 0-15) */
-#define LPC43_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+#define LPC43_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define LPC43_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
diff --git a/arch/arm/include/nuc1xx/irq.h b/arch/arm/include/nuc1xx/irq.h
index 0db0379d1b4b4360b1ba4fe68491c546afcdf1d5..26b0d8125f510f055abdc400f8e08a8e66e52a44 100644
--- a/arch/arm/include/nuc1xx/irq.h
+++ b/arch/arm/include/nuc1xx/irq.h
@@ -58,7 +58,7 @@
/* Processor Exceptions (vectors 0-15) */
-#define NUC_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+#define NUC_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define NUC_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
diff --git a/arch/arm/include/sam34/chip.h b/arch/arm/include/sam34/chip.h
index 3bd3b42d51e868e3a52c113302d244bef281e19c..fc67f3b5fd4850b1ab2ae988a28f5c39d341aa65 100644
--- a/arch/arm/include/sam34/chip.h
+++ b/arch/arm/include/sam34/chip.h
@@ -543,21 +543,21 @@
/* AT91SAM4S Family *****************************************************************/
/*
- * FEATURE SAM4SD32C SAM4SD32B SAM4SD16C SAM4SD16B SAM4SA16C SAM4SA16B SAM4S16C SAM4S16B SAM4S8C SAM4S8B
- * ------------- --------- --------- --------- --------- --------- --------- -------- -------- ------- -------
- * Flash 2x1MB 2x1MB 2x512KB 1x1MB 1x1MB 1x1MB 1x1MB 1x1MB 1x512KB 1x512KB
- * SRAM 160KB 160KB 160KB 160KB 160KB 160KB 128KB 128KB 128KB 128KB
- * HCACHE 2KB 2KB 2KB 2KB 2KB 2KB - - - -
- * Pins 100 64 100 64 100 64 100 64 100 64
- * No. PIOs 79 47 79 47 79 47 79 47 79 47
- * Ext. BUS Yes No Yes No Yes No Yes No Yes No
- * 12-bit ADC 16 ch 11 ch 16 ch 11 ch 16 ch 11 ch 16 ch 11 ch 16 ch 11 ch
- * 12-bit DAC 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch
- * Timer Counter 6 ch 3 ch 6 ch 3 ch 6 ch 3 ch 6 ch 3 ch 6 ch 3 ch
- * PDC 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch
- * USART 2 2 2 2 2 2 2 2 2 2
- * UART 2 2 2 2 2 2 2 2 2 2
- * HSMCI Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
+ * FEATURE SAM4SD32C SAM4SD32B SAM4SD16C SAM4SD16B SAM4SA16C SAM4SA16B SAM4S16C SAM4S16B SAM4S8C SAM4S8B SAM4S4C
+ * ------------- --------- --------- --------- --------- --------- --------- -------- -------- ------- ------- -------
+ * Flash 2x1MB 2x1MB 2x512KB 1x1MB 1x1MB 1x1MB 1x1MB 1x1MB 1x512KB 1x512KB 1x256KB
+ * SRAM 160KB 160KB 160KB 160KB 160KB 160KB 128KB 128KB 128KB 128KB 64KB
+ * HCACHE 2KB 2KB 2KB 2KB 2KB 2KB - - - - -
+ * Pins 100 64 100 64 100 64 100 64 100 64 100
+ * No. PIOs 79 47 79 47 79 47 79 47 79 47 79
+ * Ext. BUS Yes No Yes No Yes No Yes No Yes No Yes
+ * 12-bit ADC 16 ch 11 ch 16 ch 11 ch 16 ch 11 ch 16 ch 11 ch 16 ch 11 ch 16 ch
+ * 12-bit DAC 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch 2 ch
+ * Timer Counter 6 ch 3 ch 6 ch 3 ch 6 ch 3 ch 6 ch 3 ch 6 ch 3 ch 6 ch
+ * PDC 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch 22 ch
+ * USART 2 2 2 2 2 2 2 2 2 2 2
+ * UART 2 2 2 2 2 2 2 2 2 2 2
+ * HSMCI Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
*/
#elif defined(CONFIG_ARCH_CHIP_ATSAM4SD32C)
@@ -760,6 +760,26 @@
# define SAM34_NUDPFS 1 /* 1 USB full speed device */
# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
+#elif defined(CONFIG_ARCH_CHIP_ATSAM4S4C)
+/* Internal memory */
+
+# define SAM34_FLASH_SIZE (256*1024) /* 256KB */
+# define SAM34_SRAM0_SIZE (64*1024) /* 64KB */
+# define SAM34_SRAM1_SIZE 0 /* None */
+# define SAM34_NFCSRAM_SIZE 0 /* None */
+
+/* Peripherals */
+
+# define SAM34_NDMACHAN 0 /* No DMAC Channels */
+# define SAM34_NPDCCHAN 22 /* 22 PDC Channels */
+# define SAM34_NMCI2 1 /* 1 memory card interface */
+# define SAM34_NSLCD 0 /* No segment LCD interface */
+# define SAM34_NAESA 0 /* No advanced encryption standard */
+# define SAM34_NUDPHS 0 /* No USB high speed device */
+# define SAM34_NUHPHS 0 /* No USB high speed embedded host */
+# define SAM34_NUDPFS 1 /* 1 USB full speed device */
+# define SAM34_NUHPFS 0 /* No USB full speed embedded host */
+
/* AT91SAM4E Family *****************************************************************/
/* FEATURE SAM4E16E SAM4E8E SAM4E16C SAM4E8C
* ----------- --------- -------- -------- --------
diff --git a/arch/arm/include/sam34/irq.h b/arch/arm/include/sam34/irq.h
index 521cd5a93cd71b10d8f5076fb8283a0bd4fbc423..a0f5de604f78b1455b2e72f10108a31f4c8efd42 100644
--- a/arch/arm/include/sam34/irq.h
+++ b/arch/arm/include/sam34/irq.h
@@ -58,7 +58,7 @@
/* Common Processor Exceptions (vectors 0-15) */
-#define SAM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+#define SAM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define SAM_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
diff --git a/arch/arm/include/samdl/irq.h b/arch/arm/include/samdl/irq.h
index d74584fb298cc557b03dfe5dfb2804d0a811152c..7da8c7b21e6282b70b4645c57fb806645ef07fc2 100644
--- a/arch/arm/include/samdl/irq.h
+++ b/arch/arm/include/samdl/irq.h
@@ -58,7 +58,7 @@
/* Processor Exceptions (vectors 0-15) */
-#define SAM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+#define SAM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define SAM_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
diff --git a/arch/arm/include/samdl/samd20_irq.h b/arch/arm/include/samdl/samd20_irq.h
index 01361e8e00e5b8d9d7e9574fbdacf5b13deca5ee..709fddaeac891120c423746105fa696dcc3580e5 100644
--- a/arch/arm/include/samdl/samd20_irq.h
+++ b/arch/arm/include/samdl/samd20_irq.h
@@ -81,7 +81,7 @@
/* GPIO interrupts. Up to 16 pins may be configured to support interrupts */
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_SAMDL_GPIOIRQ
# define SAM_IRQ_EXTINT0 (SAM_IRQ_NIRQS+0) /* External interrupt 0 */
# define SAM_IRQ_EXTINT1 (SAM_IRQ_NIRQS+1) /* External interrupt 1 */
# define SAM_IRQ_EXTINT2 (SAM_IRQ_NIRQS+2) /* External interrupt 2 */
diff --git a/arch/arm/include/samdl/samd21_irq.h b/arch/arm/include/samdl/samd21_irq.h
index 2ea4db825795737185aeda5fdea09c6c10357645..7b5c633ef62bffe9675a20ced0096a3c5d75bcf3 100644
--- a/arch/arm/include/samdl/samd21_irq.h
+++ b/arch/arm/include/samdl/samd21_irq.h
@@ -88,7 +88,7 @@
/* GPIO interrupts. Up to 16 pins may be configured to support interrupts */
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_SAMDL_GPIOIRQ
# define SAM_IRQ_EXTINT0 (SAM_IRQ_NIRQS+0) /* External interrupt 0 */
# define SAM_IRQ_EXTINT1 (SAM_IRQ_NIRQS+1) /* External interrupt 1 */
# define SAM_IRQ_EXTINT2 (SAM_IRQ_NIRQS+2) /* External interrupt 2 */
diff --git a/arch/arm/include/samdl/saml21_irq.h b/arch/arm/include/samdl/saml21_irq.h
index 9622a0321523cc257ab1de0f09435cea89c86439..24c774dbd0f4421e56f97c5e1eedf73d4083d51d 100644
--- a/arch/arm/include/samdl/saml21_irq.h
+++ b/arch/arm/include/samdl/saml21_irq.h
@@ -89,7 +89,7 @@
/* GPIO interrupts. Up to 16 pins may be configured to support interrupts */
-#ifdef CONFIG_GPIO_IRQ
+#ifdef CONFIG_SAMDL_GPIOIRQ
# define SAM_IRQ_EXTINT0 (SAM_IRQ_NIRQS+0) /* External interrupt 0 */
# define SAM_IRQ_EXTINT1 (SAM_IRQ_NIRQS+1) /* External interrupt 1 */
# define SAM_IRQ_EXTINT2 (SAM_IRQ_NIRQS+2) /* External interrupt 2 */
diff --git a/arch/arm/include/samv7/irq.h b/arch/arm/include/samv7/irq.h
index 4c33f3dbec0bb4b61b846958c7226f274b549b84..eec3d12e054038332fe20043930130db88ed1820 100644
--- a/arch/arm/include/samv7/irq.h
+++ b/arch/arm/include/samv7/irq.h
@@ -58,7 +58,7 @@
/* Common Processor Exceptions (vectors 0-15) */
-#define SAM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+#define SAM_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define SAM_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
diff --git a/arch/arm/include/spinlock.h b/arch/arm/include/spinlock.h
index fbd0e424382e7aff2c0607abe48b3b71cd4e5ec0..16079cc81a333f6fed72d3e7b80662859eb0390f 100644
--- a/arch/arm/include/spinlock.h
+++ b/arch/arm/include/spinlock.h
@@ -44,13 +44,59 @@
# include
#endif /* __ASSEMBLY__ */
+/* Include ARM architecture-specific IRQ definitions (including register
+ * save structure and up_irq_save()/up_irq_restore() functions)
+ */
+
+#if defined(CONFIG_ARCH_CORTEXA5) || defined(CONFIG_ARCH_CORTEXA8) || \
+ defined(CONFIG_ARCH_CORTEXA9)
+# include
+#elif defined(CONFIG_ARCH_CORTEXR4) || defined(CONFIG_ARCH_CORTEXR4F) || \
+ defined(CONFIG_ARCH_CORTEXR5) || defined(CONFIG_ARCH_CORTEXR5F) || \
+ defined(CONFIG_ARCH_CORTEXR7) || defined(CONFIG_ARCH_CORTEXR7F)
+# include
+#elif defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4) || \
+ defined(CONFIG_ARCH_CORTEXM7)
+# include
+#elif defined(CONFIG_ARCH_CORTEXM0)
+# include
+#else
+# include
+#endif
+
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
+/* Spinlock states */
+
#define SP_UNLOCKED 0 /* The Un-locked state */
#define SP_LOCKED 1 /* The Locked state */
+/* Memory barriers for use with NuttX spinlock logic
+ *
+ * Data Memory Barrier (DMB) acts as a memory barrier. It ensures that all
+ * explicit memory accesses that appear in program order before the DMB
+ * instruction are observed before any explicit memory accesses that appear
+ * in program order after the DMB instruction. It does not affect the
+ * ordering of any other instructions executing on the processor
+ *
+ * dmb st - Data memory barrier. Wait for stores to complete.
+ *
+ * Data Synchronization Barrier (DSB) acts as a special kind of memory
+ * barrier. No instruction in program order after this instruction executes
+ * until this instruction completes. This instruction completes when: (1) All
+ * explicit memory accesses before this instruction complete, and (2) all
+ * Cache, Branch predictor and TLB maintenance operations before this
+ * instruction complete.
+ *
+ * dsb sy - Data syncrhonization barrier. Assures that the CPU waits until
+ * all memory accesses are complete
+ */
+
+#define SP_DSB(n) __asm__ __volatile__ ("dsb sy" : : : "memory")
+#define SP_DMB(n) __asm__ __volatile__ ("dmb st" : : : "memory")
+
/****************************************************************************
* Public Types
****************************************************************************/
@@ -82,7 +128,7 @@ typedef uint8_t spinlock_t;
* Name: up_testset
*
* Description:
- * Perform and atomic test and set operation on the provided spinlock.
+ * Perform an atomic test and set operation on the provided spinlock.
*
* This function must be provided via the architecture-specific logoic.
*
diff --git a/arch/arm/include/stm32/chip.h b/arch/arm/include/stm32/chip.h
index 98d0073c50617e9ab25a7cb6ddf2e99f0ffb3586..0844c5a09fb5b9d888891b414b79680eafd2b15d 100644
--- a/arch/arm/include/stm32/chip.h
+++ b/arch/arm/include/stm32/chip.h
@@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/include/stm32/chip.h
*
- * Copyright (C) 2009, 2011-2014 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2009, 2011-2014, 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -86,6 +86,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 0 /* No FSMC */
@@ -126,6 +127,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 0 /* No FSMC */
@@ -166,6 +168,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 0 /* No FSMC */
@@ -206,6 +209,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 0 /* No FSMC */
@@ -246,6 +250,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 0 /* No FSMC */
@@ -286,6 +291,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 0 /* No FSMC */
@@ -404,6 +410,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 0 /* No FSMC */
@@ -442,6 +449,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 0 /* FSMC */
@@ -483,6 +491,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 0 /* FSMC */
@@ -522,6 +531,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 1 /* FSMC */
@@ -600,6 +610,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 0 /* FSMC */
@@ -638,6 +649,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 0 /* No FSMC */
@@ -676,6 +688,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 0 /* No FSMC */
@@ -714,6 +727,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 0 /* No FSMC */
@@ -757,6 +771,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 1 /* FSMC */
@@ -798,6 +813,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 1 /* FSMC */
@@ -839,6 +855,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx families */
# define STM32_NFSMC 1 /* FSMC */
@@ -878,6 +895,7 @@
# define CONFIG_STM32_CONNECTIVITYLINE 1 /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 1 /* FSMC */
@@ -903,6 +921,44 @@
# define STM32_NRNG 0 /* No random number generator (RNG) */
# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
+#elif defined(CONFIG_ARCH_CHIP_STM32F105RB)
+# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
+# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
+# define CONFIG_STM32_STM32F10XX 1 /* STM32F10xxx family */
+# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
+# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
+# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
+# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
+# undef CONFIG_STM32_VALUELINE /* STM32F100x */
+# define CONFIG_STM32_CONNECTIVITYLINE 1 /* STM32F105x and STM32F107x */
+# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
+# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
+# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
+# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
+# define STM32_NFSMC 1 /* FSMC */
+# define STM32_NATIM 1 /* One advanced timers TIM1 */
+# define STM32_NGTIM 4 /* 16-bit general timers TIM2-5 with DMA */
+# define STM32_NGTIMNDMA 0 /* No 16-bit general timers without DMA */
+# define STM32_NBTIM 2 /* Two basic timers, TIM6-7 */
+# define STM32_NDMA 2 /* DMA1-2 */
+# define STM32_NSPI 3 /* SPI1-3 */
+# define STM32_NI2S 2 /* I2S1-2 (multiplexed with SPI2-3) */
+# define STM32_NUSART 5 /* USART1-3, UART 4-5 */
+# define STM32_NI2C 2 /* I2C1-2 */
+# define STM32_NCAN 2 /* CAN1-2 */
+# define STM32_NSDIO 0 /* No SDIO */
+# define STM32_NLCD 0 /* No LCD */
+# define STM32_NUSBOTG 1 /* USB OTG FS/HS */
+# define STM32_NGPIO 51 /* GPIOA-E */
+# define STM32_NADC 2 /* ADC1-2 */
+# define STM32_NDAC 2 /* DAC1-2 */
+# define STM32_NCAPSENSE 0 /* No capacitive sensing channels */
+# define STM32_NCRC 1 /* CRC */
+# define STM32_NETHERNET 0 /* 100/100 Ethernet MAC */
+# define STM32_NRNG 0 /* No random number generator (RNG) */
+# define STM32_NDCMI 0 /* No digital camera interface (DCMI) */
+
#elif defined(CONFIG_ARCH_CHIP_STM32F107VC)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
@@ -915,6 +971,7 @@
# define CONFIG_STM32_CONNECTIVITYLINE 1 /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 1 /* FSMC */
@@ -954,6 +1011,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# define CONFIG_STM32_STM32F20XX 1 /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
@@ -992,6 +1050,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# define CONFIG_STM32_STM32F20XX 1 /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 1 /* FSMC */
@@ -1030,6 +1089,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# define CONFIG_STM32_STM32F20XX 1 /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 1 /* FSMC */
@@ -1060,11 +1120,10 @@
/* Part Numbering: STM32Fssscfxxx
*
* Where
- * sss = 302/303 or 372/373
+ * sss = 302/303, 334 or 372/373
* c = C (48pins) R (68 pins) V (100 pins)
* c = K (32 pins), C (48 pins), R (68 pins), V (100 pins)
* f = 6 (32KB FLASH), 8 (64KB FLASH), B (128KB FLASH), C (256KB FLASH)
- * f = 8 (64KB FLASH), B (128KB FLASH), C (256KB FLASH)
* xxx = Package, temperature range, options (ignored here)
*/
@@ -1118,6 +1177,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
@@ -1158,6 +1218,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
@@ -1198,6 +1259,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
@@ -1238,6 +1300,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
@@ -1278,6 +1341,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
@@ -1318,6 +1382,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
@@ -1338,7 +1403,7 @@
# define STM32_NLCD 0 /* (0) No LCD */
# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */
# define STM32_NGPIO 37 /* GPIOA-F */
-# define STM32_NADC 3 /* (3) 12-bit ADC1-3 */
+# define STM32_NADC 4 /* (3) 12-bit ADC1-4 */
# define STM32_NDAC 2 /* (2) 12-bit DAC1-2 */
# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */
# define STM32_NCRC 1 /* (1) CRC calculation unit */
@@ -1358,6 +1423,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
@@ -1378,7 +1444,7 @@
# define STM32_NLCD 0 /* (0) No LCD */
# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */
# define STM32_NGPIO 52 /* GPIOA-F */
-# define STM32_NADC 3 /* (3) 12-bit ADC1-3 */
+# define STM32_NADC 4 /* (3) 12-bit ADC1-4 */
# define STM32_NDAC 2 /* (2) 12-bit DAC1-2 */
# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */
# define STM32_NCRC 1 /* (1) CRC calculation unit */
@@ -1398,6 +1464,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
@@ -1438,6 +1505,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# define CONFIG_STM32_STM32F30XX 1 /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
@@ -1458,7 +1526,7 @@
# define STM32_NLCD 0 /* (0) No LCD */
# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */
# define STM32_NGPIO 87 /* GPIOA-F */
-# define STM32_NADC 3 /* (3) 12-bit ADC1-3 */
+# define STM32_NADC 4 /* (3) 12-bit ADC1-4 */
# define STM32_NDAC 2 /* (2) 12-bit DAC1-2 */
# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */
# define STM32_NCRC 1 /* (1) CRC calculation unit */
@@ -1466,6 +1534,138 @@
# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
+#elif defined(CONFIG_ARCH_CHIP_STM32F334K4) || defined(CONFIG_ARCH_CHIP_STM32F334K6) || defined(CONFIG_ARCH_CHIP_STM32F334K8)
+# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
+# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
+# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
+# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
+# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
+# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
+# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
+# undef CONFIG_STM32_VALUELINE /* STM32F100x */
+# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
+# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
+# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# define CONFIG_STM32_STM32F33XX 1 /* STM32F33xxx family */
+# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
+# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
+# define STM32_NFSMC 0 /* No FSMC */
+
+# define STM32_HRTIM 1 /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */
+# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1*/
+# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3
+ * (1) 32-bit general timers with DMA: TIM2
+ * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
+# define STM32_NGTIMNDMA 0 /* All timers have DMA */
+# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */
+# define STM32_NDMA 1 /* (2) DMA1 (7 channels) */
+# define STM32_NSPI 1 /* (3) SPI1 */
+# define STM32_NI2S 0 /* (0) I2S1 */
+# define STM32_NUSART 2 /* (2) USART1-2 */
+# define STM32_NI2C 1 /* (2) I2C1 */
+# define STM32_NCAN 1 /* (1) CAN1 */
+# define STM32_NSDIO 0 /* (0) No SDIO */
+# define STM32_NLCD 0 /* (0) No LCD */
+# define STM32_NUSBOTG 0 /* (0) No USB */
+# define STM32_NGPIO 25 /* GPIOA-F */
+# define STM32_NADC 2 /* (3) 12-bit ADC1-2 */
+# define STM32_NDAC 2 /* (2) 12-bit DAC1-2 */
+# define STM32_NCMP 2 /* (2) Ultra-fast analog comparators: COMP2 and COMP4 */
+# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */
+# define STM32_NCAPSENSE 14 /* (14) No capacitive sensing channels */
+# define STM32_NCRC 1 /* (1) CRC calculation unit */
+# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */
+# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
+# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
+
+#elif defined(CONFIG_ARCH_CHIP_STM32F334C4) || defined(CONFIG_ARCH_CHIP_STM32F334C6) || defined(CONFIG_ARCH_CHIP_STM32F334C8)
+# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
+# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
+# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
+# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
+# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
+# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
+# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
+# undef CONFIG_STM32_VALUELINE /* STM32F100x */
+# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
+# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
+# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# define CONFIG_STM32_STM32F33XX 1 /* STM32F33xxx family */
+# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
+# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
+# define STM32_NFSMC 0 /* No FSMC */
+
+# define STM32_HRTIM 1 /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */
+# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1*/
+# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3
+ * (1) 32-bit general timers with DMA: TIM2
+ * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
+# define STM32_NGTIMNDMA 0 /* All timers have DMA */
+# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */
+# define STM32_NDMA 1 /* (2) DMA1 (7 channels) */
+# define STM32_NSPI 1 /* (3) SPI1 */
+# define STM32_NI2S 0 /* (0) I2S1 */
+# define STM32_NUSART 3 /* (2) USART1-3 */
+# define STM32_NI2C 1 /* (2) I2C1 */
+# define STM32_NCAN 1 /* (1) CAN1 */
+# define STM32_NSDIO 0 /* (0) No SDIO */
+# define STM32_NLCD 0 /* (0) No LCD */
+# define STM32_NUSBOTG 0 /* (0) No USB */
+# define STM32_NGPIO 37 /* GPIOA-F */
+# define STM32_NADC 3 /* (3) 12-bit ADC1-3 */
+# define STM32_NDAC 2 /* (2) 12-bit DAC1-2 */
+# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6 */
+# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */
+# define STM32_NCAPSENSE 17 /* (17) No capacitive sensing channels */
+# define STM32_NCRC 1 /* (1) CRC calculation unit */
+# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */
+# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
+# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
+
+#elif defined(CONFIG_ARCH_CHIP_STM32F334R4) || defined(CONFIG_ARCH_CHIP_STM32F334R6) || defined(CONFIG_ARCH_CHIP_STM32F334R8)
+# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
+# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite family */
+# undef CONFIG_STM32_STM32F10XX /* STM32F10xxx family */
+# undef CONFIG_STM32_LOWDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
+# undef CONFIG_STM32_MEDIUMDENSITY /* STM32F100x, STM32F101x, STM32F102x and STM32F103x w/ 64/128 Kbytes */
+# undef CONFIG_STM32_MEDIUMPLUSDENSITY /* STM32L15xxC w/ 32/256 Kbytes */
+# undef CONFIG_STM32_HIGHDENSITY /* STM32F100x, STM32F101x, and STM32F103x w/ 256/512 Kbytes */
+# undef CONFIG_STM32_VALUELINE /* STM32F100x */
+# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
+# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
+# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# define CONFIG_STM32_STM32F33XX 1 /* STM32F33xxx family */
+# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
+# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
+# define STM32_NFSMC 0 /* No FSMC */
+
+# define STM32_HRTIM 1 /* (1) High-resolution timer 16-bit, 10 channels: HRTIM1 */
+# define STM32_NATIM 1 /* (1) Advanced 16-bit timers with DMA: TIM1*/
+# define STM32_NGTIM 5 /* (1) 16-bit general timers with DMA: TIM3
+ * (1) 32-bit general timers with DMA: TIM2
+ * (3) 16-bit general timers count-up timers with DMA: TIM15-17 */
+# define STM32_NGTIMNDMA 0 /* All timers have DMA */
+# define STM32_NBTIM 2 /* (2) Basic timers: TIM6 and TIM7 */
+# define STM32_NDMA 1 /* (2) DMA1 (7 channels) */
+# define STM32_NSPI 1 /* (3) SPI1 */
+# define STM32_NI2S 0 /* (0) I2S1 */
+# define STM32_NUSART 3 /* (2) USART1-3 */
+# define STM32_NI2C 1 /* (2) I2C1 */
+# define STM32_NCAN 1 /* (1) CAN1 */
+# define STM32_NSDIO 0 /* (0) No SDIO */
+# define STM32_NLCD 0 /* (0) No LCD */
+# define STM32_NUSBOTG 0 /* (0) No USB */
+# define STM32_NGPIO 51 /* GPIOA-F */
+# define STM32_NADC 3 /* (3) 12-bit ADC1-3 */
+# define STM32_NDAC 2 /* (3) 12-bit DAC1-2 */
+# define STM32_NCMP 3 /* (3) Ultra-fast analog comparators: COMP2, COMP4 and COMP6 */
+# define STM32_NPGA 1 /* (1) Operational amplifiers: OPAMP */
+# define STM32_NCAPSENSE 18 /* (18) No capacitive sensing channels */
+# define STM32_NCRC 1 /* (1) CRC calculation unit */
+# define STM32_NETHERNET 0 /* (0) No Ethernet MAC */
+# define STM32_NRNG 0 /* (0) No random number generator (RNG) */
+# define STM32_NDCMI 0 /* (0) No digital camera interface (DCMI) */
+
#elif defined(CONFIG_ARCH_CHIP_STM32F373C8) || defined(CONFIG_ARCH_CHIP_STM32F373CB) || defined(CONFIG_ARCH_CHIP_STM32F373CC)
# undef CONFIG_STM32_STM32L15XX /* STM32L151xx and STM32L152xx family */
# undef CONFIG_STM32_ENERGYLITE /* STM32L EnergyLite vamily */
@@ -1477,6 +1677,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# define CONFIG_STM32_STM32F37XX 1 /* STM32F37xxx family */
# undef CONFIG_STM32_STM32F40XX /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
@@ -1497,7 +1698,8 @@
# define STM32_NLCD 0 /* (0) No LCD */
# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */
# define STM32_NGPIO 87 /* GPIOA-F */
-# define STM32_NADC 1 /* (3) 12-bit ADC1 */
+# define STM32_NADC 1 /* (1) 12-bit ADC1 */
+# define STM32_NSDADC 3 /* (3) 16-bit SDADC1-3 */
# define STM32_NDAC 2 /* (2) 12-bit DAC1-2 */
# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */
# define STM32_NCRC 1 /* (1) CRC calculation unit */
@@ -1521,6 +1723,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
@@ -1559,6 +1762,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
@@ -1597,6 +1801,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
@@ -1635,6 +1840,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 0 /* No FSMC */
@@ -1673,6 +1879,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 1 /* FSMC */
@@ -1711,6 +1918,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 1 /* FSMC */
@@ -1749,6 +1957,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 1 /* FSMC */
@@ -1787,6 +1996,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 1 /* FSMC */
@@ -1825,6 +2035,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 1 /* FSMC */
@@ -1863,6 +2074,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 1 /* FSMC */
@@ -1901,6 +2113,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 1 /* FSMC */
@@ -1939,6 +2152,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx and STM32407xx */
# define STM32_NFSMC 1 /* FSMC */
@@ -1977,6 +2191,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */
# define STM32_NFSMC 1 /* FSMC */
@@ -2015,6 +2230,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */
# define STM32_NFSMC 1 /* FSMC */
@@ -2053,6 +2269,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */
# define STM32_NFSMC 1 /* FSMC */
@@ -2091,6 +2308,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */
# define STM32_NFSMC 1 /* FSMC */
@@ -2129,6 +2347,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437/429/439 */
# define STM32_NFSMC 1 /* FSMC */
@@ -2167,6 +2386,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */
# define STM32_NFSMC 1 /* FSMC */
@@ -2205,6 +2425,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 STM32F466 */
# define STM32_NFSMC 0 /* FSMC */
@@ -2243,6 +2464,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 STM32F466 */
# define STM32_NFSMC 0 /* FSMC */
@@ -2281,6 +2503,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 STM32F466 */
# define STM32_NFSMC 1 /* FSMC */
@@ -2319,6 +2542,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 STM32F466 */
# define STM32_NFSMC 1 /* FSMC */
@@ -2357,6 +2581,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */
# define STM32_NFSMC 1 /* FSMC */
@@ -2398,6 +2623,7 @@
# undef CONFIG_STM32_CONNECTIVITYLINE /* STM32F105x and STM32F107x */
# undef CONFIG_STM32_STM32F20XX /* STM32F205x and STM32F207x */
# undef CONFIG_STM32_STM32F30XX /* STM32F30xxx family */
+# undef CONFIG_STM32_STM32F33XX /* STM32F33xxx family */
# undef CONFIG_STM32_STM32F37XX /* STM32F37xxx family */
# define CONFIG_STM32_STM32F40XX 1 /* STM32F405xx, STM32407xx and STM32F427/437 */
# define STM32_NFSMC 1 /* FSMC */
@@ -2430,7 +2656,7 @@
# if defined(CONFIG_ARCH_CHIP_STM32F469A)
# define STM32_NETHERNET 0 /* No Ethernet MAC */
# elif defined(CONFIG_ARCH_CHIP_STM32F469I) || \
-# defined(CONFIG_ARCH_CHIP_STM32F469B) || \
+ defined(CONFIG_ARCH_CHIP_STM32F469B) || \
defined(CONFIG_ARCH_CHIP_STM32F469N)
# define STM32_NETHERNET 1 /* 100/100 Ethernet MAC */
# endif
diff --git a/arch/arm/include/stm32/dma2d.h b/arch/arm/include/stm32/dma2d.h
index 349944148f93158f1c2b80f11a6187693b2ffd6e..be807de31dca8b917cad700529c7d6da46568c57 100644
--- a/arch/arm/include/stm32/dma2d.h
+++ b/arch/arm/include/stm32/dma2d.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/include/stm32/dma2d.h
+ * arch/arm/include/stm32/dma2d.h
*
* Copyright (C) 2015 Marco Krahl. All rights reserved.
* Author: Marco Krahl
@@ -345,7 +345,7 @@ struct dma2d_layer_s
*
****************************************************************************/
-FAR struct dma2d_layer_s * up_dma2dgetlayer(int lid);
+FAR struct dma2d_layer_s *up_dma2dgetlayer(int lid);
/****************************************************************************
* Name: up_dma2dcreatelayer
diff --git a/arch/arm/include/stm32/irq.h b/arch/arm/include/stm32/irq.h
index 1d57bc3e500147c86db55809a6c4cad1aca92c5e..ed369355a14f5576168ee5be11872976bdd211e0 100644
--- a/arch/arm/include/stm32/irq.h
+++ b/arch/arm/include/stm32/irq.h
@@ -1,7 +1,7 @@
/************************************************************************************
- * arch/arm/include/stm32s/irq.h
+ * arch/arm/include/stm32/irq.h
*
- * Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2009, 2012, 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -59,7 +59,7 @@
/* Processor Exceptions (vectors 0-15) */
-#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
@@ -85,6 +85,8 @@
# include
#elif defined(CONFIG_STM32_STM32F30XX)
# include
+#elif defined(CONFIG_STM32_STM32F33XX)
+# include
#elif defined(CONFIG_STM32_STM32F37XX)
# include
#elif defined(CONFIG_STM32_STM32F40XX)
diff --git a/arch/arm/include/stm32/ltdc.h b/arch/arm/include/stm32/ltdc.h
index 70f978058aa6fa13a6f791c99fb80b6781837272..704b578a9965f4cdd9218f5caddf52bb0a8c74ff 100644
--- a/arch/arm/include/stm32/ltdc.h
+++ b/arch/arm/include/stm32/ltdc.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * arch/arm/src/include/stm32/ltdc.h
+ * arch/arm/include/stm32/ltdc.h
*
* Copyright (C) 2014-2015 Marco Krahl. All rights reserved.
* Author: Marco Krahl
diff --git a/arch/arm/include/stm32/stm32f10xxx_irq.h b/arch/arm/include/stm32/stm32f10xxx_irq.h
index 29f07b0fd8837e37be3182765bbe25130ef752e3..e56df1338e93ae326dcb9e882234ffbad42c2af5 100644
--- a/arch/arm/include/stm32/stm32f10xxx_irq.h
+++ b/arch/arm/include/stm32/stm32f10xxx_irq.h
@@ -1,5 +1,5 @@
/************************************************************************************
- * arch/arm/include/stm32s/stm32f10xxx_irq.h
+ * arch/arm/include/stm32/stm32f10xxx_irq.h
*
* Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -199,7 +199,7 @@
# define STM32_IRQ_ETH (77) /* 61: Ethernet global interrupt */
# define STM32_IRQ_ETHWKUP (78) /* 62: Ethernet Wakeup through EXTI line interrupt */
# define STM32_IRQ_CAN2TX (79) /* 63: CAN2 TX interrupts */
-# define STM32_IRQ_CAN2RX0 (70) /* 64: CAN2 RX0 interrupts */
+# define STM32_IRQ_CAN2RX0 (80) /* 64: CAN2 RX0 interrupts */
# define STM32_IRQ_CAN2RX1 (81) /* 65: CAN2 RX1 interrupt */
# define STM32_IRQ_CAN2SCE (82) /* 66: CAN2 SCE interrupt */
# define STM32_IRQ_OTGFS (83) /* 67: USB On The Go FS global interrupt */
diff --git a/arch/arm/include/stm32/stm32f20xxx_irq.h b/arch/arm/include/stm32/stm32f20xxx_irq.h
index 43a2e218eb9ca9c329692e457834dbbe45b88867..1c5bc9480e15b43b715c5ca3aa4e006eefa63069 100644
--- a/arch/arm/include/stm32/stm32f20xxx_irq.h
+++ b/arch/arm/include/stm32/stm32f20xxx_irq.h
@@ -1,5 +1,5 @@
/****************************************************************************************************
- * arch/arm/include/stm32s/stm32f20xxx_irq.h
+ * arch/arm/include/stm32/stm32f20xxx_irq.h
*
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/arm/include/stm32/stm32f30xxx_irq.h b/arch/arm/include/stm32/stm32f30xxx_irq.h
index 74c8a279a65ecfad11406d4ee14b0b4b57ee416b..f109c8b85d7899cedff414af9c14eb1f958550d3 100644
--- a/arch/arm/include/stm32/stm32f30xxx_irq.h
+++ b/arch/arm/include/stm32/stm32f30xxx_irq.h
@@ -1,5 +1,5 @@
/****************************************************************************************************
- * arch/arm/include/stm32s/stm32f30xxx_irq.h
+ * arch/arm/include/stm32/stm32f30xxx_irq.h
*
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/arm/include/stm32/stm32f33xxx_irq.h b/arch/arm/include/stm32/stm32f33xxx_irq.h
new file mode 100644
index 0000000000000000000000000000000000000000..7170959ec93f8734ec49c4a40e5112b350756941
--- /dev/null
+++ b/arch/arm/include/stm32/stm32f33xxx_irq.h
@@ -0,0 +1,185 @@
+/****************************************************************************************************
+ * arch/arm/include/stm32/stm32f33xxx_irq.h
+ *
+ * Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ * Modified for STM32F334 by Mateusz Szafoni
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly through nuttx/irq.h */
+
+#ifndef __ARCH_ARM_INCLUDE_STM32_STM32F33XXX_IRQ_H
+#define __ARCH_ARM_INCLUDE_STM32_STM32F33XXX_IRQ_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include
+#include
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to
+ * bits in the NVIC. This does, however, waste several words of memory in the IRQ
+ * to handle mapping tables.
+ *
+ * Processor Exceptions (vectors 0-15). These common definitions can be found
+ * in nuttx/arch/arm/include/stm32/irq.h
+ *
+ * External interrupts (vectors >= 16)
+ */
+
+#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
+#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
+#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper interrupt, or */
+#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Time stamp interrupt */
+#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
+#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
+#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
+#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
+#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
+#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt, or */
+#define STM32_IRQ_TSC (STM32_IRQ_FIRST+8) /* 8: TSC interrupt */
+#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
+#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
+#define STM32_IRQ_DMA1CH1 (STM32_IRQ_FIRST+11) /* 11: DMA1 channel 1 global interrupt */
+#define STM32_IRQ_DMA1CH2 (STM32_IRQ_FIRST+12) /* 12: DMA1 channel 2 global interrupt */
+#define STM32_IRQ_DMA1CH3 (STM32_IRQ_FIRST+13) /* 13: DMA1 channel 3 global interrupt */
+#define STM32_IRQ_DMA1CH4 (STM32_IRQ_FIRST+14) /* 14: DMA1 channel 4 global interrupt */
+#define STM32_IRQ_DMA1CH5 (STM32_IRQ_FIRST+15) /* 15: DMA1 channel 5 global interrupt */
+#define STM32_IRQ_DMA1CH6 (STM32_IRQ_FIRST+16) /* 16: DMA1 channel 6 global interrupt */
+#define STM32_IRQ_DMA1CH7 (STM32_IRQ_FIRST+17) /* 17: DMA1 channel 7 global interrupt */
+#define STM32_IRQ_ADC12 (STM32_IRQ_FIRST+18) /* 18: ADC1/ADC2 global interrupt */
+#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
+#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts*/
+#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
+#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
+#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
+#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt, or */
+#define STM32_IRQ_TIM15 (STM32_IRQ_FIRST+24) /* 24: TIM15 global interrupt */
+#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt, or */
+#define STM32_IRQ_TIM16 (STM32_IRQ_FIRST+25) /* 25: TIM16 global interrupt */
+#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts, or */
+#define STM32_IRQ_TIM17 (STM32_IRQ_FIRST+26) /* 26: TIM17 global interrupt */
+#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
+#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
+#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
+#define STM32_IRQ_RESERVED30 (STM32_IRQ_FIRST+30) /* 30: Reserved */
+#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
+#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
+#define STM32_IRQ_RESERVED33 (STM32_IRQ_FIRST+33) /* 33: Reserved */
+#define STM32_IRQ_RESERVED34 (STM32_IRQ_FIRST+34) /* 34: Reserved */
+#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
+#define STM32_IRQ_RESERVED36 (STM32_IRQ_FIRST+36) /* 36: Reserved */
+#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
+#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
+#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
+#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
+#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
+#define STM32_IRQ_RESERVED42 (STM32_IRQ_FIRST+42) /* 42: Reserved */
+#define STM32_IRQ_RESERVED43 (STM32_IRQ_FIRST+43) /* 43: Reserved */
+#define STM32_IRQ_RESERVED44 (STM32_IRQ_FIRST+44) /* 44: Reserved */
+#define STM32_IRQ_RESERVED45 (STM32_IRQ_FIRST+45) /* 45: Reserved */
+#define STM32_IRQ_RESERVED46 (STM32_IRQ_FIRST+46) /* 46: Reserved */
+#define STM32_IRQ_RESERVED47 (STM32_IRQ_FIRST+47) /* 47: Reserved */
+#define STM32_IRQ_RESERVED48 (STM32_IRQ_FIRST+48) /* 48: Reserved */
+#define STM32_IRQ_RESERVED49 (STM32_IRQ_FIRST+49) /* 49: Reserved */
+#define STM32_IRQ_RESERVED50 (STM32_IRQ_FIRST+50) /* 50: Reserved */
+#define STM32_IRQ_RESERVED51 (STM32_IRQ_FIRST+51) /* 51: Reserved */
+#define STM32_IRQ_RESERVED52 (STM32_IRQ_FIRST+52) /* 52: Reserved */
+#define STM32_IRQ_RESERVED53 (STM32_IRQ_FIRST+53) /* 53: Reserved */
+#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt, or */
+#define STM32_IRQ_DAC1 (STM32_IRQ_FIRST+54) /* 54: DAC1 underrun error interrupts */
+#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt, or */
+#define STM32_IRQ_DAC2 (STM32_IRQ_FIRST+54) /* 55: DAC2 underrun error interrupts */
+#define STM32_IRQ_RESERVED56 (STM32_IRQ_FIRST+56) /* 56: Reserved */
+#define STM32_IRQ_RESERVED57 (STM32_IRQ_FIRST+57) /* 57: Reserved */
+#define STM32_IRQ_RESERVED58 (STM32_IRQ_FIRST+58) /* 58: Reserved */
+#define STM32_IRQ_RESERVED59 (STM32_IRQ_FIRST+59) /* 59: Reserved */
+#define STM32_IRQ_RESERVED60 (STM32_IRQ_FIRST+60) /* 60: Reserved */
+#define STM32_IRQ_RESERVED61 (STM32_IRQ_FIRST+61) /* 61: Reserved */
+#define STM32_IRQ_RESERVED62 (STM32_IRQ_FIRST+62) /* 62: Reserved */
+#define STM32_IRQ_RESERVED63 (STM32_IRQ_FIRST+63) /* 63: Reserved */
+#define STM32_IRQ_COMP2 (STM32_IRQ_FIRST+64) /* 64: COMP2 interrupts, or */
+#define STM32_IRQ_EXTI2129 (STM32_IRQ_FIRST+64) /* 64: EXTI Lines 21, 22 and 29 interrupts */
+#define STM32_IRQ_COMP46 (STM32_IRQ_FIRST+65) /* 65: COMP4 & COMP6 interrupts, or */
+#define STM32_IRQ_EXTI3012 (STM32_IRQ_FIRST+65) /* 65: EXTI Lines 30, 31 and 32 interrupts */
+#define STM32_IRQ_RESERVED66 (STM32_IRQ_FIRST+66) /* 66: Reserved */
+#define STM32_IRQ_HRTIMTM (STM32_IRQ_FIRST+67) /* 67: HRTIM master timer interrupt */
+#define STM32_IRQ_HRTIMTA (STM32_IRQ_FIRST+68) /* 68: HRTIM timer A interrupt */
+#define STM32_IRQ_HRTIMTB (STM32_IRQ_FIRST+69) /* 69: HRTIM timer B interrupt */
+#define STM32_IRQ_HRTIMTC (STM32_IRQ_FIRST+70) /* 70: HRTIM timer C interrupt */
+#define STM32_IRQ_HRTIMTD (STM32_IRQ_FIRST+71) /* 71: HRTIM timer D interrupt */
+#define STM32_IRQ_HRTIMTE (STM32_IRQ_FIRST+72) /* 72: HRTIM timer E interrupt */
+#define STM32_IRQ_HRTIMFLT (STM32_IRQ_FIRST+73) /* 73: HRTIM fault interrupt */
+#define STM32_IRQ_RESERVED74 (STM32_IRQ_FIRST+74) /* 74: Reserved */
+#define STM32_IRQ_RESERVED75 (STM32_IRQ_FIRST+75) /* 75: Reserved */
+#define STM32_IRQ_RESERVED76 (STM32_IRQ_FIRST+76) /* 76: Reserved */
+#define STM32_IRQ_RESERVED77 (STM32_IRQ_FIRST+77) /* 77: Reserved */
+#define STM32_IRQ_RESERVED78 (STM32_IRQ_FIRST+78) /* 78: Reserved */
+#define STM32_IRQ_RESERVED79 (STM32_IRQ_FIRST+79) /* 79: Reserved */
+#define STM32_IRQ_RESERVED80 (STM32_IRQ_FIRST+80) /* 80: Reserved */
+#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
+
+#define NR_VECTORS (STM32_IRQ_FIRST+82)
+#define NR_IRQS (STM32_IRQ_FIRST+82)
+
+/****************************************************************************************************
+ * Public Types
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Data
+****************************************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************************************
+ * Public Functions
+ ****************************************************************************************************/
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_STM32F30XXX_IRQ_H */
diff --git a/arch/arm/include/stm32/stm32f37xxx_irq.h b/arch/arm/include/stm32/stm32f37xxx_irq.h
index 22456683bc3bcaae51a78028f9a0395f1d9a6946..4f8a431bf9d3a60650cbbbcaf48c170192d345e6 100644
--- a/arch/arm/include/stm32/stm32f37xxx_irq.h
+++ b/arch/arm/include/stm32/stm32f37xxx_irq.h
@@ -1,5 +1,5 @@
/****************************************************************************************************
- * arch/arm/include/stm32s/stm32f37xxx_irq.h
+ * arch/arm/include/stm32/stm32f37xxx_irq.h
*
* Copyright (C) 2012 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
diff --git a/arch/arm/include/stm32/stm32f40xxx_irq.h b/arch/arm/include/stm32/stm32f40xxx_irq.h
index b0499b6ba32bf3285545fb89bdc95e743345d0d6..64df1a6fe5752554ceb31090e22eaed3b6f3af7d 100644
--- a/arch/arm/include/stm32/stm32f40xxx_irq.h
+++ b/arch/arm/include/stm32/stm32f40xxx_irq.h
@@ -1,5 +1,5 @@
/****************************************************************************************************
- * arch/arm/include/stm32s/stm32f40xxx_irq.h
+ * arch/arm/include/stm32/stm32f40xxx_irq.h
*
* Copyright (C) 2009, 2014-2015 Gregory Nutt. All rights reserved.
* Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved.
diff --git a/arch/arm/include/stm32/stm32l15xxx_irq.h b/arch/arm/include/stm32/stm32l15xxx_irq.h
index ca692932f9be8e49f9be0bc23a7f844a3f4f0bba..d0c1380c8783149d36af1ebb0a6bd741564bffb1 100644
--- a/arch/arm/include/stm32/stm32l15xxx_irq.h
+++ b/arch/arm/include/stm32/stm32l15xxx_irq.h
@@ -1,5 +1,5 @@
/****************************************************************************************************
- * arch/arm/include/stm32s/stm32l15xxx_irq.h
+ * arch/arm/include/stm32/stm32l15xxx_irq.h
* For STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx advanced ARM-based 32-bit MCUs
*
* Copyright (C) 2013 Gregory Nutt. All rights reserved.
diff --git a/arch/arm/include/stm32f7/chip.h b/arch/arm/include/stm32f7/chip.h
index 372bd1143f4529271932312ce75e3bd89919a2f8..b3beb4e09e8697413a363f70b74df38caed19bb9 100644
--- a/arch/arm/include/stm32f7/chip.h
+++ b/arch/arm/include/stm32f7/chip.h
@@ -1,8 +1,9 @@
/************************************************************************************
* arch/arm/include/stm32f7/chip.h
*
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt
+ * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt
+ * David Sidrane
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
@@ -45,99 +46,272 @@
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
-/* STM32F745xx, STM32F746xx, and STM32F56xx. Differences between family members:
- *
- * ----------- ---------------- ----- -------- ------------ --------
- * PART PACKAGE GPIOs SPI/I2S ADC CHANNELS LCD-TFT?
- * ----------- ---------------- ----- -------- ------------ --------
- * STM32F745Vx LQFP100 82 4/3 16 No
- * STM32F745Zx WLCSP143/LQFP144 114 6/3 24 No
- * STM32F745Ix UFBGA176/LQFP176 140 6/3 24 No
- * STM32F745Bx LQFP208 168 6/3 24 No
- * STM32F745Nx TFBGA216 68 6/3 24 No
- *
- * STM32F746Vx LQFP100 82 4/3 16 Yes
- * STM32F746Zx WLCSP143/LQFP144 114 6/3 24 Yes
- * STM32F746Ix UFBGA176/LQFP176 140 6/3 24 Yes
- * STM32F746Bx LQFP208 168 6/3 24 Yes
- * STM32F746Nx TFBGA216 168 6/3 24 Yes
- *
- * STM32F756Vx LQFP100 82 4/3 16 Yes
- * STM32F756Zx WLCSP143/LQFP144 114 6/3 24 Yes
- * STM32F756Ix UFBGA176/LQFP176 140 6/3 24 Yes
- * STM32F756Bx LQFP208 168 6/3 24 Yes
- * STM32F756Nx TFBGA216 168 6/3 24 Yes
- * ----------- ---------------- ----- -------- ------------ --------
+/* STM32F745xx, STM32F746xx, STM32F756xx, STM32F765xx, STM32F767xx, STM32F768xx,
+ * STM32F769xx, STM32F777xx and STM32F779xx Differences between family members:
+ *
+ * ----------- ---------------- ----- ---- ----- ---- ---- ---- ---- ---- ----- ----- ---- ------------ ------
+ * SPI ADC LCD
+ * PART PACKAGE GPIOs I2S CHAN TFT MIPI JPEG CAN ETH DFSDM CRYPTO FPU RAM L1
+ * ----------- ---------------- ----- ---- ----- ---- ---- ---- ---- ---- ----- ----- ---- ------------ ------
+ * STM32F745Vx LQFP100 82 4/3 16 No No No 2 Yes No No SFPU (240+16+64) 4+4
+ * STM32F745Zx WLCSP143/LQFP144 114 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4
+ * STM32F745Ix UFBGA176/LQFP176 140 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4
+ * STM32F745Bx LQFP208 168 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4
+ * STM32F745Nx TFBGA216 68 6/3 24 No No No 2 Yes No No SFPU (240+16+64) 4+4
+ *
+ * STM32F746Vx LQFP100 82 4/3 16 Yes No No 2 Yes No No SFPU (240+16+64) 4+4
+ * STM32F746Zx WLCSP143/LQFP144 114 6/3 24 Yes No No 2 Yes No No SFPU (240+16+64) 4+4
+ * STM32F746Ix UFBGA176/LQFP176 140 6/3 24 Yes No No 2 Yes No No SFPU (240+16+64) 4+4
+ * STM32F746Bx LQFP208 168 6/3 24 Yes No No 2 Yes No No SFPU (240+16+64) 4+4
+ * STM32F746Nx TFBGA216 168 6/3 24 Yes No No 2 Yes No No SFPU
+ *
+ * STM32F756Vx LQFP100 82 4/3 16 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4
+ * STM32F756Zx WLCSP143/LQFP144 114 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4
+ * STM32F756Ix UFBGA176/LQFP176 140 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4
+ * STM32F756Bx LQFP208 168 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4
+ * STM32F756Nx TFBGA216 168 6/3 24 Yes No No 2 Yes No Yes SFPU (240+16+64) 4+4
+ *
+ * STM32F765Vx LQFP100 82 4/3 16 No No No 3 Yes Yes No DFPU (368+16+128) 16+16
+ * STM32F765Zx WLCSP143/LQFP144 114 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16
+ * STM32F765Ix UFBGA176/LQFP176 140 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16
+ * STM32F765Bx LQFP208 168 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16
+ * STM32F765Nx TFBGA216 168 6/3 24 No No No 3 Yes Yes No DFPU (368+16+128) 16+16
+ *
+ * STM32F767Vx LQFP100 82 4/3 16 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16
+ * STM32F767Zx WLCSP143/LQFP144 114 6/3 24 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16
+ * STM32F767Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
+ * STM32F767Bx LQFP208 168 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
+ * STM32F767Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
+ *
+ * STM32F768Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes No DFPU (368+16+128) 16+16
+ *
+ * STM32F769Vx LQFP100 82 4/3 16 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16
+ * STM32F769Zx LQFP144 114 6/3 24 Yes No Yes 3 Yes Yes No DFPU (368+16+128) 16+16
+ * STM32F769Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
+ * STM32F769Bx LQFP208 168 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
+ * STM32F769Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes No DFPU (368+16+128) 16+16
+ *
+ * STM32F769Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes No DFPU (368+16+128) 16+16
+ *
+ * STM32F777Vx LQFP100 82 4/3 16 Yes No Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
+ * STM32F777Zx LQFP144 114 6/3 24 Yes No Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
+ * STM32F777Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
+ * STM32F777Bx LQFP208 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
+ * STM32F777Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
+ *
+ * STM32F778Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes Yes DFPU (368+16+128) 16+16
+ *
+ * STM32F779Ix UFBGA176/LQFP176 132 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
+ * STM32F779Bx LQFP208 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
+ * STM32F779Nx TFBGA216 159 6/3 24 Yes Yes Yes 3 Yes Yes Yes DFPU (368+16+128) 16+16
+
+ * STM32F779Ax WLCSP180 129 6/3 24 Yes Yes Yes 3 No Yes Yes DFPU (368+16+128) 16+16
+ * ----------- ---------------- ----- ---- ----- ---- ---- ---- ---- ---- ----- ----- ---- ------------ ------
*
* Parts STM32F74xxE have 512Kb of FLASH
* Parts STM32F74xxG have 1024Kb of FLASH
+ * Parts STM32F74xxI have 2048Kb of FLASH
+ *
+ * The correct FLASH size will be set CONFIG_STM32F7_FLASH_CONFIG_x or overridden
+ * with CONFIG_STM32F7_FLASH_OVERRIDE_x
*
- * The correct FLASH size must be set with a CONFIG_STM32F7_FLASH_*KB
- * selection.
*/
+#if defined(CONFIG_ARCH_CHIP_STM32F745VG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F745VE) || \
+ defined(CONFIG_ARCH_CHIP_STM32F745IG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F745IE) || \
+ defined(CONFIG_ARCH_CHIP_STM32F745ZE) || \
+ defined(CONFIG_ARCH_CHIP_STM32F745ZG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F746BG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F746VG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F746VE) || \
+ defined(CONFIG_ARCH_CHIP_STM32F746BE) || \
+ defined(CONFIG_ARCH_CHIP_STM32F746ZG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F746IE) || \
+ defined(CONFIG_ARCH_CHIP_STM32F746NG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F746NE) || \
+ defined(CONFIG_ARCH_CHIP_STM32F746ZE) || \
+ defined(CONFIG_ARCH_CHIP_STM32F746IG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F756NG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F756BG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F756IG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F756VG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F756ZG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F765NI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F765VI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F765VG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F765BI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F765NG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F765ZG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F765ZI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F765IG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F765BG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F765II) || \
+ defined(CONFIG_ARCH_CHIP_STM32F767NG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F767IG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F767VG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F767ZG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F767NI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F767VI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F767BG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F767ZI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F767II) || \
+ defined(CONFIG_ARCH_CHIP_STM32F769BI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F769II) || \
+ defined(CONFIG_ARCH_CHIP_STM32F769BG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F769NI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F769AI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F769NG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F769IG) || \
+ defined(CONFIG_ARCH_CHIP_STM32F777ZI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F777VI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F777NI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F777BI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F777II) || \
+ defined(CONFIG_ARCH_CHIP_STM32F778AI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F779II) || \
+ defined(CONFIG_ARCH_CHIP_STM32F779NI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F779BI) || \
+ defined(CONFIG_ARCH_CHIP_STM32F779AI)
+#else
+# error STM32 F7 chip not identified
+#endif
-#if defined(CONFIG_ARCH_CHIP_STM32F745) || defined(CONFIG_ARCH_CHIP_STM32F746) || \
- defined(CONFIG_ARCH_CHIP_STM32F756)
-
-#if defined(CONFIG_ARCH_CHIP_STM32F745)
-# define STM32F7_STM32F745XX 1 /* STM32F745xx family */
-# undef STM32F7_STM32F746XX /* Not STM32F746xx family */
-# undef STM32F7_STM32F756XX /* Not STM32F756xx family */
-
-# define STM32F7_NLCDTFT 0 /* No LCD-TFT */
-
-#elif defined(CONFIG_ARCH_CHIP_STM32F746)
-
-# undef STM32F7_STM32F745XX /* Not STM32F745xx family */
-# define STM32F7_STM32F746XX 1 /* STM32F746xx family */
-# undef STM32F7_STM32F756XX /* Not STM32F756xx family */
-
-# define STM32F7_NLCDTFT 1 /* One LCD-TFT */
-
-#else /* if defined(CONFIG_ARCH_CHIP_STM32F746) */
-
-# undef STM32F7_STM32F745XX /* Not STM32F745xx family */
-# undef STM32F7_STM32F746XX /* Not STM32F746xx family */
-# define STM32F7_STM32F756XX 1 /* STM32F756xx family */
+/* Size SRAM */
-# define STM32F7_NLCDTFT 1 /* One LCD-TFT */
+#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
+# define STM32F7_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */
+# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
+# if defined(CONFIG_ARMV7M_HAVE_DTCM)
+# define STM32F7_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM interface */
+# else
+# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */
+# endif
+# if defined(CONFIG_ARMV7M_HAVE_ITCM)
+# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */
+# else
+# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */
+# endif
+#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77X)
+# define STM32F7_SRAM1_SIZE (368*1024) /* 368Kb SRAM1 on AHB bus Matrix */
+# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
+# if defined(CONFIG_ARMV7M_HAVE_DTCM)
+# define STM32F7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */
+# else
+# define STM32F7_DTCM_SRAM_SIZE (0) /* No DTCM SRAM on TCM interface */
+# endif
+# if defined(CONFIG_ARMV7M_HAVE_ITCM)
+# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM interface */
+# else
+# define STM32F7_ITCM_SRAM_SIZE (0) /* No ITCM SRAM on TCM interface */
+# endif
+#else
+# error STM32 F7 chip Family not identified
#endif
-# define STM32F7_SRAM1_SIZE (240*1024) /* 240Kb SRAM1 on AHB bus Matrix */
-# define STM32F7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix */
-# define STM32F7_DTCM_SRAM_SIZE (64*1024) /* 64Kb DTCM SRAM on TCM inerface */
-# define STM32F7_ITCM_SRAM_SIZE (16*1024) /* 16Kb ITCM SRAM on TCM inerface */
+/* Common to all Family members */
-# define STM32F7_NFSMC 1 /* Have FSMC memory controller */
-# define STM32F7_NETHERNET 1 /* 100/100 Ethernet MAC */
# define STM32F7_NATIM 2 /* Two advanced timers TIM1 and 8 */
# define STM32F7_NGTIM32 2 /* 32-bit general timers TIM2 and 5 with DMA */
# define STM32F7_NGTIM16 2 /* 16-bit general timers TIM3 and 4 with DMA */
# define STM32F7_NGTIMNDMA 6 /* 16-bit general timers TIM9-14 without DMA */
# define STM32F7_NBTIM 2 /* Two basic timers, TIM6-7 */
-# define STM32F7_NRNG 1 /* Random number generator (RNG) */
# define STM32F7_NUART 4 /* UART 4-5 and 7-8 */
# define STM32F7_NUSART 4 /* USART1-3 and 6 */
-# define STM32F7_NSPI 6 /* SPI1-6 (Except V series) */
# define STM32F7_NI2S 3 /* I2S1-2 (multiplexed with SPI1-3) */
# define STM32F7_NI2C 4 /* I2C1-4 */
# define STM32F7_NUSBOTGFS 1 /* USB OTG FS */
# define STM32F7_NUSBOTGHS 1 /* USB OTG HS */
-# define STM32F7_NCAN 2 /* CAN1-2 */
# define STM32F7_NSAI 2 /* SAI1-2 */
# define STM32F7_NSPDIFRX 4 /* 4 SPDIFRX inputs */
-# define STM32F7_NSDMMC 1 /* SDMMC interface */
-# define STM32F7_NDCMI 1 /* Digital camera interface (DCMI) */
# define STM32F7_NDMA 2 /* DMA1-2 */
-# define STM32F7_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */
# define STM32F7_NGPIO 11 /* 11 GPIO ports, GPIOA-K */
# define STM32F7_NADC 3 /* 12-bit ADC1-3, 24 channels *except V series) */
# define STM32F7_NDAC 2 /* 12-bit DAC1-2 */
# define STM32F7_NCAPSENSE 0 /* No capacitive sensing channels */
# define STM32F7_NCRC 1 /* CRC */
+/* TBD FPU Configuration */
+
+#if defined(CONFIG_ARCH_HAVE_FPU)
#else
-# error STM32 F7 chip not identified
+#endif
+
+#if defined(CONFIG_ARCH_HAVE_DPFPU)
+#else
+#endif
+
+/* Diversification based on Family and package */
+
+#if defined(CONFIG_STM32F7_HAVE_FSMC)
+# define STM32F7_NFSMC 1 /* Have FSMC memory controller */
+#else
+# define STM32F7_NFSMC 0 /* No FSMC memory controller */
+#endif
+#if defined(CONFIG_STM32F7_HAVE_ETHRNET)
+# define STM32F7_NETHERNET 1 /* 100/100 Ethernet MAC */
+#else
+# define STM32F7_NETHERNET 0 /* No 100/100 Ethernet MAC */
+#endif
+#if defined(CONFIG_STM32F7_HAVE_RNG)
+# define STM32F7_NRNG 1 /* Random number generator (RNG) */
+#else
+# define STM32F7_NRNG 0 /* No Random number generator (RNG) */
+#endif
+#if defined(CONFIG_STM32F7_HAVE_SPI5) && defined(CONFIG_STM32F7_HAVE_SPI6)
+# define STM32F7_NSPI 6 /* SPI1-6 (Except V series) */
+#else
+# define STM32F7_NSPI 4 /* SPI1-4 V series */
+#endif
+#if defined(CONFIG_STM32F7_HAVE_SDMMC2)
+# define STM32F7_NSDMMC 2 /* 2 SDMMC interfaces */
+#else
+# define STM32F7_NSDMMC 1 /* 1 SDMMC interface */
+#endif
+#if defined(CONFIG_STM32F7_HAVE_CAN3)
+# define STM32F7_NCAN 3 /* CAN1-3 */
+#else
+# define STM32F7_NCAN 2 /* CAN1-2 */
+#endif
+#if defined(CONFIG_STM32F7_HAVE_DCMI)
+# define STM32F7_NDCMI 1 /* Digital camera interface (DCMI) */
+#else
+# define STM32F7_NDCMI 0 /* No Digital camera interface (DCMI) */
+#endif
+#if defined(CONFIG_STM32F7_HAVE_DSIHOST)
+# define STM32F7_NDSIHOST 1 /* Have MIPI DSI Host */
+#else
+# define STM32F7_NDSIHOST 0 /* No MIPI DSI Host */
+#endif
+#if defined (CONFIG_STM32F7_HAVE_LTDC)
+# define STM32F7_NLCDTFT 1 /* One LCD-TFT */
+#else
+# define STM32F7_NLCDTFT 0 /* No LCD-TFT */
+#endif
+#if defined(CONFIG_STM32F7_HAVE_DMA2D)
+# define STM32F7_NDMA2D 0 /* No DChrom-ART Accelerator™ (DMA2D) */
+#else
+# define STM32F7_NDMA2D 1 /* DChrom-ART Accelerator™ (DMA2D) */
+#endif
+#if defined(CONFIG_STM32F7_HAVE_JPEG)
+#define STM32F7_NJPEG 1 /* One JPEG Converter */
+#else
+#define STM32F7_NJPEG 0 /* No JPEG Converter */
+#endif
+#if defined(CONFIG_STM32F7_HAVE_CRYP)
+#define STM32F7_NCRYP 1 /* One CRYP engine */
+#else
+#define STM32F7_NCRYP 0 /* No CRYP engine */
+#endif
+#if defined(CONFIG_STM32F7_HAVE_HASH)
+#define STM32F7_NHASH 1 /* One HASH engine */
+#else
+#define STM32F7_NHASH 0 /* No HASH engine */
+#endif
+#if defined(CONFIG_STM32F7_HAVE_DFSDM)
+#define STM32F7_NDFSDM 4 /* One set of 4 Digital filters */
+#else
+#define STM32F7_NDFSDM 0 /* No Digital filters */
#endif
/* NVIC priority levels *************************************************************/
diff --git a/arch/arm/include/stm32f7/irq.h b/arch/arm/include/stm32f7/irq.h
index 5a5c710803668cca2b371ceaca5c60d89b510c5a..f09659190b74a2f4078b0c0df1f5f31cbcfe2389 100644
--- a/arch/arm/include/stm32f7/irq.h
+++ b/arch/arm/include/stm32f7/irq.h
@@ -57,7 +57,7 @@
/* Processor Exceptions (vectors 0-15) */
-#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+#define STM32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define STM32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
@@ -78,6 +78,8 @@
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
# include
+#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
+# include
#else
# error "Unsupported STM32 F7 chip"
#endif
diff --git a/arch/arm/include/stm32f7/stm32f76xx77xx_irq.h b/arch/arm/include/stm32f7/stm32f76xx77xx_irq.h
new file mode 100644
index 0000000000000000000000000000000000000000..6c0461f9ef22bb07ef8381ebdcb1cc86c28eaee8
--- /dev/null
+++ b/arch/arm/include/stm32f7/stm32f76xx77xx_irq.h
@@ -0,0 +1,215 @@
+/****************************************************************************************************
+ * arch/arm/include/stm32f7/stm32f76xx77xx_irq.h.h
+ *
+ * Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ * Authors: Gregory Nutt
+ * David Sidrane
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+/* This file should never be included directed but, rather, only indirectly through arch/irq.h */
+
+#ifndef __ARCH_ARM_INCLUDE_STM32F7_STM32F76XX77XX_IRQ_H
+#define __ARCH_ARM_INCLUDE_STM32F7_STM32F76XX77XX_IRQ_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+#include
+
+/****************************************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************************************/
+
+/* IRQ numbers. The IRQ number corresponds vector number and hence map directly to bits in the
+ * NVIC. This does, however, waste several words of memory in the IRQ to handle mapping tables.
+ *
+ * Processor Exceptions (vectors 0-15). These common definitions can be found in the file
+ * nuttx/arch/arm/include/stm32f7/irq.h which includes this file
+ *
+ * External interrupts (vectors >= 16)
+ */
+
+#define STM32_IRQ_WWDG (STM32_IRQ_FIRST+0) /* 0: Window Watchdog interrupt */
+#define STM32_IRQ_PVD (STM32_IRQ_FIRST+1) /* 1: PVD through EXTI Line detection interrupt */
+#define STM32_IRQ_TAMPER (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
+#define STM32_IRQ_TIMESTAMP (STM32_IRQ_FIRST+2) /* 2: Tamper and time stamp interrupts */
+#define STM32_IRQ_RTC_WKUP (STM32_IRQ_FIRST+3) /* 3: RTC global interrupt */
+#define STM32_IRQ_FLASH (STM32_IRQ_FIRST+4) /* 4: Flash global interrupt */
+#define STM32_IRQ_RCC (STM32_IRQ_FIRST+5) /* 5: RCC global interrupt */
+#define STM32_IRQ_EXTI0 (STM32_IRQ_FIRST+6) /* 6: EXTI Line 0 interrupt */
+#define STM32_IRQ_EXTI1 (STM32_IRQ_FIRST+7) /* 7: EXTI Line 1 interrupt */
+#define STM32_IRQ_EXTI2 (STM32_IRQ_FIRST+8) /* 8: EXTI Line 2 interrupt */
+#define STM32_IRQ_EXTI3 (STM32_IRQ_FIRST+9) /* 9: EXTI Line 3 interrupt */
+#define STM32_IRQ_EXTI4 (STM32_IRQ_FIRST+10) /* 10: EXTI Line 4 interrupt */
+#define STM32_IRQ_DMA1S0 (STM32_IRQ_FIRST+11) /* 11: DMA1 Stream 0 global interrupt */
+#define STM32_IRQ_DMA1S1 (STM32_IRQ_FIRST+12) /* 12: DMA1 Stream 1 global interrupt */
+#define STM32_IRQ_DMA1S2 (STM32_IRQ_FIRST+13) /* 13: DMA1 Stream 2 global interrupt */
+#define STM32_IRQ_DMA1S3 (STM32_IRQ_FIRST+14) /* 14: DMA1 Stream 3 global interrupt */
+#define STM32_IRQ_DMA1S4 (STM32_IRQ_FIRST+15) /* 15: DMA1 Stream 4 global interrupt */
+#define STM32_IRQ_DMA1S5 (STM32_IRQ_FIRST+16) /* 16: DMA1 Stream 5 global interrupt */
+#define STM32_IRQ_DMA1S6 (STM32_IRQ_FIRST+17) /* 17: DMA1 Stream 6 global interrupt */
+#define STM32_IRQ_ADC (STM32_IRQ_FIRST+18) /* 18: ADC1, ADC2, and ADC3 global interrupt */
+#define STM32_IRQ_CAN1TX (STM32_IRQ_FIRST+19) /* 19: CAN1 TX interrupts */
+#define STM32_IRQ_CAN1RX0 (STM32_IRQ_FIRST+20) /* 20: CAN1 RX0 interrupts */
+#define STM32_IRQ_CAN1RX1 (STM32_IRQ_FIRST+21) /* 21: CAN1 RX1 interrupt */
+#define STM32_IRQ_CAN1SCE (STM32_IRQ_FIRST+22) /* 22: CAN1 SCE interrupt */
+#define STM32_IRQ_EXTI95 (STM32_IRQ_FIRST+23) /* 23: EXTI Line[9:5] interrupts */
+#define STM32_IRQ_TIM1BRK (STM32_IRQ_FIRST+24) /* 24: TIM1 Break interrupt */
+#define STM32_IRQ_TIM9 (STM32_IRQ_FIRST+24) /* 24: TIM9 global interrupt */
+#define STM32_IRQ_TIM1UP (STM32_IRQ_FIRST+25) /* 25: TIM1 Update interrupt */
+#define STM32_IRQ_TIM10 (STM32_IRQ_FIRST+25) /* 25: TIM10 global interrupt */
+#define STM32_IRQ_TIM1TRGCOM (STM32_IRQ_FIRST+26) /* 26: TIM1 Trigger and Commutation interrupts */
+#define STM32_IRQ_TIM11 (STM32_IRQ_FIRST+26) /* 26: TIM11 global interrupt */
+#define STM32_IRQ_TIM1CC (STM32_IRQ_FIRST+27) /* 27: TIM1 Capture Compare interrupt */
+#define STM32_IRQ_TIM2 (STM32_IRQ_FIRST+28) /* 28: TIM2 global interrupt */
+#define STM32_IRQ_TIM3 (STM32_IRQ_FIRST+29) /* 29: TIM3 global interrupt */
+#define STM32_IRQ_TIM4 (STM32_IRQ_FIRST+30) /* 30: TIM4 global interrupt */
+#define STM32_IRQ_I2C1EV (STM32_IRQ_FIRST+31) /* 31: I2C1 event interrupt */
+#define STM32_IRQ_I2C1ER (STM32_IRQ_FIRST+32) /* 32: I2C1 error interrupt */
+#define STM32_IRQ_I2C2EV (STM32_IRQ_FIRST+33) /* 33: I2C2 event interrupt */
+#define STM32_IRQ_I2C2ER (STM32_IRQ_FIRST+34) /* 34: I2C2 error interrupt */
+#define STM32_IRQ_SPI1 (STM32_IRQ_FIRST+35) /* 35: SPI1 global interrupt */
+#define STM32_IRQ_SPI2 (STM32_IRQ_FIRST+36) /* 36: SPI2 global interrupt */
+#define STM32_IRQ_USART1 (STM32_IRQ_FIRST+37) /* 37: USART1 global interrupt */
+#define STM32_IRQ_USART2 (STM32_IRQ_FIRST+38) /* 38: USART2 global interrupt */
+#define STM32_IRQ_USART3 (STM32_IRQ_FIRST+39) /* 39: USART3 global interrupt */
+#define STM32_IRQ_EXTI1510 (STM32_IRQ_FIRST+40) /* 40: EXTI Line[15:10] interrupts */
+#define STM32_IRQ_RTCALRM (STM32_IRQ_FIRST+41) /* 41: RTC alarm through EXTI line interrupt */
+#define STM32_IRQ_OTGFSWKUP (STM32_IRQ_FIRST+42) /* 42: USB On-The-Go FS Wakeup through EXTI line interrupt */
+#define STM32_IRQ_TIM8BRK (STM32_IRQ_FIRST+43) /* 43: TIM8 Break interrupt */
+#define STM32_IRQ_TIM12 (STM32_IRQ_FIRST+43) /* 43: TIM12 global interrupt */
+#define STM32_IRQ_TIM8UP (STM32_IRQ_FIRST+44) /* 44: TIM8 Update interrupt */
+#define STM32_IRQ_TIM13 (STM32_IRQ_FIRST+44) /* 44: TIM13 global interrupt */
+#define STM32_IRQ_TIM8TRGCOM (STM32_IRQ_FIRST+45) /* 45: TIM8 Trigger and Commutation interrupts */
+#define STM32_IRQ_TIM14 (STM32_IRQ_FIRST+45) /* 45: TIM14 global interrupt */
+#define STM32_IRQ_TIM8CC (STM32_IRQ_FIRST+46) /* 46: TIM8 Capture Compare interrupt */
+#define STM32_IRQ_DMA1S7 (STM32_IRQ_FIRST+47) /* 47: DMA1 Stream 7 global interrupt */
+#define STM32_IRQ_FSMC (STM32_IRQ_FIRST+48) /* 48: FSMC global interrupt */
+#define STM32_IRQ_SDMMC1 (STM32_IRQ_FIRST+49) /* 49: SDMMC1 global interrupt */
+#define STM32_IRQ_TIM5 (STM32_IRQ_FIRST+50) /* 50: TIM5 global interrupt */
+#define STM32_IRQ_SPI3 (STM32_IRQ_FIRST+51) /* 51: SPI3 global interrupt */
+#define STM32_IRQ_UART4 (STM32_IRQ_FIRST+52) /* 52: UART4 global interrupt */
+#define STM32_IRQ_UART5 (STM32_IRQ_FIRST+53) /* 53: UART5 global interrupt */
+#define STM32_IRQ_TIM6 (STM32_IRQ_FIRST+54) /* 54: TIM6 global interrupt */
+#define STM32_IRQ_DAC (STM32_IRQ_FIRST+54) /* 54: DAC1 and DAC2 underrun error interrupts */
+#define STM32_IRQ_TIM7 (STM32_IRQ_FIRST+55) /* 55: TIM7 global interrupt */
+#define STM32_IRQ_DMA2S0 (STM32_IRQ_FIRST+56) /* 56: DMA2 Stream 0 global interrupt */
+#define STM32_IRQ_DMA2S1 (STM32_IRQ_FIRST+57) /* 57: DMA2 Stream 1 global interrupt */
+#define STM32_IRQ_DMA2S2 (STM32_IRQ_FIRST+58) /* 58: DMA2 Stream 2 global interrupt */
+#define STM32_IRQ_DMA2S3 (STM32_IRQ_FIRST+59) /* 59: DMA2 Stream 3 global interrupt */
+#define STM32_IRQ_DMA2S4 (STM32_IRQ_FIRST+60) /* 60: DMA2 Stream 4 global interrupt */
+#define STM32_IRQ_ETH (STM32_IRQ_FIRST+61) /* 61: Ethernet global interrupt */
+#define STM32_IRQ_ETHWKUP (STM32_IRQ_FIRST+62) /* 62: Ethernet Wakeup through EXTI line interrupt */
+#define STM32_IRQ_CAN2TX (STM32_IRQ_FIRST+63) /* 63: CAN2 TX interrupts */
+#define STM32_IRQ_CAN2RX0 (STM32_IRQ_FIRST+64) /* 64: CAN2 RX0 interrupts */
+#define STM32_IRQ_CAN2RX1 (STM32_IRQ_FIRST+65) /* 65: CAN2 RX1 interrupt */
+#define STM32_IRQ_CAN2SCE (STM32_IRQ_FIRST+66) /* 66: CAN2 SCE interrupt */
+#define STM32_IRQ_OTGFS (STM32_IRQ_FIRST+67) /* 67: USB On The Go FS global interrupt */
+#define STM32_IRQ_DMA2S5 (STM32_IRQ_FIRST+68) /* 68: DMA2 Stream 5 global interrupt */
+#define STM32_IRQ_DMA2S6 (STM32_IRQ_FIRST+69) /* 69: DMA2 Stream 6 global interrupt */
+#define STM32_IRQ_DMA2S7 (STM32_IRQ_FIRST+70) /* 70: DMA2 Stream 7 global interrupt */
+#define STM32_IRQ_USART6 (STM32_IRQ_FIRST+71) /* 71: USART6 global interrupt */
+#define STM32_IRQ_I2C3EV (STM32_IRQ_FIRST+72) /* 72: I2C3 event interrupt */
+#define STM32_IRQ_I2C3ER (STM32_IRQ_FIRST+73) /* 73: I2C3 error interrupt */
+#define STM32_IRQ_OTGHSEP1OUT (STM32_IRQ_FIRST+74) /* 74: USB On The Go HS End Point 1 Out global interrupt */
+#define STM32_IRQ_OTGHSEP1IN (STM32_IRQ_FIRST+75) /* 75: USB On The Go HS End Point 1 In global interrupt */
+#define STM32_IRQ_OTGHSWKUP (STM32_IRQ_FIRST+76) /* 76: USB On The Go HS Wakeup through EXTI interrupt */
+#define STM32_IRQ_OTGHS (STM32_IRQ_FIRST+77) /* 77: USB On The Go HS global interrupt */
+#define STM32_IRQ_DCMI (STM32_IRQ_FIRST+78) /* 78: DCMI global interrupt */
+#define STM32_IRQ_CRYP (STM32_IRQ_FIRST+79) /* 79: CRYP crypto global interrupt */
+#define STM32_IRQ_HASH (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
+#define STM32_IRQ_RNG (STM32_IRQ_FIRST+80) /* 80: Hash and Rng global interrupt */
+#define STM32_IRQ_FPU (STM32_IRQ_FIRST+81) /* 81: FPU global interrupt */
+#define STM32_IRQ_UART7 (STM32_IRQ_FIRST+82) /* 82: UART7 global interrupt */
+#define STM32_IRQ_UART8 (STM32_IRQ_FIRST+83) /* 83: UART8 global interrupt */
+#define STM32_IRQ_SPI4 (STM32_IRQ_FIRST+84) /* 84: SPI4 global interrupt */
+#define STM32_IRQ_SPI5 (STM32_IRQ_FIRST+85) /* 85: SPI5 global interrupt */
+#define STM32_IRQ_SPI6 (STM32_IRQ_FIRST+86) /* 86: SPI6 global interrupt */
+#define STM32_IRQ_SAI1 (STM32_IRQ_FIRST+87) /* 87: SAI1 global interrupt */
+#define STM32_IRQ_LTDCINT (STM32_IRQ_FIRST+88) /* 88: LCD-TFT global interrupt */
+#define STM32_IRQ_LTDCERRINT (STM32_IRQ_FIRST+89) /* 89: LCD-TFT global Error interrupt */
+#define STM32_IRQ_DMA2D (STM32_IRQ_FIRST+90) /* 90: DMA2D global interrupt */
+#define STM32_IRQ_SAI2 (STM32_IRQ_FIRST+91) /* 91: SAI2 global interrupt */
+#define STM32_IRQ_QUADSPI (STM32_IRQ_FIRST+92) /* 92: QuadSPI global interrupt */
+#define STM32_IRQ_LPTIMER1 (STM32_IRQ_FIRST+93) /* 93: LP Timer1 global interrupt */
+#define STM32_IRQ_HDMICEC (STM32_IRQ_FIRST+94) /* 94: HDMI-CEC global interrupt */
+#define STM32_IRQ_I2C4EV (STM32_IRQ_FIRST+95) /* 95: I2C4 event interrupt */
+#define STM32_IRQ_I2C4ER (STM32_IRQ_FIRST+96) /* 96: I2C4 Error interrupt */
+#define STM32_IRQ_SPDIFRX (STM32_IRQ_FIRST+97) /* 97: SPDIFRX global interrupt */
+#define STM32_IRQ_DSIHOST (STM32_IRQ_FIRST+98) /* 98: DSI host global interrupt */
+#define STM32_IRQ_DFSDM1FLT0 (STM32_IRQ_FIRST+99) /* 99: DFSDM1 Filter 0 global interrupt */
+#define STM32_IRQ_DFSDM1FLT1 (STM32_IRQ_FIRST+100) /* 100: DFSDM1 Filter 1 global interrupt */
+#define STM32_IRQ_DFSDM1FLT2 (STM32_IRQ_FIRST+101) /* 101: DFSDM1 Filter 2 global interrupt */
+#define STM32_IRQ_DFSDM1FLT3 (STM32_IRQ_FIRST+102) /* 102: DFSDM1 Filter 3 global interrupt */
+#define STM32_IRQ_SDMMC2 (STM32_IRQ_FIRST+103) /* 103: SDMMC2 global interrupt */
+#define STM32_IRQ_CAN3TX (STM32_IRQ_FIRST+104) /* 104: CAN3 TX interrupt */
+#define STM32_IRQ_CAN3RX0 (STM32_IRQ_FIRST+105) /* 105: CAN3 RX0 interrupt */
+#define STM32_IRQ_CAN3RX1 (STM32_IRQ_FIRST+106) /* 106: CAN3 RX1 interrupt */
+#define STM32_IRQ_CAN3SCE (STM32_IRQ_FIRST+107) /* 107: CAN3 SCE interrupt */
+#define STM32_IRQ_JPEG (STM32_IRQ_FIRST+108) /* 108: JPEG global interrupt */
+#define STM32_IRQ_MDIOS (STM32_IRQ_FIRST+109) /* 109: MDIO slave global interrupt */
+
+#define NR_INTERRUPTS 110
+#define NR_VECTORS (STM32_IRQ_FIRST+NR_INTERRUPTS)
+
+/* EXTI interrupts (Do not use IRQ numbers) */
+
+#define NR_IRQS NR_VECTORS
+
+/****************************************************************************************************
+ * Public Types
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Public Data
+ ****************************************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************************************
+ * Public Functions
+ ****************************************************************************************************/
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_ARM_INCLUDE_STM32F7_STM32F76XX77XX_IRQ_H */
diff --git a/arch/arm/include/stm32l4/chip.h b/arch/arm/include/stm32l4/chip.h
index 12d718764060f81070e5897e5b8cd95a2e426531..9d0712b27682037e9224e5f89104edf1259841c9 100644
--- a/arch/arm/include/stm32l4/chip.h
+++ b/arch/arm/include/stm32l4/chip.h
@@ -77,7 +77,7 @@
# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */
# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
# define STM32L4_NRNG 1 /* Random number generator (RNG) */
-# define STM32L4_NUART 4 /* UART 4-5 */
+# define STM32L4_NUART 2 /* UART 4-5 */
# define STM32L4_NUSART 3 /* USART 1-3 */
# define STM32L4_NLPUART 1 /* LPUART 1 */
# define STM32L4_NSPI 3 /* SPI1-3 */
diff --git a/arch/arm/include/stm32l4/irq.h b/arch/arm/include/stm32l4/irq.h
index ebfb22667891d9084a91b3b87ee0afed7db0a55f..89e74c1760bedd01330ff9062de2016f0542782f 100644
--- a/arch/arm/include/stm32l4/irq.h
+++ b/arch/arm/include/stm32l4/irq.h
@@ -57,7 +57,7 @@
/* Processor Exceptions (vectors 0-15) */
-#define STM32L4_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+#define STM32L4_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define STM32L4_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
diff --git a/arch/arm/include/tiva/irq.h b/arch/arm/include/tiva/irq.h
index 17c73a254de4d8f121593187ba0b4c62fad42a41..d6a3216da96da623e67e666ee3a606e9b7ea630b 100644
--- a/arch/arm/include/tiva/irq.h
+++ b/arch/arm/include/tiva/irq.h
@@ -162,7 +162,7 @@
/* Processor Exceptions (vectors 0-15) */
-#define TIVA_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
+#define TIVA_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define TIVA_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
diff --git a/arch/arm/src/a1x/Make.defs b/arch/arm/src/a1x/Make.defs
index f823d5c4e6193f60741acdd0d698d83096dd93bb..7ffb41537e9ea2cdac4c22f0fd332bff095c2302 100644
--- a/arch/arm/src/a1x/Make.defs
+++ b/arch/arm/src/a1x/Make.defs
@@ -59,10 +59,6 @@ CMN_ASRCS += arm_testset.S
CMN_ASRCS += cp15_coherent_dcache.S cp15_invalidate_dcache.S
CMN_ASRCS += cp15_clean_dcache.S cp15_flush_dcache.S cp15_invalidate_dcache_all.S
-ifeq ($(CONFIG_ARCH_MEMCPY),y)
-CMN_ASRCS += arm_memcpy.S
-endif
-
# Common C source files
CMN_CSRCS = up_initialize.c up_idle.c up_interruptcontext.c up_exit.c
@@ -112,9 +108,9 @@ endif
endif
ifeq ($(CONFIG_ELF),y)
-CMN_CSRCS += arm_elf.c arm_coherent_dcache.c
+CMN_CSRCS += arm_coherent_dcache.c
else ifeq ($(CONFIG_MODULE),y)
-CMN_CSRCS += arm_elf.c arm_coherent_dcache.c
+CMN_CSRCS += arm_coherent_dcache.c
endif
ifeq ($(CONFIG_ARCH_FPU),y)
diff --git a/arch/arm/src/a1x/a1x_irq.c b/arch/arm/src/a1x/a1x_irq.c
index 65e18ffd73bb5b9e53291d548221da072f50368f..ecabb5ff4d66b77df5f7bab603d6866da245a18f 100644
--- a/arch/arm/src/a1x/a1x_irq.c
+++ b/arch/arm/src/a1x/a1x_irq.c
@@ -77,7 +77,7 @@ volatile uint32_t *g_current_regs[1];
*
****************************************************************************/
-#if defined(CONFIG_DEBUG_IRQ)
+#if defined(CONFIG_DEBUG_IRQ_INFO)
static void a1x_dumpintc(const char *msg, int irq)
{
irqstate_t flags;
@@ -85,40 +85,42 @@ static void a1x_dumpintc(const char *msg, int irq)
/* Dump some relevant ARMv7 register contents */
flags = enter_critical_section();
- lldbg("ARMv7 (%s, irq=%d):\n", msg, irq);
- lldbg(" CPSR: %08x SCTLR: %08x\n", flags, cp15_rdsctlr());
+
+ irqinfo("ARMv7 (%s, irq=%d):\n", msg, irq);
+ irqinfo(" CPSR: %08x SCTLR: %08x\n", flags, cp15_rdsctlr());
/* Dump all of the (readable) INTC register contents */
- lldbg("INTC (%s, irq=%d):\n", msg, irq);
- lldbg(" VECTOR: %08x BASE: %08x PROTECT: %08x NMICTRL: %08x\n",
- getreg32(A1X_INTC_VECTOR), getreg32(A1X_INTC_BASEADDR),
- getreg32(A1X_INTC_PROTECT), getreg32(A1X_INTC_NMICTRL));
- lldbg(" IRQ PEND: %08x %08x %08x\n",
- getreg32(A1X_INTC_IRQ_PEND0), getreg32(A1X_INTC_IRQ_PEND1),
- getreg32(A1X_INTC_IRQ_PEND2));
- lldbg(" FIQ PEND: %08x %08x %08x\n",
- getreg32(A1X_INTC_FIQ_PEND0), getreg32(A1X_INTC_FIQ_PEND1),
- getreg32(A1X_INTC_FIQ_PEND2));
- lldbg(" SEL: %08x %08x %08x\n",
- getreg32(A1X_INTC_IRQ_SEL0), getreg32(A1X_INTC_IRQ_SEL1),
- getreg32(A1X_INTC_IRQ_SEL2));
- lldbg(" EN: %08x %08x %08x\n",
- getreg32(A1X_INTC_EN0), getreg32(A1X_INTC_EN1),
- getreg32(A1X_INTC_EN2));
- lldbg(" MASK: %08x %08x %08x\n",
- getreg32(A1X_INTC_MASK0), getreg32(A1X_INTC_MASK1),
- getreg32(A1X_INTC_MASK2));
- lldbg(" RESP: %08x %08x %08x\n",
- getreg32(A1X_INTC_RESP0), getreg32(A1X_INTC_RESP1),
- getreg32(A1X_INTC_RESP2));
- lldbg(" FF: %08x %08x %08x\n",
- getreg32(A1X_INTC_FF0), getreg32(A1X_INTC_FF1),
- getreg32(A1X_INTC_FF2));
- lldbg(" PRIO: %08x %08x %08x %08x %08x\n",
- getreg32(A1X_INTC_PRIO0), getreg32(A1X_INTC_PRIO1),
- getreg32(A1X_INTC_PRIO2), getreg32(A1X_INTC_PRIO3),
- getreg32(A1X_INTC_PRIO4));
+ irqinfo("INTC (%s, irq=%d):\n", msg, irq);
+ irqinfo(" VECTOR: %08x BASE: %08x PROTECT: %08x NMICTRL: %08x\n",
+ getreg32(A1X_INTC_VECTOR), getreg32(A1X_INTC_BASEADDR),
+ getreg32(A1X_INTC_PROTECT), getreg32(A1X_INTC_NMICTRL));
+ irqinfo(" IRQ PEND: %08x %08x %08x\n",
+ getreg32(A1X_INTC_IRQ_PEND0), getreg32(A1X_INTC_IRQ_PEND1),
+ getreg32(A1X_INTC_IRQ_PEND2));
+ irqinfo(" FIQ PEND: %08x %08x %08x\n",
+ getreg32(A1X_INTC_FIQ_PEND0), getreg32(A1X_INTC_FIQ_PEND1),
+ getreg32(A1X_INTC_FIQ_PEND2));
+ irqinfo(" SEL: %08x %08x %08x\n",
+ getreg32(A1X_INTC_IRQ_SEL0), getreg32(A1X_INTC_IRQ_SEL1),
+ getreg32(A1X_INTC_IRQ_SEL2));
+ irqinfo(" EN: %08x %08x %08x\n",
+ getreg32(A1X_INTC_EN0), getreg32(A1X_INTC_EN1),
+ getreg32(A1X_INTC_EN2));
+ irqinfo(" MASK: %08x %08x %08x\n",
+ getreg32(A1X_INTC_MASK0), getreg32(A1X_INTC_MASK1),
+ getreg32(A1X_INTC_MASK2));
+ irqinfo(" RESP: %08x %08x %08x\n",
+ getreg32(A1X_INTC_RESP0), getreg32(A1X_INTC_RESP1),
+ getreg32(A1X_INTC_RESP2));
+ irqinfo(" FF: %08x %08x %08x\n",
+ getreg32(A1X_INTC_FF0), getreg32(A1X_INTC_FF1),
+ getreg32(A1X_INTC_FF2));
+ irqinfo(" PRIO: %08x %08x %08x %08x %08x\n",
+ getreg32(A1X_INTC_PRIO0), getreg32(A1X_INTC_PRIO1),
+ getreg32(A1X_INTC_PRIO2), getreg32(A1X_INTC_PRIO3),
+ getreg32(A1X_INTC_PRIO4));
+
leave_critical_section(flags);
}
#else
diff --git a/arch/arm/src/a1x/a1x_serial.c b/arch/arm/src/a1x/a1x_serial.c
index b6e536fdc601ecc0f79ec321a8eeb0f09258f4d4..ec8de5e0090507c7175fe96dd1ed9f423a5c2c61 100644
--- a/arch/arm/src/a1x/a1x_serial.c
+++ b/arch/arm/src/a1x/a1x_serial.c
@@ -93,7 +93,6 @@ struct up_dev_s
uint32_t uartbase; /* Base address of UART registers */
uint32_t baud; /* Configured baud */
uint32_t ier; /* Saved IER value */
- xcpt_t handler; /* UART interrupt handler */
uint8_t irq; /* IRQ associated with this UART */
uint8_t parity; /* 0=none, 1=odd, 2=even */
uint8_t bits; /* Number of bits (7 or 8) */
@@ -108,31 +107,7 @@ static int up_setup(struct uart_dev_s *dev);
static void up_shutdown(struct uart_dev_s *dev);
static int up_attach(struct uart_dev_s *dev);
static void up_detach(struct uart_dev_s *dev);
-static int uart_interrupt(struct uart_dev_s *dev);
-#ifdef CONFIG_A1X_UART0
-static int uart0_interrupt(int irq, void *context);
-#endif
-#ifdef CONFIG_A1X_UART1
-static int uart1_interrupt(int irq, void *context);
-#endif
-#ifdef CONFIG_A1X_UART2
-static int uart2_interrupt(int irq, void *context);
-#endif
-#ifdef CONFIG_A1X_UART3
-static int uart3_interrupt(int irq, void *context);
-#endif
-#ifdef CONFIG_A1X_UART4
-static int uart4_interrupt(int irq, void *context);
-#endif
-#ifdef CONFIG_A1X_UART5
-static int uart5_interrupt(int irq, void *context);
-#endif
-#ifdef CONFIG_A1X_UART6
-static int uart6_interrupt(int irq, void *context);
-#endif
-#ifdef CONFIG_A1X_UART7
-static int uart7_interrupt(int irq, void *context);
-#endif
+static int uart_interrupt(int irq, void *context, void *arg);
static int up_ioctl(struct file *filep, int cmd, unsigned long arg);
static int up_receive(struct uart_dev_s *dev, uint32_t *status);
static void up_rxint(struct uart_dev_s *dev, bool enable);
@@ -214,7 +189,6 @@ static struct up_dev_s g_uart0priv =
{
.uartbase = A1X_UART0_VADDR,
.baud = CONFIG_UART0_BAUD,
- .handler = uart0_interrupt,
.irq = A1X_IRQ_UART0,
.parity = CONFIG_UART0_PARITY,
.bits = CONFIG_UART0_BITS,
@@ -245,7 +219,6 @@ static struct up_dev_s g_uart1priv =
{
.uartbase = A1X_UART1_VADDR,
.baud = CONFIG_UART1_BAUD,
- .handler = uart1_interrupt,
.irq = A1X_IRQ_UART1,
.parity = CONFIG_UART1_PARITY,
.bits = CONFIG_UART1_BITS,
@@ -276,7 +249,6 @@ static struct up_dev_s g_uart2priv =
{
.uartbase = A1X_UART2_VADDR,
.baud = CONFIG_UART2_BAUD,
- .handler = uart2_interrupt,
.irq = A1X_IRQ_UART2,
.parity = CONFIG_UART2_PARITY,
.bits = CONFIG_UART2_BITS,
@@ -307,7 +279,6 @@ static struct up_dev_s g_uart3priv =
{
.uartbase = A1X_UART3_VADDR,
.baud = CONFIG_UART3_BAUD,
- .handler = uart3_interrupt,
.irq = A1X_IRQ_UART3,
.parity = CONFIG_UART3_PARITY,
.bits = CONFIG_UART3_BITS,
@@ -338,7 +309,6 @@ static struct up_dev_s g_uart4priv =
{
.uartbase = A1X_UART4_VADDR,
.baud = CONFIG_UART4_BAUD,
- .handler = uart4_interrupt,
.irq = A1X_IRQ_UART4,
.parity = CONFIG_UART4_PARITY,
.bits = CONFIG_UART4_BITS,
@@ -369,7 +339,6 @@ static struct up_dev_s g_uart5priv =
{
.uartbase = A1X_UART5_VADDR,
.baud = CONFIG_UART5_BAUD,
- .handler = uart5_interrupt,
.irq = A1X_IRQ_UART5,
.parity = CONFIG_UART5_PARITY,
.bits = CONFIG_UART5_BITS,
@@ -400,7 +369,6 @@ static struct up_dev_s g_uart6priv =
{
.uartbase = A1X_UART6_VADDR,
.baud = CONFIG_UART6_BAUD,
- .handler = uart6_interrupt,
.irq = A1X_IRQ_UART6,
.parity = CONFIG_UART6_PARITY,
.bits = CONFIG_UART6_BITS,
@@ -431,7 +399,6 @@ static struct up_dev_s g_uart7priv =
{
.uartbase = A1X_UART7_VADDR,
.baud = CONFIG_UART7_BAUD,
- .handler = uart7_interrupt,
.irq = A1X_IRQ_UART7,
.parity = CONFIG_UART7_PARITY,
.bits = CONFIG_UART7_BITS,
@@ -1068,7 +1035,7 @@ static int up_attach(struct uart_dev_s *dev)
/* Attach and enable the IRQ */
- ret = irq_attach(priv->irq, priv->handler);
+ ret = irq_attach(priv->irq, uart_interrupt, priv);
if (ret == OK)
{
/* Enable the interrupt (RX and TX interrupts are still disabled
@@ -1110,12 +1077,14 @@ static void up_detach(struct uart_dev_s *dev)
*
****************************************************************************/
-static int uart_interrupt(struct uart_dev_s *dev)
+static int uart_interrupt(int irq, void *context, void *arg)
{
- struct up_dev_s *priv;
- uint32_t status;
- int passes;
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
+ struct up_dev_s *priv = (struct up_dev_s *)arg;
+ uint32_t status;
+ int passes;
+ DEBUGASSERT(dev != NULL && dev->priv != NULL);
priv = (struct up_dev_s *)dev->priv;
/* Loop until there are no characters to be transferred or,
@@ -1156,7 +1125,7 @@ static int uart_interrupt(struct uart_dev_s *dev)
/* Read the modem status register (MSR) to clear */
status = up_serialin(priv, A1X_UART_MSR_OFFSET);
- vdbg("MSR: %02x\n", status);
+ _info("MSR: %02x\n", status);
break;
}
@@ -1167,7 +1136,7 @@ static int uart_interrupt(struct uart_dev_s *dev)
/* Read the line status register (LSR) to clear */
status = up_serialin(priv, A1X_UART_LSR_OFFSET);
- vdbg("LSR: %02x\n", status);
+ _info("LSR: %02x\n", status);
break;
}
@@ -1192,7 +1161,7 @@ static int uart_interrupt(struct uart_dev_s *dev)
default:
{
- lldbg("Unexpected IIR: %02x\n", status);
+ _err("ERROR: Unexpected IIR: %02x\n", status);
break;
}
}
@@ -1201,62 +1170,6 @@ static int uart_interrupt(struct uart_dev_s *dev)
return OK;
}
-#ifdef CONFIG_A1X_UART0
-static int uart0_interrupt(int irq, void *context)
-{
- return uart_interrupt(&g_uart0port);
-}
-#endif
-
-#ifdef CONFIG_A1X_UART1
-static int uart1_interrupt(int irq, void *context)
-{
- return uart_interrupt(&g_uart1port);
-}
-#endif
-
-#ifdef CONFIG_A1X_UART2
-static int uart2_interrupt(int irq, void *context)
-{
- return uart_interrupt(&g_uart2port);
-}
-#endif
-
-#ifdef CONFIG_A1X_UART3
-static int uart3_interrupt(int irq, void *context)
-{
- return uart_interrupt(&g_uart3port);
-}
-#endif
-
-#ifdef CONFIG_A1X_UART4
-static int uart4_interrupt(int irq, void *context)
-{
- return uart_interrupt(&g_uart4port);
-}
-#endif
-
-#ifdef CONFIG_A1X_UART5
-static int uart5_interrupt(int irq, void *context)
-{
- return uart_interrupt(&g_uart5port);
-}
-#endif
-
-#ifdef CONFIG_A1X_UART6
-static int uart6_interrupt(int irq, void *context)
-{
- return uart_interrupt(&g_uart6port);
-}
-#endif
-
-#ifdef CONFIG_A1X_UART7
-static int uart7_interrupt(int irq, void *context)
-{
- return uart_interrupt(&g_uart7port);
-}
-#endif
-
/****************************************************************************
* Name: up_ioctl
*
diff --git a/arch/arm/src/a1x/a1x_timerisr.c b/arch/arm/src/a1x/a1x_timerisr.c
index d4e827b13d539f66d2abc929350c460d3dfb6739..d5ef7508f418f5fec56a8e38186fd50cd7234581 100644
--- a/arch/arm/src/a1x/a1x_timerisr.c
+++ b/arch/arm/src/a1x/a1x_timerisr.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/a1x/a1x_timerisr.c
*
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -70,19 +70,11 @@
#define TMR_INTERVAL ((TMR0_CLOCK + (CLK_TCK >> 1)) / CLK_TCK)
/****************************************************************************
- * Private Types
+ * Private Functions
****************************************************************************/
/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Function: up_timerisr
+ * Function: a1x_timerisr
*
* Description:
* The timer ISR will perform a variety of services for various portions
@@ -90,7 +82,7 @@
*
****************************************************************************/
-int up_timerisr(int irq, uint32_t *regs)
+static int a1x_timerisr(int irq, uint32_t *regs, void *arg)
{
/* Only a TIMER0 interrupt is expected here */
@@ -107,7 +99,11 @@ int up_timerisr(int irq, uint32_t *regs)
}
/****************************************************************************
- * Function: up_timer_initialize
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function: arm_timer_initialize
*
* Description:
* This function is called during start-up to initialize
@@ -115,7 +111,7 @@ int up_timerisr(int irq, uint32_t *regs)
*
****************************************************************************/
-void up_timer_initialize(void)
+void arm_timer_initialize(void)
{
uint32_t regval;
@@ -142,7 +138,7 @@ void up_timer_initialize(void)
/* Attach the timer interrupt vector */
- (void)irq_attach(A1X_IRQ_TIMER0, (xcpt_t)up_timerisr);
+ (void)irq_attach(A1X_IRQ_TIMER0, (xcpt_t)a1x_timerisr, NULL);
/* Enable interrupts from the TIMER 0 port */
diff --git a/arch/arm/src/arm/Kconfig b/arch/arm/src/arm/Kconfig
index 53f0958b2e2fd339c6e8097b1a026599c69090c6..4b9ce185510f29490a4adeaeb4beb4b1d5b1cc89 100644
--- a/arch/arm/src/arm/Kconfig
+++ b/arch/arm/src/arm/Kconfig
@@ -7,8 +7,8 @@ comment "ARM Configuration Options"
choice
prompt "Toolchain Selection"
- default ARM_TOOLCHAIN_GNU_EABIW if HOST_WINDOWS
- default ARM_TOOLCHAIN_GNU_EABIL if !HOST_WINDOWS
+ default ARM_TOOLCHAIN_GNU_EABIW if TOOLCHAIN_WINDOWS
+ default ARM_TOOLCHAIN_GNU_EABIL if !TOOLCHAIN_WINDOWS
config ARM_TOOLCHAIN_BUILDROOT
bool "Buildroot (Cygwin or Linux)"
@@ -24,11 +24,11 @@ config ARM_TOOLCHAIN_CODESOURCERYL
config ARM_TOOLCHAIN_CODESOURCERYW
bool "CodeSourcery GNU toolchain under Windows"
- depends on HOST_WINDOWS
+ depends on TOOLCHAIN_WINDOWS
config ARM_TOOLCHAIN_DEVKITARM
bool "devkitARM GNU toolchain"
- depends on HOST_WINDOWS
+ depends on TOOLCHAIN_WINDOWS
config ARM_TOOLCHAIN_GNU_EABIL
bool "Generic GNU EABI toolchain under Linux (or other POSIX environment)"
@@ -38,7 +38,7 @@ config ARM_TOOLCHAIN_GNU_EABIL
config ARM_TOOLCHAIN_GNU_EABIW
bool "Generic GNU EABI toolchain under Windows"
- depends on HOST_WINDOWS
+ depends on TOOLCHAIN_WINDOWS
---help---
This option should work for any modern GNU toolchain (GCC 4.5 or newer)
configured for arm-none-eabi-.
diff --git a/arch/arm/src/arm/up_assert.c b/arch/arm/src/arm/up_assert.c
index 336a76c8613862c4bcea2c7b559eb727c947360e..3d188174b3d3ea661b7d508ef738cbef6fb73761 100644
--- a/arch/arm/src/arm/up_assert.c
+++ b/arch/arm/src/arm/up_assert.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/arm/up_assert.c
*
- * Copyright (C) 2007-2010, 2012-2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2007-2010, 2012-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
#include
@@ -77,23 +66,6 @@
# undef CONFIG_ARCH_USBDUMP
#endif
-/* The following is just intended to keep some ugliness out of the mainline
- * code. We are going to print the task name if:
- *
- * CONFIG_TASK_NAME_SIZE > 0 && <-- The task has a name
- * (defined(CONFIG_DEBUG) || <-- And the debug is enabled (lldbg used)
- * defined(CONFIG_ARCH_STACKDUMP) <-- Or lowsyslog() is used
- */
-
-#undef CONFIG_PRINT_TASKNAME
-#if CONFIG_TASK_NAME_SIZE > 0 && (defined(CONFIG_DEBUG) || defined(CONFIG_ARCH_STACKDUMP))
-# define CONFIG_PRINT_TASKNAME 1
-#endif
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -127,7 +99,7 @@ static void up_stackdump(uint32_t sp, uint32_t stack_base)
for (stack = sp & ~0x1f; stack < stack_base; stack += 32)
{
uint32_t *ptr = (uint32_t *)stack;
- lldbg("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ _alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
stack, ptr[0], ptr[1], ptr[2], ptr[3],
ptr[4], ptr[5], ptr[6], ptr[7]);
}
@@ -154,12 +126,12 @@ static inline void up_registerdump(void)
for (regs = REG_R0; regs <= REG_R15; regs += 8)
{
uint32_t *ptr = (uint32_t *)&CURRENT_REGS[regs];
- lldbg("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ _alert("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs, ptr[0], ptr[1], ptr[2], ptr[3],
ptr[4], ptr[5], ptr[6], ptr[7]);
}
- lldbg("CPSR: %08x\n", CURRENT_REGS[REG_CPSR]);
+ _alert("CPSR: %08x\n", CURRENT_REGS[REG_CPSR]);
}
}
#else
@@ -179,7 +151,7 @@ static int usbtrace_syslog(FAR const char *fmt, ...)
/* Let vsyslog do the real work */
va_start(ap, fmt);
- ret = lowvsyslog(LOG_INFO, fmt, ap);
+ ret = vsyslog(LOG_EMERG, fmt, ap);
va_end(ap);
return ret;
}
@@ -228,12 +200,12 @@ static void up_dumpstate(void)
/* Show interrupt stack info */
- lldbg("sp: %08x\n", sp);
- lldbg("IRQ stack:\n");
- lldbg(" base: %08x\n", istackbase);
- lldbg(" size: %08x\n", istacksize);
+ _alert("sp: %08x\n", sp);
+ _alert("IRQ stack:\n");
+ _alert(" base: %08x\n", istackbase);
+ _alert(" size: %08x\n", istacksize);
#ifdef CONFIG_STACK_COLORATION
- lldbg(" used: %08x\n", up_check_intstack());
+ _alert(" used: %08x\n", up_check_intstack());
#endif
/* Does the current stack pointer lie within the interrupt
@@ -251,24 +223,24 @@ static void up_dumpstate(void)
*/
sp = g_intstackbase;
- lldbg("sp: %08x\n", sp);
+ _alert("sp: %08x\n", sp);
}
/* Show user stack info */
- lldbg("User stack:\n");
- lldbg(" base: %08x\n", ustackbase);
- lldbg(" size: %08x\n", ustacksize);
+ _alert("User stack:\n");
+ _alert(" base: %08x\n", ustackbase);
+ _alert(" size: %08x\n", ustacksize);
#ifdef CONFIG_STACK_COLORATION
- lldbg(" used: %08x\n", up_check_tcbstack(rtcb));
+ _alert(" used: %08x\n", up_check_tcbstack(rtcb));
#endif
#else
- lldbg("sp: %08x\n", sp);
- lldbg("stack base: %08x\n", ustackbase);
- lldbg("stack size: %08x\n", ustacksize);
+ _alert("sp: %08x\n", sp);
+ _alert("stack base: %08x\n", ustackbase);
+ _alert("stack size: %08x\n", ustacksize);
#ifdef CONFIG_STACK_COLORATION
- lldbg("stack used: %08x\n", up_check_tcbstack(rtcb));
+ _alert("stack used: %08x\n", up_check_tcbstack(rtcb));
#endif
#endif
@@ -279,7 +251,7 @@ static void up_dumpstate(void)
if (sp > ustackbase || sp <= ustackbase - ustacksize)
{
#if !defined(CONFIG_ARCH_INTERRUPTSTACK) || CONFIG_ARCH_INTERRUPTSTACK < 4
- lldbg("ERROR: Stack pointer is not within allocated stack\n");
+ _alert("ERROR: Stack pointer is not within allocated stack\n");
#endif
}
else
@@ -339,17 +311,17 @@ static void _up_assert(int errorcode)
void up_assert(const uint8_t *filename, int lineno)
{
-#ifdef CONFIG_PRINT_TASKNAME
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT)
struct tcb_s *rtcb = this_task();
#endif
board_autoled_on(LED_ASSERTION);
-#ifdef CONFIG_PRINT_TASKNAME
- lldbg("Assertion failed at file:%s line: %d task: %s\n",
+#if CONFIG_TASK_NAME_SIZE > 0
+ _alert("Assertion failed at file:%s line: %d task: %s\n",
filename, lineno, rtcb->name);
#else
- lldbg("Assertion failed at file:%s line: %d\n",
+ _alert("Assertion failed at file:%s line: %d\n",
filename, lineno);
#endif
diff --git a/arch/arm/src/arm/up_dataabort.c b/arch/arm/src/arm/up_dataabort.c
index 2ab00b15c9403b3e349288ef734b3c48f68a37f9..318c59232c46ab0464c2a6c3be1ec2885247cdf7 100644
--- a/arch/arm/src/arm/up_dataabort.c
+++ b/arch/arm/src/arm/up_dataabort.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/arm/up_dataabort.c
*
- * Copyright (C) 2007-2011, 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2007-2011, 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
@@ -63,18 +52,6 @@
# include "arm.h"
#endif
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -112,7 +89,6 @@ void up_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr)
* for register dumps and possibly context switching.
*/
-
savestate = (uint32_t *)CURRENT_REGS;
#endif
CURRENT_REGS = regs;
@@ -131,7 +107,7 @@ void up_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr)
* fatal error.
*/
- pglldbg("FSR: %08x FAR: %08x\n", fsr, far);
+ pginfo("FSR: %08x FAR: %08x\n", fsr, far);
if ((fsr & FSR_MASK) != FSR_PAGE)
{
goto segfault;
@@ -142,7 +118,7 @@ void up_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr)
* (It has not yet been saved in the register context save area).
*/
- pgllvdbg("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND);
+ pginfo("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND);
if (far < PG_PAGED_VBASE || far >= PG_PAGED_VEND)
{
goto segfault;
@@ -180,7 +156,7 @@ void up_dataabort(uint32_t *regs, uint32_t far, uint32_t fsr)
segfault:
#endif
- lldbg("Data abort. PC: %08x FAR: %08x FSR: %08x\n", regs[REG_PC], far, fsr);
+ _alert("Data abort. PC: %08x FAR: %08x FSR: %08x\n", regs[REG_PC], far, fsr);
PANIC();
}
@@ -196,7 +172,7 @@ void up_dataabort(uint32_t *regs)
/* Crash -- possibly showing diagnost debug information. */
- lldbg("Data abort. PC: %08x\n", regs[REG_PC]);
+ _alert("Data abort. PC: %08x\n", regs[REG_PC]);
PANIC();
}
diff --git a/arch/arm/src/arm/up_head.S b/arch/arm/src/arm/up_head.S
index 53f94a2e0faf31dd1cb2c73141c0c8c89bfa571f..da317c12f978c740dc6472bdbcdbfb19e7411b4f 100644
--- a/arch/arm/src/arm/up_head.S
+++ b/arch/arm/src/arm/up_head.S
@@ -208,7 +208,7 @@
/* This macro will modify r0, r1, r2 and r14 */
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
.macro showprogress, code
mov r0, #\code
bl up_lowputc
diff --git a/arch/arm/src/arm/up_nommuhead.S b/arch/arm/src/arm/up_nommuhead.S
index 04c5205efe057ee58a52286f961e40e3a65624ad..d8689d85bd6ee0d893a2e8f7040a44422d0787ae 100644
--- a/arch/arm/src/arm/up_nommuhead.S
+++ b/arch/arm/src/arm/up_nommuhead.S
@@ -49,7 +49,7 @@
/* This macro will modify r0, r1, r2 and r14 */
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
.macro showprogress, code
mov r0, #\code
bl up_lowputc
@@ -115,7 +115,7 @@ __start:
bl up_earlyserialinit
#endif
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
mov r0, #'C'
bl up_putc
mov r0, #'\n'
diff --git a/arch/arm/src/arm/up_prefetchabort.c b/arch/arm/src/arm/up_prefetchabort.c
index ed2bfb1bf9db8035dfb43915edf2ca23ad37051a..ab97efd5737264712b8b8e4b20e68e35d7ad9f00 100644
--- a/arch/arm/src/arm/up_prefetchabort.c
+++ b/arch/arm/src/arm/up_prefetchabort.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/arm/up_prefetchabort.c
*
- * Copyright (C) 2007-2011, 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2007-2011, 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
@@ -110,8 +99,8 @@ void up_prefetchabort(uint32_t *regs)
* virtual addresses.
*/
- pglldbg("VADDR: %08x VBASE: %08x VEND: %08x\n",
- regs[REG_PC], PG_PAGED_VBASE, PG_PAGED_VEND);
+ pginfo("VADDR: %08x VBASE: %08x VEND: %08x\n",
+ regs[REG_PC], PG_PAGED_VBASE, PG_PAGED_VEND);
if (regs[REG_R15] >= PG_PAGED_VBASE && regs[REG_R15] < PG_PAGED_VEND)
{
@@ -148,7 +137,7 @@ void up_prefetchabort(uint32_t *regs)
else
#endif
{
- lldbg("Prefetch abort. PC: %08x\n", regs[REG_PC]);
+ _alert("Prefetch abort. PC: %08x\n", regs[REG_PC]);
PANIC();
}
}
diff --git a/arch/arm/src/arm/up_releasepending.c b/arch/arm/src/arm/up_releasepending.c
index 4defb895e00e0398df6d95c135f521300e313211..c0ee7e6e727051e418f6e8638db3f8e9cbafe3ef 100644
--- a/arch/arm/src/arm/up_releasepending.c
+++ b/arch/arm/src/arm/up_releasepending.c
@@ -67,7 +67,7 @@ void up_release_pending(void)
{
struct tcb_s *rtcb = this_task();
- slldbg("From TCB=%p\n", rtcb);
+ sinfo("From TCB=%p\n", rtcb);
/* Merge the g_pendingtasks list into the ready-to-run task list */
diff --git a/arch/arm/src/arm/up_reprioritizertr.c b/arch/arm/src/arm/up_reprioritizertr.c
index 8f6b739d08dc5cb7265c9234dcc93cb9b1faebe1..95679e31dd7276d9b11c1c24d8a8dfa25e7c1e1c 100644
--- a/arch/arm/src/arm/up_reprioritizertr.c
+++ b/arch/arm/src/arm/up_reprioritizertr.c
@@ -95,7 +95,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
struct tcb_s *rtcb = this_task();
bool switch_needed;
- slldbg("TCB=%p PRI=%d\n", tcb, priority);
+ sinfo("TCB=%p PRI=%d\n", tcb, priority);
/* Remove the tcb task from the ready-to-run list.
* sched_removereadytorun will return true if we just
diff --git a/arch/arm/src/arm/up_schedulesigaction.c b/arch/arm/src/arm/up_schedulesigaction.c
index 3972b7792120a9ebe55b3ae569862e5b259c90cd..f6f0c655e8fe2cd623e84ea9e487b6c0af15ac33 100644
--- a/arch/arm/src/arm/up_schedulesigaction.c
+++ b/arch/arm/src/arm/up_schedulesigaction.c
@@ -94,7 +94,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
{
irqstate_t flags;
- sdbg("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
+ sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
/* Make sure that interrupts are disabled */
@@ -108,7 +108,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* being delivered to the currently executing task.
*/
- sdbg("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
+ sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
if (tcb == this_task())
{
diff --git a/arch/arm/src/arm/up_sigdeliver.c b/arch/arm/src/arm/up_sigdeliver.c
index c03511d4df485c2648ae567bcbdb43656196e8d7..29176429f3cecd284f677bb9f74cb46be9570aeb 100644
--- a/arch/arm/src/arm/up_sigdeliver.c
+++ b/arch/arm/src/arm/up_sigdeliver.c
@@ -95,7 +95,7 @@ void up_sigdeliver(void)
board_autoled_on(LED_SIGNAL);
- sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
+ sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
ASSERT(rtcb->xcp.sigdeliver != NULL);
@@ -126,7 +126,7 @@ void up_sigdeliver(void)
* errno that is needed by the user logic (it is probably EINTR).
*/
- sdbg("Resuming\n");
+ sinfo("Resuming\n");
(void)up_irq_save();
rtcb->pterrno = saved_errno;
diff --git a/arch/arm/src/arm/up_syscall.c b/arch/arm/src/arm/up_syscall.c
index 07d8ac26d229a90eff58544e4349008ffde9a7d4..c52b036951920870dff3fc4882d72e63f17a07cb 100644
--- a/arch/arm/src/arm/up_syscall.c
+++ b/arch/arm/src/arm/up_syscall.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/arm/up_syscall.c
*
- * Copyright (C) 2007-2009 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2007-2009, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
@@ -58,22 +47,6 @@
#include "up_arch.h"
#include "up_internal.h"
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * vectors
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -82,8 +55,8 @@
* Name: up_syscall
*
* Description:
- * SWI interrupts will vection here with insn=the SWI
- * instruction and xcp=the interrupt context
+ * SWI interrupts will vector here with insn=the SWI instruction and
+ * xcp=the interrupt context
*
* The handler may get the SWI number be de-referencing
* the return address saved in the xcp and decoding
@@ -93,7 +66,7 @@
void up_syscall(uint32_t *regs)
{
- lldbg("Syscall from 0x%x\n", regs[REG_PC]);
+ _alert("Syscall from 0x%x\n", regs[REG_PC]);
CURRENT_REGS = regs;
PANIC();
}
diff --git a/arch/arm/src/arm/up_undefinedinsn.c b/arch/arm/src/arm/up_undefinedinsn.c
index 99b1e3fc66b1bca83ed545f1f9e6442f24d65ad2..364b072acdef98754b6e72d7921904c05576427b 100644
--- a/arch/arm/src/arm/up_undefinedinsn.c
+++ b/arch/arm/src/arm/up_undefinedinsn.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/arm/up_undefinedinsn.c
*
- * Copyright (C) 2007-2009, 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2007-2009, 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
#include
@@ -58,18 +47,6 @@
#include "up_internal.h"
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -80,7 +57,7 @@
void up_undefinedinsn(uint32_t *regs)
{
- lldbg("Undefined instruction at 0x%x\n", regs[REG_PC]);
+ _alert("Undefined instruction at 0x%x\n", regs[REG_PC]);
CURRENT_REGS = regs;
PANIC();
}
diff --git a/arch/arm/src/armv6-m/Kconfig b/arch/arm/src/armv6-m/Kconfig
index ed8b54a8e1a06c89ed5864f86e1be46649e2df06..ed56bc9a71e7f7b36730fc08ed420fafe6e0d45a 100644
--- a/arch/arm/src/armv6-m/Kconfig
+++ b/arch/arm/src/armv6-m/Kconfig
@@ -7,12 +7,12 @@ comment "ARMV6M Configuration Options"
choice
prompt "Toolchain Selection"
- default ARMV6M_TOOLCHAIN_GNU_EABIW if HOST_WINDOWS
- default ARMV6M_TOOLCHAIN_GNU_EABIL if !HOST_WINDOWS
+ default ARMV6M_TOOLCHAIN_GNU_EABIW if TOOLCHAIN_WINDOWS
+ default ARMV6M_TOOLCHAIN_GNU_EABIL if !TOOLCHAIN_WINDOWS
config ARMV6M_TOOLCHAIN_ATOLLIC
bool "Atollic Lite/Pro for Windows"
- depends on HOST_WINDOWS
+ depends on TOOLCHAIN_WINDOWS
config ARMV6M_TOOLCHAIN_BUILDROOT
bool "Buildroot (Cygwin or Linux)"
@@ -24,7 +24,7 @@ config ARMV6M_TOOLCHAIN_CODEREDL
config ARMV6M_TOOLCHAIN_CODEREDW
bool "CodeRed for Windows"
- depends on HOST_WINDOWS
+ depends on TOOLCHAIN_WINDOWS
config ARMV6M_TOOLCHAIN_CODESOURCERYL
bool "CodeSourcery GNU toolchain under Linux"
@@ -32,11 +32,11 @@ config ARMV6M_TOOLCHAIN_CODESOURCERYL
config ARMV6M_TOOLCHAIN_CODESOURCERYW
bool "CodeSourcery GNU toolchain under Windows"
- depends on HOST_WINDOWS
+ depends on TOOLCHAIN_WINDOWS
config ARMV6M_TOOLCHAIN_DEVKITARM
bool "devkitARM GNU toolchain"
- depends on HOST_WINDOWS
+ depends on TOOLCHAIN_WINDOWS
config ARMV6M_TOOLCHAIN_GNU_EABIL
bool "Generic GNU EABI toolchain under Linux (or other POSIX environment)"
@@ -46,7 +46,7 @@ config ARMV6M_TOOLCHAIN_GNU_EABIL
config ARMV6M_TOOLCHAIN_GNU_EABIW
bool "Generic GNU EABI toolchain under Windows"
- depends on HOST_WINDOWS
+ depends on TOOLCHAIN_WINDOWS
---help---
This option should work for any modern GNU toolchain (GCC 4.5 or newer)
configured for arm-none-eabi.
diff --git a/arch/arm/src/armv6-m/nvic.h b/arch/arm/src/armv6-m/nvic.h
index 945d5c4338f27eddd05964437a3989e5459fbce5..b6f4391a4a68466c299e149d152d83d0ad48f284 100644
--- a/arch/arm/src/armv6-m/nvic.h
+++ b/arch/arm/src/armv6-m/nvic.h
@@ -41,6 +41,7 @@
****************************************************************************************************/
#include
+#include
/****************************************************************************************************
* Pre-processor Definitions
@@ -386,7 +387,7 @@ extern "C"
*
****************************************************************************************************/
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
void up_dumpnvic(FAR const char *msg);
#else
# define up_dumpnvic(m)
diff --git a/arch/arm/src/armv6-m/up_assert.c b/arch/arm/src/armv6-m/up_assert.c
index dcb71392696ac255d524318c661bc8d5c0b136df..f218cd477b028866ec07d179ca4daeedda62f1a7 100644
--- a/arch/arm/src/armv6-m/up_assert.c
+++ b/arch/arm/src/armv6-m/up_assert.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv6-m/up_assert.c
*
- * Copyright (C) 2013-2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013-2015, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
#include
@@ -76,23 +65,6 @@
# undef CONFIG_ARCH_USBDUMP
#endif
-/* The following is just intended to keep some ugliness out of the mainline
- * code. We are going to print the task name if:
- *
- * CONFIG_TASK_NAME_SIZE > 0 && <-- The task has a name
- * (defined(CONFIG_DEBUG) || <-- And the debug is enabled (lldbg used)
- * defined(CONFIG_ARCH_STACKDUMP) <-- Or lowsyslog() is used
- */
-
-#undef CONFIG_PRINT_TASKNAME
-#if CONFIG_TASK_NAME_SIZE > 0 && (defined(CONFIG_DEBUG) || defined(CONFIG_ARCH_STACKDUMP))
-# define CONFIG_PRINT_TASKNAME 1
-#endif
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -126,7 +98,7 @@ static void up_stackdump(uint32_t sp, uint32_t stack_base)
for (stack = sp & ~0x1f; stack < stack_base; stack += 32)
{
uint32_t *ptr = (uint32_t *)stack;
- lldbg("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ _alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
stack, ptr[0], ptr[1], ptr[2], ptr[3],
ptr[4], ptr[5], ptr[6], ptr[7]);
}
@@ -144,12 +116,12 @@ static void up_taskdump(FAR struct tcb_s *tcb, FAR void *arg)
{
/* Dump interesting properties of this task */
-#ifdef CONFIG_PRINT_TASKNAME
- lldbg("%s: PID=%d Stack Used=%lu of %lu\n",
+#if CONFIG_TASK_NAME_SIZE > 0
+ _alert("%s: PID=%d Stack Used=%lu of %lu\n",
tcb->name, tcb->pid, (unsigned long)up_check_tcbstack(tcb),
(unsigned long)tcb->adj_stack_size);
#else
- lldbg("PID: %d Stack Used=%lu of %lu\n",
+ _alert("PID: %d Stack Used=%lu of %lu\n",
tcb->pid, (unsigned long)up_check_tcbstack(tcb),
(unsigned long)tcb->adj_stack_size);
#endif
@@ -184,22 +156,22 @@ static inline void up_registerdump(void)
{
/* Yes.. dump the interrupt registers */
- lldbg("R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ _alert("R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
CURRENT_REGS[REG_R0], CURRENT_REGS[REG_R1],
CURRENT_REGS[REG_R2], CURRENT_REGS[REG_R3],
CURRENT_REGS[REG_R4], CURRENT_REGS[REG_R5],
CURRENT_REGS[REG_R6], CURRENT_REGS[REG_R7]);
- lldbg("R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ _alert("R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
CURRENT_REGS[REG_R8], CURRENT_REGS[REG_R9],
CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
#ifdef CONFIG_BUILD_PROTECTED
- lldbg("xPSR: %08x PRIMASK: %08x EXEC_RETURN: %08x\n",
+ _alert("xPSR: %08x PRIMASK: %08x EXEC_RETURN: %08x\n",
CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK],
CURRENT_REGS[REG_EXC_RETURN]);
#else
- lldbg("xPSR: %08x PRIMASK: %08x\n",
+ _alert("xPSR: %08x PRIMASK: %08x\n",
CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]);
#endif
}
@@ -221,7 +193,7 @@ static int usbtrace_syslog(FAR const char *fmt, ...)
/* Let vsyslog do the real work */
va_start(ap, fmt);
- ret = lowvsyslog(LOG_INFO, fmt, ap);
+ ret = vsyslog(LOG_EMERG, fmt, ap);
va_end(ap);
return ret;
}
@@ -270,12 +242,12 @@ static void up_dumpstate(void)
/* Show interrupt stack info */
- lldbg("sp: %08x\n", sp);
- lldbg("IRQ stack:\n");
- lldbg(" base: %08x\n", istackbase);
- lldbg(" size: %08x\n", istacksize);
+ _alert("sp: %08x\n", sp);
+ _alert("IRQ stack:\n");
+ _alert(" base: %08x\n", istackbase);
+ _alert(" size: %08x\n", istacksize);
#ifdef CONFIG_STACK_COLORATION
- lldbg(" used: %08x\n", up_check_intstack());
+ _alert(" used: %08x\n", up_check_intstack());
#endif
/* Does the current stack pointer lie within the interrupt
@@ -297,14 +269,14 @@ static void up_dumpstate(void)
if (CURRENT_REGS)
{
sp = CURRENT_REGS[REG_R13];
- lldbg("sp: %08x\n", sp);
+ _alert("sp: %08x\n", sp);
}
- lldbg("User stack:\n");
- lldbg(" base: %08x\n", ustackbase);
- lldbg(" size: %08x\n", ustacksize);
+ _alert("User stack:\n");
+ _alert(" base: %08x\n", ustackbase);
+ _alert(" size: %08x\n", ustacksize);
#ifdef CONFIG_STACK_COLORATION
- lldbg(" used: %08x\n", up_check_tcbstack(rtcb));
+ _alert(" used: %08x\n", up_check_tcbstack(rtcb));
#endif
/* Dump the user stack if the stack pointer lies within the allocated user
@@ -317,11 +289,11 @@ static void up_dumpstate(void)
}
#else
- lldbg("sp: %08x\n", sp);
- lldbg("stack base: %08x\n", ustackbase);
- lldbg("stack size: %08x\n", ustacksize);
+ _alert("sp: %08x\n", sp);
+ _alert("stack base: %08x\n", ustackbase);
+ _alert("stack size: %08x\n", ustacksize);
#ifdef CONFIG_STACK_COLORATION
- lldbg("stack used: %08x\n", up_check_tcbstack(rtcb));
+ _alert("stack used: %08x\n", up_check_tcbstack(rtcb));
#endif
/* Dump the user stack if the stack pointer lies within the allocated user
@@ -330,7 +302,7 @@ static void up_dumpstate(void)
if (sp > ustackbase || sp <= ustackbase - ustacksize)
{
- lldbg("ERROR: Stack pointer is not within allocated stack\n");
+ _alert("ERROR: Stack pointer is not within allocated stack\n");
}
else
{
@@ -394,17 +366,17 @@ static void _up_assert(int errorcode)
void up_assert(const uint8_t *filename, int lineno)
{
-#ifdef CONFIG_PRINT_TASKNAME
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT)
struct tcb_s *rtcb = this_task();
#endif
board_autoled_on(LED_ASSERTION);
-#ifdef CONFIG_PRINT_TASKNAME
- lldbg("Assertion failed at file:%s line: %d task: %s\n",
+#if CONFIG_TASK_NAME_SIZE > 0
+ _alert("Assertion failed at file:%s line: %d task: %s\n",
filename, lineno, rtcb->name);
#else
- lldbg("Assertion failed at file:%s line: %d\n",
+ _alert("Assertion failed at file:%s line: %d\n",
filename, lineno);
#endif
diff --git a/arch/arm/src/armv6-m/up_dumpnvic.c b/arch/arm/src/armv6-m/up_dumpnvic.c
index 36c2fdf21682cf9e24b417aa83da5bcd60ae845c..8439ac6a2a91f7005ea86a5fe762fdf560dbce8b 100644
--- a/arch/arm/src/armv6-m/up_dumpnvic.c
+++ b/arch/arm/src/armv6-m/up_dumpnvic.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv6-m/up_dumpnvic.c
*
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -48,19 +48,7 @@
#include "nvic.h"
-#ifdef CONFIG_DEBUG
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
+#ifdef CONFIG_DEBUG_FEATURES
/****************************************************************************
* Public Functions
@@ -76,6 +64,7 @@
void up_dumpnvic(FAR const char *msg)
{
+#ifdef CONFIG_DEBUG_INFO
irqstate_t flags;
int i;
@@ -83,29 +72,30 @@ void up_dumpnvic(FAR const char *msg)
flags = enter_critical_section();
- lldbg("NVIC: %s\n", msg);
- lldbg(" ISER: %08x ICER: %08x ISPR: %08x ICPR: %08x\n",
- getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER),
- getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
+ _info("NVIC: %s\n", msg);
+ _info(" ISER: %08x ICER: %08x ISPR: %08x ICPR: %08x\n",
+ getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER),
+ getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
for (i = 0 ; i < 8; i += 4)
{
- lldbg(" IPR%d: %08x IPR%d: %08x IPR%d: %08x IPR%d: %08x\n",
- i, getreg32(ARMV6M_NVIC_IPR(i)),
- i+1, getreg32(ARMV6M_NVIC_IPR(i+1)),
- i+2, getreg32(ARMV6M_NVIC_IPR(i+2)),
- i+3, getreg32(ARMV6M_NVIC_IPR(i+3)));
+ _info(" IPR%d: %08x IPR%d: %08x IPR%d: %08x IPR%d: %08x\n",
+ i, getreg32(ARMV6M_NVIC_IPR(i)),
+ i+1, getreg32(ARMV6M_NVIC_IPR(i+1)),
+ i+2, getreg32(ARMV6M_NVIC_IPR(i+2)),
+ i+3, getreg32(ARMV6M_NVIC_IPR(i+3)));
}
- lldbg("SYSCON:\n");
- lldbg(" CPUID: %08x ICSR: %08x AIRCR: %08x SCR: %08x\n",
- getreg32(ARMV6M_SYSCON_CPUID), getreg32(ARMV6M_SYSCON_ICSR),
- getreg32(ARMV6M_SYSCON_AIRCR), getreg32(ARMV6M_SYSCON_SCR));
- lldbg(" CCR: %08x SHPR2: %08x SHPR3: %08x\n",
- getreg32(ARMV6M_SYSCON_CCR), getreg32(ARMV6M_SYSCON_SHPR2),
- getreg32(ARMV6M_SYSCON_SHPR3));
+ _info("SYSCON:\n");
+ _info(" CPUID: %08x ICSR: %08x AIRCR: %08x SCR: %08x\n",
+ getreg32(ARMV6M_SYSCON_CPUID), getreg32(ARMV6M_SYSCON_ICSR),
+ getreg32(ARMV6M_SYSCON_AIRCR), getreg32(ARMV6M_SYSCON_SCR));
+ _info(" CCR: %08x SHPR2: %08x SHPR3: %08x\n",
+ getreg32(ARMV6M_SYSCON_CCR), getreg32(ARMV6M_SYSCON_SHPR2),
+ getreg32(ARMV6M_SYSCON_SHPR3));
leave_critical_section(flags);
+#endif
}
-#endif /* CONFIG_DEBUG */
+#endif /* CONFIG_DEBUG_FEATURES */
diff --git a/arch/arm/src/armv6-m/up_hardfault.c b/arch/arm/src/armv6-m/up_hardfault.c
index edd1bab6a23606f93397d4c85bd62494de83cf90..6b4f69760e19327fb4fb3bf72e496290ef256e28 100644
--- a/arch/arm/src/armv6-m/up_hardfault.c
+++ b/arch/arm/src/armv6-m/up_hardfault.c
@@ -55,25 +55,13 @@
****************************************************************************/
#ifdef CONFIG_DEBUG_HARDFAULT
-# define hfdbg(format, ...) lldbg(format, ##__VA_ARGS__)
+# define hfinfo(format, ...) _alert(format, ##__VA_ARGS__)
#else
-# define hfdbg(x...)
+# define hfinfo(x...)
#endif
#define INSN_SVC0 0xdf00 /* insn: svc 0 */
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -87,7 +75,7 @@
*
****************************************************************************/
-int up_hardfault(int irq, FAR void *context)
+int up_hardfault(int irq, FAR void *context, FAR void *arg)
{
uint32_t *regs = (uint32_t *)context;
@@ -118,7 +106,7 @@ int up_hardfault(int irq, FAR void *context)
/* Fetch the instruction that caused the Hard fault */
uint16_t insn = *pc;
- hfdbg(" PC: %p INSN: %04x\n", pc, insn);
+ hfinfo(" PC: %p INSN: %04x\n", pc, insn);
/* If this was the instruction 'svc 0', then forward processing
* to the SVCall handler
@@ -126,30 +114,30 @@ int up_hardfault(int irq, FAR void *context)
if (insn == INSN_SVC0)
{
- hfdbg("Forward SVCall\n");
- return up_svcall(irq, context);
+ hfinfo("Forward SVCall\n");
+ return up_svcall(irq, context, NULL);
}
}
#if defined(CONFIG_DEBUG_HARDFAULT)
/* Dump some hard fault info */
- hfdbg("\nHard Fault:\n");
- hfdbg(" IRQ: %d regs: %p\n", irq, regs);
- hfdbg(" PRIMASK: %08x IPSR: %08x\n",
- getprimask(), getipsr());
- hfdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
- regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
- hfdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
- regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
- hfdbg(" xPSR: %08x PRIMASK: %08x (saved)\n",
- CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]);
+ _alert("\nHard Fault:\n");
+ _alert(" IRQ: %d regs: %p\n", irq, regs);
+ _alert(" PRIMASK: %08x IPSR: %08x\n",
+ getprimask(), getipsr());
+ _alert(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
+ regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
+ _alert(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
+ regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
+ _alert(" xPSR: %08x PRIMASK: %08x (saved)\n",
+ CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]);
#endif
(void)up_irq_save();
- lldbg("PANIC!!! Hard fault\n");
+ _alert("PANIC!!! Hard fault\n");
PANIC();
return OK; /* Won't get here */
}
diff --git a/arch/arm/src/armv6-m/up_releasepending.c b/arch/arm/src/armv6-m/up_releasepending.c
index c3e2d02ea70c64ed4323136e48f3dff423627322..3c925a02b816280902308c6f314ef8baadc8dc9c 100644
--- a/arch/arm/src/armv6-m/up_releasepending.c
+++ b/arch/arm/src/armv6-m/up_releasepending.c
@@ -66,7 +66,7 @@ void up_release_pending(void)
{
struct tcb_s *rtcb = this_task();
- slldbg("From TCB=%p\n", rtcb);
+ sinfo("From TCB=%p\n", rtcb);
/* Merge the g_pendingtasks list into the ready-to-run task list */
diff --git a/arch/arm/src/armv6-m/up_reprioritizertr.c b/arch/arm/src/armv6-m/up_reprioritizertr.c
index bd50b88b70c2d8c05e5f29b410eeff6af135ac88..41f0c8700d33b9b6859c372b6a134087d4ed89e7 100644
--- a/arch/arm/src/armv6-m/up_reprioritizertr.c
+++ b/arch/arm/src/armv6-m/up_reprioritizertr.c
@@ -94,7 +94,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
struct tcb_s *rtcb = this_task();
bool switch_needed;
- slldbg("TCB=%p PRI=%d\n", tcb, priority);
+ sinfo("TCB=%p PRI=%d\n", tcb, priority);
/* Remove the tcb task from the ready-to-run list.
* sched_removereadytorun will return true if we just removed the head
diff --git a/arch/arm/src/armv6-m/up_schedulesigaction.c b/arch/arm/src/armv6-m/up_schedulesigaction.c
index be9505a9c2c9ae74404f0cf8edd4d215b42cc432..5040582bacf59d2c87c8f27501cb454fd648b357 100644
--- a/arch/arm/src/armv6-m/up_schedulesigaction.c
+++ b/arch/arm/src/armv6-m/up_schedulesigaction.c
@@ -107,7 +107,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
{
irqstate_t flags;
- sdbg("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
+ sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
/* Make sure that interrupts are disabled */
@@ -121,7 +121,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* to the currently executing task.
*/
- sdbg("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
+ sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
if (tcb == this_task())
{
diff --git a/arch/arm/src/armv6-m/up_sigdeliver.c b/arch/arm/src/armv6-m/up_sigdeliver.c
index 84b89542a207aff8cceb519d51bd8e0ac47ce0ff..c2b3e8675e0ee606060d2872254b66607aa5a354 100644
--- a/arch/arm/src/armv6-m/up_sigdeliver.c
+++ b/arch/arm/src/armv6-m/up_sigdeliver.c
@@ -100,7 +100,7 @@ void up_sigdeliver(void)
board_autoled_on(LED_SIGNAL);
- sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
+ sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
ASSERT(rtcb->xcp.sigdeliver != NULL);
@@ -135,7 +135,7 @@ void up_sigdeliver(void)
* errno that is needed by the user logic (it is probably EINTR).
*/
- sdbg("Resuming\n");
+ sinfo("Resuming\n");
(void)up_irq_save();
rtcb->pterrno = saved_errno;
diff --git a/arch/arm/src/armv6-m/up_svcall.c b/arch/arm/src/armv6-m/up_svcall.c
index b5cec07937933cdc12a47165f980057554c8b0e2..fd61de1906f7a6dbf464e0048981d44216b85e99 100644
--- a/arch/arm/src/armv6-m/up_svcall.c
+++ b/arch/arm/src/armv6-m/up_svcall.c
@@ -55,33 +55,6 @@
#include "exc_return.h"
#include "up_internal.h"
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-/* Configuration ************************************************************/
-
-/* Debug ********************************************************************/
-/* Debug output from this file may interfere with context switching! To get
- * debug output you must enabled the following in your NuttX configuration:
- *
- * - CONFIG_DEBUG and CONFIG_DEBUG_SYSCALL (shows only syscalls)
- * - CONFIG_DEBUG and CONFIG_DEBUG_SVCALL (shows everything)
- */
-
-#if defined(CONFIG_DEBUG_SYSCALL) || defined(CONFIG_DEBUG_SVCALL)
-# define svcdbg(format, ...) lldbg(format, ##__VA_ARGS__)
-#else
-# define svcdbg(x...)
-#endif
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -157,7 +130,7 @@ static void dispatch_syscall(void)
*
****************************************************************************/
-int up_svcall(int irq, FAR void *context)
+int up_svcall(int irq, FAR void *context, FAR void *arg)
{
uint32_t *regs = (uint32_t *)context;
uint32_t cmd;
@@ -169,24 +142,24 @@ int up_svcall(int irq, FAR void *context)
* and R1..R7 = variable number of arguments depending on the system call.
*/
-#if defined(CONFIG_DEBUG_SYSCALL) || defined(CONFIG_DEBUG_SVCALL)
+#ifdef CONFIG_DEBUG_SYSCALL_INFO
# ifndef CONFIG_DEBUG_SVCALL
if (cmd > SYS_switch_context)
# endif
{
- svcdbg("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd);
- svcdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
- regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
- svcdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
- regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
+ svcinfo("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd);
+ svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
+ regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
+ svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
+ regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
# ifdef CONFIG_BUILD_PROTECTED
- svcdbg(" PSR: %08x PRIMASK: %08x EXC_RETURN: %08x\n",
- regs[REG_XPSR], regs[REG_PRIMASK], regs[REG_EXC_RETURN]);
+ svcinfo(" PSR: %08x PRIMASK: %08x EXC_RETURN: %08x\n",
+ regs[REG_XPSR], regs[REG_PRIMASK], regs[REG_EXC_RETURN]);
# else
- svcdbg(" PSR: %08x PRIMASK: %08x\n",
- regs[REG_XPSR], regs[REG_PRIMASK]);
+ svcinfo(" PSR: %08x PRIMASK: %08x\n",
+ regs[REG_XPSR], regs[REG_PRIMASK]);
# endif
}
#endif
@@ -471,7 +444,7 @@ int up_svcall(int irq, FAR void *context)
regs[REG_R0] -= CONFIG_SYS_RESERVED;
#else
- slldbg("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
+ svcerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
#endif
}
break;
@@ -479,37 +452,37 @@ int up_svcall(int irq, FAR void *context)
/* Report what happened. That might difficult in the case of a context switch */
-#if defined(CONFIG_DEBUG_SYSCALL) || defined(CONFIG_DEBUG_SVCALL)
+#ifdef CONFIG_DEBUG_SYSCALL_INFO
# ifndef CONFIG_DEBUG_SVCALL
if (cmd > SYS_switch_context)
# else
if (regs != CURRENT_REGS)
# endif
{
- svcdbg("SVCall Return:\n");
- svcdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- CURRENT_REGS[REG_R0], CURRENT_REGS[REG_R1],
- CURRENT_REGS[REG_R2], CURRENT_REGS[REG_R3],
- CURRENT_REGS[REG_R4], CURRENT_REGS[REG_R5],
- CURRENT_REGS[REG_R6], CURRENT_REGS[REG_R7]);
- svcdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- CURRENT_REGS[REG_R8], CURRENT_REGS[REG_R9],
- CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
- CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
- CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
+ svcinfo("SVCall Return:\n");
+ svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ CURRENT_REGS[REG_R0], CURRENT_REGS[REG_R1],
+ CURRENT_REGS[REG_R2], CURRENT_REGS[REG_R3],
+ CURRENT_REGS[REG_R4], CURRENT_REGS[REG_R5],
+ CURRENT_REGS[REG_R6], CURRENT_REGS[REG_R7]);
+ svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ CURRENT_REGS[REG_R8], CURRENT_REGS[REG_R9],
+ CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
+ CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
+ CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
#ifdef CONFIG_BUILD_PROTECTED
- svcdbg(" PSR: %08x PRIMASK: %08x EXC_RETURN: %08x\n",
- CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK],
- CURRENT_REGS[REG_EXC_RETURN]);
+ svcinfo(" PSR: %08x PRIMASK: %08x EXC_RETURN: %08x\n",
+ CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK],
+ CURRENT_REGS[REG_EXC_RETURN]);
#else
- svcdbg(" PSR: %08x PRIMASK: %08x\n",
- CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]);
+ svcinfo(" PSR: %08x PRIMASK: %08x\n",
+ CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]);
#endif
}
# ifdef CONFIG_DEBUG_SVCALL
else
{
- svcdbg("SVCall Return: %d\n", regs[REG_R0]);
+ svcinfo("SVCall Return: %d\n", regs[REG_R0]);
}
# endif
#endif
diff --git a/arch/arm/src/armv7-a/Kconfig b/arch/arm/src/armv7-a/Kconfig
index 85ad10bbee0c202068ccec5d04ae73a1af94596c..e4746900a3fb81a0e821bb37fedc80986deb4e7d 100644
--- a/arch/arm/src/armv7-a/Kconfig
+++ b/arch/arm/src/armv7-a/Kconfig
@@ -128,15 +128,17 @@ endif # ARMV7A_HAVE_L2CC
choice
prompt "Toolchain Selection"
- default ARMV7A_TOOLCHAIN_GNU_EABIW if HOST_WINDOWS
- default ARMV7A_TOOLCHAIN_GNU_EABIL if !HOST_WINDOWS
+ default ARMV7A_TOOLCHAIN_GNU_EABIW if TOOLCHAIN_WINDOWS
+ default ARMV7A_TOOLCHAIN_GNU_EABIL if !TOOLCHAIN_WINDOWS
config ARMV7A_TOOLCHAIN_BUILDROOT
bool "Buildroot (Cygwin or Linux)"
+ select ARM_TOOLCHAIN_GNU
depends on !WINDOWS_NATIVE
config ARMV7A_TOOLCHAIN_CODESOURCERYL
bool "CodeSourcery GNU toolchain under Linux"
+ select ARM_TOOLCHAIN_GNU
depends on HOST_LINUX
---help---
For use with the GNU toolchain built with the NuttX buildroot package.
@@ -145,27 +147,32 @@ config ARMV7A_TOOLCHAIN_CODESOURCERYL
config ARMV7A_TOOLCHAIN_CODESOURCERYW
bool "CodeSourcery GNU toolchain under Windows"
- depends on HOST_WINDOWS
+ select ARM_TOOLCHAIN_GNU
+ depends on TOOLCHAIN_WINDOWS
config ARMV7A_TOOLCHAIN_DEVKITARM
bool "devkitARM GNU toolchain"
- depends on HOST_WINDOWS
+ select ARM_TOOLCHAIN_GNU
+ depends on TOOLCHAIN_WINDOWS
config ARMV7A_TOOLCHAIN_GNU_EABIL
bool "Generic GNU EABI toolchain under Linux (or other POSIX environment)"
+ select ARM_TOOLCHAIN_GNU
---help---
This option should work for any modern GNU toolchain (GCC 4.5 or newer)
configured for arm-none-eabi-.
config ARMV7A_TOOLCHAIN_GNU_EABIW
bool "Generic GNU EABI toolchain under Windows"
- depends on HOST_WINDOWS
+ select ARM_TOOLCHAIN_GNU
+ depends on TOOLCHAIN_WINDOWS
---help---
This option should work for any modern GNU toolchain (GCC 4.5 or newer)
configured for arm-none-eabi-.
config ARMV7A_TOOLCHAIN_GNU_OABI
bool "Generic GNU OABI toolchain"
+ select ARM_TOOLCHAIN_GNU
---help---
This option should work for any GNU toolchain configured for arm-elf-.
diff --git a/arch/arm/src/armv7-a/arm_addrenv.c b/arch/arm/src/armv7-a/arm_addrenv.c
index 2bd1f886cecc08fa8ea163c382416c38cbe64375..7d2818283dca2d1148ea3ecb01c9c4b66fae85a0 100644
--- a/arch/arm/src/armv7-a/arm_addrenv.c
+++ b/arch/arm/src/armv7-a/arm_addrenv.c
@@ -257,7 +257,7 @@ int up_addrenv_create(size_t textsize, size_t datasize, size_t heapsize,
{
int ret;
- bvdbg("addrenv=%p textsize=%lu datasize=%lu\n",
+ binfo("addrenv=%p textsize=%lu datasize=%lu\n",
addrenv, (unsigned long)textsize, (unsigned long)datasize);
DEBUGASSERT(addrenv);
@@ -278,7 +278,7 @@ int up_addrenv_create(size_t textsize, size_t datasize, size_t heapsize,
MMU_L2_UTEXTFLAGS);
if (ret < 0)
{
- bdbg("ERROR: Failed to create .text region: %d\n", ret);
+ berr("ERROR: Failed to create .text region: %d\n", ret);
goto errout;
}
@@ -293,7 +293,7 @@ int up_addrenv_create(size_t textsize, size_t datasize, size_t heapsize,
MMU_L2_UDATAFLAGS);
if (ret < 0)
{
- bdbg("ERROR: Failed to create .bss/.data region: %d\n", ret);
+ berr("ERROR: Failed to create .bss/.data region: %d\n", ret);
goto errout;
}
@@ -305,7 +305,7 @@ int up_addrenv_create(size_t textsize, size_t datasize, size_t heapsize,
ret = up_addrenv_initdata((uintptr_t)addrenv->data[0] & PMD_PTE_PADDR_MASK);
if (ret < 0)
{
- bdbg("ERROR: Failed to initialize .bss/.data region: %d\n", ret);
+ berr("ERROR: Failed to initialize .bss/.data region: %d\n", ret);
goto errout;
}
#endif
@@ -318,7 +318,7 @@ int up_addrenv_create(size_t textsize, size_t datasize, size_t heapsize,
MMU_L2_UDATAFLAGS);
if (ret < 0)
{
- bdbg("ERROR: Failed to create heap region: %d\n", ret);
+ berr("ERROR: Failed to create heap region: %d\n", ret);
goto errout;
}
@@ -353,7 +353,7 @@ errout:
int up_addrenv_destroy(FAR group_addrenv_t *addrenv)
{
- bvdbg("addrenv=%p\n", addrenv);
+ binfo("addrenv=%p\n", addrenv);
DEBUGASSERT(addrenv);
/* Destroy the .text region */
@@ -405,7 +405,7 @@ int up_addrenv_destroy(FAR group_addrenv_t *addrenv)
int up_addrenv_vtext(FAR group_addrenv_t *addrenv, FAR void **vtext)
{
- bvdbg("return=%p\n", (FAR void *)CONFIG_ARCH_TEXT_VBASE);
+ binfo("return=%p\n", (FAR void *)CONFIG_ARCH_TEXT_VBASE);
/* Not much to do in this case */
@@ -439,7 +439,7 @@ int up_addrenv_vtext(FAR group_addrenv_t *addrenv, FAR void **vtext)
int up_addrenv_vdata(FAR group_addrenv_t *addrenv, uintptr_t textsize,
FAR void **vdata)
{
- bvdbg("return=%p\n",
+ binfo("return=%p\n",
(FAR void *)(CONFIG_ARCH_DATA_VBASE + ARCH_DATA_RESERVE_SIZE));
/* Not much to do in this case */
@@ -636,7 +636,7 @@ int up_addrenv_restore(FAR const save_addrenv_t *oldenv)
uintptr_t vaddr;
int i;
- bvdbg("oldenv=%p\n", oldenv);
+ binfo("oldenv=%p\n", oldenv);
DEBUGASSERT(oldenv);
for (vaddr = CONFIG_ARCH_TEXT_VBASE, i = 0;
@@ -752,7 +752,7 @@ int up_addrenv_coherent(FAR const group_addrenv_t *addrenv)
int up_addrenv_clone(FAR const group_addrenv_t *src,
FAR group_addrenv_t *dest)
{
- bvdbg("src=%p dest=%p\n", src, dest);
+ binfo("src=%p dest=%p\n", src, dest);
DEBUGASSERT(src && dest);
/* Just copy the address environment from the source to the destination */
@@ -784,7 +784,7 @@ int up_addrenv_clone(FAR const group_addrenv_t *src,
int up_addrenv_attach(FAR struct task_group_s *group, FAR struct tcb_s *tcb)
{
- bvdbg("group=%p tcb=%p\n", group, tcb);
+ binfo("group=%p tcb=%p\n", group, tcb);
/* Nothing needs to be done in this implementation */
@@ -817,7 +817,7 @@ int up_addrenv_attach(FAR struct task_group_s *group, FAR struct tcb_s *tcb)
int up_addrenv_detach(FAR struct task_group_s *group, FAR struct tcb_s *tcb)
{
- bvdbg("group=%p tcb=%p\n", group, tcb);
+ binfo("group=%p tcb=%p\n", group, tcb);
/* Nothing needs to be done in this implementation */
diff --git a/arch/arm/src/armv7-a/arm_addrenv_kstack.c b/arch/arm/src/armv7-a/arm_addrenv_kstack.c
index da2a474126edce8306937c48ce5202bb016f14b7..5bb2b688b541cc09b477555ac879010dd39f7d06 100644
--- a/arch/arm/src/armv7-a/arm_addrenv_kstack.c
+++ b/arch/arm/src/armv7-a/arm_addrenv_kstack.c
@@ -144,7 +144,7 @@
int up_addrenv_kstackalloc(FAR struct tcb_s *tcb)
{
- bvdbg("tcb=%p stacksize=%u\n", tcb, ARCH_KERNEL_STACKSIZE);
+ binfo("tcb=%p stacksize=%u\n", tcb, ARCH_KERNEL_STACKSIZE);
DEBUGASSERT(tcb && tcb->xcp.kstack == 0);
@@ -153,7 +153,7 @@ int up_addrenv_kstackalloc(FAR struct tcb_s *tcb)
tcb->xcp.kstack = (FAR uint32_t *)kmm_memalign(8, ARCH_KERNEL_STACKSIZE);
if (!tcb->xcp.kstack)
{
- bdbg("ERROR: Failed to allocate the kernel stack\n");
+ berr("ERROR: Failed to allocate the kernel stack\n");
return -ENOMEM;
}
@@ -177,7 +177,7 @@ int up_addrenv_kstackalloc(FAR struct tcb_s *tcb)
int up_addrenv_kstackfree(FAR struct tcb_s *tcb)
{
- bvdbg("tcb=%p\n", tcb);
+ binfo("tcb=%p\n", tcb);
DEBUGASSERT(tcb);
/* Does the exiting thread have a kernel stack? */
diff --git a/arch/arm/src/armv7-a/arm_addrenv_shm.c b/arch/arm/src/armv7-a/arm_addrenv_shm.c
index 9a05b9f7b92997542052a72156a2b7c1dab6cbb2..cc9c9440d802dba65a345c74e6c7ebbb98e108c6 100644
--- a/arch/arm/src/armv7-a/arm_addrenv_shm.c
+++ b/arch/arm/src/armv7-a/arm_addrenv_shm.c
@@ -92,7 +92,7 @@ int up_shmat(FAR uintptr_t *pages, unsigned int npages, uintptr_t vaddr)
unsigned int nmapped;
unsigned int shmndx;
- shmvdbg("pages=%p npages=%d vaddr=%08lx\n",
+ shminfo("pages=%p npages=%d vaddr=%08lx\n",
pages, npages, (unsigned long)vaddr);
/* Sanity checks */
@@ -241,7 +241,7 @@ int up_shmdt(uintptr_t vaddr, unsigned int npages)
unsigned int nunmapped;
unsigned int shmndx;
- shmvdbg("npages=%d vaddr=%08lx\n", npages, (unsigned long)vaddr);
+ shminfo("npages=%d vaddr=%08lx\n", npages, (unsigned long)vaddr);
/* Sanity checks */
diff --git a/arch/arm/src/armv7-a/arm_addrenv_ustack.c b/arch/arm/src/armv7-a/arm_addrenv_ustack.c
index 206d517ef3810f7190d84bc1d0241328b851ddf9..4b7be01bd6d73e4c8df83412385790799d7ed909 100644
--- a/arch/arm/src/armv7-a/arm_addrenv_ustack.c
+++ b/arch/arm/src/armv7-a/arm_addrenv_ustack.c
@@ -143,7 +143,7 @@ int up_addrenv_ustackalloc(FAR struct tcb_s *tcb, size_t stacksize)
{
int ret;
- bvdbg("tcb=%p stacksize=%lu\n", tcb, (unsigned long)stacksize);
+ binfo("tcb=%p stacksize=%lu\n", tcb, (unsigned long)stacksize);
DEBUGASSERT(tcb);
@@ -163,7 +163,7 @@ int up_addrenv_ustackalloc(FAR struct tcb_s *tcb, size_t stacksize)
MMU_L2_UDATAFLAGS);
if (ret < 0)
{
- bdbg("ERROR: Failed to create stack region: %d\n", ret);
+ berr("ERROR: Failed to create stack region: %d\n", ret);
up_addrenv_ustackfree(tcb);
return ret;
}
@@ -190,7 +190,7 @@ int up_addrenv_ustackalloc(FAR struct tcb_s *tcb, size_t stacksize)
int up_addrenv_ustackfree(FAR struct tcb_s *tcb)
{
- bvdbg("tcb=%p\n", tcb);
+ binfo("tcb=%p\n", tcb);
DEBUGASSERT(tcb);
/* Destroy the stack region */
@@ -221,7 +221,7 @@ int up_addrenv_ustackfree(FAR struct tcb_s *tcb)
int up_addrenv_vustack(FAR const struct tcb_s *tcb, FAR void **vstack)
{
- bvdbg("Return=%p\n", (FAR void *)CONFIG_ARCH_STACK_VBASE);
+ binfo("Return=%p\n", (FAR void *)CONFIG_ARCH_STACK_VBASE);
/* Not much to do in this case */
diff --git a/arch/arm/src/armv7-a/arm_addrenv_utils.c b/arch/arm/src/armv7-a/arm_addrenv_utils.c
index f3147918f26e5f32c8d749b19eb6be06a1b1aee0..2eb58623afaa55e5da925232879a620c256823c5 100644
--- a/arch/arm/src/armv7-a/arm_addrenv_utils.c
+++ b/arch/arm/src/armv7-a/arm_addrenv_utils.c
@@ -84,7 +84,7 @@ int arm_addrenv_create_region(FAR uintptr_t **list, unsigned int listlen,
unsigned int i;
unsigned int j;
- bvdbg("listlen=%d vaddr=%08lx regionsize=%ld, mmuflags=%08x\n",
+ binfo("listlen=%d vaddr=%08lx regionsize=%ld, mmuflags=%08x\n",
listlen, (unsigned long)vaddr, (unsigned long)regionsize,
(unsigned int)mmuflags);
@@ -98,7 +98,7 @@ int arm_addrenv_create_region(FAR uintptr_t **list, unsigned int listlen,
npages = MM_NPAGES(regionsize);
if (npages > (listlen << (20 - MM_PGSHIFT)))
{
- bdbg("ERROR: npages=%u listlen=%u\n", npages, listlen);
+ berr("ERROR: npages=%u listlen=%u\n", npages, listlen);
return -E2BIG;
}
@@ -201,7 +201,7 @@ void arm_addrenv_destroy_region(FAR uintptr_t **list, unsigned int listlen,
int i;
int j;
- bvdbg("listlen=%d vaddr=%08lx\n", listlen, (unsigned long)vaddr);
+ binfo("listlen=%d vaddr=%08lx\n", listlen, (unsigned long)vaddr);
for (i = 0; i < listlen; vaddr += SECTION_SIZE, list++, i++)
{
diff --git a/arch/arm/src/armv7-a/arm_assert.c b/arch/arm/src/armv7-a/arm_assert.c
index ab3bd4c90819c9eea4377d7116f9a111cf366c31..72952e0cfaa096d8902ff03440d4ece14c70bd07 100644
--- a/arch/arm/src/armv7-a/arm_assert.c
+++ b/arch/arm/src/armv7-a/arm_assert.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv7-a/arm_assert.c
*
- * Copyright (C) 2013-2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
#include
@@ -64,6 +53,7 @@
#include "up_arch.h"
#include "sched/sched.h"
+#include "irq/irq.h"
#include "up_internal.h"
/****************************************************************************
@@ -75,19 +65,6 @@
# undef CONFIG_ARCH_USBDUMP
#endif
-/* The following is just intended to keep some ugliness out of the mainline
- * code. We are going to print the task name if:
- *
- * CONFIG_TASK_NAME_SIZE > 0 && <-- The task has a name
- * (defined(CONFIG_DEBUG) || <-- And the debug is enabled (lldbg used)
- * defined(CONFIG_ARCH_STACKDUMP) <-- Or lowsyslog() is used
- */
-
-#undef CONFIG_PRINT_TASKNAME
-#if CONFIG_TASK_NAME_SIZE > 0 && (defined(CONFIG_DEBUG) || defined(CONFIG_ARCH_STACKDUMP))
-# define CONFIG_PRINT_TASKNAME 1
-#endif
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -121,7 +98,7 @@ static void up_stackdump(uint32_t sp, uint32_t stack_base)
for (stack = sp & ~0x1f; stack < stack_base; stack += 32)
{
uint32_t *ptr = (uint32_t *)stack;
- lldbg("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ _alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
stack, ptr[0], ptr[1], ptr[2], ptr[3],
ptr[4], ptr[5], ptr[6], ptr[7]);
}
@@ -139,12 +116,12 @@ static void up_taskdump(FAR struct tcb_s *tcb, FAR void *arg)
{
/* Dump interesting properties of this task */
-#ifdef CONFIG_PRINT_TASKNAME
- lldbg("%s: PID=%d Stack Used=%lu of %lu\n",
+#if CONFIG_TASK_NAME_SIZE > 0
+ _alert("%s: PID=%d Stack Used=%lu of %lu\n",
tcb->name, tcb->pid, (unsigned long)up_check_tcbstack(tcb),
(unsigned long)tcb->adj_stack_size);
#else
- lldbg("PID: %d Stack Used=%lu of %lu\n",
+ _alert("PID: %d Stack Used=%lu of %lu\n",
tcb->pid, (unsigned long)up_check_tcbstack(tcb),
(unsigned long)tcb->adj_stack_size);
#endif
@@ -184,12 +161,12 @@ static inline void up_registerdump(void)
for (regs = REG_R0; regs <= REG_R15; regs += 8)
{
uint32_t *ptr = (uint32_t *)&CURRENT_REGS[regs];
- lldbg("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ _alert("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs, ptr[0], ptr[1], ptr[2], ptr[3],
ptr[4], ptr[5], ptr[6], ptr[7]);
}
- lldbg("CPSR: %08x\n", CURRENT_REGS[REG_CPSR]);
+ _alert("CPSR: %08x\n", CURRENT_REGS[REG_CPSR]);
}
}
#else
@@ -209,7 +186,7 @@ static int usbtrace_syslog(FAR const char *fmt, ...)
/* Let vsyslog do the real work */
va_start(ap, fmt);
- ret = lowvsyslog(LOG_INFO, fmt, ap);
+ ret = vsyslog(LOG_EMERG, fmt, ap);
va_end(ap);
return ret;
}
@@ -253,7 +230,7 @@ static void up_dumpstate(void)
ustacksize = (uint32_t)rtcb->adj_stack_size;
}
- lldbg("Current sp: %08x\n", sp);
+ _alert("Current sp: %08x\n", sp);
#if CONFIG_ARCH_INTERRUPTSTACK > 3
/* Get the limits on the interrupt stack memory */
@@ -263,21 +240,21 @@ static void up_dumpstate(void)
/* Show interrupt stack info */
- lldbg("Interrupt stack:\n");
- lldbg(" base: %08x\n", istackbase);
- lldbg(" size: %08x\n", istacksize);
+ _alert("Interrupt stack:\n");
+ _alert(" base: %08x\n", istackbase);
+ _alert(" size: %08x\n", istacksize);
#ifdef CONFIG_STACK_COLORATION
- lldbg(" used: %08x\n", up_check_intstack());
+ _alert(" used: %08x\n", up_check_intstack());
#endif
#endif
/* Show user stack info */
- lldbg("User stack:\n");
- lldbg(" base: %08x\n", ustackbase);
- lldbg(" size: %08x\n", ustacksize);
+ _alert("User stack:\n");
+ _alert(" base: %08x\n", ustackbase);
+ _alert(" size: %08x\n", ustacksize);
#ifdef CONFIG_STACK_COLORATION
- lldbg(" used: %08x\n", up_check_tcbstack(rtcb));
+ _alert(" used: %08x\n", up_check_tcbstack(rtcb));
#endif
#ifdef CONFIG_ARCH_KERNEL_STACK
@@ -287,9 +264,9 @@ static void up_dumpstate(void)
{
kstackbase = (uint32_t)rtcb->xcp.kstack + CONFIG_ARCH_KERNEL_STACKSIZE - 4;
- lldbg("Kernel stack:\n");
- lldbg(" base: %08x\n", kstackbase);
- lldbg(" size: %08x\n", CONFIG_ARCH_KERNEL_STACKSIZE);
+ _alert("Kernel stack:\n");
+ _alert(" base: %08x\n", kstackbase);
+ _alert(" size: %08x\n", CONFIG_ARCH_KERNEL_STACKSIZE);
}
#endif
@@ -300,7 +277,7 @@ static void up_dumpstate(void)
{
/* Yes.. dump the interrupt stack */
- lldbg("Interrupt Stack\n", sp);
+ _alert("Interrupt Stack\n", sp);
up_stackdump(sp, istackbase);
/* Extract the user stack pointer which should lie
@@ -308,7 +285,7 @@ static void up_dumpstate(void)
*/
sp = g_intstackbase;
- lldbg("User sp: %08x\n", sp);
+ _alert("User sp: %08x\n", sp);
}
#endif
@@ -318,7 +295,7 @@ static void up_dumpstate(void)
if (sp > ustackbase - ustacksize && sp < ustackbase)
{
- lldbg("User Stack\n", sp);
+ _alert("User Stack\n", sp);
up_stackdump(sp, ustackbase);
}
@@ -329,7 +306,7 @@ static void up_dumpstate(void)
if (sp >= (uint32_t)rtcb->xcp.kstack && sp < kstackbase)
{
- lldbg("Kernel Stack\n", sp);
+ _alert("Kernel Stack\n", sp);
up_stackdump(sp, kstackbase);
}
#endif
@@ -337,7 +314,7 @@ static void up_dumpstate(void)
#ifdef CONFIG_SMP
/* Show the CPU number */
- lldbg("CPU%d:\n", up_cpu_index());
+ _alert("CPU%d:\n", up_cpu_index());
#endif
/* Then dump the CPU registers (if available) */
@@ -369,10 +346,21 @@ static void _up_assert(int errorcode)
if (CURRENT_REGS || this_task()->pid == 0)
{
+ /* Disable interrupts on this CPU */
+
(void)up_irq_save();
+
for (; ; )
{
+#ifdef CONFIG_SMP
+ /* Try (again) to stop activity on other CPUs */
+
+ (void)spin_trylock(&g_cpu_irqlock);
+#endif
+
#ifdef CONFIG_ARCH_LEDS
+ /* FLASH LEDs a 2Hz */
+
board_autoled_on(LED_PANIC);
up_mdelay(250);
board_autoled_off(LED_PANIC);
@@ -396,16 +384,16 @@ static void _up_assert(int errorcode)
void up_assert(const uint8_t *filename, int lineno)
{
-#ifdef CONFIG_PRINT_TASKNAME
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT)
struct tcb_s *rtcb = this_task();
#endif
board_autoled_on(LED_ASSERTION);
-#ifdef CONFIG_PRINT_TASKNAME
- lldbg("Assertion failed at file:%s line: %d task: %s\n",
+#if CONFIG_TASK_NAME_SIZE > 0
+ _alert("Assertion failed at file:%s line: %d task: %s\n",
filename, lineno, rtcb->name);
#else
- lldbg("Assertion failed at file:%s line: %d\n",
+ _alert("Assertion failed at file:%s line: %d\n",
filename, lineno);
#endif
up_dumpstate();
diff --git a/arch/arm/src/armv7-a/arm_cpuhead.S b/arch/arm/src/armv7-a/arm_cpuhead.S
index 487fee0a46bc805660b030c47d20c34976627b10..02735e36d50c39df1d5ff8a558fcf138d66df0fa 100644
--- a/arch/arm/src/armv7-a/arm_cpuhead.S
+++ b/arch/arm/src/armv7-a/arm_cpuhead.S
@@ -308,7 +308,11 @@ __cpu3_start:
orr r0, r0, #(SCTLR_RR)
#endif
-#ifndef CPU_DCACHE_DISABLE
+ /* In SMP configurations, the data cache will not be enabled until later
+ * after SMP cache coherency has been setup.
+ */
+
+#if 0 /* !defined(CPU_DCACHE_DISABLE) && !defined(CONFIG_SMP) */
/* Dcache enable
*
* SCTLR_C Bit 2: DCache enable
diff --git a/arch/arm/src/armv7-a/arm_cpupause.c b/arch/arm/src/armv7-a/arm_cpupause.c
index 585d574b06c5f6f97c42bac4a46b28b90e9b3277..8a1499c29761cc4acfa98b48696e7db45188bdb0 100644
--- a/arch/arm/src/armv7-a/arm_cpupause.c
+++ b/arch/arm/src/armv7-a/arm_cpupause.c
@@ -44,6 +44,7 @@
#include
#include
#include
+#include
#include "up_internal.h"
#include "gic.h"
@@ -55,18 +56,58 @@
* Private Data
****************************************************************************/
-static spinlock_t g_cpu_wait[CONFIG_SMP_NCPUS];
-static spinlock_t g_cpu_paused[CONFIG_SMP_NCPUS];
+/* These spinlocks are used in the SMP configuration in order to implement
+ * up_cpu_pause(). The protocol for CPUn to pause CPUm is as follows
+ *
+ * 1. The up_cpu_pause() implementation on CPUn locks both g_cpu_wait[m]
+ * and g_cpu_paused[m]. CPUn then waits spinning on g_cpu_paused[m].
+ * 2. CPUm receives the interrupt it (1) unlocks g_cpu_paused[m] and
+ * (2) locks g_cpu_wait[m]. The first unblocks CPUn and the second
+ * blocks CPUm in the interrupt handler.
+ *
+ * When CPUm resumes, CPUn unlocks g_cpu_wait[m] and the interrupt handler
+ * on CPUm continues. CPUm must, of course, also then unlock g_cpu_wait[m]
+ * so that it will be ready for the next pause operation.
+ */
+
+static volatile spinlock_t g_cpu_wait[CONFIG_SMP_NCPUS] SP_SECTION;
+static volatile spinlock_t g_cpu_paused[CONFIG_SMP_NCPUS] SP_SECTION;
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
- * Name: arm_pause_handler
+ * Name: up_cpu_pausereq
*
* Description:
- * This is the handler for SGI2. It performs the following operations:
+ * Return true if a pause request is pending for this CPU.
+ *
+ * Input Parameters:
+ * cpu - The index of the CPU to be queried
+ *
+ * Returned Value:
+ * true = a pause request is pending.
+ * false = no pasue request is pending.
+ *
+ ****************************************************************************/
+
+bool up_cpu_pausereq(int cpu)
+{
+ return spin_islocked(&g_cpu_paused[cpu]);
+}
+
+/****************************************************************************
+ * Name: up_cpu_paused
+ *
+ * Description:
+ * Handle a pause request from another CPU. Normally, this logic is
+ * executed from interrupt handling logic within the architecture-specific
+ * However, it is sometimes necessary necessary to perform the pending
+ * pause operation in other contexts where the interrupt cannot be taken
+ * in order to avoid deadlocks.
+ *
+ * This function performs the following operations:
*
* 1. It saves the current task state at the head of the current assigned
* task list.
@@ -75,49 +116,107 @@ static spinlock_t g_cpu_paused[CONFIG_SMP_NCPUS];
* head of the ready to run list.
*
* Input Parameters:
- * Standard interrupt handling
+ * cpu - The index of the CPU to be paused
*
* Returned Value:
- * Zero on success; a negated errno value on failure.
+ * On success, OK is returned. Otherwise, a negated errno value indicating
+ * the nature of the failure is returned.
*
****************************************************************************/
-int arm_pause_handler(int irq, FAR void *context)
+int up_cpu_paused(int cpu)
{
FAR struct tcb_s *tcb = this_task();
- int cpu = up_cpu_index();
/* Update scheduler parameters */
sched_suspend_scheduler(tcb);
- /* Save the current context at CURRENT_REGS into the TCB at the head of the
- * assigned task list for this CPU.
+#ifdef CONFIG_SCHED_INSTRUMENTATION
+ /* Notify that we are paused */
+
+ sched_note_cpu_paused(tcb);
+#endif
+
+ /* Save the current context at CURRENT_REGS into the TCB at the head
+ * of the assigned task list for this CPU.
*/
up_savestate(tcb->xcp.regs);
- /* Wait for the spinlock to be released */
+ /* Release the g_cpu_puased spinlock to synchronize with the
+ * requesting CPU.
+ */
spin_unlock(&g_cpu_paused[cpu]);
+
+ /* Wait for the spinlock to be released. The requesting CPU will release
+ * the spinlcok when the CPU is resumed.
+ */
+
spin_lock(&g_cpu_wait[cpu]);
- /* Restore the exception context of the tcb at the (new) head of the
- * assigned task list.
+ /* This CPU has been resumed. Restore the exception context of the TCB at
+ * the (new) head of the assigned task list.
*/
tcb = this_task();
+#ifdef CONFIG_SCHED_INSTRUMENTATION
+ /* Notify that we have resumed */
+
+ sched_note_cpu_resumed(tcb);
+#endif
+
/* Reset scheduler parameters */
sched_resume_scheduler(tcb);
- /* Then switch contexts. Any necessary address environment changes will
- * be made when the interrupt returns.
+ /* Then switch contexts. Any necessary address environment changes
+ * will be made when the interrupt returns.
*/
up_restorestate(tcb->xcp.regs);
spin_unlock(&g_cpu_wait[cpu]);
+
+ return OK;
+}
+
+/****************************************************************************
+ * Name: arm_pause_handler
+ *
+ * Description:
+ * This is the handler for SGI2. It performs the following operations:
+ *
+ * 1. It saves the current task state at the head of the current assigned
+ * task list.
+ * 2. It waits on a spinlock, then
+ * 3. Returns from interrupt, restoring the state of the new task at the
+ * head of the ready to run list.
+ *
+ * Input Parameters:
+ * Standard interrupt handling
+ *
+ * Returned Value:
+ * Zero on success; a negated errno value on failure.
+ *
+ ****************************************************************************/
+
+int arm_pause_handler(int irq, FAR void *context, FAR void *arg)
+{
+ int cpu = this_cpu();
+
+ /* Check for false alarms. Such false could occur as a consequence of
+ * some deadlock breaking logic that might have already serviced the SG2
+ * interrupt by calling up_cpu_paused(). If the pause event has already
+ * been processed then g_cpu_paused[cpu] will not be locked.
+ */
+
+ if (spin_islocked(&g_cpu_paused[cpu]))
+ {
+ return up_cpu_paused(cpu);
+ }
+
return OK;
}
@@ -134,7 +233,7 @@ int arm_pause_handler(int irq, FAR void *context)
* CPU.
*
* Input Parameters:
- * cpu - The index of the CPU to be stopped/
+ * cpu - The index of the CPU to be stopped
*
* Returned Value:
* Zero on success; a negated errno value on failure.
@@ -147,6 +246,12 @@ int up_cpu_pause(int cpu)
DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu());
+#ifdef CONFIG_SCHED_INSTRUMENTATION
+ /* Notify of the pause event */
+
+ sched_note_cpu_pause(this_task(), cpu);
+#endif
+
/* Take the both spinlocks. The g_cpu_wait spinlock will prevent the SGI2
* handler from returning until up_cpu_resume() is called; g_cpu_paused
* is a handshake that will prefent this function from returning until
@@ -210,6 +315,12 @@ int up_cpu_resume(int cpu)
{
DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu());
+#ifdef CONFIG_SCHED_INSTRUMENTATION
+ /* Notify of the resume event */
+
+ sched_note_cpu_resume(this_task(), cpu);
+#endif
+
/* Release the spinlock. Releasing the spinlock will cause the SGI2
* handler on 'cpu' to continue and return from interrupt to the newly
* established thread.
diff --git a/arch/arm/src/armv7-a/arm_cpustart.c b/arch/arm/src/armv7-a/arm_cpustart.c
index 1ec95da855a9122c37c018593feda1c0d9118b2b..3226153f5c188719e76ac95da412d11078cb1488 100644
--- a/arch/arm/src/armv7-a/arm_cpustart.c
+++ b/arch/arm/src/armv7-a/arm_cpustart.c
@@ -43,10 +43,11 @@
#include
#include
+#include
#include "up_internal.h"
-#include "gic.h"
#include "cp15_cacheops.h"
+#include "gic.h"
#include "sched/sched.h"
#ifdef CONFIG_SMP
@@ -64,19 +65,19 @@ static inline void arm_registerdump(FAR struct tcb_s *tcb)
{
int regndx;
- lldbg("CPU%d:\n", up_cpu_index());
+ _info("CPU%d:\n", up_cpu_index());
/* Dump the startup registers */
for (regndx = REG_R0; regndx <= REG_R15; regndx += 8)
{
uint32_t *ptr = (uint32_t *)&tcb->xcp.regs[regndx];
- lldbg("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regndx, ptr[0], ptr[1], ptr[2], ptr[3],
- ptr[4], ptr[5], ptr[6], ptr[7]);
+ _info("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regndx, ptr[0], ptr[1], ptr[2], ptr[3],
+ ptr[4], ptr[5], ptr[6], ptr[7]);
}
- lldbg("CPSR: %08x\n", tcb->xcp.regs[REG_CPSR]);
+ _info("CPSR: %08x\n", tcb->xcp.regs[REG_CPSR]);
}
#else
# define arm_registerdump(tcb)
@@ -102,15 +103,20 @@ static inline void arm_registerdump(FAR struct tcb_s *tcb)
*
****************************************************************************/
-int arm_start_handler(int irq, FAR void *context)
+int arm_start_handler(int irq, FAR void *context, FAR void *arg)
{
- FAR struct tcb_s *tcb;
+ FAR struct tcb_s *tcb = this_task();
+
+ sinfo("CPU%d Started\n", this_cpu());
+
+#ifdef CONFIG_SCHED_INSTRUMENTATION
+ /* Notify that this CPU has started */
- sllvdbg("CPU%d Started\n", up_cpu_index());
+ sched_note_cpu_started(tcb);
+#endif
/* Reset scheduler parameters */
- tcb = this_task();
sched_resume_scheduler(tcb);
/* Dump registers so that we can see what is going to happen on return */
@@ -155,10 +161,16 @@ int arm_start_handler(int irq, FAR void *context)
int up_cpu_start(int cpu)
{
- sllvdbg("Starting CPU%d\n", cpu);
+ sinfo("Starting CPU%d\n", cpu);
DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu());
+#ifdef CONFIG_SCHED_INSTRUMENTATION
+ /* Notify of the start event */
+
+ sched_note_cpu_start(this_task(), cpu);
+#endif
+
/* Make the content of CPU0 L1 cache has been written to coherent L2 */
cp15_clean_dcache(CONFIG_RAM_START, CONFIG_RAM_END - 1);
diff --git a/arch/arm/src/armv7-a/arm_dataabort.c b/arch/arm/src/armv7-a/arm_dataabort.c
index 818557c552abc99c82e0acde220c62afeb9ff910..50c95a20188001fd7013b49f8822ce9ec930d9bc 100644
--- a/arch/arm/src/armv7-a/arm_dataabort.c
+++ b/arch/arm/src/armv7-a/arm_dataabort.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv7-a/arm_dataabort.c
*
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
@@ -115,7 +104,7 @@ uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr)
* fatal error.
*/
- pglldbg("DFSR: %08x DFAR: %08x\n", dfsr, dfar);
+ pginfo("DFSR: %08x DFAR: %08x\n", dfsr, dfar);
if ((dfsr & FSR_MASK) != FSR_PAGE)
{
goto segfault;
@@ -126,7 +115,7 @@ uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr)
* (It has not yet been saved in the register context save area).
*/
- pgllvdbg("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND);
+ pginfo("VBASE: %08x VEND: %08x\n", PG_PAGED_VBASE, PG_PAGED_VEND);
if (dfar < PG_PAGED_VBASE || dfar >= PG_PAGED_VEND)
{
goto segfault;
@@ -163,7 +152,7 @@ uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr)
return regs;
segfault:
- lldbg("Data abort. PC: %08x DFAR: %08x DFSR: %08x\n",
+ _alert("Data abort. PC: %08x DFAR: %08x DFSR: %08x\n",
regs[REG_PC], dfar, dfsr);
PANIC();
return regs; /* To keep the compiler happy */
@@ -181,7 +170,7 @@ uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr)
/* Crash -- possibly showing diagnostic debug information. */
- lldbg("Data abort. PC: %08x DFAR: %08x DFSR: %08x\n",
+ _alert("Data abort. PC: %08x DFAR: %08x DFSR: %08x\n",
regs[REG_PC], dfar, dfsr);
PANIC();
return regs; /* To keep the compiler happy */
diff --git a/arch/arm/src/armv7-a/arm_doirq.c b/arch/arm/src/armv7-a/arm_doirq.c
index b3d98151c0bcb262f2b0e10901a684e78fb80544..fa3e104582383162b874619a58dfd86b165aed78 100644
--- a/arch/arm/src/armv7-a/arm_doirq.c
+++ b/arch/arm/src/armv7-a/arm_doirq.c
@@ -40,10 +40,10 @@
#include
#include
-#include
-#include
#include
+#include
+#include
#include
#include
@@ -51,21 +51,40 @@
#include "up_internal.h"
#include "group/group.h"
+#include "gic.h"
/****************************************************************************
- * Public Functions
+ * Private Data
****************************************************************************/
-uint32_t *arm_doirq(int irq, uint32_t *regs)
-{
- board_autoled_on(LED_INIRQ);
-#ifdef CONFIG_SUPPRESS_INTERRUPTS
- PANIC();
+/* A bit set of pending, non-maskable SGI interrupts, on bit set for each
+ * supported CPU.
+ */
+
+#ifdef CONFIG_ARMV7A_HAVE_GICv2
+#ifdef CONFIG_SMP
+static uint16_t g_sgi_pending[CONFIG_SMP_NCPUS];
#else
- /* Nested interrupts are not supported */
+static uint16_t g_sgi_pending[1];
+#endif
+#endif
- DEBUGASSERT(CURRENT_REGS == NULL);
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: _arm_doirq
+ *
+ * Description:
+ * Receives the one decoded interrupt and dispatches control to the
+ * attached interrupt handler.
+ *
+ ****************************************************************************/
+#ifndef CONFIG_SUPPRESS_INTERRUPTS
+static inline uint32_t *_arm_doirq(int irq, uint32_t *regs)
+{
/* Current regs non-zero indicates that we are processing an interrupt;
* CURRENT_REGS is also used to manage interrupt level context switches.
*/
@@ -110,8 +129,131 @@ uint32_t *arm_doirq(int irq, uint32_t *regs)
regs = (uint32_t *)CURRENT_REGS;
CURRENT_REGS = NULL;
+
+ return regs;
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arm_doirq
+ *
+ * Description:
+ * Receives the decoded GIC interrupt information and dispatches control
+ * to the attached interrupt handler. There are two versions:
+ *
+ * 1) For the simple case where all interrupts are maskable. In that
+ * simple case, arm_doirq() is simply a wrapper for the inlined
+ * _arm_do_irq() that does the real work.
+ *
+ * 2) With the GICv2, there are 16 non-maskable software generated
+ * interrupts (SGIs) that also come through arm_doirq(). In that case,
+ * we must avoid nesting interrupt handling and serial the processing.
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_ARMV7A_HAVE_GICv2
+uint32_t *arm_doirq(int irq, uint32_t *regs)
+{
+ board_autoled_on(LED_INIRQ);
+#ifdef CONFIG_SUPPRESS_INTERRUPTS
+ PANIC();
+#else
+ /* Nested interrupts are not supported */
+
+ DEBUGASSERT(CURRENT_REGS == NULL);
+
+ /* Dispatch the interrupt to its attached handler */
+
+ regs = _arm_doirq(irq, regs);
+#endif
+
+ board_autoled_off(LED_INIRQ);
+ return regs;
+}
+#endif
+
+#ifdef CONFIG_ARMV7A_HAVE_GICv2
+uint32_t *arm_doirq(int irq, uint32_t *regs)
+{
+#ifndef CONFIG_SUPPRESS_INTERRUPTS
+ uint32_t bit;
+ int cpu;
+ int i;
+#endif
+
+ board_autoled_on(LED_INIRQ);
+#ifdef CONFIG_SUPPRESS_INTERRUPTS
+ PANIC();
+
+#else
+ /* Get the CPU processing the interrupt */
+
+#ifdef CONFIG_SMP
+ cpu = up_cpu_index();
+#else
+ cpu = 0;
+#endif
+
+ /* Non-zero CURRENT_REGS indicates that we are already processing an
+ * interrupt. This could be a normal event for the case of the GICv2;
+ * Software generated interrupts are non-maskable.
+ *
+ * REVISIT: There is no support for nested SGIs! That will cause an
+ * assertion below. There is also no protection for concurrent access
+ * to g_sgi_pending for that case.
+ */
+
+ if (CURRENT_REGS != NULL)
+ {
+ int ndx = irq - GIC_IRQ_SGI0;
+ bit = (1 << (ndx));
+
+ /* Only an SGI should cause this event. We also cannot support
+ * multiple pending SGI interrupts.
+ */
+
+ ASSERT((unsigned int)irq <= GIC_IRQ_SGI15 &&
+ (g_sgi_pending[cpu] & bit) == 0);
+
+ /* Mare the SGI as pending and return immediately */
+
+ sinfo("SGI%d pending\n", ndx);
+ g_sgi_pending[cpu] |= bit;
+ return regs;
+ }
+
+ /* Dispatch the interrupt to its attached handler */
+
+ regs = _arm_doirq(irq, regs);
+
+ /* Then loop dispatching any pending SGI interrupts that occcurred during
+ * processing of the interrupts.
+ */
+
+ for (i = 0; i < 16 && g_sgi_pending[cpu] != 0; i++)
+ {
+ /* Check if this SGI is pending */
+
+ bit = (1 << i);
+ if ((g_sgi_pending[cpu] & bit) != 0)
+ {
+ /* Clear the pending bit */
+
+ g_sgi_pending[cpu] &= ~bit;
+
+ /* And dispatch the SGI */
+
+ sinfo("Dispatching pending SGI%d\n", i + GIC_IRQ_SGI0);
+ regs = _arm_doirq(i + GIC_IRQ_SGI0, regs);
+ }
+ }
#endif
board_autoled_off(LED_INIRQ);
return regs;
}
+#endif
diff --git a/arch/arm/src/armv7-a/arm_gicv2.c b/arch/arm/src/armv7-a/arm_gicv2.c
index 990a2c66dd3dd11ae2e9d58e6ab6dc020ecef858..ec32fa5271072f011e78732f7514b125f2abfe95 100644
--- a/arch/arm/src/armv7-a/arm_gicv2.c
+++ b/arch/arm/src/armv7-a/arm_gicv2.c
@@ -122,10 +122,10 @@ void arm_gic0_initialize(void)
}
#ifdef CONFIG_SMP
- /* Attach SGI interrupt handlers */
+ /* Attach SGI interrupt handlers. This attaches the handler for all CPUs. */
- DEBUGVERIFY(irq_attach(GIC_IRQ_SGI1, arm_start_handler));
- DEBUGVERIFY(irq_attach(GIC_IRQ_SGI2, arm_pause_handler));
+ DEBUGVERIFY(irq_attach(GIC_IRQ_SGI1, arm_start_handler, NULL));
+ DEBUGVERIFY(irq_attach(GIC_IRQ_SGI2, arm_pause_handler, NULL));
#endif
arm_gic_dump("Exit arm_gic0_initialize", true, 0);
@@ -387,7 +387,7 @@ uint32_t *arm_decodeirq(uint32_t *regs)
regval = getreg32(GIC_ICCIAR);
irq = (regval & GIC_ICCIAR_INTID_MASK) >> GIC_ICCIAR_INTID_SHIFT;
- gicllvdbg("irq=%d\n", irq);
+ irqinfo("irq=%d\n", irq);
/* Ignore spurions IRQs. ICCIAR will report 1023 if there is no pending
* interrupt.
@@ -574,5 +574,4 @@ int arm_gic_irq_trigger(int irq, bool edge)
return -EINVAL;
}
-
#endif /* CONFIG_ARMV7A_HAVE_GICv2 */
diff --git a/arch/arm/src/armv7-a/arm_gicv2_dump.c b/arch/arm/src/armv7-a/arm_gicv2_dump.c
index 9e4dfa340f1f97b25cdf3c55dce81d9f1610012e..23e43738da24a1716663f518a2294a08c1306a4f 100644
--- a/arch/arm/src/armv7-a/arm_gicv2_dump.c
+++ b/arch/arm/src/armv7-a/arm_gicv2_dump.c
@@ -40,12 +40,12 @@
#include
#include
-#include
+#include
#include "up_arch.h"
#include "gic.h"
-#if defined(CONFIG_ARMV7A_HAVE_GICv2) && defined(CONFIG_DEBUG_IRQ)
+#if defined(CONFIG_ARMV7A_HAVE_GICv2) && defined(CONFIG_DEBUG_IRQ_INFO)
/****************************************************************************
* Private Functions
@@ -69,22 +69,22 @@
static inline void arm_gic_dump_cpu(bool all, int irq, int nlines)
{
- lowsyslog(LOG_INFO, " CPU Interface Registers:\n");
- lowsyslog(LOG_INFO, " ICR: %08x PMR: %08x BPR: %08x IAR: %08x\n",
- getreg32(GIC_ICCICR), getreg32(GIC_ICCPMR),
- getreg32(GIC_ICCBPR), getreg32(GIC_ICCIAR));
- lowsyslog(LOG_INFO, " RPR: %08x HPIR: %08x ABPR: %08x\n",
- getreg32(GIC_ICCRPR), getreg32(GIC_ICCHPIR),
- getreg32(GIC_ICCABPR));
- lowsyslog(LOG_INFO, " AIAR: %08x AHPIR: %08x IDR: %08x\n",
- getreg32(GIC_ICCAIAR), getreg32(GIC_ICCAHPIR),
- getreg32(GIC_ICCIDR));
- lowsyslog(LOG_INFO, " APR1: %08x APR2: %08x APR3: %08x APR4: %08x\n",
- getreg32(GIC_ICCAPR1), getreg32(GIC_ICCAPR2),
- getreg32(GIC_ICCAPR3), getreg32(GIC_ICCAPR4));
- lowsyslog(LOG_INFO, " NSAPR1: %08x NSAPR2: %08x NSAPR3: %08x NSAPR4: %08x\n",
- getreg32(GIC_ICCNSAPR1), getreg32(GIC_ICCNSAPR2),
- getreg32(GIC_ICCNSAPR3), getreg32(GIC_ICCNSAPR4));
+ irqinfo(" CPU Interface Registers:\n");
+ irqinfo(" ICR: %08x PMR: %08x BPR: %08x IAR: %08x\n",
+ getreg32(GIC_ICCICR), getreg32(GIC_ICCPMR),
+ getreg32(GIC_ICCBPR), getreg32(GIC_ICCIAR));
+ irqinfo(" RPR: %08x HPIR: %08x ABPR: %08x\n",
+ getreg32(GIC_ICCRPR), getreg32(GIC_ICCHPIR),
+ getreg32(GIC_ICCABPR));
+ irqinfo(" AIAR: %08x AHPIR: %08x IDR: %08x\n",
+ getreg32(GIC_ICCAIAR), getreg32(GIC_ICCAHPIR),
+ getreg32(GIC_ICCIDR));
+ irqinfo(" APR1: %08x APR2: %08x APR3: %08x APR4: %08x\n",
+ getreg32(GIC_ICCAPR1), getreg32(GIC_ICCAPR2),
+ getreg32(GIC_ICCAPR3), getreg32(GIC_ICCAPR4));
+ irqinfo(" NSAPR1: %08x NSAPR2: %08x NSAPR3: %08x NSAPR4: %08x\n",
+ getreg32(GIC_ICCNSAPR1), getreg32(GIC_ICCNSAPR2),
+ getreg32(GIC_ICCNSAPR3), getreg32(GIC_ICCNSAPR4));
}
/****************************************************************************
@@ -110,9 +110,9 @@ static void arm_gic_dumpregs(uintptr_t regaddr, int nlines, int incr)
incr <<= 2;
for (i = 0; i < nlines; i += incr, regaddr += 16)
{
- lowsyslog(LOG_INFO, " %08x %08x %08x %08x\n",
- getreg32(regaddr), getreg32(regaddr + 4),
- getreg32(regaddr + 8), getreg32(regaddr + 12));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(regaddr), getreg32(regaddr + 4),
+ getreg32(regaddr + 8), getreg32(regaddr + 12));
}
}
@@ -135,7 +135,7 @@ static void arm_gic_dumpregs(uintptr_t regaddr, int nlines, int incr)
static inline void arm_gic_dump4(const char *name, uintptr_t regaddr,
int nlines)
{
- lowsyslog(LOG_INFO, " %s[%08lx]\n", name, (unsigned long)regaddr);
+ irqinfo(" %s[%08lx]\n", name, (unsigned long)regaddr);
arm_gic_dumpregs(regaddr, nlines, 4);
}
@@ -158,7 +158,7 @@ static inline void arm_gic_dump4(const char *name, uintptr_t regaddr,
static inline void arm_gic_dump8(const char *name, uintptr_t regaddr,
int nlines)
{
- lowsyslog(LOG_INFO, " %s[%08lx]\n", name, (unsigned long)regaddr);
+ irqinfo(" %s[%08lx]\n", name, (unsigned long)regaddr);
arm_gic_dumpregs(regaddr, nlines, 8);
}
@@ -181,7 +181,7 @@ static inline void arm_gic_dump8(const char *name, uintptr_t regaddr,
static inline void arm_gic_dump16(const char *name, uintptr_t regaddr,
int nlines)
{
- lowsyslog(LOG_INFO, " %s[%08lx]\n", name, (unsigned long)regaddr);
+ irqinfo(" %s[%08lx]\n", name, (unsigned long)regaddr);
arm_gic_dumpregs(regaddr, nlines, 16);
}
@@ -204,7 +204,7 @@ static inline void arm_gic_dump16(const char *name, uintptr_t regaddr,
static inline void arm_gic_dump32(const char *name, uintptr_t regaddr,
int nlines)
{
- lowsyslog(LOG_INFO, " %s[%08lx]\n", name, (unsigned long)regaddr);
+ irqinfo(" %s[%08lx]\n", name, (unsigned long)regaddr);
arm_gic_dumpregs(regaddr, nlines, 32);
}
@@ -226,10 +226,10 @@ static inline void arm_gic_dump32(const char *name, uintptr_t regaddr,
static inline void arm_gic_dump_distributor(bool all, int irq, int nlines)
{
- lowsyslog(LOG_INFO, " Distributor Registers:\n");
- lowsyslog(LOG_INFO, " DCR: %08x ICTR: %08x IIDR: %08x\n",
- getreg32(GIC_ICDDCR), getreg32(GIC_ICDICTR),
- getreg32(GIC_ICDIIDR));
+ irqinfo(" Distributor Registers:\n");
+ irqinfo(" DCR: %08x ICTR: %08x IIDR: %08x\n",
+ getreg32(GIC_ICDDCR), getreg32(GIC_ICDICTR),
+ getreg32(GIC_ICDIIDR));
if (all)
{
@@ -246,27 +246,27 @@ static inline void arm_gic_dump_distributor(bool all, int irq, int nlines)
}
else
{
- lowsyslog(LOG_INFO, " ISR: %08x ISER: %08x ISPR: %08x SAR: %08x\n",
- getreg32(GIC_ICDISR(irq)), getreg32(GIC_ICDISER(irq)),
- getreg32(GIC_ICDISPR(irq)), getreg32(GIC_ICDSAR(irq)));
- lowsyslog(LOG_INFO, " IPR: %08x IPTR: %08x ICFR: %08x SPISR: %08x\n",
- getreg32(GIC_ICDIPR(irq)), getreg32(GIC_ICDIPTR(irq)),
- getreg32(GIC_ICDICFR(irq)), getreg32(GIC_ICDSPISR(irq)));
- lowsyslog(LOG_INFO, " NSACR: %08x SCPR: %08x\n",
- getreg32(GIC_ICDNSACR(irq)), getreg32(GIC_ICDSCPR(irq)));
+ irqinfo(" ISR: %08x ISER: %08x ISPR: %08x SAR: %08x\n",
+ getreg32(GIC_ICDISR(irq)), getreg32(GIC_ICDISER(irq)),
+ getreg32(GIC_ICDISPR(irq)), getreg32(GIC_ICDSAR(irq)));
+ irqinfo(" IPR: %08x IPTR: %08x ICFR: %08x SPISR: %08x\n",
+ getreg32(GIC_ICDIPR(irq)), getreg32(GIC_ICDIPTR(irq)),
+ getreg32(GIC_ICDICFR(irq)), getreg32(GIC_ICDSPISR(irq)));
+ irqinfo(" NSACR: %08x SCPR: %08x\n",
+ getreg32(GIC_ICDNSACR(irq)), getreg32(GIC_ICDSCPR(irq)));
}
- lowsyslog(LOG_INFO, " PIDR[%08lx]:\n", (unsigned long)GIC_ICDPIDR(0));
- lowsyslog(LOG_INFO, " %08x %08x %08x %08x\n",
- getreg32(GIC_ICDPIDR(0)), getreg32(GIC_ICDPIDR(1)),
- getreg32(GIC_ICDPIDR(2)), getreg32(GIC_ICDPIDR(3)));
- lowsyslog(LOG_INFO, " %08x %08x %08x %08x\n",
- getreg32(GIC_ICDPIDR(4)), getreg32(GIC_ICDPIDR(5)),
- getreg32(GIC_ICDPIDR(6)));
- lowsyslog(LOG_INFO, " CIDR[%08lx]:\n", (unsigned long)GIC_ICDCIDR(0));
- lowsyslog(LOG_INFO, " %08x %08x %08x %08x\n",
- getreg32(GIC_ICDCIDR(0)), getreg32(GIC_ICDCIDR(1)),
- getreg32(GIC_ICDCIDR(2)), getreg32(GIC_ICDCIDR(3)));
+ irqinfo(" PIDR[%08lx]:\n", (unsigned long)GIC_ICDPIDR(0));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(GIC_ICDPIDR(0)), getreg32(GIC_ICDPIDR(1)),
+ getreg32(GIC_ICDPIDR(2)), getreg32(GIC_ICDPIDR(3)));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(GIC_ICDPIDR(4)), getreg32(GIC_ICDPIDR(5)),
+ getreg32(GIC_ICDPIDR(6)));
+ irqinfo(" CIDR[%08lx]:\n", (unsigned long)GIC_ICDCIDR(0));
+ irqinfo(" %08x %08x %08x %08x\n",
+ getreg32(GIC_ICDCIDR(0)), getreg32(GIC_ICDCIDR(1)),
+ getreg32(GIC_ICDCIDR(2)), getreg32(GIC_ICDCIDR(3)));
}
/****************************************************************************
@@ -295,15 +295,15 @@ void arm_gic_dump(const char *msg, bool all, int irq)
if (all)
{
- lowsyslog(LOG_INFO, "GIC: %s NLINES=%u\n", msg, nlines);
+ irqinfo("GIC: %s NLINES=%u\n", msg, nlines);
}
else
{
- lowsyslog(LOG_INFO, "GIC: %s IRQ=%d\n", msg, irq);
+ irqinfo("GIC: %s IRQ=%d\n", msg, irq);
}
arm_gic_dump_cpu(all, irq, nlines);
arm_gic_dump_distributor(all, irq, nlines);
}
-#endif /* CONFIG_ARMV7A_HAVE_GICv2 && CONFIG_DEBUG_IRQ */
+#endif /* CONFIG_ARMV7A_HAVE_GICv2 && CONFIG_DEBUG_IRQ_INFO */
diff --git a/arch/arm/src/armv7-a/arm_head.S b/arch/arm/src/armv7-a/arm_head.S
index 220026da340758619e11b7ec48c3b122957a5975..27c2a5b4dcfb628db63ee069385070ef01a39735 100644
--- a/arch/arm/src/armv7-a/arm_head.S
+++ b/arch/arm/src/armv7-a/arm_head.S
@@ -169,7 +169,7 @@
/* This macro will modify r0, r1, r2 and r14 */
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
.macro showprogress, code
mov r0, #\code
bl up_lowputc
@@ -450,7 +450,11 @@ __start:
orr r0, r0, #(SCTLR_RR)
#endif
-#ifndef CPU_DCACHE_DISABLE
+ /* In SMP configurations, the data cache will not be enabled until later
+ * after SMP cache coherency has been setup.
+ */
+
+#if !defined(CPU_DCACHE_DISABLE) && !defined(CONFIG_SMP)
/* Dcache enable
*
* SCTLR_C Bit 2: DCache enable
@@ -638,7 +642,7 @@ __start:
#endif
/* Perform early C-level, platform-specific initialization. Logic
- * within arm_boot() must configure SDRAM and call arm_ram_initailize.
+ * within arm_boot() must configure SDRAM and call arm_data_initialize().
*/
bl arm_boot
diff --git a/arch/arm/src/armv7-a/arm_l2cc_pl310.c b/arch/arm/src/armv7-a/arm_l2cc_pl310.c
index 64aeaf3b8bc61cbec7dc990fee8011650c961de3..9d455e40d270d8daec5a960739716f01599fcbfe 100644
--- a/arch/arm/src/armv7-a/arm_l2cc_pl310.c
+++ b/arch/arm/src/armv7-a/arm_l2cc_pl310.c
@@ -411,7 +411,7 @@ void up_l2ccinitialize(void)
putreg32(L2CC_CR_L2CEN, L2CC_CR);
}
- lldbg("(%d ways) * (%d bytes/way) = %d bytes\n",
+ sinfo("(%d ways) * (%d bytes/way) = %d bytes\n",
PL310_NWAYS, PL310_WAYSIZE, PL310_CACHE_SIZE);
}
diff --git a/arch/arm/src/armv7-a/arm_pghead.S b/arch/arm/src/armv7-a/arm_pghead.S
index bc4c99ce26da187dc4508f79e9737b4663ca1fbf..1dda0acdd929ba56db8fa450e68d781300c084df 100644
--- a/arch/arm/src/armv7-a/arm_pghead.S
+++ b/arch/arm/src/armv7-a/arm_pghead.S
@@ -194,7 +194,7 @@
/* This macro will modify r0, r1, r2 and r14 */
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_FEATURES
.macro showprogress, code
mov r0, #\code
bl up_lowputc
@@ -434,7 +434,11 @@ __start:
orr r0, r0, #(SCTLR_RR)
#endif
-#ifndef CPU_DCACHE_DISABLE
+ /* In SMP configurations, the data cache will not be enabled until later
+ * after SMP cache coherency has been setup.
+ */
+
+#if !defined(CPU_DCACHE_DISABLE) && !defined(CONFIG_SMP)
/* Dcache enable
*
* SCTLR_C Bit 2: DCache enable
@@ -670,7 +674,7 @@ __start:
#endif
/* Perform early C-level, platform-specific initialization. Logic
- * within arm_boot() must configure SDRAM and call arm_ram_initailize.
+ * within arm_boot() must configure SDRAM and call arm_data_initialize().
*/
bl arm_boot
diff --git a/arch/arm/src/armv7-a/arm_prefetchabort.c b/arch/arm/src/armv7-a/arm_prefetchabort.c
index bdd28c4a3aa72505bd66d469e5d6bcf24dddeee5..0bb8cd37932f68ed9c101f5ad575b3a7f7f16f38 100644
--- a/arch/arm/src/armv7-a/arm_prefetchabort.c
+++ b/arch/arm/src/armv7-a/arm_prefetchabort.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv7-a/arm_prefetchabort.c
*
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
@@ -97,8 +86,8 @@ uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr)
* virtual addresses.
*/
- pglldbg("VADDR: %08x VBASE: %08x VEND: %08x\n",
- regs[REG_PC], PG_PAGED_VBASE, PG_PAGED_VEND);
+ pginfo("VADDR: %08x VBASE: %08x VEND: %08x\n",
+ regs[REG_PC], PG_PAGED_VBASE, PG_PAGED_VEND);
if (regs[REG_R15] >= PG_PAGED_VBASE && regs[REG_R15] < PG_PAGED_VEND)
{
@@ -134,7 +123,7 @@ uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr)
}
else
{
- lldbg("Prefetch abort. PC: %08x IFAR: %08x IFSR: %08x\n",
+ _alert("Prefetch abort. PC: %08x IFAR: %08x IFSR: %08x\n",
regs[REG_PC], ifar, ifsr);
PANIC();
}
@@ -154,7 +143,7 @@ uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr)
/* Crash -- possibly showing diagnostic debug information. */
- lldbg("Prefetch abort. PC: %08x IFAR: %08x IFSR: %08x\n",
+ _alert("Prefetch abort. PC: %08x IFAR: %08x IFSR: %08x\n",
regs[REG_PC], ifar, ifsr);
PANIC();
return regs; /* To keep the compiler happy */
diff --git a/arch/arm/src/armv7-a/arm_releasepending.c b/arch/arm/src/armv7-a/arm_releasepending.c
index 9696e931c0bdb7643535b0aa3e795eb237cb9c8c..7afc6989a75829f647ee14ba35e2a6b3ef991415 100644
--- a/arch/arm/src/armv7-a/arm_releasepending.c
+++ b/arch/arm/src/armv7-a/arm_releasepending.c
@@ -67,7 +67,7 @@ void up_release_pending(void)
{
struct tcb_s *rtcb = this_task();
- slldbg("From TCB=%p\n", rtcb);
+ sinfo("From TCB=%p\n", rtcb);
/* Merge the g_pendingtasks list into the ready-to-run task list */
diff --git a/arch/arm/src/armv7-a/arm_reprioritizertr.c b/arch/arm/src/armv7-a/arm_reprioritizertr.c
index d4b2699f6dd01f2a3cc0c3be38038f1961c18c6e..4381178e05b311e620c620b6d9465e10cec5a333 100644
--- a/arch/arm/src/armv7-a/arm_reprioritizertr.c
+++ b/arch/arm/src/armv7-a/arm_reprioritizertr.c
@@ -95,7 +95,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
struct tcb_s *rtcb = this_task();
bool switch_needed;
- slldbg("TCB=%p PRI=%d\n", tcb, priority);
+ sinfo("TCB=%p PRI=%d\n", tcb, priority);
/* Remove the tcb task from the ready-to-run list.
* sched_removereadytorun will return true if we just
diff --git a/arch/arm/src/armv7-a/arm_schedulesigaction.c b/arch/arm/src/armv7-a/arm_schedulesigaction.c
index 3dfe5fc285f7c9a5f4de4a519107067c5ca1bb34..9f1a46f67542b2a245d73006af5bec0462302d7a 100644
--- a/arch/arm/src/armv7-a/arm_schedulesigaction.c
+++ b/arch/arm/src/armv7-a/arm_schedulesigaction.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv7-a/arm_schedulesigaction.c
*
- * Copyright (C) 2013, 2015-2016 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2015-2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -51,6 +51,8 @@
#include "up_internal.h"
#include "up_arch.h"
+#include "irq/irq.h"
+
#ifndef CONFIG_DISABLE_SIGNALS
/****************************************************************************
@@ -90,11 +92,12 @@
*
****************************************************************************/
+#ifndef CONFIG_SMP
void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
{
irqstate_t flags;
- sdbg("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
+ sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
/* Make sure that interrupts are disabled */
@@ -105,10 +108,10 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
if (!tcb->xcp.sigdeliver)
{
/* First, handle some special cases when the signal is being delivered
- * to the currently executing task.
+ * to task that is currently executing on this CPU.
*/
- sdbg("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
+ sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
if (tcb == this_task())
{
@@ -142,16 +145,16 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* the signals have been delivered.
*/
- tcb->xcp.sigdeliver = sigdeliver;
- tcb->xcp.saved_pc = CURRENT_REGS[REG_PC];
- tcb->xcp.saved_cpsr = CURRENT_REGS[REG_CPSR];
+ tcb->xcp.sigdeliver = sigdeliver;
+ tcb->xcp.saved_pc = CURRENT_REGS[REG_PC];
+ tcb->xcp.saved_cpsr = CURRENT_REGS[REG_CPSR];
/* Then set up to vector to the trampoline with interrupts
* disabled
*/
- CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver;
- CURRENT_REGS[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
+ CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver;
+ CURRENT_REGS[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
/* And make sure that the saved context in the TCB is the same
* as the interrupt return context.
@@ -163,7 +166,168 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
/* Otherwise, we are (1) signaling a task is not running from an
* interrupt handler or (2) we are not in an interrupt handler and the
- * running task is signalling some non-running task.
+ * running task is signalling some other non-running task.
+ */
+
+ else
+ {
+ /* Save the return lr and cpsr and one scratch register. These
+ * will be restored by the signal trampoline after the signals
+ * have been delivered.
+ */
+
+ tcb->xcp.sigdeliver = sigdeliver;
+ tcb->xcp.saved_pc = tcb->xcp.regs[REG_PC];
+ tcb->xcp.saved_cpsr = tcb->xcp.regs[REG_CPSR];
+
+ /* Then set up to vector to the trampoline with interrupts
+ * disabled
+ */
+
+ tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
+ tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
+ }
+ }
+
+ leave_critical_section(flags);
+}
+#endif /* !CONFIG_SMP */
+
+#ifdef CONFIG_SMP
+void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
+{
+ irqstate_t flags;
+ int cpu;
+ int me;
+
+ sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
+
+ /* Make sure that interrupts are disabled */
+
+ flags = enter_critical_section();
+
+ /* Refuse to handle nested signal actions */
+
+ if (!tcb->xcp.sigdeliver)
+ {
+ /* First, handle some special cases when the signal is being delivered
+ * to task that is currently executing on any CPU.
+ */
+
+ sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
+
+ if (tcb->task_state == TSTATE_TASK_RUNNING)
+ {
+ me = this_cpu();
+ cpu = tcb->cpu;
+
+ /* CASE 1: We are not in an interrupt handler and a task is
+ * signalling itself for some reason.
+ */
+
+ if (cpu == me && !CURRENT_REGS)
+ {
+ /* In this case just deliver the signal now. */
+
+ sigdeliver(tcb);
+ }
+
+ /* CASE 2: The task that needs to receive the signal is running.
+ * This could happen if the task is running on another CPU OR if
+ * we are in an interrupt handler and the task is running on this
+ * CPU. In the former case, we will have to PAUSE the other CPU
+ * first. But in either case, we will have to modify the return
+ * state as well as the state in the TCB.
+ *
+ * Hmmm... there looks like a latent bug here: The following logic
+ * would fail in the strange case where we are in an interrupt
+ * handler, the thread is signalling itself, but a context switch
+ * to another task has occurred so that CURRENT_REGS does not
+ * refer to the thread of this_task()!
+ */
+
+ else
+ {
+ /* If we signalling a task running on the other CPU, we have
+ * to PAUSE the other CPU.
+ */
+
+ if (cpu != me)
+ {
+ up_cpu_pause(cpu);
+ }
+
+ /* Save the return lr and cpsr and one scratch register
+ * These will be restored by the signal trampoline after
+ * the signals have been delivered.
+ */
+
+ tcb->xcp.sigdeliver = sigdeliver;
+ tcb->xcp.saved_pc = CURRENT_REGS[REG_PC];
+ tcb->xcp.saved_cpsr = CURRENT_REGS[REG_CPSR];
+
+ /* Increment the IRQ lock count so that when the task is restarted,
+ * it will hold the IRQ spinlock.
+ */
+
+ DEBUGASSERT(tcb->irqcount < INT16_MAX);
+ tcb->irqcount++;
+
+ /* Handle a possible race condition where the TCB was suspended
+ * just before we paused the other CPU. The critical section
+ * established above will prevent new threads from running on
+ * that CPU, but it will not guarantee that the running thread
+ * did not suspend itself (allowing any threads "assigned" to
+ * the CPU to run).
+ */
+
+ if (tcb->task_state != TSTATE_TASK_RUNNING)
+ {
+ /* Then set up to vector to the trampoline with interrupts
+ * disabled
+ */
+
+ tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
+ tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
+ }
+ else
+ {
+ /* Then set up to vector to the trampoline with interrupts
+ * disabled
+ */
+
+ CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver;
+ CURRENT_REGS[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
+
+ /* In an SMP configuration, the interrupt disable logic also
+ * involves spinlocks that are configured per the TCB irqcount
+ * field. This is logically equivalent to enter_critical_section().
+ * The matching call to leave_critical_section() will be
+ * performed in up_sigdeliver().
+ */
+
+ spin_setbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock,
+ &g_cpu_irqlock);
+
+ /* And make sure that the saved context in the TCB is the same
+ * as the interrupt return context.
+ */
+
+ up_savestate(tcb->xcp.regs);
+ }
+
+ /* RESUME the other CPU if it was PAUSED */
+
+ if (cpu != me)
+ {
+ up_cpu_resume(cpu);
+ }
+ }
+ }
+
+ /* Otherwise, we are (1) signaling a task is not running from an
+ * interrupt handler or (2) we are not in an interrupt handler and the
+ * running task is signalling some other non-running task.
*/
else
@@ -173,20 +337,28 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* have been delivered.
*/
- tcb->xcp.sigdeliver = sigdeliver;
- tcb->xcp.saved_pc = tcb->xcp.regs[REG_PC];
- tcb->xcp.saved_cpsr = tcb->xcp.regs[REG_CPSR];
+ tcb->xcp.sigdeliver = sigdeliver;
+ tcb->xcp.saved_pc = tcb->xcp.regs[REG_PC];
+ tcb->xcp.saved_cpsr = tcb->xcp.regs[REG_CPSR];
+
+ /* Increment the IRQ lock count so that when the task is restarted,
+ * it will hold the IRQ spinlock.
+ */
+
+ DEBUGASSERT(tcb->irqcount < INT16_MAX);
+ tcb->irqcount++;
/* Then set up to vector to the trampoline with interrupts
* disabled
*/
- tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
- tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
+ tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
+ tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
}
}
leave_critical_section(flags);
}
+#endif /* CONFIG_SMP */
#endif /* !CONFIG_DISABLE_SIGNALS */
diff --git a/arch/arm/src/armv7-a/arm_scu.c b/arch/arm/src/armv7-a/arm_scu.c
new file mode 100644
index 0000000000000000000000000000000000000000..eedf179e73161438d738872ce2af869d634cd3b5
--- /dev/null
+++ b/arch/arm/src/armv7-a/arm_scu.c
@@ -0,0 +1,227 @@
+/****************************************************************************
+ * arch/arm/src/armv7-a/arm_scu.c
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include
+
+#include
+
+#include "up_arch.h"
+#include "cp15_cacheops.h"
+#include "sctlr.h"
+#include "cache.h"
+#include "scu.h"
+
+#ifdef CONFIG_SMP
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arm_get_sctlr
+ *
+ * Description:
+ * Get the contents of the SCTLR register
+ *
+ ****************************************************************************/
+
+static inline uint32_t arm_get_sctlr(void)
+{
+ uint32_t sctlr;
+
+ __asm__ __volatile__
+ (
+ "\tmrc p15, 0, %0, c1, c0, 0\n" /* Read SCTLR */
+ : "=r"(sctlr)
+ :
+ :
+ );
+
+ return sctlr;
+}
+
+/****************************************************************************
+ * Name: arm_set_sctlr
+ *
+ * Description:
+ * Set the contents of the SCTLR register
+ *
+ ****************************************************************************/
+
+static inline void arm_set_sctlr(uint32_t sctlr)
+{
+ __asm__ __volatile__
+ (
+ "\tmcr p15, 0, %0, c1, c0, 0\n" /* Write SCTLR */
+ :
+ : "r"(sctlr)
+ :
+ );
+}
+
+/****************************************************************************
+ * Name: arm_get_actlr
+ *
+ * Description:
+ * Get the contents of the ACTLR register
+ *
+ ****************************************************************************/
+
+static inline uint32_t arm_get_actlr(void)
+{
+ uint32_t actlr;
+
+ __asm__ __volatile__
+ (
+ "\tmrc p15, 0, %0, c1, c0, 1\n" /* Read ACTLR */
+ : "=r"(actlr)
+ :
+ :
+ );
+
+ return actlr;
+}
+
+/****************************************************************************
+ * Name: arm_set_actlr
+ *
+ * Description:
+ * Set the contents of the ACTLR register
+ *
+ ****************************************************************************/
+
+static inline void arm_set_actlr(uint32_t actlr)
+{
+ __asm__ __volatile__
+ (
+ "\tmcr p15, 0, %0, c1, c0, 1\n" /* Write ACTLR */
+ :
+ : "r"(actlr)
+ :
+ );
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arm_enable_smp
+ *
+ * Description:
+ * Enable the SCU and make certain that current CPU is participating in
+ * the SMP cache coherency.
+ *
+ * Assumption:
+ * Called early in the CPU start-up. No special critical sections are
+ * needed if only CPU-private registers are modified.
+ *
+ ****************************************************************************/
+
+void arm_enable_smp(int cpu)
+{
+ uint32_t regval;
+
+ /* Handle actions unique to CPU0 which comes up first */
+
+ if (cpu == 0)
+ {
+ /* Invalidate the SCU duplicate tags for all processors */
+
+ putreg32((SCU_INVALIDATE_ALL_WAYS << SCU_INVALIDATE_CPU0_SHIFT) |
+ (SCU_INVALIDATE_ALL_WAYS << SCU_INVALIDATE_CPU1_SHIFT) |
+ (SCU_INVALIDATE_ALL_WAYS << SCU_INVALIDATE_CPU2_SHIFT) |
+ (SCU_INVALIDATE_ALL_WAYS << SCU_INVALIDATE_CPU3_SHIFT),
+ SCU_INVALIDATE);
+
+ /* Invalidate CPUn L1 data cache so that is will we be reloaded from
+ * coherent L2.
+ */
+
+ cp15_invalidate_dcache_all();
+ ARM_DSB();
+
+ /* Invalidate the L2C-310 -- Missing logic. */
+
+ /* Enable the SCU */
+
+ regval = getreg32(SCU_CTRL);
+ regval |= SCU_CTRL_ENABLE;
+ putreg32(regval, SCU_CTRL);
+ }
+
+ /* Actions for other CPUs */
+
+ else
+ {
+ /* Invalidate CPUn L1 data cache so that is will we be reloaded from
+ * coherent L2.
+ */
+
+ cp15_invalidate_dcache_all();
+ ARM_DSB();
+
+ /* Wait for the SCU to be enabled by the primary processor -- should
+ * not be necessary.
+ */
+ }
+
+ /* Enable the data cache, set the SMP mode with ACTLR.SMP=1.
+ *
+ * SMP - Sgnals if the Cortex-A9 processor is taking part in coherency
+ * or not.
+ *
+ * Cortex-A9 also needs ACTLR.FW=1
+ *
+ * FW - Cache and TLB maintenance broadcast.
+ */
+
+ regval = arm_get_actlr();
+ regval |= ACTLR_SMP;
+#ifdef CONFIG_ARCH_CORTEXA9
+ regval |= ACTLR_FW;
+#endif
+ arm_set_actlr(regval);
+
+ regval = arm_get_sctlr();
+ regval |= SCTLR_C;
+ arm_set_sctlr(regval);
+}
+
+#endif
diff --git a/arch/arm/src/armv7-a/arm_sigdeliver.c b/arch/arm/src/armv7-a/arm_sigdeliver.c
index 32f1e0b40d1219f98a282c6ca98fa5c7070bcc6a..5d89583282032ac543a151682ff517f94b31b212 100644
--- a/arch/arm/src/armv7-a/arm_sigdeliver.c
+++ b/arch/arm/src/armv7-a/arm_sigdeliver.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv7-a/arm_sigdeliver.c
*
- * Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -83,7 +83,7 @@ void up_sigdeliver(void)
board_autoled_on(LED_SIGNAL);
- sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
+ sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
ASSERT(rtcb->xcp.sigdeliver != NULL);
@@ -103,18 +103,27 @@ void up_sigdeliver(void)
/* Then restore the task interrupt state */
- up_irq_restore(regs[REG_CPSR]);
+ leave_critical_section(regs[REG_CPSR]);
- /* Deliver the signals */
+ /* Deliver the signal */
sigdeliver(rtcb);
/* Output any debug messages BEFORE restoring errno (because they may
* alter errno), then disable interrupts again and restore the original
* errno that is needed by the user logic (it is probably EINTR).
+ *
+ * REVISIT: In SMP mode up_irq_save() probably only disables interrupts
+ * on the local CPU. We do not want to call enter_critical_section()
+ * here, however, because we don't want this state to stick after the
+ * call to up_fullcontextrestore().
+ *
+ * I would prefer that all interrupts are disabled when
+ * up_fullcontextrestore() is called, but that may not be necessary.
*/
- sdbg("Resuming\n");
+ sinfo("Resuming\n");
+
(void)up_irq_save();
rtcb->pterrno = saved_errno;
diff --git a/arch/arm/src/armv7-a/arm_syscall.c b/arch/arm/src/armv7-a/arm_syscall.c
index 854ece3de2cdf789db4e59069a03236733dd78da..77b33b45f4be7954bc50389d3c3d8ccade7776eb 100644
--- a/arch/arm/src/armv7-a/arm_syscall.c
+++ b/arch/arm/src/armv7-a/arm_syscall.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv7-a/arm_syscall.c
*
- * Copyright (C) 2013-2014 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013-2014, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
#include
@@ -65,17 +54,6 @@
#include "addrenv.h"
#include "up_internal.h"
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-/* Debug ********************************************************************/
-
-#if defined(CONFIG_DEBUG_SYSCALL)
-# define svcdbg(format, ...) lldbg(format, ##__VA_ARGS__)
-#else
-# define svcdbg(x...)
-#endif
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -178,16 +156,14 @@ uint32_t *arm_syscall(uint32_t *regs)
* and R1..R7 = variable number of arguments depending on the system call.
*/
-#if defined(CONFIG_DEBUG_SYSCALL)
- svcdbg("SYSCALL Entry: regs: %p cmd: %d\n", regs, cmd);
- svcdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
- regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
- svcdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
- regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
- svcdbg("CPSR: %08x\n", regs[REG_CPSR]);
-#endif
+ svcinfo("SYSCALL Entry: regs: %p cmd: %d\n", regs, cmd);
+ svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
+ regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
+ svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
+ regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
+ svcinfo("CPSR: %08x\n", regs[REG_CPSR]);
/* Handle the SVCall according to the command in R0 */
@@ -480,7 +456,7 @@ uint32_t *arm_syscall(uint32_t *regs)
regs[REG_R0] -= CONFIG_SYS_RESERVED;
#else
- svcdbg("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
+ svcerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
#endif
#ifdef CONFIG_ARCH_KERNEL_STACK
@@ -501,18 +477,16 @@ uint32_t *arm_syscall(uint32_t *regs)
break;
}
-#if defined(CONFIG_DEBUG_SYSCALL)
/* Report what happened */
- svcdbg("SYSCALL Exit: regs: %p\n", regs);
- svcdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
- regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
- svcdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
+ svcinfo("SYSCALL Exit: regs: %p\n", regs);
+ svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
+ regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
+ svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
- svcdbg("CPSR: %08x\n", regs[REG_CPSR]);
-#endif
+ svcinfo("CPSR: %08x\n", regs[REG_CPSR]);
/* Return the last value of curent_regs. This supports context switches
* on return from the exception. That capability is only used with the
@@ -526,7 +500,7 @@ uint32_t *arm_syscall(uint32_t *regs)
uint32_t *arm_syscall(uint32_t *regs)
{
- lldbg("SYSCALL from 0x%x\n", regs[REG_PC]);
+ _alert("SYSCALL from 0x%x\n", regs[REG_PC]);
CURRENT_REGS = regs;
PANIC();
}
diff --git a/arch/arm/src/armv7-a/arm_testset.S b/arch/arm/src/armv7-a/arm_testset.S
index 6d6cdcd4acb78859f48730a62024408df1df53de..638736e4d6729815674902098a7e3c867ee42760 100644
--- a/arch/arm/src/armv7-a/arm_testset.S
+++ b/arch/arm/src/armv7-a/arm_testset.S
@@ -70,12 +70,12 @@
* Name: up_testset
*
* Description:
- * Perform and atomic test and set operation on the provided spinlock.
+ * Perform an atomic test and set operation on the provided spinlock.
*
* This function must be provided via the architecture-specific logoic.
*
* Input Parameters:
- * lock - The address of spinlock object.
+ * lock - The address of spinlock object (r0).
*
* Returned Value:
* The spinlock is always locked upon return. The value of previous value
@@ -84,6 +84,8 @@
* obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked
* (meaning that we successfully obtained the lock)
*
+ * Modifies: r1, r2, and lr
+ *
****************************************************************************/
.globl up_testset
@@ -98,7 +100,7 @@ up_testset:
1:
ldrexb r2, [r0] /* Test if spinlock is locked or not */
cmp r2, r1 /* Already locked? */
- beq 2f /* If alrady locked, return SP_LOCKED */
+ beq 2f /* If already locked, return SP_LOCKED */
/* Not locked ... attempt to lock it */
diff --git a/arch/arm/src/armv7-a/arm_undefinedinsn.c b/arch/arm/src/armv7-a/arm_undefinedinsn.c
index 0c051d9dd916accbf64c8e0d35fb5a5ad801071d..54dbcc25b8a2aa0ce2da4506083a11934f1fef5e 100644
--- a/arch/arm/src/armv7-a/arm_undefinedinsn.c
+++ b/arch/arm/src/armv7-a/arm_undefinedinsn.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv7-a/arm_undefinedinsn.c
*
- * Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
#include
@@ -68,7 +57,7 @@
uint32_t *arm_undefinedinsn(uint32_t *regs)
{
- lldbg("Undefined instruction at 0x%x\n", regs[REG_PC]);
+ _alert("Undefined instruction at 0x%x\n", regs[REG_PC]);
CURRENT_REGS = regs;
PANIC();
return regs; /* To keep the compiler happy */
diff --git a/arch/arm/src/armv7-a/arm_vectors.S b/arch/arm/src/armv7-a/arm_vectors.S
index 33d1f8fc550dc6e49d4e7623e2a66892de87837d..8a76e000b563ec9c1c9e6a19322ce8e0af7ec0ff 100644
--- a/arch/arm/src/armv7-a/arm_vectors.S
+++ b/arch/arm/src/armv7-a/arm_vectors.S
@@ -64,6 +64,10 @@ g_fiqtmp:
.word 0 /* Saved lr */
.word 0 /* Saved spsr */
#endif
+#if CONFIG_ARCH_INTERRUPTSTACK > 3 && defined(CONFIG_ARMV7A_HAVE_GICv2)
+g_nestlevel:
+ .word 0 /* Interrupt nesting level */
+#endif
/************************************************************************************
* Private Functions
@@ -172,13 +176,53 @@ arm_vectorirq:
mov r0, sp /* Get r0=xcp */
#if CONFIG_ARCH_INTERRUPTSTACK > 3
+#ifdef CONFIG_ARMV7A_HAVE_GICv2
+ /* We will switch to the interrupt stack, UNLESS we are processing a
+ * nested interrupt in which case we are already using the interrupt
+ * stack. SGI interrupts may be nested because they are non-maskable.
+ */
+
+ ldr r5, .Lirqnestlevel /* r1=Points to interrupt nesting level */
+ ldr r1, [r5] /* Get r1= nesting level */
+ add r1, r1, #1 /* Increment nesting level */
+ str r1, [r5] /* Save r1= nesting level */
+
+ cmp r1, #1 /* r1>1 if nested */
+ bgt .Lintnested /* Use current SP if nested */
+#endif
+
+ /* Call arm_decodeirq() on the interrupt stack */
+
ldr sp, .Lirqstackbase /* SP = interrupt stack base */
str r0, [sp] /* Save the user stack pointer */
mov r4, sp /* Save the SP in a preserved register */
bic sp, sp, #7 /* Force 8-byte alignment */
bl arm_decodeirq /* Call the handler */
ldr sp, [r4] /* Restore the user stack pointer */
+
+#ifdef CONFIG_ARMV7A_HAVE_GICv2
+ b .Lintreturn
+
+ /* Call arm_decodeirq() on whatever stack is in place */
+
+.Lintnested:
+ mov r4, sp /* Save the SP in a preserved register */
+ bic sp, sp, #7 /* Force 8-byte alignment */
+ bl arm_decodeirq /* Call the handler */
+ mov sp, r4 /* Restore the possibly unaligned stack pointer */
+
+ /* Decrement the nesting level (r5 should be preserved) */
+
+.Lintreturn:
+ ldr r1, [r5] /* Get r1= nesting level */
+ cmp r1, #0 /* A sanity check*/
+ subgt r1, r1, #1 /* Decrement nesting level */
+ strgt r1, [r5] /* Save r1= nesting level */
+#endif
+
#else
+ /* Call arm_decodeirq() on the user stack */
+
mov r4, sp /* Save the SP in a preserved register */
bic sp, sp, #7 /* Force 8-byte alignment */
bl arm_decodeirq /* Call the handler */
@@ -227,6 +271,10 @@ arm_vectorirq:
#if CONFIG_ARCH_INTERRUPTSTACK > 3
.Lirqstackbase:
.word g_intstackbase
+#ifdef CONFIG_ARMV7A_HAVE_GICv2
+.Lirqnestlevel:
+ .word g_nestlevel
+#endif
#endif
.size arm_vectorirq, . - arm_vectorirq
.align 5
@@ -937,7 +985,7 @@ arm_vectorfiq:
.word g_fiqtmp
#if CONFIG_ARCH_INTERRUPTSTACK > 3
.Lfiqstackbase:
- .word g_intstackbase
+ .word g_fiqstackbase
#endif
#else
@@ -965,5 +1013,21 @@ g_intstackbase:
.size g_intstackbase, 4
.size g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~3)
+ .globl g_fiqstackalloc
+ .type g_fiqstackalloc, object
+ .globl g_fiqstackbase
+ .type g_fiqstackbase, object
+
+/************************************************************************************
+ * Name: g_fiqstackalloc/g_fiqstackbase
+ ************************************************************************************/
+
+g_fiqstackalloc:
+ .skip ((CONFIG_ARCH_INTERRUPTSTACK & ~3) - 4)
+g_fiqstackbase:
+ .skip 4
+ .size g_fiqstackbase, 4
+ .size g_fiqstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~3)
+
#endif /* CONFIG_ARCH_INTERRUPTSTACK > 3 */
.end
diff --git a/arch/arm/src/armv7-a/cache.h b/arch/arm/src/armv7-a/cache.h
index dda36271e2d865a5e2533e9201feea5952fc9845..c9af0611f7b31d4a16fac7ca43b299f68f08c283 100644
--- a/arch/arm/src/armv7-a/cache.h
+++ b/arch/arm/src/armv7-a/cache.h
@@ -50,6 +50,16 @@
* Pre-processor Definitions
************************************************************************************/
+/* Intrinsics are used in these inline functions */
+
+#define arm_isb(n) __asm__ __volatile__ ("isb " #n : : : "memory")
+#define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory")
+#define arm_dmb(n) __asm__ __volatile__ ("dmb " #n : : : "memory")
+
+#define ARM_DSB() arm_dsb(15)
+#define ARM_ISB() arm_isb(15)
+#define ARM_DMB() arm_dmb(15)
+
/************************************************************************************
* Inline Functions
************************************************************************************/
diff --git a/arch/arm/src/armv7-a/gic.h b/arch/arm/src/armv7-a/gic.h
index cc6ee4833004f661ec96a5f9d248d23944a7ff6b..8c882ad6ddc2c8711c978f0885c83fe11b8a9afa 100644
--- a/arch/arm/src/armv7-a/gic.h
+++ b/arch/arm/src/armv7-a/gic.h
@@ -590,21 +590,6 @@
#define GIC_IRQ_SPI 32 /* First SPI interrupt ID */
-/* General Macro Definitions ************************************************/
-/* Debug */
-
-#ifdef CONFIG_DEBUG_IRQ
-# define gicdbg(format, ...) dbg(format, ##__VA_ARGS__)
-# define giclldbg(format, ...) lldbg(format, ##__VA_ARGS__)
-# define gicvdbg(format, ...) vdbg(format, ##__VA_ARGS__)
-# define gicllvdbg(format, ...) llvdbg(format, ##__VA_ARGS__)
-#else
-# define gicdbg(x...)
-# define giclldbg(x...)
-# define gicvdbg(x...)
-# define gicllvdbg(x...)
-#endif
-
/****************************************************************************
* Inline Functions
****************************************************************************/
@@ -774,7 +759,7 @@ uint32_t *arm_decodeirq(uint32_t *regs);
****************************************************************************/
#ifdef CONFIG_SMP
-int arm_start_handler(int irq, FAR void *context);
+int arm_start_handler(int irq, FAR void *context, FAR void *arg);
#endif
/****************************************************************************
@@ -798,7 +783,7 @@ int arm_start_handler(int irq, FAR void *context);
****************************************************************************/
#ifdef CONFIG_SMP
-int arm_pause_handler(int irq, FAR void *context);
+int arm_pause_handler(int irq, FAR void *context, FAR void *arg);
#endif
/****************************************************************************
@@ -817,7 +802,7 @@ int arm_pause_handler(int irq, FAR void *context);
*
****************************************************************************/
-#ifdef CONFIG_DEBUG_IRQ
+#ifdef CONFIG_DEBUG_IRQ_INFO
void arm_gic_dump(const char *msg, bool all, int irq);
#else
# define arm_gic_dump(m,a,i)
diff --git a/arch/arm/src/armv7-a/mmu.h b/arch/arm/src/armv7-a/mmu.h
index 9ce8280b73232ba793c8a0d11ed0e958f41aeb77..c6338d33378b30395f574085ac6aac80ed98a4f6 100644
--- a/arch/arm/src/armv7-a/mmu.h
+++ b/arch/arm/src/armv7-a/mmu.h
@@ -513,7 +513,6 @@
* NMRR registers. For the simple case where TEX[2:0] = 0b000, the control
* is as follows:
*
- *
* MEMORY INNER OUTER OUTER SHAREABLE
* C B TYPE CACHEABILITY CACHEABILITY ATTRIBUTE
* - - ---------- ------------- ------------ -----------------
@@ -602,7 +601,6 @@
#define MMU_L2_PGTABFLAGS (PTE_TYPE_SMALL | PTE_WRITE_THROUGH | PTE_AP_RW1)
#define MMU_L1_VECTORFLAGS (PMD_TYPE_PTE | PMD_PTE_PXN | PMD_PTE_DOM(0))
-
#define MMU_L2_VECTRWFLAGS (PTE_TYPE_SMALL | PTE_WRITE_THROUGH | PTE_AP_RW1)
#define MMU_L2_VECTROFLAGS (PTE_TYPE_SMALL | PTE_WRITE_THROUGH | PTE_AP_R1)
#define MMU_L2_VECTORFLAGS MMU_L2_VECTRWFLAGS
@@ -1424,6 +1422,28 @@ void mmu_l1_restore(uintptr_t vaddr, uint32_t l1entry);
# define mmu_l1_clrentry(v) mmu_l1_restore(v,0)
#endif
+/****************************************************************************
+ * Name: mmu_l2_setentry
+ *
+ * Description:
+ * Set one small (4096B) entry in a level2 translation table.
+ *
+ * Input Parameters:
+ * l2vaddr - the virtual address of the beginning of the L2 translation
+ * table.
+ * paddr - The physical address to be mapped. Must be aligned to a 4KB
+ * address boundary
+ * vaddr - The virtual address to be mapped. Must be aligned to a 4KB
+ * address boundary
+ * mmuflags - The MMU flags to use in the mapping.
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_ARCH_ROMPGTABLE
+void mmu_l2_setentry(uint32_t l2vaddr, uint32_t paddr, uint32_t vaddr,
+ uint32_t mmuflags);
+#endif
+
/************************************************************************************
* Name: mmu_l1_map_region
*
diff --git a/arch/arm/src/armv7-a/scu.h b/arch/arm/src/armv7-a/scu.h
new file mode 100644
index 0000000000000000000000000000000000000000..a84fb0cc4f84bdaa007b4ee61edd1bd295cf947f
--- /dev/null
+++ b/arch/arm/src/armv7-a/scu.h
@@ -0,0 +1,176 @@
+/****************************************************************************
+ * arch/arm/src/armv7-a/scu.h
+ * Generic Interrupt Controller Definitions
+ *
+ * Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt
+ *
+ * Reference:
+ * Cortex™-A9 MPCore, Revision: r4p1, Technical Reference Manual, ARM DDI
+ * 0407I (ID091612).
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_ARMV7_A_SCU_H
+#define __ARCH_ARM_SRC_ARMV7_A_SCU_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include "mpcore.h" /* For MPCORE_SCU_VBASE */
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define SCU_CTRL_OFFSET 0x0000 /* SCU Control Register (Implementation defined) */
+#define SCU_CONFIG_OFFSET 0x0004 /* SCU Configuration Register (Implementation defined) */
+#define SCU_PWRSTATUS_OFFSET 0x0008 /* SCU CPU Power Status Register */
+#define SCU_INVALIDATE_OFFSET 0x000c /* SCU Invalidate All Registers in Secure State */
+#define SCU_FILTERSTART_OFFSET 0x0040 /* Filtering Start Address Register Defined by FILTERSTART input */
+#define SCU_FILTEREND_OFFSET 0x0044 /* Filtering End Address Register Defined by FILTEREND input */
+#define SCU_SAC_OFFSET 0x0050 /* SCU Access Control (SAC) Register */
+#define SCU_SNSAC_OFFSET 0x0054 /* SCU Non-secure Access Control (SNSAC) Register */
+
+/* Register addresses *******************************************************/
+
+#define SCU_CTRL (MPCORE_SCU_VBASE+SCU_CTRL_OFFSET)
+#define SCU_CONFIG (MPCORE_SCU_VBASE+SCU_CONFIG_OFFSET)
+#define SCU_PWRSTATUS (MPCORE_SCU_VBASE+SCU_PWRSTATUS_OFFSET)
+#define SCU_INVALIDATE (MPCORE_SCU_VBASE+SCU_INVALIDATE_OFFSET)
+#define SCU_FILTERSTART (MPCORE_SCU_VBASE+SCU_FILTERSTART_OFFSET)
+#define SCU_FILTEREND (MPCORE_SCU_VBASE+SCU_FILTEREND_OFFSET)
+#define SCU_SAC (MPCORE_SCU_VBASE+SCU_SAC_OFFSET)
+#define SCU_SNSAC (MPCORE_SCU_VBASE+SCU_SNSAC_OFFSET)
+
+/* Register bit-field definitions *******************************************/
+
+/* SCU Control Register (Implementation defined) */
+
+#define SCU_CTRL_ENABLE (1 << 0) /* SCU enable */
+#define SCU_CTRL_ADDRFILTER (1 << 1) /* Address filtering enable */
+#define SCU_CTRL_RAMPARITY (1 << 2) /* SCU RAMs parity enable */
+#define SCU_CTRL_LINFILL (1 << 3) /* SCU speculative linefill enable */
+#define SCU_CTRL_PORT0 (1 << 4) /* Force all device to port0 enable */
+#define SCU_CTRL_STANDBY (1 << 5) /* SCU standby enable */
+#define SCU_CTRL_ICSTANDBY (1 << 6) /* IC standby enable */
+
+/* SCU Configuration Register (Implementation defined) */
+
+#define SCU_CONFIG_NCPUS_SHIFT 0 /* CPU number Number of CPUs present */
+#define SCU_CONFIG_NCPUS_MASK (3 << SCU_CONFIG_NCPUS_SHIFT)
+# define SCU_CONFIG_NCPUS(r) ((((uint32_t)(r) & SCU_CONFIG_NCPUS_MASK) >> SCU_CONFIG_NCPUS_SHIFT) + 1)
+#define SCU_CONFIG_SMPCPUS_SHIFT 4 /* Processors that are in SMP or AMP mode */
+#define SCU_CONFIG_SMPCPUS_MASK (15 << SCU_CONFIG_SMPCPUS_SHIFT)
+# define SCU_CONFIG_CPU_SMP(n) (1 << ((n)+4))
+# define SCU_CONFIG_CPU0_SMP (1 << 4)
+# define SCU_CONFIG_CPU1_SMP (1 << 5)
+# define SCU_CONFIG_CPU2_SMP (1 << 6)
+# define SCU_CONFIG_CPU3_SMP (1 << 7)
+
+#define SCU_CONFIG_TAGRAM_16KB 0
+#define SCU_CONFIG_TAGRAM_32KB 1
+#define SCU_CONFIG_TAGRAM_64KB 2
+
+#define SCU_CONFIG_CPU0_TAGRAM_SHIFT 8 /* CPU 0 tag RAM size */
+#define SCU_CONFIG_CPU0_TAGRAM_MASK (3 << SCU_CONFIG_CPU0_TAGRAM_SHIFT)
+#define SCU_CONFIG_CPU1_TAGRAM_SHIFT 10 /* CPU 1 tag RAM size */
+#define SCU_CONFIG_CPU1_TAGRAM_MASK (3 << SCU_CONFIG_CPU0_TAGRAM_SHIFT)
+#define SCU_CONFIG_CPU2_TAGRAM_SHIFT 12 /* CPU 1 tag RAM size */
+#define SCU_CONFIG_CPU2_TAGRAM_MASK (3 << SCU_CONFIG_CPU0_TAGRAM_SHIFT)
+#define SCU_CONFIG_CPU3_TAGRAM_SHIFT 14 /* CPU 1 tag RAM size */
+#define SCU_CONFIG_CPU3_TAGRAM_MASK (3 << SCU_CONFIG_CPU0_TAGRAM_SHIFT)
+
+/* SCU CPU Power Status Register */
+
+#define SCU_PWRSTATUS_NORMAL 0
+#define SCU_PWRSTATUS_DORMANT 2
+#define SCU_PWRSTATUS_PWROFF 3
+
+#define SCU_PWRSTATUS_CPU0_SHIFT 0 /* CPU0 status Power status */
+#define SCU_PWRSTATUS_CPU0_MASK (3 << SCU_PWRSTATUS_CPU0_SHIFT)
+#define SCU_PWRSTATUS_CPU1_SHIFT 8 /* CPU1 status Power status */
+#define SCU_PWRSTATUS_CPU1_MASK (3 << SCU_PWRSTATUS_CPU1_SHIFT)
+#define SCU_PWRSTATUS_CPU2_SHIFT 16 /* CPU2 status Power status */
+#define SCU_PWRSTATUS_CPU2_MASK (3 << SCU_PWRSTATUS_CPU2_SHIFT)
+#define SCU_PWRSTATUS_CPU3_SHIFT 24 /* CPU3 status Power status */
+#define SCU_PWRSTATUS_CPU3_MASK (3 << SCU_PWRSTATUS_CPU3_SHIFT)
+
+/* SCU Invalidate All Registers in Secure State */
+
+#define SCU_INVALIDATE_ALL_WAYS 15
+#define SCU_INVALIDATE_CPU0_SHIFT 0 /* Ways that must be invalidated for CPU0 */
+#define SCU_INVALIDATE_CPU0_MASK (15 << SCU_INVALIDATE_CPU0_SHIFT)
+#define SCU_INVALIDATE_CPU1_SHIFT 4 /* Ways that must be invalidated for CPU1 */
+#define SCU_INVALIDATE_CPU1_MASK (15 << SCU_INVALIDATE_CPU1_SHIFT)
+#define SCU_INVALIDATE_CPU2_SHIFT 8 /* Ways that must be invalidated for CPU2 */
+#define SCU_INVALIDATE_CPU2_MASK (15 << SCU_INVALIDATE_CPU2_SHIFT)
+#define SCU_INVALIDATE_CPU3_SHIFT 12 /* Ways that must be invalidated for CPU3 */
+#define SCU_INVALIDATE_CPU3_MASK (15 << SCU_INVALIDATE_CPU3_SHIFT)
+
+/* Filtering Start Address Register Defined by FILTERSTART input */
+
+#define SCU_FILTERSTART_SHIFT 10 /* Filtering start address */
+#define SCU_FILTERSTART_MASK (0xfff << SCU_FILTERSTART_SHIFT)
+
+/* Filtering End Address Register Defined by FILTEREND input */
+
+#define SCU_FILTEREND_SHIFT 10 /* Filtering start address */
+#define SCU_FILTEREND_MASK (0xfff << SCU_FILTEREND_SHIFT)
+
+/* SCU Access Control (SAC) Register */
+
+#define SCU_SAC_CPU(n) (1 << (n)) /* CPUn may access components */
+
+/* SCU Non-secure Access Control (SNSAC) Register */
+
+#define SCU_SNSAC_COMP_CPU(n) (1 << (n)) /* CPUn has non-secure access to components */
+#define SCU_SNSAC_PTIM_CPU(n) (1 << ((n)+4)) /* CPUn has non-secure access to private timers */
+#define SCU_SNSAC_GTIM_CPU(n) (1 << ((n)+8)) /* CPUn has non-secure access to global timer */
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: arm_enable_smp
+ *
+ * Description:
+ * Enable the SCU and make certain that current CPU is participating in
+ * the SMP cache coherency.
+ *
+ ****************************************************************************/
+
+void arm_enable_smp(int cpu);
+
+#endif /* __ARCH_ARM_SRC_ARMV7_A_SCU_H */
diff --git a/arch/arm/src/armv7-m/Kconfig b/arch/arm/src/armv7-m/Kconfig
index 406e2e46624be926494b130312a91d539bc3c02b..4c66b55d54d2f55a97b2b1d4a15e566f8c3ed6d6 100644
--- a/arch/arm/src/armv7-m/Kconfig
+++ b/arch/arm/src/armv7-m/Kconfig
@@ -48,12 +48,12 @@ config ARMV7M_DTCM
choice
prompt "Toolchain Selection"
- default ARMV7M_TOOLCHAIN_GNU_EABIW if HOST_WINDOWS
- default ARMV7M_TOOLCHAIN_GNU_EABIL if !HOST_WINDOWS
+ default ARMV7M_TOOLCHAIN_GNU_EABIW if TOOLCHAIN_WINDOWS
+ default ARMV7M_TOOLCHAIN_GNU_EABIL if !TOOLCHAIN_WINDOWS
config ARMV7M_TOOLCHAIN_IARW
bool "IAR for Windows"
- depends on HOST_WINDOWS
+ depends on TOOLCHAIN_WINDOWS
select ARM_TOOLCHAIN_IAR
config ARMV7M_TOOLCHAIN_IARL
@@ -63,7 +63,7 @@ config ARMV7M_TOOLCHAIN_IARL
config ARMV7M_TOOLCHAIN_ATOLLIC
bool "Atollic Lite/Pro for Windows"
- depends on HOST_WINDOWS
+ depends on TOOLCHAIN_WINDOWS
select ARM_TOOLCHAIN_GNU
config ARMV7M_TOOLCHAIN_BUILDROOT
@@ -78,7 +78,7 @@ config ARMV7M_TOOLCHAIN_CODEREDL
config ARMV7M_TOOLCHAIN_CODEREDW
bool "CodeRed for Windows"
- depends on HOST_WINDOWS
+ depends on TOOLCHAIN_WINDOWS
select ARM_TOOLCHAIN_GNU
config ARMV7M_TOOLCHAIN_CODESOURCERYL
@@ -88,12 +88,12 @@ config ARMV7M_TOOLCHAIN_CODESOURCERYL
config ARMV7M_TOOLCHAIN_CODESOURCERYW
bool "CodeSourcery GNU toolchain under Windows"
- depends on HOST_WINDOWS
+ depends on TOOLCHAIN_WINDOWS
select ARM_TOOLCHAIN_GNU
config ARMV7M_TOOLCHAIN_DEVKITARM
bool "devkitARM GNU toolchain"
- depends on HOST_WINDOWS
+ depends on TOOLCHAIN_WINDOWS
select ARM_TOOLCHAIN_GNU
config ARMV7M_TOOLCHAIN_GNU_EABIL
@@ -106,7 +106,7 @@ config ARMV7M_TOOLCHAIN_GNU_EABIL
config ARMV7M_TOOLCHAIN_GNU_EABIW
bool "Generic GNU EABI toolchain under Windows"
- depends on HOST_WINDOWS
+ depends on TOOLCHAIN_WINDOWS
select ARM_TOOLCHAIN_GNU
---help---
This option should work for any modern GNU toolchain (GCC 4.5 or newer)
@@ -114,7 +114,7 @@ config ARMV7M_TOOLCHAIN_GNU_EABIW
config ARMV7M_TOOLCHAIN_RAISONANCE
bool "STMicro Raisonance for Windows"
- depends on HOST_WINDOWS
+ depends on TOOLCHAIN_WINDOWS
select ARM_TOOLCHAIN_GNU
endchoice
@@ -160,6 +160,7 @@ config ARMV7M_STACKCHECK
config ARMV7M_ITMSYSLOG
bool "ITM SYSLOG support"
default n
+ select ARCH_SYSLOG
select SYSLOG
---help---
Enable hooks to support ITM syslog output. This requires additional
diff --git a/arch/arm/src/armv7-m/gnu/up_testset.S b/arch/arm/src/armv7-m/gnu/up_testset.S
index 7dd45eee4dbef257817c6ac0095450811b371d80..c1888c56a98fcc5a64381b053c0e8903c585c65e 100644
--- a/arch/arm/src/armv7-m/gnu/up_testset.S
+++ b/arch/arm/src/armv7-m/gnu/up_testset.S
@@ -72,7 +72,7 @@
* Name: up_testset
*
* Description:
- * Perform and atomic test and set operation on the provided spinlock.
+ * Perform an atomic test and set operation on the provided spinlock.
*
* This function must be provided via the architecture-specific logoic.
*
diff --git a/arch/arm/src/armv7-m/iar/up_testset.S b/arch/arm/src/armv7-m/iar/up_testset.S
index 9590e576e77ef8d16927948a82564f75401e38fb..e690aed3de9d7f6ae88d9374e67b6f71d04d32ae 100644
--- a/arch/arm/src/armv7-m/iar/up_testset.S
+++ b/arch/arm/src/armv7-m/iar/up_testset.S
@@ -57,7 +57,7 @@
* Name: up_testset
*
* Description:
- * Perform and atomic test and set operation on the provided spinlock.
+ * Perform an atomic test and set operation on the provided spinlock.
*
* This function must be provided via the architecture-specific logoic.
*
diff --git a/arch/arm/src/armv7-m/itm_syslog.h b/arch/arm/src/armv7-m/itm_syslog.h
index 1b42be2ea8e442ee412ebf9169103b7c8fa9f289..40f71624f57dad9714603f428ef48e839f0d843d 100644
--- a/arch/arm/src/armv7-m/itm_syslog.h
+++ b/arch/arm/src/armv7-m/itm_syslog.h
@@ -57,7 +57,7 @@
*
****************************************************************************/
-#if defined(CONFIG_SYSLOG) || defined(CONFIG_ARMV7M_ITMSYSLOG)
+#ifdef CONFIG_ARMV7M_ITMSYSLOG
void itm_syslog_initialize(void);
#else
# define itm_syslog_initialize()
diff --git a/arch/arm/src/armv7-m/mpu.h b/arch/arm/src/armv7-m/mpu.h
index 310c21a90912303363435c59a6dbf1f348386ca2..4a5bab065bda53bc67807f874c0e77683d05adca 100644
--- a/arch/arm/src/armv7-m/mpu.h
+++ b/arch/arm/src/armv7-m/mpu.h
@@ -219,12 +219,13 @@ uint32_t mpu_subregion(uintptr_t base, size_t size, uint8_t l2size);
static inline void mpu_showtype(void)
{
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_SCHED_INFO
uint32_t regval = getreg32(MPU_TYPE);
- dbg("%s MPU Regions: data=%d instr=%d\n",
- (regval & MPU_TYPE_SEPARATE) != 0 ? "Separate" : "Unified",
- (regval & MPU_TYPE_DREGION_MASK) >> MPU_TYPE_DREGION_SHIFT,
- (regval & MPU_TYPE_IREGION_MASK) >> MPU_TYPE_IREGION_SHIFT);
+
+ sinfo("%s MPU Regions: data=%d instr=%d\n",
+ (regval & MPU_TYPE_SEPARATE) != 0 ? "Separate" : "Unified",
+ (regval & MPU_TYPE_DREGION_MASK) >> MPU_TYPE_DREGION_SHIFT,
+ (regval & MPU_TYPE_IREGION_MASK) >> MPU_TYPE_IREGION_SHIFT);
#endif
}
@@ -356,7 +357,7 @@ static inline void mpu_priv_flash(uintptr_t base, size_t size)
/* Select the region */
- putreg32(mpu_allocregion(), MPU_RNR);
+ putreg32(region, MPU_RNR);
/* Select the region base address */
diff --git a/arch/arm/src/armv7-m/up_assert.c b/arch/arm/src/armv7-m/up_assert.c
index 0f6fa00d219488401220dc6d35a5d469786f66d8..11f29cd653422c3b58535fabcac7249c72115eec 100644
--- a/arch/arm/src/armv7-m/up_assert.c
+++ b/arch/arm/src/armv7-m/up_assert.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv7-m/up_assert.c
*
- * Copyright (C) 2009-2010, 2012-2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2009-2010, 2012-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
#include
@@ -64,6 +53,7 @@
#include "up_arch.h"
#include "sched/sched.h"
+#include "irq/irq.h"
#include "up_internal.h"
/****************************************************************************
@@ -75,23 +65,6 @@
# undef CONFIG_ARCH_USBDUMP
#endif
-/* The following is just intended to keep some ugliness out of the mainline
- * code. We are going to print the task name if:
- *
- * CONFIG_TASK_NAME_SIZE > 0 && <-- The task has a name
- * (defined(CONFIG_DEBUG) || <-- And the debug is enabled (lldbg used)
- * defined(CONFIG_ARCH_STACKDUMP) <-- Or lowsyslog() is used
- */
-
-#undef CONFIG_PRINT_TASKNAME
-#if CONFIG_TASK_NAME_SIZE > 0 && (defined(CONFIG_DEBUG) || defined(CONFIG_ARCH_STACKDUMP))
-# define CONFIG_PRINT_TASKNAME 1
-#endif
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -125,7 +98,7 @@ static void up_stackdump(uint32_t sp, uint32_t stack_base)
for (stack = sp & ~0x1f; stack < stack_base; stack += 32)
{
uint32_t *ptr = (uint32_t *)stack;
- lldbg("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ _alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
stack, ptr[0], ptr[1], ptr[2], ptr[3],
ptr[4], ptr[5], ptr[6], ptr[7]);
}
@@ -143,12 +116,12 @@ static void up_taskdump(FAR struct tcb_s *tcb, FAR void *arg)
{
/* Dump interesting properties of this task */
-#ifdef CONFIG_PRINT_TASKNAME
- lldbg("%s: PID=%d Stack Used=%lu of %lu\n",
+#if CONFIG_TASK_NAME_SIZE > 0
+ _alert("%s: PID=%d Stack Used=%lu of %lu\n",
tcb->name, tcb->pid, (unsigned long)up_check_tcbstack(tcb),
(unsigned long)tcb->adj_stack_size);
#else
- lldbg("PID: %d Stack Used=%lu of %lu\n",
+ _alert("PID: %d Stack Used=%lu of %lu\n",
tcb->pid, (unsigned long)up_check_tcbstack(tcb),
(unsigned long)tcb->adj_stack_size);
#endif
@@ -183,29 +156,29 @@ static inline void up_registerdump(void)
{
/* Yes.. dump the interrupt registers */
- lldbg("R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ _alert("R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
CURRENT_REGS[REG_R0], CURRENT_REGS[REG_R1],
CURRENT_REGS[REG_R2], CURRENT_REGS[REG_R3],
CURRENT_REGS[REG_R4], CURRENT_REGS[REG_R5],
CURRENT_REGS[REG_R6], CURRENT_REGS[REG_R7]);
- lldbg("R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ _alert("R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
CURRENT_REGS[REG_R8], CURRENT_REGS[REG_R9],
CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
#ifdef CONFIG_ARMV7M_USEBASEPRI
- lldbg("xPSR: %08x BASEPRI: %08x CONTROL: %08x\n",
+ _alert("xPSR: %08x BASEPRI: %08x CONTROL: %08x\n",
CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_BASEPRI],
getcontrol());
#else
- lldbg("xPSR: %08x PRIMASK: %08x CONTROL: %08x\n",
+ _alert("xPSR: %08x PRIMASK: %08x CONTROL: %08x\n",
CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK],
getcontrol());
#endif
#ifdef REG_EXC_RETURN
- lldbg("EXC_RETURN: %08x\n", CURRENT_REGS[REG_EXC_RETURN]);
+ _alert("EXC_RETURN: %08x\n", CURRENT_REGS[REG_EXC_RETURN]);
#endif
}
}
@@ -226,7 +199,7 @@ static int usbtrace_syslog(FAR const char *fmt, ...)
/* Let vsyslog do the real work */
va_start(ap, fmt);
- ret = lowvsyslog(LOG_INFO, fmt, ap);
+ ret = vsyslog(LOG_EMERG, fmt, ap);
va_end(ap);
return ret;
}
@@ -275,12 +248,12 @@ static void up_dumpstate(void)
/* Show interrupt stack info */
- lldbg("sp: %08x\n", sp);
- lldbg("IRQ stack:\n");
- lldbg(" base: %08x\n", istackbase);
- lldbg(" size: %08x\n", istacksize);
+ _alert("sp: %08x\n", sp);
+ _alert("IRQ stack:\n");
+ _alert(" base: %08x\n", istackbase);
+ _alert(" size: %08x\n", istacksize);
#ifdef CONFIG_STACK_COLORATION
- lldbg(" used: %08x\n", up_check_intstack());
+ _alert(" used: %08x\n", up_check_intstack());
#endif
/* Does the current stack pointer lie within the interrupt
@@ -302,14 +275,14 @@ static void up_dumpstate(void)
if (CURRENT_REGS)
{
sp = CURRENT_REGS[REG_R13];
- lldbg("sp: %08x\n", sp);
+ _alert("sp: %08x\n", sp);
}
- lldbg("User stack:\n");
- lldbg(" base: %08x\n", ustackbase);
- lldbg(" size: %08x\n", ustacksize);
+ _alert("User stack:\n");
+ _alert(" base: %08x\n", ustackbase);
+ _alert(" size: %08x\n", ustacksize);
#ifdef CONFIG_STACK_COLORATION
- lldbg(" used: %08x\n", up_check_tcbstack(rtcb));
+ _alert(" used: %08x\n", up_check_tcbstack(rtcb));
#endif
/* Dump the user stack if the stack pointer lies within the allocated user
@@ -325,11 +298,11 @@ static void up_dumpstate(void)
/* Show user stack info */
- lldbg("sp: %08x\n", sp);
- lldbg("stack base: %08x\n", ustackbase);
- lldbg("stack size: %08x\n", ustacksize);
+ _alert("sp: %08x\n", sp);
+ _alert("stack base: %08x\n", ustackbase);
+ _alert("stack size: %08x\n", ustacksize);
#ifdef CONFIG_STACK_COLORATION
- lldbg("stack used: %08x\n", up_check_tcbstack(rtcb));
+ _alert("stack used: %08x\n", up_check_tcbstack(rtcb));
#endif
/* Dump the user stack if the stack pointer lies within the allocated user
@@ -338,7 +311,7 @@ static void up_dumpstate(void)
if (sp > ustackbase || sp <= ustackbase - ustacksize)
{
- lldbg("ERROR: Stack pointer is not within the allocated stack\n");
+ _alert("ERROR: Stack pointer is not within the allocated stack\n");
}
else
{
@@ -347,6 +320,12 @@ static void up_dumpstate(void)
#endif
+#ifdef CONFIG_SMP
+ /* Show the CPU number */
+
+ _alert("CPU%d:\n", up_cpu_index());
+#endif
+
/* Then dump the registers (if available) */
up_registerdump();
@@ -379,6 +358,12 @@ static void _up_assert(int errorcode)
(void)up_irq_save();
for (; ; )
{
+#ifdef CONFIG_SMP
+ /* Try (again) to stop activity on other CPUs */
+
+ (void)spin_trylock(&g_cpu_irqlock);
+#endif
+
#ifdef CONFIG_ARCH_LEDS
board_autoled_on(LED_PANIC);
up_mdelay(250);
@@ -403,17 +388,17 @@ static void _up_assert(int errorcode)
void up_assert(const uint8_t *filename, int lineno)
{
-#ifdef CONFIG_PRINT_TASKNAME
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT)
struct tcb_s *rtcb = this_task();
#endif
board_autoled_on(LED_ASSERTION);
-#ifdef CONFIG_PRINT_TASKNAME
- lldbg("Assertion failed at file:%s line: %d task: %s\n",
+#if CONFIG_TASK_NAME_SIZE > 0
+ _alert("Assertion failed at file:%s line: %d task: %s\n",
filename, lineno, rtcb->name);
#else
- lldbg("Assertion failed at file:%s line: %d\n",
+ _alert("Assertion failed at file:%s line: %d\n",
filename, lineno);
#endif
diff --git a/arch/arm/src/armv7-m/up_coherent_dcache.c b/arch/arm/src/armv7-m/up_coherent_dcache.c
index 019205f46bc8f74e50e92a124a4a067a41a0a560..008b37a9a338a21bd68415eda8710aeae0085582 100644
--- a/arch/arm/src/armv7-m/up_coherent_dcache.c
+++ b/arch/arm/src/armv7-m/up_coherent_dcache.c
@@ -46,18 +46,6 @@
#include
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
diff --git a/arch/arm/src/armv7-m/up_copyarmstate.c b/arch/arm/src/armv7-m/up_copyarmstate.c
index 13fec55422aa731c510d0c807e52d77c1098e4db..22e2f390036cdc1fcc76aa4fcdc511d939deb03a 100644
--- a/arch/arm/src/armv7-m/up_copyarmstate.c
+++ b/arch/arm/src/armv7-m/up_copyarmstate.c
@@ -48,18 +48,6 @@
#if defined(CONFIG_ARCH_FPU) && \
(!defined(CONFIG_ARMV7M_CMNVECTOR) || defined(CONFIG_ARMV7M_LAZYFPU))
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
diff --git a/arch/arm/src/armv7-m/up_copyfullstate.c b/arch/arm/src/armv7-m/up_copyfullstate.c
index e3618d486238c6ac0c14b2a79bce17c6506ab855..43b10751898b8efcf0bf0584183891f83ffba0cc 100644
--- a/arch/arm/src/armv7-m/up_copyfullstate.c
+++ b/arch/arm/src/armv7-m/up_copyfullstate.c
@@ -44,18 +44,6 @@
#include "up_internal.h"
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
diff --git a/arch/arm/src/armv7-m/up_doirq.c b/arch/arm/src/armv7-m/up_doirq.c
index b51c10e55823bf3ca9861292e97258244519c3cd..8a9cea505e9d85a4457298b39c8f3a8030141775 100644
--- a/arch/arm/src/armv7-m/up_doirq.c
+++ b/arch/arm/src/armv7-m/up_doirq.c
@@ -50,22 +50,6 @@
#include "up_arch.h"
#include "up_internal.h"
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -83,7 +67,7 @@ uint32_t *up_doirq(int irq, uint32_t *regs)
* CURRENT_REGS is handled and (2) the design associated with
* CONFIG_ARCH_INTERRUPTSTACK. The savestate variable will not work for
* that purpose as implemented here because only the outermost nested
- * interrupt can result in a context switch (it can probably be deleted).
+ * interrupt can result in a context switch.
*/
/* Current regs non-zero indicates that we are processing an interrupt;
diff --git a/arch/arm/src/armv7-m/up_hardfault.c b/arch/arm/src/armv7-m/up_hardfault.c
index 807d45cc43922595c1dbb7a3c92a0235acbf76e9..a68996836e17e68d5cbb42b4a76f5d34b3e4ba76 100644
--- a/arch/arm/src/armv7-m/up_hardfault.c
+++ b/arch/arm/src/armv7-m/up_hardfault.c
@@ -60,25 +60,13 @@
*/
#ifdef CONFIG_DEBUG_HARDFAULT
-# define hfdbg(format, ...) lldbg(format, ##__VA_ARGS__)
+# define hfalert(format, ...) _alert(format, ##__VA_ARGS__)
#else
-# define hfdbg(x...)
+# define hfalert(x...)
#endif
#define INSN_SVC0 0xdf00 /* insn: svc 0 */
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -92,7 +80,7 @@
*
****************************************************************************/
-int up_hardfault(int irq, FAR void *context)
+int up_hardfault(int irq, FAR void *context, FAR void *arg)
{
#if defined(CONFIG_DEBUG_HARDFAULT) || !defined(CONFIG_ARMV7M_USEBASEPRI)
uint32_t *regs = (uint32_t *)context;
@@ -127,7 +115,7 @@ int up_hardfault(int irq, FAR void *context)
/* Fetch the instruction that caused the Hard fault */
uint16_t insn = *pc;
- hfdbg(" PC: %p INSN: %04x\n", pc, insn);
+ hfalert(" PC: %p INSN: %04x\n", pc, insn);
/* If this was the instruction 'svc 0', then forward processing
* to the SVCall handler
@@ -135,51 +123,51 @@ int up_hardfault(int irq, FAR void *context)
if (insn == INSN_SVC0)
{
- hfdbg("Forward SVCall\n");
- return up_svcall(irq, context);
+ hfalert("Forward SVCall\n");
+ return up_svcall(irq, context, arg);
}
}
#endif
/* Dump some hard fault info */
- hfdbg("Hard Fault:\n");
- hfdbg(" IRQ: %d regs: %p\n", irq, regs);
- hfdbg(" BASEPRI: %08x PRIMASK: %08x IPSR: %08x CONTROL: %08x\n",
- getbasepri(), getprimask(), getipsr(), getcontrol());
- hfdbg(" CFAULTS: %08x HFAULTS: %08x DFAULTS: %08x BFAULTADDR: %08x AFAULTS: %08x\n",
- getreg32(NVIC_CFAULTS), getreg32(NVIC_HFAULTS),
- getreg32(NVIC_DFAULTS), getreg32(NVIC_BFAULT_ADDR),
- getreg32(NVIC_AFAULTS));
- hfdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
- regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
- hfdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
- regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
+ hfalert("Hard Fault:\n");
+ hfalert(" IRQ: %d regs: %p\n", irq, regs);
+ hfalert(" BASEPRI: %08x PRIMASK: %08x IPSR: %08x CONTROL: %08x\n",
+ getbasepri(), getprimask(), getipsr(), getcontrol());
+ hfalert(" CFAULTS: %08x HFAULTS: %08x DFAULTS: %08x BFAULTADDR: %08x AFAULTS: %08x\n",
+ getreg32(NVIC_CFAULTS), getreg32(NVIC_HFAULTS),
+ getreg32(NVIC_DFAULTS), getreg32(NVIC_BFAULT_ADDR),
+ getreg32(NVIC_AFAULTS));
+ hfalert(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
+ regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
+ hfalert(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
+ regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
#ifdef CONFIG_ARMV7M_USEBASEPRI
# ifdef REG_EXC_RETURN
- hfdbg(" xPSR: %08x BASEPRI: %08x EXC_RETURN: %08x (saved)\n",
- CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_BASEPRI],
- CURRENT_REGS[REG_EXC_RETURN]);
+ hfalert(" xPSR: %08x BASEPRI: %08x EXC_RETURN: %08x (saved)\n",
+ CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_BASEPRI],
+ CURRENT_REGS[REG_EXC_RETURN]);
# else
- hfdbg(" xPSR: %08x BASEPRI: %08x (saved)\n",
- CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_BASEPRI]);
+ hfalert(" xPSR: %08x BASEPRI: %08x (saved)\n",
+ CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_BASEPRI]);
# endif
#else
# ifdef REG_EXC_RETURN
- hfdbg(" xPSR: %08x PRIMASK: %08x EXC_RETURN: %08x (saved)\n",
- CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK],
- CURRENT_REGS[REG_EXC_RETURN]);
+ hfalert(" xPSR: %08x PRIMASK: %08x EXC_RETURN: %08x (saved)\n",
+ CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK],
+ CURRENT_REGS[REG_EXC_RETURN]);
# else
- hfdbg(" xPSR: %08x PRIMASK: %08x (saved)\n",
- CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]);
+ hfalert(" xPSR: %08x PRIMASK: %08x (saved)\n",
+ CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]);
# endif
#endif
(void)up_irq_save();
- lldbg("PANIC!!! Hard fault: %08x\n", getreg32(NVIC_HFAULTS));
+ _alert("PANIC!!! Hard fault: %08x\n", getreg32(NVIC_HFAULTS));
PANIC();
return OK;
}
diff --git a/arch/arm/src/armv7-m/up_initialstate.c b/arch/arm/src/armv7-m/up_initialstate.c
index 7cf6816c21820e75a684e276469410c04f5fd1ae..37cb86cb4640a812243730349401b44c872dd674 100644
--- a/arch/arm/src/armv7-m/up_initialstate.c
+++ b/arch/arm/src/armv7-m/up_initialstate.c
@@ -51,18 +51,6 @@
#include "psr.h"
#include "exc_return.h"
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
diff --git a/arch/arm/src/armv7-m/up_itm_syslog.c b/arch/arm/src/armv7-m/up_itm_syslog.c
index 94b499879a79b9111a9225f50f6990a66e6059fb..d63fed09adb238e571c2cdd74f731759cb67e848 100644
--- a/arch/arm/src/armv7-m/up_itm_syslog.c
+++ b/arch/arm/src/armv7-m/up_itm_syslog.c
@@ -2,7 +2,7 @@
* arch/arm/src/armv7-m/up_itm_syslog.c
*
* Copyright (C) 2014 Pierre-noel Bouteville . All rights reserved.
- * Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved.
* Authors: Pierre-noel Bouteville
* Gregory Nutt
*
@@ -52,7 +52,7 @@
#include "up_arch.h"
#include "itm_syslog.h"
-#if defined(CONFIG_SYSLOG) || defined(CONFIG_ARMV7M_ITMSYSLOG)
+#ifdef CONFIG_ARMV7M_ITMSYSLOG
/****************************************************************************
* Pre-processor Definitions
@@ -72,6 +72,73 @@
# define CONFIG_ARMV7M_ITMSYSLOG_PORT 0
#endif
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* SYSLOG channel methods */
+
+static int itm_putc(int ch);
+static int itm_flush(void);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* This structure describes the ITM SYSLOG channel */
+
+static const struct syslog_channel_s g_itm_channel =
+{
+ .sc_putc = itm_putc,
+ .sc_force = itm_putc,
+ .sc_flush = itm_flush,
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: itm_putc
+ *
+ * Description:
+ * This is the low-level system logging interface.
+ *
+ ****************************************************************************/
+
+static int itm_putc(int ch)
+{
+ /* ITM enabled */
+
+ if ((getreg32(ITM_TCR) & ITM_TCR_ITMENA_Msk) == 0)
+ {
+ return EOF;
+ }
+
+ /* ITM Port "CONFIG_ARMV7M_ITMSYSLOG_PORT" enabled */
+
+ if (getreg32(ITM_TER) & (1 << CONFIG_ARMV7M_ITMSYSLOG_PORT))
+ {
+ while (getreg32(ITM_PORT(CONFIG_ARMV7M_ITMSYSLOG_PORT)) == 0);
+ putreg8((uint8_t)ch, ITM_PORT(CONFIG_ARMV7M_ITMSYSLOG_PORT));
+ }
+
+ return ch;
+}
+
+/****************************************************************************
+ * Name: itm_flush
+ *
+ * Description:
+ * A dummy FLUSH method
+ *
+ ****************************************************************************/
+
+static int itm_flush(void)
+{
+ return OK;
+}
+
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -116,38 +183,10 @@ void itm_syslog_initialize(void)
putreg32(0x0001000d, ITM_TCR);
putreg32(0x00000100, TPI_FFCR);
putreg32(0xffffffff, ITM_TER); /* Enable 32 Ports */
-}
-/****************************************************************************
- * Name: syslog_putc
- *
- * Description:
- * This is the low-level system logging interface. The debugging/syslogging
- * interfaces are syslog() and lowsyslog(). The difference is that
- * the syslog() internface writes to fd=1 (stdout) whereas lowsyslog() uses
- * a lower level interface that works from interrupt handlers. This
- * function is the low-level interface used to implement lowsyslog().
- *
- ****************************************************************************/
+ /* Setup the SYSLOG channel */
-int syslog_putc(int ch)
-{
- /* ITM enabled */
-
- if ((getreg32(ITM_TCR) & ITM_TCR_ITMENA_Msk) == 0)
- {
- return EOF;
- }
-
- /* ITM Port "CONFIG_ARMV7M_ITMSYSLOG_PORT" enabled */
-
- if (getreg32(ITM_TER) & (1 << CONFIG_ARMV7M_ITMSYSLOG_PORT))
- {
- while (getreg32(ITM_PORT(CONFIG_ARMV7M_ITMSYSLOG_PORT)) == 0);
- putreg8((uint8_t)ch, ITM_PORT(CONFIG_ARMV7M_ITMSYSLOG_PORT));
- }
-
- return ch;
+ (void)syslog_channel(&g_itm_channel);
}
-#endif /* CONFIG_SYSLOG && CONFIG_ARMV7M_ITMSYSLOG */
+#endif /* CONFIG_ARMV7M_ITMSYSLOG */
diff --git a/arch/arm/src/armv7-m/up_memfault.c b/arch/arm/src/armv7-m/up_memfault.c
index 145dba531d0d788fc61d212c3f9ec860f0e2da35..f4f642e4defc21856c9fc75676bdeb85dc5e91b5 100644
--- a/arch/arm/src/armv7-m/up_memfault.c
+++ b/arch/arm/src/armv7-m/up_memfault.c
@@ -55,23 +55,13 @@
#undef DEBUG_MEMFAULTS /* Define to debug memory management faults */
#ifdef DEBUG_MEMFAULTS
-# define mfdbg(format, ...) lldbg(format, ##__VA_ARGS__)
+# define mferr(format, ...) _alert(format, ##__VA_ARGS__)
+# define mfinfo(format, ...) _alert(format, ##__VA_ARGS__)
#else
-# define mfdbg(x...)
+# define mferr(x...)
+# define mfinfo(x...)
#endif
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -87,41 +77,41 @@
*
****************************************************************************/
-int up_memfault(int irq, FAR void *context)
+int up_memfault(int irq, FAR void *context, FAR void *arg)
{
/* Dump some memory management fault info */
(void)up_irq_save();
- lldbg("PANIC!!! Memory Management Fault:\n");
- mfdbg(" IRQ: %d context: %p\n", irq, regs);
- lldbg(" CFAULTS: %08x MMFAR: %08x\n",
+ _alert("PANIC!!! Memory Management Fault:\n");
+ mfinfo(" IRQ: %d context: %p\n", irq, regs);
+ _alert(" CFAULTS: %08x MMFAR: %08x\n",
getreg32(NVIC_CFAULTS), getreg32(NVIC_MEMMANAGE_ADDR));
- mfdbg(" BASEPRI: %08x PRIMASK: %08x IPSR: %08x CONTROL: %08x\n",
- getbasepri(), getprimask(), getipsr(), getcontrol());
- mfdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
- regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
- mfdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
- regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
+ mfinfo(" BASEPRI: %08x PRIMASK: %08x IPSR: %08x CONTROL: %08x\n",
+ getbasepri(), getprimask(), getipsr(), getcontrol());
+ mfinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
+ regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
+ mfinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
+ regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
#ifdef CONFIG_ARMV7M_USEBASEPRI
# ifdef REG_EXC_RETURN
- mfdbg(" xPSR: %08x BASEPRI: %08x EXC_RETURN: %08x (saved)\n",
- CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_BASEPRI],
- CURRENT_REGS[REG_EXC_RETURN]);
+ mfinfo(" xPSR: %08x BASEPRI: %08x EXC_RETURN: %08x (saved)\n",
+ CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_BASEPRI],
+ CURRENT_REGS[REG_EXC_RETURN]);
# else
- mfdbg(" xPSR: %08x BASEPRI: %08x (saved)\n",
- CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_BASEPRI]);
+ mfinfo(" xPSR: %08x BASEPRI: %08x (saved)\n",
+ CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_BASEPRI]);
# endif
#else
# ifdef REG_EXC_RETURN
- mfdbg(" xPSR: %08x PRIMASK: %08x EXC_RETURN: %08x (saved)\n",
- CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK],
- CURRENT_REGS[REG_EXC_RETURN]);
+ mfinfo(" xPSR: %08x PRIMASK: %08x EXC_RETURN: %08x (saved)\n",
+ CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK],
+ CURRENT_REGS[REG_EXC_RETURN]);
# else
- mfdbg(" xPSR: %08x PRIMASK: %08x (saved)\n",
- CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]);
+ mfinfo(" xPSR: %08x PRIMASK: %08x (saved)\n",
+ CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_PRIMASK]);
# endif
#endif
diff --git a/arch/arm/src/armv7-m/up_ramvec_attach.c b/arch/arm/src/armv7-m/up_ramvec_attach.c
index 3700cdb00bc1542ff0b44e29585e3363475cded5..6b954803e03db95599e75c5d3066d61c2cd80b36 100644
--- a/arch/arm/src/armv7-m/up_ramvec_attach.c
+++ b/arch/arm/src/armv7-m/up_ramvec_attach.c
@@ -49,39 +49,6 @@
#ifdef CONFIG_ARCH_RAMVECTORS
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-/* Debug ********************************************************************/
-/* Non-standard debug that may be enabled just for testing the interrupt
- * config. NOTE: that only lldbg types are used so that the output is
- * immediately available.
- */
-
-#ifdef CONFIG_DEBUG_IRQ
-# define intdbg lldbg
-# define intvdbg llvdbg
-#else
-# define intdbg(x...)
-# define intvdbg(x...)
-#endif
-
-/****************************************************************************
- * Private Type Declarations
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -103,7 +70,7 @@ int up_ramvec_attach(int irq, up_vector_t vector)
{
int ret = -EINVAL;
- intvdbg("%s IRQ%d\n", vector ? "Attaching" : "Detaching", irq);
+ irqinfo("%s IRQ%d\n", vector ? "Attaching" : "Detaching", irq);
if ((unsigned)irq < NR_VECTORS)
{
diff --git a/arch/arm/src/armv7-m/up_ramvec_initialize.c b/arch/arm/src/armv7-m/up_ramvec_initialize.c
index 80b176d67403d0eaf8d14cb880ac1b3e99946bc7..4db7bb2be322172bf6bf3a036a8bb8d0fa7132b9 100644
--- a/arch/arm/src/armv7-m/up_ramvec_initialize.c
+++ b/arch/arm/src/armv7-m/up_ramvec_initialize.c
@@ -71,24 +71,6 @@
#define RAMVEC_ALIGN ((~NVIC_VECTAB_TBLOFF_MASK & 0xffff) + 1)
-/* Debug ********************************************************************/
-/* Non-standard debug that may be enabled just for testing the interrupt
- * config. NOTE: that only lldbg types are used so that the output is
- * immediately available.
- */
-
-#ifdef CONFIG_DEBUG_IRQ
-# define intdbg lldbg
-# define intvdbg llvdbg
-#else
-# define intdbg(x...)
-# define intvdbg(x...)
-#endif
-
-/****************************************************************************
- * Private Type Declarations
- ****************************************************************************/
-
/****************************************************************************
* Public Data
****************************************************************************/
@@ -108,14 +90,6 @@
up_vector_t g_ram_vectors[ARMV7M_VECTAB_SIZE]
__attribute__ ((section (".ram_vectors"), aligned (RAMVEC_ALIGN)));
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -147,7 +121,7 @@ void up_ramvec_initialize(void)
src = (const CODE up_vector_t *)getreg32(NVIC_VECTAB);
dest = g_ram_vectors;
- intvdbg("src=%p dest=%p\n", src, dest);
+ irqinfo("src=%p dest=%p\n", src, dest);
for (i = 0; i < ARMV7M_VECTAB_SIZE; i++)
{
@@ -163,7 +137,7 @@ void up_ramvec_initialize(void)
* the table alignment is insufficient.
*/
- intvdbg("NVIC_VECTAB=%08x\n", getreg32(NVIC_VECTAB));
+ irqinfo("NVIC_VECTAB=%08x\n", getreg32(NVIC_VECTAB));
DEBUGASSERT(getreg32(NVIC_VECTAB) == (uint32_t)g_ram_vectors);
}
diff --git a/arch/arm/src/armv7-m/up_releasepending.c b/arch/arm/src/armv7-m/up_releasepending.c
index e9f4cceb33cdf2181f3273caa7bc473d0ea4201d..83be88094e75072d3bc5c8020673c247465829cf 100644
--- a/arch/arm/src/armv7-m/up_releasepending.c
+++ b/arch/arm/src/armv7-m/up_releasepending.c
@@ -66,7 +66,7 @@ void up_release_pending(void)
{
struct tcb_s *rtcb = this_task();
- slldbg("From TCB=%p\n", rtcb);
+ sinfo("From TCB=%p\n", rtcb);
/* Merge the g_pendingtasks list into the ready-to-run task list */
diff --git a/arch/arm/src/armv7-m/up_reprioritizertr.c b/arch/arm/src/armv7-m/up_reprioritizertr.c
index d3415e77414246695490bb00e54bb912dbb6dac7..5e65a3d33837b16d3928614b6fbd726d2009b34d 100644
--- a/arch/arm/src/armv7-m/up_reprioritizertr.c
+++ b/arch/arm/src/armv7-m/up_reprioritizertr.c
@@ -94,7 +94,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
struct tcb_s *rtcb = this_task();
bool switch_needed;
- slldbg("TCB=%p PRI=%d\n", tcb, priority);
+ sinfo("TCB=%p PRI=%d\n", tcb, priority);
/* Remove the tcb task from the ready-to-run list.
* sched_removereadytorun will return true if we just removed the head
diff --git a/arch/arm/src/armv7-m/up_schedulesigaction.c b/arch/arm/src/armv7-m/up_schedulesigaction.c
index c44298c14ece181a4a7033324d600a2258b752c8..42aa2932ba64ce13f56a3ef67af8512a83780ba1 100644
--- a/arch/arm/src/armv7-m/up_schedulesigaction.c
+++ b/arch/arm/src/armv7-m/up_schedulesigaction.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv7-m/up_schedulesigaction.c
*
- * Copyright (C) 2009-2014, 2016 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2009-2014, 2016-2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -52,6 +52,8 @@
#include "up_internal.h"
#include "up_arch.h"
+#include "irq/irq.h"
+
#ifndef CONFIG_DISABLE_SIGNALS
/****************************************************************************
@@ -91,11 +93,12 @@
*
****************************************************************************/
+#ifndef CONFIG_SMP
void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
{
irqstate_t flags;
- sdbg("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
+ sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
DEBUGASSERT(tcb != NULL && sigdeliver != NULL);
/* Make sure that interrupts are disabled */
@@ -110,7 +113,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* to the currently executing task.
*/
- sdbg("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
+ sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
if (tcb == this_task())
{
@@ -163,7 +166,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
#endif
CURRENT_REGS[REG_XPSR] = ARMV7M_XPSR_T;
#ifdef CONFIG_BUILD_PROTECTED
- CURRENT_REGS[REG_LR] = EXC_RETURN_PRIVTHR;
+ CURRENT_REGS[REG_LR] = EXC_RETURN_PRIVTHR;
#endif
/* And make sure that the saved context in the TCB is the same
* as the interrupt return context.
@@ -216,5 +219,214 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
leave_critical_section(flags);
}
+#endif /* !CONFIG_SMP */
+
+#ifdef CONFIG_SMP
+void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
+{
+ irqstate_t flags;
+ int cpu;
+ int me;
+
+ sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
+
+ /* Make sure that interrupts are disabled */
+
+ flags = enter_critical_section();
+
+ /* Refuse to handle nested signal actions */
+
+ if (!tcb->xcp.sigdeliver)
+ {
+ /* First, handle some special cases when the signal is being delivered
+ * to task that is currently executing on any CPU.
+ */
+
+ sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
+
+ if (tcb->task_state == TSTATE_TASK_RUNNING)
+ {
+ me = this_cpu();
+ cpu = tcb->cpu;
+
+ /* CASE 1: We are not in an interrupt handler and a task is
+ * signalling itself for some reason.
+ */
+
+ if (cpu == me && !CURRENT_REGS)
+ {
+ /* In this case just deliver the signal now. */
+
+ sigdeliver(tcb);
+ }
+
+ /* CASE 2: The task that needs to receive the signal is running.
+ * This could happen if the task is running on another CPU OR if
+ * we are in an interrupt handler and the task is running on this
+ * CPU. In the former case, we will have to PAUSE the other CPU
+ * first. But in either case, we will have to modify the return
+ * state as well as the state in the TCB.
+ *
+ * Hmmm... there looks like a latent bug here: The following logic
+ * would fail in the strange case where we are in an interrupt
+ * handler, the thread is signalling itself, but a context switch
+ * to another task has occurred so that CURRENT_REGS does not
+ * refer to the thread of this_task()!
+ */
+
+ else
+ {
+ /* If we signalling a task running on the other CPU, we have
+ * to PAUSE the other CPU.
+ */
+
+ if (cpu != me)
+ {
+ up_cpu_pause(cpu);
+ }
+
+ /* Save the return PC, CPSR and either the BASEPRI or PRIMASK
+ * registers (and perhaps also the LR). These will be
+ * restored by the signal trampoline after the signal has been
+ * delivered.
+ */
+
+ tcb->xcp.sigdeliver = (FAR void *)sigdeliver;
+ tcb->xcp.saved_pc = CURRENT_REGS[REG_PC];
+#ifdef CONFIG_ARMV7M_USEBASEPRI
+ tcb->xcp.saved_basepri = CURRENT_REGS[REG_BASEPRI];
+#else
+ tcb->xcp.saved_primask = CURRENT_REGS[REG_PRIMASK];
+#endif
+ tcb->xcp.saved_xpsr = CURRENT_REGS[REG_XPSR];
+#ifdef CONFIG_BUILD_PROTECTED
+ tcb->xcp.saved_lr = CURRENT_REGS[REG_LR];
+#endif
+ /* Increment the IRQ lock count so that when the task is restarted,
+ * it will hold the IRQ spinlock.
+ */
+
+ DEBUGASSERT(tcb->irqcount < INT16_MAX);
+ tcb->irqcount++;
+
+ /* Handle a possible race condition where the TCB was suspended
+ * just before we paused the other CPU. The critical section
+ * established above will prevent new threads from running on
+ * that CPU, but it will not guarantee that the running thread
+ * did not suspend itself (allowing any threads "assigned" to
+ * the CPU to run).
+ */
+
+ if (tcb->task_state != TSTATE_TASK_RUNNING)
+ {
+ /* Then set up to vector to the trampoline with interrupts
+ * disabled. We must already be in privileged thread mode
+ * to be here.
+ */
+
+ tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
+#ifdef CONFIG_ARMV7M_USEBASEPRI
+ tcb->xcp.regs[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY;
+#else
+ tcb->xcp.regs[REG_PRIMASK] = 1;
+#endif
+ tcb->xcp.regs[REG_XPSR] = ARMV7M_XPSR_T;
+#ifdef CONFIG_BUILD_PROTECTED
+ tcb->xcp.regs[REG_LR] = EXC_RETURN_PRIVTHR;
+#endif
+ }
+ else
+ {
+ /* Then set up to vector to the trampoline with interrupts
+ * disabled
+ */
+
+ CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver;
+#ifdef CONFIG_ARMV7M_USEBASEPRI
+ CURRENT_REGS[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY;
+#else
+ CURRENT_REGS[REG_PRIMASK] = 1;
+#endif
+ CURRENT_REGS[REG_XPSR] = ARMV7M_XPSR_T;
+#ifdef CONFIG_BUILD_PROTECTED
+ CURRENT_REGS[REG_LR] = EXC_RETURN_PRIVTHR;
+#endif
+ /* In an SMP configuration, the interrupt disable logic also
+ * involves spinlocks that are configured per the TCB irqcount
+ * field. This is logically equivalent to enter_critical_section().
+ * The matching call to leave_critical_section() will be
+ * performed in up_sigdeliver().
+ */
+
+ spin_setbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock,
+ &g_cpu_irqlock);
+
+ /* And make sure that the saved context in the TCB is the same
+ * as the interrupt return context.
+ */
+
+ up_savestate(tcb->xcp.regs);
+ }
+
+ /* RESUME the other CPU if it was PAUSED */
+
+ if (cpu != me)
+ {
+ up_cpu_resume(cpu);
+ }
+ }
+ }
+
+ /* Otherwise, we are (1) signaling a task is not running from an
+ * interrupt handler or (2) we are not in an interrupt handler and the
+ * running task is signalling some other non-running task.
+ */
+
+ else
+ {
+ /* Save the return PC, CPSR and either the BASEPRI or PRIMASK
+ * registers (and perhaps also the LR). These will be restored
+ * by the signal trampoline after the signal has been delivered.
+ */
+
+ tcb->xcp.sigdeliver = (FAR void *)sigdeliver;
+ tcb->xcp.saved_pc = tcb->xcp.regs[REG_PC];
+#ifdef CONFIG_ARMV7M_USEBASEPRI
+ tcb->xcp.saved_basepri = tcb->xcp.regs[REG_BASEPRI];
+#else
+ tcb->xcp.saved_primask = tcb->xcp.regs[REG_PRIMASK];
+#endif
+ tcb->xcp.saved_xpsr = tcb->xcp.regs[REG_XPSR];
+#ifdef CONFIG_BUILD_PROTECTED
+ tcb->xcp.saved_lr = tcb->xcp.regs[REG_LR];
+#endif
+ /* Increment the IRQ lock count so that when the task is restarted,
+ * it will hold the IRQ spinlock.
+ */
+
+ DEBUGASSERT(tcb->irqcount < INT16_MAX);
+ tcb->irqcount++;
+
+ /* Then set up to vector to the trampoline with interrupts
+ * disabled. We must already be in privileged thread mode to be
+ * here.
+ */
+
+ tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
+#ifdef CONFIG_ARMV7M_USEBASEPRI
+ tcb->xcp.regs[REG_BASEPRI] = NVIC_SYSH_DISABLE_PRIORITY;
+#else
+ tcb->xcp.regs[REG_PRIMASK] = 1;
+#endif
+ tcb->xcp.regs[REG_XPSR] = ARMV7M_XPSR_T;
+#ifdef CONFIG_BUILD_PROTECTED
+ tcb->xcp.regs[REG_LR] = EXC_RETURN_PRIVTHR;
+#endif
+ }
+ }
+
+ leave_critical_section(flags);
+}
+#endif /* CONFIG_SMP */
#endif /* !CONFIG_DISABLE_SIGNALS */
diff --git a/arch/arm/src/armv7-m/up_sigdeliver.c b/arch/arm/src/armv7-m/up_sigdeliver.c
index bfa672aa7acf3d154b2169869a9c9166149ea4bc..5aff11499c2630f32e12785f1c94e56d57e68b1d 100644
--- a/arch/arm/src/armv7-m/up_sigdeliver.c
+++ b/arch/arm/src/armv7-m/up_sigdeliver.c
@@ -54,18 +54,6 @@
#ifndef CONFIG_DISABLE_SIGNALS
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -95,7 +83,7 @@ void up_sigdeliver(void)
board_autoled_on(LED_SIGNAL);
- sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
+ sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
ASSERT(rtcb->xcp.sigdeliver != NULL);
@@ -124,9 +112,9 @@ void up_sigdeliver(void)
/* Then restore the task interrupt state */
#ifdef CONFIG_ARMV7M_USEBASEPRI
- up_irq_restore((uint8_t)regs[REG_BASEPRI]);
+ leave_critical_section((uint8_t)regs[REG_BASEPRI]);
#else
- up_irq_restore((uint16_t)regs[REG_PRIMASK]);
+ leave_critical_section((uint16_t)regs[REG_PRIMASK]);
#endif
/* Deliver the signal */
@@ -136,9 +124,18 @@ void up_sigdeliver(void)
/* Output any debug messages BEFORE restoring errno (because they may
* alter errno), then disable interrupts again and restore the original
* errno that is needed by the user logic (it is probably EINTR).
+ *
+ * REVISIT: In SMP mode up_irq_save() probably only disables interrupts
+ * on the local CPU. We do not want to call enter_critical_section()
+ * here, however, because we don't want this state to stick after the
+ * call to up_fullcontextrestore().
+ *
+ * I would prefer that all interrupts are disabled when
+ * up_fullcontextrestore() is called, but that may not be necessary.
*/
- sdbg("Resuming\n");
+ sinfo("Resuming\n");
+
(void)up_irq_save();
rtcb->pterrno = saved_errno;
diff --git a/arch/arm/src/armv7-m/up_signal_dispatch.c b/arch/arm/src/armv7-m/up_signal_dispatch.c
index 4a03a26b213e7d39ceedd7086c6c10162d4d6051..9ec7d151529ca35f84e4dc939165e35f8882d9a5 100644
--- a/arch/arm/src/armv7-m/up_signal_dispatch.c
+++ b/arch/arm/src/armv7-m/up_signal_dispatch.c
@@ -46,18 +46,6 @@
#if ((defined(CONFIG_BUILD_PROTECTED) && defined(__KERNEL__)) || \
defined(CONFIG_BUILD_KERNEL)) && !defined(CONFIG_DISABLE_SIGNALS)
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
diff --git a/arch/arm/src/armv7-m/up_svcall.c b/arch/arm/src/armv7-m/up_svcall.c
index 4d28224fd7eba41837ef4b49a91a4381733c4af4..e16a6f104c2dd841df3fe1b6d41cf3e9cf45c2ab 100644
--- a/arch/arm/src/armv7-m/up_svcall.c
+++ b/arch/arm/src/armv7-m/up_svcall.c
@@ -56,33 +56,6 @@
#include "exc_return.h"
#include "up_internal.h"
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-/* Configuration ************************************************************/
-
-/* Debug ********************************************************************/
-/* Debug output from this file may interfere with context switching! To get
- * debug output you must enabled the following in your NuttX configuration:
- *
- * - CONFIG_DEBUG and CONFIG_DEBUG_SYSCALL (shows only syscalls)
- * - CONFIG_DEBUG and CONFIG_DEBUG_SVCALL (shows everything)
- */
-
-#if defined(CONFIG_DEBUG_SYSCALL) || defined(CONFIG_DEBUG_SVCALL)
-# define svcdbg(format, ...) lldbg(format, ##__VA_ARGS__)
-#else
-# define svcdbg(x...)
-#endif
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -152,7 +125,7 @@ static void dispatch_syscall(void)
*
****************************************************************************/
-int up_svcall(int irq, FAR void *context)
+int up_svcall(int irq, FAR void *context, FAR void *arg)
{
uint32_t *regs = (uint32_t *)context;
uint32_t cmd;
@@ -164,23 +137,23 @@ int up_svcall(int irq, FAR void *context)
* and R1..R7 = variable number of arguments depending on the system call.
*/
-#if defined(CONFIG_DEBUG_SYSCALL) || defined(CONFIG_DEBUG_SVCALL)
+#ifdef CONFIG_DEBUG_SYSCALL_INFO
# ifndef CONFIG_DEBUG_SVCALL
if (cmd > SYS_switch_context)
# endif
{
- svcdbg("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd);
- svcdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
- regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
- svcdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
- regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
+ svcinfo("SVCALL Entry: regs: %p cmd: %d\n", regs, cmd);
+ svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
+ regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
+ svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
+ regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
# ifdef REG_EXC_RETURN
- svcdbg(" PSR: %08x EXC_RETURN: %08x\n",
- regs[REG_XPSR], regs[REG_EXC_RETURN]);
+ svcinfo(" PSR: %08x EXC_RETURN: %08x\n",
+ regs[REG_XPSR], regs[REG_EXC_RETURN]);
# else
- svcdbg(" PSR: %08x\n", regs[REG_XPSR]);
+ svcinfo(" PSR: %08x\n", regs[REG_XPSR]);
# endif
}
#endif
@@ -473,7 +446,7 @@ int up_svcall(int irq, FAR void *context)
regs[REG_R0] -= CONFIG_SYS_RESERVED;
#else
- slldbg("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
+ svcerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
#endif
}
break;
@@ -481,35 +454,35 @@ int up_svcall(int irq, FAR void *context)
/* Report what happened. That might difficult in the case of a context switch */
-#if defined(CONFIG_DEBUG_SYSCALL) || defined(CONFIG_DEBUG_SVCALL)
+#ifdef CONFIG_DEBUG_SYSCALL_INFO
# ifndef CONFIG_DEBUG_SVCALL
if (cmd > SYS_switch_context)
# else
if (regs != CURRENT_REGS)
# endif
{
- svcdbg("SVCall Return:\n");
- svcdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- CURRENT_REGS[REG_R0], CURRENT_REGS[REG_R1],
- CURRENT_REGS[REG_R2], CURRENT_REGS[REG_R3],
- CURRENT_REGS[REG_R4], CURRENT_REGS[REG_R5],
- CURRENT_REGS[REG_R6], CURRENT_REGS[REG_R7]);
- svcdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- CURRENT_REGS[REG_R8], CURRENT_REGS[REG_R9],
- CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
- CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
- CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
+ svcinfo("SVCall Return:\n");
+ svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ CURRENT_REGS[REG_R0], CURRENT_REGS[REG_R1],
+ CURRENT_REGS[REG_R2], CURRENT_REGS[REG_R3],
+ CURRENT_REGS[REG_R4], CURRENT_REGS[REG_R5],
+ CURRENT_REGS[REG_R6], CURRENT_REGS[REG_R7]);
+ svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ CURRENT_REGS[REG_R8], CURRENT_REGS[REG_R9],
+ CURRENT_REGS[REG_R10], CURRENT_REGS[REG_R11],
+ CURRENT_REGS[REG_R12], CURRENT_REGS[REG_R13],
+ CURRENT_REGS[REG_R14], CURRENT_REGS[REG_R15]);
# ifdef REG_EXC_RETURN
- svcdbg(" PSR: %08x EXC_RETURN: %08x\n",
- CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_EXC_RETURN]);
+ svcinfo(" PSR: %08x EXC_RETURN: %08x\n",
+ CURRENT_REGS[REG_XPSR], CURRENT_REGS[REG_EXC_RETURN]);
# else
- svcdbg(" PSR: %08x\n", CURRENT_REGS[REG_XPSR]);
+ svcinfo(" PSR: %08x\n", CURRENT_REGS[REG_XPSR]);
# endif
}
# ifdef CONFIG_DEBUG_SVCALL
else
{
- svcdbg("SVCall Return: %d\n", regs[REG_R0]);
+ svcinfo("SVCall Return: %d\n", regs[REG_R0]);
}
# endif
#endif
diff --git a/arch/arm/src/armv7-r/Kconfig b/arch/arm/src/armv7-r/Kconfig
index 0582a4fee3361af32e82c9d368bddce074040244..b4ec974db03d58b0a67a10b2eb5bb7c66ae7b6db 100644
--- a/arch/arm/src/armv7-r/Kconfig
+++ b/arch/arm/src/armv7-r/Kconfig
@@ -3,7 +3,7 @@
# see the file kconfig-language.txt in the NuttX tools repository.
#
-comment "ARMv7-A Configuration Options"
+comment "ARMv7-R Configuration Options"
config ARMV7R_MEMINIT
bool
@@ -19,6 +19,29 @@ config ARMV7R_MEMINIT
the memory initialization first, then explicitly call
arm_data_initialize().
+config ARMV7R_HAVE_ICACHE
+ bool
+ default n
+
+config ARMV7R_HAVE_DCACHE
+ bool
+ default n
+
+config ARMV7R_ICACHE
+ bool "Use I-Cache"
+ default n
+ depends on ARMV7R_HAVE_ICACHE
+
+config ARMV7R_DCACHE
+ bool "Use D-Cache"
+ default n
+ depends on ARMV7R_HAVE_DCACHE
+
+config ARMV7R_DCACHE_WRITETHROUGH
+ bool "D-Cache Write-Through"
+ default n
+ depends on ARMV7R_DCACHE
+
config ARMV7R_HAVE_L2CC
bool
default n
@@ -121,15 +144,17 @@ endif # ARMV7R_HAVE_L2CC
choice
prompt "Toolchain Selection"
- default ARMV7R_TOOLCHAIN_GNU_EABIW if HOST_WINDOWS
- default ARMV7R_TOOLCHAIN_GNU_EABIL if !HOST_WINDOWS
+ default ARMV7R_TOOLCHAIN_GNU_EABIW if TOOLCHAIN_WINDOWS
+ default ARMV7R_TOOLCHAIN_GNU_EABIL if !TOOLCHAIN_WINDOWS
config ARMV7R_TOOLCHAIN_BUILDROOT
bool "Buildroot (Cygwin or Linux)"
+ select ARM_TOOLCHAIN_GNU
depends on !WINDOWS_NATIVE
config ARMV7R_TOOLCHAIN_CODESOURCERYL
bool "CodeSourcery GNU toolchain under Linux"
+ select ARM_TOOLCHAIN_GNU
depends on HOST_LINUX
---help---
For use with the GNU toolchain built with the NuttX buildroot package.
@@ -138,31 +163,36 @@ config ARMV7R_TOOLCHAIN_CODESOURCERYL
config ARMV7R_TOOLCHAIN_CODESOURCERYW
bool "CodeSourcery GNU toolchain under Windows"
- depends on HOST_WINDOWS
+ select ARM_TOOLCHAIN_GNU
+ depends on TOOLCHAIN_WINDOWS
config ARMV7R_TOOLCHAIN_DEVKITARM
bool "devkitARM GNU toolchain"
- depends on HOST_WINDOWS
+ select ARM_TOOLCHAIN_GNU
+ depends on TOOLCHAIN_WINDOWS
config ARMV7R_TOOLCHAIN_GNU_EABIL
bool "Generic GNU EABI toolchain under Linux (or other POSIX environment)"
+ select ARM_TOOLCHAIN_GNU
---help---
This option should work for any modern GNU toolchain (GCC 4.5 or newer)
configured for arm-none-eabi-.
config ARMV7R_TOOLCHAIN_GNU_EABIW
bool "Generic GNU EABI toolchain under Windows"
- depends on HOST_WINDOWS
+ select ARM_TOOLCHAIN_GNU
+ depends on TOOLCHAIN_WINDOWS
---help---
This option should work for any modern GNU toolchain (GCC 4.5 or newer)
configured for arm-none-eabi-.
config ARMV7R_TOOLCHAIN_GNU_OABI
bool "Generic GNU OABI toolchain"
+ select ARM_TOOLCHAIN_GNU
---help---
This option should work for any GNU toolchain configured for arm-elf-.
-endchoice # ARMV7R_HAVE_L2CC
+endchoice # Toolchain Selection
config ARMV7R_OABI_TOOLCHAIN
bool "OABI (vs EABI)"
diff --git a/arch/arm/src/armv7-r/arm_assert.c b/arch/arm/src/armv7-r/arm_assert.c
index 11dd9fad09be9e339bb896a1767a819ff7e0583a..b841416450be9d4b20e612b6d2fea91c4d305c6a 100644
--- a/arch/arm/src/armv7-r/arm_assert.c
+++ b/arch/arm/src/armv7-r/arm_assert.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv7-r/arm_assert.c
*
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
#include
@@ -69,25 +58,13 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
+
/* USB trace dumping */
#ifndef CONFIG_USBDEV_TRACE
# undef CONFIG_ARCH_USBDUMP
#endif
-/* The following is just intended to keep some ugliness out of the mainline
- * code. We are going to print the task name if:
- *
- * CONFIG_TASK_NAME_SIZE > 0 && <-- The task has a name
- * (defined(CONFIG_DEBUG) || <-- And the debug is enabled (lldbg used)
- * defined(CONFIG_ARCH_STACKDUMP) <-- Or lowsyslog() is used
- */
-
-#undef CONFIG_PRINT_TASKNAME
-#if CONFIG_TASK_NAME_SIZE > 0 && (defined(CONFIG_DEBUG) || defined(CONFIG_ARCH_STACKDUMP))
-# define CONFIG_PRINT_TASKNAME 1
-#endif
-
/****************************************************************************
* Private Functions
****************************************************************************/
@@ -121,7 +98,7 @@ static void up_stackdump(uint32_t sp, uint32_t stack_base)
for (stack = sp & ~0x1f; stack < stack_base; stack += 32)
{
uint32_t *ptr = (uint32_t *)stack;
- lldbg("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ _alert("%08x: %08x %08x %08x %08x %08x %08x %08x %08x\n",
stack, ptr[0], ptr[1], ptr[2], ptr[3],
ptr[4], ptr[5], ptr[6], ptr[7]);
}
@@ -139,12 +116,12 @@ static void up_taskdump(FAR struct tcb_s *tcb, FAR void *arg)
{
/* Dump interesting properties of this task */
-#ifdef CONFIG_PRINT_TASKNAME
- lldbg("%s: PID=%d Stack Used=%lu of %lu\n",
+#if CONFIG_TASK_NAME_SIZE > 0
+ _alert("%s: PID=%d Stack Used=%lu of %lu\n",
tcb->name, tcb->pid, (unsigned long)up_check_tcbstack(tcb),
(unsigned long)tcb->adj_stack_size);
#else
- lldbg("PID: %d Stack Used=%lu of %lu\n",
+ _alert("PID: %d Stack Used=%lu of %lu\n",
tcb->pid, (unsigned long)up_check_tcbstack(tcb),
(unsigned long)tcb->adj_stack_size);
#endif
@@ -184,12 +161,12 @@ static inline void up_registerdump(void)
for (regs = REG_R0; regs <= REG_R15; regs += 8)
{
uint32_t *ptr = (uint32_t *)&CURRENT_REGS[regs];
- lldbg("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ _alert("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n",
regs, ptr[0], ptr[1], ptr[2], ptr[3],
ptr[4], ptr[5], ptr[6], ptr[7]);
}
- lldbg("CPSR: %08x\n", CURRENT_REGS[REG_CPSR]);
+ _alert("CPSR: %08x\n", CURRENT_REGS[REG_CPSR]);
}
}
#else
@@ -209,7 +186,7 @@ static int usbtrace_syslog(FAR const char *fmt, ...)
/* Let vsyslog do the real work */
va_start(ap, fmt);
- ret = lowvsyslog(LOG_INFO, fmt, ap);
+ ret = vsyslog(LOG_EMERG, fmt, ap);
va_end(ap);
return ret;
}
@@ -253,7 +230,7 @@ static void up_dumpstate(void)
ustacksize = (uint32_t)rtcb->adj_stack_size;
}
- lldbg("Current sp: %08x\n", sp);
+ _alert("Current sp: %08x\n", sp);
#if CONFIG_ARCH_INTERRUPTSTACK > 3
/* Get the limits on the interrupt stack memory */
@@ -263,21 +240,21 @@ static void up_dumpstate(void)
/* Show interrupt stack info */
- lldbg("Interrupt stack:\n");
- lldbg(" base: %08x\n", istackbase);
- lldbg(" size: %08x\n", istacksize);
+ _alert("Interrupt stack:\n");
+ _alert(" base: %08x\n", istackbase);
+ _alert(" size: %08x\n", istacksize);
#ifdef CONFIG_STACK_COLORATION
- lldbg(" used: %08x\n", up_check_intstack());
+ _alert(" used: %08x\n", up_check_intstack());
#endif
#endif
/* Show user stack info */
- lldbg("User stack:\n");
- lldbg(" base: %08x\n", ustackbase);
- lldbg(" size: %08x\n", ustacksize);
+ _alert("User stack:\n");
+ _alert(" base: %08x\n", ustackbase);
+ _alert(" size: %08x\n", ustacksize);
#ifdef CONFIG_STACK_COLORATION
- lldbg(" used: %08x\n", up_check_tcbstack(rtcb));
+ _alert(" used: %08x\n", up_check_tcbstack(rtcb));
#endif
#ifdef CONFIG_ARCH_KERNEL_STACK
@@ -287,9 +264,9 @@ static void up_dumpstate(void)
{
kstackbase = (uint32_t)rtcb->xcp.kstack + CONFIG_ARCH_KERNEL_STACKSIZE - 4;
- lldbg("Kernel stack:\n");
- lldbg(" base: %08x\n", kstackbase);
- lldbg(" size: %08x\n", CONFIG_ARCH_KERNEL_STACKSIZE);
+ _alert("Kernel stack:\n");
+ _alert(" base: %08x\n", kstackbase);
+ _alert(" size: %08x\n", CONFIG_ARCH_KERNEL_STACKSIZE);
}
#endif
@@ -300,7 +277,7 @@ static void up_dumpstate(void)
{
/* Yes.. dump the interrupt stack */
- lldbg("Interrupt Stack\n", sp);
+ _alert("Interrupt Stack\n", sp);
up_stackdump(sp, istackbase);
/* Extract the user stack pointer which should lie
@@ -308,7 +285,7 @@ static void up_dumpstate(void)
*/
sp = g_intstackbase;
- lldbg("User sp: %08x\n", sp);
+ _alert("User sp: %08x\n", sp);
}
#endif
@@ -318,7 +295,7 @@ static void up_dumpstate(void)
if (sp > ustackbase - ustacksize && sp < ustackbase)
{
- lldbg("User Stack\n", sp);
+ _alert("User Stack\n", sp);
up_stackdump(sp, ustackbase);
}
@@ -329,7 +306,7 @@ static void up_dumpstate(void)
if (sp >= (uint32_t)rtcb->xcp.kstack && sp < kstackbase)
{
- lldbg("Kernel Stack\n", sp);
+ _alert("Kernel Stack\n", sp);
up_stackdump(sp, kstackbase);
}
#endif
@@ -390,16 +367,16 @@ static void _up_assert(int errorcode)
void up_assert(const uint8_t *filename, int lineno)
{
-#ifdef CONFIG_PRINT_TASKNAME
+#if CONFIG_TASK_NAME_SIZE > 0 && defined(CONFIG_DEBUG_ALERT)
struct tcb_s *rtcb = this_task();
#endif
board_autoled_on(LED_ASSERTION);
-#ifdef CONFIG_PRINT_TASKNAME
- lldbg("Assertion failed at file:%s line: %d task: %s\n",
+#if CONFIG_TASK_NAME_SIZE > 0
+ _alert("Assertion failed at file:%s line: %d task: %s\n",
filename, lineno, rtcb->name);
#else
- lldbg("Assertion failed at file:%s line: %d\n",
+ _alert("Assertion failed at file:%s line: %d\n",
filename, lineno);
#endif
up_dumpstate();
diff --git a/arch/arm/src/armv7-r/arm_dataabort.c b/arch/arm/src/armv7-r/arm_dataabort.c
index 789fb0f5adae6e62bc6be4e1b919da3f9b56abcc..52f5d124365dbe84f502b6f133721e76e174faa2 100644
--- a/arch/arm/src/armv7-r/arm_dataabort.c
+++ b/arch/arm/src/armv7-r/arm_dataabort.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv7-r/arm_dataabort.c
*
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
@@ -86,7 +75,7 @@ uint32_t *arm_dataabort(uint32_t *regs, uint32_t dfar, uint32_t dfsr)
/* Crash -- possibly showing diagnostic debug information. */
- lldbg("Data abort. PC: %08x DFAR: %08x DFSR: %08x\n",
+ _alert("Data abort. PC: %08x DFAR: %08x DFSR: %08x\n",
regs[REG_PC], dfar, dfsr);
PANIC();
return regs; /* To keep the compiler happy */
diff --git a/arch/arm/src/armv7-r/arm_doirq.c b/arch/arm/src/armv7-r/arm_doirq.c
index fdf392d3384d5ceab1b845f49c83b511221c0032..5d492f5ddc7efb134a332b74f2c98a712def7ec9 100644
--- a/arch/arm/src/armv7-r/arm_doirq.c
+++ b/arch/arm/src/armv7-r/arm_doirq.c
@@ -52,22 +52,6 @@
#include "group/group.h"
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
diff --git a/arch/arm/src/armv7-r/arm_fullcontextrestore.S b/arch/arm/src/armv7-r/arm_fullcontextrestore.S
index 9f197063b27de976981cef4065527029a2b2d1cb..06daa2218262b5b223219b0f85450e505786911e 100644
--- a/arch/arm/src/armv7-r/arm_fullcontextrestore.S
+++ b/arch/arm/src/armv7-r/arm_fullcontextrestore.S
@@ -60,7 +60,6 @@
.cpu cortex-r4f
#endif
.syntax unified
- .file "arm_fullcontextrestore.S"
/****************************************************************************
* Public Functions
@@ -157,20 +156,11 @@ up_fullcontextrestore:
*/
ldr r1, [r0, #(4*REG_CPSR)] /* Fetch the stored CPSR value */
- msr cpsr, r1 /* Set the CPSR */
-
- /* Now recover r0 and r1 */
-
- ldr r0, [sp]
- ldr r1, [sp, #4]
- add sp, sp, #(2*4)
-
- /* Then return to the address at the stop of the stack,
- * destroying the stack frame
- */
+ msr spsr_cxsf, r1 /* Set the SPSR */
- ldr pc, [sp], #4
+ /* Now recover r0-r1, pc and cpsr, destroying the stack frame */
+ ldmia sp!, {r0-r1, pc}^
#endif
.size up_fullcontextrestore, . - up_fullcontextrestore
diff --git a/arch/arm/src/armv7-r/arm_l2cc_pl310.c b/arch/arm/src/armv7-r/arm_l2cc_pl310.c
index e019e70e95f2e95d4a1581da09d3f350585c29d1..18c3d224a2c6cbfb6e10d62007f55c42f3c0709f 100644
--- a/arch/arm/src/armv7-r/arm_l2cc_pl310.c
+++ b/arch/arm/src/armv7-r/arm_l2cc_pl310.c
@@ -411,8 +411,8 @@ void up_l2ccinitialize(void)
putreg32(L2CC_CR_L2CEN, L2CC_CR);
}
- lldbg("(%d ways) * (%d bytes/way) = %d bytes\n",
- PL310_NWAYS, PL310_WAYSIZE, PL310_CACHE_SIZE);
+ sinfo("(%d ways) * (%d bytes/way) = %d bytes\n",
+ PL310_NWAYS, PL310_WAYSIZE, PL310_CACHE_SIZE);
}
/****************************************************************************
diff --git a/arch/arm/src/armv7-r/arm_prefetchabort.c b/arch/arm/src/armv7-r/arm_prefetchabort.c
index bf16d194676ce28f4402db9c4330a28c73c90c6a..74713f5ad3eae3be527be24885bab7aaea3df460 100644
--- a/arch/arm/src/armv7-r/arm_prefetchabort.c
+++ b/arch/arm/src/armv7-r/arm_prefetchabort.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv7-r/arm_prefetchabort.c
*
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
@@ -82,7 +71,7 @@ uint32_t *arm_prefetchabort(uint32_t *regs, uint32_t ifar, uint32_t ifsr)
/* Crash -- possibly showing diagnostic debug information. */
- lldbg("Prefetch abort. PC: %08x IFAR: %08x IFSR: %08x\n",
+ _alert("Prefetch abort. PC: %08x IFAR: %08x IFSR: %08x\n",
regs[REG_PC], ifar, ifsr);
PANIC();
return regs; /* To keep the compiler happy */
diff --git a/arch/arm/src/armv7-r/arm_releasepending.c b/arch/arm/src/armv7-r/arm_releasepending.c
index 89827085907498d7edaab83db8dd1fab47e3c817..a66de941356278880015b60eeeec25132b261cdf 100644
--- a/arch/arm/src/armv7-r/arm_releasepending.c
+++ b/arch/arm/src/armv7-r/arm_releasepending.c
@@ -67,7 +67,7 @@ void up_release_pending(void)
{
struct tcb_s *rtcb = this_task();
- slldbg("From TCB=%p\n", rtcb);
+ sinfo("From TCB=%p\n", rtcb);
/* Merge the g_pendingtasks list into the ready-to-run task list */
diff --git a/arch/arm/src/armv7-r/arm_reprioritizertr.c b/arch/arm/src/armv7-r/arm_reprioritizertr.c
index 4fed13e8f272ca7b43fd90e1e65109e3bc18ae63..db96424eb2f4d6042c672334f327784d4fcecbee 100644
--- a/arch/arm/src/armv7-r/arm_reprioritizertr.c
+++ b/arch/arm/src/armv7-r/arm_reprioritizertr.c
@@ -95,7 +95,7 @@ void up_reprioritize_rtr(struct tcb_s *tcb, uint8_t priority)
struct tcb_s *rtcb = this_task();
bool switch_needed;
- slldbg("TCB=%p PRI=%d\n", tcb, priority);
+ sinfo("TCB=%p PRI=%d\n", tcb, priority);
/* Remove the tcb task from the ready-to-run list.
* sched_removereadytorun will return true if we just
diff --git a/arch/arm/src/armv7-r/arm_schedulesigaction.c b/arch/arm/src/armv7-r/arm_schedulesigaction.c
index 692debff2f0590db39b0d6d12d8c716cdf210c9f..a51d660cb4c686297671874d892868d1d91d266d 100644
--- a/arch/arm/src/armv7-r/arm_schedulesigaction.c
+++ b/arch/arm/src/armv7-r/arm_schedulesigaction.c
@@ -94,7 +94,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
{
irqstate_t flags;
- sdbg("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
+ sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
/* Make sure that interrupts are disabled */
@@ -108,7 +108,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
* to the currently executing task.
*/
- sdbg("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
+ sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
if (tcb == this_task())
{
diff --git a/arch/arm/src/armv7-r/arm_sigdeliver.c b/arch/arm/src/armv7-r/arm_sigdeliver.c
index f638b35bfd64aec670f86dca54c1a23ebe4ad4c3..280a5ef9c71b0bb360fc444edb21675d85c72eab 100644
--- a/arch/arm/src/armv7-r/arm_sigdeliver.c
+++ b/arch/arm/src/armv7-r/arm_sigdeliver.c
@@ -83,7 +83,7 @@ void up_sigdeliver(void)
board_autoled_on(LED_SIGNAL);
- sdbg("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
+ sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n",
rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head);
ASSERT(rtcb->xcp.sigdeliver != NULL);
@@ -114,7 +114,7 @@ void up_sigdeliver(void)
* errno that is needed by the user logic (it is probably EINTR).
*/
- sdbg("Resuming\n");
+ sinfo("Resuming\n");
(void)up_irq_save();
rtcb->pterrno = saved_errno;
diff --git a/arch/arm/src/armv7-r/arm_syscall.c b/arch/arm/src/armv7-r/arm_syscall.c
index 3e41a3484344f1dafbbfa8258f892f3986c125b8..49290d5509ef138578d1f52f66b62982f21f17cf 100644
--- a/arch/arm/src/armv7-r/arm_syscall.c
+++ b/arch/arm/src/armv7-r/arm_syscall.c
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
#include
@@ -64,18 +53,7 @@
#include "up_internal.h"
/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-/* Debug ********************************************************************/
-
-#if defined(CONFIG_DEBUG_SYSCALL)
-# define svcdbg(format, ...) lldbg(format, ##__VA_ARGS__)
-#else
-# define svcdbg(x...)
-#endif
-
-/****************************************************************************
- * Private Data
+ * Private Functions
****************************************************************************/
/****************************************************************************
@@ -176,16 +154,14 @@ uint32_t *arm_syscall(uint32_t *regs)
* and R1..R7 = variable number of arguments depending on the system call.
*/
-#if defined(CONFIG_DEBUG_SYSCALL)
- svcdbg("SYSCALL Entry: regs: %p cmd: %d\n", regs, cmd);
- svcdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
- regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
- svcdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
- regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
- svcdbg("CPSR: %08x\n", regs[REG_CPSR]);
-#endif
+ svcinfo("SYSCALL Entry: regs: %p cmd: %d\n", regs, cmd);
+ svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
+ regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
+ svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
+ regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
+ svcinfo("CPSR: %08x\n", regs[REG_CPSR]);
/* Handle the SVCall according to the command in R0 */
@@ -478,7 +454,7 @@ uint32_t *arm_syscall(uint32_t *regs)
regs[REG_R0] -= CONFIG_SYS_RESERVED;
#else
- svcdbg("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
+ svcerr("ERROR: Bad SYS call: %d\n", regs[REG_R0]);
#endif
#ifdef CONFIG_ARCH_KERNEL_STACK
@@ -499,18 +475,16 @@ uint32_t *arm_syscall(uint32_t *regs)
break;
}
-#if defined(CONFIG_DEBUG_SYSCALL)
/* Report what happened */
- svcdbg("SYSCALL Exit: regs: %p\n", regs);
- svcdbg(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
- regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
- svcdbg(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
- regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
- regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
- svcdbg("CPSR: %08x\n", regs[REG_CPSR]);
-#endif
+ svcinfo("SYSCALL Exit: regs: %p\n", regs);
+ svcinfo(" R0: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R0], regs[REG_R1], regs[REG_R2], regs[REG_R3],
+ regs[REG_R4], regs[REG_R5], regs[REG_R6], regs[REG_R7]);
+ svcinfo(" R8: %08x %08x %08x %08x %08x %08x %08x %08x\n",
+ regs[REG_R8], regs[REG_R9], regs[REG_R10], regs[REG_R11],
+ regs[REG_R12], regs[REG_R13], regs[REG_R14], regs[REG_R15]);
+ svcinfo("CPSR: %08x\n", regs[REG_CPSR]);
/* Return the last value of curent_regs. This supports context switches
* on return from the exception. That capability is only used with the
@@ -524,7 +498,7 @@ uint32_t *arm_syscall(uint32_t *regs)
uint32_t *arm_syscall(uint32_t *regs)
{
- lldbg("SYSCALL from 0x%x\n", regs[REG_PC]);
+ _alert("SYSCALL from 0x%x\n", regs[REG_PC]);
CURRENT_REGS = regs;
PANIC();
}
diff --git a/arch/arm/src/armv7-r/arm_testset.S b/arch/arm/src/armv7-r/arm_testset.S
index 7cd741fed734dfe86cd9b803306c74fc09973435..f82837d5fe8f688779b5620a0ad03fa029631071 100644
--- a/arch/arm/src/armv7-r/arm_testset.S
+++ b/arch/arm/src/armv7-r/arm_testset.S
@@ -70,7 +70,7 @@
* Name: up_testset
*
* Description:
- * Perform and atomic test and set operation on the provided spinlock.
+ * Perform an atomic test and set operation on the provided spinlock.
*
* This function must be provided via the architecture-specific logoic.
*
diff --git a/arch/arm/src/armv7-r/arm_undefinedinsn.c b/arch/arm/src/armv7-r/arm_undefinedinsn.c
index b1db4f88686c6f35d98ef625c8e3a50a1b4af2dc..733fb06cb2b4ec245e40aa0fcf3e96ab73a5f5bc 100644
--- a/arch/arm/src/armv7-r/arm_undefinedinsn.c
+++ b/arch/arm/src/armv7-r/arm_undefinedinsn.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv7-r/arm_undefinedinsn.c
*
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Redistribution and use in source and binary forms, with or without
@@ -39,17 +39,6 @@
#include
-/* Output debug info if stack dump is selected -- even if debug is not
- * selected.
- */
-
-#ifdef CONFIG_ARCH_STACKDUMP
-# undef CONFIG_DEBUG
-# undef CONFIG_DEBUG_VERBOSE
-# define CONFIG_DEBUG 1
-# define CONFIG_DEBUG_VERBOSE 1
-#endif
-
#include
#include
#include
@@ -58,18 +47,6 @@
#include "up_internal.h"
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -80,7 +57,7 @@
uint32_t *arm_undefinedinsn(uint32_t *regs)
{
- lldbg("Undefined instruction at 0x%x\n", regs[REG_PC]);
+ _alert("Undefined instruction at 0x%x\n", regs[REG_PC]);
CURRENT_REGS = regs;
PANIC();
return regs; /* To keep the compiler happy */
diff --git a/arch/arm/src/armv7-r/arm_vectors.S b/arch/arm/src/armv7-r/arm_vectors.S
index 216633e3a36f47d7c16ca8ae23af25aec2bd5bd8..bea7c927bcebf14c8e4aee423be394ccb3b58870 100644
--- a/arch/arm/src/armv7-r/arm_vectors.S
+++ b/arch/arm/src/armv7-r/arm_vectors.S
@@ -202,7 +202,7 @@ arm_vectorirq:
/* Restore the CPSR, SVC mode registers and return */
ldr r1, [r0, #(4*REG_CPSR)] /* Fetch the return SPSR */
- msr spsr, r1 /* Set the return mode SPSR */
+ msr spsr_cxsf, r1 /* Set the return mode SPSR */
#ifdef CONFIG_BUILD_PROTECTED
/* Are we leaving in user mode? If so then we need to restore the
@@ -331,7 +331,7 @@ arm_vectorsvc:
/* Restore the CPSR, SVC mode registers and return */
ldr r1, [r0, #(4*REG_CPSR)] /* Fetch the return SPSR */
- msr spsr, r1 /* Set the return mode SPSR */
+ msr spsr_cxsf, r1 /* Set the return mode SPSR */
#ifdef CONFIG_BUILD_PROTECTED
/* Are we leaving in user mode? If so then we need to restore the
@@ -913,7 +913,7 @@ arm_vectorfiq:
/* Restore the CPSR, SVC mode registers and return */
ldr r1, [r0, #(4*REG_CPSR)] /* Fetch the return SPSR */
- msr spsr, r1 /* Set the return mode SPSR */
+ msr spsr_cxsf, r1 /* Set the return mode SPSR */
#ifdef CONFIG_BUILD_PROTECTED
/* Are we leaving in user mode? If so then we need to restore the
diff --git a/arch/arm/src/armv7-r/cache.h b/arch/arm/src/armv7-r/cache.h
index 2c60fe2c3d62d266e01506c6473f4473609efb42..721f40313f29236c6ffcc0b7d0f10ec304129ccf 100644
--- a/arch/arm/src/armv7-r/cache.h
+++ b/arch/arm/src/armv7-r/cache.h
@@ -43,6 +43,7 @@
#include
#include
+#include "sctlr.h"
#include "cp15_cacheops.h"
#include "l2cc.h"
@@ -50,7 +51,17 @@
* Pre-processor Definitions
************************************************************************************/
- /************************************************************************************
+/* Intrinsics are used in these inline functions */
+
+#define arm_isb(n) __asm__ __volatile__ ("isb " #n : : : "memory")
+#define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory")
+#define arm_dmb(n) __asm__ __volatile__ ("dmb " #n : : : "memory")
+
+#define ARM_DSB() arm_dsb(15)
+#define ARM_ISB() arm_isb(15)
+#define ARM_DMB() arm_dmb(15)
+
+/************************************************************************************
* Inline Functions
************************************************************************************/
@@ -183,6 +194,70 @@ static inline void arch_flush_dcache(uintptr_t start, uintptr_t end)
l2cc_flush(start, end);
}
+/****************************************************************************
+ * Name: arch_enable_icache
+ *
+ * Description:
+ * Enable the I-Cache
+ *
+ * Input Parameters:
+ * None
+ *
+ * Returned Value:
+ * None
+ *
+ ****************************************************************************/
+
+static inline void arch_enable_icache(void)
+{
+#ifdef CONFIG_ARMV7R_ICACHE
+ uint32_t regval;
+
+ ARM_DSB();
+ ARM_ISB();
+
+ /* Enable the I-Cache */
+
+ regval = cp15_rdsctlr();
+ if ((regval & SCTLR_I) == 0)
+ {
+ cp15_wrsctlr(regval | SCTLR_I);
+ }
+
+ ARM_DSB();
+ ARM_ISB();
+#endif
+}
+
+/****************************************************************************
+* Name: arch_enable_dcache
+*
+* Description:
+* Enable the D-Cache
+*
+* Input Parameters:
+* None
+*
+* Returned Value:
+* None
+*
+****************************************************************************/
+
+static inline void arch_enable_dcache(void)
+{
+#ifdef CONFIG_ARMV7R_DCACHE
+ uint32_t regval;
+
+ /* Enable the D-Cache */
+
+ regval = cp15_rdsctlr();
+ if ((regval & SCTLR_C) == 0)
+ {
+ cp15_wrsctlr(regval | SCTLR_C);
+ }
+#endif
+}
+
/****************************************************************************
* Public Data
****************************************************************************/
diff --git a/arch/arm/src/armv7-r/cp15_coherent_dcache.S b/arch/arm/src/armv7-r/cp15_coherent_dcache.S
index fa8b728f28713a874fa8858e7fb5f183d134103d..beecbd9733dbe15260cdddbd2854c7e1e270cca8 100644
--- a/arch/arm/src/armv7-r/cp15_coherent_dcache.S
+++ b/arch/arm/src/armv7-r/cp15_coherent_dcache.S
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/armv7-r/cp15_coherent_dcache.S
*
- * Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2015, 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* References:
@@ -93,7 +93,7 @@
.type cp15_coherent_dcache, function
cp15_coherent_dcache:
- mrc CP15_CTR(r3) /* Read the Cache Type Register */
+ mrc CP15_CTR(r3) /* Read the Cache Type Register */
lsr r3, r3, #16 /* Isolate the DMinLine field */
and r3, r3, #0xf
mov r2, #4
@@ -111,7 +111,7 @@ cp15_coherent_dcache:
dsb
- mrc CP15_CTR(r3) /* Read the Cache Type Register */
+ mrc CP15_CTR(r3) /* Read the Cache Type Register */
and r3, r3, #0xf /* Isolate the IminLine field */
mov r2, #4
mov r2, r2, lsl r3 /* Get the cache line size in bytes */
@@ -127,8 +127,10 @@ cp15_coherent_dcache:
blo 1b
mov r0, #0
+#ifdef CONFIG_SMP
mcr CP15_BPIALLIS(r0) /* Invalidate entire branch predictor array Inner Shareable */
- mcr CP15_BPIALL(r0) /* Invalidate entire branch predictor array Inner Shareable */
+#endif
+ mcr CP15_BPIALL(r0) /* Invalidate all branch predictors */
dsb
isb
diff --git a/arch/arm/src/armv7-r/mpu.h b/arch/arm/src/armv7-r/mpu.h
index 67aeb2e94a240db6b6f00282643b4590dca98065..7c1a201567db5188478ece9a7d3bce27a3dc62bc 100644
--- a/arch/arm/src/armv7-r/mpu.h
+++ b/arch/arm/src/armv7-r/mpu.h
@@ -49,6 +49,8 @@
# include
# include "up_arch.h"
+# include "cache.h"
+# include "sctlr.h"
# include "cp15.h"
#endif
@@ -66,7 +68,7 @@
/* Region Base Address Register Definitions */
-#define MPU_RBAR_MASK 0xfffffffc
+#define MPU_RBAR_ADDR_MASK 0xfffffffc
/* Region Size and Enable Register */
@@ -201,7 +203,7 @@ static inline unsigned int mpu_get_mpuir(void)
unsigned int mpuir;
__asm__ __volatile__
(
- "\tmrc " CP15_MPUIR(%0)
+ "\tmrc p15, 0, %0, c0, c0, 4"
: "=r" (mpuir)
:
: "memory"
@@ -222,7 +224,7 @@ static inline void mpu_set_drbar(unsigned int drbar)
{
__asm__ __volatile__
(
- "\tmcr " CP15_DRBAR(%0)
+ "\tmcr p15, 0, %0, c6, c1, 0"
:
: "r" (drbar)
: "memory"
@@ -241,7 +243,7 @@ static inline void mpu_set_drsr(unsigned int drsr)
{
__asm__ __volatile__
(
- "\tmcr " CP15_DRSR(%0)
+ "\tmcr p15, 0, %0, c6, c1, 2"
:
: "r" (drsr)
: "memory"
@@ -260,7 +262,7 @@ static inline void mpu_set_dracr(unsigned int dracr)
{
__asm__ __volatile__
(
- "\tmcr " CP15_DRACR(%0)
+ "\tmcr p15, 0, %0, c6, c1, 4"
:
: "r" (dracr)
: "memory"
@@ -280,7 +282,7 @@ static inline void mpu_set_irbar(unsigned int irbar)
{
__asm__ __volatile__
(
- "\tmcr " CP15_IRBAR(%0)
+ "\tmcr p15, 0, %0, c6, c1, 1"
:
: "r" (irbar)
: "memory"
@@ -301,7 +303,7 @@ static inline void mpu_set_irsr(unsigned int irsr)
{
__asm__ __volatile__
(
- "\tmcr " CP15_IRSR(%0)
+ "\tmcr p15, 0, %0, c6, c1, 3"
:
: "r" (irsr)
: "memory"
@@ -322,7 +324,7 @@ static inline void mpu_set_iracr(unsigned int iracr)
{
__asm__ __volatile__
(
- "\tmcr " CP15_IRACR(%0)
+ "\tmcr p15, 0, %0, c6, c1, 5"
:
: "r" (iracr)
: "memory"
@@ -342,7 +344,7 @@ static inline void mpu_set_rgnr(unsigned int rgnr)
{
__asm__ __volatile__
(
- "\tmcr " CP15_RGNR(%0)
+ "\tmcr p15, 0, %0, c6, c2, 0"
:
: "r" (rgnr)
: "memory"
@@ -359,12 +361,12 @@ static inline void mpu_set_rgnr(unsigned int rgnr)
static inline void mpu_showtype(void)
{
-#ifdef CONFIG_DEBUG
+#ifdef CONFIG_DEBUG_SCHED_INFO
uint32_t regval = mpu_get_mpuir();
- dbg("%s MPU Regions: data=%d instr=%d\n",
- (regval & MPUIR_SEPARATE) != 0 ? "Separate" : "Unified",
- (regval & MPUIR_DREGION_MASK) >> MPUIR_DREGION_SHIFT,
- (regval & MPUIR_IREGION_MASK) >> MPUIR_IREGION_SHIFT);
+ sinfo("%s MPU Regions: data=%d instr=%d\n",
+ (regval & MPUIR_SEPARATE) != 0 ? "Separate" : "Unified",
+ (regval & MPUIR_DREGION_MASK) >> MPUIR_DREGION_SHIFT,
+ (regval & MPUIR_IREGION_MASK) >> MPUIR_IREGION_SHIFT);
#endif
}
@@ -390,7 +392,6 @@ static inline void mpu_control(bool enable)
if (enable)
{
regval |= (SCTLR_M | SCTLR_BR);
- cp15_wrsctlr(regval);
}
else
{
@@ -408,7 +409,7 @@ static inline void mpu_control(bool enable)
*
****************************************************************************/
-#if defined(CONFIG_ARMV7M_HAVE_ICACHE) || defined(CONFIG_ARMV7M_DCACHE)
+#if defined(CONFIG_ARMV7R_HAVE_ICACHE) || defined(CONFIG_ARMV7R_DCACHE)
static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size)
{
unsigned int region = mpu_allocregion();
@@ -422,7 +423,7 @@ static inline void mpu_priv_stronglyordered(uintptr_t base, size_t size)
/* Select the region base address */
- mpu_set_drbar(base & MPU_RBAR_ADDR_MASK) | region | MPU_RBAR_VALID);
+ mpu_set_drbar(base & MPU_RBAR_ADDR_MASK);
/* Select the region size and the sub-region map */
@@ -465,7 +466,7 @@ static inline void mpu_user_flash(uintptr_t base, size_t size)
/* Select the region base address */
- mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region);
+ mpu_set_drbar(base & MPU_RBAR_ADDR_MASK);
/* Select the region size and the sub-region map */
@@ -506,7 +507,7 @@ static inline void mpu_priv_flash(uintptr_t base, size_t size)
/* Select the region base address */
- mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region);
+ mpu_set_drbar(base & MPU_RBAR_ADDR_MASK);
/* Select the region size and the sub-region map */
@@ -546,7 +547,7 @@ static inline void mpu_user_intsram(uintptr_t base, size_t size)
/* Select the region base address */
- mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region);
+ mpu_set_drbar(base & MPU_RBAR_ADDR_MASK);
/* Select the region size and the sub-region map */
@@ -587,7 +588,7 @@ static inline void mpu_priv_intsram(uintptr_t base, size_t size)
/* Select the region base address */
- mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region);
+ mpu_set_drbar(base & MPU_RBAR_ADDR_MASK);
/* Select the region size and the sub-region map */
@@ -628,7 +629,7 @@ static inline void mpu_user_extsram(uintptr_t base, size_t size)
/* Select the region base address */
- mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region);
+ mpu_set_drbar(base & MPU_RBAR_ADDR_MASK);
/* Select the region size and the sub-region map */
@@ -670,7 +671,7 @@ static inline void mpu_priv_extsram(uintptr_t base, size_t size)
/* Select the region base address */
- mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region);
+ mpu_set_drbar(base & MPU_RBAR_ADDR_MASK);
/* Select the region size and the sub-region map */
@@ -712,7 +713,7 @@ static inline void mpu_peripheral(uintptr_t base, size_t size)
/* Select the region base address */
- mpu_set_drbar((base & MPU_RBAR_ADDR_MASK) | region);
+ mpu_set_drbar(base & MPU_RBAR_ADDR_MASK);
/* Select the region size and the sub-region map */
diff --git a/arch/arm/src/c5471/Kconfig b/arch/arm/src/c5471/Kconfig
index 17b615a0973de6b10fe31faaecf11b7afd0054fc..5f46d7684a967f190b343a84a55c81e9e26fae08 100644
--- a/arch/arm/src/c5471/Kconfig
+++ b/arch/arm/src/c5471/Kconfig
@@ -110,3 +110,23 @@ config C5471_BASET10
bool "10BaseT FullDuplex"
endchoice
+
+choice
+ prompt "Ethernet work queue"
+ default C5471_LPWORK if SCHED_LPWORK
+ default C5471_HPWORK if !SCHED_LPWORK && SCHED_HPWORK
+ depends on SCHED_WORKQUEUE
+ ---help---
+ Work queue support is required to use the Ethernet driver. If the
+ low priority work queue is available, then it should be used by the
+ driver.
+
+config C5471_HPWORK
+ bool "High priority"
+ depends on SCHED_HPWORK
+
+config C5471_LPWORK
+ bool "Low priority"
+ depends on SCHED_LPWORK
+
+endchoice # Work queue
diff --git a/arch/arm/src/c5471/Make.defs b/arch/arm/src/c5471/Make.defs
index 92320e5d480af0fc2b7d5d84672d5c1b59e62daa..a0c3b9a5b399cad6adbf08f4eb37c0326bd212a9 100644
--- a/arch/arm/src/c5471/Make.defs
+++ b/arch/arm/src/c5471/Make.defs
@@ -45,12 +45,6 @@ CMN_CSRCS += up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c
CMN_CSRCS += up_sigdeliver.c up_stackframe.c up_syscall.c up_unblocktask.c
CMN_CSRCS += up_undefinedinsn.c up_usestack.c up_vfork.c
-ifeq ($(CONFIG_ELF),y)
-CMN_CSRCS += up_elf.c
-else ifeq ($(CONFIG_MODULE),y)
-CMN_CSRCS += up_elf.c
-endif
-
ifeq ($(CONFIG_STACK_COLORATION),y)
CMN_CSRCS += up_checkstack.c
endif
diff --git a/arch/arm/src/c5471/c5471_ethernet.c b/arch/arm/src/c5471/c5471_ethernet.c
index 5d1ddb686322c6f2fb36a35b26aa9e3590f9278a..03ddbe33837179b224215d5e7b10c658beacfc6d 100644
--- a/arch/arm/src/c5471/c5471_ethernet.c
+++ b/arch/arm/src/c5471/c5471_ethernet.c
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/arm/src/c5471/c5471_ethernet.c
*
- * Copyright (C) 2007, 2009-2010, 2014-2015 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2007, 2009-2010, 2014-2015, 2017 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
*
* Based one a C5471 Linux driver and released under this BSD license with
@@ -59,6 +59,7 @@
#include
#include
#include
+#include
#include
#include
@@ -75,6 +76,25 @@
****************************************************************************/
/* Configuration ************************************************************/
+/* If processing is not done at the interrupt level, then work queue support
+ * is required.
+ */
+
+#if !defined(CONFIG_SCHED_WORKQUEUE)
+# error Work queue support is required in this configuration (CONFIG_SCHED_WORKQUEUE)
+#else
+
+ /* Use the low priority work queue if possible */
+
+# if defined(CONFIG_C5471_HPWORK)
+# define ETHWORK HPWORK
+# elif defined(CONFIG_C5471_LPWORK)
+# define ETHWORK LPWORK
+# else
+# error Neither CONFIG_C5471_HPWORK nor CONFIG_C5471_LPWORK defined
+# endif
+#endif
+
/* CONFIG_C5471_NET_NINTERFACES determines the number of physical interfaces
* that will be supported.
*/
@@ -273,12 +293,16 @@
/* This is a helper pointer for accessing the contents of the Ethernet header */
-#define BUF ((struct eth_hdr_s *)c5471->c_dev.d_buf)
+#define BUF ((struct eth_hdr_s *)priv->c_dev.d_buf)
/****************************************************************************
* Private Types
****************************************************************************/
+/* A single packet buffer is used */
+
+static uint8_t g_pktbuf[MAX_NET_DEV_MTU + CONFIG_NET_GUARDSIZE];
+
/* The c5471_driver_s encapsulates all state information for a single c5471
* hardware interface
*/
@@ -288,6 +312,8 @@ struct c5471_driver_s
bool c_bifup; /* true:ifup false:ifdown */
WDOG_ID c_txpoll; /* TX poll timer */
WDOG_ID c_txtimeout; /* TX timeout timer */
+ struct work_s c_irqwork; /* For deferring interrupt work to the work queue */
+ struct work_s c_pollwork; /* For deferring poll work to the work queue */
/* Note: According to the C547x documentation: "The software has to maintain
* two pointers to the current RX-CPU and TX-CPU descriptors. At init time,
@@ -356,36 +382,44 @@ static int c5471_phyinit (void);
/* Support logic */
-static inline void c5471_inctxcpu(struct c5471_driver_s *c5471);
-static inline void c5471_incrxcpu(struct c5471_driver_s *c5471);
+static inline void c5471_inctxcpu(struct c5471_driver_s *priv);
+static inline void c5471_incrxcpu(struct c5471_driver_s *priv);
/* Common TX logic */
-static int c5471_transmit(struct c5471_driver_s *c5471);
+static int c5471_transmit(struct c5471_driver_s *priv);
static int c5471_txpoll(struct net_driver_s *dev);
/* Interrupt handling */
#ifdef CONFIG_C5471_NET_STATS
-static void c5471_rxstatus(struct c5471_driver_s *c5471);
+static void c5471_rxstatus(struct c5471_driver_s *priv);
#endif
-static void c5471_receive(struct c5471_driver_s *c5471);
+static void c5471_receive(struct c5471_driver_s *priv);
#ifdef CONFIG_C5471_NET_STATS
-static void c5471_txstatus(struct c5471_driver_s *c5471);
+static void c5471_txstatus(struct c5471_driver_s *priv);
#endif
-static void c5471_txdone(struct c5471_driver_s *c5471);
-static int c5471_interrupt(int irq, FAR void *context);
+static void c5471_txdone(struct c5471_driver_s *priv);
+
+static void c5471_interrupt_work(FAR void *arg);
+static int c5471_interrupt(int irq, FAR void *context, FAR void *arg);
/* Watchdog timer expirations */
-static void c5471_polltimer(int argc, uint32_t arg, ...);
-static void c5471_txtimeout(int argc, uint32_t arg, ...);
+static void c5471_txtimeout_work(FAR void *arg);
+static void c5471_txtimeout_expiry(int argc, uint32_t arg, ...);
+
+static void c5471_poll_work(FAR void *arg);
+static void c5471_poll_expiry(int argc, uint32_t arg, ...);
/* NuttX callback functions */
static int c5471_ifup(struct net_driver_s *dev);
static int c5471_ifdown(struct net_driver_s *dev);
+
+static void c5471_txavail_work(FAR void *arg);
static int c5471_txavail(struct net_driver_s *dev);
+
#ifdef CONFIG_NET_IGMP
static int c5471_addmac(struct net_driver_s *dev, FAR const uint8_t *mac);
static int c5471_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac);
@@ -393,10 +427,10 @@ static int c5471_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac);
/* Initialization functions */
-static void c5471_eimreset (struct c5471_driver_s *c5471);
-static void c5471_eimconfig(struct c5471_driver_s *c5471);
-static void c5471_reset(struct c5471_driver_s *c5471);
-static void c5471_macassign(struct c5471_driver_s *c5471);
+static void c5471_eimreset (struct c5471_driver_s *priv);
+static void c5471_eimconfig(struct c5471_driver_s *priv);
+static void c5471_reset(struct c5471_driver_s *priv);
+static void c5471_macassign(struct c5471_driver_s *priv);
/****************************************************************************
* Private Functions
@@ -411,13 +445,14 @@ static void c5471_macassign(struct c5471_driver_s *c5471);
****************************************************************************/
#ifdef CONFIG_C5471_NET_DUMPBUFFER
-static inline void c5471_dumpbuffer(const char *msg, const uint8_t *buffer, unsigned int nbytes)
+static inline void c5471_dumpbuffer(const char *msg, const uint8_t *buffer,
+ unsigned int nbytes)
{
- /* CONFIG_DEBUG, CONFIG_DEBUG_VERBOSE, and CONFIG_DEBUG_NET have to be
+ /* CONFIG_DEBUG_FEATURES, CONFIG_DEBUG_INFO, and CONFIG_DEBUG_NET have to be
* defined or the following does nothing.
*/
- nvdbgdumpbuffer(msg, buffer, nbytes);
+ ninfodumpbuffer(msg, buffer, nbytes);
}
#else
# define c5471_dumpbuffer(msg, buffer,nbytes)
@@ -737,22 +772,22 @@ static int c5471_phyinit (void)
phyid = (c5471_mdread(0, MD_PHY_MSB_REG) << 16) | c5471_mdread(0, MD_PHY_LSB_REG);
if (phyid != LU3X31_T64_PHYID)
{
- ndbg("Unrecognized PHY ID: %08x\n", phyid);
+ nerr("ERROR: Unrecognized PHY ID: %08x\n", phyid);
return ERROR;
}
/* Next, Set desired network rate, 10BaseT, 100BaseT, or auto. */
#ifdef CONFIG_C5471_AUTONEGOTIATION
- ndbg("Setting PHY Transceiver for Autonegotiation\n");
+ ninfo("Setting PHY Transceiver for Autonegotiation\n");
c5471_mdwrite(0, MD_PHY_CONTROL_REG, MODE_AUTONEG);
#endif
#ifdef CONFIG_C5471_BASET100
- ndbg("Setting PHY Transceiver for 100BaseT FullDuplex\n");
+ ninfo("Setting PHY Transceiver for 100BaseT FullDuplex\n");
c5471_mdwrite(0, MD_PHY_CONTROL_REG, MODE_100MBIT_FULLDUP);
#endif
#ifdef CONFIG_C5471_BASET10
- ndbg("Setting PHY Transceiver for 10BaseT FullDuplex\n");
+ ninfo("Setting PHY Transceiver for 10BaseT FullDuplex\n");
c5471_mdwrite(0, MD_PHY_CONTROL_REG, MODE_10MBIT_FULLDUP);
#endif
@@ -789,20 +824,20 @@ static int c5471_phyinit (void)
*
****************************************************************************/
-static inline void c5471_inctxcpu(struct c5471_driver_s *c5471)
+static inline void c5471_inctxcpu(struct c5471_driver_s *priv)
{
- if (EIM_TXDESC_WRAP_NEXT & getreg32(c5471->c_txcpudesc))
+ if (EIM_TXDESC_WRAP_NEXT & getreg32(priv->c_txcpudesc))
{
/* Loop back around to base of descriptor queue */
- c5471->c_txcpudesc = getreg32(EIM_CPU_TXBA) + EIM_RAM_START;
+ priv->c_txcpudesc = getreg32(EIM_CPU_TXBA) + EIM_RAM_START;
}
else
{
- c5471->c_txcpudesc += 2*sizeof(uint32_t);
+ priv->c_txcpudesc += 2*sizeof(uint32_t);
}
- nvdbg("TX CPU desc: %08x\n", c5471->c_txcpudesc);
+ ninfo("TX CPU desc: %08x\n", priv->c_txcpudesc);
}
/****************************************************************************
@@ -812,20 +847,20 @@ static inline void c5471_inctxcpu(struct c5471_driver_s *c5471)
*
****************************************************************************/
-static inline void c5471_incrxcpu(struct c5471_driver_s *c5471)
+static inline void c5471_incrxcpu(struct c5471_driver_s *priv)
{
- if (EIM_RXDESC_WRAP_NEXT & getreg32(c5471->c_rxcpudesc))
+ if (EIM_RXDESC_WRAP_NEXT & getreg32(priv->c_rxcpudesc))
{
/* Loop back around to base of descriptor queue */
- c5471->c_rxcpudesc = getreg32(EIM_CPU_RXBA) + EIM_RAM_START;
+ priv->c_rxcpudesc = getreg32(EIM_CPU_RXBA) + EIM_RAM_START;
}
else
{
- c5471->c_rxcpudesc += 2*sizeof(uint32_t);
+ priv->c_rxcpudesc += 2*sizeof(uint32_t);
}
- nvdbg("RX CPU desc: %08x\n", c5471->c_rxcpudesc);
+ ninfo("RX CPU desc: %08x\n", priv->c_rxcpudesc);
}
/****************************************************************************
@@ -836,7 +871,7 @@ static inline void c5471_incrxcpu(struct c5471_driver_s *c5471)
* handling or from watchdog based polling.
*
* Parameters:
- * c5471 - Reference to the driver state structure
+ * priv - Reference to the driver state structure
*
* Returned Value:
* OK on success; a negated errno on failure
@@ -845,9 +880,9 @@ static inline void c5471_incrxcpu(struct c5471_driver_s *c5471)
*
****************************************************************************/
-static int c5471_transmit(struct c5471_driver_s *c5471)
+static int c5471_transmit(struct c5471_driver_s *priv)
{
- struct net_driver_s *dev = &c5471->c_dev;
+ struct net_driver_s *dev = &priv->c_dev;
volatile uint16_t *packetmem;
uint16_t framelen;
bool bfirstframe;
@@ -856,12 +891,12 @@ static int c5471_transmit(struct c5471_driver_s *c5471)
unsigned int i;
unsigned int j;
- nbytes = (dev->d_len + 1) & ~1;
- j = 0;
- bfirstframe = true;
- c5471->c_lastdescstart = c5471->c_rxcpudesc;
+ nbytes = (dev->d_len + 1) & ~1;
+ j = 0;
+ bfirstframe = true;
+ priv->c_lastdescstart = priv->c_rxcpudesc;
- nvdbg("Packet size: %d RX CPU desc: %08x\n", nbytes, c5471->c_rxcpudesc);
+ ninfo("Packet size: %d RX CPU desc: %08x\n", nbytes, priv->c_rxcpudesc);
c5471_dumpbuffer("Transmit packet", dev->d_buf, dev->d_len);
while (nbytes)
@@ -869,7 +904,7 @@ static int c5471_transmit(struct c5471_driver_s *c5471)
/* Verify that the hardware is ready to send another packet */
/* Words #0 and #1 of descriptor */
- while (EIM_TXDESC_OWN_HOST & getreg32(c5471->c_rxcpudesc))
+ while (EIM_TXDESC_OWN_HOST & getreg32(priv->c_rxcpudesc))
{
/* Loop until the SWITCH lets go of the descriptor giving us access
* rights to submit our new ether frame to it.
@@ -878,18 +913,18 @@ static int c5471_transmit(struct c5471_driver_s *c5471)
if (bfirstframe)
{
- putreg32((getreg32(c5471->c_rxcpudesc) | EIM_RXDESC_FIF), c5471->c_rxcpudesc);
+ putreg32((getreg32(priv->c_rxcpudesc) | EIM_RXDESC_FIF), priv->c_rxcpudesc);
}
else
{
- putreg32((getreg32(c5471->c_rxcpudesc) & ~EIM_RXDESC_FIF), c5471->c_rxcpudesc);
+ putreg32((getreg32(priv->c_rxcpudesc) & ~EIM_RXDESC_FIF), priv->c_rxcpudesc);
}
- putreg32((getreg32(c5471->c_rxcpudesc) & ~EIM_RXDESC_PADCRC), c5471->c_rxcpudesc);
+ putreg32((getreg32(priv->c_rxcpudesc) & ~EIM_RXDESC_PADCRC), priv->c_rxcpudesc);
if (bfirstframe)
{
- putreg32((getreg32(c5471->c_rxcpudesc) | EIM_RXDESC_PADCRC), c5471->c_rxcpudesc);
+ putreg32((getreg32(priv->c_rxcpudesc) | EIM_RXDESC_PADCRC), priv->c_rxcpudesc);
}
if (nbytes >= EIM_PACKET_BYTES)
@@ -908,7 +943,7 @@ static int c5471_transmit(struct c5471_driver_s *c5471)
/* Words #2 and #3 of descriptor */
- packetmem = (uint16_t *)getreg32(c5471->c_rxcpudesc + sizeof(uint32_t));
+ packetmem = (uint16_t *)getreg32(priv->c_rxcpudesc + sizeof(uint32_t));
for (i = 0; i < nshorts; i++, j++)
{
/* 16-bits at a time. */
@@ -916,43 +951,45 @@ static int c5471_transmit(struct c5471_driver_s *c5471)
packetmem[i] = htons(((uint16_t *)dev->d_buf)[j]);
}
- putreg32(((getreg32(c5471->c_rxcpudesc) & ~EIM_RXDESC_BYTEMASK) | framelen), c5471->c_rxcpudesc);
+ putreg32(((getreg32(priv->c_rxcpudesc) & ~EIM_RXDESC_BYTEMASK) | framelen),
+ priv->c_rxcpudesc);
nbytes -= framelen;
- nvdbg("Wrote framelen: %d nbytes: %d nshorts: %d\n", framelen, nbytes, nshorts);
+ ninfo("Wrote framelen: %d nbytes: %d nshorts: %d\n", framelen, nbytes, nshorts);
if (0 == nbytes)
{
- putreg32((getreg32(c5471->c_rxcpudesc) | EIM_RXDESC_LIF), c5471->c_rxcpudesc);
+ putreg32((getreg32(priv->c_rxcpudesc) | EIM_RXDESC_LIF), priv->c_rxcpudesc);
}
else
{
- putreg32((getreg32(c5471->c_rxcpudesc) & ~EIM_RXDESC_LIF), c5471->c_rxcpudesc);
+ putreg32((getreg32(priv->c_rxcpudesc) & ~EIM_RXDESC_LIF), priv->c_rxcpudesc);
}
/* We're done with that descriptor; give access rights back to h/w */
- putreg32((getreg32(c5471->c_rxcpudesc) | EIM_RXDESC_OWN_HOST), c5471->c_rxcpudesc);
+ putreg32((getreg32(priv->c_rxcpudesc) | EIM_RXDESC_OWN_HOST), priv->c_rxcpudesc);
/* Next, tell Ether Module that those submitted bytes are ready for the wire */
putreg32(0x00000001, EIM_CPU_RXREADY);
- c5471->c_lastdescend = c5471->c_rxcpudesc;
+ priv->c_lastdescend = priv->c_rxcpudesc;
/* Advance to the next free descriptor */
- c5471_incrxcpu(c5471);
+ c5471_incrxcpu(priv);
bfirstframe = false;
}
/* Packet transferred .. Update statistics */
#ifdef CONFIG_C5471_NET_STATS
- c5471->c_txpackets++;
+ priv->c_txpackets++;
#endif
/* Setup the TX timeout watchdog (perhaps restarting the timer) */
- (void)wd_start(c5471->c_txtimeout, C5471_TXTIMEOUT, c5471_txtimeout, 1, (uint32_t)c5471);
+ (void)wd_start(priv->c_txtimeout, C5471_TXTIMEOUT,
+ c5471_txtimeout_expiry, 1, (wdparm_t)priv);
return OK;
}
@@ -979,13 +1016,13 @@ static int c5471_transmit(struct c5471_driver_s *c5471)
static int c5471_txpoll(struct net_driver_s *dev)
{
- struct c5471_driver_s *c5471 = (struct c5471_driver_s *)dev->d_private;
+ struct c5471_driver_s *priv = (struct c5471_driver_s *)dev->d_private;
/* If the polling resulted in data that should be sent out on the network,
* the field d_len is set to a value > 0.
*/
- if (c5471->c_dev.d_len > 0)
+ if (priv->c_dev.d_len > 0)
{
/* Look up the destination MAC address and add it to the Ethernet
* header.
@@ -993,10 +1030,10 @@ static int c5471_txpoll(struct net_driver_s *dev)
#ifdef CONFIG_NET_IPv4
#ifdef CONFIG_NET_IPv6
- if (IFF_IS_IPv4(c5471->c_dev.d_flags))
+ if (IFF_IS_IPv4(priv->c_dev.d_flags))
#endif
{
- arp_out(&c5471->c_dev);
+ arp_out(&priv->c_dev);
}
#endif /* CONFIG_NET_IPv4 */
@@ -1005,19 +1042,19 @@ static int c5471_txpoll(struct net_driver_s *dev)
else
#endif
{
- neighbor_out(&c5471->c_dev);
+ neighbor_out(&priv->c_dev);
}
#endif /* CONFIG_NET_IPv6 */
/* Send the packet */
- c5471_transmit(c5471);
+ c5471_transmit(priv);
/* Check if the ESM has let go of the RX descriptor giving us access
* rights to submit another Ethernet frame.
*/
- if ((EIM_TXDESC_OWN_HOST & getreg32(c5471->c_rxcpudesc)) != 0)
+ if ((EIM_TXDESC_OWN_HOST & getreg32(priv->c_rxcpudesc)) != 0)
{
/* No, then return non-zero to terminate the poll */
@@ -1039,7 +1076,7 @@ static int c5471_txpoll(struct net_driver_s *dev)
* An interrupt was received indicating that the last RX packet(s) is done
*
* Parameters:
- * c5471 - Reference to the driver state structure
+ * priv - Reference to the driver state structure
*
* Returned Value:
* None
@@ -1049,9 +1086,9 @@ static int c5471_txpoll(struct net_driver_s *dev)
****************************************************************************/
#ifdef CONFIG_C5471_NET_STATS
-static void c5471_rxstatus(struct c5471_driver_s *c5471)
+static void c5471_rxstatus(struct c5471_driver_s *priv)
{
- uint32_t desc = c5471->c_txcpudesc;
+ uint32_t desc = priv->c_txcpudesc;
uint32_t rxstatus;
/* Walk that last packet we just received to collect xmit status bits. */
@@ -1091,44 +1128,44 @@ static void c5471_rxstatus(struct c5471_driver_s *c5471)
{
if ((rxstatus & EIM_TXDESC_RETRYERROR) != 0)
{
- c5471->c_rxretries++;
- nvdbg("c_rxretries: %d\n", c5471->c_rxretries);
+ priv->c_rxretries++;
+ ninfo("c_rxretries: %d\n", priv->c_rxretries);
}
if ((rxstatus & EIM_TXDESC_HEARTBEAT) != 0)
{
- c5471->c_rxheartbeat++;
- nvdbg("c_rxheartbeat: %d\n", c5471->c_rxheartbeat);
+ priv->c_rxheartbeat++;
+ ninfo("c_rxheartbeat: %d\n", priv->c_rxheartbeat);
}
if ((rxstatus & EIM_TXDESC_LCOLLISON) != 0)
{
- c5471->c_rxlcollision++;
- nvdbg("c_rxlcollision: %d\n", c5471->c_rxlcollision);
+ priv->c_rxlcollision++;
+ ninfo("c_rxlcollision: %d\n", priv->c_rxlcollision);
}
if ((rxstatus & EIM_TXDESC_COLLISION) != 0)
{
- c5471->c_rxcollision++;
- nvdbg("c_rxcollision: %d\n", c5471->c_rxcollision);
+ priv->c_rxcollision++;
+ ninfo("c_rxcollision: %d\n", priv->c_rxcollision);
}
if ((rxstatus & EIM_TXDESC_CRCERROR) != 0)
{
- c5471->c_rxcrc++;
- nvdbg("c_rxcrc: %d\n", c5471->c_rxcrc);
+ priv->c_rxcrc++;
+ ninfo("c_rxcrc: %d\n", priv->c_rxcrc);
}
if ((rxstatus & EIM_TXDESC_UNDERRUN) != 0)
{
- c5471->c_rxunderrun++;
- nvdbg("c_rxunderrun: %d\n", c5471->c_rxunderrun);
+ priv->c_rxunderrun++;
+ ninfo("c_rxunderrun: %d\n", priv->c_rxunderrun);
}
if ((rxstatus & EIM_TXDESC_LOC) != 0)
{
- c5471->c_rxloc++;
- nvdbg("c_rxloc: %d\n", c5471->c_rxloc);
+ priv->c_rxloc++;
+ ninfo("c_rxloc: %d\n", priv->c_rxloc);
}
}
}
@@ -1141,7 +1178,7 @@ static void c5471_rxstatus(struct c5471_driver_s *c5471)
* An interrupt was received indicating the availability of a new RX packet
*
* Parameters:
- * c5471 - Reference to the driver state structure
+ * priv - Reference to the driver state structure
*
* Returned Value:
* None
@@ -1150,9 +1187,9 @@ static void c5471_rxstatus(struct c5471_driver_s *c5471)
*
****************************************************************************/
-static void c5471_receive(struct c5471_driver_s *c5471)
+static void c5471_receive(struct c5471_driver_s *priv)
{
- struct net_driver_s *dev = &c5471->c_dev;
+ struct net_driver_s *dev = &priv->c_dev;
uint16_t *packetmem;
bool bmore = true;
int packetlen = 0;
@@ -1166,12 +1203,12 @@ static void c5471_receive(struct c5471_driver_s *c5471)
* the EIM for additional packets that might be received later from the network.
*/
- nvdbg("Reading TX CPU desc: %08x\n", c5471->c_txcpudesc);
+ ninfo("Reading TX CPU desc: %08x\n", priv->c_txcpudesc);
while (bmore)
{
/* Words #0 and #1 of descriptor */
- if (EIM_TXDESC_OWN_HOST & getreg32(c5471->c_txcpudesc))
+ if (EIM_TXDESC_OWN_HOST & getreg32(priv->c_txcpudesc))
{
/* No further packets to receive. */
@@ -1182,7 +1219,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
* and update the accumulated packet size
*/
- framelen = (getreg32(c5471->c_txcpudesc) & EIM_TXDESC_BYTEMASK);
+ framelen = (getreg32(priv->c_txcpudesc) & EIM_TXDESC_BYTEMASK);
packetlen += framelen;
/* Check if the received packet will fit within the network packet buffer */
@@ -1191,17 +1228,17 @@ static void c5471_receive(struct c5471_driver_s *c5471)
{
/* Get the packet memory from words #2 and #3 of descriptor */
- packetmem = (uint16_t *)getreg32(c5471->c_txcpudesc + sizeof(uint32_t));
+ packetmem = (uint16_t *)getreg32(priv->c_txcpudesc + sizeof(uint32_t));
/* Divide by 2 with round up to get the number of 16-bit words. */
nshorts = (framelen + 1) >> 1;
- nvdbg("Reading framelen: %d packetlen: %d nshorts: %d packetmen: %p\n",
+ ninfo("Reading framelen: %d packetlen: %d nshorts: %d packetmen: %p\n",
framelen, packetlen, nshorts, packetmem);
for (i = 0 ; i < nshorts; i++, j++)
{
- /* Copy the data data from the hardware to c5471->c_dev.d_buf 16-bits at
+ /* Copy the data data from the hardware to priv->c_dev.d_buf 16-bits at
* a time.
*/
@@ -1210,10 +1247,10 @@ static void c5471_receive(struct c5471_driver_s *c5471)
}
else
{
- nvdbg("Discarding framelen: %d packetlen\n", framelen, packetlen);
+ ninfo("Discarding framelen: %d packetlen\n", framelen, packetlen);
}
- if (getreg32(c5471->c_txcpudesc) & EIM_TXDESC_LIF)
+ if (getreg32(priv->c_txcpudesc) & EIM_TXDESC_LIF)
{
bmore = false;
}
@@ -1222,16 +1259,16 @@ static void c5471_receive(struct c5471_driver_s *c5471)
* the settings of a select few. Can leave descriptor words 2/3 alone.
*/
- putreg32((getreg32(c5471->c_txcpudesc) & (EIM_TXDESC_WRAP_NEXT | EIM_TXDESC_INTRE)),
- c5471->c_txcpudesc);
+ putreg32((getreg32(priv->c_txcpudesc) & (EIM_TXDESC_WRAP_NEXT | EIM_TXDESC_INTRE)),
+ priv->c_txcpudesc);
/* Next, Give ownership of now emptied descriptor back to the Ether Module's SWITCH */
- putreg32((getreg32(c5471->c_txcpudesc) | EIM_TXDESC_OWN_HOST), c5471->c_txcpudesc);
+ putreg32((getreg32(priv->c_txcpudesc) | EIM_TXDESC_OWN_HOST), priv->c_txcpudesc);
/* Advance to the next data buffer */
- c5471_inctxcpu(c5471);
+ c5471_inctxcpu(priv);
}
/* Adjust the packet length to remove the CRC bytes that the network doesn't care about. */
@@ -1241,7 +1278,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
#ifdef CONFIG_C5471_NET_STATS
/* Increment the count of received packets */
- c5471->c_rxpackets++;
+ priv->c_rxpackets++;
#endif
/* If we successfully transferred the data into the network buffer, then pass it on
@@ -1250,10 +1287,10 @@ static void c5471_receive(struct c5471_driver_s *c5471)
if (packetlen > 0 && packetlen < CONFIG_NET_ETH_MTU)
{
- /* Set amount of data in c5471->c_dev.d_len. */
+ /* Set amount of data in priv->c_dev.d_len. */
dev->d_len = packetlen;
- nvdbg("Received packet, packetlen: %d type: %02x\n", packetlen, ntohs(BUF->type));
+ ninfo("Received packet, packetlen: %d type: %02x\n", packetlen, ntohs(BUF->type));
c5471_dumpbuffer("Received packet", dev->d_buf, dev->d_len);
#ifdef CONFIG_NET_PKT
@@ -1267,7 +1304,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
#ifdef CONFIG_NET_IPv4
if (BUF->type == HTONS(ETHTYPE_IP))
{
- nllvdbg("IPv4 frame\n");
+ ninfo("IPv4 frame\n");
/* Handle ARP on input then give the IPv4 packet to the network
* layer
@@ -1283,7 +1320,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
*/
if (dev->d_len > 0 &&
- (EIM_TXDESC_OWN_HOST & getreg32(c5471->c_rxcpudesc)) == 0)
+ (EIM_TXDESC_OWN_HOST & getreg32(priv->c_rxcpudesc)) == 0)
{
/* Update the Ethernet header with the correct MAC address */
@@ -1302,7 +1339,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
/* And send the packet */
- c5471_transmit(c5471);
+ c5471_transmit(priv);
}
}
else
@@ -1310,7 +1347,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
#ifdef CONFIG_NET_IPv6
if (BUF->type == HTONS(ETHTYPE_IP6))
{
- nllvdbg("Iv6 frame\n");
+ ninfo("Iv6 frame\n");
/* Give the IPv6 packet to the network layer */
@@ -1323,7 +1360,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
*/
if (dev->d_len > 0 &&
- (EIM_TXDESC_OWN_HOST & getreg32(c5471->c_rxcpudesc)) == 0)
+ (EIM_TXDESC_OWN_HOST & getreg32(priv->c_rxcpudesc)) == 0)
{
/* Update the Ethernet header with the correct MAC address */
@@ -1342,7 +1379,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
/* And send the packet */
- c5471_transmit(c5471);
+ c5471_transmit(priv);
}
}
else
@@ -1359,9 +1396,9 @@ static void c5471_receive(struct c5471_driver_s *c5471)
*/
if (dev->d_len > 0 &&
- (EIM_TXDESC_OWN_HOST & getreg32(c5471->c_rxcpudesc)) == 0)
+ (EIM_TXDESC_OWN_HOST & getreg32(priv->c_rxcpudesc)) == 0)
{
- c5471_transmit(c5471);
+ c5471_transmit(priv);
}
}
#endif
@@ -1371,8 +1408,8 @@ static void c5471_receive(struct c5471_driver_s *c5471)
{
/* Increment the count of dropped packets */
- ndbg("Too big! packetlen: %d\n", packetlen);
- c5471->c_rxdropped++;
+ nwarn("WARNING: Too big! packetlen: %d\n", packetlen);
+ priv->c_rxdropped++;
}
#endif
}
@@ -1384,7 +1421,7 @@ static void c5471_receive(struct c5471_driver_s *c5471)
* An interrupt was received indicating that the last TX packet(s) is done
*
* Parameters:
- * c5471 - Reference to the driver state structure
+ * priv - Reference to the driver state structure
*
* Returned Value:
* None
@@ -1394,27 +1431,27 @@ static void c5471_receive(struct c5471_driver_s *c5471)
****************************************************************************/
#ifdef CONFIG_C5471_NET_STATS
-static void c5471_txstatus(struct c5471_driver_s *c5471)
+static void c5471_txstatus(struct c5471_driver_s *priv)
{
- uint32_t desc = c5471->c_lastdescstart;
+ uint32_t desc = priv->c_lastdescstart;
uint32_t txstatus;
/* Walk that last packet we just sent to collect xmit status bits. */
txstatus = 0;
- if (c5471->c_lastdescstart && c5471->c_lastdescend)
+ if (priv->c_lastdescstart && priv->c_lastdescend)
{
for (; ; )
{
txstatus |= (getreg32(desc) & EIM_RXDESC_STATUSMASK);
- if (desc == c5471->c_lastdescend)
+ if (desc == priv->c_lastdescend)
{
break;
}
/* This packet is made up of several descriptors, find next one in chain. */
- if (EIM_RXDESC_WRAP_NEXT & getreg32(c5471->c_rxcpudesc))
+ if (EIM_RXDESC_WRAP_NEXT & getreg32(priv->c_rxcpudesc))
{
/* Loop back around to base of descriptor queue. */
@@ -1431,44 +1468,44 @@ static void c5471_txstatus(struct c5471_driver_s *c5471)
{
if ((txstatus & EIM_RXDESC_MISS) != 0)
{
- c5471->c_txmiss++;
- nvdbg("c_txmiss: %d\n", c5471->c_txmiss);
+ priv->c_txmiss++;
+ ninfo("c_txmiss: %d\n", priv->c_txmiss);
}
if ((txstatus & EIM_RXDESC_VLAN) != 0)
{
- c5471->c_txvlan++;
- nvdbg("c_txvlan: %d\n", c5471->c_txvlan);
+ priv->c_txvlan++;
+ ninfo("c_txvlan: %d\n", priv->c_txvlan);
}
if ((txstatus & EIM_RXDESC_LFRAME) != 0)
{
- c5471->c_txlframe++;
- nvdbg("c_txlframe: %d\n", c5471->c_txlframe);
+ priv->c_txlframe++;
+ ninfo("c_txlframe: %d\n", priv->c_txlframe);
}
if ((txstatus & EIM_RXDESC_SFRAME) != 0)
{
- c5471->c_txsframe++;
- nvdbg("c_txsframe: %d\n", c5471->c_txsframe);
+ priv->c_txsframe++;
+ ninfo("c_txsframe: %d\n", priv->c_txsframe);
}
if ((txstatus & EIM_RXDESC_CRCERROR) != 0)
{
- c5471->c_txcrc++;
- nvdbg("c_txcrc: %d\n", c5471->c_txcrc);
+ priv->c_txcrc++;
+ ninfo("c_txcrc: %d\n", priv->c_txcrc);
}
if ((txstatus & EIM_RXDESC_OVERRUN) != 0)
{
- c5471->c_txoverrun++;
- nvdbg("c_txoverrun: %d\n", c5471->c_txoverrun);
+ priv->c_txoverrun++;
+ ninfo("c_txoverrun: %d\n", priv->c_txoverrun);
}
if ((txstatus & EIM_RXDESC_OVERRUN) != 0)
{
- c5471->c_txalign++;
- nvdbg("c_txalign: %d\n", c5471->c_txalign);
+ priv->c_txalign++;
+ ninfo("c_txalign: %d\n", priv->c_txalign);
}
}
}
@@ -1481,7 +1518,7 @@ static void c5471_txstatus(struct c5471_driver_s *c5471)
* An interrupt was received indicating that the last TX packet(s) is done
*
* Parameters:
- * c5471 - Reference to the driver state structure
+ * priv - Reference to the driver state structure
*
* Returned Value:
* None
@@ -1490,50 +1527,50 @@ static void c5471_txstatus(struct c5471_driver_s *c5471)
*
****************************************************************************/
-static void c5471_txdone(struct c5471_driver_s *c5471)
+static void c5471_txdone(struct c5471_driver_s *priv)
{
/* If no further xmits are pending, then cancel the TX timeout */
- wd_cancel(c5471->c_txtimeout);
+ wd_cancel(priv->c_txtimeout);
/* Then poll the network for new XMIT data */
- (void)devif_poll(&c5471->c_dev, c5471_txpoll);
+ (void)devif_poll(&priv->c_dev, c5471_txpoll);
}
/****************************************************************************
- * Function: c5471_interrupt
+ * Function: c5471_interrupt_work
*
* Description:
- * Hardware interrupt handler
+ * Perform interrupt related work from the worker thread
*
* Parameters:
- * irq - Number of the IRQ that generated the interrupt
- * context - Interrupt register state save info (architecture-specific)
+ * arg - The argument passed when work_queue() was called.
*
* Returned Value:
* OK on success
*
* Assumptions:
+ * The network is locked.
*
****************************************************************************/
-static int c5471_interrupt(int irq, FAR void *context)
+static void c5471_interrupt_work(FAR void *arg)
{
-#if CONFIG_C5471_NET_NINTERFACES == 1
- register struct c5471_driver_s *c5471 = &g_c5471[0];
-#else
-# error "Additional logic needed to support multiple interfaces"
-#endif
+ FAR struct c5471_driver_s *priv = (FAR struct c5471_driver_s *)arg;
+
+ /* Process pending Ethernet interrupts */
+
+ net_lock();
/* Get and clear interrupt status bits */
- c5471->c_eimstatus = getreg32(EIM_STATUS);
+ priv->c_eimstatus = getreg32(EIM_STATUS);
/* Handle interrupts according to status bit settings */
/* Check if we received an incoming packet, if so, call c5471_receive() */
- if ((EIM_STATUS_CPU_TX & c5471->c_eimstatus) != 0)
+ if ((EIM_STATUS_CPU_TX & priv->c_eimstatus) != 0)
{
/* An incoming packet has been received by the EIM from the network and
* the interrupt associated with EIM's CPU TX queue has been asserted. It
@@ -1545,17 +1582,17 @@ static int c5471_interrupt(int irq, FAR void *context)
#ifdef CONFIG_C5471_NET_STATS
/* Check for RX errors */
- c5471_rxstatus(c5471);
+ c5471_rxstatus(priv);
#endif
/* Process the received packet */
- c5471_receive(c5471);
+ c5471_receive(priv);
}
/* Check is a packet transmission just completed. If so, call c5471_txdone */
- if ((EIM_STATUS_CPU_RX & c5471->c_eimstatus) != 0)
+ if ((EIM_STATUS_CPU_RX & priv->c_eimstatus) != 0)
{
/* An outgoing packet has been processed by the EIM and the interrupt
* associated with EIM's CPU RX que has been asserted. It is the EIM's
@@ -1566,65 +1603,116 @@ static int c5471_interrupt(int irq, FAR void *context)
#ifdef CONFIG_C5471_NET_STATS
/* Check for TX errors */
- c5471_txstatus(c5471);
+ c5471_txstatus(priv);
#endif
/* Handle the transmission done event */
- c5471_txdone(c5471);
+ c5471_txdone(priv);
}
- /* Enable Ethernet interrupts (perhaps excluding the TX done interrupt if
- * there are no pending transmissions.
+ net_unlock();
+
+ /* Re-enable Ethernet interrupts */
+
+ up_enable_irq(C5471_IRQ_ETHER);
+}
+
+/****************************************************************************
+ * Function: c5471_interrupt
+ *
+ * Description:
+ * Hardware interrupt handler
+ *
+ * Parameters:
+ * irq - Number of the IRQ that generated the interrupt
+ * context - Interrupt register state save info (architecture-specific)
+ *
+ * Returned Value:
+ * OK on success
+ *
+ * Assumptions:
+ *
+ ****************************************************************************/
+
+static int c5471_interrupt(int irq, FAR void *context, FAR void *arg)
+{
+#if CONFIG_C5471_NET_NINTERFACES == 1
+ register struct c5471_driver_s *priv = &g_c5471[0];
+#else
+# error "Additional logic needed to support multiple interfaces"
+#endif
+
+ /* Disable further Ethernet interrupts. Because Ethernet interrupts are
+ * also disabled if the TX timeout event occurs, there can be no race
+ * condition here.
*/
+ up_disable_irq(C5471_IRQ_ETHER);
+
+ /* TODO: Determine if a TX transfer just completed */
+
+ {
+ /* If a TX transfer just completed, then cancel the TX timeout so
+ * there will be no race condition between any subsequent timeout
+ * expiration and the deferred interrupt processing.
+ */
+
+ wd_cancel(priv->c_txtimeout);
+ }
+
+ /* Schedule to perform the interrupt processing on the worker thread. */
+
+ work_queue(ETHWORK, &priv->c_irqwork, c5471_interrupt_work, priv, 0);
return OK;
}
/****************************************************************************
- * Function: c5471_txtimeout
+ * Function: c5471_txtimeout_work
*
* Description:
- * Our TX watchdog timed out. Called from the timer interrupt handler.
- * The last TX never completed. Reset the hardware and start again.
+ * Perform TX timeout related work from the worker thread
*
* Parameters:
- * argc - The number of available arguments
- * arg - The first argument
+ * arg - The argument passed when work_queue() as called.
*
* Returned Value:
- * None
+ * OK on success
*
* Assumptions:
+ * The network is locked.
*
****************************************************************************/
-static void c5471_txtimeout(int argc, uint32_t arg, ...)
+static void c5471_txtimeout_work(FAR void *arg)
{
- struct c5471_driver_s *c5471 = (struct c5471_driver_s *)arg;
+ FAR struct c5471_driver_s *priv = (FAR struct c5471_driver_s *)arg;
/* Increment statistics */
+ net_lock();
#ifdef CONFIG_C5471_NET_STATS
- c5471->c_txtimeouts++;
- nvdbg("c_txtimeouts: %d\n", c5471->c_txtimeouts);
+ priv->c_txtimeouts++;
+ ninfo("c_txtimeouts: %d\n", priv->c_txtimeouts);
#endif
/* Then try to restart the hardware */
- c5471_ifdown(&c5471->c_dev);
- c5471_ifup(&c5471->c_dev);
+ c5471_ifdown(&priv->c_dev);
+ c5471_ifup(&priv->c_dev);
/* Then poll the network for new XMIT data */
- (void)devif_poll(&c5471->c_dev, c5471_txpoll);
+ (void)devif_poll(&priv->c_dev, c5471_txpoll);
+ net_unlock();
}
/****************************************************************************
- * Function: c5471_polltimer
+ * Function: c5471_txtimeout_expiry
*
* Description:
- * Periodic timer handler. Called from the timer interrupt handler.
+ * Our TX watchdog timed out. Called from the timer interrupt handler.
+ * The last TX never completed. Reset the hardware and start again.
*
* Parameters:
* argc - The number of available arguments
@@ -1634,27 +1722,93 @@ static void c5471_txtimeout(int argc, uint32_t arg, ...)
* None
*
* Assumptions:
+ * Global interrupts are disabled by the watchdog logic.
+ *
+ ****************************************************************************/
+
+static void c5471_txtimeout_expiry(int argc, wdparm_t arg, ...)
+{
+ struct c5471_driver_s *priv = (struct c5471_driver_s *)arg;
+
+ /* Disable further Ethernet interrupts. This will prevent some race
+ * conditions with interrupt work. There is still a potential race
+ * condition with interrupt work that is already queued and in progress.
+ */
+
+ up_disable_irq(C5471_IRQ_ETHER);
+
+ /* Schedule to perform the TX timeout processing on the worker thread,
+ * canceling any pending IRQ work.
+ */
+
+ work_queue(ETHWORK, &priv->c_irqwork, c5471_txtimeout_work, priv, 0);
+}
+
+/****************************************************************************
+ * Function: c5471_poll_work
+ *
+ * Description:
+ * Perform periodic polling from the worker thread
+ *
+ * Parameters:
+ * arg - The argument passed when work_queue() as called.
+ *
+ * Returned Value:
+ * OK on success
+ *
+ * Assumptions:
+ * The network is locked.
*
****************************************************************************/
-static void c5471_polltimer(int argc, uint32_t arg, ...)
+static void c5471_poll_work(FAR void *arg)
{
- struct c5471_driver_s *c5471 = (struct c5471_driver_s *)arg;
+ FAR struct c5471_driver_s *priv = (FAR struct c5471_driver_s *)arg;
/* Check if the ESM has let go of the RX descriptor giving us access rights
* to submit another Ethernet frame.
*/
- if ((EIM_TXDESC_OWN_HOST & getreg32(c5471->c_rxcpudesc)) == 0)
+ net_lock();
+ if ((EIM_TXDESC_OWN_HOST & getreg32(priv->c_rxcpudesc)) == 0)
{
/* If so, update TCP timing states and poll the network for new XMIT data */
- (void)devif_timer(&c5471->c_dev, c5471_txpoll);
+ (void)devif_timer(&priv->c_dev, c5471_txpoll);
}
/* Setup the watchdog poll timer again */
- (void)wd_start(c5471->c_txpoll, C5471_WDDELAY, c5471_polltimer, 1, arg);
+ (void)wd_start(priv->c_txpoll, C5471_WDDELAY, c5471_poll_expiry, 1,
+ (wdparm_t)priv);
+ net_unlock();
+}
+
+/****************************************************************************
+ * Function: c5471_poll_expiry
+ *
+ * Description:
+ * Periodic timer handler. Called from the timer interrupt handler.
+ *
+ * Parameters:
+ * argc - The number of available arguments
+ * arg - The first argument
+ *
+ * Returned Value:
+ * None
+ *
+ * Assumptions:
+ * Global interrupts are disabled by the watchdog logic.
+ *
+ ****************************************************************************/
+
+static void c5471_poll_expiry(int argc, wdparm_t arg, ...)
+{
+ struct c5471_driver_s *priv = (struct c5471_driver_s *)arg;
+
+ /* Schedule to perform the interrupt processing on the worker thread. */
+
+ work_queue(ETHWORK, &priv->c_pollwork, c5471_poll_work, priv, 0);
}
/****************************************************************************
@@ -1677,20 +1831,20 @@ static void c5471_polltimer(int argc, uint32_t arg, ...)
static int c5471_ifup(struct net_driver_s *dev)
{
- struct c5471_driver_s *c5471 = (struct c5471_driver_s *)dev->d_private;
+ struct c5471_driver_s *priv = (struct c5471_driver_s *)dev->d_private;
volatile uint32_t clearbits;
- ndbg("Bringing up: %d.%d.%d.%d\n",
- dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
- (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
+ ninfo("Bringing up: %d.%d.%d.%d\n",
+ dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff,
+ (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24);
/* Initilize Ethernet interface */
- c5471_reset(c5471);
+ c5471_reset(priv);
/* Assign the MAC to the device */
- c5471_macassign(c5471);
+ c5471_macassign(priv);
/* Clear pending interrupts by reading the EIM status register */
@@ -1712,11 +1866,12 @@ static int c5471_ifup(struct net_driver_s *dev)
/* Set and activate a timer process */
- (void)wd_start(c5471->c_txpoll, C5471_WDDELAY, c5471_polltimer, 1, (uint32_t)c5471);
+ (void)wd_start(priv->c_txpoll, C5471_WDDELAY, c5471_poll_expiry,
+ 1, (wdparm_t)priv);
/* Enable the Ethernet interrupt */
- c5471->c_bifup = true;
+ priv->c_bifup = true;
up_enable_irq(C5471_IRQ_ETHER);
return OK;
}
@@ -1739,10 +1894,10 @@ static int c5471_ifup(struct net_driver_s *dev)
static int c5471_ifdown(struct net_driver_s *dev)
{
- struct c5471_driver_s *c5471 = (struct c5471_driver_s *)dev->d_private;
+ struct c5471_driver_s *priv = (struct c5471_driver_s *)dev->d_private;
irqstate_t flags;
- ndbg("Stopping\n");
+ ninfo("Stopping\n");
/* Disable the Ethernet interrupt */
@@ -1764,60 +1919,94 @@ static int c5471_ifdown(struct net_driver_s *dev)
/* Cancel the TX poll timer and TX timeout timers */
- wd_cancel(c5471->c_txpoll);
- wd_cancel(c5471->c_txtimeout);
+ wd_cancel(priv->c_txpoll);
+ wd_cancel(priv->c_txtimeout);
/* Reset the device */
- c5471->c_bifup = false;
+ priv->c_bifup = false;
leave_critical_section(flags);
return OK;
}
/****************************************************************************
- * Function: c5471_txavail
+ * Function: c5471_txavail_work
*
* Description:
- * Driver callback invoked when new TX data is available. This is a
- * stimulus perform an out-of-cycle poll and, thereby, reduce the TX
- * latency.
+ * Perform an out-of-cycle poll on the worker thread.
*
* Parameters:
- * dev - Reference to the NuttX driver state structure
+ * arg - Reference to the NuttX driver state structure (cast to void*)
*
* Returned Value:
* None
*
* Assumptions:
- * Called in normal user mode
+ * Called on the higher priority worker thread.
*
****************************************************************************/
-static int c5471_txavail(struct net_driver_s *dev)
+static void c5471_txavail_work(FAR void *arg)
{
- struct c5471_driver_s *c5471 = (struct c5471_driver_s *)dev->d_private;
- irqstate_t flags;
+ FAR struct c5471_driver_s *priv = (FAR struct c5471_driver_s *)arg;
- ndbg("Polling\n");
- flags = enter_critical_section();
+ ninfo("Polling\n");
/* Ignore the notification if the interface is not yet up */
- if (c5471->c_bifup)
+ net_lock();
+ if (priv->c_bifup)
{
/* Check if the ESM has let go of the RX descriptor giving us access
* rights to submit another Ethernet frame.
*/
- if ((EIM_TXDESC_OWN_HOST & getreg32(c5471->c_rxcpudesc)) == 0)
+ if ((EIM_TXDESC_OWN_HOST & getreg32(priv->c_rxcpudesc)) == 0)
{
/* If so, then poll the network for new XMIT data */
- (void)devif_poll(&c5471->c_dev, c5471_txpoll);
+ (void)devif_poll(&priv->c_dev, c5471_txpoll);
}
}
- leave_critical_section(flags);
+ net_unlock();
+}
+
+/****************************************************************************
+ * Function: c5471_txavail
+ *
+ * Description:
+ * Driver callback invoked when new TX data is available. This is a
+ * stimulus perform an out-of-cycle poll and, thereby, reduce the TX
+ * latency.
+ *
+ * Parameters:
+ * dev - Reference to the NuttX driver state structure
+ *
+ * Returned Value:
+ * None
+ *
+ * Assumptions:
+ * Called in normal user mode
+ *
+ ****************************************************************************/
+
+static int c5471_txavail(FAR struct net_driver_s *dev)
+{
+ struct c5471_driver_s *priv = (struct c5471_driver_s *)dev->d_private;
+
+ /* Is our single work structure available? It may not be if there are
+ * pending interrupt actions and we will have to ignore the Tx
+ * availability action.
+ */
+
+ if (work_available(&priv->c_pollwork))
+ {
+ /* Schedule to serialize the poll on the worker thread. */
+
+ work_queue(ETHWORK, &priv->c_pollwork, c5471_txavail_work, priv, 0);
+ }
+
return OK;
}
@@ -1895,7 +2084,7 @@ static int c5471_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac)
*
****************************************************************************/
-static void c5471_eimreset (struct c5471_driver_s *c5471)
+static void c5471_eimreset (struct c5471_driver_s *priv)
{
/* Stop the EIM module clock */
@@ -1925,8 +2114,8 @@ static void c5471_eimreset (struct c5471_driver_s *c5471)
/* All EIM register should now be in there power-up default states */
- c5471->c_lastdescstart = 0;
- c5471->c_lastdescend = 0;
+ priv->c_lastdescstart = 0;
+ priv->c_lastdescend = 0;
}
/****************************************************************************
@@ -1939,7 +2128,7 @@ static void c5471_eimreset (struct c5471_driver_s *c5471)
*
****************************************************************************/
-static void c5471_eimconfig(struct c5471_driver_s *c5471)
+static void c5471_eimconfig(struct c5471_driver_s *priv)
{
volatile uint32_t pbuf;
volatile uint32_t desc;
@@ -1951,7 +2140,7 @@ static void c5471_eimconfig(struct c5471_driver_s *c5471)
/* TX ENET 0 */
- ndbg("TX ENET0 desc: %08x pbuf: %08x\n", desc, pbuf);
+ ninfo("TX ENET0 desc: %08x pbuf: %08x\n", desc, pbuf);
putreg32((desc & 0x0000ffff), ENET0_TDBA); /* 16-bit offset address */
for (i = NUM_DESC_TX-1; i >= 0; i--)
{
@@ -1978,7 +2167,7 @@ static void c5471_eimconfig(struct c5471_driver_s *c5471)
/* RX ENET 0 */
- ndbg("RX ENET0 desc: %08x pbuf: %08x\n", desc, pbuf);
+ ninfo("RX ENET0 desc: %08x pbuf: %08x\n", desc, pbuf);
putreg32((desc & 0x0000ffff), ENET0_RDBA); /* 16-bit offset address */
for (i = NUM_DESC_RX-1; i >= 0; i--)
{
@@ -2005,8 +2194,8 @@ static void c5471_eimconfig(struct c5471_driver_s *c5471)
/* TX CPU */
- ndbg("TX CPU desc: %08x pbuf: %08x\n", desc, pbuf);
- c5471->c_txcpudesc = desc;
+ ninfo("TX CPU desc: %08x pbuf: %08x\n", desc, pbuf);
+ priv->c_txcpudesc = desc;
putreg32((desc & 0x0000ffff), EIM_CPU_TXBA); /* 16-bit offset address */
for (i = NUM_DESC_TX-1; i >= 0; i--)
{
@@ -2035,8 +2224,8 @@ static void c5471_eimconfig(struct c5471_driver_s *c5471)
/* RX CPU */
- ndbg("RX CPU desc: %08x pbuf: %08x\n", desc, pbuf);
- c5471->c_rxcpudesc = desc;
+ ninfo("RX CPU desc: %08x pbuf: %08x\n", desc, pbuf);
+ priv->c_rxcpudesc = desc;
putreg32((desc & 0x0000ffff), EIM_CPU_RXBA); /* 16-bit offset address */
for (i = NUM_DESC_RX-1; i >= 0; i--)
{
@@ -2063,7 +2252,7 @@ static void c5471_eimconfig(struct c5471_driver_s *c5471)
pbuf += sizeof(uint32_t); /* Ether Module's "Buffer Usage Word" */
}
- ndbg("END desc: %08x pbuf: %08x\n", desc, pbuf);
+ ninfo("END desc: %08x pbuf: %08x\n", desc, pbuf);
/* Save the descriptor packet size */
@@ -2147,17 +2336,17 @@ static void c5471_eimconfig(struct c5471_driver_s *c5471)
*
****************************************************************************/
-static void c5471_reset(struct c5471_driver_s *c5471)
+static void c5471_reset(struct c5471_driver_s *priv)
{
#if defined(CONFIG_C5471_PHY_LU3X31T_T64)
- ndbg("EIM reset\n");
- c5471_eimreset(c5471);
+ ninfo("EIM reset\n");
+ c5471_eimreset(priv);
#endif
- ndbg("PHY init\n");
+ ninfo("PHY init\n");
c5471_phyinit();
- ndbg("EIM config\n");
- c5471_eimconfig(c5471);
+ ninfo("EIM config\n");
+ c5471_eimconfig(priv);
}
/****************************************************************************
@@ -2172,13 +2361,13 @@ static void c5471_reset(struct c5471_driver_s *c5471)
*
****************************************************************************/
-static void c5471_macassign(struct c5471_driver_s *c5471)
+static void c5471_macassign(struct c5471_driver_s *priv)
{
- struct net_driver_s *dev = &c5471->c_dev;
+ struct net_driver_s *dev = &priv->c_dev;
uint8_t *mptr = dev->d_mac.ether_addr_octet;
register uint32_t tmp;
- ndbg("MAC: %0x:%0x:%0x:%0x:%0x:%0x\n",
+ ninfo("MAC: %0x:%0x:%0x:%0x:%0x:%0x\n",
mptr[0], mptr[1], mptr[2], mptr[3], mptr[4], mptr[5]);
/* Set CPU port MAC address. S/W will only see incoming packets that match
@@ -2237,17 +2426,18 @@ void up_netinitialize(void)
{
/* Attach the IRQ to the driver */
- if (irq_attach(C5471_IRQ_ETHER, c5471_interrupt))
+ if (irq_attach(C5471_IRQ_ETHER, c5471_interrupt, NULL))
{
/* We could not attach the ISR to the ISR */
- nlldbg("irq_attach() failed\n");
+ nerr("ERROR: irq_attach() failed\n");
return;
}
/* Initialize the driver structure */
memset(g_c5471, 0, CONFIG_C5471_NET_NINTERFACES*sizeof(struct c5471_driver_s));
+ g_c5471[0].c_dev.d_buf = g_pktbuf; /* Single packet buffer */
g_c5471[0].c_dev.d_ifup = c5471_ifup; /* I/F down callback */
g_c5471[0].c_dev.d_ifdown = c5471_ifdown; /* I/F up (new IP address) callback */
g_c5471[0].c_dev.d_txavail = c5471_txavail; /* New TX data callback */
diff --git a/arch/arm/src/c5471/c5471_serial.c b/arch/arm/src/c5471/c5471_serial.c
index 935bc46871de9100e78b1c337d3a7f9f2b754f9c..44d0dc7fd250d0b5e62204d6528faf25cff8f3a2 100644
--- a/arch/arm/src/c5471/c5471_serial.c
+++ b/arch/arm/src/c5471/c5471_serial.c
@@ -108,7 +108,7 @@ static int up_setup(struct uart_dev_s *dev);
static void up_shutdown(struct uart_dev_s *dev);
static int up_attach(struct uart_dev_s *dev);
static void up_detach(struct uart_dev_s *dev);
-static int up_interrupt(int irq, void *context);
+static int up_interrupt(int irq, void *context, void *arg);
static int up_ioctl(struct file *filep, int cmd, unsigned long arg);
static int up_receive(struct uart_dev_s *dev, unsigned int *status);
static void up_rxint(struct uart_dev_s *dev, bool enable);
@@ -491,7 +491,7 @@ static int up_attach(struct uart_dev_s *dev)
/* Attach and enable the IRQ */
- ret = irq_attach(priv->irq, up_interrupt);
+ ret = irq_attach(priv->irq, up_interrupt, dev);
if (ret == OK)
{
/* Enable the interrupt (RX and TX interrupts are still disabled
@@ -534,24 +534,13 @@ static void up_detach(struct uart_dev_s *dev)
*
****************************************************************************/
-static int up_interrupt(int irq, void *context)
+static int up_interrupt(int irq, void *context, void *arg)
{
- struct uart_dev_s *dev = NULL;
+ struct uart_dev_s *dev = (struct uart_dev_s *)arg;
struct up_dev_s *priv;
volatile uint32_t cause;
- if (g_irdapriv.irq == irq)
- {
- dev = &g_irdaport;
- }
- else if (g_modempriv.irq == irq)
- {
- dev = &g_modemport;
- }
- else
- {
- PANIC();
- }
+ DEBUGASSERT(dev != NULL && dev->priv != NULL);
priv = (struct up_dev_s *)dev->priv;
cause = up_inserial(priv, UART_ISR_OFFS) & 0x0000003f;
diff --git a/arch/arm/src/c5471/c5471_timerisr.c b/arch/arm/src/c5471/c5471_timerisr.c
index 6f1ca3da87b808f69a558e28e4cb23b2cd9814e8..3933e5252bb6a106cc6fa181e1318b71e9178b3f 100644
--- a/arch/arm/src/c5471/c5471_timerisr.c
+++ b/arch/arm/src/c5471/c5471_timerisr.c
@@ -70,19 +70,11 @@
#define PTV 0x00000003
/****************************************************************************
- * Private Types
+ * Private Functions
****************************************************************************/
/****************************************************************************
- * Private Function Prototypes
- ****************************************************************************/
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Function: up_timerisr
+ * Function: c5471_timerisr
*
* Description:
* The timer ISR will perform a variety of services for
@@ -90,7 +82,7 @@
*
****************************************************************************/
-int up_timerisr(int irq, uint32_t *regs)
+static int c5471_timerisr(int irq, uint32_t *regs, FAR void *arg)
{
/* Process timer interrupt */
@@ -99,7 +91,11 @@ int up_timerisr(int irq, uint32_t *regs)
}
/****************************************************************************
- * Function: up_timer_initialize
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function: arm_timer_initialize
*
* Description:
* This function is called during start-up to initialize
@@ -107,7 +103,7 @@ int up_timerisr(int irq, uint32_t *regs)
*
****************************************************************************/
-void up_timer_initialize(void)
+void arm_timer_initialize(void)
{
uint32_t val;
@@ -122,6 +118,6 @@ void up_timer_initialize(void)
/* Attach and enable the timer interrupt */
- irq_attach(C5471_IRQ_SYSTIMER, (xcpt_t)up_timerisr);
+ irq_attach(C5471_IRQ_SYSTIMER, (xcpt_t)c5471_timerisr, NULL);
up_enable_irq(C5471_IRQ_SYSTIMER);
}
diff --git a/arch/arm/src/c5471/c5471_watchdog.c b/arch/arm/src/c5471/c5471_watchdog.c
index 2143246d6e7597754d6716eb259808b946a17af4..baa7dd77496224d8fbecbfe9aadad9ffe4406841 100644
--- a/arch/arm/src/c5471/c5471_watchdog.c
+++ b/arch/arm/src/c5471/c5471_watchdog.c
@@ -95,7 +95,7 @@
static inline unsigned int wdt_prescaletoptv(unsigned int prescale);
static int wdt_setusec(uint32_t usec);
-static int wdt_interrupt(int irq, void *context);
+static int wdt_interrupt(int irq, void *context, FAR void *arg);
static int wdt_open(struct file *filep);
static int wdt_close(struct file *filep);
@@ -155,7 +155,7 @@ static inline unsigned int wdt_prescaletoptv(unsigned int prescale)
}
}
- dbg("prescale=%d -> ptv=%d\n", prescale, ptv);
+ wdinfo("prescale=%d -> ptv=%d\n", prescale, ptv);
return ptv;
}
@@ -173,7 +173,7 @@ static int wdt_setusec(uint32_t usec)
uint32_t divisor = 1;
uint32_t mode;
- dbg("usec=%d\n", usec);
+ wdinfo("usec=%d\n", usec);
/* Calculate a value of prescaler and divisor that will be able
* to count to the usec. It may not be exact or the best
@@ -186,7 +186,7 @@ static int wdt_setusec(uint32_t usec)
do
{
divisor = (CLOCK_MHZx2 * usec) / (prescaler * 2);
- dbg("divisor=0x%x prescaler=0x%x\n", divisor, prescaler);
+ wdinfo("divisor=0x%x prescaler=0x%x\n", divisor, prescaler);
if (divisor >= 0x10000)
{
@@ -194,7 +194,7 @@ static int wdt_setusec(uint32_t usec)
{
/* This is the max possible ~2.5 seconds. */
- dbg("prescaler=0x%x too big!\n", prescaler);
+ wderr("ERROR: prescaler=0x%x too big!\n", prescaler);
return ERROR;
}
@@ -207,19 +207,19 @@ static int wdt_setusec(uint32_t usec)
}
while (divisor >= 0x10000);
- dbg("prescaler=0x%x divisor=0x%x\n", prescaler, divisor);
+ wdinfo("prescaler=0x%x divisor=0x%x\n", prescaler, divisor);
mode = wdt_prescaletoptv(prescaler);
mode &= ~C5471_TIMER_AUTORELOAD; /* One shot mode. */
mode |= divisor << 5;
- dbg("mode=0x%x\n", mode);
+ wdinfo("mode=0x%x\n", mode);
c5471_wdt_cntl = mode;
/* Now start the watchdog */
c5471_wdt_cntl |= C5471_TIMER_STARTBIT;
- dbg("cntl_timer=0x%x\n", c5471_wdt_cntl);
+ wdinfo("cntl_timer=0x%x\n", c5471_wdt_cntl);
return 0;
}
@@ -232,19 +232,19 @@ static int wdt_setusec(uint32_t usec)
* Name: wdt_interrupt
****************************************************************************/
-static int wdt_interrupt(int irq, void *context)
+static int wdt_interrupt(int irq, void *context, FAR void *arg)
{
- dbg("expired\n");
+ wdinfo("expired\n");
#if defined(CONFIG_SOFTWARE_REBOOT)
# if defined(CONFIG_SOFTWARE_TEST)
- dbg(" Test only\n");
+ wdinfo(" Test only\n");
# else
- dbg(" Re-booting\n");
+ wdinfo(" Re-booting\n");
# warning "Add logic to reset CPU here"
# endif
#else
- dbg(" No reboot\n");
+ wdinfo(" No reboot\n");
#endif
return OK;
}
@@ -259,7 +259,7 @@ static ssize_t wdt_read(struct file *filep, char *buffer, size_t buflen)
* not work if the user provides a buffer smaller than 18 bytes.
*/
- dbg("buflen=%d\n", buflen);
+ wdinfo("buflen=%d\n", buflen);
if (buflen >= 18)
{
sprintf(buffer, "%08x %08x\n", c5471_wdt_cntl, c5471_wdt_count);
@@ -274,7 +274,7 @@ static ssize_t wdt_read(struct file *filep, char *buffer, size_t buflen)
static ssize_t wdt_write(struct file *filep, const char *buffer, size_t buflen)
{
- dbg("buflen=%d\n", buflen);
+ wdinfo("buflen=%d\n", buflen);
if (buflen)
{
/* Reset the timer to the maximum delay */
@@ -292,7 +292,7 @@ static ssize_t wdt_write(struct file *filep, const char *buffer, size_t buflen)
static int wdt_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
{
- dbg("ioctl Call: cmd=0x%x arg=0x%x", cmd, arg);
+ wdinfo("ioctl Call: cmd=0x%x arg=0x%x", cmd, arg);
/* Process the IOCTL command (see arch/watchdog.h) */
@@ -315,8 +315,6 @@ static int wdt_ioctl(FAR struct file *filep, int cmd, unsigned long arg)
static int wdt_open(struct file *filep)
{
- dbg("");
-
if (g_wdtopen)
{
return -EBUSY;
@@ -339,11 +337,8 @@ static int wdt_open(struct file *filep)
static int wdt_close(struct file *filep)
{
- dbg("");
-
/* The task controlling the watchdog has terminated. Take the timer
- * the
- * watchdog in interrupt mode -- we are going to reset unless the
+ * the watchdog in interrupt mode -- we are going to reset unless the
* reopened again soon.
*/
@@ -367,7 +362,7 @@ int up_wdtinit(void)
{
int ret;
- dbg("C547x Watchdog Driver\n");
+ wdinfo("C547x Watchdog Driver\n");
/* Register as /dev/wdt */
@@ -379,7 +374,7 @@ int up_wdtinit(void)
/* Register for an interrupt level callback through wdt_interrupt */
- dbg("Attach to IRQ=%d\n", C5471_IRQ_WATCHDOG);
+ wdinfo("Attach to IRQ=%d\n", C5471_IRQ_WATCHDOG);
/* Make sure that the timer is stopped */
@@ -387,7 +382,7 @@ int up_wdtinit(void)
/* Request the interrupt. */
- ret = irq_attach(C5471_IRQ_WATCHDOG, wdt_interrupt);
+ ret = irq_attach(C5471_IRQ_WATCHDOG, wdt_interrupt, NULL);
if (ret)
{
unregister_driver("/dev/wdt");
diff --git a/arch/arm/src/c5471/chip.h b/arch/arm/src/c5471/chip.h
index 580ae075dcd6a8fef32e505b78ef45e2cd249253..e1f40e58d3e9999a08b232b58e0c5787cbc4e561 100644
--- a/arch/arm/src/c5471/chip.h
+++ b/arch/arm/src/c5471/chip.h
@@ -1,5 +1,5 @@
/****************************************************************************
- * c5471/chip.h
+ * arch/arm/src/c5471/chip.h
*
* Copyright (C) 2007 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt
@@ -33,8 +33,8 @@
*
****************************************************************************/
-#ifndef __C5471_CHIP_H
-#define __C5471_CHIP_H
+#ifndef __ARCH_ARM_SRC_C5471_CHIP_H
+#define __ARCH_ARM_SRC_C5471_CHIP_H
/****************************************************************************
* Included Files
@@ -368,4 +368,4 @@
* Public Function Prototypes
****************************************************************************/
-#endif /* __C5471_CHIP_H */
+#endif /* __ARCH_ARM_SRC_C5471_CHIP_H */
diff --git a/arch/arm/src/calypso/Kconfig b/arch/arm/src/calypso/Kconfig
deleted file mode 100644
index e044280f6269506a88aea11e65cf644a639a958c..0000000000000000000000000000000000000000
--- a/arch/arm/src/calypso/Kconfig
+++ /dev/null
@@ -1,115 +0,0 @@
-#
-# For a description of the syntax of this configuration file,
-# see the file kconfig-language.txt in the NuttX tools repository.
-#
-
-comment "Calypso Configuration Options"
-
-menu "Modem UART Configuration"
-
-config UART_MODEM_BAUD
- int "Modem UART BAUD"
- default 115200
-
-config UART_MODEM_PARITY
- int "Modem UART parity"
- default 0
- ---help---
- Modem UART parity. 0=None, 1=Odd, 2=Even. Default: None
-
-config UART_MODEM_BITS
- int "Modem UART number of bits"
- default 8
- ---help---
- Modem UART number of bits. Default: 8
-
-config UART_MODEM_2STOP
- int "Modem UART two stop bits"
- default 0
- ---help---
- 0=1 stop bit, 1=Two stop bits. Default: 1 stop bit
-
-config UART_MODEM_RXBUFSIZE
- int "Modem UART Rx buffer size"
- default 256
- ---help---
- Modem UART Rx buffer size. Default: 256
-
-config UART_MODEM_TXBUFSIZE
- int "Modem UART Tx buffer size"
- default 256
- ---help---
- Modem UART Tx buffer size. Default: 256
-
-config UART_MODEM_HWFLOWCONTROL
- bool "Hardware flow control"
- default n
- ---help---
- Enabled Modem UART hardware flow control. Default: n
-
-endmenu
-
-menu "IrDA UART Configuration"
-
-config UART_IRDA_BAUD
- int "IrDA UART BAUD"
- default 115200
-
-config UART_IRDA_PARITY
- int "IrDA UART parity"
- default 0
- ---help---
- IrDA UART parity. 0=None, 1=Odd, 2=Even. Default: None
-
-config UART_IRDA_BITS
- int "IrDA UART number of bits"
- default 8
- ---help---
- IrDA UART number of bits. Default: 8
-
-config UART_IRDA_2STOP
- int "IrDA UART two stop bits"
- default 0
- ---help---
- 0=1 stop bit, 1=Two stop bits. Default: 1 stop bit
-
-config UART_IRDA_RXBUFSIZE
- int "IrDA UART Rx buffer size"
- default 256
- ---help---
- IrDA UART Rx buffer size. Default: 256
-
-config UART_IRDA_TXBUFSIZE
- int "IrDA UART Tx buffer size"
- default 256
- ---help---
- IrDA UART Tx buffer size. Default: 256
-
-config UART_IRDA_HWFLOWCONTROL
- bool "Hardware flow control"
- default n
- ---help---
- Enabled IrDA UART hardware flow control. Default: n
-
-endmenu
-
-choice
- prompt "Serial Console Selection"
- default SERIAL_CONSOLE_NONE
- depends on DEV_CONSOLE
-
-# See drivers/Kconfig
-config USE_SERCOMM_CONSOLE
- bool "SERCOMM console"
- select SERCOMM_CONSOLE
-
-config SERIAL_MODEM_CONSOLE
- bool "Serial console on modem UART"
-
-config SERIAL_IRDA_CONSOLE
- bool "Serial console on IrDA UART"
-
-config SERIAL_CONSOLE_NONE
- bool "No serial console"
-
-endchoice
diff --git a/arch/arm/src/calypso/Make.defs b/arch/arm/src/calypso/Make.defs
deleted file mode 100644
index c3d6b6b0bb53d4c625c3e08aefc5c8445bc6dc01..0000000000000000000000000000000000000000
--- a/arch/arm/src/calypso/Make.defs
+++ /dev/null
@@ -1,71 +0,0 @@
-############################################################################
-# calypso/Make.defs
-#
-# Copyright (C) 2007, 2013-2015 Gregory Nutt. All rights reserved.
-# Author: Gregory Nutt
-#
-# Copyright (C) 2011 Stefan Richter. All rights reserved.
-# Author: Stefan Richter
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions
-# are met:
-#
-# 1. Redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer.
-# 2. Redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in
-# the documentation and/or other materials provided with the
-# distribution.
-# 3. Neither the name Gregory Nutt nor the names of its contributors may be
-# used to endorse or promote products derived from this software
-# without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
-# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
-# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-# POSSIBILITY OF SUCH DAMAGE.
-#
-############################################################################
-
-HEAD_ASRC = calypso_head.S
-
-CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_vectors.S
-CMN_ASRCS += up_nommuhead.S vfork.S
-CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copyfullstate.c
-CMN_CSRCS += up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c
-CMN_CSRCS += up_doirq.c up_exit.c up_idle.c up_initialstate.c up_initialize.c
-CMN_CSRCS += up_interruptcontext.c up_prefetchabort.c up_releasepending.c
-CMN_CSRCS += up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c
-CMN_CSRCS += up_sigdeliver.c up_stackframe.c up_syscall.c up_unblocktask.c
-CMN_CSRCS += up_undefinedinsn.c up_usestack.c calypso_power.c up_vfork.c
-
-ifeq ($(CONFIG_ELF),y)
-CMN_CSRCS += up_elf.c
-else ifeq ($(CONFIG_MODULE),y)
-CMN_CSRCS += up_elf.c
-endif
-
-ifeq ($(CONFIG_STACK_COLORATION),y)
-CMN_CSRCS += up_checkstack.c
-endif
-
-CHIP_ASRCS = calypso_lowputc.S
-CHIP_CSRCS = calypso_irq.c calypso_heap.c calypso_serial.c clock.c
-CHIP_CSRCS += calypso_uwire.c calypso_armio.c calypso_keypad.c
-
-ifeq ($(CONFIG_SPI),y)
-CHIP_CSRCS += calypso_spi.c
-endif
-
-ifneq ($(CONFIG_SCHED_TICKLESS),y)
-CHIP_CSRCS += calypso_timer.c
-endif
diff --git a/arch/arm/src/calypso/calypso_armio.c b/arch/arm/src/calypso/calypso_armio.c
deleted file mode 100644
index c210fa34dce0e2b030308775ad9a30056e5f5d04..0000000000000000000000000000000000000000
--- a/arch/arm/src/calypso/calypso_armio.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/****************************************************************************
- * Driver for shared features of ARMIO modules
- *
- * Copyright (C) 2011 Stefan Richter. All rights reserved.
- * Author: Stefan Richter
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-#include
-
-#include
-#include
-
-#include
-#include
-
-#include "up_arch.h"
-
-/****************************************************************************
- * HW access
- ****************************************************************************/
-
-#define BASE_ADDR_ARMIO 0xfffe4800
-#define ARMIO_REG(x) (BASE_ADDR_ARMIO + (x))
-
-enum armio_reg {
- LATCH_IN = 0x00,
- LATCH_OUT = 0x02,
- IO_CNTL = 0x04,
- CNTL_REG = 0x06,
- LOAD_TIM = 0x08,
- KBR_LATCH_REG = 0x0a,
- KBC_REG = 0x0c,
- BUZZ_LIGHT_REG = 0x0e,
- LIGHT_LEVEL = 0x10,
- BUZZER_LEVEL = 0x12,
- GPIO_EVENT_MODE = 0x14,
- KBD_GPIO_INT = 0x16,
- KBD_GPIO_MASKIT = 0x18,
- GPIO_DEBOUNCING = 0x1a,
- GPIO_LATCH = 0x1c,
-};
-
-#define KBD_INT (1 << 0)
-#define GPIO_INT (1 << 1)
-
-/****************************************************************************
- * ARMIO interrupt handler
- * forward keypad events
- * forward GPIO events
- ****************************************************************************/
-
-static int kbd_gpio_irq(int irq, uint32_t *regs)
-{
- return calypso_kbd_irq(irq, regs);
-}
-
-/****************************************************************************
- * Initialize ARMIO
- ****************************************************************************/
-
-void calypso_armio(void)
-{
- /* Enable ARMIO clock */
-
- putreg16(1 << 5, ARMIO_REG(CNTL_REG));
-
- /* Mask GPIO interrupt and keypad interrupt */
-
- putreg16(KBD_INT | GPIO_INT, ARMIO_REG(KBD_GPIO_MASKIT));
-
- /* Attach and enable the interrupt */
-
- irq_attach(IRQ_KEYPAD_GPIO, (xcpt_t)kbd_gpio_irq);
- up_enable_irq(IRQ_KEYPAD_GPIO);
-}
diff --git a/arch/arm/src/calypso/calypso_head.S b/arch/arm/src/calypso/calypso_head.S
deleted file mode 100644
index eb83b68516f261043edeb713474cb864fda7b5d2..0000000000000000000000000000000000000000
--- a/arch/arm/src/calypso/calypso_head.S
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Place a branch to the real head at the entry point */
-.section .text.start
- b __start
-
-
-/* Exception Vectors like they are needed for the exception vector
- indirection of the internal boot ROM. The following section must
- be liked to appear at 0x80001c */
-.section .text.exceptions
-_undef_instr:
- b up_vectorundefinsn
-_sw_interr:
- b up_vectorswi
-_prefetch_abort:
- b up_vectorprefetch
-_data_abort:
- b up_vectordata
-_reserved:
- b _reserved
-_irq:
- b up_vectorirq
-_fiq:
- b up_vectorfiq
diff --git a/arch/arm/src/calypso/calypso_irq.c b/arch/arm/src/calypso/calypso_irq.c
deleted file mode 100644
index 85f4f084589bb7ac4e68b25f5761191a3bdcfdd3..0000000000000000000000000000000000000000
--- a/arch/arm/src/calypso/calypso_irq.c
+++ /dev/null
@@ -1,357 +0,0 @@
-/****************************************************************************
- * arch/arm/src/calypso/calypso_irq.c
- * Driver for Calypso IRQ controller
- *
- * (C) 2010 by Harald Welte
- * (C) 2011 by Stefan Richter
- *
- * This source code is derivated from Osmocom-BB project and was
- * relicensed as BSD with permission from original authors.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include
-
-#include
-#include
-
-#include
-#include
-
-#include
-#include
-
-#include "arm.h"
-#include "up_internal.h"
-#include "up_arch.h"
-
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-#define BASE_ADDR_IRQ 0xfffffa00
-#define BASE_ADDR_IBOOT_EXC 0x0080001C
-
-enum irq_reg
-{
- IT_REG1 = 0x00,
- IT_REG2 = 0x02,
- MASK_IT_REG1 = 0x08,
- MASK_IT_REG2 = 0x0a,
- IRQ_NUM = 0x10,
- FIQ_NUM = 0x12,
- IRQ_CTRL = 0x14,
-};
-
-#define ILR_IRQ(x) (0x20 + (x*2))
-#define IRQ_REG(x) (BASE_ADDR_IRQ + (x))
-
-#ifndef ARRAY_SIZE
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-#endif
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/* g_current_regs[] holds a references to the current interrupt level
- * register storage structure. If is non-NULL only during interrupt
- * processing. Access to g_current_regs[] must be through the macro
- * CURRENT_REGS for portability.
- */
-
-volatile uint32_t *g_current_regs[1];
-extern uint32_t _exceptions;
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-static uint8_t default_irq_prio[] =
-{
- [IRQ_WATCHDOG] = 0xff,
- [IRQ_TIMER1] = 0xff,
- [IRQ_TIMER2] = 0xff,
- [IRQ_TSP_RX] = 0,
- [IRQ_TPU_FRAME] = 3,
- [IRQ_TPU_PAGE] = 0xff,
- [IRQ_SIMCARD] = 0xff,
- [IRQ_UART_MODEM] = 8,
- [IRQ_KEYPAD_GPIO] = 4,
- [IRQ_RTC_TIMER] = 9,
- [IRQ_RTC_ALARM_I2C] = 10,
- [IRQ_ULPD_GAUGING] = 2,
- [IRQ_EXTERNAL] = 12,
- [IRQ_SPI] = 0xff,
- [IRQ_DMA] = 0xff,
- [IRQ_API] = 0xff,
- [IRQ_SIM_DETECT] = 0,
- [IRQ_EXTERNAL_FIQ] = 7,
- [IRQ_UART_IRDA] = 2,
- [IRQ_ULPD_GSM_TIMER] = 1,
- [IRQ_GEA] = 0xff,
-};
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-static void _irq_enable(enum irq_nr nr, int enable)
-{
- uintptr_t reg = IRQ_REG(MASK_IT_REG1);
- uint16_t val;
-
- if (nr > 15)
- {
- reg = IRQ_REG(MASK_IT_REG2);
- nr -= 16;
- }
-
- val = getreg16(reg);
- if (enable)
- {
- val &= ~(1 << nr);
- }
- else
- {
- val |= (1 << nr);
- }
-
- putreg16(val, reg);
-}
-
-static void set_default_priorities(void)
-{
- unsigned int i;
-
- for (i = 0; i < ARRAY_SIZE(default_irq_prio); i++)
- {
- uint16_t val;
- uint8_t prio = default_irq_prio[i];
-
- if (prio > 31)
- {
- prio = 31;
- }
-
- val = getreg16(IRQ_REG(ILR_IRQ(i)));
- val &= ~(0x1f << 2);
- val |= prio << 2;
-
- /* Make edge mode default. Hopefully causes less trouble */
-
- val |= 0x02;
-
- putreg16(val, IRQ_REG(ILR_IRQ(i)));
- }
-}
-
-/* Install the exception handlers to where the ROM loader jumps */
-
-static void calypso_exceptions_install(void)
-{
- uint32_t *exceptions_dst = (uint32_t *) BASE_ADDR_IBOOT_EXC;
- uint32_t *exceptions_src = &_exceptions;
- int i;
-
- for (i = 0; i < 7; i++)
- {
- *exceptions_dst++ = *exceptions_src++;
- }
-}
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: up_irqinitialize
- *
- * Description:
- * Setup the IRQ and FIQ controllers
- *
- ****************************************************************************/
-
-void up_irqinitialize(void)
-{
- /* Prepare hardware */
-
- calypso_exceptions_install();
- CURRENT_REGS = NULL;
-
- /* Switch to internal ROM */
-
- calypso_bootrom(1);
-
- /* Set default priorities */
-
- set_default_priorities();
-
- /* Mask all interrupts off */
-
- putreg16(0xffff, IRQ_REG(MASK_IT_REG1));
- putreg16(0xffff, IRQ_REG(MASK_IT_REG2));
-
- /* clear all pending interrupts */
- putreg16(0, IRQ_REG(IT_REG1));
- putreg16(0, IRQ_REG(IT_REG2));
-
- /* Enable interrupts globally to the ARM core */
-
-#ifndef CONFIG_SUPPRESS_INTERRUPTS
- up_irq_restore(SVC_MODE | PSR_F_BIT);
-#endif
-}
-
-/****************************************************************************
- * Name: up_disable_irq
- *
- * Description:
- * Disable the IRQ specified by 'irq'
- *
- ****************************************************************************/
-
-void up_disable_irq(int irq)
-{
- if ((unsigned)irq < NR_IRQS)
- {
- _irq_enable(irq, 0);
- }
-}
-
-/****************************************************************************
- * Name: up_enable_irq
- *
- * Description:
- * Enable the IRQ specified by 'irq'
- *
- ****************************************************************************/
-
-void up_enable_irq(int irq)
-{
- if ((unsigned)irq < NR_IRQS)
- {
- _irq_enable(irq, 1);
- }
-}
-
-/****************************************************************************
- * Name: up_prioritize_irq
- *
- * Description:
- * Set the priority of an IRQ.
- *
- ****************************************************************************/
-
-#ifndef CONFIG_ARCH_IRQPRIO
-int up_prioritize_irq(int nr, int prio)
-{
- uint16_t val;
-
- if (prio == -1)
- {
- prio = default_irq_prio[nr];
- }
-
- if (prio > 31)
- {
- prio = 31;
- }
-
- val = prio << 2;
- putreg16(val, IRQ_REG(ILR_IRQ(nr)));
-
- return 0;
-}
-#endif
-
-/****************************************************************************
- * Entry point for interrupts
- ****************************************************************************/
-
-void up_decodeirq(uint32_t *regs)
-{
- uint8_t num, tmp;
- uint32_t *saved_regs;
-
- /* XXX: What is this???
- * Passed to but ignored in IRQ handlers
- * Only valid meaning is apparently non-NULL == IRQ context */
-
- saved_regs = (uint32_t *)CURRENT_REGS;
- CURRENT_REGS = regs;
-
- /* Detect & deliver the IRQ */
-
- num = getreg8(IRQ_REG(IRQ_NUM)) & 0x1f;
- irq_dispatch(num, regs);
-
- /* Start new IRQ agreement */
-
- tmp = getreg8(IRQ_REG(IRQ_CTRL));
- tmp |= 0x01;
- putreg8(tmp, IRQ_REG(IRQ_CTRL));
-
- CURRENT_REGS = saved_regs;
-}
-
-/****************************************************************************
- * Entry point for FIQs
- ****************************************************************************/
-
-void calypso_fiq(void)
-{
- uint8_t num, tmp;
- uint32_t *regs;
-
- /* XXX: What is this???
- * Passed to but ignored in IRQ handlers
- * Only valid meaning is apparently non-NULL == IRQ context */
-
- regs = (uint32_t *)CURRENT_REGS;
- CURRENT_REGS = (uint32_t *)#
-
- /* Detect & deliver like an IRQ but we are in FIQ context */
-
- num = getreg8(IRQ_REG(FIQ_NUM)) & 0x1f;
- irq_dispatch(num, regs);
-
- /* Start new FIQ agreement */
-
- tmp = getreg8(IRQ_REG(IRQ_CTRL));
- tmp |= 0x02;
- putreg8(tmp, IRQ_REG(IRQ_CTRL));
-
- CURRENT_REGS = regs;
-}
diff --git a/arch/arm/src/calypso/calypso_keypad.c b/arch/arm/src/calypso/calypso_keypad.c
deleted file mode 100644
index 2430667ca553012fdcec47709e6576c4ec6d3eb0..0000000000000000000000000000000000000000
--- a/arch/arm/src/calypso/calypso_keypad.c
+++ /dev/null
@@ -1,380 +0,0 @@
-/****************************************************************************
- * Driver for Calypso keypad hardware
- *
- * Copyright (C) 2011 Stefan Richter. All rights reserved.
- * Author: Stefan Richter
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-#include
-
-#include
-#include
-#include
-
-#include
-#include
-#include
-#include
-#include
-
-#include
-#include
-#include
-#include
-
-/****************************************************************************
- * HW access
- ****************************************************************************/
-
-#define BASE_ADDR_ARMIO 0xfffe4800
-#define ARMIO_REG(x) ((void *)BASE_ADDR_ARMIO + (x))
-
-enum armio_reg
-{
- LATCH_IN = 0x00,
- LATCH_OUT = 0x02,
- IO_CNTL = 0x04,
- CNTL_REG = 0x06,
- LOAD_TIM = 0x08,
- KBR_LATCH_REG = 0x0a,
- KBC_REG = 0x0c,
- BUZZ_LIGHT_REG = 0x0e,
- LIGHT_LEVEL = 0x10,
- BUZZER_LEVEL = 0x12,
- GPIO_EVENT_MODE = 0x14,
- KBD_GPIO_INT = 0x16,
- KBD_GPIO_MASKIT = 0x18,
- GPIO_DEBOUNCING = 0x1a,
- GPIO_LATCH = 0x1c,
-};
-
-#define KBD_INT (1 << 0)
-#define GPIO_INT (1 << 1)
-
-/****************************************************************************
- * Decoder functions for matrix and power button
- ****************************************************************************/
-
-static int btn_dec(uint32_t * btn_state, uint8_t col, uint8_t reg,
- char *buf, size_t buflen, size_t * len)
-{
- uint8_t diff = (*btn_state ^ reg) & 0x1f;
-
- while (diff)
- {
- uint8_t val = diff & ~(diff - 1);
- uint8_t sc = val >> 1;
- sc |= sc << 2;
- sc += col;
- sc += (sc & 0x20) ? 0x26 : 0x3f;
-
- if (reg & val)
- {
- sc |= 0x20;
- }
-
- /* Check for space in buffer and dispatch */
-
- if (*len < buflen)
- {
- buf[(*len)++] = sc;
- }
- else
- {
- break;
- }
-
- /* Only change diff if dispatched/buffer not full */
-
- diff ^= val;
- }
-
- /* Store new state of the buttons (but only if they where dispatch) */
-
- *btn_state >>= 5;
-#ifdef INCLUDE_ALL_COLS
- *btn_state |= (reg ^ diff) << 20;
-#else
- *btn_state |= (reg ^ diff) << 15;
-#endif
- return diff;
-}
-
-static int pwr_btn_dec(uint32_t * state, uint8_t reg, char *buf, size_t * len)
-{
- if (reg)
- {
- /* Check for pressed power button. If pressed, ignore other
- * buttons since it collides with an entire row.
- */
-
- if (~*state & 0x80000000)
- {
- buf[0] = 'z';
- *len = 1;
- *state |= 0x80000000;
- }
-
- return 1; /* break loop in caller */
- }
- else
- {
- /* Check for released power button. */
-
- if (*state & 0x80000000)
- {
- buf[0] = 'Z';
- *len = 1;
-
- *state &= 0x7fffffff;
-
- /* Don't scan others when released; might trigger
- * false keystrokes otherwise
- */
-
- return 1;
- }
- }
-
- return 0; /* Continue with other columns */
-}
-
-/****************************************************************************
- * Keypad: Fileops Prototypes and Structures
- ****************************************************************************/
-
-typedef FAR struct file file_t;
-
-static int keypad_open(file_t * filep);
-static int keypad_close(file_t * filep);
-static ssize_t keypad_read(file_t * filep, FAR char *buffer, size_t buflen);
-#ifndef CONFIG_DISABLE_POLL
-static int keypad_poll(file_t * filep, FAR struct pollfd *fds, bool setup);
-#endif
-
-static const struct file_operations keypad_ops =
-{
- keypad_open, /* open */
- keypad_close, /* close */
- keypad_read, /* read */
- 0, /* write */
- 0, /* seek */
- 0, /* ioctl */
-#ifndef CONFIG_DISABLE_POLL
- keypad_poll /* poll */
-#endif
-};
-
-static sem_t kbdsem;
-
-/****************************************************************************
- * Keypad: Fileops
- ****************************************************************************/
-
-static int keypad_open(file_t * filep)
-{
- register uint16_t reg;
-
- /* Unmask keypad interrupt */
-
- reg = readw(ARMIO_REG(KBD_GPIO_MASKIT));
- writew(reg & ~KBD_INT, ARMIO_REG(KBD_GPIO_MASKIT));
-
- return OK;
-}
-
-static int keypad_close(file_t * filep)
-{
- register uint16_t reg;
-
- /* Mask keypad interrupt */
-
- reg = readw(ARMIO_REG(KBD_GPIO_MASKIT));
- writew(reg | KBD_INT, ARMIO_REG(KBD_GPIO_MASKIT));
-
- return OK;
-}
-
-static ssize_t keypad_read(file_t * filep, FAR char *buf, size_t buflen)
-{
- static uint32_t btn_state = 0;
- register uint16_t reg;
- uint16_t col, col_mask;
- size_t len = 0;
-
- if (buf == NULL || buflen < 1)
- {
- /* Well... nothing to do */
-
- return -EINVAL;
- }
-
-retry:
- col = 1;
- col_mask = 0x1e;
-
- if (!btn_state)
- {
- /* Drive all cols low such that all buttons cause events */
-
- writew(0, ARMIO_REG(KBC_REG));
-
- /* No button currently pressed, use IRQ */
-
- reg = readw(ARMIO_REG(KBD_GPIO_MASKIT));
- writew(reg & ~KBD_INT, ARMIO_REG(KBD_GPIO_MASKIT));
- sem_wait(&kbdsem);
- }
- else
- {
- writew(0x1f, ARMIO_REG(KBC_REG));
- usleep(80000);
- }
-
- /* Scan columns */
-
-#ifdef INCLUDE_ALL_COLS
- while (col <= 6)
- {
-#else
- while (col <= 5)
- {
-#endif
- /* Read keypad latch and immediately set new column since
- * synchronization takes about 5usec. For the 1st round, the
- * interrupt has prepared this and the context switch takes
- * long enough to serve as a delay.
- */
-
- reg = readw(ARMIO_REG(KBR_LATCH_REG));
- writew(col_mask, ARMIO_REG(KBC_REG));
-
- /* Turn pressed buttons into 1s */
-
- reg = 0x1f & ~reg;
-
- if (col == 1)
- {
- /* Power/End switch */
-
- if (pwr_btn_dec(&btn_state, reg, buf, &len))
- {
- break;
- }
- }
- else
- {
- /* Non-power switches */
-
- if (btn_dec(&btn_state, col, reg, buf, buflen, &len))
- {
- break;
- }
- }
-
- /* Select next column and respective mask */
-
- col_mask = 0x1f & ~(1 << col++);
-
- /* We have to wait for synchronization of the inputs. The
- * processing is too fast if no/few buttons are processed.
- */
-
- usleep(5);
-
- /* XXX: usleep seems to suffer hugh overhead. Better this!?
- * If nothing else can be done, it's overhead still wastes
- * time 'usefully'.
- */
- /* sched_yield(); up_udelay(2); */
- }
-
- /* If we don't have anything to return, retry to avoid EOF */
-
- if (!len)
- {
- goto retry;
- }
-
- return len;
-}
-
-/****************************************************************************
- * Keypad interrupt handler
- * mask interrupts
- * prepare column drivers for scan
- * posts keypad semaphore
- ****************************************************************************/
-
-int calypso_kbd_irq(int irq, uint32_t * regs)
-{
- register uint16_t reg;
-
- /* Mask keypad interrupt */
-
- reg = readw(ARMIO_REG(KBD_GPIO_MASKIT));
- writew(reg | KBD_INT, ARMIO_REG(KBD_GPIO_MASKIT));
-
- /* Turn off column drivers */
-
- writew(0x1f, ARMIO_REG(KBC_REG));
-
- /* Let the userspace know */
-
- sem_post(&kbdsem);
-
- return 0;
-}
-
-/****************************************************************************
- * Initialize device, add /dev/... nodes
- ****************************************************************************/
-
-void up_keypad(void)
-{
- /* Semaphore; helps leaving IRQ ctx as soon as possible */
-
- sem_init(&kbdsem, 0, 0);
-
- /* Drive cols low in idle state such that all buttons cause events */
-
- writew(0, ARMIO_REG(KBC_REG));
-
- (void)register_driver("/dev/keypad", &keypad_ops, 0444, NULL);
-}
-
-int keypad_kbdinit(void)
-{
- calypso_armio();
- up_keypad();
-
- return OK;
-}
diff --git a/arch/arm/src/calypso/calypso_power.c b/arch/arm/src/calypso/calypso_power.c
deleted file mode 100644
index 11b51a629bf63315435e70725a0df8bd4f47ed56..0000000000000000000000000000000000000000
--- a/arch/arm/src/calypso/calypso_power.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include
-
-#include
-
-#include
-#include |