From 84723f6a54b73e653b16171f5dd11b6689e0a93d Mon Sep 17 00:00:00 2001 From: patacongo <patacongo@42af7a65-404d-4744-a932-0658087f49c3> Date: Wed, 10 Aug 2011 21:18:00 +0000 Subject: [PATCH] Add Kinetis ADC, CRC, RNGB and MMCAU header files git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@3864 42af7a65-404d-4744-a932-0658087f49c3 --- arch/arm/src/kinetis/chip.h | 72 +++---- arch/arm/src/kinetis/kinetis_adc.h | 311 +++++++++++++++++++++++++++ arch/arm/src/kinetis/kinetis_crc.h | 3 + arch/arm/src/kinetis/kinetis_mmcau.h | 138 ++++++++++++ arch/arm/src/kinetis/kinetis_rngb.h | 161 ++++++++++++++ arch/arm/src/kinetis/kinetis_rtc.h | 3 + 6 files changed, 652 insertions(+), 36 deletions(-) create mode 100644 arch/arm/src/kinetis/kinetis_adc.h create mode 100644 arch/arm/src/kinetis/kinetis_mmcau.h create mode 100644 arch/arm/src/kinetis/kinetis_rngb.h diff --git a/arch/arm/src/kinetis/chip.h b/arch/arm/src/kinetis/chip.h index 704f343e87..d893d104f9 100644 --- a/arch/arm/src/kinetis/chip.h +++ b/arch/arm/src/kinetis/chip.h @@ -88,8 +88,8 @@ # define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ # undef KINETIS_NTIMERS20 /* No 20 channel timers */ # undef KINETIS_NRNG /* No random number generator */ -# define KINETIS_RTC 1 /* Real time clock */ -# undef KINETIS_NENCRYPT /* No hardware encryption */ +# define KINETIS_NRTC 1 /* Real time clock */ +# undef KINETIS_NMMCAU /* No hardware encryption */ # undef KINETIS_NTAMPER /* No tamper detect */ # define KINETIS_NCRC 1 /* CRC */ @@ -132,9 +132,9 @@ # define KINETIS_NVREF 1 /* Voltage reference */ # define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ # undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_RTC 1 /* Real time clock */ +# define KINETIS_NRTC 1 /* Real time clock */ # undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NENCRYPT /* No hardware encryption */ +# undef KINETIS_NMMCAU /* No hardware encryption */ # undef KINETIS_NTAMPER /* No tamper detect */ # define KINETIS_NCRC 1 /* CRC */ @@ -173,9 +173,9 @@ # define KINETIS_NVREF 1 /* Voltage reference */ # define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ # undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_RTC 1 /* Real time clock */ +# define KINETIS_NRTC 1 /* Real time clock */ # undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NENCRYPT /* No hardware encryption */ +# undef KINETIS_NMMCAU /* No hardware encryption */ # undef KINETIS_NTAMPER /* No tamper detect */ # define KINETIS_NCRC 1 /* CRC */ @@ -213,9 +213,9 @@ # define KINETIS_NVREF 1 /* Voltage reference */ # define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ # undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_RTC 1 /* Real time clock */ +# define KINETIS_NRTC 1 /* Real time clock */ # undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NENCRYPT /* No hardware encryption */ +# undef KINETIS_NMMCAU /* No hardware encryption */ # undef KINETIS_NTAMPER /* No tamper detect */ # define KINETIS_NCRC 1 /* CRC */ @@ -253,9 +253,9 @@ # define KINETIS_NVREF 1 /* Voltage reference */ # define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ # undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_RTC 1 /* Real time clock */ +# define KINETIS_NRTC 1 /* Real time clock */ # undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NENCRYPT /* No hardware encryption */ +# undef KINETIS_NMMCAU /* No hardware encryption */ # undef KINETIS_NTAMPER /* No tamper detect */ # define KINETIS_NCRC 1 /* CRC */ @@ -295,9 +295,9 @@ # define KINETIS_NVREF 1 /* Voltage reference */ # define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ # undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_RTC 1 /* Real time clock */ +# define KINETIS_NRTC 1 /* Real time clock */ # undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NENCRYPT /* No hardware encryption */ +# undef KINETIS_NMMCAU /* No hardware encryption */ # undef KINETIS_NTAMPER /* No tamper detect */ # define KINETIS_NCRC 1 /* CRC */ @@ -338,9 +338,9 @@ # define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ # define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ # undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_RTC 1 /* Real time clock */ +# define KINETIS_NRTC 1 /* Real time clock */ # undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NENCRYPT /* No hardware encryption */ +# undef KINETIS_NMMCAU /* No hardware encryption */ # undef KINETIS_NTAMPER /* No tamper detect */ # define KINETIS_NCRC 1 /* CRC */ @@ -381,9 +381,9 @@ # define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ # define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ # undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_RTC 1 /* Real time clock */ +# define KINETIS_NRTC 1 /* Real time clock */ # undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NENCRYPT /* No hardware encryption */ +# undef KINETIS_NMMCAU /* No hardware encryption */ # undef KINETIS_NTAMPER /* No tamper detect */ # define KINETIS_NCRC 1 /* CRC */ @@ -424,9 +424,9 @@ # define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ # define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ # undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_RTC 1 /* Real time clock */ +# define KINETIS_NRTC 1 /* Real time clock */ # undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NENCRYPT /* No hardware encryption */ +# undef KINETIS_NMMCAU /* No hardware encryption */ # undef KINETIS_NTAMPER /* No tamper detect */ # define KINETIS_NCRC 1 /* CRC */ @@ -467,9 +467,9 @@ # define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ # define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ # undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_RTC 1 /* Real time clock */ +# define KINETIS_NRTC 1 /* Real time clock */ # undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NENCRYPT /* No hardware encryption */ +# undef KINETIS_NMMCAU /* No hardware encryption */ # undef KINETIS_NTAMPER /* No tamper detect */ # define KINETIS_NCRC 1 /* CRC */ @@ -510,9 +510,9 @@ # define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ # define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ # undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_RTC 1 /* Real time clock */ +# define KINETIS_NRTC 1 /* Real time clock */ # undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NENCRYPT /* No hardware encryption */ +# undef KINETIS_NMMCAU /* No hardware encryption */ # undef KINETIS_NTAMPER /* No tamper detect */ # define KINETIS_NCRC 1 /* CRC */ @@ -553,9 +553,9 @@ # define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ # define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ # undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_RTC 1 /* Real time clock */ +# define KINETIS_NRTC 1 /* Real time clock */ # undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NENCRYPT /* No hardware encryption */ +# undef KINETIS_NMMCAU /* No hardware encryption */ # undef KINETIS_NTAMPER /* No tamper detect */ # define KINETIS_NCRC 1 /* CRC */ @@ -596,9 +596,9 @@ # define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ # define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ # undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_RTC 1 /* Real time clock */ +# define KINETIS_NRTC 1 /* Real time clock */ # undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NENCRYPT /* No hardware encryption */ +# undef KINETIS_NMMCAU /* No hardware encryption */ # undef KINETIS_NTAMPER /* No tamper detect */ # define KINETIS_NCRC 1 /* CRC */ @@ -639,9 +639,9 @@ # define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ # define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ # undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_RTC 1 /* Real time clock */ +# define KINETIS_NRTC 1 /* Real time clock */ # undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NENCRYPT /* No hardware encryption */ +# undef KINETIS_NMMCAU /* No hardware encryption */ # undef KINETIS_NTAMPER /* No tamper detect */ # define KINETIS_NCRC 1 /* CRC */ @@ -682,9 +682,9 @@ # define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ # define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ # undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_RTC 1 /* Real time clock */ +# define KINETIS_NRTC 1 /* Real time clock */ # undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NENCRYPT /* No hardware encryption */ +# undef KINETIS_NMMCAU /* No hardware encryption */ # undef KINETIS_NTAMPER /* No tamper detect */ # define KINETIS_NCRC 1 /* CRC */ @@ -725,9 +725,9 @@ # define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ # define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ # undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_RTC 1 /* Real time clock */ +# define KINETIS_NRTC 1 /* Real time clock */ # undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NENCRYPT /* No hardware encryption */ +# undef KINETIS_NMMCAU /* No hardware encryption */ # undef KINETIS_NTAMPER /* No tamper detect */ # define KINETIS_NCRC 1 /* CRC */ @@ -768,9 +768,9 @@ # define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ # define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ # undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_RTC 1 /* Real time clock */ +# define KINETIS_NRTC 1 /* Real time clock */ # undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NENCRYPT /* No hardware encryption */ +# undef KINETIS_NMMCAU /* No hardware encryption */ # undef KINETIS_NTAMPER /* No tamper detect */ # define KINETIS_NCRC 1 /* CRC */ @@ -811,9 +811,9 @@ # define KINETIS_NTIMERS20 4 /* Four 20 channel timers */ # define KINETIS_NTIMERS12 3 /* Three 12 channel timers */ # undef KINETIS_NTIMERS20 /* No 20 channel timers */ -# define KINETIS_RTC 1 /* Real time clock */ +# define KINETIS_NRTC 1 /* Real time clock */ # undef KINETIS_NRNG /* No random number generator */ -# undef KINETIS_NENCRYPT /* No hardware encryption */ +# undef KINETIS_NMMCAU /* No hardware encryption */ # undef KINETIS_NTAMPER /* No tamper detect */ # define KINETIS_NCRC 1 /* CRC */ diff --git a/arch/arm/src/kinetis/kinetis_adc.h b/arch/arm/src/kinetis/kinetis_adc.h new file mode 100644 index 0000000000..7ddda81371 --- /dev/null +++ b/arch/arm/src/kinetis/kinetis_adc.h @@ -0,0 +1,311 @@ +/******************************************************************************************** + * arch/arm/src/kinetis/kinetis_adc.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_ADC_H +#define __ARCH_ARM_SRC_KINETIS_KINETIS_ADC_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ + +/* Register Offsets *************************************************************************/ + +#define KINETIS_ADC_SC1A_OFFSET 0x0000 /* ADC status and control registers 1 */ +#define KINETIS_ADC_SC1B_OFFSET 0x0004 /* ADC status and control registers 1 */ +#define KINETIS_ADC_CFG1_OFFSET 0x0008 /* ADC configuration register 1 */ +#define KINETIS_ADC_CFG2_OFFSET 0x000c /* Configuration register 2 */ +#define KINETIS_ADC_RA_OFFSET 0x0010 /* ADC data result register */ +#define KINETIS_ADC_RB_OFFSET 0x0014 /* ADC data result register */ +#define KINETIS_ADC_CV1_OFFSET 0x0018 /* Compare value registers */ +#define KINETIS_ADC_CV2_OFFSET 0x001c /* Compare value registers */ +#define KINETIS_ADC_SC2_OFFSET 0x0020 /* Status and control register 2 */ +#define KINETIS_ADC_SC3_OFFSET 0x0024 /* Status and control register 3 */ +#define KINETIS_ADC_OFS_OFFSET 0x0028 /* ADC offset correction register */ +#define KINETIS_ADC_PG_OFFSET 0x002c /* ADC plus-side gain register */ +#define KINETIS_ADC_MG_OFFSET 0x0030 /* ADC minus-side gain register */ +#define KINETIS_ADC_CLPD_OFFSET 0x0034 /* ADC plus-side general calibration value register */ +#define KINETIS_ADC_CLPS_OFFSET 0x0038 /* ADC plus-side general calibration value register */ +#define KINETIS_ADC_CLP4_OFFSET 0x003c /* ADC plus-side general calibration value register */ +#define KINETIS_ADC_CLP3_OFFSET 0x0040 /* ADC plus-side general calibration value register */ +#define KINETIS_ADC_CLP2_OFFSET 0x0044 /* ADC plus-side general calibration value register */ +#define KINETIS_ADC_CLP1_OFFSET 0x0048 /* ADC plus-side general calibration value register */ +#define KINETIS_ADC_CLP0_OFFSET 0x004c /* ADC plus-side general calibration value register */ +#define KINETIS_ADC_PGA_OFFSET 0x0050 /* ADC PGA register */ +#define KINETIS_ADC_CLMD_OFFSET 0x0054 /* ADC minus-side general calibration value register */ +#define KINETIS_ADC_CLMS_OFFSET 0x0058 /* ADC minus-side general calibration value register */ +#define KINETIS_ADC_CLM4_OFFSET 0x005c /* ADC minus-side general calibration value register */ +#define KINETIS_ADC_CLM3_OFFSET 0x0060 /* ADC minus-side general calibration value register */ +#define KINETIS_ADC_CLM2_OFFSET 0x0064 /* ADC minus-side general calibration value register */ +#define KINETIS_ADC_CLM1_OFFSET 0x0068 /* ADC minus-side general calibration value register */ +#define KINETIS_ADC_CLM0_OFFSET 0x006c /* ADC minus-side general calibration value register */ + +/* Register Addresses ***********************************************************************/ +# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */ + +#define KINETIS_ADC0_SC1A (KINETIS_ADC0_BASE+KINETIS_ADC_SC1A_OFFSET) +#define KINETIS_ADC0_SC1B (KINETIS_ADC0_BASE+KINETIS_ADC_SC1B_OFFSET) +#define KINETIS_ADC0_CFG1 (KINETIS_ADC0_BASE+KINETIS_ADC_CFG1_OFFSET) +#define KINETIS_ADC0_CFG2 (KINETIS_ADC0_BASE+KINETIS_ADC_CFG2_OFFSET) +#define KINETIS_ADC0_RA (KINETIS_ADC0_BASE+KINETIS_ADC_RA_OFFSET) +#define KINETIS_ADC0_RB (KINETIS_ADC0_BASE+KINETIS_ADC_RB_OFFSET) +#define KINETIS_ADC0_CV1 (KINETIS_ADC0_BASE+KINETIS_ADC_CV1_OFFSET) +#define KINETIS_ADC0_CV2 (KINETIS_ADC0_BASE+KINETIS_ADC_CV2_OFFSET) +#define KINETIS_ADC0_SC2 (KINETIS_ADC0_BASE+KINETIS_ADC_SC2_OFFSET) +#define KINETIS_ADC0_SC3 (KINETIS_ADC0_BASE+KINETIS_ADC_SC3_OFFSET) +#define KINETIS_ADC0_OFS (KINETIS_ADC0_BASE+KINETIS_ADC_OFS_OFFSET) +#define KINETIS_ADC0_PG (KINETIS_ADC0_BASE+KINETIS_ADC_PG_OFFSET) +#define KINETIS_ADC0_MG (KINETIS_ADC0_BASE+KINETIS_ADC_MG_OFFSET) +#define KINETIS_ADC0_CLPD (KINETIS_ADC0_BASE+KINETIS_ADC_CLPD_OFFSET) +#define KINETIS_ADC0_CLPS (KINETIS_ADC0_BASE+KINETIS_ADC_CLPS_OFFSET) +#define KINETIS_ADC0_CLP4 (KINETIS_ADC0_BASE+KINETIS_ADC_CLP4_OFFSET) +#define KINETIS_ADC0_CLP3 (KINETIS_ADC0_BASE+KINETIS_ADC_CLP3_OFFSET) +#define KINETIS_ADC0_CLP2 (KINETIS_ADC0_BASE+KINETIS_ADC_CLP2_OFFSET) +#define KINETIS_ADC0_CLP1 (KINETIS_ADC0_BASE+KINETIS_ADC_CLP1_OFFSET) +#define KINETIS_ADC0_CLP0 (KINETIS_ADC0_BASE+KINETIS_ADC_CLP0_OFFSET) +#define KINETIS_ADC0_PGA (KINETIS_ADC0_BASE+KINETIS_ADC_PGA_OFFSET) +#define KINETIS_ADC0_CLMD (KINETIS_ADC0_BASE+KINETIS_ADC_CLMD_OFFSET) +#define KINETIS_ADC0_CLMS (KINETIS_ADC0_BASE+KINETIS_ADC_CLMS_OFFSET) +#define KINETIS_ADC0_CLM4 (KINETIS_ADC0_BASE+KINETIS_ADC_CLM4_OFFSET) +#define KINETIS_ADC0_CLM3 (KINETIS_ADC0_BASE+KINETIS_ADC_CLM3_OFFSET) +#define KINETIS_ADC0_CLM2 (KINETIS_ADC0_BASE+KINETIS_ADC_CLM2_OFFSET) +#define KINETIS_ADC0_CLM1 (KINETIS_ADC0_BASE+KINETIS_ADC_CLM1_OFFSET) +#define KINETIS_ADC0_CLM0 (KINETIS_ADC0_BASE+KINETIS_ADC_CLM0_OFFSET) + +#define KINETIS_ADC1_SC1A (KINETIS_ADC1_BASE+KINETIS_ADC_SC1A_OFFSET) +#define KINETIS_ADC1_SC1B (KINETIS_ADC1_BASE+KINETIS_ADC_SC1B_OFFSET) +#define KINETIS_ADC1_CFG1 (KINETIS_ADC1_BASE+KINETIS_ADC_CFG1_OFFSET) +#define KINETIS_ADC1_CFG2 (KINETIS_ADC1_BASE+KINETIS_ADC_CFG2_OFFSET) +#define KINETIS_ADC1_RA (KINETIS_ADC1_BASE+KINETIS_ADC_RA_OFFSET) +#define KINETIS_ADC1_RB (KINETIS_ADC1_BASE+KINETIS_ADC_RB_OFFSET) +#define KINETIS_ADC1_CV1 (KINETIS_ADC1_BASE+KINETIS_ADC_CV1_OFFSET) +#define KINETIS_ADC1_CV2 (KINETIS_ADC1_BASE+KINETIS_ADC_CV2_OFFSET) +#define KINETIS_ADC1_SC2 (KINETIS_ADC1_BASE+KINETIS_ADC_SC2_OFFSET) +#define KINETIS_ADC1_SC3 (KINETIS_ADC1_BASE+KINETIS_ADC_SC3_OFFSET) +#define KINETIS_ADC1_OFS (KINETIS_ADC1_BASE+KINETIS_ADC_OFS_OFFSET) +#define KINETIS_ADC1_PG (KINETIS_ADC1_BASE+KINETIS_ADC_PG_OFFSET) +#define KINETIS_ADC1_MG (KINETIS_ADC1_BASE+KINETIS_ADC_MG_OFFSET) +#define KINETIS_ADC1_CLPD (KINETIS_ADC1_BASE+KINETIS_ADC_CLPD_OFFSET) +#define KINETIS_ADC1_CLPS (KINETIS_ADC1_BASE+KINETIS_ADC_CLPS_OFFSET) +#define KINETIS_ADC1_CLP4 (KINETIS_ADC1_BASE+KINETIS_ADC_CLP4_OFFSET) +#define KINETIS_ADC1_CLP3 (KINETIS_ADC1_BASE+KINETIS_ADC_CLP3_OFFSET) +#define KINETIS_ADC1_CLP2 (KINETIS_ADC1_BASE+KINETIS_ADC_CLP2_OFFSET) +#define KINETIS_ADC1_CLP1 (KINETIS_ADC1_BASE+KINETIS_ADC_CLP1_OFFSET) +#define KINETIS_ADC1_CLP0 (KINETIS_ADC1_BASE+KINETIS_ADC_CLP0_OFFSET) +#define KINETIS_ADC1_PGA (KINETIS_ADC1_BASE+KINETIS_ADC_PGA_OFFSET) +#define KINETIS_ADC1_CLMD (KINETIS_ADC1_BASE+KINETIS_ADC_CLMD_OFFSET) +#define KINETIS_ADC1_CLMS (KINETIS_ADC1_BASE+KINETIS_ADC_CLMS_OFFSET) +#define KINETIS_ADC1_CLM4 (KINETIS_ADC1_BASE+KINETIS_ADC_CLM4_OFFSET) +#define KINETIS_ADC1_CLM3 (KINETIS_ADC1_BASE+KINETIS_ADC_CLM3_OFFSET) +#define KINETIS_ADC1_CLM2 (KINETIS_ADC1_BASE+KINETIS_ADC_CLM2_OFFSET) +#define KINETIS_ADC1_CLM1 (KINETIS_ADC1_BASE+KINETIS_ADC_CLM1_OFFSET) +#define KINETIS_ADC1_CLM0 (KINETIS_ADC1_BASE+KINETIS_ADC_CLM0_OFFSET) + +/* Register Bit Definitions *****************************************************************/ + +/* ADC status and control registers 1 */ + +#define ADC_SC1_ADCH_SHIFT (0) /* Bits 0-4: Input channel select */ +#define ADC_SC1_ADCH_MASK (31 << ADC_SC1_ADCH_SHIFT) +# define ADC_SC1_ADCH_DADP0 (0 << ADC_SC1_ADCH_SHIFT) /* DIFF=0 DADP0; DIFF=1, DAD0 */ +# define ADC_SC1_ADCH_DADP1 (1 << ADC_SC1_ADCH_SHIFT) /* DIFF=0 DADP1; DIFF=1, DAD1 */ +# define ADC_SC1_ADCH_DADP2 (2 << ADC_SC1_ADCH_SHIFT) /* DIFF=0 DADP2; DIFF=1, DAD2 */ +# define ADC_SC1_ADCH_DADP3 (3 << ADC_SC1_ADCH_SHIFT) /* DIFF=0 DADP3; DIFF=1, DAD3 */ +# define ADC_SC1_ADCH_AD4 (4 << ADC_SC1_ADCH_SHIFT) /* DIFF=0 AD4; DIFF=1 reserved */ +# define ADC_SC1_ADCH_AD5 (5 << ADC_SC1_ADCH_SHIFT) /* DIFF=0 AD5; DIFF=1 reserved */ +# define ADC_SC1_ADCH_AD6 (6 << ADC_SC1_ADCH_SHIFT) /* DIFF=0 AD6; DIFF=1 reserved */ +# define ADC_SC1_ADCH_AD7 (7 << ADC_SC1_ADCH_SHIFT) /* DIFF=0 AD7; DIFF=1 reserved */ +# define ADC_SC1_ADCH_AD8 (8 << ADC_SC1_ADCH_SHIFT) /* DIFF=0 AD8; DIFF=1 reserved */ +# define ADC_SC1_ADCH_AD9 (9 << ADC_SC1_ADCH_SHIFT) /* DIFF=0 AD9; DIFF=1 reserved */ +# define ADC_SC1_ADCH_AD10 (10 << ADC_SC1_ADCH_SHIFT) /* DIFF=0 AD10; DIFF=1 reserved */ +# define ADC_SC1_ADCH_AD11 (11 << ADC_SC1_ADCH_SHIFT) /* DIFF=0 AD11; DIFF=1 reserved */ +# define ADC_SC1_ADCH_AD12 (12 << ADC_SC1_ADCH_SHIFT) /* DIFF=0 AD12; DIFF=1 reserved */ +# define ADC_SC1_ADCH_AD13 (13 << ADC_SC1_ADCH_SHIFT) /* DIFF=0 AD13; DIFF=1 reserved */ +# define ADC_SC1_ADCH_AD14 (14 << ADC_SC1_ADCH_SHIFT) /* DIFF=0 AD14; DIFF=1 reserved */ +# define ADC_SC1_ADCH_AD15 (15 << ADC_SC1_ADCH_SHIFT) /* DIFF=0 AD15; DIFF=1 reserved */ +# define ADC_SC1_ADCH_AD16 (16 << ADC_SC1_ADCH_SHIFT) /* DIFF=0 AD16; DIFF=1 reserved */ +# define ADC_SC1_ADCH_AD17 (17 << ADC_SC1_ADCH_SHIFT) /* DIFF=0 AD17; DIFF=1 reserved */ +# define ADC_SC1_ADCH_AD18 (18 << ADC_SC1_ADCH_SHIFT) /* DIFF=0 AD18; DIFF=1 reserved */ +# define ADC_SC1_ADCH_AD19 (19 << ADC_SC1_ADCH_SHIFT) /* DIFF=0 AD19; DIFF=1 reserved */ +# define ADC_SC1_ADCH_AD20 (20 << ADC_SC1_ADCH_SHIFT) /* DIFF=0 AD20; DIFF=1 reserved */ +# define ADC_SC1_ADCH_AD21 (21 << ADC_SC1_ADCH_SHIFT) /* DIFF=0 AD21; DIFF=1 reserved */ +# define ADC_SC1_ADCH_AD22 (22 << ADC_SC1_ADCH_SHIFT) /* DIFF=0 AD22; DIFF=1 reserved */ +# define ADC_SC1_ADCH_AD23 (23 << ADC_SC1_ADCH_SHIFT) /* DIFF=0 AD23; DIFF=1 reserved */ +# define ADC_SC1_ADCH_TEMP (26 << ADC_SC1_ADCH_SHIFT) /* Temp sensor */ +# define ADC_SC1_ADCH_BANDGAP (27 << ADC_SC1_ADCH_SHIFT) /* Bandgap */ +# define ADC_SC1_ADCH_VREFSH (29 << ADC_SC1_ADCH_SHIFT) /* VREFSH */ +# define ADC_SC1_ADCH_VREFSL (30 << ADC_SC1_ADCH_SHIFT) /* DIFF=0 VREFSL; DIFF=1 reserved */ +# define ADC_SC1_ADCH_DISABLED (31 << ADC_SC1_ADCH_SHIFT) /* Module disabled */ +#define ADC_SC1_DIFF (1 << 5) /* Bit 5: Differential mode enable */ +#define ADC_SC1_AIEN (1 << 6) /* Bit 6: Interrupt enable */ +#define ADC_SC1_COCO (1 << 7) /* Bit 7: Conversion complete flag */ + /* Bits 8-31: Reserved */ +/* ADC configuration register 1 */ + +#define ADC_CFG1_ADICLK_SHIFT (0) /* Bits 0-1: Input clock select */ +#define ADC_CFG1_ADICLK_MASK (3 << ADC_CFG1_ADICLK_SHIFT) +# define ADC_CFG1_ADICLK_BUSCLK (0 << ADC_CFG1_ADICLK_SHIFT) /* Bus clock */ +# define ADC_CFG1_ADICLK_BUSDIV2 (1 << ADC_CFG1_ADICLK_SHIFT) /* Bus clock/ 2 */ +# define ADC_CFG1_ADICLK_ALTCLK (2 << ADC_CFG1_ADICLK_SHIFT) /* Alternate clock */ +# define ADC_CFG1_ADICLK_ADACK (3 << ADC_CFG1_ADICLK_SHIFT) /* Asynchronous clock */ +#define ADC_CFG1_MODE_SHIFT (2) /* Bits 2-3: Conversion mode selection */ +#define ADC_CFG1_MODE_MASK (3 << ADC_CFG1_MODE_SHIFT) +# define ADC_CFG1_MODE_89BIT (0 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 8-bit; DIFF=1 9-bit */ +# define ADC_CFG1_MODE_1213BIT (1 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 12-bit; DIFF=1 13-bit */ +# define ADC_CFG1_MODE_1011BIT (2 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 10-bit; DIFF=1 11-bit */ +# define ADC_CFG1_MODE_1616BIT (3 << ADC_CFG1_MODE_SHIFT) /* DIFF=0 16-bit; DIFF=1 16-bit */ +#define ADC_CFG1_ADLSMP (1 << 4) /* Bit 4: Sample time configuration */ +#define ADC_CFG1_ADIV_SHIFT (5) /* Bits 5-6: Clock divide select */ +#define ADC_CFG1_ADIV_MASK (3 << ADC_CFG1_ADIV_SHIFT) +# define ADC_CFG1_ADIV_DIV1 (0 << ADC_CFG1_ADIV_SHIFT) /* Divider=1 rate=input clock */ +# define ADC_CFG1_ADIV_DIV2 (1 << ADC_CFG1_ADIV_SHIFT) /* Divider=2 rate=input clock/2 */ +# define ADC_CFG1_ADIV_DIV4 (2 << ADC_CFG1_ADIV_SHIFT) /* Divider=4 rate=input clock/4 */ +# define ADC_CFG1_ADIV_DIV5 (3 << ADC_CFG1_ADIV_SHIFT) /* Divider=8 rate=input clock/8 */ +#define ADC_CFG1_ADLPC (1 << 7) /* Bit 7: Low-power configuration */ + /* Bits 8-31: Reserved */ +/* Configuration register 2 */ + +#define ADC_CFG2_ADLSTS_SHIFT (0) /* Bits 0-1: Long sample time select */ +#define ADC_CFG2_ADLSTS_MASK (3 << ADC_CFG2_ADLSTS_SHIFT) +# define ADC_CFG2_ADLSTS_LONGEST (0 << ADC_CFG2_ADLSTS_SHIFT) /* Default longest sample time */ +# define ADC_CFG2_ADLSTS_PLUS12 (1 << ADC_CFG2_ADLSTS_SHIFT) /* 12 extra ADCK cycles */ +# define ADC_CFG2_ADLSTS_PLUS6 (2 << ADC_CFG2_ADLSTS_SHIFT) /* 6 extra ADCK cycles */ +# define ADC_CFG2_ADLSTS_PLUS2 (3 << ADC_CFG2_ADLSTS_SHIFT) /* 2 extra ADCK cycles */ +#define ADC_CFG2_ADHSC (1 << 2) /* Bit 2: High speed configuration */ +#define ADC_CFG2_ADACKEN (1 << 3) /* Bit 3: Asynchronous clock output enable */ +#define ADC_CFG2_MUXSEL (1 << 4) /* Bit 4: ADC Mux select */ + /* Bits 5-31: Reserved */ +/* ADC data result register */ + +#define ADC_R_MASK (0xffff) /* 16-bit signed or unsigned data */ + +/* Compare value registers */ + +#define ADC_CV_MASK (0xffff) /* Compare value */ + +/* Status and control register 2 */ + +#define ADC_SC2_REFSEL_SHIFT (0) /* Bits 0-1: Voltage reference selection */ +#define ADC_SC2_REFSEL_MASK (3 << ADC_SC2_REFSEL_SHIFT) +# define ADC_SC2_REFSEL_DEFAULT (0 << ADC_SC2_REFSEL_SHIFT) /* Default reference: V REFH and V REFL */ +# define ADC_SC2_REFSEL_ALT (1 << ADC_SC2_REFSEL_SHIFT) /* Alternate reference: V ALTH and V ALTL */ +#define ADC_SC2_DMAEN (1 << 2) /* Bit 2: DMA enable */ +#define ADC_SC2_ACREN (1 << 3) /* Bit 3: Compare function range enable */ +#define ADC_SC2_ACFGT (1 << 4) /* Bit 4: Compare function greater than enable */ +#define ADC_SC2_ACFE (1 << 5) /* Bit 5: Compare function enable */ +#define ADC_SC2_ADTRG (1 << 6) /* Bit 6: Conversion trigger select */ +#define ADC_SC2_ADACT (1 << 7) /* Bit 7: Conversion active */ + /* Bits 8-31: Reserved */ +/* Status and control register 3 */ + +#define ADC_SC3_AVGS_SHIFT (0) /* Bits 0-1: Hardware average select */ +#define ADC_SC3_AVGS_MASK (3 << ADC_SC3_AVGS_SHIFT) +# define ADC_SC3_AVGS_4SAMPLS (0 << ADC_SC3_AVGS_SHIFT) /* 4 samples averaged */ +# define ADC_SC3_AVGS_8SAMPLS (1 << ADC_SC3_AVGS_SHIFT) /* 8 samples averaged */ +# define ADC_SC3_AVGS_16SAMPLS (2 << ADC_SC3_AVGS_SHIFT) /* 18 samples averaged */ +# define ADC_SC3_AVGS_32SAMPLS (3 << ADC_SC3_AVGS_SHIFT) /* 32 samples averaged */ +#define ADC_SC3_AVGE (1 << 2) /* Bit 2: Hardware average enable */ +#define ADC_SC3_ADCO (1 << 3) /* Bit 3: Continuous conversion enable */ + /* Bits 4-5: Reserved */ +#define ADC_SC3_CALF (1 << 6) /* Bit 6: Calibration failed flag */ +#define ADC_SC3_CAL (1 << 7) /* Bit 7: Calibration */ + /* Bits 8-31: Reserved */ +/* ADC offset correction register */ + +#define ADC_OFS_MASK (0xffff) /* Bits 0-15: Offset error correction value */ + +/* ADC plus-side gain register */ + +#define ADC_PG_MASK (0xffff) /* Bits 0-15: Plus-side gain */ + +/* ADC minus-side gain register */ + +#define ADC_MG_MASK (0xffff) /* Bits 0-15: Minus-side gain */ + +/* ADC plus-side general calibration value registers */ + +#define ADC_CLPD_MASK (0x3f) /* Bits 0-5: Calibration value */ +#define ADC_CLPS_MASK (0x3f) /* Bits 0-5: Calibration value */ +#define ADC_CLP4_MASK (0x3ff) /* Bits 0-9: Calibration value */ +#define ADC_CLP3_MASK (0x1ff) /* Bits 0-8: Calibration value */ +#define ADC_CLP2_MASK (0xff) /* Bits 0-7: Calibration value */ +#define ADC_CLP1_MASK (0x7f) /* Bits 0-6: Calibration value */ +#define ADC_CLP0_MASK (0x3f) /* Bits 0-5: Calibration value */ + +/* ADC PGA register */ + /* Bits 0-15: Reserved */ +#define ADC_PGA_PGAG_SHIFT (16) /* Bits 16-19: PGA gain setting*/ +#define ADC_PGA_PGAG_MASK (15 << ADC_PGA_PGAG_SHIFT) +# define ADC_PGA_PGAG_1 (0 << ADC_PGA_PGAG_SHIFT) +# define ADC_PGA_PGAG_2 (1 << ADC_PGA_PGAG_SHIFT) +# define ADC_PGA_PGAG_4 (2 << ADC_PGA_PGAG_SHIFT) +# define ADC_PGA_PGAG_8 (3 << ADC_PGA_PGAG_SHIFT) +# define ADC_PGA_PGAG_16 (4 << ADC_PGA_PGAG_SHIFT) +# define ADC_PGA_PGAG_32 (5 << ADC_PGA_PGAG_SHIFT) +# define ADC_PGA_PGAG_64 (6 << ADC_PGA_PGAG_SHIFT) +#define ADC_PGA_PGALP (1 << 20) /* Bit 20: PGA low-power mode control*/ + /* Bits 21-22: Reserved */ +#define ADC_PGA_PGAEN (1 << 23) /* Bit 23: PGA enable*/ + /* Bits 24-31: Reserved */ +/* ADC minus-side general calibration value registers */ + +#define ADC_CLMD_MASK (0x3f) /* Bits 0-5: Calibration value */ +#define ADC_CLMS_MASK (0x3f) /* Bits 0-5: Calibration value */ +#define ADC_CLM4_MASK (0x3ff) /* Bits 0-9: Calibration value */ +#define ADC_CLM3_MASK (0x1ff) /* Bits 0-8: Calibration value */ +#define ADC_CLM2_MASK (0xff) /* Bits 0-7: Calibration value */ +#define ADC_CLM1_MASK (0x7f) /* Bits 0-6: Calibration value */ +#define ADC_CLM0_MASK (0x3f) /* Bits 0-5: Calibration value */ + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +/******************************************************************************************** + * Public Data + ********************************************************************************************/ + +/******************************************************************************************** + * Public Functions + ********************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_ADC_H */ diff --git a/arch/arm/src/kinetis/kinetis_crc.h b/arch/arm/src/kinetis/kinetis_crc.h index 6b309533b1..88e20f64c0 100644 --- a/arch/arm/src/kinetis/kinetis_crc.h +++ b/arch/arm/src/kinetis/kinetis_crc.h @@ -44,6 +44,8 @@ #include "chip.h" +#if defined(KINETIS_NCRC) && KINETIS_NCRC > 0 + /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ @@ -111,4 +113,5 @@ * Public Functions ************************************************************************************/ +#endif /* KINETIS_NCRC && KINETIS_NCRC > 0 */ #endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_CRC_H */ diff --git a/arch/arm/src/kinetis/kinetis_mmcau.h b/arch/arm/src/kinetis/kinetis_mmcau.h new file mode 100644 index 0000000000..f1ba0e7690 --- /dev/null +++ b/arch/arm/src/kinetis/kinetis_mmcau.h @@ -0,0 +1,138 @@ +/************************************************************************************ + * arch/arm/src/kinetis/kinetis_mmcau.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_MMCAU_H +#define __ARCH_ARM_SRC_KINETIS_KINETIS_MMCAU_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" + +#if defined(KINETIS_NMMCAU) && KINETIS_NMMCAU > 0 + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Register Offsets *****************************************************************/ + +#define KINETIS_CAU_CASR_OFFSET 0x0000 /* Status Register */ +#define KINETIS_CAU_CAA_OFFSET 0x0001 /* Accumulator */ + +#define KINETIS_CAU_CA_OFFSET(n) ((n)+2) /* General Purpose Register n */ +#define KINETIS_CAU_CA0_OFFSET 0x0002 /* General Purpose Register 0 */ +#define KINETIS_CAU_CA1_OFFSET 0x0003 /* General Purpose Register 1 */ +#define KINETIS_CAU_CA2_OFFSET 0x0004 /* General Purpose Register 2 */ +#define KINETIS_CAU_CA3_OFFSET 0x0005 /* General Purpose Register 3 */ +#define KINETIS_CAU_CA4_OFFSET 0x0006 /* General Purpose Register 4 */ +#define KINETIS_CAU_CA5_OFFSET 0x0007 /* General Purpose Register 5 */ +#define KINETIS_CAU_CA6_OFFSET 0x0008 /* General Purpose Register 6 */ +#define KINETIS_CAU_CA7_OFFSET 0x0009 /* General Purpose Register 7 */ +#define KINETIS_CAU_CA8_OFFSET 0x000a /* General Purpose Register 8 */ + +/* Register Addresses ***************************************************************/ + +#define KINETIS_CAU_CASR (KINETIS_MMCAU_BASE+KINETIS_CAU_CASR_OFFSET) +#define KINETIS_CAU_CAA (KINETIS_MMCAU_BASE+KINETIS_CAU_CAA_OFFSET) + +#define KINETIS_CAU_CA(n) (KINETIS_MMCAU_BASE+KINETIS_CAU_CA_OFFSET(n)) +#define KINETIS_CAU_CA0 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA0_OFFSET) +#define KINETIS_CAU_CA1 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA1_OFFSET) +#define KINETIS_CAU_CA2 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA2_OFFSET) +#define KINETIS_CAU_CA3 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA3_OFFSET) +#define KINETIS_CAU_CA4 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA4_OFFSET) +#define KINETIS_CAU_CA5 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA5_OFFSET) +#define KINETIS_CAU_CA6 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA6_OFFSET) +#define KINETIS_CAU_CA7 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA7_OFFSET) +#define KINETIS_CAU_CA8 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA8_OFFSET) + +/* Register Bit Definitions *********************************************************/ + +/* Status Register */ + +#define CAU_CASR_IC (1 << 0) /* Bit 0: Illegal command */ +#define CAU_CASR_DPE (1 << 1) /* Bit 1: DES parity error */ + /* Bits 2-27: Reserved */ +#define CAU_CASR_VER_SHIFT (28) /* Bits 28-31: CAU version */ +#define CAU_CASR_VER_MASK (15 << CAU_CASR_VER_SHIFT) + +/* Accumulator (32-bit accumulated value)*/ +/* General Purpose Register n (32-bit value used by CAU commands) */ + +/* CAU Commands *********************************************************************/ + +/* Bits 4-8 of 9-bit commands (bits 0-3 may be arguments of the command) */ + +#define CAU_CMD_CNOP 0x000 /* No Operation */ +#define CAU_CMD_LDR 0x010 /* Load Reg */ +#define CAU_CMD_STR 0x020 /* Store Reg */ +#define CAU_CMD_ADR 0x030 /* Add */ +#define CAU_CMD_RADR 0x040 /* Reverse and Add */ +#define CAU_CMD_ADRA 0x050 /* Add Reg to Acc */ +#define CAU_CMD_XOR 0x060 /* Exclusive Or */ +#define CAU_CMD_ROTL 0x070 /* Rotate Left */ +#define CAU_CMD_MVRA 0x080 /* Move Reg to Acc */ +#define CAU_CMD_MVAR 0x090 /* Move Acc to Reg */ +#define CAU_CMD_AESS 0x0a0 /* AES Sub Bytes */ +#define CAU_CMD_AESIS 0x0b0 /* AES Inv Sub Bytes */ +#define CAU_CMD_AESC 0x0c0 /* AES Column Op */ +#define CAU_CMD_AESIC 0x0d0 /* AES Inv Column Op */ +#define CAU_CMD_AESR 0x0e0 /* AES Shift Rows */ +#define CAU_CMD_AESIR 0x0f0 /* AES Inv Shift Rows */ +#define CAU_CMD_DESR 0x100 /* DES Round */ +#define CAU_CMD_DESK 0x110 /* DES Key Setup */ +#define CAU_CMD_HASH 0x120 /* Hash Function */ +#define CAU_CMD_SHS 0x130 /* Secure Hash Shift */ +#define CAU_CMD_MDS 0x140 /* Message Digest Shift */ +#define CAU_CMD_SHS2 0x150 /* Secure Hash Shift 2 */ +#define CAU_CMD_ILL 0x1f0 /* Illegal Command */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* KINETIS_NMMCAU && KINETIS_NMMCAU > 0 */ +#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_MMCAU_H */ diff --git a/arch/arm/src/kinetis/kinetis_rngb.h b/arch/arm/src/kinetis/kinetis_rngb.h new file mode 100644 index 0000000000..f55b37843e --- /dev/null +++ b/arch/arm/src/kinetis/kinetis_rngb.h @@ -0,0 +1,161 @@ +/************************************************************************************ + * arch/arm/src/kinetis/kinetis_rngb.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt <spudmonkey@racsa.co.cr> + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_RNGB_H +#define __ARCH_ARM_SRC_KINETIS_KINETIS_RNGB_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include <nuttx/config.h> + +#include "chip.h" + +#if defined(KINETIS_NRNG) && KINETIS_NRNG > 0 + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define KINETIS_RNG_VER_OFFSET 0x0000 /* RNGB Version ID Register */ +#define KINETIS_RNG_CMD_OFFSET 0x0004 /* RNGB Command Register */ +#define KINETIS_RNG_CR_OFFSET 0x0008 /* RNGB Control Register */ +#define KINETIS_RNG_SR_OFFSET 0x000c /* RNGB Status Register */ +#define KINETIS_RNG_ESR_OFFSET 0x0010 /* RNGB Error Status Register */ +#define KINETIS_RNG_OUT_OFFSET 0x0014 /* RNGB Output FIFO */ + +/* Register Addresses ***************************************************************/ + +#define KINETIS_RNG_VER (KINETIS_RNGB_BASE+KINETIS_RNG_VER_OFFSET) +#define KINETIS_RNG_CMD (KINETIS_RNGB_BASE+KINETIS_RNG_CMD_OFFSET) +#define KINETIS_RNG_CR (KINETIS_RNGB_BASE+KINETIS_RNG_CR_OFFSET) +#define KINETIS_RNG_SR (KINETIS_RNGB_BASE+KINETIS_RNG_SR_OFFSET) +#define KINETIS_RNG_ESR (KINETIS_RNGB_BASE+KINETIS_RNG_ESR_OFFSET) +#define KINETIS_RNG_OUT (KINETIS_RNGB_BASE+KINETIS_RNG_OUT_OFFSET) + +/* Register Bit Definitions *********************************************************/ + +/* RNGB Version ID Register */ + +#define RNG_VER_MINOR_SHIFT (0) /* Bits 0-7: Minor version number */ +#define RNG_VER_MINOR_MASK (0xff << RNG_VER_MINOR_SHIFT) +#define RNG_VER_MAJOR_SHIFT (8) /* Bits 8-15: Major version number */ +#define RNG_VER_MAJOR_MASK (0xff << RNG_VER_MAJOR_SHIFT) + /* Bits 27�16: Reserved */ +#define RNG_VER_TYPE_SHIFT (28) /* Bits 28-31: Random number generator type */ +#define RNG_VER_TYPE_MASK (15 << RNG_VER_TYPE_SHIFT) +# define RNG_VER_TYPE_RNGA (0 << RNG_VER_TYPE_SHIFT) +# define RNG_VER_TYPE_RNGB (1 << RNG_VER_TYPE_SHIFT) +# define RNG_VER_TYPE_RNGC (2 << RNG_VER_TYPE_SHIFT) + +/* RNGB Command Register */ + +#define RNG_CMD_ST (1 << 0) /* Bit 0: Self test */ +#define RNG_CMD_GS (1 << 1) /* Bit 1: Generate seed */ + /* Bits 2-3: Reserved */ +#define RNG_CMD_CI (1 << 4) /* Bit 4: Clear interrupt */ +#define RNG_CMD_CE (1 << 5) /* Bit 5: Clear error */ +#define RNG_CMD_SR (1 << 6) /* Bit 6: Software reset */ + /* Bits 7-31: Reserved */ +/* RNGB Control Register */ + +#define RNG_CR_FUFMOD_SHIFT (0) /* Bits 0-1: FIFO underflow response mode */ +#define RNG_CR_FUFMOD_MASK (3 << RNG_CR_FUFMOD_SHIFT) +# define RNG_CR_FUFMOD_ZEROS (0 << RNG_CR_FUFMOD_SHIFT) /* Return zeros, set RNG_ESR[FUFE] */ +# define RNG_CR_FUFMOD_ERROR (2 << RNG_CR_FUFMOD_SHIFT) /* Generate bus transfer error */ +# define RNG_CR_FUFMOD_INT (3 << RNG_CR_FUFMOD_SHIFT) /* Generate interrupt, return zeros */ + /* Bits 2-3: Reserved */ +#define RNG_CR_AR (1 << 4) /* Bit 4: Auto-reseed */ +#define RNG_CR_MASKDONE (1 << 5) /* Bit 5: Mask done interrupt */ +#define RNG_CR_MASKERR (1 << 6) /* Bit 6: Mask error interrupt */ + /* Bits 7-31: Reserved */ +/* RNGB Status Register */ + /* Bit 0: Reserved */ +#define RNG_SR_BUSY (1 << 1) /* Bit 1: Busy */ +#define RNG_SR_SLP (1 << 2) /* Bit 2: Sleep */ +#define RNG_SR_RS (1 << 3) /* Bit 3: Reseed needed */ +#define RNG_SR_STDN (1 << 4) /* Bit 4: Self test done */ +#define RNG_SR_SDN (1 << 5) /* Bit 5: Seed done */ +#define RNG_SR_NSDN (1 << 6) /* Bit 6: New seed done */ + /* Bit 7: Reserved */ +#define RNG_SR_FIFO_LVL_SHIFT (8) /* Bits 8-11: FIFO level */ +#define RNG_SR_FIFO_LVL_MASK (15 << RNG_SR_FIFO_LVL_SHIFT) +#define RNG_SR_FIFO_SIZE_SHIFT (12) /* Bits 12-15: FIFO size */ +#define RNG_SR_FIFO_SIZE_MASK (15 << RNG_SR_FIFO_SIZE_SHIFT) +#define RNG_SR_ERR (1 << 16) /* Bit 16: Error */ + /* Bits 17-20: Reserved */ +#define RNG_SR_ST_PF_SHIFT (21) /* Bits 21-23: Self Test Pass Fail */ +#define RNG_SR_ST_PF_MASK (7 << RNG_SR_ST_PF_SHIFT) +# define RNG_SR_ST_PF_TRNG (4 << RNG_SR_ST_PF_SHIFT) /* TRNG self test pass/fail */ +# define RNG_SR_ST_PF_PRNG (2 << RNG_SR_ST_PF_SHIFT) /* PRNG self test pass/fail */ +# define RNG_SR_ST_PF_RESEED (1 << RNG_SR_ST_PF_SHIFT) /* RESEED self test pass/fail */ +#define RNG_SR_STATPF_SHIFT (24) /* Bits 24-31: Statistics test pass fail */ +#define RNG_SR_STATPF_MASK (0xff << RNG_SR_STATPF_SHIFT) +# define RNG_SR_STATPF_LONG (0x80 << RNG_SR_STATPF_SHIFT) /* Long run test (>34) */ +# define RNG_SR_STATPF_LEN6 (0x40 << RNG_SR_STATPF_SHIFT) /* Length 6+ run test */ +# define RNG_SR_STATPF_LEN5 (0x20 << RNG_SR_STATPF_SHIFT) /* Length 5 run test */ +# define RNG_SR_STATPF_LEN4 (0x10 << RNG_SR_STATPF_SHIFT) /* Length 4 run test */ +# define RNG_SR_STATPF_LEN3 (0x08 << RNG_SR_STATPF_SHIFT) /* Length 3 run test */ +# define RNG_SR_STATPF_LEN2 (0x04 << RNG_SR_STATPF_SHIFT) /* Length 2 run test */ +# define RNG_SR_STATPF_LEN1 (0x02 << RNG_SR_STATPF_SHIFT) /* Length 1 run test */ +# define RNG_SR_STATPF_MONO (0x01 << RNG_SR_STATPF_SHIFT) /* Monobit test */ + +/* RNGB Error Status Register */ + +#define RNG_ESR_LFE (1 << 0) /* Bit 0: Linear feedback shift register (LFSR) error */ +#define RNG_ESR_OSCE (1 << 1) /* Bit 1: Oscillator error */ +#define RNG_ESR_STE (1 << 2) /* Bit 2: Self test error */ +#define RNG_ESR_SATE (1 << 3) /* Bit 3: Statistical test error */ +#define RNG_ESR_FUFE (1 << 4) /* Bit 4: FIFO underflow error */ + /* Bits 5-31: Reserved */ +/* RNGB Output FIFO (32-bit random output) */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* KINETIS_NRNG && KINETIS_NRNG > 0 */ +#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_RNGB_H */ diff --git a/arch/arm/src/kinetis/kinetis_rtc.h b/arch/arm/src/kinetis/kinetis_rtc.h index 8c97bd00eb..2a3c57e59d 100644 --- a/arch/arm/src/kinetis/kinetis_rtc.h +++ b/arch/arm/src/kinetis/kinetis_rtc.h @@ -44,6 +44,8 @@ #include "chip.h" +#if defined(KINETIS_NRTC) && KINETIS_NRTC > 0 + /************************************************************************************ * Pre-processor Definitions ************************************************************************************/ @@ -201,4 +203,5 @@ * Public Functions ************************************************************************************/ +#endif /* KINETIS_NRTC && KINETIS_NRTC > 0 */ #endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_RTC_H */ -- GitLab