diff --git a/arch/arm/src/sam3u/Make.defs b/arch/arm/src/sam3u/Make.defs
index 66a6ad75646704e12a35d157dc72458b1e66d761..dd66295be1cb1bcbc2b8373da8a34c896b29fe33 100755
--- a/arch/arm/src/sam3u/Make.defs
+++ b/arch/arm/src/sam3u/Make.defs
@@ -45,5 +45,6 @@ CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
up_usestack.c up_doirq.c up_hardfault.c up_svcall.c
CHIP_ASRCS =
-CHIP_CSRCS = sam3u_irq.c sam3u_start.c
+CHIP_CSRCS = sam3u_clockconfig.c sam3u_irq.c sam3u_lowputc.c sam3u_start.c \
+ sam3u_timerisr.c
diff --git a/arch/arm/src/sam3u/sam3u_clockconfig.c b/arch/arm/src/sam3u/sam3u_clockconfig.c
new file mode 100755
index 0000000000000000000000000000000000000000..6ff3c8329b7f1a4687a2473ecbca6dfe6520ea01
--- /dev/null
+++ b/arch/arm/src/sam3u/sam3u_clockconfig.c
@@ -0,0 +1,308 @@
+/****************************************************************************
+ * arch/arm/src/sam3u/sam3u_clockconfig.c
+ * arch/arm/src/chip/sam3u_clockconfig.c
+ *
+ * Copyright (C) 2010 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "up_internal.h"
+#include "sam3u_internal.h"
+#include "sam3u_pmc.h"
+#include "sam3u_eefc.h"
+#include "sam3u_wdt.h"
+#include "sam3u_supc.h"
+#include "sam3u_matrix.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* PMC register settings based on the board configuration values defined
+ * in board.h
+ */
+
+#define CKGR_MOR_KEY (0x37 << CKGR_MOR_KEY_SHIFT)
+#define SUPR_CR_KEY (0xa5 << SUPC_CR_KEY_SHIFT)
+
+#define BOARD_CKGR_MOR (CKGR_MOR_KEY|BOARD_CKGR_MOR_MOSCXTST|\
+ CKGR_MOR_MOSCRCEN|CKGR_MOR_MOSCXTEN)
+
+#define BOARD_CKGR_PLLAR (CKGR_PLLAR_ONE|BOARD_CKGR_PLLAR_MULA|\
+ BOARD_CKGR_PLLAR_STMODE|BOARD_CKGR_PLLAR_PLLACOUNT|\
+ BOARD_CKGR_PLLAR_DIVA)
+
+#define BOARD_PMC_MCKR_FAST (BOARD_PMC_MCKR_PRES|PMC_MCKR_CSS_MAIN)
+#define BOARD_PMC_MCKR (BOARD_PMC_MCKR_PRES|BOARD_PMC_MCKR_CSS)
+
+#define BOARD_CKGR_UCKR (BOARD_CKGR_UCKR_UPLLCOUNT|CKGR_UCKR_UPLLEN)
+
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: sam3u_efcsetup
+ *
+ * Description:
+ * Configure 2 waitstates for embedded flash access
+ *
+ ****************************************************************************/
+
+static inline void sam3u_efcsetup(void)
+{
+ putreg32((2 << EEFC_FMR_FWS_SHIFT), SAM3U_EEFC0_FMR);
+ putreg32((2 << EEFC_FMR_FWS_SHIFT), SAM3U_EEFC1_FMR);
+}
+
+/****************************************************************************
+ * Name: sam3u_wdtsetup
+ *
+ * Description:
+ * Disable the watchdog timer
+ *
+ ****************************************************************************/
+
+static inline void sam3u_wdtsetup(void)
+{
+ putreg32(WDT_MR_WDDIS, SAM3U_WDT_MR);
+}
+
+/****************************************************************************
+ * Name: sam3u_supcsetup
+ *
+ * Description:
+ * Select the external slow clock
+ *
+ ****************************************************************************/
+
+static inline void sam3u_supcsetup(void)
+{
+ /* Check if the 32-kHz is already selected */
+
+ if ((getreg32(SAM3U_SUPC_SR) & SUPC_SR_OSCSEL) == 0)
+ {
+ uint32_t delay;
+ putreg32((SUPC_CR_XTALSEL|SUPR_CR_KEY), SAM3U_SUPC_CR);
+ for (delay = 0;
+ (getreg32(SAM3U_SUPC_SR) & SUPC_SR_OSCSEL) == 0 && delay < UINT32_MAX;
+ delay++);
+ }
+}
+
+/****************************************************************************
+ * Name: sam3u_pmcwait
+ *
+ * Description:
+ * Initialize clocking
+ *
+ ****************************************************************************/
+
+static void sam3u_pmcwait(uint32_t bit)
+{
+ uint32_t delay;
+ for (delay = 0;
+ (getreg32(SAM3U_PMC_SR) & bit) == 0 && delay < UINT32_MAX;
+ delay++);
+}
+
+/****************************************************************************
+ * Name: sam3u_pmcsetup
+ *
+ * Description:
+ * Initialize clocking
+ *
+ ****************************************************************************/
+
+static inline void sam3u_pmcsetup(void)
+{
+ uint32_t regval;
+
+ /* Initialize main oscillator (if it has not already been selected */
+
+ if ((getreg32(SAM3U_CKGR_MOR) & CKGR_MOR_MOSCSEL) == 0)
+ {
+ putreg32(BOARD_CKGR_MOR, SAM3U_CKGR_MOR);
+ sam3u_pmcwait(PMC_INT_MOSCXTS);
+ }
+
+ /* Switch to the main oscillator */
+
+ putreg32((BOARD_CKGR_MOR|CKGR_MOR_MOSCSEL), SAM3U_CKGR_MOR);
+ sam3u_pmcwait(PMC_INT_MOSCSELS);
+
+ regval = getreg32(SAM3U_PMC_MCKR);
+ regval &= ~PMC_MCKR_CSS_MASK;
+ regval |= PMC_MCKR_CSS_MAIN;
+ putreg32(regval, SAM3U_PMC_MCKR);
+ sam3u_pmcwait(PMC_INT_MCKRDY);
+
+ /* Settup PLLA */
+
+ putreg32(BOARD_CKGR_PLLAR, SAM3U_CKGR_PLLAR);
+ sam3u_pmcwait(PMC_INT_LOCKA);
+
+ /* Setup UTMI for USB */
+
+#ifdef CONFIG_USBDEV
+ regval = getreg32(SAM3U_CKGR_UCKR);
+ regval |= BOARD_CKGR_UCKR;
+ putreg32(regval, SAM3U_CKGR_UCKR);
+ sam3u_pmcwait(PMC_INT_LOCKU);
+#endif
+
+ /* Switch to the fast clock */
+
+ putreg32(BOARD_PMC_MCKR_FAST, SAM3U_PMC_MCKR);
+ sam3u_pmcwait(PMC_INT_MCKRDY);
+
+ putreg32(BOARD_PMC_MCKR, SAM3U_PMC_MCKR);
+ sam3u_pmcwait(PMC_INT_MCKRDY);
+}
+
+/****************************************************************************
+ * Name: sam3u_enabledefaultmaster and sam3u_disabledefaultmaster
+ *
+ * Description:
+ * Enable/disable default master access
+ *
+ ****************************************************************************/
+
+static inline void sam3u_enabledefaultmaster(void)
+{
+ uint32_t regval;
+
+ /* Set default master: SRAM0 -> Cortex-M3 System */
+
+ regval = getreg32(SAM3U_MATRIX_SCFG0);
+ regval |= (MATRIX_SCFG0_FIXEDDEFMSTR_ARMS|MATRIX_SCFG_DEFMSTRTYPE_FIXED);
+ putreg32(regval, SAM3U_MATRIX_SCFG0);
+
+ /* Set default master: SRAM1 -> Cortex-M3 System */
+
+ regval = getreg32(SAM3U_MATRIX_SCFG1);
+ regval |= (MATRIX_SCFG1_FIXEDDEFMSTR_ARMS|MATRIX_SCFG_DEFMSTRTYPE_FIXED);
+ putreg32(regval, SAM3U_MATRIX_SCFG1);
+
+ /* Set default master: Internal flash0 -> Cortex-M3 Instruction/Data */
+
+ regval = getreg32(SAM3U_MATRIX_SCFG3);
+ regval |= (MATRIX_SCFG3_FIXEDDEFMSTR_ARMC|MATRIX_SCFG_DEFMSTRTYPE_FIXED);
+ putreg32(regval, SAM3U_MATRIX_SCFG3);
+}
+
+#if 0 /* Not used */
+static inline void sam3u_disabledefaultmaster(void)
+{
+ uint32_t regval;
+
+ /* Clear default master: SRAM0 -> Cortex-M3 System */
+
+ regval = getreg32(SAM3U_MATRIX_SCFG0);
+ regval &= ~MATRIX_SCFG_DEFMSTRTYPE_MASK;
+ putreg32(regval, SAM3U_MATRIX_SCFG0);
+
+ /* Clear default master: SRAM1 -> Cortex-M3 System */
+
+ regval = getreg32(SAM3U_MATRIX_SCFG1);
+ regval &= ~MATRIX_SCFG_DEFMSTRTYPE_MASK;
+ putreg32(regval, SAM3U_MATRIX_SCFG1);
+
+ /* Clear default master: Internal flash0 -> Cortex-M3 Instruction/Data */
+
+ regval = getreg32(SAM3U_MATRIX_SCFG3);
+ regval &= ~MATRIX_SCFG_DEFMSTRTYPE_MASK;
+ putreg32(regval, SAM3U_MATRIX_SCFG3);
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/************************************************************************************
+ * Name: sam3u_clockconfig
+ *
+ * Description:
+ * Called to initialize the SAM3U. This does whatever setup is needed to put the
+ * SoC in a usable state. This includes the initialization of clocking using the
+ * settings in board.h. (After power-on reset, the sam3u is initiallyrunning on
+ * a 4MHz internal RC clock). This function also performs other low-level chip
+ * initialization of the chip including EFC, master clock, IRQ & watchdog
+ * configuration.
+ *
+ ************************************************************************************/
+
+void sam3u_clockconfig(void)
+{
+ /* Configure embedded flash access */
+
+ sam3u_efcsetup();
+
+ /* Configure the watchdog timer */
+
+ sam3u_wdtsetup();
+
+ /* Setup the supply controller to use the external slow clock */
+
+ sam3u_supcsetup();
+
+ /* Initialize clocking */
+
+ sam3u_pmcsetup();
+
+ /* Optimize CPU setting for speed */
+
+ sam3u_enabledefaultmaster();
+}
+
diff --git a/arch/arm/src/sam3u/sam3u_internal.h b/arch/arm/src/sam3u/sam3u_internal.h
index a0ea45f028f66c4cc1063c5b14063696aef9f317..3eace01ceaeaec36a2293276ed815212f485b35e 100755
--- a/arch/arm/src/sam3u/sam3u_internal.h
+++ b/arch/arm/src/sam3u/sam3u_internal.h
@@ -1,7 +1,7 @@
/************************************************************************************
* arch/arm/src/sam3u/sam3u_internal.h
*
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@@ -84,24 +84,31 @@ extern "C" {
************************************************************************************/
/************************************************************************************
- * Name: sam3u_lowsetup
+ * Name: sam3u_clockconfig
*
* Description:
- * Called at the very beginning of _start. Performs low level initialization.
+ * Called to initialize the SAM3U. This does whatever setup is needed to put the
+ * SoC in a usable state. This includes the initialization of clocking using the
+ * settings in board.h. (After power-on reset, the sam3u is initiallyrunning on
+ * a 4MHz internal RC clock). This function also performs other low-level chip
+ * initialization of the chip including EFC, master clock, IRQ and watchdog
+ * configuration.
*
************************************************************************************/
-EXTERN void sam3u_lowsetup(void);
+EXTERN void sam3u_clockconfig(void);
/************************************************************************************
- * Name: sam3u_clockconfig
+ * Name: sam3u_lowsetup
*
* Description:
- * Called to change to new clock based on settings in board.h
+ * Called at the very beginning of _start. Performs low level initialization
+ * including setup of the console UART. This UART done early so that the serial
+ * console is available for debugging very early in the boot sequence.
*
************************************************************************************/
-EXTERN void sam3u_clockconfig(void);
+EXTERN void sam3u_lowsetup(void);
#undef EXTERN
#if defined(__cplusplus)
diff --git a/arch/arm/src/sam3u/sam3u_lowputc.c b/arch/arm/src/sam3u/sam3u_lowputc.c
new file mode 100755
index 0000000000000000000000000000000000000000..399950a8391ca1c5de6e96f6ae32d5ddeca2db87
--- /dev/null
+++ b/arch/arm/src/sam3u/sam3u_lowputc.c
@@ -0,0 +1,208 @@
+/**************************************************************************
+ * arch/arm/src/sam3u/sam3u_lowputc.c
+ *
+ * Copyright (C) 2010 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ **************************************************************************/
+
+/**************************************************************************
+ * Included Files
+ **************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+#include <arch/irq.h>
+#include <arch/board/board.h>
+
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "sam3u_internal.h"
+#include "sam3u_pmc.h"
+
+/**************************************************************************
+ * Private Definitions
+ **************************************************************************/
+
+/* Configuration **********************************************************/
+
+#ifndef CONFIG_USART0_ISUART
+# undef CONFIG_SAM3U_USART0
+#endif
+#ifndef CONFIG_USART1_ISUART
+# undef CONFIG_SAM3U_USART1
+#endif
+#ifndef CONFIG_USART2_ISUART
+# undef CONFIG_SAM3U_USART2
+#endif
+#ifndef CONFIG_USART3_ISUART
+# undef CONFIG_SAM3U_USART3
+#endif
+
+/* Is there a serial console? It could be on the UART, or USARTn */
+
+#if defined(CONFIG_UART_SERIAL_CONSOLE) && defined(CONFIG_SAM3U_UART)
+# undef CONFIG_USART0_SERIAL_CONSOLE
+# undef CONFIG_USART1_SERIAL_CONSOLE
+# undef CONFIG_USART2_SERIAL_CONSOLE
+# undef CONFIG_USART3_SERIAL_CONSOLE
+# define HAVE_CONSOLE 1
+#elif defined(CONFIG_USART0_SERIAL_CONSOLE) && defined(CONFIG_SAM3U_USART0)
+# undef CONFIG_USART_SERIAL_CONSOLE
+# undef CONFIG_USART1_SERIAL_CONSOLE
+# undef CONFIG_USART2_SERIAL_CONSOLE
+# undef CONFIG_USART3_SERIAL_CONSOLE
+# define HAVE_CONSOLE 1
+#elif defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_SAM3U_USART1)
+# undef CONFIG_USART_SERIAL_CONSOLE
+# undef CONFIG_USART0_SERIAL_CONSOLE
+# undef CONFIG_USART2_SERIAL_CONSOLE
+# undef CONFIG_USART3_SERIAL_CONSOLE
+# define HAVE_CONSOLE 1
+#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_SAM3U_USART2)
+# undef CONFIG_USART_SERIAL_CONSOLE
+# undef CONFIG_USART0_SERIAL_CONSOLE
+# undef CONFIG_USART1_SERIAL_CONSOLE
+# undef CONFIG_USART3_SERIAL_CONSOLE
+# define HAVE_CONSOLE 1
+#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_SAM3U_USART3)
+# undef CONFIG_USART_SERIAL_CONSOLE
+# undef CONFIG_USART0_SERIAL_CONSOLE
+# undef CONFIG_USART1_SERIAL_CONSOLE
+# undef CONFIG_USART2_SERIAL_CONSOLE
+# define HAVE_CONSOLE 1
+#else
+# undef CONFIG_USART_SERIAL_CONSOLE
+# undef CONFIG_USART0_SERIAL_CONSOLE
+# undef CONFIG_USART1_SERIAL_CONSOLE
+# undef CONFIG_USART2_SERIAL_CONSOLE
+# undef CONFIG_USART3_SERIAL_CONSOLE
+# undef HAVE_CONSOLE
+#endif
+
+/* Select USART parameters for the selected console */
+
+#if defined(CONFIG_UART_SERIAL_CONSOLE)
+# define SAM3U_CONSOLE_BASE SAM3U_UART_BASE
+# define SAM3U_CONSOLE_BAUD CONFIG_USART_BAUD
+# define SAM3U_CONSOLE_BITS CONFIG_USART_BITS
+# define SAM3U_CONSOLE_PARITY CONFIG_USART_PARITY
+# define SAM3U_CONSOLE_2STOP CONFIG_USART_2STOP
+#elif defined(CONFIG_USART0_SERIAL_CONSOLE)
+# define SAM3U_CONSOLE_BASE SAM3U_USART0_BASE
+# define SAM3U_CONSOLE_BAUD CONFIG_USART0_BAUD
+# define SAM3U_CONSOLE_BITS CONFIG_USART0_BITS
+# define SAM3U_CONSOLE_PARITY CONFIG_USART0_PARITY
+# define SAM3U_CONSOLE_2STOP CONFIG_USART0_2STOP
+#elif defined(CONFIG_USART1_SERIAL_CONSOLE)
+# define SAM3U_CONSOLE_BASE SAM3U_USART1_BASE
+# define SAM3U_CONSOLE_BAUD CONFIG_USART1_BAUD
+# define SAM3U_CONSOLE_BITS CONFIG_USART1_BITS
+# define SAM3U_CONSOLE_PARITY CONFIG_USART1_PARITY
+# define SAM3U_CONSOLE_2STOP CONFIG_USART1_2STOP
+#elif defined(CONFIG_USART2_SERIAL_CONSOLE)
+# define SAM3U_CONSOLE_BASE SAM3U_USART2_BASE
+# define SAM3U_CONSOLE_BAUD CONFIG_USART2_BAUD
+# define SAM3U_CONSOLE_BITS CONFIG_USART2_BITS
+# define SAM3U_CONSOLE_PARITY CONFIG_USART2_PARITY
+# define SAM3U_CONSOLE_2STOP CONFIG_USART2_2STOP
+#elif defined(CONFIG_USART3_SERIAL_CONSOLE)
+# define SAM3U_CONSOLE_BASE SAM3U_USART3_BASE
+# define SAM3U_CONSOLE_BAUD CONFIG_USART3_BAUD
+# define SAM3U_CONSOLE_BITS CONFIG_USART3_BITS
+# define SAM3U_CONSOLE_PARITY CONFIG_USART3_PARITY
+# define SAM3U_CONSOLE_2STOP CONFIG_USART3_2STOP
+#else
+# error "No CONFIG_U[S]ARTn_SERIAL_CONSOLE Setting"
+#endif
+
+/**************************************************************************
+ * Private Types
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Function Prototypes
+ **************************************************************************/
+
+/**************************************************************************
+ * Global Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Public Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Name: up_lowputc
+ *
+ * Description:
+ * Output one byte on the serial console
+ *
+ **************************************************************************/
+
+void up_lowputc(char ch)
+{
+#warning "To be provided"
+}
+
+/**************************************************************************
+ * Name: sam3u_lowsetup
+ *
+ * Description:
+ * This performs basic initialization of the USART used for the serial
+ * console. Its purpose is to get the console output availabe as soon
+ * as possible.
+ *
+ **************************************************************************/
+
+void sam3u_lowsetup(void)
+{
+ uint32_t regval;
+
+#warning "To be provided"
+ /* Enable clocking for the UART */
+
+ regval = getreg32(SAM3U_PMC_PCER);
+ regval |= (1 << SAM3U_PID_UART);
+ putreg32(regval, SAM3U_PMC_PCER);
+}
+
+
diff --git a/arch/arm/src/sam3u/sam3u_matrix.h b/arch/arm/src/sam3u/sam3u_matrix.h
index df630f5e0d8b97d859d5f54629e11686852a6d70..e9d41a658adc2e7d2c4e6d6276e9a9ca80bb90fe 100755
--- a/arch/arm/src/sam3u/sam3u_matrix.h
+++ b/arch/arm/src/sam3u/sam3u_matrix.h
@@ -1,7 +1,7 @@
/****************************************************************************************
* arch/arm/src/sam3u/sam3u_matric.h
*
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@@ -51,109 +51,125 @@
/* MATRIX register offsets **************************************************************/
-#define SAM3U_MATRIX_MCFG_OFFSET(n) ((n)<<2)
-#define SAM3U_MATRIX_MCFG0_OFFSET 0x0000 /* Master Configuration Register 0 */
-#define SAM3U_MATRIX_MCFG1_OFFSET 0x0004 /* Master Configuration Register 1 */
-#define SAM3U_MATRIX_MCFG2_OFFSET 0x0008 /* Master Configuration Register 2 */
-#define SAM3U_MATRIX_MCFG3_OFFSET 0x000c /* Master Configuration Register 3 */
-#define SAM3U_MATRIX_MCFG4_OFFSET 0x0010 /* Master Configuration Register 4 */
- /* 0x0014-0x003c: Reserved */
-#define SAM3U_MATRIX_SCFG_OFFSET(n) (0x0040+((n)<<2))
-#define SAM3U_MATRIX_SCFG0_OFFSET 0x0040 /* Slave Configuration Register 0 */
-#define SAM3U_MATRIX_SCFG1_OFFSET 0x0044 /* Slave Configuration Register 1 */
-#define SAM3U_MATRIX_SCFG2_OFFSET 0x0048 /* Slave Configuration Register 2 */
-#define SAM3U_MATRIX_SCFG3_OFFSET 0x004c /* Slave Configuration Register 3 */
-#define SAM3U_MATRIX_SCFG4_OFFSET 0x0050 /* Slave Configuration Register 4 */
-#define SAM3U_MATRIX_SCFG5_OFFSET 0x0054 /* Slave Configuration Register 5 */
-#define SAM3U_MATRIX_SCFG6_OFFSET 0x0058 /* Slave Configuration Register 6 */
-#define SAM3U_MATRIX_SCFG7_OFFSET 0x005c /* Slave Configuration Register 7 */
-#define SAM3U_MATRIX_SCFG8_OFFSET 0x0060 /* Slave Configuration Register 8 */
-#define SAM3U_MATRIX_SCFG9_OFFSET 0x0064 /* Slave Configuration Register 9 */
- /* 0x0068-0x007c: Reserved */
-#define SAM3U_MATRIX_SCFG_OFFSET(n) (0x0080+((n)<<3))
-#define SAM3U_MATRIX_PRAS0_OFFSET 0x0080 /* Priority Register A for Slave 0 */
- /* 0x0084: Reserved */
-#define SAM3U_MATRIX_PRAS1_OFFSET 0x0088 /* Priority Register A for Slave 1 */
- /* 0x008c: Reserved */
-#define SAM3U_MATRIX_PRAS2_OFFSET 0x0090 /* Priority Register A for Slave 2 */
- /* 0x0094: Reserved */
-#define SAM3U_MATRIX_PRAS3_OFFSET 0x0098 /* Priority Register A for Slave 3 */
- /* 0x009c: Reserved */
-#define SAM3U_MATRIX_PRAS4_OFFSET 0x00a0 /* Priority Register A for Slave 4 */
- /* 0x00a4: Reserved */
-#define SAM3U_MATRIX_PRAS5_OFFSET 0x00a8 /* Priority Register A for Slave 5 */
- /* 0x00ac: Reserved */
-#define SAM3U_MATRIX_PRAS6_OFFSET 0x00b0 /* Priority Register A for Slave 6 */
- /* 0x00b4: Reserved */
-#define SAM3U_MATRIX_PRAS7_OFFSET 0x00b8 /* Priority Register A for Slave 7 */
- /* 0x00bc: Reserved */
-#define SAM3U_MATRIX_PRAS8_OFFSET 0x00c0 /* Priority Register A for Slave 8 */
- /* 0x00c4: Reserved */
-#define SAM3U_MATRIX_PRAS9_OFFSET 0x00c8 /* Priority Register A for Slave 9 */
- /* 0x00cc-0x00fc: Reserved */
-#define SAM3U_MATRIX_MRCR_OFFSET 0x0100 /* Master Remap Control Register */
- /* 0x0104-0x010c: Reserved */
-#define SAM3U_MATRIX_WPMR_OFFSET 0x01e4 /* Write Protect Mode Register */
-#define SAM3U_MATRIX_WPSR_OFFSET 0x01e8 /* Write Protect Status Register */
- /* 0x0110 - 0x01fc: Reserved */
+#define SAM3U_MATRIX_MCFG_OFFSET(n) ((n)<<2)
+#define SAM3U_MATRIX_MCFG0_OFFSET 0x0000 /* Master Configuration Register 0 */
+#define SAM3U_MATRIX_MCFG1_OFFSET 0x0004 /* Master Configuration Register 1 */
+#define SAM3U_MATRIX_MCFG2_OFFSET 0x0008 /* Master Configuration Register 2 */
+#define SAM3U_MATRIX_MCFG3_OFFSET 0x000c /* Master Configuration Register 3 */
+#define SAM3U_MATRIX_MCFG4_OFFSET 0x0010 /* Master Configuration Register 4 */
+ /* 0x0014-0x003c: Reserved */
+#define SAM3U_MATRIX_SCFG_OFFSET(n) (0x0040+((n)<<2))
+#define SAM3U_MATRIX_SCFG0_OFFSET 0x0040 /* Slave Configuration Register 0 */
+#define SAM3U_MATRIX_SCFG1_OFFSET 0x0044 /* Slave Configuration Register 1 */
+#define SAM3U_MATRIX_SCFG2_OFFSET 0x0048 /* Slave Configuration Register 2 */
+#define SAM3U_MATRIX_SCFG3_OFFSET 0x004c /* Slave Configuration Register 3 */
+#define SAM3U_MATRIX_SCFG4_OFFSET 0x0050 /* Slave Configuration Register 4 */
+#define SAM3U_MATRIX_SCFG5_OFFSET 0x0054 /* Slave Configuration Register 5 */
+#define SAM3U_MATRIX_SCFG6_OFFSET 0x0058 /* Slave Configuration Register 6 */
+#define SAM3U_MATRIX_SCFG7_OFFSET 0x005c /* Slave Configuration Register 7 */
+#define SAM3U_MATRIX_SCFG8_OFFSET 0x0060 /* Slave Configuration Register 8 */
+#define SAM3U_MATRIX_SCFG9_OFFSET 0x0064 /* Slave Configuration Register 9 */
+ /* 0x0068-0x007c: Reserved */
+#define SAM3U_MATRIX_PRAS_OFFSET(n) (0x0080+((n)<<3))
+#define SAM3U_MATRIX_PRAS0_OFFSET 0x0080 /* Priority Register A for Slave 0 */
+ /* 0x0084: Reserved */
+#define SAM3U_MATRIX_PRAS1_OFFSET 0x0088 /* Priority Register A for Slave 1 */
+ /* 0x008c: Reserved */
+#define SAM3U_MATRIX_PRAS2_OFFSET 0x0090 /* Priority Register A for Slave 2 */
+ /* 0x0094: Reserved */
+#define SAM3U_MATRIX_PRAS3_OFFSET 0x0098 /* Priority Register A for Slave 3 */
+ /* 0x009c: Reserved */
+#define SAM3U_MATRIX_PRAS4_OFFSET 0x00a0 /* Priority Register A for Slave 4 */
+ /* 0x00a4: Reserved */
+#define SAM3U_MATRIX_PRAS5_OFFSET 0x00a8 /* Priority Register A for Slave 5 */
+ /* 0x00ac: Reserved */
+#define SAM3U_MATRIX_PRAS6_OFFSET 0x00b0 /* Priority Register A for Slave 6 */
+ /* 0x00b4: Reserved */
+#define SAM3U_MATRIX_PRAS7_OFFSET 0x00b8 /* Priority Register A for Slave 7 */
+ /* 0x00bc: Reserved */
+#define SAM3U_MATRIX_PRAS8_OFFSET 0x00c0 /* Priority Register A for Slave 8 */
+ /* 0x00c4: Reserved */
+#define SAM3U_MATRIX_PRAS9_OFFSET 0x00c8 /* Priority Register A for Slave 9 */
+ /* 0x00cc-0x00fc: Reserved */
+#define SAM3U_MATRIX_MRCR_OFFSET 0x0100 /* Master Remap Control Register */
+ /* 0x0104-0x010c: Reserved */
+#define SAM3U_MATRIX_WPMR_OFFSET 0x01e4 /* Write Protect Mode Register */
+#define SAM3U_MATRIX_WPSR_OFFSET 0x01e8 /* Write Protect Status Register */
+ /* 0x0110 - 0x01fc: Reserved */
/* MATRIX register adresses *************************************************************/
-#define SAM3U_MATRIX_MCFG(n)) (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG_OFFSET(n))
-#define SAM3U_MATRIX_MCFG0 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG0_OFFSET)
-#define SAM3U_MATRIX_MCFG1 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG1_OFFSET)
-#define SAM3U_MATRIX_MCFG2 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG2_OFFSET)
-#define SAM3U_MATRIX_MCFG3 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG3_OFFSET)
-#define SAM3U_MATRIX_MCFG4 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG4_OFFSET)
+#define SAM3U_MATRIX_MCFG(n)) (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG_OFFSET(n))
+#define SAM3U_MATRIX_MCFG0 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG0_OFFSET)
+#define SAM3U_MATRIX_MCFG1 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG1_OFFSET)
+#define SAM3U_MATRIX_MCFG2 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG2_OFFSET)
+#define SAM3U_MATRIX_MCFG3 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG3_OFFSET)
+#define SAM3U_MATRIX_MCFG4 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MCFG4_OFFSET)
-#define SAM3U_MATRIX_SCFG(n) (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG_OFFSET(n))
-#define SAM3U_MATRIX_SCFG0 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG0_OFFSET)
-#define SAM3U_MATRIX_SCFG1 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG1_OFFSET)
-#define SAM3U_MATRIX_SCFG2 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG2_OFFSET)
-#define SAM3U_MATRIX_SCFG3 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG3_OFFSET)
-#define SAM3U_MATRIX_SCFG4 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG4_OFFSET)
-#define SAM3U_MATRIX_SCFG5 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG5_OFFSET)
-#define SAM3U_MATRIX_SCFG6 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG6_OFFSET)
-#define SAM3U_MATRIX_SCFG7 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG7_OFFSET)
-#define SAM3U_MATRIX_SCFG8 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG8_OFFSET)
-#define SAM3U_MATRIX_SCFG9 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG9_OFFSET)
-
-#define SAM3U_MATRIX_SCFG(n) (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG_OFFSET(n))
-#define SAM3U_MATRIX_PRAS0 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS0_OFFSET)
-#define SAM3U_MATRIX_PRAS1 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS1_OFFSET)
-#define SAM3U_MATRIX_PRAS2 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS2_OFFSET)
-#define SAM3U_MATRIX_PRAS3 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS3_OFFSET)
-#define SAM3U_MATRIX_PRAS4 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS4_OFFSET)
-#define SAM3U_MATRIX_PRAS5 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS5_OFFSET)
-#define SAM3U_MATRIX_PRAS6 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS6_OFFSET)
-#define SAM3U_MATRIX_PRAS7 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS7_OFFSET)
-#define SAM3U_MATRIX_PRAS8 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS8_OFFSET)
-#define SAM3U_MATRIX_PRAS9 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS9_OFFSET)
-
-#define SAM3U_MATRIX_MRCR (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MRCR_OFFSET)
-#define SAM3U_MATRIX_WPMR (SAM3U_MATRIX_BASE+SAM3U_MATRIX_WPMR_OFFSET)
-#define SAM3U_MATRIX_WPSR (SAM3U_MATRIX_BASE+SAM3U_MATRIX_WPSR_OFFSET)
+#define SAM3U_MATRIX_SCFG(n) (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG_OFFSET(n))
+#define SAM3U_MATRIX_SCFG0 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG0_OFFSET)
+#define SAM3U_MATRIX_SCFG1 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG1_OFFSET)
+#define SAM3U_MATRIX_SCFG2 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG2_OFFSET)
+#define SAM3U_MATRIX_SCFG3 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG3_OFFSET)
+#define SAM3U_MATRIX_SCFG4 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG4_OFFSET)
+#define SAM3U_MATRIX_SCFG5 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG5_OFFSET)
+#define SAM3U_MATRIX_SCFG6 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG6_OFFSET)
+#define SAM3U_MATRIX_SCFG7 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG7_OFFSET)
+#define SAM3U_MATRIX_SCFG8 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG8_OFFSET)
+#define SAM3U_MATRIX_SCFG9 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_SCFG9_OFFSET)
+
+#define SAM3U_MATRIX_PRAS(n) (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS_OFFSET(n))
+#define SAM3U_MATRIX_PRAS0 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS0_OFFSET)
+#define SAM3U_MATRIX_PRAS1 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS1_OFFSET)
+#define SAM3U_MATRIX_PRAS2 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS2_OFFSET)
+#define SAM3U_MATRIX_PRAS3 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS3_OFFSET)
+#define SAM3U_MATRIX_PRAS4 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS4_OFFSET)
+#define SAM3U_MATRIX_PRAS5 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS5_OFFSET)
+#define SAM3U_MATRIX_PRAS6 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS6_OFFSET)
+#define SAM3U_MATRIX_PRAS7 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS7_OFFSET)
+#define SAM3U_MATRIX_PRAS8 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS8_OFFSET)
+#define SAM3U_MATRIX_PRAS9 (SAM3U_MATRIX_BASE+SAM3U_MATRIX_PRAS9_OFFSET)
+
+#define SAM3U_MATRIX_MRCR (SAM3U_MATRIX_BASE+SAM3U_MATRIX_MRCR_OFFSET)
+#define SAM3U_MATRIX_WPMR (SAM3U_MATRIX_BASE+SAM3U_MATRIX_WPMR_OFFSET)
+#define SAM3U_MATRIX_WPSR (SAM3U_MATRIX_BASE+SAM3U_MATRIX_WPSR_OFFSET)
/* MATRIX register bit definitions ******************************************************/
-#define MATRIX_MCFG_ULBT_SHIFT (0) /* Bits 0-2: Undefined Length Burst Type */
-#define MATRIX_MCFG_ULBT_MASK (7 << MATRIX_MCFG_ULBT_SHIFT)
-# define MATRIX_MCFG_ULBT_INF (0 << MATRIX_MCFG_ULBT_SHIFT) /* Infinite Length Burst
-# define MATRIX_MCFG_ULBT_SINGLE (1 << MATRIX_MCFG_ULBT_SHIFT) /* Single Access
-# define MATRIX_MCFG_ULBT_4BEAT (2 << MATRIX_MCFG_ULBT_SHIFT) /* Four Beat Burst
-# define MATRIX_MCFG_ULBT_8BEAT (3 << MATRIX_MCFG_ULBT_SHIFT) /* Eight Beat Burst
-# define MATRIX_MCFG_ULBT_16BEAT (4 << MATRIX_MCFG_ULBT_SHIFT) /* Sixteen Beat Burst
-
-#define MATRIX_SCFG_SLOT_CYCLE_SHIFT (0) /* Bits 0-7: Maximum Number of Allowed Cycles for a Burst */
-#define MATRIX_SCFG_SLOT_CYCLE_MASK (0xff << MATRIX_SCFG_SLOT_CYCLE_SHIFT)
-#define MATRIX_SCFG_DEFMSTR_TYPE_SHIFT (16) /* Bits 16-17: Default Master Type */
-#define MATRIX_SCFG_DEFMSTR_TYPE_MASK (3 << MATRIX_SCFG_DEFMSTR_TYPE_SHIFT)
-#define MATRIX_SCFG_FIXED_DEFMSTR_SHIFT (18) /* Bits 18-20: Fixed Default Master */
-#define MATRIX_SCFG_FIXED_DEFMSTR_MASK (7 << MATRIX_SCFG_FIXED_DEFMSTR_SHIFT)
+#define MATRIX_MCFG_ULBT_SHIFT (0) /* Bits 0-2: Undefined Length Burst Type */
+#define MATRIX_MCFG_ULBT_MASK (7 << MATRIX_MCFG_ULBT_SHIFT)
+# define MATRIX_MCFG_ULBT_INF (0 << MATRIX_MCFG_ULBT_SHIFT) /* Infinite Length Burst */
+# define MATRIX_MCFG_ULBT_SINGLE (1 << MATRIX_MCFG_ULBT_SHIFT) /* Single Access */
+# define MATRIX_MCFG_ULBT_4BEAT (2 << MATRIX_MCFG_ULBT_SHIFT) /* Four Beat Burst */
+# define MATRIX_MCFG_ULBT_8BEAT (3 << MATRIX_MCFG_ULBT_SHIFT) /* Eight Beat Burst */
+# define MATRIX_MCFG_ULBT_16BEAT (4 << MATRIX_MCFG_ULBT_SHIFT) /* Sixteen Beat Burst */
+
+#define MATRIX_SCFG_SLOTCYCLE_SHIFT (0) /* Bits 0-7: Maximum Number of Allowed Cycles for a Burst */
+#define MATRIX_SCFG_SLOTCYCLE_MASK (0xff << MATRIX_SCFG_SLOTCYCLE_SHIFT)
+#define MATRIX_SCFG_DEFMSTRTYPE_SHIFT (16) /* Bits 16-17: Default Master Type */
+#define MATRIX_SCFG_DEFMSTRTYPE_MASK (3 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT)
+# define MATRIX_SCFG_DEFMSTRTYPE_NONE (0 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT)
+# define MATRIX_SCFG_DEFMSTRTYPE_LAST (1 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT)
+# define MATRIX_SCFG_DEFMSTRTYPE_FIXED (2 << MATRIX_SCFG_DEFMSTRTYPE_SHIFT)
+#define MATRIX_SCFG_FIXEDDEFMSTR_SHIFT (18) /* Bits 18-20: Fixed Default Master */
+#define MATRIX_SCFG_FIXEDDEFMSTR_MASK (7 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
+# define MATRIX_SCFG0_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
+# define MATRIX_SCFG1_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
+# define MATRIX_SCFG2_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
+# define MATRIX_SCFG3_FIXEDDEFMSTR_ARMC (0 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
+# define MATRIX_SCFG4_FIXEDDEFMSTR_ARMC (0 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
+# define MATRIX_SCFG5_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
+# define MATRIX_SCFG6_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
+# define MATRIX_SCFG7_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
+# define MATRIX_SCFG8_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
+# define MATRIX_SCFG8_FIXEDDEFMSTR_HDMA (4 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
+# define MATRIX_SCFG9_FIXEDDEFMSTR_ARMS (1 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
+# define MATRIX_SCFG9_FIXEDDEFMSTR_HDMA (4 << MATRIX_SCFG_FIXEDDEFMSTR_SHIFT)
+
#define MATRIX_SCFG_ARBT_SHIFT (24) /* Bits 24-25: Arbitration Type */
#define MATRIX_SCFG_ARBT_MASK (3 << MATRIX_SCFG_ARBT_SHIFT)
-# define MATRIX_SCFG_ARBT_RR (0 << MATRIX_SCFG_ARBT_SHIFT) /* Round-Robin Arbitration
-# define MATRIX_SCFG_ARBT_FIXED (1 << MATRIX_SCFG_ARBT_SHIFT) /* Fixed Priority Arbitration
+# define MATRIX_SCFG_ARBT_RR (0 << MATRIX_SCFG_ARBT_SHIFT) /* Round-Robin Arbitration */
+# define MATRIX_SCFG_ARBT_FIXED (1 << MATRIX_SCFG_ARBT_SHIFT) /* Fixed Priority Arbitration */
#define MATRIX_PRAS_MPR_SHIFT(x) ((n)<<2)
#define MATRIX_PRAS_MPR_MASK(x) (3 << MATRIX_PRAS_MPR_SHIFT(x))
diff --git a/arch/arm/src/sam3u/sam3u_pmc.h b/arch/arm/src/sam3u/sam3u_pmc.h
index ba808c2fc60132e62a74275a189e367e053e8349..3fde5b642ba6ccdcc6f94ed0c28de2553d72161e 100755
--- a/arch/arm/src/sam3u/sam3u_pmc.h
+++ b/arch/arm/src/sam3u/sam3u_pmc.h
@@ -196,8 +196,9 @@
#define CKGR_PLLAR_STMODE_MASK (3 << CKGR_PLLAR_STMODE_SHIFT)
# define CKGR_PLLAR_STMODE_FAST (0 << CKGR_PLLAR_STMODE_SHIFT) /* Fast Startup */
# define CKGR_PLLAR_STMODE_NORMAL (2 << CKGR_PLLAR_STMODE_SHIFT) /* Normal Startup */
-#define CKGR_PLLAR_MULA_SHIFT (24) /* Bits 24-26: PLLA Multiplier */
-#define CKGR_PLLAR_MULA_MASK (7 << CKGR_PLLAR_MULA_SHIFT)
+#define CKGR_PLLAR_MULA_SHIFT (16) /* Bits 16-26: PLLA Multiplier */
+#define CKGR_PLLAR_MULA_MASK (0x7ff << CKGR_PLLAR_MULA_SHIFT)
+#define CKGR_PLLAR_ONE (1 << 29) /* Bit 29: Always one */
/* PMC Master Clock Register */
@@ -244,7 +245,7 @@
#define PMC_INT_MOSCXTS (1 << 0) /* Bit 0: Main Crystal Oscillator Status Interrupt */
#define PMC_INT_LOCKA (1 << 1) /* Bit 1: PLL A Lock Interrupt */
-#define PMC_INT_MCKRDY (1 << 2) /* Bit 3: Master Clock Ready Interrupt */
+#define PMC_INT_MCKRDY (1 << 3) /* Bit 3: Master Clock Ready Interrupt */
#define PMC_INT_LOCKU (1 << 6) /* Bit 6: UTMI PLL Lock Interrupt */
#define PMC_SR_OSCSELS (1 << 7) /* Bit 7: Slow Clock Oscillator Selection (SR only) */
#define PMC_INT_PCKRDY(n) (1<<((n)+8)
diff --git a/arch/arm/src/sam3u/sam3u_start.c b/arch/arm/src/sam3u/sam3u_start.c
index 34b418cc3bd94dfadb803f4a5320d5bba31cee76..71027be669c15222bceb8fb5c772cab3a3edc78a 100755
--- a/arch/arm/src/sam3u/sam3u_start.c
+++ b/arch/arm/src/sam3u/sam3u_start.c
@@ -2,7 +2,7 @@
* arch/arm/src/sam3u/sam3u_start.c
* arch/arm/src/chip/sam3u_start.c
*
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
diff --git a/arch/arm/src/sam3u/sam3u_supc.h b/arch/arm/src/sam3u/sam3u_supc.h
index 60017324b8d84ab17f04ca84d93df484e05e0cc7..8cde5389e7cfd6d10f27c7c9800cb0942610743b 100755
--- a/arch/arm/src/sam3u/sam3u_supc.h
+++ b/arch/arm/src/sam3u/sam3u_supc.h
@@ -94,8 +94,8 @@
# define SUPC_SMMR_SMTH_3p4V (15 << SUPC_SMMR_SMTH_SHIFT) /* 3.4V */
#define SUPC_SMMR_SMSMPL_SHIFT (8) /* Bits 8-10: Supply Monitor Sampling Period */
#define SUPC_SMMR_SMSMPL_MASK (7 << SUPC_SMMR_SMSMPL_SHIFT)
-# define SUPC_SMMR_SMSMPL_SMD (0 << SUPC_SMMR_SMSMPL_SHIFT) /* Supply Monitor disabled */ */
-# define SUPC_SMMR_SMSMPL_CSM (1 << SUPC_SMMR_SMSMPL_SHIFT) /* Continuous Supply Monitor
+# define SUPC_SMMR_SMSMPL_SMD (0 << SUPC_SMMR_SMSMPL_SHIFT) /* Supply Monitor disabled */
+# define SUPC_SMMR_SMSMPL_CSM (1 << SUPC_SMMR_SMSMPL_SHIFT) /* Continuous Supply Monitor */
# define SUPC_SMMR_SMSMPL_32SLCK (2 << SUPC_SMMR_SMSMPL_SHIFT) /* Eevery 32 SLCK periods */
# define SUPC_SMMR_SMSMPL_256SLCK (3 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 256 SLCK periods */
# define SUPC_SMMR_SMSMPL_2048SLCK (4 << SUPC_SMMR_SMSMPL_SHIFT) /* Every 2,048 SLCK periods */
@@ -123,12 +123,12 @@
#define SUPC_WUMR_FWUPDBC_32768SCLK (5 << SUPC_WUMR_FWUPDBC_SHIFT) /* FWUP at least 32768 SLCK periods */
#define SUPC_WUMR_WKUPDBC_SHIFT (12) /* Bits 12-14: Wake Up Inputs Debouncer */
#define SUPC_WUMR_WKUPDBC_MASK (7 << SUPC_WUMR_WKUPDBC_SHIFT)
-# define SUPC_WUMR_WKUPDBC_ 1SCLK (0 << SUPC_WUMR_WKUPDBC_SHIFT) /* Immediate, no debouncing */
-# define SUPC_WUMR_WKUPDBC_ 3SCLK (1 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 3 SLCK periods */
-# define SUPC_WUMR_WKUPDBC_ 32SCLK (2 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32 SLCK periods */
-# define SUPC_WUMR_WKUPDBC_ 512SCLK (3 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 512 SLCK periods */
-# define SUPC_WUMR_WKUPDBC_ 4096SCLK (4 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 4096 SLCK periods */
-# define SUPC_WUMR_WKUPDBC_ 32768SCLK (5 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32768 SLCK periods */
+# define SUPC_WUMR_WKUPDBC_1SCLK (0 << SUPC_WUMR_WKUPDBC_SHIFT) /* Immediate, no debouncing */
+# define SUPC_WUMR_WKUPDBC_3SCLK (1 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 3 SLCK periods */
+# define SUPC_WUMR_WKUPDBC_32SCLK (2 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32 SLCK periods */
+# define SUPC_WUMR_WKUPDBC_512SCLK (3 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 512 SLCK periods */
+# define SUPC_WUMR_WKUPDBC_4096SCLK (4 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 4096 SLCK periods */
+# define SUPC_WUMR_WKUPDBC_32768SCLK (5 << SUPC_WUMR_WKUPDBC_SHIFT) /* Input active at least 32768 SLCK periods */
#define SUPC_WUIR_WKUPEN_SHIFT (0) /* Bits 0-15: Wake Up Input Enable 0 to 15 */
#define SUPC_WUIR_WKUPEN_MASK (0xffff << SUPC_WUIR_WKUPEN_SHIFT)
diff --git a/arch/arm/src/sam3u/sam3u_timerisr.c b/arch/arm/src/sam3u/sam3u_timerisr.c
new file mode 100755
index 0000000000000000000000000000000000000000..225af25f6a381976cfeac5674d1c6c8351796fc0
--- /dev/null
+++ b/arch/arm/src/sam3u/sam3u_timerisr.c
@@ -0,0 +1,162 @@
+/****************************************************************************
+ * arch/arm/src/sam3u/sam3u_timerisr.c
+ *
+ * Copyright (C) 2010 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <time.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+#include <arch/board/board.h>
+
+#include "nvic.h"
+#include "clock_internal.h"
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "chip.h"
+#include "sam3u_internal.h"
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/* The desired timer interrupt frequency is provided by the definition
+ * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
+ * system clock ticks per second. That value is a user configurable setting
+ * that defaults to 100 (100 ticks per second = 10 MS interval).
+ *
+ * The SAM3U feeds the Cortex System Timer (SysTick) with the MCK clock or
+ * the MCK clock divided by 8, configurable with the CLKSOURCE bit in the
+ * SysTick Control and Status register.
+ */
+
+#undef CONFIG_SAM3U_SYSTICK_HCLKd8 /* Power up default is MCK, not MCK/8 */
+
+#if CONFIG_SAM3U_SYSTICK_HCLKd8
+# define SYSTICK_RELOAD ((SAM3U_MCK_FREQUENCY / 8 / CLK_TCK) - 1)
+#else
+# define SYSTICK_RELOAD ((SAM3U_MCK_FREQUENCY / CLK_TCK) - 1)
+#endif
+
+/* The size of the reload field is 24 bits. Verify that the reload value
+ * will fit in the reload register.
+ */
+
+#if SYSTICK_RELOAD > 0x00ffffff
+# error SYSTICK_RELOAD exceeds the range of the RELOAD register
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Global Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function: up_timerisr
+ *
+ * Description:
+ * The timer ISR will perform a variety of services for various portions
+ * of the systems.
+ *
+ ****************************************************************************/
+
+int up_timerisr(int irq, uint32_t *regs)
+{
+ /* Process timer interrupt */
+
+ sched_process_timer();
+ return 0;
+}
+
+/****************************************************************************
+ * Function: up_timerinit
+ *
+ * Description:
+ * This function is called during start-up to initialize
+ * the timer interrupt.
+ *
+ ****************************************************************************/
+
+void up_timerinit(void)
+{
+ uint32_t regval;
+
+ /* Set the SysTick interrupt to the default priority */
+
+ regval = getreg32(NVIC_SYSH12_15_PRIORITY);
+ regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK;
+ regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT);
+ putreg32(regval, NVIC_SYSH12_15_PRIORITY);
+
+ /* Make sure that the SYSTICK clock source is set correctly */
+
+#if 0 /* Does not work. Comes up with HCLK source and I can't change it */
+ regval = getreg32(NVIC_SYSTICK_CTRL);
+#if CONFIG_SAM3U_SYSTICK_HCLKd8
+ regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE;
+#else
+ regval |= NVIC_SYSTICK_CTRL_CLKSOURCE;
+#endif
+ putreg32(regval, NVIC_SYSTICK_CTRL);
+#endif
+
+ /* Configure SysTick to interrupt at the requested rate */
+
+ putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
+
+ /* Attach the timer interrupt vector */
+
+ (void)irq_attach(SAM3U_IRQ_SYSTICK, (xcpt_t)up_timerisr);
+
+ /* Enable SysTick interrupts */
+
+ putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE|NVIC_SYSTICK_CTRL_TICKINT|NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);
+
+ /* And enable the timer interrupt */
+
+ up_enable_irq(SAM3U_IRQ_SYSTICK);
+}
diff --git a/configs/sam3u-ek/include/board.h b/configs/sam3u-ek/include/board.h
index 83fbdbd8fed1434fed91691615fb0b79d1ba848d..4dd4de11d5adb6893d34dda50203b053213a5b3a 100755
--- a/configs/sam3u-ek/include/board.h
+++ b/configs/sam3u-ek/include/board.h
@@ -53,17 +53,46 @@
************************************************************************************/
/* Clocking *************************************************************************/
+/* After power-on reset, the sam3u device is running on a 4MHz internal RC. These
+ * definitions will configure clocking with MCK = 48MHz, PLLA = 96, and CPU=48MHz.
+ */
+
+/* Main oscillator register settings */
+
+#define BOARD_CKGR_MOR_MOSCXTST (63 << CKGR_MOR_MOSCXTST_SHIFT) /* Start-up Time */
+
+/* PLLA configuration */
+
+#define BOARD_CKGR_PLLAR_MULA (7 << CKGR_PLLAR_MULA_SHIFT)
+#define BOARD_CKGR_PLLAR_STMODE CKGR_PLLAR_STMODE_FAST
+#define BOARD_CKGR_PLLAR_PLLACOUNT (63 << CKGR_PLLAR_PLLACOUNT_SHIFT)
+#define BOARD_CKGR_PLLAR_DIVA CKGR_PLLAR_DIVA_BYPASS
+
+/* PMC master clock register settings */
+
+#define BOARD_PMC_MCKR_CSS PMC_MCKR_CSS_PLLA
+#define BOARD_PMC_MCKR_PRES PMC_MCKR_PRES_DIV2
+
+/* USB UTMI PLL start-up time */
+
+#define BOARD_CKGR_UCKR_UPLLCOUNT (3 << CKGR_UCKR_UPLLCOUNT_SHIFT)
+
+/* Resulting frequencies */
+
+#define SAM3U_MCK_FREQUENCY (48000000)
+#define SAM3U_PLLA_FREQUENCY (96000000)
+#define SAM3U_CPU_FREQUENCY (48000000)
/* LED definitions ******************************************************************/
-#define LED_STARTED 0
-#define LED_HEAPALLOCATE 1
-#define LED_IRQSENABLED 2
-#define LED_STACKCREATED 3
-#define LED_INIRQ 4
-#define LED_SIGNAL 5
-#define LED_ASSERTION 6
-#define LED_PANIC 7
+#define LED_STARTED 0
+#define LED_HEAPALLOCATE 1
+#define LED_IRQSENABLED 2
+#define LED_STACKCREATED 3
+#define LED_INIRQ 4
+#define LED_SIGNAL 5
+#define LED_ASSERTION 6
+#define LED_PANIC 7
/************************************************************************************
* Public Data
diff --git a/configs/sam3u-ek/ostest/defconfig b/configs/sam3u-ek/ostest/defconfig
index cc19b2cd935ff88f9ee7edb0933baf5895499d3a..7c5b33c31bd004bea82da1dc999fb9db0663c833 100755
--- a/configs/sam3u-ek/ostest/defconfig
+++ b/configs/sam3u-ek/ostest/defconfig
@@ -129,43 +129,43 @@ CONFIG_USART3_ISUART=y
# CONFIG_USARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
# CONFIG_USARTn_2STOP - Two stop bits
#
-CONFIG_USART_SERIAL_CONSOLE=Y
+CONFIG_UART_SERIAL_CONSOLE=Y
CONFIG_USART0_SERIAL_CONSOLE=n
CONFIG_USART1_SERIAL_CONSOLE=n
CONFIG_USART2_SERIAL_CONSOLE=n
CONFIG_USART3_SERIAL_CONSOLE=n
-CONFIG_USART_TXBUFSIZE=256
+CONFIG_UART_TXBUFSIZE=256
CONFIG_USART0_TXBUFSIZE=256
CONFIG_USART1_TXBUFSIZE=256
CONFIG_USART2_TXBUFSIZE=256
CONFIG_USART3_TXBUFSIZE=256
-CONFIG_USART_RXBUFSIZE=256
+CONFIG_UART_RXBUFSIZE=256
CONFIG_USART0_RXBUFSIZE=256
CONFIG_USART1_RXBUFSIZE=256
CONFIG_USART2_RXBUFSIZE=256
CONFIG_USART3_RXBUFSIZE=256
-CONFIG_USART_BAUD=115200
+CONFIG_UART_BAUD=115200
CONFIG_USART0_BAUD=115200
CONFIG_USART1_BAUD=115200
CONFIG_USART2_BAUD=115200
CONFIG_USART3_BAUD=115200
-CONFIG_USART_BITS=8
+CONFIG_UART_BITS=8
CONFIG_USART0_BITS=8
CONFIG_USART1_BITS=8
CONFIG_USART2_BITS=8
CONFIG_USART3_BITS=8
-CONFIG_USART_PARITY=0
+CONFIG_UART_PARITY=0
CONFIG_USART0_PARITY=0
CONFIG_USART1_PARITY=0
CONFIG_USART2_PARITY=0
CONFIG_USART3_PARITY=0
-CONFIG_USART_2STOP=0
+CONFIG_UART_2STOP=0
CONFIG_USART0_2STOP=0
CONFIG_USART1_2STOP=0
CONFIG_USART2_2STOP=0