diff --git a/arch/arm/src/lpc17xx/lpc17_usbhost.c b/arch/arm/src/lpc17xx/lpc17_usbhost.c
index 1cd2bb1ff17aaa0b7fd13a1f080c49e07c2ccf41..86457bf403d3abf74c8709051ab65908178d63b7 100755
--- a/arch/arm/src/lpc17xx/lpc17_usbhost.c
+++ b/arch/arm/src/lpc17xx/lpc17_usbhost.c
@@ -1469,7 +1469,7 @@ static int lpc17_usbinterrupt(int irq, FAR void *context)
{
/* The transfer failed for some reason... dump some diagnostic info. */
- ulldbg("ERROR: ED: xfrtype:%d TD CTRL:%08x/CC:%d RHPORTST1:%08x\n",
+ ulldbg("ERROR: ED xfrtype:%d TD CTRL:%08x/CC:%d RHPORTST1:%08x\n",
ed->xfrtype, td->hw.ctrl, ed->tdstatus,
lpc17_getreg(LPC17_USBHOST_RHPORTST1));
}
diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs
index 34b6458b1875022c22888a381092f3368cf575fe..be772f179122aa29687a12c6a1db69923659258a 100755
--- a/arch/arm/src/stm32/Make.defs
+++ b/arch/arm/src/stm32/Make.defs
@@ -48,5 +48,5 @@ CHIP_ASRCS =
CHIP_CSRCS = stm32_start.c stm32_rcc.c stm32_gpio.c stm32_idle.c \
stm32_irq.c stm32_timerisr.c stm32_dma.c stm32_lowputc.c \
stm32_serial.c stm32_spi.c stm32_usbdev.c stm32_sdio.c \
- stm32_tim.c
+ stm32_tim.c stm32_i2c.c
diff --git a/arch/arm/src/stm32/chip.h b/arch/arm/src/stm32/chip.h
index 28d59c838197938cb14b377e333c5d4c5482d9e7..5d01eadde8ceda07323ec9bde61b343b23de000f 100755
--- a/arch/arm/src/stm32/chip.h
+++ b/arch/arm/src/stm32/chip.h
@@ -33,20 +33,29 @@
*
************************************************************************************/
+/** \file
+ * \author Gregory Nutt <spudmonkey@racsa.co.cr>
+ * \brief Chip Definition provides over-all memory Map, and pin mapping
+ **/
+
#ifndef __ARCH_ARM_SRC_STM32_CHIP_H
#define __ARCH_ARM_SRC_STM32_CHIP_H
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
-/* Get customizations for each supported chip (only the STM32F103Z right now) */
+/* Get customizations for each supported chip and provide alternate function pin-mapping
+ *
+ * NOTE: Each GPIO pin may serve either for general purpose I/O or for a special
+ * alternate function (such as USART, CAN, USB, SDIO, etc.). That particular
+ * pin-mapping will depend on the package and STM32 family. If you are incorporating
+ * a new STM32 chip into NuttX, you will need to add the pin-mapping to a header file
+ * and to include that header file below. The chip-specific pin-mapping is defined in
+ * the chip datasheet.
+ */
#if defined(CONFIG_ARCH_CHIP_STM32F103ZET6)
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
@@ -67,6 +76,7 @@
# define STM32_NDAC 0 /* No DAC */
# define STM32_NCRC 0 /* No CRC */
# define STM32_NTHERNET 0 /* No ethernet */
+# include "stm32f103ze_pinmap.h"
#elif defined(CONFIG_ARCH_CHIP_STM32F103RET6)
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
@@ -87,6 +97,7 @@
# define STM32_NDAC 2 /* DAC1-2 */
# define STM32_NCRC 1 /* CRC */
# define STM32_NTHERNET 0 /* No ethernet */
+# include "stm32f103re_pinmap.h"
#elif defined(CONFIG_ARCH_CHIP_STM32F107VC)
# undef CONFIG_STM32_LOWDENSITY /* STM32F101x, STM32F102x and STM32F103x w/ 16/32 Kbytes */
@@ -107,27 +118,16 @@
# define STM32_NDAC 2 /* DAC1-2 */
# define STM32_NCRC 1 /* CRC */
# define STM32_NTHERNET 1 /* 100/100 Ethernet MAC */
+# include "stm32f107vc_pinmap.h"
#else
# error "Unsupported STM32 chip"
#endif
-/* Include only the memory map. Other chip hardware files should then include this
- * file for the proper setup
+/* Include only the memory map.
+ * Other chip hardware files should then include this file for the proper setup
*/
#include "stm32_memorymap.h"
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-/************************************************************************************
- * Public Data
- ************************************************************************************/
-
-/************************************************************************************
- * Public Functions
- ************************************************************************************/
-
#endif /* __ARCH_ARM_SRC_STM32_CHIP_H */
diff --git a/arch/arm/src/stm32/chip/stm32_gpio.h b/arch/arm/src/stm32/chip/stm32_gpio.h
new file mode 100644
index 0000000000000000000000000000000000000000..3ecd5fca1937baf67b9918e5763a4148ba448a32
--- /dev/null
+++ b/arch/arm/src/stm32/chip/stm32_gpio.h
@@ -0,0 +1,364 @@
+/************************************************************************************
+ * arch/arm/src/stm32/chip/stm32_gpio.h
+ *
+ * Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_GPIO_H
+#define __ARCH_ARM_SRC_STM32_CHIP_STM32_GPIO_H
+
+
+/************************************************************************************
+ * Pre-processor Definitions (Hardware Register Descriptions)
+ ************************************************************************************/
+
+#define STM32_NGPIO_PORTS ((STM32_NGPIO + 15) >> 4)
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_GPIO_CRL_OFFSET 0x0000 /* Port configuration register low */
+#define STM32_GPIO_CRH_OFFSET 0x0004 /* Port configuration register high */
+#define STM32_GPIO_IDR_OFFSET 0x0008 /* Port input data register */
+#define STM32_GPIO_ODR_OFFSET 0x000c /* Port output data register */
+#define STM32_GPIO_BSRR_OFFSET 0x0010 /* Port bit set/reset register */
+#define STM32_GPIO_BRR_OFFSET 0x0014 /* Port bit reset register */
+#define STM32_GPIO_LCKR_OFFSET 0x0018 /* Port configuration lock register */
+
+#define STM32_AFIO_EVCR_OFFSET 0x0000 /* Event control register */
+#define STM32_AFIO_MAPR_OFFSET 0x0004 /* AF remap and debug I/O configuration register */
+#define STM32_AFIO_EXTICR_OFFSET(p) (0x0008 + ((p) >> 2))
+#define STM32_AFIO_EXTICR1_OFFSET 0x0008 /* External interrupt configuration register 1 */
+#define STM32_AFIO_EXTICR2_OFFSET 0x000c /* External interrupt configuration register 2 */
+#define STM32_AFIO_EXTICR3_OFFSET 0x0010 /* External interrupt configuration register 3 */
+#define STM32_AFIO_EXTICR4_OFFSET 0x0014 /* External interrupt configuration register 4 */
+
+/* Register Addresses ***************************************************************/
+
+#if STM32_NGPIO_PORTS > 0
+# define STM32_GPIOA_CRL (STM32_GPIOA_BASE+STM32_GPIO_CRL_OFFSET)
+# define STM32_GPIOA_CRH (STM32_GPIOA_BASE+STM32_GPIO_CRH_OFFSET)
+# define STM32_GPIOA_IDR (STM32_GPIOA_BASE+STM32_GPIO_IDR_OFFSET)
+# define STM32_GPIOA_ODR (STM32_GPIOA_BASE+STM32_GPIO_ODR_OFFSET)
+# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE+STM32_GPIO_BSRR_OFFSET)
+# define STM32_GPIOA_BRR (STM32_GPIOA_BASE+STM32_GPIO_BRR_OFFSET)
+# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE+STM32_GPIO_LCKR_OFFSET)
+#endif
+
+#if STM32_NGPIO_PORTS > 1
+# define STM32_GPIOB_CRL (STM32_GPIOB_BASE+STM32_GPIO_CRL_OFFSET)
+# define STM32_GPIOB_CRH (STM32_GPIOB_BASE+STM32_GPIO_CRH_OFFSET)
+# define STM32_GPIOB_IDR (STM32_GPIOB_BASE+STM32_GPIO_IDR_OFFSET)
+# define STM32_GPIOB_ODR (STM32_GPIOB_BASE+STM32_GPIO_ODR_OFFSET)
+# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE+STM32_GPIO_BSRR_OFFSET)
+# define STM32_GPIOB_BRR (STM32_GPIOB_BASE+STM32_GPIO_BRR_OFFSET)
+# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE+STM32_GPIO_LCKR_OFFSET)
+#endif
+
+#if STM32_NGPIO_PORTS > 2
+# define STM32_GPIOC_CRL (STM32_GPIOC_BASE+STM32_GPIO_CRL_OFFSET)
+# define STM32_GPIOC_CRH (STM32_GPIOC_BASE+STM32_GPIO_CRH_OFFSET)
+# define STM32_GPIOC_IDR (STM32_GPIOC_BASE+STM32_GPIO_IDR_OFFSET)
+# define STM32_GPIOC_ODR (STM32_GPIOC_BASE+STM32_GPIO_ODR_OFFSET)
+# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE+STM32_GPIO_BSRR_OFFSET)
+# define STM32_GPIOC_BRR (STM32_GPIOC_BASE+STM32_GPIO_BRR_OFFSET)
+# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE+STM32_GPIO_LCKR_OFFSET)
+#endif
+
+#if STM32_NGPIO_PORTS > 3
+# define STM32_GPIOD_CRL (STM32_GPIOD_BASE+STM32_GPIO_CRL_OFFSET)
+# define STM32_GPIOD_CRH (STM32_GPIOD_BASE+STM32_GPIO_CRH_OFFSET)
+# define STM32_GPIOD_IDR (STM32_GPIOD_BASE+STM32_GPIO_IDR_OFFSET)
+# define STM32_GPIOD_ODR (STM32_GPIOD_BASE+STM32_GPIO_ODR_OFFSET)
+# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE+STM32_GPIO_BSRR_OFFSET)
+# define STM32_GPIOD_BRR (STM32_GPIOD_BASE+STM32_GPIO_BRR_OFFSET)
+# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE+STM32_GPIO_LCKR_OFFSET)
+#endif
+
+#if STM32_NGPIO_PORTS > 4
+# define STM32_GPIOE_CRL (STM32_GPIOE_BASE+STM32_GPIO_CRL_OFFSET)
+# define STM32_GPIOE_CRH (STM32_GPIOE_BASE+STM32_GPIO_CRH_OFFSET)
+# define STM32_GPIOE_IDR (STM32_GPIOE_BASE+STM32_GPIO_IDR_OFFSET)
+# define STM32_GPIOE_ODR (STM32_GPIOE_BASE+STM32_GPIO_ODR_OFFSET)
+# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE+STM32_GPIO_BSRR_OFFSET)
+# define STM32_GPIOE_BRR (STM32_GPIOE_BASE+STM32_GPIO_BRR_OFFSET)
+# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE+STM32_GPIO_LCKR_OFFSET)
+#endif
+
+#if STM32_NGPIO_PORTS > 5
+# define STM32_GPIOF_CRL (STM32_GPIOF_BASE+STM32_GPIO_CRL_OFFSET)
+# define STM32_GPIOF_CRH (STM32_GPIOF_BASE+STM32_GPIO_CRH_OFFSET)
+# define STM32_GPIOF_IDR (STM32_GPIOF_BASE+STM32_GPIO_IDR_OFFSET)
+# define STM32_GPIOF_ODR (STM32_GPIOF_BASE+STM32_GPIO_ODR_OFFSET)
+# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE+STM32_GPIO_BSRR_OFFSET)
+# define STM32_GPIOF_BRR (STM32_GPIOF_BASE+STM32_GPIO_BRR_OFFSET)
+# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE+STM32_GPIO_LCKR_OFFSET)
+#endif
+
+#if STM32_NGPIO_PORTS > 6
+# define STM32_GPIOG_CRL (STM32_GPIOG_BASE+STM32_GPIO_CRL_OFFSET)
+# define STM32_GPIOG_CRH (STM32_GPIOG_BASE+STM32_GPIO_CRH_OFFSET)
+# define STM32_GPIOG_IDR (STM32_GPIOG_BASE+STM32_GPIO_IDR_OFFSET)
+# define STM32_GPIOG_ODR (STM32_GPIOG_BASE+STM32_GPIO_ODR_OFFSET)
+# define STM32_GPIOG_BSRR (STM32_GPIOG_BASE+STM32_GPIO_BSRR_OFFSET)
+# define STM32_GPIOG_BRR (STM32_GPIOG_BASE+STM32_GPIO_BRR_OFFSET)
+# define STM32_GPIOG_LCKR (STM32_GPIOG_BASE+STM32_GPIO_LCKR_OFFSET)
+#endif
+
+#define STM32_AFIO_EVCR (STM32_AFIO_BASE+STM32_AFIO_EVCR_OFFSET)
+#define STM32_AFIO_MAPR (STM32_AFIO_BASE+STM32_AFIO_MAPR_OFFSET)
+#define STM32_AFIO_EXTICR(p) (STM32_AFIO_BASE+STM32_AFIO_EXTICR_OFFSET(p))
+#define STM32_AFIO_EXTICR1 (STM32_AFIO_BASE+STM32_AFIO_EXTICR1_OFFSET)
+#define STM32_AFIO_EXTICR2 (STM32_AFIO_BASE+STM32_AFIO_EXTICR3_OFFSET)
+#define STM32_AFIO_EXTICR3 (STM32_AFIO_BASE+STM32_AFIO_EXTICR3_OFFSET)
+#define STM32_AFIO_EXTICR4 (STM32_AFIO_BASE+STM32_AFIO_EXTICR4_OFFSET)
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* Port configuration register low */
+
+#define GPIO_CR_MODE_SHIFT(n) ((n) << 2)
+#define GPIO_CR_MODE_MASK(n) (3 << GPIO_CR_MODE_SHIFT(n))
+#define GPIO_CR_CNF_SHIFT(n) (2 + ((n) << 2))
+#define GPIO_CR_CNF_MASK(n) (3 << GPIO_CR_CNF_SHIFT(n))
+
+#define GPIO_CR_MODECNF_SHIFT(n) ((n) << 2)
+#define GPIO_CR_MODECNF_MASK(n) (0x0f << GPIO_CR_MODECNF_SHIFT(n))
+
+#define GPIO_CRL_MODE0_SHIFT (0) /* Bits 1:0: Port mode bits */
+#define GPIO_CRL_MODE0_MASK (3 << GPIO_CRL_MODE0_SHIFT)
+#define GPIO_CRL_CNF0_SHIFT (2) /* Bits 3:2: Port configuration bits */
+#define GPIO_CRL_CNF0_MASK (3 << GPIO_CRL_CNF0_SHIFT)
+#define GPIO_CRL_MODE1_SHIFT (4) /* Bits 5:4: Port mode bits */
+#define GPIO_CRL_MODE1_MASK (3 << GPIO_CRL_MODE1_SHIFT)
+#define GPIO_CRL_CNF1_SHIFT (6) /* Bits 7:6: Port configuration bits */
+#define GPIO_CRL_CNF1_MASK (3 << GPIO_CRL_CNF1_SHIFT)
+#define GPIO_CRL_MODE2_SHIFT (8) /* Bits 9:8: Port mode bits */
+#define GPIO_CRL_MODE2_MASK (3 << GPIO_CRL_MODE2_SHIFT)
+#define GPIO_CRL_CNF2_SHIFT (10) /* Bits 11:10: Port configuration bits */
+#define GPIO_CRL_CNF2_MASK (3 << GPIO_CRL_CNF2_SHIFT)
+#define GPIO_CRL_MODE3_SHIFT (12) /* Bits 13:12: Port mode bits */
+#define GPIO_CRL_MODE3_MASK (3 << GPIO_CRL_MODE3_SHIFT)
+#define GPIO_CRL_CNF3_SHIFT (14) /* Bits 15:14: Port configuration bits */
+#define GPIO_CRL_CNF3_MASK (3 << GPIO_CRL_CNF3_SHIFT)
+#define GPIO_CRL_MODE4_SHIFT (16) /* Bits 17:16: Port mode bits */
+#define GPIO_CRL_MODE4_MASK (3 << GPIO_CRL_MODE4_SHIFT)
+#define GPIO_CRL_CNF4_SHIFT (18) /* Bits 19:18: Port configuration bits */
+#define GPIO_CRL_CNF4_MASK (3 << GPIO_CRL_CNF4_SHIFT)
+#define GPIO_CRL_MODE5_SHIFT (20) /* Bits 21:20: Port mode bits */
+#define GPIO_CRL_MODE5_MASK (3 << GPIO_CRL_MODE5_SHIFT)
+#define GPIO_CRL_CNF5_SHIFT (22) /* Bits 23:22: Port configuration bits */
+#define GPIO_CRL_CNF5_MASK (3 << GPIO_CRL_CNF5_SHIFT)
+#define GPIO_CRL_MODE6_SHIFT (24) /* Bits 25:24: Port mode bits */
+#define GPIO_CRL_MODE6_MASK (3 << GPIO_CRL_MODE6_SHIFT)
+#define GPIO_CRL_CNF6_SHIFT (26) /* Bits 27:26: Port configuration bits */
+#define GPIO_CRL_CNF6_MASK (3 << GPIO_CRL_CNF6_SHIFT)
+#define GPIO_CRL_MODE7_SHIFT (28) /* Bits 29:28: Port mode bits */
+#define GPIO_CRL_MODE7_MASK (3 << GPIO_CRL_MODE7_SHIFT)
+#define GPIO_CRL_CNF7_SHIFT (30) /* Bits 31:30: Port configuration bits */
+#define GPIO_CRL_CNF7_MASK (3 << GPIO_CRL_CNF7_SHIFT)
+
+#define GPIO_CR_CNF_INANALOG (0) /* 00: Analog input mode */
+#define GPIO_CR_CNF_INFLOAT (1) /* 01: Floating input (reset state) */
+#define GPIO_CR_CNF_INPULLUD (2) /* 10: Input with pull-up / pull-down */
+
+#define GPIO_CR_CNF_OUTPP (0) /* 00: General purpose output push-pull */
+#define GPIO_CR_CNF_OUTOD (1) /* 01: General purpose output Open-drain */
+#define GPIO_CR_CNF_ALTPP (2) /* 10: Alternate function output Push-pull */
+#define GPIO_CR_CNF_ALTOD (3) /* 11: Alternate function output Open-drain */
+
+#define GPIO_CR_MODE_INRST (0) /* 00: Input mode (reset state) */
+#define GPIO_CR_MODE_OUT10MHz (1) /* 01: Output mode, max speed 10 MHz */
+#define GPIO_CR_MODE_OUT2MHz (2) /* 10: Output mode, max speed 2 MHz */
+#define GPIO_CR_MODE_OUT50MHz (3) /* 11: Output mode, max speed 50 MHz */
+
+/* Port configuration register high */
+
+#define GPIO_CRH_MODE8_SHIFT (0) /* Bits 1:0: Port mode bits */
+#define GPIO_CRH_MODE8_MASK (3 << GPIO_CRH_MODE8_SHIFT)
+#define GPIO_CRH_CNF8_SHIFT (2) /* Bits 3:2: Port configuration bits */
+#define GPIO_CRH_CNF8_MASK (3 << GPIO_CRH_CNF8_SHIFT)
+#define GPIO_CRH_MODE9_SHIFT (4) /* Bits 5:4: Port mode bits */
+#define GPIO_CRH_MODE9_MASK (3 << GPIO_CRH_MODE9_SHIFT)
+#define GPIO_CRH_CNF9_SHIFT (6) /* Bits 7:6: Port configuration bits */
+#define GPIO_CRH_CNF9_MASK (3 << GPIO_CRH_CNF9_SHIFT)
+#define GPIO_CRH_MODE10_SHIFT (8) /* Bits 9:8: Port mode bits */
+#define GPIO_CRH_MODE10_MASK (3 << GPIO_CRH_MODE10_SHIFT)
+#define GPIO_CRH_CNF10_SHIFT (10) /* Bits 11:10: Port configuration bits */
+#define GPIO_CRH_CNF10_MASK (3 << GPIO_CRH_CNF10_SHIFT)
+#define GPIO_CRH_MODE11_SHIFT (12) /* Bits 13:12: Port mode bits */
+#define GPIO_CRH_MODE11_MASK (3 << GPIO_CRH_MODE11_SHIFT)
+#define GPIO_CRH_CNF11_SHIFT (14) /* Bits 15:14: Port configuration bits */
+#define GPIO_CRH_CNF11_MASK (3 << GPIO_CRH_CNF11_SHIFT)
+#define GPIO_CRH_MODE12_SHIFT (16) /* Bits 17:16: Port mode bits */
+#define GPIO_CRH_MODE12_MASK (3 << GPIO_CRH_MODE12_SHIFT)
+#define GPIO_CRH_CNF12_SHIFT (18) /* Bits 19:18: Port configuration bits */
+#define GPIO_CRH_CNF12_MASK (3 << GPIO_CRH_CNF12_SHIFT)
+#define GPIO_CRH_MODE13_SHIFT (20) /* Bits 21:20: Port mode bits */
+#define GPIO_CRH_MODE13_MASK (3 << GPIO_CRH_MODE13_SHIFT)
+#define GPIO_CRH_CNF13_SHIFT (22) /* Bits 23:22: Port configuration bits */
+#define GPIO_CRH_CNF13_MASK (3 << GPIO_CRH_CNF13_SHIFT)
+#define GPIO_CRH_MODE14_SHIFT (24) /* Bits 25:24: Port mode bits */
+#define GPIO_CRH_MODE14_MASK (3 << GPIO_CRH_MODE14_SHIFT)
+#define GPIO_CRH_CNF14_SHIFT (26) /* Bits 27:26: Port configuration bits */
+#define GPIO_CRH_CNF14_MASK (3 << GPIO_CRH_CNF14_SHIFT)
+#define GPIO_CRH_MODE15_SHIFT (28) /* Bits 29:28: Port mode bits */
+#define GPIO_CRH_MODE15_MASK (3 << GPIO_CRH_MODE15_SHIFT)
+#define GPIO_CRH_CNF15_SHIFT (30) /* Bits 31:30: Port configuration bits */
+#define GPIO_CRL_CNF15_MASK (3 << GPIO_CRL_CNF15_SHIFT)
+
+/* Port input/ouput data register */
+
+#define GPIO_IDR(n) (1 << (n))
+#define GPIO_ODR(n) (1 << (n))
+
+/* Port bit set/reset register */
+
+#define GPIO_BSRR_RESET(n) (1 << ((n)+16))
+#define GPIO_BSRR_SET(n) (1 << (n))
+#define GPIO_BRR(n) (1 << (n))
+
+/* Port configuration lock register */
+
+#define GPIO_LCKR_LCKK (1 << 16) /* Bit 16: Lock key */
+#define GPIO_LCKR_LCK(n) (1 << (n))
+
+/* Event control register */
+
+#define AFIO_EVCR_PIN_SHIFT (0) /* Bits 3-0: Pin selection */
+#define AFIO_EVCR_PIN_MASK (0x0f << AFIO_EVCR_PIN_SHIFT)
+#define AFIO_EVCR_PORT_SHIFT (4) /* Bits 6-4: Port selection */
+#define AFIO_EVCR_PORT_MASK (7 << AFIO_EVCR_PORT_SHIFT)
+# define AFIO_EVCR_PORTA (0 << AFIO_EVCR_PORT_SHIFT) /* 000: PA selected */
+# define AFIO_EVCR_PORTB (1 << AFIO_EVCR_PORT_SHIFT) /* 001: PB selected */
+# define AFIO_EVCR_PORTC (2 << AFIO_EVCR_PORT_SHIFT) /* 010: PC selected */
+# define AFIO_EVCR_PORTD (3 << AFIO_EVCR_PORT_SHIFT) /* 011: PD selected */
+# define AFIO_EVCR_PORTE (4 << AFIO_EVCR_PORT_SHIFT) /* 100: PE selected */
+#define AFIO_EVCR_EVOE (1 << 7) /* Bit 7: Event Output Enable */
+
+/* AF remap and debug I/O configuration register */
+
+#define AFIO_MAPR_SWJ_CFG_SHIFT (24) /* Bits 26-24: Serial Wire JTAG configuration*/
+#define AFIO_MAPR_SWJ_CFG_MASK (7 << AFIO_MAPR_SWJ_CFG_SHIFT)
+# define AFIO_MAPR_SWJRST (0 << AFIO_MAPR_SWJ_CFG_SHIFT) /* 000: Full SWJ (JTAG-DP + SW-DP): Reset State */
+# define AFIO_MAPR_SWJ (1 << AFIO_MAPR_SWJ_CFG_SHIFT) /* 001: Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
+# define AFIO_MAPR_SWDP (2 << AFIO_MAPR_SWJ_CFG_SHIFT) /* 010: JTAG-DP Disabled and SW-DP Enabled */
+# define AFIO_MAPR_DISAB (4 << AFIO_MAPR_SWJ_CFG_SHIFT) /* 100: JTAG-DP Disabled and SW-DP Disabled */
+#define AFIO_MAPR_PD01_REMAP (1 << 15) /* Bit 15 : Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+#define AFIO_MAPR_CAN_REMAP_SHIFT (13) /* Bits 14-13: CAN Alternate function remapping */
+#define AFIO_MAPR_CAN_REMAP_MASK (3 << AFIO_MAPR_CAN_REMAP_SHIFT)
+# define AFIO_MAPR_PA1112 (0 << AFIO_MAPR_CAN_REMAP_SHIFT) /* 00: CANRX mapped to PA11, CANTX mapped to PA12 */
+# define AFIO_MAPR_PB89 (2 << AFIO_MAPR_CAN_REMAP_SHIFT) /* 10: CANRX mapped to PB8, CANTX mapped to PB9 */
+# define AFIO_MAPR_PD01 (3 << AFIO_MAPR_CAN_REMAP_SHIFT) /* 11: CANRX mapped to PD0, CANTX mapped to PD1 */
+#define AFIO_MAPR_TIM4_REMAP (1 << 12) /* Bit 12: TIM4 remapping */
+#define AFIO_MAPR_TIM3_REMAP_SHIFT (10) /* Bits 11-10: TIM3 remapping */
+#define AFIO_MAPR_TIM3_REMAP_MASK (3 << AFIO_MAPR_TIM3_REMAP_SHIFT)
+# define AFIO_MAPR_TIM3_NOREMAP (0 << AFIO_MAPR_TIM3_REMAP_SHIFT) /* 00: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
+# define AFIO_MAPR_TIM3_PARTREMAP (2 << AFIO_MAPR_TIM3_REMAP_SHIFT) /* 10: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
+# define AFIO_MAPR_TIM3_FULLREMAP (3 << AFIO_MAPR_TIM3_REMAP_SHIFT) /* 11: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
+#define AFIO_MAPR_TIM2_REMAP_SHIFT (8) /* Bits 9-8: TIM2 remapping */
+#define AFIO_MAPR_TIM2_REMAP_MASK (3 << AFIO_MAPR_TIM2_REMAP_SHIFT)
+# define AFIO_MAPR_TIM2_NOREMAP (0 << AFIO_MAPR_TIM2_REMAP_SHIFT) /* 00: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
+# define AFIO_MAPR_TIM2_PARTREMAP1 (1 << AFIO_MAPR_TIM2_REMAP_SHIFT) /* 01: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
+# define AFIO_MAPR_TIM2_PARTREMAP2 (2 << AFIO_MAPR_TIM2_REMAP_SHIFT) /* 10: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
+# define AFIO_MAPR_TIM2_FULLREMAP (3 << AFIO_MAPR_TIM2_REMAP_SHIFT) /* 11: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
+#define AFIO_MAPR_TIM1_REMAP_SHIFT (6) /* Bits 7-6: TIM1 remapping */
+#define AFIO_MAPR_TIM1_REMAP_MASK (3 << AFIO_MAPR_TIM1_REMAP_SHIFT)
+# define AFIO_MAPR_TIM1_NOREMAP (0 << AFIO_MAPR_TIM1_REMAP_SHIFT) /* 00: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
+# define AFIO_MAPR_TIM1_PARTREMAP (1 << AFIO_MAPR_TIM1_REMAP_SHIFT) /* 01: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
+# define AFIO_MAPR_TIM1_FULLREMAP (3 << AFIO_MAPR_TIM1_REMAP_SHIFT) /* 11: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
+#define AFIO_MAPR_USART3_REMAP_SHIFT (6) /* Bits 5-4: USART3 remapping */
+#define AFIO_MAPR_USART3_REMAP_MASK (3 << AFIO_MAPR_USART3_REMAP_SHIFT)
+# define AFIO_MAPR_USART3_NOREMAP (0 << AFIO_MAPR_USART3_REMAP_SHIFT) /* 00: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
+# define AFIO_MAPR_USART3_PARTREMAP (1 << AFIO_MAPR_USART3_REMAP_SHIFT) /* 01: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
+# define AFIO_MAPR_USART3_FULLREMAP (3 << AFIO_MAPR_USART3_REMAP_SHIFT) /* 11: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
+#define AFIO_MAPR_USART2_REMAP (1 << 3) /* Bit 3: USART2 remapping */
+#define AFIO_MAPR_USART1_REMAP (1 << 2) /* Bit 2: USART1 remapping */
+#define AFIO_MAPR_I2C1_REMAP (1 << 1) /* Bit 1: I2C1 remapping */
+#define AFIO_MAPR_SPI1_REMAP (1 << 0) /* Bit 0: SPI1 remapping */
+
+/* External interrupt configuration register 1 */
+
+#define AFIO_EXTICR_PORT_MASK (0x0f)
+#define AFIO_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2)
+#define AFIO_EXTICR_EXTI_MASK(g) (AFIO_EXTICR_PORT_MASK << (AFIO_EXTICR_EXTI_SHIFT(g)))
+
+#define AFIO_EXTICR1_EXTI0_SHIFT (0) /* Bits 3-0: EXTI 0 configuration */
+#define AFIO_EXTICR1_EXTI0_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR1_EXTI0_SHIFT)
+#define AFIO_EXTICR1_EXTI1_SHIFT (4) /* Bits 7-4: EXTI 1 configuration */
+#define AFIO_EXTICR1_EXTI1_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR1_EXTI1_SHIFT)
+#define AFIO_EXTICR1_EXTI2_SHIFT (8) /* Bits 11-8: EXTI 2 configuration */
+#define AFIO_EXTICR1_EXTI2_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR1_EXTI2_SHIFT)
+#define AFIO_EXTICR1_EXTI3_SHIFT (12) /* Bits 15-12: EXTI 3 configuration */
+#define AFIO_EXTICR1_EXTI3_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR1_EXTI3_SHIFT)
+
+#define AFIO_EXTICR_PORTA (0) /* 0000: PA[x] pin */
+#define AFIO_EXTICR_PORTB (1) /* 0001: PB[x] pin */
+#define AFIO_EXTICR_PORTC (2) /* 0010: PC[x] pin */
+#define AFIO_EXTICR_PORTD (3) /* 0011: PD[x] pin */
+#define AFIO_EXTICR_PORTE (4) /* 0100: PE[x] pin */
+#define AFIO_EXTICR_PORTF (5) /* 0101: PF[x] pin */
+#define AFIO_EXTICR_PORTG (6) /* 0110: PG[x] pin */
+
+/* External interrupt configuration register 2 */
+
+#define AFIO_EXTICR2_EXTI4_SHIFT (0) /* Bits 3-0: EXTI 4 configuration */
+#define AFIO_EXTICR2_EXTI4_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR2_EXTI4_SHIFT)
+#define AFIO_EXTICR2_EXTI5_SHIFT (4) /* Bits 7-4: EXTI 5 configuration */
+#define AFIO_EXTICR2_EXTI5_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR2_EXTI5_SHIFT)
+#define AFIO_EXTICR2_EXTI6_SHIFT (8) /* Bits 11-8: EXTI 6 configuration */
+#define AFIO_EXTICR2_EXTI6_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR2_EXTI6_SHIFT)
+#define AFIO_EXTICR2_EXTI7_SHIFT (12) /* Bits 15-12: EXTI 7 configuration */
+#define AFIO_EXTICR2_EXTI7_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR2_EXTI7_SHIFT)
+
+/* External interrupt configuration register 3 */
+
+#define AFIO_EXTICR3_EXTI8_SHIFT (0) /* Bits 3-0: EXTI 8 configuration */
+#define AFIO_EXTICR3_EXTI8_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR3_EXTI8_SHIFT)
+#define AFIO_EXTICR3_EXTI9_SHIFT (4) /* Bits 7-4: EXTI 9 configuration */
+#define AFIO_EXTICR3_EXTI9_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR3_EXTI9_SHIFT)
+#define AFIO_EXTICR3_EXTI10_SHIFT (8) /* Bits 11-8: EXTI 10 configuration */
+#define AFIO_EXTICR3_EXTI10_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR3_EXTI10_SHIFT)
+#define AFIO_EXTICR3_EXTI11_SHIFT (12) /* Bits 15-12: EXTI 11 configuration */
+#define AFIO_EXTICR3_EXTI11_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR3_EXTI11_SHIFT)
+
+/* External interrupt configuration register 4 */
+
+#define AFIO_EXTICR4_EXTI12_SHIFT (0) /* Bits 3-0: EXTI 12 configuration */
+#define AFIO_EXTICR4_EXTI12_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR4_EXTI12_SHIFT)
+#define AFIO_EXTICR4_EXTI13_SHIFT (4) /* Bits 7-4: EXTI 13 configuration */
+#define AFIO_EXTICR4_EXTI13_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR4_EXTI13_SHIFT)
+#define AFIO_EXTICR4_EXTI14_SHIFT (8) /* Bits 11-8: EXTI 14 configuration */
+#define AFIO_EXTICR4_EXTI14_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR4_EXTI14_SHIFT)
+#define AFIO_EXTICR4_EXTI15_SHIFT (12) /* Bits 15-12: EXTI 15 configuration */
+#define AFIO_EXTICR4_EXTI15_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR4_EXTI15_SHIFT)
+
+#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_GPIO_H */
diff --git a/arch/arm/src/stm32/stm32_gpio.c b/arch/arm/src/stm32/stm32_gpio.c
index 66186f11673a92f082fdb9776ecb101f13ad6bee..963e6286eb8750df44fe81e63ccdd3a740e0d51a 100755
--- a/arch/arm/src/stm32/stm32_gpio.c
+++ b/arch/arm/src/stm32/stm32_gpio.c
@@ -33,9 +33,10 @@
*
****************************************************************************/
-/****************************************************************************
- * Included Files
- ****************************************************************************/
+/** \file
+ * \author Gregory Nutt <spudmonkey@racsa.co.cr>
+ * \brief STM32 GPIO
+ **/
#include <nuttx/config.h>
@@ -50,13 +51,6 @@
#include "stm32_rcc.h"
#include "stm32_internal.h"
-/****************************************************************************
- * Pre-processor Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Types
- ****************************************************************************/
/****************************************************************************
* Private Data
@@ -91,23 +85,12 @@ static const uint32_t g_gpiobase[STM32_NGPIO_PORTS] =
static const char g_portchar[8] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
#endif
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Global Functions
- ****************************************************************************/
/****************************************************************************
- * Name: stm32_configgpio
- *
- * Description:
- * Configure a GPIO pin based on bit-encoded description of the pin.
- *
+ * Private Functions
****************************************************************************/
-int stm32_configgpio(uint32_t cfgset)
+int stm32_gpio_configlock(uint32_t cfgset, bool altlock)
{
uint32_t base;
uint32_t cr;
@@ -146,23 +129,44 @@ int stm32_configgpio(uint32_t cfgset)
cr = base + STM32_GPIO_CRH_OFFSET;
pos = pin - 8;
}
-
+
/* Input or output? */
input = ((cfgset & GPIO_INPUT) != 0);
/* Decode the mode and configuration */
+
+ regval = getreg32(cr);
+
+ /* Is present (old) config already in GPIO_ALT? and we got request to
+ * lock the alternative configuration. If so we allow the following
+ * changes only:
+ * - to HiZ (unlocking the configuration)
+ * - AFPP
+ * - AFOD
+ */
+
+ uint32_t oldmode = (regval >> GPIO_CR_MODECNF_SHIFT(pos));
+ if (altlock &&
+ (oldmode & (GPIO_MODE_MASK >> GPIO_MODE_SHIFT)) && /* previous state was output? */
+ ((oldmode>>2) & GPIO_CR_CNF_ALTOD) > GPIO_CR_CNF_OUTOD && /* previous state is ALT? */
+ ( ((cfgset & GPIO_CNF_MASK) >> GPIO_CNF_SHIFT) < GPIO_CR_CNF_ALTPP || /* new state is not output ALT? */
+ input ) ) /* or it is input */
+ {
+ return ERROR;
+ }
+
if (input)
{
/* Input.. force mode = INPUT */
modecnf = 0;
- }
+ }
else
{
/* Output or alternate function */
-
+
modecnf = (cfgset & GPIO_MODE_MASK) >> GPIO_MODE_SHIFT;
}
@@ -170,7 +174,6 @@ int stm32_configgpio(uint32_t cfgset)
/* Set the port configuration register */
- regval = getreg32(cr);
regval &= ~(GPIO_CR_MODECNF_MASK(pos));
regval |= (modecnf << GPIO_CR_MODECNF_SHIFT(pos));
putreg32(regval, cr);
@@ -241,6 +244,139 @@ int stm32_configgpio(uint32_t cfgset)
return OK;
}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+void stm32_gpio_remap(void)
+{
+ uint32_t val = 0;
+
+#ifdef CONFIG_STM32_JTAG_FULL_ENABLE
+ // the reset default
+#elif CONFIG_STM32_JTAG_NOJNTRST_ENABLE
+ val |= AFIO_MAPR_SWJ; /* enabled but without JNTRST */
+#elif CONFIG_STM32_JTAG_SW_ENABLE
+ val |= AFIO_MAPR_SWDP; /* set JTAG-DP disabled and SW-DP enabled */
+#else
+ val |= AFIO_MAPR_DISAB; /* set JTAG-DP and SW-DP Disabled */
+#endif
+
+#ifdef CONFIG_STM32_TIM1_FULL_REMAP
+ val |= AFIO_MAPR_TIM1_FULLREMAP;
+#endif
+#ifdef CONFIG_STM32_TIM1_PARTIAL_REMAP
+ val |= AFIO_MAPR_TIM1_PARTREMAP;
+#endif
+#ifdef CONFIG_STM32_TIM2_FULL_REMAP
+ val |= AFIO_MAPR_TIM2_FULLREMAP;
+#endif
+#ifdef CONFIG_STM32_TIM2_PARTIAL_REMAP_1
+ val |= AFIO_MAPR_TIM2_PARTREMAP1;
+#endif
+#ifdef CONFIG_STM32_TIM2_PARTIAL_REMAP_2
+ val |= AFIO_MAPR_TIM2_PARTREMAP2;
+#endif
+#ifdef CONFIG_STM32_TIM3_FULL_REMAP
+ val |= AFIO_MAPR_TIM3_FULLREMAP;
+#endif
+#ifdef CONFIG_STM32_TIM3_PARTIAL_REMAP
+ val |= AFIO_MAPR_TIM3_PARTREMAP;
+#endif
+#ifdef CONFIG_STM32_TIM4_REMAP
+ val |= AFIO_MAPR_TIM4_REMAP;
+#endif
+
+#ifdef CONFIG_STM32_USART1_REMAP
+ val |= AFIO_MAPR_USART1_REMAP;
+#endif
+#ifdef CONFIG_STM32_USART2_REMAP
+ val |= AFIO_MAPR_USART2_REMAP;
+#endif
+#ifdef CONFIG_STM32_USART3_FULL_REMAP
+ val |= AFIO_MAPR_USART3_FULLREMAP;
+#endif
+#ifdef CONFIG_STM32_USART3_PARTIAL_REMAP
+ val |= AFIO_MAPR_USART3_PARTREMAP;
+#endif
+
+#ifdef CONFIG_STM32_SPI1_REMAP
+ val |= AFIO_MAPR_SPI1_REMAP;
+#endif
+#ifdef CONFIG_STM32_SPI3_REMAP
+#endif
+
+#ifdef CONFIG_STM32_I2C1_REMAP
+ val |= AFIO_MAPR_I2C1_REMAP;
+#endif
+
+#ifdef CONFIG_STM32_CAN1_REMAP1
+ val |= AFIO_MAPR_PB89;
+#endif
+#ifdef CONFIG_STM32_CAN1_REMAP2
+ val |= AFIO_MAPR_PD01;
+#endif
+
+ putreg32(val, STM32_AFIO_MAPR);
+}
+
+
+/************************************************************************************
+ * Name: stm32_configgpio
+ *
+ * Description:
+ * Configure a GPIO pin based on bit-encoded description of the pin.
+ * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...)
+ * function, it must be unconfigured with stm32_unconfiggpio() with
+ * the same cfgset first before it can be set to non-alternative function.
+ *
+ * Returns:
+ * OK on success
+ * ERROR on invalid port, or when pin is locked as ALT function.
+ *
+ * \todo Auto Power Enable
+ ************************************************************************************/
+
+int stm32_configgpio(uint32_t cfgset)
+{
+ return stm32_gpio_configlock(cfgset, true);
+}
+
+
+/************************************************************************************
+ * Name: stm32_unconfiggpio
+ *
+ * Description:
+ * Unconfigure a GPIO pin based on bit-encoded description of the pin, set it
+ * into default HiZ state (and possibly mark it's unused) and unlock it whether
+ * it was previsouly selected as alternative function (GPIO_ALT|GPIO_CNF_AFPP|...).
+ *
+ * This is a safety function and prevents hardware from schocks, as unexpected
+ * write to the Timer Channel Output GPIO to fixed '1' or '0' while it should
+ * operate in PWM mode could produce excessive on-board currents and trigger
+ * over-current/alarm function.
+ *
+ * Returns:
+ * OK on success
+ * ERROR on invalid port
+ *
+ * \todo Auto Power Disable
+ ************************************************************************************/
+
+int stm32_unconfiggpio(uint32_t cfgset)
+{
+ /* Reuse port and pin number and set it to default HiZ INPUT */
+
+ cfgset &= GPIO_PORT_MASK | GPIO_PIN_MASK;
+ cfgset |= GPIO_INPUT | GPIO_CNF_INFLOAT | GPIO_MODE_INPUT;
+
+ /* \todo : Mark its unuse for automatic power saving options */
+
+ return stm32_gpio_configlock(cfgset, false);
+}
+
+
/****************************************************************************
* Name: stm32_gpiowrite
*
@@ -357,6 +493,3 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg)
return OK;
}
#endif
-
-
-
diff --git a/arch/arm/src/stm32/stm32_gpio.h b/arch/arm/src/stm32/stm32_gpio.h
index 3061b6b81712ce1239d410c324261800d20acfb4..abced530451f7dedf57234e04d6b18dd80aa78d4 100644
--- a/arch/arm/src/stm32/stm32_gpio.h
+++ b/arch/arm/src/stm32/stm32_gpio.h
@@ -36,348 +36,219 @@
#ifndef __ARCH_ARM_SRC_STM32_STM32_GPIO_H
#define __ARCH_ARM_SRC_STM32_STM32_GPIO_H
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
#include <nuttx/config.h>
#include "chip.h"
+#include "chip/stm32_gpio.h"
+
/************************************************************************************
- * Pre-processor Definitions
+ * Pre-Processor Declarations
************************************************************************************/
-#define STM32_NGPIO_PORTS ((STM32_NGPIO + 15) >> 4)
-
-/* Register Offsets *****************************************************************/
-
-#define STM32_GPIO_CRL_OFFSET 0x0000 /* Port configuration register low */
-#define STM32_GPIO_CRH_OFFSET 0x0004 /* Port configuration register high */
-#define STM32_GPIO_IDR_OFFSET 0x0008 /* Port input data register */
-#define STM32_GPIO_ODR_OFFSET 0x000c /* Port output data register */
-#define STM32_GPIO_BSRR_OFFSET 0x0010 /* Port bit set/reset register */
-#define STM32_GPIO_BRR_OFFSET 0x0014 /* Port bit reset register */
-#define STM32_GPIO_LCKR_OFFSET 0x0018 /* Port configuration lock register */
-
-#define STM32_AFIO_EVCR_OFFSET 0x0000 /* Event control register */
-#define STM32_AFIO_MAPR_OFFSET 0x0004 /* AF remap and debug I/O configuration register */
-#define STM32_AFIO_EXTICR_OFFSET(p) (0x0008 + ((p) >> 2))
-#define STM32_AFIO_EXTICR1_OFFSET 0x0008 /* External interrupt configuration register 1 */
-#define STM32_AFIO_EXTICR2_OFFSET 0x000c /* External interrupt configuration register 2 */
-#define STM32_AFIO_EXTICR3_OFFSET 0x0010 /* External interrupt configuration register 3 */
-#define STM32_AFIO_EXTICR4_OFFSET 0x0014 /* External interrupt configuration register 4 */
-
-/* Register Addresses ***************************************************************/
-
-#if STM32_NGPIO_PORTS > 0
-# define STM32_GPIOA_CRL (STM32_GPIOA_BASE+STM32_GPIO_CRL_OFFSET)
-# define STM32_GPIOA_CRH (STM32_GPIOA_BASE+STM32_GPIO_CRH_OFFSET)
-# define STM32_GPIOA_IDR (STM32_GPIOA_BASE+STM32_GPIO_IDR_OFFSET)
-# define STM32_GPIOA_ODR (STM32_GPIOA_BASE+STM32_GPIO_ODR_OFFSET)
-# define STM32_GPIOA_BSRR (STM32_GPIOA_BASE+STM32_GPIO_BSRR_OFFSET)
-# define STM32_GPIOA_BRR (STM32_GPIOA_BASE+STM32_GPIO_BRR_OFFSET)
-# define STM32_GPIOA_LCKR (STM32_GPIOA_BASE+STM32_GPIO_LCKR_OFFSET)
-#endif
+#ifndef __ASSEMBLY__
-#if STM32_NGPIO_PORTS > 1
-# define STM32_GPIOB_CRL (STM32_GPIOB_BASE+STM32_GPIO_CRL_OFFSET)
-# define STM32_GPIOB_CRH (STM32_GPIOB_BASE+STM32_GPIO_CRH_OFFSET)
-# define STM32_GPIOB_IDR (STM32_GPIOB_BASE+STM32_GPIO_IDR_OFFSET)
-# define STM32_GPIOB_ODR (STM32_GPIOB_BASE+STM32_GPIO_ODR_OFFSET)
-# define STM32_GPIOB_BSRR (STM32_GPIOB_BASE+STM32_GPIO_BSRR_OFFSET)
-# define STM32_GPIOB_BRR (STM32_GPIOB_BASE+STM32_GPIO_BRR_OFFSET)
-# define STM32_GPIOB_LCKR (STM32_GPIOB_BASE+STM32_GPIO_LCKR_OFFSET)
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
#endif
+
+ /* Bit-encoded input to stm32_configgpio()
+ * These definitions could be replaced by 'enum' as a stm32_gpio_t data type.
+ */
-#if STM32_NGPIO_PORTS > 2
-# define STM32_GPIOC_CRL (STM32_GPIOC_BASE+STM32_GPIO_CRL_OFFSET)
-# define STM32_GPIOC_CRH (STM32_GPIOC_BASE+STM32_GPIO_CRH_OFFSET)
-# define STM32_GPIOC_IDR (STM32_GPIOC_BASE+STM32_GPIO_IDR_OFFSET)
-# define STM32_GPIOC_ODR (STM32_GPIOC_BASE+STM32_GPIO_ODR_OFFSET)
-# define STM32_GPIOC_BSRR (STM32_GPIOC_BASE+STM32_GPIO_BSRR_OFFSET)
-# define STM32_GPIOC_BRR (STM32_GPIOC_BASE+STM32_GPIO_BRR_OFFSET)
-# define STM32_GPIOC_LCKR (STM32_GPIOC_BASE+STM32_GPIO_LCKR_OFFSET)
-#endif
+/* 16-bit Encoding:
+ * OFFS SX.. VPPP BBBB
+ */
-#if STM32_NGPIO_PORTS > 3
-# define STM32_GPIOD_CRL (STM32_GPIOD_BASE+STM32_GPIO_CRL_OFFSET)
-# define STM32_GPIOD_CRH (STM32_GPIOD_BASE+STM32_GPIO_CRH_OFFSET)
-# define STM32_GPIOD_IDR (STM32_GPIOD_BASE+STM32_GPIO_IDR_OFFSET)
-# define STM32_GPIOD_ODR (STM32_GPIOD_BASE+STM32_GPIO_ODR_OFFSET)
-# define STM32_GPIOD_BSRR (STM32_GPIOD_BASE+STM32_GPIO_BSRR_OFFSET)
-# define STM32_GPIOD_BRR (STM32_GPIOD_BASE+STM32_GPIO_BRR_OFFSET)
-# define STM32_GPIOD_LCKR (STM32_GPIOD_BASE+STM32_GPIO_LCKR_OFFSET)
-#endif
+/* Output mode:
+ *
+ * O... .... .... ....
+ */
-#if STM32_NGPIO_PORTS > 4
-# define STM32_GPIOE_CRL (STM32_GPIOE_BASE+STM32_GPIO_CRL_OFFSET)
-# define STM32_GPIOE_CRH (STM32_GPIOE_BASE+STM32_GPIO_CRH_OFFSET)
-# define STM32_GPIOE_IDR (STM32_GPIOE_BASE+STM32_GPIO_IDR_OFFSET)
-# define STM32_GPIOE_ODR (STM32_GPIOE_BASE+STM32_GPIO_ODR_OFFSET)
-# define STM32_GPIOE_BSRR (STM32_GPIOE_BASE+STM32_GPIO_BSRR_OFFSET)
-# define STM32_GPIOE_BRR (STM32_GPIOE_BASE+STM32_GPIO_BRR_OFFSET)
-# define STM32_GPIOE_LCKR (STM32_GPIOE_BASE+STM32_GPIO_LCKR_OFFSET)
-#endif
+#define GPIO_INPUT (1 << 15) /* Bit 15: 1=Input mode */
+#define GPIO_OUTPUT (0) /* 0=Output or alternate function */
+#define GPIO_ALT (0)
-#if STM32_NGPIO_PORTS > 5
-# define STM32_GPIOF_CRL (STM32_GPIOF_BASE+STM32_GPIO_CRL_OFFSET)
-# define STM32_GPIOF_CRH (STM32_GPIOF_BASE+STM32_GPIO_CRH_OFFSET)
-# define STM32_GPIOF_IDR (STM32_GPIOF_BASE+STM32_GPIO_IDR_OFFSET)
-# define STM32_GPIOF_ODR (STM32_GPIOF_BASE+STM32_GPIO_ODR_OFFSET)
-# define STM32_GPIOF_BSRR (STM32_GPIOF_BASE+STM32_GPIO_BSRR_OFFSET)
-# define STM32_GPIOF_BRR (STM32_GPIOF_BASE+STM32_GPIO_BRR_OFFSET)
-# define STM32_GPIOF_LCKR (STM32_GPIOF_BASE+STM32_GPIO_LCKR_OFFSET)
-#endif
+/* If the pin is a GPIO digital output, then this identifies the initial output value.
+ * If the pin is an input, this bit is overloaded to provide the qualifier to\
+ * distinquish input pull-up and -down:
+ *
+ * .... .... V... ....
+ */
+
+#define GPIO_OUTPUT_SET (1 << 7) /* Bit 7: If output, inital value of output */
+#define GPIO_OUTPUT_CLEAR (0)
+
+/* These bits set the primary function of the pin:
+ * .FF. .... .... ....
+ */
+
+#define GPIO_CNF_SHIFT 13 /* Bits 13-14: GPIO function */
+#define GPIO_CNF_MASK (3 << GPIO_CNF_SHIFT)
+
+# define GPIO_CNF_ANALOGIN (0 << GPIO_CNF_SHIFT) /* Analog input */
+# define GPIO_CNF_INFLOAT (1 << GPIO_CNF_SHIFT) /* Input floating */
+# define GPIO_CNF_INPULLUD (2 << GPIO_CNF_SHIFT) /* Input pull-up/down general bit, since up is composed of two parts */
+# define GPIO_CNF_INPULLDWN (2 << GPIO_CNF_SHIFT) /* Input pull-down */
+# define GPIO_CNF_INPULLUP ((2 << GPIO_CNF_SHIFT) | GPIO_OUTPUT_SET) /* Input pull-up */
+
+# define GPIO_CNF_OUTPP (0 << GPIO_CNF_SHIFT) /* Output push-pull */
+# define GPIO_CNF_OUTOD (1 << GPIO_CNF_SHIFT) /* Output open-drain */
+# define GPIO_CNF_AFPP (2 << GPIO_CNF_SHIFT) /* Alternate function push-pull */
+# define GPIO_CNF_AFOD (3 << GPIO_CNF_SHIFT) /* Alternate function open-drain */
+
+/* Maximum frequency selection:
+ * ...S S... .... ....
+ */
+
+#define GPIO_MODE_SHIFT 11 /* Bits 11-12: GPIO frequency selection */
+#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT)
+# define GPIO_MODE_INPUT (0 << GPIO_MODE_SHIFT) /* Input mode (reset state) */
+# define GPIO_MODE_10MHz (1 << GPIO_MODE_SHIFT) /* Output mode, max speed 10 MHz */
+# define GPIO_MODE_2MHz (2 << GPIO_MODE_SHIFT) /* Output mode, max speed 2 MHz */
+# define GPIO_MODE_50MHz (3 << GPIO_MODE_SHIFT) /* Output mode, max speed 50 MHz */
+
+/* External interrupt selection (GPIO inputs only):
+ * .... .X.. .... ....
+ */
+
+#define GPIO_EXTI (1 << 10) /* Bit 10: Configure as EXTI interrupt */
+
+/* This identifies the GPIO port:
+ * .... .... .PPP ....
+ */
+
+#define GPIO_PORT_SHIFT 4 /* Bit 4-6: Port number */
+#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT)
+#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */
+#define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */
+#define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */
+#define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */
+#define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */
+#define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */
+#define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */
+
+/* This identifies the bit in the port:
+ * .... .... .... BBBB
+ */
+
+#define GPIO_PIN_SHIFT 0 /* Bits 0-3: GPIO number: 0-15 */
+#define GPIO_PIN_MASK (15 << GPIO_PIN_SHIFT)
+#define GPIO_PIN0 (0 << GPIO_PIN_SHIFT)
+#define GPIO_PIN1 (1 << GPIO_PIN_SHIFT)
+#define GPIO_PIN2 (2 << GPIO_PIN_SHIFT)
+#define GPIO_PIN3 (3 << GPIO_PIN_SHIFT)
+#define GPIO_PIN4 (4 << GPIO_PIN_SHIFT)
+#define GPIO_PIN5 (5 << GPIO_PIN_SHIFT)
+#define GPIO_PIN6 (6 << GPIO_PIN_SHIFT)
+#define GPIO_PIN7 (7 << GPIO_PIN_SHIFT)
+#define GPIO_PIN8 (8 << GPIO_PIN_SHIFT)
+#define GPIO_PIN9 (9 << GPIO_PIN_SHIFT)
+#define GPIO_PIN10 (10 << GPIO_PIN_SHIFT)
+#define GPIO_PIN11 (11 << GPIO_PIN_SHIFT)
+#define GPIO_PIN12 (12 << GPIO_PIN_SHIFT)
+#define GPIO_PIN13 (13 << GPIO_PIN_SHIFT)
+#define GPIO_PIN14 (14 << GPIO_PIN_SHIFT)
+#define GPIO_PIN15 (15 << GPIO_PIN_SHIFT)
-#if STM32_NGPIO_PORTS > 6
-# define STM32_GPIOG_CRL (STM32_GPIOG_BASE+STM32_GPIO_CRL_OFFSET)
-# define STM32_GPIOG_CRH (STM32_GPIOG_BASE+STM32_GPIO_CRH_OFFSET)
-# define STM32_GPIOG_IDR (STM32_GPIOG_BASE+STM32_GPIO_IDR_OFFSET)
-# define STM32_GPIOG_ODR (STM32_GPIOG_BASE+STM32_GPIO_ODR_OFFSET)
-# define STM32_GPIOG_BSRR (STM32_GPIOG_BASE+STM32_GPIO_BSRR_OFFSET)
-# define STM32_GPIOG_BRR (STM32_GPIOG_BASE+STM32_GPIO_BRR_OFFSET)
-# define STM32_GPIOG_LCKR (STM32_GPIOG_BASE+STM32_GPIO_LCKR_OFFSET)
-#endif
-#define STM32_AFIO_EVCR (STM32_AFIO_BASE+STM32_AFIO_EVCR_OFFSET)
-#define STM32_AFIO_MAPR (STM32_AFIO_BASE+STM32_AFIO_MAPR_OFFSET)
-#define STM32_AFIO_EXTICR(p) (STM32_AFIO_BASE+STM32_AFIO_EXTICR_OFFSET(p))
-#define STM32_AFIO_EXTICR1 (STM32_AFIO_BASE+STM32_AFIO_EXTICR1_OFFSET)
-#define STM32_AFIO_EXTICR2 (STM32_AFIO_BASE+STM32_AFIO_EXTICR3_OFFSET)
-#define STM32_AFIO_EXTICR3 (STM32_AFIO_BASE+STM32_AFIO_EXTICR3_OFFSET)
-#define STM32_AFIO_EXTICR4 (STM32_AFIO_BASE+STM32_AFIO_EXTICR4_OFFSET)
-
-/* Register Bitfield Definitions ****************************************************/
-
-/* Port configuration register low */
-
-#define GPIO_CR_MODE_SHIFT(n) ((n) << 2)
-#define GPIO_CR_MODE_MASK(n) (3 << GPIO_CR_MODE_SHIFT(n))
-#define GPIO_CR_CNF_SHIFT(n) (2 + ((n) << 2))
-#define GPIO_CR_CNF_MASK(n) (3 << GPIO_CR_CNF_SHIFT(n))
-
-#define GPIO_CR_MODECNF_SHIFT(n) ((n) << 2)
-#define GPIO_CR_MODECNF_MASK(n) (0x0f << GPIO_CR_MODECNF_SHIFT(n))
-
-#define GPIO_CRL_MODE0_SHIFT (0) /* Bits 1:0: Port mode bits */
-#define GPIO_CRL_MODE0_MASK (3 << GPIO_CRL_MODE0_SHIFT)
-#define GPIO_CRL_CNF0_SHIFT (2) /* Bits 3:2: Port configuration bits */
-#define GPIO_CRL_CNF0_MASK (3 << GPIO_CRL_CNF0_SHIFT)
-#define GPIO_CRL_MODE1_SHIFT (4) /* Bits 5:4: Port mode bits */
-#define GPIO_CRL_MODE1_MASK (3 << GPIO_CRL_MODE1_SHIFT)
-#define GPIO_CRL_CNF1_SHIFT (6) /* Bits 7:6: Port configuration bits */
-#define GPIO_CRL_CNF1_MASK (3 << GPIO_CRL_CNF1_SHIFT)
-#define GPIO_CRL_MODE2_SHIFT (8) /* Bits 9:8: Port mode bits */
-#define GPIO_CRL_MODE2_MASK (3 << GPIO_CRL_MODE2_SHIFT)
-#define GPIO_CRL_CNF2_SHIFT (10) /* Bits 11:10: Port configuration bits */
-#define GPIO_CRL_CNF2_MASK (3 << GPIO_CRL_CNF2_SHIFT)
-#define GPIO_CRL_MODE3_SHIFT (12) /* Bits 13:12: Port mode bits */
-#define GPIO_CRL_MODE3_MASK (3 << GPIO_CRL_MODE3_SHIFT)
-#define GPIO_CRL_CNF3_SHIFT (14) /* Bits 15:14: Port configuration bits */
-#define GPIO_CRL_CNF3_MASK (3 << GPIO_CRL_CNF3_SHIFT)
-#define GPIO_CRL_MODE4_SHIFT (16) /* Bits 17:16: Port mode bits */
-#define GPIO_CRL_MODE4_MASK (3 << GPIO_CRL_MODE4_SHIFT)
-#define GPIO_CRL_CNF4_SHIFT (18) /* Bits 19:18: Port configuration bits */
-#define GPIO_CRL_CNF4_MASK (3 << GPIO_CRL_CNF4_SHIFT)
-#define GPIO_CRL_MODE5_SHIFT (20) /* Bits 21:20: Port mode bits */
-#define GPIO_CRL_MODE5_MASK (3 << GPIO_CRL_MODE5_SHIFT)
-#define GPIO_CRL_CNF5_SHIFT (22) /* Bits 23:22: Port configuration bits */
-#define GPIO_CRL_CNF5_MASK (3 << GPIO_CRL_CNF5_SHIFT)
-#define GPIO_CRL_MODE6_SHIFT (24) /* Bits 25:24: Port mode bits */
-#define GPIO_CRL_MODE6_MASK (3 << GPIO_CRL_MODE6_SHIFT)
-#define GPIO_CRL_CNF6_SHIFT (26) /* Bits 27:26: Port configuration bits */
-#define GPIO_CRL_CNF6_MASK (3 << GPIO_CRL_CNF6_SHIFT)
-#define GPIO_CRL_MODE7_SHIFT (28) /* Bits 29:28: Port mode bits */
-#define GPIO_CRL_MODE7_MASK (3 << GPIO_CRL_MODE7_SHIFT)
-#define GPIO_CRL_CNF7_SHIFT (30) /* Bits 31:30: Port configuration bits */
-#define GPIO_CRL_CNF7_MASK (3 << GPIO_CRL_CNF7_SHIFT)
-
-#define GPIO_CR_CNF_INANALOG (0) /* 00: Analog input mode */
-#define GPIO_CR_CNF_INFLOAT (1) /* 01: Floating input (reset state) */
-#define GPIO_CR_CNF_INPULLUD (2) /* 10: Input with pull-up / pull-down */
-
-#define GPIO_CR_CNF_OUTPP (0) /* 00: General purpose output push-pull */
-#define GPIO_CR_CNF_OUTOD (1) /* 01: General purpose output Open-drain */
-#define GPIO_CR_CNF_ALTPP (2) /* 10: Alternate function output Push-pull */
-#define GPIO_CR_CNF_ALTOD (3) /* 11: Alternate function output Open-drain */
-
-#define GPIO_CR_MODE_INRST (0) /* 00: Input mode (reset state) */
-#define GPIO_CR_MODE_OUT10MHz (1) /* 01: Output mode, max speed 10 MHz */
-#define GPIO_CR_MODE_OUT2MHz (2) /* 10: Output mode, max speed 2 MHz */
-#define GPIO_CR_MODE_OUT50MHz (3) /* 11: Output mode, max speed 50 MHz */
-
-/* Port configuration register high */
-
-#define GPIO_CRH_MODE8_SHIFT (0) /* Bits 1:0: Port mode bits */
-#define GPIO_CRH_MODE8_MASK (3 << GPIO_CRH_MODE8_SHIFT)
-#define GPIO_CRH_CNF8_SHIFT (2) /* Bits 3:2: Port configuration bits */
-#define GPIO_CRH_CNF8_MASK (3 << GPIO_CRH_CNF8_SHIFT)
-#define GPIO_CRH_MODE9_SHIFT (4) /* Bits 5:4: Port mode bits */
-#define GPIO_CRH_MODE9_MASK (3 << GPIO_CRH_MODE9_SHIFT)
-#define GPIO_CRH_CNF9_SHIFT (6) /* Bits 7:6: Port configuration bits */
-#define GPIO_CRH_CNF9_MASK (3 << GPIO_CRH_CNF9_SHIFT)
-#define GPIO_CRH_MODE10_SHIFT (8) /* Bits 9:8: Port mode bits */
-#define GPIO_CRH_MODE10_MASK (3 << GPIO_CRH_MODE10_SHIFT)
-#define GPIO_CRH_CNF10_SHIFT (10) /* Bits 11:10: Port configuration bits */
-#define GPIO_CRH_CNF10_MASK (3 << GPIO_CRH_CNF10_SHIFT)
-#define GPIO_CRH_MODE11_SHIFT (12) /* Bits 13:12: Port mode bits */
-#define GPIO_CRH_MODE11_MASK (3 << GPIO_CRH_MODE11_SHIFT)
-#define GPIO_CRH_CNF11_SHIFT (14) /* Bits 15:14: Port configuration bits */
-#define GPIO_CRH_CNF11_MASK (3 << GPIO_CRH_CNF11_SHIFT)
-#define GPIO_CRH_MODE12_SHIFT (16) /* Bits 17:16: Port mode bits */
-#define GPIO_CRH_MODE12_MASK (3 << GPIO_CRH_MODE12_SHIFT)
-#define GPIO_CRH_CNF12_SHIFT (18) /* Bits 19:18: Port configuration bits */
-#define GPIO_CRH_CNF12_MASK (3 << GPIO_CRH_CNF12_SHIFT)
-#define GPIO_CRH_MODE13_SHIFT (20) /* Bits 21:20: Port mode bits */
-#define GPIO_CRH_MODE13_MASK (3 << GPIO_CRH_MODE13_SHIFT)
-#define GPIO_CRH_CNF13_SHIFT (22) /* Bits 23:22: Port configuration bits */
-#define GPIO_CRH_CNF13_MASK (3 << GPIO_CRH_CNF13_SHIFT)
-#define GPIO_CRH_MODE14_SHIFT (24) /* Bits 25:24: Port mode bits */
-#define GPIO_CRH_MODE14_MASK (3 << GPIO_CRH_MODE14_SHIFT)
-#define GPIO_CRH_CNF14_SHIFT (26) /* Bits 27:26: Port configuration bits */
-#define GPIO_CRH_CNF14_MASK (3 << GPIO_CRH_CNF14_SHIFT)
-#define GPIO_CRH_MODE15_SHIFT (28) /* Bits 29:28: Port mode bits */
-#define GPIO_CRH_MODE15_MASK (3 << GPIO_CRH_MODE15_SHIFT)
-#define GPIO_CRH_CNF15_SHIFT (30) /* Bits 31:30: Port configuration bits */
-#define GPIO_CRL_CNF15_MASK (3 << GPIO_CRL_CNF15_SHIFT)
-
-/* Port input/ouput data register */
-
-#define GPIO_IDR(n) (1 << (n))
-#define GPIO_ODR(n) (1 << (n))
-
-/* Port bit set/reset register */
-
-#define GPIO_BSRR_RESET(n) (1 << ((n)+16))
-#define GPIO_BSRR_SET(n) (1 << (n))
-#define GPIO_BRR(n) (1 << (n))
-
-/* Port configuration lock register */
-
-#define GPIO_LCKR_LCKK (1 << 16) /* Bit 16: Lock key */
-#define GPIO_LCKR_LCK(n) (1 << (n))
-
-/* Event control register */
-
-#define AFIO_EVCR_PIN_SHIFT (0) /* Bits 3-0: Pin selection */
-#define AFIO_EVCR_PIN_MASK (0x0f << AFIO_EVCR_PIN_SHIFT)
-#define AFIO_EVCR_PORT_SHIFT (4) /* Bits 6-4: Port selection */
-#define AFIO_EVCR_PORT_MASK (7 << AFIO_EVCR_PORT_SHIFT)
-# define AFIO_EVCR_PORTA (0 << AFIO_EVCR_PORT_SHIFT) /* 000: PA selected */
-# define AFIO_EVCR_PORTB (1 << AFIO_EVCR_PORT_SHIFT) /* 001: PB selected */
-# define AFIO_EVCR_PORTC (2 << AFIO_EVCR_PORT_SHIFT) /* 010: PC selected */
-# define AFIO_EVCR_PORTD (3 << AFIO_EVCR_PORT_SHIFT) /* 011: PD selected */
-# define AFIO_EVCR_PORTE (4 << AFIO_EVCR_PORT_SHIFT) /* 100: PE selected */
-#define AFIO_EVCR_EVOE (1 << 7) /* Bit 7: Event Output Enable */
-
-/* AF remap and debug I/O configuration register */
-
-#define AFIO_MAPR_SWJ_CFG_SHIFT (24) /* Bits 26-24: Serial Wire JTAG configuration*/
-#define AFIO_MAPR_SWJ_CFG_MASK (7 << AFIO_MAPR_SWJ_CFG_SHIFT)
-# define AFIO_MAPR_SWJRST (0 << AFIO_MAPR_SWJ_CFG_SHIFT) /* 000: Full SWJ (JTAG-DP + SW-DP): Reset State */
-# define AFIO_MAPR_SWJ (1 << AFIO_MAPR_SWJ_CFG_SHIFT) /* 001: Full SWJ (JTAG-DP + SW-DP) but without JNTRST */
-# define AFIO_MAPR_SWDP (2 << AFIO_MAPR_SWJ_CFG_SHIFT) /* 010: JTAG-DP Disabled and SW-DP Enabled */
-# define AFIO_MAPR_DISAB (4 << AFIO_MAPR_SWJ_CFG_SHIFT) /* 100: JTAG-DP Disabled and SW-DP Disabled */
-#define AFIO_MAPR_PD01_REMAP (1 << 15) /* Bit 15 : Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
-#define AFIO_MAPR_CAN_REMAP_SHIFT (13) /* Bits 14-13: CAN Alternate function remapping */
-#define AFIO_MAPR_CAN_REMAP_MASK (3 << AFIO_MAPR_CAN_REMAP_SHIFT)
-# define AFIO_MAPR_PA1112 (0 << AFIO_MAPR_CAN_REMAP_SHIFT) /* 00: CANRX mapped to PA11, CANTX mapped to PA12 */
-# define AFIO_MAPR_PB89 (2 << AFIO_MAPR_CAN_REMAP_SHIFT) /* 10: CANRX mapped to PB8, CANTX mapped to PB9 */
-# define AFIO_MAPR_PD01 (3 << AFIO_MAPR_CAN_REMAP_SHIFT) /* 11: CANRX mapped to PD0, CANTX mapped to PD1 */
-#define AFIO_MAPR_TIM4_REMAP (1 << 12) /* Bit 12: TIM4 remapping */
-#define AFIO_MAPR_TIM3_REMAP_SHIFT (10) /* Bits 11-10: TIM3 remapping */
-#define AFIO_MAPR_TIM3_REMAP_MASK (3 << AFIO_MAPR_TIM3_REMAP_SHIFT)
-# define AFIO_MAPR_TIM3_NOREMAP (0 << AFIO_MAPR_TIM3_REMAP_SHIFT) /* 00: No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */
-# define AFIO_MAPR_TIM3_PARTREMAP (2 << AFIO_MAPR_TIM3_REMAP_SHIFT) /* 10: Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */
-# define AFIO_MAPR_TIM3_FULLREMAP (3 << AFIO_MAPR_TIM3_REMAP_SHIFT) /* 11: Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */
-#define AFIO_MAPR_TIM2_REMAP_SHIFT (8) /* Bits 9-8: TIM2 remapping */
-#define AFIO_MAPR_TIM2_REMAP_MASK (3 << AFIO_MAPR_TIM2_REMAP_SHIFT)
-# define AFIO_MAPR_TIM2_NOREMAP (0 << AFIO_MAPR_TIM2_REMAP_SHIFT) /* 00: No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */
-# define AFIO_MAPR_TIM2_PARTREMAP1 (1 << AFIO_MAPR_TIM2_REMAP_SHIFT) /* 01: Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */
-# define AFIO_MAPR_TIM2_PARTREMAP2 (2 << AFIO_MAPR_TIM2_REMAP_SHIFT) /* 10: Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */
-# define AFIO_MAPR_TIM2_FULLREMAP (3 << AFIO_MAPR_TIM2_REMAP_SHIFT) /* 11: Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */
-#define AFIO_MAPR_TIM1_REMAP_SHIFT (6) /* Bits 7-6: TIM1 remapping */
-#define AFIO_MAPR_TIM1_REMAP_MASK (3 << AFIO_MAPR_TIM1_REMAP_SHIFT)
-# define AFIO_MAPR_TIM1_NOREMAP (0 << AFIO_MAPR_TIM1_REMAP_SHIFT) /* 00: No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */
-# define AFIO_MAPR_TIM1_PARTREMAP (1 << AFIO_MAPR_TIM1_REMAP_SHIFT) /* 01: Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */
-# define AFIO_MAPR_TIM1_FULLREMAP (3 << AFIO_MAPR_TIM1_REMAP_SHIFT) /* 11: Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */
-#define AFIO_MAPR_USART3_REMAP_SHIFT (6) /* Bits 5-4: USART3 remapping */
-#define AFIO_MAPR_USART3_REMAP_MASK (3 << AFIO_MAPR_USART3_REMAP_SHIFT)
-# define AFIO_MAPR_USART3_NOREMAP (0 << AFIO_MAPR_USART3_REMAP_SHIFT) /* 00: No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */
-# define AFIO_MAPR_USART3_PARTREMAP (1 << AFIO_MAPR_USART3_REMAP_SHIFT) /* 01: Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */
-# define AFIO_MAPR_USART3_FULLREMAP (3 << AFIO_MAPR_USART3_REMAP_SHIFT) /* 11: Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */
-#define AFIO_MAPR_USART2_REMAP (1 << 3) /* Bit 3: USART2 remapping */
-#define AFIO_MAPR_USART1_REMAP (1 << 2) /* Bit 2: USART1 remapping */
-#define AFIO_MAPR_I2C1_REMAP (1 << 1) /* Bit 1: I2C1 remapping */
-#define AFIO_MAPR_SPI1_REMAP (1 << 0) /* Bit 0: SPI1 remapping */
-
-/* External interrupt configuration register 1 */
-
-#define AFIO_EXTICR_PORT_MASK (0x0f)
-#define AFIO_EXTICR_EXTI_SHIFT(g) (((g) & 3) << 2)
-#define AFIO_EXTICR_EXTI_MASK(g) (AFIO_EXTICR_PORT_MASK << (AFIO_EXTICR_EXTI_SHIFT(g)))
-
-#define AFIO_EXTICR1_EXTI0_SHIFT (0) /* Bits 3-0: EXTI 0 configuration */
-#define AFIO_EXTICR1_EXTI0_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR1_EXTI0_SHIFT)
-#define AFIO_EXTICR1_EXTI1_SHIFT (4) /* Bits 7-4: EXTI 1 configuration */
-#define AFIO_EXTICR1_EXTI1_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR1_EXTI1_SHIFT)
-#define AFIO_EXTICR1_EXTI2_SHIFT (8) /* Bits 11-8: EXTI 2 configuration */
-#define AFIO_EXTICR1_EXTI2_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR1_EXTI2_SHIFT)
-#define AFIO_EXTICR1_EXTI3_SHIFT (12) /* Bits 15-12: EXTI 3 configuration */
-#define AFIO_EXTICR1_EXTI3_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR1_EXTI3_SHIFT)
-
-#define AFIO_EXTICR_PORTA (0) /* 0000: PA[x] pin */
-#define AFIO_EXTICR_PORTB (1) /* 0001: PB[x] pin */
-#define AFIO_EXTICR_PORTC (2) /* 0010: PC[x] pin */
-#define AFIO_EXTICR_PORTD (3) /* 0011: PD[x] pin */
-#define AFIO_EXTICR_PORTE (4) /* 0100: PE[x] pin */
-#define AFIO_EXTICR_PORTF (5) /* 0101: PF[x] pin */
-#define AFIO_EXTICR_PORTG (6) /* 0110: PG[x] pin */
-
-/* External interrupt configuration register 2 */
-
-#define AFIO_EXTICR2_EXTI4_SHIFT (0) /* Bits 3-0: EXTI 4 configuration */
-#define AFIO_EXTICR2_EXTI4_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR2_EXTI4_SHIFT)
-#define AFIO_EXTICR2_EXTI5_SHIFT (4) /* Bits 7-4: EXTI 5 configuration */
-#define AFIO_EXTICR2_EXTI5_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR2_EXTI5_SHIFT)
-#define AFIO_EXTICR2_EXTI6_SHIFT (8) /* Bits 11-8: EXTI 6 configuration */
-#define AFIO_EXTICR2_EXTI6_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR2_EXTI6_SHIFT)
-#define AFIO_EXTICR2_EXTI7_SHIFT (12) /* Bits 15-12: EXTI 7 configuration */
-#define AFIO_EXTICR2_EXTI7_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR2_EXTI7_SHIFT)
-
-/* External interrupt configuration register 3 */
-
-#define AFIO_EXTICR3_EXTI8_SHIFT (0) /* Bits 3-0: EXTI 8 configuration */
-#define AFIO_EXTICR3_EXTI8_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR3_EXTI8_SHIFT)
-#define AFIO_EXTICR3_EXTI9_SHIFT (4) /* Bits 7-4: EXTI 9 configuration */
-#define AFIO_EXTICR3_EXTI9_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR3_EXTI9_SHIFT)
-#define AFIO_EXTICR3_EXTI10_SHIFT (8) /* Bits 11-8: EXTI 10 configuration */
-#define AFIO_EXTICR3_EXTI10_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR3_EXTI10_SHIFT)
-#define AFIO_EXTICR3_EXTI11_SHIFT (12) /* Bits 15-12: EXTI 11 configuration */
-#define AFIO_EXTICR3_EXTI11_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR3_EXTI11_SHIFT)
-
-/* External interrupt configuration register 4 */
-
-#define AFIO_EXTICR4_EXTI12_SHIFT (0) /* Bits 3-0: EXTI 12 configuration */
-#define AFIO_EXTICR4_EXTI12_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR4_EXTI12_SHIFT)
-#define AFIO_EXTICR4_EXTI13_SHIFT (4) /* Bits 7-4: EXTI 13 configuration */
-#define AFIO_EXTICR4_EXTI13_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR4_EXTI13_SHIFT)
-#define AFIO_EXTICR4_EXTI14_SHIFT (8) /* Bits 11-8: EXTI 14 configuration */
-#define AFIO_EXTICR4_EXTI14_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR4_EXTI14_SHIFT)
-#define AFIO_EXTICR4_EXTI15_SHIFT (12) /* Bits 15-12: EXTI 15 configuration */
-#define AFIO_EXTICR4_EXTI15_MASK (AFIO_EXTICR_PORT_MASK << AFIO_EXTICR4_EXTI15_SHIFT)
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
/************************************************************************************
- * Public Types
+ * Name: stm32_configgpio
+ *
+ * Description:
+ * Configure a GPIO pin based on bit-encoded description of the pin.
+ * Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...)
+ * function, it must be unconfigured with stm32_unconfiggpio() with
+ * the same cfgset first before it can be set to non-alternative function.
+ *
+ * Returns:
+ * OK on success
+ * ERROR on invalid port, or when pin is locked as ALT function.
+ *
+ * \todo Auto Power Enable
************************************************************************************/
+EXTERN int stm32_configgpio(uint32_t cfgset);
+
/************************************************************************************
- * Public Data
+ * Name: stm32_unconfiggpio
+ *
+ * Description:
+ * Unconfigure a GPIO pin based on bit-encoded description of the pin, set it
+ * into default HiZ state (and possibly mark it's unused) and unlock it whether
+ * it was previsouly selected as alternative function (GPIO_ALT|GPIO_CNF_AFPP|...).
+ *
+ * This is a safety function and prevents hardware from schocks, as unexpected
+ * write to the Timer Channel Output GPIO to fixed '1' or '0' while it should
+ * operate in PWM mode could produce excessive on-board currents and trigger
+ * over-current/alarm function.
+ *
+ * Returns:
+ * OK on success
+ * ERROR on invalid port
+ *
+ * \todo Auto Power Disable
************************************************************************************/
+EXTERN int stm32_unconfiggpio(uint32_t cfgset);
+
/************************************************************************************
- * Public Function Prototypes
+ * Name: stm32_gpiowrite
+ *
+ * Description:
+ * Write one or zero to the selected GPIO pin
+ *
************************************************************************************/
+EXTERN void stm32_gpiowrite(uint32_t pinset, bool value);
+
+/************************************************************************************
+ * Name: stm32_gpioread
+ *
+ * Description:
+ * Read one or zero from the selected GPIO pin
+ *
+ ************************************************************************************/
+
+EXTERN bool stm32_gpioread(uint32_t pinset);
+
+/************************************************************************************
+ * Function: stm32_dumpgpio
+ *
+ * Description:
+ * Dump all GPIO registers associated with the provided base address
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_DEBUG
+EXTERN int stm32_dumpgpio(uint32_t pinset, const char *msg);
+#else
+# define stm32_dumpgpio(p,m)
+#endif
+
+
+/************************************************************************************
+ * Function: stm32_gpio_remap
+ *
+ * Description:
+ * Based on configuration within the .config file, remap positions of alternative
+ * functions. Typically called from stm32_start().
+ ************************************************************************************/
+
+EXTERN void stm32_gpio_remap(void);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32_STM32_GPIO_H */
diff --git a/arch/arm/src/stm32/stm32_i2c.c b/arch/arm/src/stm32/stm32_i2c.c
new file mode 100644
index 0000000000000000000000000000000000000000..4b03f6427fa328123ac9ad80ac5a6655a398bc2c
--- /dev/null
+++ b/arch/arm/src/stm32/stm32_i2c.c
@@ -0,0 +1,451 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_i2c.h
+ *
+ * Copyright (C) 2011 Uros Platise. All rights reserved.
+ * Author: Uros Platise <uros.platise@isotel.eu>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/** \file
+ * \author Uros Platise
+ * \brief STM32 I2C Hardware Layer - Device Driver
+ *
+ * Supports:
+ * - Master operation, 100 kHz (standard) and 400 kHz (full speed)
+ * - Multiple instances (shared bus)
+ * - Interrupt based operation
+ *
+ * Structure naming:
+ * - Device: structure as defined by the nuttx/i2c.h
+ * - Instance: represents each individual access to the I2C driver, obtained by
+ * the i2c_init(); it extends the Device structure from the nuttx/i2c.h;
+ * Instance points to OPS, to common I2C Hardware private data and contains
+ * its own private data, as frequency, address, mode of operation (in the future)
+ * - Private: Private data of an I2C Hardware
+ *
+ * \todo
+ * - SMBus support (hardware layer timings are already supported) and add SMBA gpio pin
+ * - Slave support with multiple addresses (on multiple instances):
+ * - 2 x 7-bit address or
+ * - 1 x 10 bit adresses + 1 x 7 bit address (?)
+ * - plus the broadcast address (general call)
+ * - Multi-master support
+ * - DMA (to get rid of too many CPU wake-ups and interventions)
+ * - Be ready for IPMI
+ **/
+
+#include <nuttx/config.h>
+#include <nuttx/arch.h>
+#include <nuttx/irq.h>
+#include <nuttx/i2c.h>
+#include <arch/board/board.h>
+
+#include <sys/types.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <semaphore.h>
+#include <errno.h>
+#include <debug.h>
+
+#include "up_arch.h"
+
+#include "stm32_rcc.h"
+#include "stm32_i2c.h"
+
+
+/************************************************************************************
+ * Private Types
+ ************************************************************************************/
+
+
+/** I2C Device Private Data
+ */
+struct stm32_i2c_priv_s {
+ uint32_t base;
+ int refs;
+ sem_t sem;
+};
+
+
+/** I2C Device, Instance
+ */
+struct stm32_i2c_inst_s {
+ struct i2c_ops_s * ops;
+ struct stm32_i2c_priv_s * priv;
+
+ uint32_t frequency;
+ int address;
+};
+
+
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/** Get register value by offset */
+static inline uint16_t stm32_i2c_getreg(FAR struct i2c_dev_s *dev, uint8_t offset)
+{
+ return getreg16( ((struct stm32_i2c_inst_s *)dev)->priv->base + offset);
+}
+
+
+/** Put register value by offset */
+static inline void stm32_i2c_putreg(FAR struct i2c_dev_s *dev, uint8_t offset, uint16_t value)
+{
+ //printf("putreg(%8x)=%4x\n", ((struct stm32_i2c_priv_s *)dev)->base + offset, value );
+ putreg16(value, ((struct stm32_i2c_inst_s *)dev)->priv->base + offset);
+}
+
+
+/** Modify register value by offset */
+static inline void stm32_i2c_modifyreg(FAR struct i2c_dev_s *dev, uint8_t offset, uint16_t clearbits, uint16_t setbits)
+{
+ modifyreg16( ((struct stm32_i2c_inst_s *)dev)->priv->base + offset, clearbits, setbits);
+}
+
+
+void inline stm32_i2c_sem_wait(FAR struct i2c_dev_s *dev)
+{
+ while( sem_wait( &((struct stm32_i2c_inst_s *)dev)->priv->sem ) != 0 ) {
+ ASSERT(errno == EINTR);
+ }
+}
+
+
+void inline stm32_i2c_sem_post(FAR struct i2c_dev_s *dev)
+{
+ sem_post( &((struct stm32_i2c_inst_s *)dev)->priv->sem );
+}
+
+
+void inline stm32_i2c_sem_init(FAR struct i2c_dev_s *dev)
+{
+ sem_init( &((struct stm32_i2c_inst_s *)dev)->priv->sem, 0, 1);
+}
+
+
+void inline stm32_i2c_sem_destroy(FAR struct i2c_dev_s *dev)
+{
+ sem_destroy( &((struct stm32_i2c_inst_s *)dev)->priv->sem );
+}
+
+
+static void stm32_i2c_setclock(FAR struct i2c_dev_s *inst, bool fast)
+{
+ /* Disable Peripheral if rising time is to be changed,
+ * and restore state on return. */
+
+ uint16_t cr1 = stm32_i2c_getreg(inst, STM32_I2C_CR1_OFFSET);
+
+ if (cr1 & I2C_CR1_PE)
+ stm32_i2c_putreg(inst, STM32_I2C_CR1_OFFSET, cr1 ^ I2C_CR1_PE);
+
+ /* Update timing and control registers */
+
+ if (!fast) {
+
+ /* Speed: 100 kHz
+ * Risetime: 1000 ns
+ * Duty: t_low / t_high = 1
+ */
+ stm32_i2c_putreg(inst, STM32_I2C_CCR_OFFSET, STM32_BOARD_HCLK / 200000);
+ stm32_i2c_putreg(inst, STM32_I2C_TRISE_OFFSET, 1 + STM32_BOARD_HCLK/1000000);
+ }
+ else {
+
+ /* Speed: 400 kHz
+ * Risetime: 1000 ns ??? \todo check rise time for 400 kHz devices
+ * Duty: t_low / t_high = 2
+ */
+ stm32_i2c_putreg(inst, STM32_I2C_CCR_OFFSET, STM32_BOARD_HCLK / 1200000);
+ stm32_i2c_putreg(inst, STM32_I2C_TRISE_OFFSET, 1 + STM32_BOARD_HCLK/1000000);
+ }
+
+ /* Restore state */
+
+ if (cr1 & I2C_CR1_PE)
+ stm32_i2c_putreg(inst, STM32_I2C_CR1_OFFSET, cr1);
+}
+
+
+/** Setup the I2C hardware, ready for operation with defaults */
+static int stm32_i2c_init(FAR struct i2c_dev_s *inst)
+{
+ /* Power-up and configure GPIOs */
+
+ switch( ((struct stm32_i2c_inst_s *)inst)->priv->base ) {
+ case STM32_I2C1_BASE:
+ modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_I2C1EN);
+ stm32_configgpio(GPIO_I2C1_SCL);
+ stm32_configgpio(GPIO_I2C1_SDA);
+ break;
+
+ case STM32_I2C2_BASE:
+ modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_I2C2EN);
+ stm32_configgpio(GPIO_I2C2_SCL);
+ stm32_configgpio(GPIO_I2C2_SDA);
+ break;
+
+ default: return ERROR;
+ }
+
+ /* Set peripheral frequency, where it must be at least 2 MHz
+ * for 100 kHz or 4 MHz for 400 kHz. Enable interrupt generation.
+ */
+
+#if STM32_BOARD_HCLK < 4000000
+# error STM32_I2C_INIT: Peripheral clock must be at least 4 MHz to support 100/400 kHz operation.
+#endif
+
+ stm32_i2c_putreg(inst, STM32_I2C_CR2_OFFSET,
+ I2C_CR2_ITERREN | I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN |
+ (STM32_BOARD_HCLK / 1000000)
+ );
+
+ stm32_i2c_setclock(inst, false);
+
+ /* Enable I2C */
+
+ stm32_i2c_putreg(inst, STM32_I2C_CR1_OFFSET, I2C_CR1_PE);
+
+ return OK;
+}
+
+
+/** Shutdown the I2C hardware */
+static int stm32_i2c_deinit(FAR struct i2c_dev_s *inst)
+{
+ /* Disable I2C */
+
+ stm32_i2c_putreg(inst, STM32_I2C_CR1_OFFSET, 0);
+
+ switch( ((struct stm32_i2c_inst_s *)inst)->priv->base ) {
+ case STM32_I2C1_BASE:
+ stm32_unconfiggpio(GPIO_I2C1_SCL);
+ stm32_unconfiggpio(GPIO_I2C1_SDA);
+ modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_I2C1EN, 0);
+ break;
+
+ case STM32_I2C2_BASE:
+ stm32_unconfiggpio(GPIO_I2C2_SCL);
+ stm32_unconfiggpio(GPIO_I2C2_SDA);
+ modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_I2C2EN, 0);
+ break;
+
+ default: return ERROR;
+ }
+
+ return OK;
+}
+
+
+/************************************************************************************
+ * Interrupt Service Routines
+ ************************************************************************************/
+
+static int stm32_i2c1_isr(int irq, void *context)
+{
+ // ACK before return!
+ return OK;
+}
+
+
+static int stm32_i2c2_isr(int irq, void *context)
+{
+ // ACK before return!
+ return OK;
+}
+
+
+/************************************************************************************
+ * Device Driver OPS - Blocking Type
+ ************************************************************************************/
+
+uint32_t stm32_i2c_setfrequency(FAR struct i2c_dev_s *inst, uint32_t frequency)
+{
+ stm32_i2c_sem_wait(inst);
+ ((struct stm32_i2c_inst_s *)inst)->frequency = frequency;
+
+
+ stm32_i2c_sem_post(inst);
+ return ((struct stm32_i2c_inst_s *)inst)->frequency;
+}
+
+
+int stm32_i2c_setaddress(FAR struct i2c_dev_s *inst, int addr, int nbits)
+{
+ stm32_i2c_sem_wait(inst);
+
+ ((struct stm32_i2c_inst_s *)inst)->address = addr;
+
+
+ stm32_i2c_sem_post(inst);
+ return OK;
+}
+
+
+int stm32_i2c_write(FAR struct i2c_dev_s *inst, const uint8_t *buffer, int buflen)
+{
+ stm32_i2c_sem_wait(inst);
+ stm32_i2c_sem_post(inst);
+
+ return OK;
+}
+
+
+int stm32_i2c_read(FAR struct i2c_dev_s *inst, uint8_t *buffer, int buflen)
+{
+ stm32_i2c_sem_wait(inst);
+ stm32_i2c_sem_post(inst);
+
+ return OK;
+}
+
+
+#ifdef CONFIG_I2C_TRANSFER
+int stm32_i2c_transfer(FAR struct i2c_dev_s *inst, FAR struct i2c_msg_s *msgs, int count)
+{
+ stm32_i2c_sem_wait(inst);
+ stm32_i2c_sem_post(inst);
+
+ return OK;
+}
+#endif
+
+
+/************************************************************************************
+ * Device Structures, Instantiation
+ ************************************************************************************/
+
+struct i2c_ops_s stm32_i2c_ops = {
+ .setfrequency = stm32_i2c_setfrequency,
+ .setaddress = stm32_i2c_setaddress,
+ .write = stm32_i2c_write,
+ .read = stm32_i2c_read
+#ifdef CONFIG_I2C_TRANSFER
+ , .transfer = stm32_i2c_transfer
+#endif
+};
+
+
+struct stm32_i2c_priv_s stm32_i2c1_priv = {
+ .base = STM32_I2C1_BASE,
+ .refs = 0
+};
+
+
+struct stm32_i2c_priv_s stm32_i2c2_priv = {
+ .base = STM32_I2C2_BASE,
+ .refs = 0
+};
+
+
+
+/************************************************************************************
+ * Public Function - Initialization
+ ************************************************************************************/
+
+FAR struct i2c_dev_s * up_i2cinitialize(int port)
+{
+ struct stm32_i2c_priv_s * priv = NULL; /* private data of device with multiple instances */
+ struct stm32_i2c_inst_s * inst = NULL; /* device, single instance */
+ int irqs;
+
+ /* Get structure and enable power */
+
+ switch(port) {
+ case 1: priv = (struct stm32_i2c_priv_s *)&stm32_i2c1_priv; break;
+ case 2: priv = (struct stm32_i2c_priv_s *)&stm32_i2c2_priv; break;
+ default: return NULL;
+ }
+
+ /* Allocate instance */
+
+ if ( !(inst = malloc( sizeof(struct stm32_i2c_inst_s) )) ) return NULL;
+
+ /* initialize instance */
+
+ inst->ops = &stm32_i2c_ops;
+ inst->priv = priv;
+ inst->frequency = 100e3;
+ inst->address = 0;
+
+ /* Init private data for the first time, increment refs count,
+ * power-up hardware and configure GPIOs.
+ */
+
+ irqs = irqsave();
+
+ if ((volatile int)priv->refs++ == 0) {
+ stm32_i2c_sem_init( (struct i2c_dev_s *)inst );
+ stm32_i2c_init( (struct i2c_dev_s *)inst );
+ }
+
+ irqrestore(irqs);
+
+ return (struct i2c_dev_s *)inst;
+}
+
+
+int up_i2cuninitialize(FAR struct i2c_dev_s * inst)
+{
+ int irqs;
+
+ ASSERT(inst);
+
+ /* Decrement refs and check for underflow */
+
+ if ( ((struct stm32_i2c_inst_s *)inst)->priv->refs == 0 )
+ return ERROR;
+
+ irqs = irqsave();
+
+ if ( --((struct stm32_i2c_inst_s *)inst)->priv->refs ) {
+ irqrestore(irqs);
+ free(inst);
+ return OK;
+ }
+
+ irqrestore(irqs);
+
+ /* Disable power and other HW resource (GPIO's) */
+
+ stm32_i2c_deinit( (struct i2c_dev_s *)inst );
+
+ /* Release unused resources */
+
+ stm32_i2c_sem_destroy( (struct i2c_dev_s *)inst );
+
+ free(inst);
+ return OK;
+}
+
diff --git a/arch/arm/src/stm32/stm32_i2c.h b/arch/arm/src/stm32/stm32_i2c.h
index 5df00d675e33b0ec7da2d3b4e4970873b8f424f8..d8aad330832d6880f5187ba85af9ff6215a77c77 100755
--- a/arch/arm/src/stm32/stm32_i2c.h
+++ b/arch/arm/src/stm32/stm32_i2c.h
@@ -111,7 +111,7 @@
#define I2C_CR2_FREQ_MASK (0x3f << I2C_CR2_FREQ_SHIFT)
#define I2C_CR2_ITERREN (1 << 8) /* Bit 8: Error Interrupt Enable */
#define I2C_CR2_ITEVTEN (1 << 9) /* Bit 9: Event Interrupt Enable */
-#define I2C_CR2_ITBUFEN (1 << 10 /* Bit 10: Buffer Interrupt Enable */
+#define I2C_CR2_ITBUFEN (1 << 10) /* Bit 10: Buffer Interrupt Enable */
#define I2C_CR2_DMAEN (1 << 11) /* Bit 11: DMA Requests Enable */
#define I2C_CR2_LAST (1 << 12) /* Bit 12: DMA Last Transfer */
diff --git a/arch/arm/src/stm32/stm32_internal.h b/arch/arm/src/stm32/stm32_internal.h
index 1af627a710a925ae1dc2433ef435c7e36e995972..d5568c8415bb55503f5c0240fb9a2d0899b7f807 100755
--- a/arch/arm/src/stm32/stm32_internal.h
+++ b/arch/arm/src/stm32/stm32_internal.h
@@ -48,6 +48,7 @@
#include "up_internal.h"
#include "chip.h"
+#include "stm32_gpio.h"
/************************************************************************************
* Definitions
@@ -65,120 +66,6 @@
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
-/* Bit-encoded input to stm32_configgpio() *******************************************/
-
-/* 16-bit Encoding:
- * OFFS SX.. VPPP BBBB
- */
-
-/* Output mode:
- *
- * O... .... .... ....
- */
-
-#define GPIO_INPUT (1 << 15) /* Bit 15: 1=Input mode */
-#define GPIO_OUTPUT (0) /* 0=Output or alternate function */
-#define GPIO_ALT (0)
-
-/* If the pin is a GPIO digital output, then this identifies the initial output value.
- * If the pin is an input, this bit is overloaded to provide the qualifier to\
- * distinquish input pull-up and -down:
- *
- * .... .... V... ....
- */
-
-#define GPIO_OUTPUT_SET (1 << 7) /* Bit 7: If output, inital value of output */
-#define GPIO_OUTPUT_CLEAR (0)
-
-/* These bits set the primary function of the pin:
- * .FF. .... .... ....
- */
-
-#define GPIO_CNF_SHIFT 13 /* Bits 13-14: GPIO function */
-#define GPIO_CNF_MASK (3 << GPIO_CNF_SHIFT)
-
-# define GPIO_CNF_ANALOGIN (0 << GPIO_CNF_SHIFT) /* Analog input */
-# define GPIO_CNF_INFLOAT (1 << GPIO_CNF_SHIFT) /* Input floating */
-# define GPIO_CNF_INPULLUD (2 << GPIO_CNF_SHIFT) /* Input pull-up/down general bit, since up is composed of two parts */
-# define GPIO_CNF_INPULLDWN (2 << GPIO_CNF_SHIFT) /* Input pull-down */
-# define GPIO_CNF_INPULLUP ((2 << GPIO_CNF_SHIFT) | GPIO_OUTPUT_SET) /* Input pull-up */
-
-# define GPIO_CNF_OUTPP (0 << GPIO_CNF_SHIFT) /* Output push-pull */
-# define GPIO_CNF_OUTOD (1 << GPIO_CNF_SHIFT) /* Output open-drain */
-# define GPIO_CNF_AFPP (2 << GPIO_CNF_SHIFT) /* Alternate function push-pull */
-# define GPIO_CNF_AFOD (3 << GPIO_CNF_SHIFT) /* Alternate function open-drain */
-
-/* Maximum frequency selection:
- * ...S S... .... ....
- */
-
-#define GPIO_MODE_SHIFT 11 /* Bits 11-12: GPIO frequency selection */
-#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT)
-# define GPIO_MODE_INPUT (0 << GPIO_MODE_SHIFT) /* Input mode (reset state) */
-# define GPIO_MODE_10MHz (1 << GPIO_MODE_SHIFT) /* Output mode, max speed 10 MHz */
-# define GPIO_MODE_2MHz (2 << GPIO_MODE_SHIFT) /* Output mode, max speed 2 MHz */
-# define GPIO_MODE_50MHz (3 << GPIO_MODE_SHIFT) /* Output mode, max speed 50 MHz */
-
-/* External interrupt selection (GPIO inputs only):
- * .... .X.. .... ....
- */
-
-#define GPIO_EXTI (1 << 10) /* Bit 10: Configure as EXTI interrupt */
-
-/* This identifies the GPIO port:
- * .... .... .PPP ....
- */
-
-#define GPIO_PORT_SHIFT 4 /* Bit 4-6: Port number */
-#define GPIO_PORT_MASK (7 << GPIO_PORT_SHIFT)
-#define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */
-#define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */
-#define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */
-#define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */
-#define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */
-#define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */
-#define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */
-
-/* This identifies the bit in the port:
- * .... .... .... BBBB
- */
-
-#define GPIO_PIN_SHIFT 0 /* Bits 0-3: GPIO number: 0-15 */
-#define GPIO_PIN_MASK (15 << GPIO_PIN_SHIFT)
-#define GPIO_PIN0 (0 << GPIO_PIN_SHIFT)
-#define GPIO_PIN1 (1 << GPIO_PIN_SHIFT)
-#define GPIO_PIN2 (2 << GPIO_PIN_SHIFT)
-#define GPIO_PIN3 (3 << GPIO_PIN_SHIFT)
-#define GPIO_PIN4 (4 << GPIO_PIN_SHIFT)
-#define GPIO_PIN5 (5 << GPIO_PIN_SHIFT)
-#define GPIO_PIN6 (6 << GPIO_PIN_SHIFT)
-#define GPIO_PIN7 (7 << GPIO_PIN_SHIFT)
-#define GPIO_PIN8 (8 << GPIO_PIN_SHIFT)
-#define GPIO_PIN9 (9 << GPIO_PIN_SHIFT)
-#define GPIO_PIN10 (10 << GPIO_PIN_SHIFT)
-#define GPIO_PIN11 (11 << GPIO_PIN_SHIFT)
-#define GPIO_PIN12 (12 << GPIO_PIN_SHIFT)
-#define GPIO_PIN13 (13 << GPIO_PIN_SHIFT)
-#define GPIO_PIN14 (14 << GPIO_PIN_SHIFT)
-#define GPIO_PIN15 (15 << GPIO_PIN_SHIFT)
-
-/* Alternate function pin-mapping ***************************************************/
-
-/* Each GPIO pin may serve either for general purpose I/O or for a special alternate
- * function (such as USART, CAN, USB, SDIO, etc.). That particular pin-mapping will
- * depend on the package and STM32 family. If you are incorporating a new STM32
- * chip into NuttX, you will need to add the pin-mapping to a header file and to
- * include that header file. NOTE: You can get the chip-specific pin-mapping info
- * from the chip datasheet.
- */
-
-#if defined(CONFIG_ARCH_CHIP_STM32F103ZET6)
-# include "stm32f103ze_pinmap.h"
-#elif defined(CONFIG_ARCH_CHIP_STM32F103RET6)
-# include "stm32f103re_pinmap.h"
-#elif defined(CONFIG_ARCH_CHIP_STM32F107VC)
-# include "stm32f107vc_pinmap.h"
-#endif
/************************************************************************************
* Public Types
@@ -249,49 +136,6 @@ EXTERN void stm32_lowsetup(void);
EXTERN void stm32_clockconfig(void);
-/************************************************************************************
- * Name: stm32_configgpio
- *
- * Description:
- * Configure a GPIO pin based on bit-encoded description of the pin.
- *
- ************************************************************************************/
-
-EXTERN int stm32_configgpio(uint32_t cfgset);
-
-/************************************************************************************
- * Name: stm32_gpiowrite
- *
- * Description:
- * Write one or zero to the selected GPIO pin
- *
- ************************************************************************************/
-
-EXTERN void stm32_gpiowrite(uint32_t pinset, bool value);
-
-/************************************************************************************
- * Name: stm32_gpioread
- *
- * Description:
- * Read one or zero from the selected GPIO pin
- *
- ************************************************************************************/
-
-EXTERN bool stm32_gpioread(uint32_t pinset);
-
-/************************************************************************************
- * Function: stm32_dumpgpio
- *
- * Description:
- * Dump all GPIO registers associated with the provided base address
- *
- ************************************************************************************/
-
-#ifdef CONFIG_DEBUG
-EXTERN int stm32_dumpgpio(uint32_t pinset, const char *msg);
-#else
-# define stm32_dumpgpio(p,m)
-#endif
/****************************************************************************
* Name: stm32_dmachannel
diff --git a/arch/arm/src/stm32/stm32_start.c b/arch/arm/src/stm32/stm32_start.c
index 9deb19dd2c021ef370f0c8a302817d7ba52789a9..ca47f540a300e91e00817eaba992c6cc2f3a9675 100644
--- a/arch/arm/src/stm32/stm32_start.c
+++ b/arch/arm/src/stm32/stm32_start.c
@@ -34,10 +34,6 @@
*
****************************************************************************/
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
#include <nuttx/config.h>
#include <stdint.h>
@@ -54,47 +50,6 @@
#include "stm32_gpio.h"
-/****************************************************************************
- * Private Definitions
- ****************************************************************************/
-
-/****************************************************************************
- * Private Data
- ****************************************************************************/
-
-/****************************************************************************
- * Public Data
- ****************************************************************************/
-
-/****************************************************************************
- * Private Functions
- ****************************************************************************/
-
-void stm32_jtag_enable(void)
-{
-#ifdef CONFIG_STM32_JTAG_FULL_ENABLE
-
-#elif CONFIG_STM32_JTAG_NOJNTRST_ENABLE
- uint32_t val = getreg32(STM32_AFIO_MAPR);
- val &= 0x00FFFFFF; // clear undefined readings ...
- val |= AFIO_MAPR_SWJ; // enabled but without JNTRST
- putreg32(val, STM32_AFIO_MAPR);
-
-#elif CONFIG_STM32_JTAG_SW_ENABLE
- uint32_t val = getreg32(STM32_AFIO_MAPR);
- val &= 0x00FFFFFF; // clear undefined readings ...
- val |= AFIO_MAPR_SWDP; // set JTAG-DP disabled and SW-DP enabled
- putreg32(val, STM32_AFIO_MAPR);
-
-#else
- uint32_t val = getreg32(STM32_AFIO_MAPR);
- val &= 0x00FFFFFF; // clear undefined readings ...
- val |= AFIO_MAPR_DISAB; // set JTAG-DP and SW-DP Disabled
- putreg32(val, STM32_AFIO_MAPR);
-
-#endif
-}
-
/****************************************************************************
* Name: showprogress
*
@@ -130,7 +85,7 @@ void __start(void)
stm32_clockconfig();
stm32_lowsetup();
- stm32_jtag_enable();
+ stm32_gpio_remap();
showprogress('A');
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
diff --git a/arch/arm/src/stm32/stm32_tim.c b/arch/arm/src/stm32/stm32_tim.c
index e185b1a87958c91ea526dbc35f91594cfd4cfa48..d5c9d6f70fe4ab0c5f11618001c99360cb1ff6fb 100644
--- a/arch/arm/src/stm32/stm32_tim.c
+++ b/arch/arm/src/stm32/stm32_tim.c
@@ -139,6 +139,19 @@ static void stm32_tim_reset(FAR struct stm32_tim_dev_s *dev)
}
+static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode)
+{
+ /** \todo Added support for input capture and bipolar dual outputs for TIM8 */
+
+ if (mode & STM32_TIM_CH_MODE_MASK) {
+ stm32_configgpio(cfg);
+ }
+ else {
+ stm32_unconfiggpio(cfg);
+ }
+}
+
+
/************************************************************************************
* Basic Functions
************************************************************************************/
@@ -210,8 +223,6 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, int (*handler)(int
}
/* Otherwise set callback and enable interrupt */
-
- printf("Attaching ISR: %d, %p\n", vectorno, handler);
irq_attach(vectorno, handler);
up_enable_irq(vectorno);
@@ -366,6 +377,67 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
stm32_tim_putreg(dev, ccmr_offset, ccmr_val);
stm32_tim_putreg(dev, STM32_GTIM_CCER_OFFSET, ccer_val);
+ /* set GPIO */
+
+ switch( ((struct stm32_tim_priv_s *)dev)->base ) {
+
+ case STM32_TIM1_BASE:
+ switch(channel) {
+ case 0: stm32_tim_gpioconfig(GPIO_TIM1_CH1OUT, mode); break;
+ case 1: stm32_tim_gpioconfig(GPIO_TIM1_CH2OUT, mode); break;
+ case 2: stm32_tim_gpioconfig(GPIO_TIM1_CH3OUT, mode); break;
+ case 3: stm32_tim_gpioconfig(GPIO_TIM1_CH4OUT, mode); break;
+ }
+ break;
+
+ case STM32_TIM2_BASE:
+ switch(channel) {
+ case 0: stm32_tim_gpioconfig(GPIO_TIM2_CH1OUT, mode); break;
+ case 1: stm32_tim_gpioconfig(GPIO_TIM2_CH2OUT, mode); break;
+ case 2: stm32_tim_gpioconfig(GPIO_TIM2_CH3OUT, mode); break;
+ case 3: stm32_tim_gpioconfig(GPIO_TIM2_CH4OUT, mode); break;
+ }
+ break;
+
+ case STM32_TIM3_BASE:
+ switch(channel) {
+ case 0: stm32_tim_gpioconfig(GPIO_TIM3_CH1OUT, mode); break;
+ case 1: stm32_tim_gpioconfig(GPIO_TIM3_CH2OUT, mode); break;
+ case 2: stm32_tim_gpioconfig(GPIO_TIM3_CH3OUT, mode); break;
+ case 3: stm32_tim_gpioconfig(GPIO_TIM3_CH4OUT, mode); break;
+ }
+ break;
+
+ case STM32_TIM4_BASE:
+ switch(channel) {
+ case 0: stm32_tim_gpioconfig(GPIO_TIM4_CH1OUT, mode); break;
+ case 1: stm32_tim_gpioconfig(GPIO_TIM4_CH2OUT, mode); break;
+ case 2: stm32_tim_gpioconfig(GPIO_TIM4_CH3OUT, mode); break;
+ case 3: stm32_tim_gpioconfig(GPIO_TIM4_CH4OUT, mode); break;
+ }
+ break;
+
+ case STM32_TIM5_BASE:
+ switch(channel) {
+ case 0: stm32_tim_gpioconfig(GPIO_TIM5_CH1OUT, mode); break;
+ case 1: stm32_tim_gpioconfig(GPIO_TIM5_CH2OUT, mode); break;
+ case 2: stm32_tim_gpioconfig(GPIO_TIM5_CH3OUT, mode); break;
+ case 3: stm32_tim_gpioconfig(GPIO_TIM5_CH4OUT, mode); break;
+ }
+ break;
+
+ case STM32_TIM8_BASE:
+ switch(channel) {
+ case 0: stm32_tim_gpioconfig(GPIO_TIM8_CH1OUT, mode); break;
+ case 1: stm32_tim_gpioconfig(GPIO_TIM8_CH2OUT, mode); break;
+ case 2: stm32_tim_gpioconfig(GPIO_TIM8_CH3OUT, mode); break;
+ case 3: stm32_tim_gpioconfig(GPIO_TIM8_CH4OUT, mode); break;
+ }
+ break;
+
+ default: return ERROR;
+ }
+
return OK;
}
diff --git a/arch/arm/src/stm32/stm32_tim.h b/arch/arm/src/stm32/stm32_tim.h
index 60cbec69196981f2cfa8f8f022db264c1b022044..42f7ac2954adf43ab169f8ec5259d0370d1209fd 100644
--- a/arch/arm/src/stm32/stm32_tim.h
+++ b/arch/arm/src/stm32/stm32_tim.h
@@ -880,7 +880,7 @@ typedef enum {
STM32_TIM_MODE_UNUSED = -1,
/* One of the following */
- STM32_TIM_MODE_MASK = 0x0300,
+ STM32_TIM_MODE_MASK = 0x0310,
STM32_TIM_MODE_DISABLED = 0x0000,
STM32_TIM_MODE_UP = 0x0100,
STM32_TIM_MODE_DOWN = 0x0110,
@@ -924,6 +924,7 @@ typedef enum {
// TODO other modes ... as PWM capture, ENCODER and Hall Sensor
// STM32_TIM_CH_INCAPTURE = 0x10,
// STM32_TIM_CH_INPWM = 0x20
+// STM32_TIM_CH_DRIVE_OC -- open collector mode
} stm32_tim_channel_t;
diff --git a/arch/arm/src/stm32/stm32f103re_pinmap.h b/arch/arm/src/stm32/stm32f103re_pinmap.h
index c78f0bd9e6ea124a5d1927cc38b5cd237f125b13..4a44cd3dce44d64779d98a660f23ef1ba2d58288 100644
--- a/arch/arm/src/stm32/stm32f103re_pinmap.h
+++ b/arch/arm/src/stm32/stm32f103re_pinmap.h
@@ -35,20 +35,19 @@
*
************************************************************************************/
+/** \file
+ */
+
#ifndef __ARCH_ARM_SRC_STM32_STM32F103RE_PINMAP_H
#define __ARCH_ARM_SRC_STM32_STM32F103RE_PINMAP_H
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
#include <nuttx/config.h>
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
-/* Alternate Pin Functions: */
+ /* TIMERS */
#if defined(CONFIG_STM32_TIM1_FULL_REMAP)
# define GPIO_TIM1_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTE|GPIO_PIN7)
@@ -185,9 +184,31 @@
# define GPIO_TIM4_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
#endif
+#define GPIO_TIM5_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_TIM5_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_TIM5_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_TIM5_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_TIM5_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_TIM5_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN2)
#define GPIO_TIM5_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN3)
#define GPIO_TIM5_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_TIM8_ETR (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_TIM8_CH1IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN6)
+#define GPIO_TIM8_CH1OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN6)
+#define GPIO_TIM8_CH2IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN7)
+#define GPIO_TIM8_CH2OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN7)
+#define GPIO_TIM8_CH3IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN8)
+#define GPIO_TIM8_CH3OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN8)
+#define GPIO_TIM8_CH4IN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTC|GPIO_PIN9)
+#define GPIO_TIM8_CH4OUT (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN9)
+#define GPIO_TIM8_BKIN (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN6)
+#define GPIO_TIM8_CH1N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN7)
+#define GPIO_TIM8_CH2N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_TIM8_CH3N (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN1)
+
+ /* USART */
+
#if defined(CONFIG_STM32_USART1_REMAP)
# define GPIO_USART1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTA|GPIO_PIN9)
# define GPIO_USART1_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN10)
@@ -230,6 +251,8 @@
# define GPIO_USART3_RTS (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN14)
#endif
+ /* SPI */
+
#if defined(CONFIG_STM32_SPI1_REMAP)
# define GPIO_SPI1_NSS (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN15)
# define GPIO_SPI1_SCK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN3)
@@ -254,6 +277,8 @@
# define GPIO_SPI3_MOSI (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
#endif
+ /* I2C */
+
#if defined(CONFIG_STM32_I2C1_REMAP)
# define GPIO_I2C1_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN8)
# define GPIO_I2C1_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN9)
@@ -261,6 +286,13 @@
# define GPIO_I2C1_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN6)
# define GPIO_I2C1_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN7)
#endif
+#define GPIO_I2C1_SMBA (GPIO_ALT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN5)
+
+#define GPIO_I2C2_SCL (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN10)
+#define GPIO_I2C2_SDA (GPIO_ALT|GPIO_CNF_AFOD|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_I2C2_SMBA (GPIO_ALT|GPIO_CNF_INFLOAT|GPIO_MODE_50MHz|GPIO_PORTB|GPIO_PIN12)
+
+ /* CAN */
#if defined(CONFIG_STM32_CAN1_FULL_REMAP)
# define GPIO_CAN1_TX (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN0)
@@ -281,7 +313,7 @@
# define GPIO_CAN2_RX (GPIO_INPUT|GPIO_CNF_INFLOAT|GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN13)
#endif
-/* SDIO */
+ /* SDIO */
#define GPIO_SDIO_D0 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN8)
@@ -298,6 +330,7 @@
#define GPIO_SDIO_CK (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTC|GPIO_PIN12)
#define GPIO_SDIO_CMD (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN2)
+
/************************************************************************************
* Public Types
************************************************************************************/
diff --git a/configs/vsn/include/board.h b/configs/vsn/include/board.h
index 733f1fc32434f9b4c0fd0c9f36900dc36ae93bd0..a1a30c4b198f6e47ca47ad2175be11e79e767b06 100644
--- a/configs/vsn/include/board.h
+++ b/configs/vsn/include/board.h
@@ -55,51 +55,6 @@
/************************************************************************************
* Definitions
************************************************************************************/
-
-/* Board Peripheral Assignment
- *
- * RS232/Power connector:
- * - USART1, is the default bootloader and console
- *
- * Sensor Connector:
- * Digital:
- * - GPIOs: PB10, PB11 (or even TIM2 CH3 and CH4)
- * - USART3
- * - I2C2
- * Analog:
- * - ADC1
- * Supporting Analog Circuitry (not seen outside)
- * - RefTap (TIM3_CH3)
- * - Power PWM Out (TIM8_CH1 / TIM3_CH1)
- * - Filtered Out (TIM3_CH4)
- * (TIM8 could run at lower frequency, while TIM3 must run at highest possible)
- * - Gain selection muxed with SDcard I/Os.
- *
- * Radio connector:
- * - UART3 / UART4
- * - SPI2
- * - I2C1 (remapped pins vs. Expansion connector)
- * - CAN
- * - TIM4 CH[3:4]
- *
- * Expansion connector:
- * - WakeUp Pin
- * - System Wide Reset
- * - SPI1 is wired to expansion port
- * - I2C1
- * - USART2 [Rx, Tx, CTS, RTS]
- * - DAC [0:1]
- * - ADC2 on pins [0:7]
- * - TIM2 Channels [1:4]
- * - TIM5 Channels [1:4]
- *
- * Onboard Components:
- * - SPI3 has direct connection with FRAM
- * - SDCard, conencts the microSD and shares the control lines with Sensor Interface
- * to select Amplifier Gain
- * - ADC3 is used also for power management (can be shared with ADC1 on sensor connector
- * if not used)
- */
/* Clocking *************************************************************************/
diff --git a/configs/vsn/nsh/defconfig b/configs/vsn/nsh/defconfig
index b4055a00e30a92c22c3b8906f2ad175a277a9a95..875da63f8dc20a74371777d47a93d821d58a7eed 100755
--- a/configs/vsn/nsh/defconfig
+++ b/configs/vsn/nsh/defconfig
@@ -101,6 +101,40 @@ CONFIG_STM32_RAISONANCE=n
CONFIG_STM32_BUILDROOT=y
CONFIG_STM32_DFU=n
+#
+# STM32 JTAG Options
+#
+# CONFIG_STM32_JTAG_FULL_ENABLE -- Full JTAG Enable (Parallel and Serial)
+# CONFIG_STM32_JTAG_NOJNTRST_ENABLE -- Full but without the JNTRST pin
+# CONFIG_STM32_JTAG_SW_ENABLE - Serial (SWJ) dual pin only which, can
+# coexist besides the FRAM on SPI3
+#
+CONFIG_STM32_JTAG_FULL_ENABLE=n
+CONFIG_STM32_JTAG_NOJNTRST_ENABLE=n
+CONFIG_STM32_JTAG_SW_ENABLE=n
+
+#
+# STM32 Individual Peripheral Pin Mapping
+#
+CONFIG_STM32_TIM1_FULL_REMAP=n
+CONFIG_STM32_TIM1_PARTIAL_REMAP=n
+CONFIG_STM32_TIM2_FULL_REMAP=n
+CONFIG_STM32_TIM2_PARTIAL_REMAP_1=n
+CONFIG_STM32_TIM2_PARTIAL_REMAP_2=n
+CONFIG_STM32_TIM3_FULL_REMAP=n
+CONFIG_STM32_TIM3_PARTIAL_REMAP=n
+CONFIG_STM32_TIM4_REMAP=n
+CONFIG_STM32_USART1_REMAP=n
+CONFIG_STM32_USART2_REMAP=n
+CONFIG_STM32_USART3_FULL_REMAP=n
+CONFIG_STM32_USART3_PARTIAL_REMAP=n
+CONFIG_STM32_SPI1_REMAP=n
+CONFIG_STM32_SPI3_REMAP=n
+CONFIG_STM32_I2C1_REMAP=y
+CONFIG_STM32_CAN1_REMAP1=n
+CONFIG_STM32_CAN1_REMAP2=n
+
+
#
# Individual subsystems can be enabled:
# AHB:
@@ -139,17 +173,6 @@ CONFIG_STM32_TIM8=n
CONFIG_STM32_USART1=y
CONFIG_STM32_ADC3=n
-#
-# STM32 JTAG Options
-#
-# CONFIG_STM32_JTAG_FULL_ENABLE -- Full JTAG Enable (Parallel and Serial)
-# CONFIG_STM32_JTAG_NOJNTRST_ENABLE -- Full but without the JNTRST pin
-# CONFIG_STM32_JTAG_SW_ENABLE - Serial (SWJ) dual pin only which, can
-# coexist besides the FRAM on SPI3
-#
-CONFIG_STM32_JTAG_FULL_ENABLE=n
-CONFIG_STM32_JTAG_NOJNTRST_ENABLE=n
-CONFIG_STM32_JTAG_SW_ENABLE=n
#
# STM32F103Z specific serial device driver settings
diff --git a/configs/vsn/src/nsh.c b/configs/vsn/src/nsh.c
deleted file mode 100644
index c4e691ba9cac856dca4f5c5ed6299f70c0a50fef..0000000000000000000000000000000000000000
--- a/configs/vsn/src/nsh.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/****************************************************************************
- * config/vsn/src/nsh.c
- * arch/arm/src/board/nsh.c
- *
- * Copyright (C) 2011 Uros Platise. All rights reserved.
- * Copyright (C) 2009 Gregory Nutt. All rights reserved.
- *
- * Authors: Uros Platise <uros.platise@isotel.eu>
- * Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-#include <stdbool.h>
-#include <stdio.h>
-#include <debug.h>
-#include <errno.h>
-
-#include "vsn.h"
-
-/****************************************************************************
- * Pre-Processor Definitions
- ****************************************************************************/
-
-/* Configuration ************************************************************/
-
-/* PORT and SLOT number probably depend on the board configuration */
-
-#define CONFIG_NSH_HAVEUSBDEV 1
-
-/* Can't support USB features if USB is not enabled */
-
-#ifndef CONFIG_USBDEV
-# undef CONFIG_NSH_HAVEUSBDEV
-#endif
-
-
-
-/****************************************************************************
- * Public Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Name: nsh_archinitialize
- *
- * Description:
- * Perform architecture specific initialization
- *
- ****************************************************************************/
-
-int nsh_archinitialize(void)
-{
-// up_ramtron();
-// up_sdcard();
-
- return OK;
-}
diff --git a/configs/vsn/src/sif.c b/configs/vsn/src/sif.c
index cdd7967f91e5863878a609ac515a7e6430544f54..9d5f8af6a3a9ad0db33561519526071b90923746 100644
--- a/configs/vsn/src/sif.c
+++ b/configs/vsn/src/sif.c
@@ -70,6 +70,7 @@
#include <nuttx/config.h>
#include <nuttx/fs.h>
+#include <nuttx/i2c.h>
#include <semaphore.h>
#include <stdio.h>
@@ -171,6 +172,9 @@ struct vsn_sif_s {
struct stm32_tim_dev_s * tim3; // Timer3 is used for PWM, and Analog RefTap
struct stm32_tim_dev_s * tim8; // Timer8 is used for Power Switch
+ struct i2c_dev_s * i2c1;
+ struct i2c_dev_s * i2c2;
+
sem_t exclusive_access;
};
@@ -226,7 +230,8 @@ void sif_gpio1_update(void)
case VSN_SIF_GPIO_OUTHIGH: val = GPIO_GP1_HIGH;break;
default: return;
}
- stm32_configgpio(val);
+ if (stm32_configgpio(val) == ERROR)
+ printf("Error updating1\n");
if ( stm32_gpioread(val) )
vsn_sif.gpio[0] |= VSN_SIF_GPIO_READ_MASK;
@@ -246,7 +251,8 @@ void sif_gpio2_update(void)
case VSN_SIF_GPIO_OUTHIGH: val = GPIO_GP2_HIGH;break;
default: return;
}
- stm32_configgpio(val);
+ if (stm32_configgpio(val) == ERROR)
+ printf("Error updating2\n");
if ( stm32_gpioread(val) )
vsn_sif.gpio[1] |= VSN_SIF_GPIO_READ_MASK;
@@ -289,30 +295,31 @@ int sif_anout_init(void)
vsn_sif.tim3 = stm32_tim_init(3);
vsn_sif.tim8 = stm32_tim_init(8);
+ vsn_sif.i2c1 = up_i2cinitialize(1);
+ vsn_sif.i2c2 = up_i2cinitialize(2);
+
if (!vsn_sif.tim3 || !vsn_sif.tim8) return ERROR;
// Use the TIM3 as PWM modulated analogue output
- STM32_TIM_SETCHANNEL(vsn_sif.tim3, GPIO_OUT_PWM_TIM3_CH4, STM32_TIM_CH_OUTPWM | STM32_TIM_CH_POLARITY_NEG);
STM32_TIM_SETPERIOD(vsn_sif.tim3, 4096);
- STM32_TIM_SETCOMPARE(vsn_sif.tim3, GPIO_OUT_PWM_TIM3_CH4, 1024);
+ STM32_TIM_SETCOMPARE(vsn_sif.tim3, GPIO_OUT_PWM_TIM3_CH, 1024);
STM32_TIM_SETCLOCK(vsn_sif.tim3, 36e6);
STM32_TIM_SETMODE(vsn_sif.tim3, STM32_TIM_MODE_UP);
- stm32_configgpio(GPIO_OUT_HIZ);
+ //STM32_TIM_SETCHANNEL(vsn_sif.tim3, GPIO_OUT_PWM_TIM3_CH, STM32_TIM_CH_OUTPWM | STM32_TIM_CH_POLARITY_NEG);
// Use the TIM8 to drive the upper power mosfet
STM32_TIM_SETISR(vsn_sif.tim8, sif_anout_isr, 0);
STM32_TIM_ENABLEINT(vsn_sif.tim8, 0);
-
- STM32_TIM_SETCHANNEL(vsn_sif.tim8, GPIO_OUT_PWRPWM_TIM8_CH1P, STM32_TIM_CH_OUTPWM | STM32_TIM_CH_POLARITY_NEG);
+
STM32_TIM_SETPERIOD(vsn_sif.tim8, 4096);
- STM32_TIM_SETCOMPARE(vsn_sif.tim8, GPIO_OUT_PWRPWM_TIM8_CH1P, 0);
+ STM32_TIM_SETCOMPARE(vsn_sif.tim8, GPIO_OUT_PWRPWM_TIM8_CH, 0);
STM32_TIM_SETCLOCK(vsn_sif.tim8, 36e6);
STM32_TIM_SETMODE(vsn_sif.tim8, STM32_TIM_MODE_UP);
- stm32_configgpio(GPIO_OUT_PWRPWM);
+ STM32_TIM_SETCHANNEL(vsn_sif.tim8, GPIO_OUT_PWRPWM_TIM8_CH, STM32_TIM_CH_OUTPWM | STM32_TIM_CH_POLARITY_NEG);
return OK;
}
@@ -476,7 +483,7 @@ int sif_init(void)
int sif_main(int argc, char *argv[])
{
if (argc >= 2) {
- if (!strcmp(argv[1], "init")) {
+ if (!strcmp(argv[1], "init")) {
return sif_init();
}
else if (!strcmp(argv[1], "gpio") && argc == 4) {
@@ -489,7 +496,7 @@ int sif_main(int argc, char *argv[])
}
else if (!strcmp(argv[1], "pwr") && argc == 3) {
int val = atoi(argv[2]);
- STM32_TIM_SETCOMPARE(vsn_sif.tim8, GPIO_OUT_PWRPWM_TIM8_CH1P, val);
+ STM32_TIM_SETCOMPARE(vsn_sif.tim8, GPIO_OUT_PWRPWM_TIM8_CH, val);
return 0;
}
else if (!strcmp(argv[1], "c")) {
diff --git a/configs/vsn/src/vsn.h b/configs/vsn/src/vsn.h
index 5d017b07a68bb8135deb5ca09c20e3cd4113db3b..c9058663ee60cc3823378db126bdd719de2df31d 100644
--- a/configs/vsn/src/vsn.h
+++ b/configs/vsn/src/vsn.h
@@ -51,6 +51,51 @@
/************************************************************************************
* PIN Definitions
************************************************************************************/
+
+ /* Board Peripheral Assignment
+ *
+ * RS232/Power connector:
+ * - USART1, is the default bootloader and console
+ *
+ * Sensor Connector:
+ * Digital:
+ * - GPIOs: PB10, PB11 (or even TIM2 CH3 and CH4)
+ * - USART3
+ * - I2C2
+ * Analog:
+ * - ADC1
+ * Supporting Analog Circuitry (not seen outside)
+ * - RefTap (TIM3_CH3)
+ * - Power PWM Out (TIM8_CH1 / TIM3_CH1)
+ * - Filtered Out (TIM3_CH4)
+ * (TIM8 could run at lower frequency, while TIM3 must run at highest possible)
+ * - Gain selection muxed with SDcard I/Os.
+ *
+ * Radio connector:
+ * - UART3 / UART4
+ * - SPI2
+ * - I2C1 (remapped pins vs. Expansion connector)
+ * - CAN
+ * - TIM4 CH[3:4]
+ *
+ * Expansion connector:
+ * - WakeUp Pin
+ * - System Wide Reset
+ * - SPI1 is wired to expansion port
+ * - I2C1
+ * - USART2 [Rx, Tx, CTS, RTS]
+ * - DAC [0:1]
+ * - ADC2 on pins [0:7]
+ * - TIM2 Channels [1:4]
+ * - TIM5 Channels [1:4]
+ *
+ * Onboard Components:
+ * - SPI3 has direct connection with FRAM
+ * - SDCard, conencts the microSD and shares the control lines with Sensor Interface
+ * to select Amplifier Gain
+ * - ADC3 is used also for power management (can be shared with ADC1 on sensor connector
+ * if not used)
+ */
/* LED */
@@ -94,7 +139,7 @@
#define GPIO_OUT_PWRON (GPIO_OUTPUT|GPIO_CNF_OUTPP |GPIO_MODE_2MHz |GPIO_PORTC|GPIO_PIN6 |GPIO_OUTPUT_CLEAR)
#define GPIO_OUT_PWROFF (GPIO_OUTPUT|GPIO_CNF_OUTPP |GPIO_MODE_2MHz |GPIO_PORTC|GPIO_PIN6 |GPIO_OUTPUT_SET)
#define GPIO_OUT_PWRPWM (GPIO_ALT |GPIO_CNF_AFPP |GPIO_MODE_10MHz|GPIO_PORTC|GPIO_PIN6 )
-#define GPIO_OUT_PWRPWM_TIM8_CH1P 1 /* TIM8.CH1 */
+#define GPIO_OUT_PWRPWM_TIM8_CH 1 /* TIM8.CH1 */
#define GPIO_OUT_HIZ (GPIO_INPUT |GPIO_CNF_INFLOAT |GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1 )
#define GPIO_OUT_PUP (GPIO_INPUT |GPIO_CNF_INPULLUP |GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1 )
@@ -103,7 +148,7 @@
#define GPIO_OUT_HIGH (GPIO_OUTPUT|GPIO_CNF_OUTPP |GPIO_MODE_2MHz |GPIO_PORTB|GPIO_PIN1 |GPIO_OUTPUT_SET)
#define GPIO_OUT_AIN (GPIO_INPUT |GPIO_CNF_ANALOGIN |GPIO_MODE_INPUT|GPIO_PORTB|GPIO_PIN1 )
#define GPIO_OUT_PWM (GPIO_ALT |GPIO_CNF_AFPP |GPIO_MODE_10MHz|GPIO_PORTB|GPIO_PIN1 )
-#define GPIO_OUT_PWM_TIM3_CH4 4 /* TIM3.CH4 */
+#define GPIO_OUT_PWM_TIM3_CH 4 /* TIM3.CH4 */
/* Radio Connector */
diff --git a/include/nuttx/i2c.h b/include/nuttx/i2c.h
index 471d256190401e78a9f32fa35c3f0842af112b20..b4aadb7098489241adc422b7d0bee52e2f09d416 100644
--- a/include/nuttx/i2c.h
+++ b/include/nuttx/i2c.h
@@ -251,6 +251,24 @@ extern "C" {
EXTERN FAR struct i2c_dev_s *up_i2cinitialize(int port);
+
+/****************************************************************************
+ * Name: up_i2cuninitialize
+ *
+ * Description:
+ * De-initialize the selected I2C port, and power down the device.
+ *
+ * Input Parameter:
+ * Device structure as returned by the up_i2cinitalize()
+ *
+ * Returned Value:
+ * OK on success, ERROR when internal reference count missmatch or dev
+ * points to invalid hardware device.
+ *
+ ****************************************************************************/
+
+EXTERN int up_i2cuninitialize(FAR struct i2c_dev_s * dev);
+
#undef EXTERN
#if defined(__cplusplus)
}
diff --git a/sched/sem_holder.c b/sched/sem_holder.c
index 28d74a8683e65abba5fb91be6a8f12152cfaa45c..2dfc50ee6112af2a3a4d0163ae7ff3e8bfe7b428 100644
--- a/sched/sem_holder.c
+++ b/sched/sem_holder.c
@@ -1,7 +1,7 @@
/****************************************************************************
* sched/sem_holder.c
*
- * Copyright (C) 2009-2010 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2009-2011 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@@ -249,11 +249,13 @@ static int sem_foreachholder(FAR sem_t *sem, holderhandler_t handler, FAR void *
* Name: sem_recoverholders
****************************************************************************/
+#if CONFIG_SEM_PREALLOCHOLDERS > 0
static int sem_recoverholders(FAR struct semholder_s *pholder, FAR sem_t *sem, FAR void *arg)
{
sem_freeholder(sem, pholder);
return 0;
}
+#endif
/****************************************************************************
* Name: sem_boostholderprio