diff --git a/arch/arm/src/armv7-m/nvic.h b/arch/arm/src/armv7-m/nvic.h
index 43cd470fb4102497a765a57d2c09b8e42521d2c4..ed66e06e921376f565ec185d6adf051076786c6d 100644
--- a/arch/arm/src/armv7-m/nvic.h
+++ b/arch/arm/src/armv7-m/nvic.h
@@ -170,6 +170,8 @@
#define NVIC_IRQ232_235_PRIORITY_OFFSET 0x04e8 /* IRQ 232-235 priority register */
#define NVIC_IRQ236_239_PRIORITY_OFFSET 0x04ec /* IRQ 236-239 priority register */
+/* System Control Block (SCB) */
+
#define NVIC_CPUID_BASE_OFFSET 0x0d00 /* CPUID base register */
#define NVIC_INTCTRL_OFFSET 0x0d04 /* Interrupt control state register */
#define NVIC_VECTAB_OFFSET 0x0d08 /* Vector table offset register */
@@ -200,6 +202,7 @@
#define NVIC_ISAR2_OFFSET 0x0d68 /* ISA feature register 2 */
#define NVIC_ISAR3_OFFSET 0x0d6c /* ISA feature register 3 */
#define NVIC_ISAR4_OFFSET 0x0d70 /* ISA feature register 4 */
+#define NVIC_CPACR_OFFSET 0x0d88 /* Coprocessor Access Control Register */
#define NVIC_STIR_OFFSET 0x0f00 /* Software trigger interrupt register */
#define NVIC_PID4_OFFSET 0x0fd0 /* Peripheral identification register (PID4) */
#define NVIC_PID5_OFFSET 0x0fd4 /* Peripheral identification register (PID5) */
@@ -363,6 +366,7 @@
#define NVIC_ISAR2 (ARMV7M_NVIC_BASE + NVIC_ISAR2_OFFSET)
#define NVIC_ISAR3 (ARMV7M_NVIC_BASE + NVIC_ISAR3_OFFSET)
#define NVIC_ISAR4 (ARMV7M_NVIC_BASE + NVIC_ISAR4_OFFSET)
+#define NVIC_CPACR (ARMV7M_NVIC_BASE + NVIC_CPACR_OFFSET)
#define NVIC_STIR (ARMV7M_NVIC_BASE + NVIC_STIR_OFFSET)
#define NVIC_PID4 (ARMV7M_NVIC_BASE + NVIC_PID4_OFFSET)
#define NVIC_PID5 (ARMV7M_NVIC_BASE + NVIC_PID5_OFFSET)
diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs
index d59363c3ed89eceec802238abd98e07c3a131db2..b09ffd5190d9f1a3b96e2ed80d05706560423f58 100644
--- a/arch/arm/src/stm32/Make.defs
+++ b/arch/arm/src/stm32/Make.defs
@@ -36,7 +36,7 @@
HEAD_ASRC = stm32_vectors.S
CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_switchcontext.S
-CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
+CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c \
up_createstack.c up_mdelay.c up_udelay.c up_exit.c \
up_initialize.c up_initialstate.c up_interruptcontext.c \
up_memfault.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c \
@@ -49,10 +49,11 @@ CMN_CSRCS += up_checkstack.c
endif
CHIP_ASRCS =
-CHIP_CSRCS = stm32_start.c stm32_rcc.c stm32_gpio.c stm32_exti.c stm32_flash.c \
- stm32_irq.c stm32_timerisr.c stm32_dma.c stm32_lowputc.c \
- stm32_serial.c stm32_spi.c stm32_usbdev.c stm32_sdio.c \
- stm32_tim.c stm32_i2c.c stm32_pwr.c stm32_idle.c stm32_waste.c
+CHIP_CSRCS = stm32_allocateheap.c stm32_start.c stm32_rcc.c stm32_lse.c \
+ stm32_gpio.c stm32_exti.c stm32_flash.c stm32_irq.c \
+ stm32_timerisr.c stm32_dma.c stm32_lowputc.c stm32_serial.c \
+ stm32_spi.c stm32_usbdev.c stm32_sdio.c stm32_tim.c stm32_i2c.c \
+ stm32_pwr.c stm32_idle.c stm32_waste.c
ifeq ($(CONFIG_STM32_RCCLOCK),y)
CHIP_CSRCS += stm32_rcclock.c
diff --git a/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h b/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
index 9242ad02738db3d45dbadbffb1d5d556d6790416..9ae4220c176e34a8e5567e30cc59d190eaaf3b9e 100644
--- a/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
+++ b/arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
@@ -512,10 +512,10 @@
#define GPIO_USART1_CK (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN8)
#define GPIO_USART1_CTS (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN11)
#define GPIO_USART1_RTS (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN12)
-#define GPIO_USART1_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN10)
-#define GPIO_USART1_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN7)
-#define GPIO_USART1_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN9)
-#define GPIO_USART1_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN6)
+#define GPIO_USART1_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN10)
+#define GPIO_USART1_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN7)
+#define GPIO_USART1_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN9)
+#define GPIO_USART1_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN6)
#define GPIO_USART2_CK_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN4)
#define GPIO_USART2_CK_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN7)
@@ -523,10 +523,10 @@
#define GPIO_USART2_CTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN3)
#define GPIO_USART2_RTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN1)
#define GPIO_USART2_RTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN4)
-#define GPIO_USART2_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN3)
-#define GPIO_USART2_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN6)
-#define GPIO_USART2_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTA|GPIO_PIN2)
-#define GPIO_USART2_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN5)
+#define GPIO_USART2_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN3)
+#define GPIO_USART2_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN6)
+#define GPIO_USART2_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN2)
+#define GPIO_USART2_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN5)
#define GPIO_USART3_CK_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN12)
#define GPIO_USART3_CK_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN12)
@@ -535,20 +535,20 @@
#define GPIO_USART3_CTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN11)
#define GPIO_USART3_RTS_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN14)
#define GPIO_USART3_RTS_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN12)
-#define GPIO_USART3_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN11)
-#define GPIO_USART3_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN11)
-#define GPIO_USART3_RX_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN9)
-#define GPIO_USART3_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PORTB|GPIO_PIN10)
-#define GPIO_USART3_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PORTC|GPIO_PIN10)
-#define GPIO_USART3_TX_3 (GPIO_ALT|GPIO_AF7|GPIO_PORTD|GPIO_PIN8)
+#define GPIO_USART3_RX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN11)
+#define GPIO_USART3_RX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11)
+#define GPIO_USART3_RX_3 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN9)
+#define GPIO_USART3_TX_1 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN10)
+#define GPIO_USART3_TX_2 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10)
+#define GPIO_USART3_TX_3 (GPIO_ALT|GPIO_AF7|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN8)
-#define GPIO_UART4_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN1)
-#define GPIO_UART4_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN11)
-#define GPIO_UART4_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTA|GPIO_PIN0)
-#define GPIO_UART4_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN10)
+#define GPIO_UART4_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN1)
+#define GPIO_UART4_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN11)
+#define GPIO_UART4_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_UART4_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN10)
-#define GPIO_UART5_RX (GPIO_ALT|GPIO_AF8|GPIO_PORTD|GPIO_PIN2)
-#define GPIO_UART5_TX (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN12)
+#define GPIO_UART5_RX (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN2)
+#define GPIO_UART5_TX (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN12)
#define GPIO_USART6_CK_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN8)
#define GPIO_USART6_CK_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN7)
@@ -556,10 +556,10 @@
#define GPIO_USART6_CTS_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN15)
#define GPIO_USART6_RTS_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN12)
#define GPIO_USART6_RTS_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN8)
-#define GPIO_USART6_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN7)
-#define GPIO_USART6_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN9)
-#define GPIO_USART6_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PORTC|GPIO_PIN6)
-#define GPIO_USART6_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PORTG|GPIO_PIN14)
+#define GPIO_USART6_RX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN7)
+#define GPIO_USART6_RX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN9)
+#define GPIO_USART6_TX_1 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN6)
+#define GPIO_USART6_TX_2 (GPIO_ALT|GPIO_AF8|GPIO_PULLUP|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN14)
#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F40XXX_PINMAP_H */
diff --git a/arch/arm/src/stm32/stm32_allocateheap.c b/arch/arm/src/stm32/stm32_allocateheap.c
new file mode 100644
index 0000000000000000000000000000000000000000..576db404780cf6a1ebcce6bc478a4d0504943b55
--- /dev/null
+++ b/arch/arm/src/stm32/stm32_allocateheap.c
@@ -0,0 +1,161 @@
+/****************************************************************************
+ * arch/arm/src/stm32/up_allocateheap.c
+ *
+ * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/types.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "up_arch.h"
+#include "up_internal.h"
+
+/****************************************************************************
+ * Private Definitions
+ ****************************************************************************/
+
+/* For the STM312F10xxx family, all SRAM is in a contiguous block starting
+ * at g_heapbase and extending through CONFIG_DRAM_END (my apologies for
+ * the bad naming).
+ */
+
+#if defined(CONFIG_STM32_STM32F10XX)
+# define SRAM1_END CONFIG_DRAM_END
+
+/* All members of the STM32F40xxx family have 192Kb in three banks:
+ *
+ * 1) 112Kb of SRAM beginning at address 0x2000:0000
+ * 2) 16Kb of SRAM beginning at address 0x2001:c000
+ * 3) 64Kb of TCM SRAM beginning at address 0x1000:0000
+ *
+ * As determined by ld.script, g_heapbase lies in the 112Kb memory
+ * region and that extends to 0x2001:0000. But the first and second memory
+ * regions are contiguous and treated as one in this logic that extends to
+ * 0x2002:0000.
+ */
+
+#elif defined(CONFIG_STM32_STM32F40XX)
+# define SRAM1_END 0x20020000
+# define SRAM2_START 0x10000000
+# define SRAM2_END 0x10010000
+#else
+# error "Unsupported STM32 chip"
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_allocate_heap
+ *
+ * Description:
+ * The heap may be statically allocated by
+ * defining CONFIG_HEAP_BASE and CONFIG_HEAP_SIZE. If these
+ * are not defined, then this function will be called to
+ * dynamically set aside the heap region.
+ *
+ ****************************************************************************/
+
+void up_allocate_heap(FAR void **heap_start, size_t *heap_size)
+{
+ up_ledon(LED_HEAPALLOCATE);
+ *heap_start = (FAR void*)g_heapbase;
+ *heap_size = SRAM1_END - g_heapbase;
+}
+
+/****************************************************************************
+ * Name: up_addregion
+ *
+ * Description:
+ * Memory may be added in non-contiguous chunks. Additional chunks are
+ * added by calling this function.
+ *
+ ****************************************************************************/
+
+#if CONFIG_MM_REGIONS > 1
+# if defined(CONFIG_STM32_STM32F40XX)
+# if defined(CONFIG_HEAP2_BASE) && defined(CONFIG_HEAP2_END)
+# if CONFIG_MM_REGIONS > 3
+# error "CONFIG_MM_REGIONS > 3 but I don't know what all of the regions are"
+# endif
+# elif CONFIG_MM_REGIONS > 2
+# error "CONFIG_MM_REGIONS > 2 but I don't know what all of the regions are"
+# endif
+
+void up_addregion(void)
+{
+ /* Add the STM32F40xxx TCM SRAM heap region. */
+
+ mm_addregion((FAR void*)SRAM2_START, SRAM2_END-SRAM2_START);
+
+ /* Add the user specified heap region. */
+
+# if CONFIG_MM_REGIONS > 2 && defined(CONFIG_HEAP2_BASE) && defined(CONFIG_HEAP2_END)
+ mm_addregion((FAR void*)CONFIG_HEAP2_BASE, CONFIG_HEAP2_END - CONFIG_HEAP2_BASE);
+# endif
+}
+
+# elif defined(CONFIG_HEAP2_BASE) && defined(CONFIG_HEAP2_END)
+# if CONFIG_MM_REGIONS > 2
+# error "CONFIG_MM_REGIONS > 2 but I don't know what all of the regions are"
+# endif
+
+void up_addregion(void)
+{
+ /* Add the user specified heap region. */
+
+ mm_addregion((FAR void*)CONFIG_HEAP2_BASE, CONFIG_HEAP2_END - CONFIG_HEAP2_BASE);
+}
+
+# else
+# error "CONFIG_MM_REGIONS > 1 but I don't know what any of the region(s) are"
+# endif
+#endif
diff --git a/arch/arm/src/stm32/stm32_gpio.c b/arch/arm/src/stm32/stm32_gpio.c
index 7c59f4a094918fefe04f81cf5ebac5e66b42ff0e..a22d208838ce2ffc91f686d01c17e930d36a4583 100644
--- a/arch/arm/src/stm32/stm32_gpio.c
+++ b/arch/arm/src/stm32/stm32_gpio.c
@@ -500,7 +500,7 @@ int stm32_configgpio(uint32_t cfgset)
setting = GPIO_OSPEED_25MHz;
break;
- case GPIO_SPEED_20MHz: /* 50 MHz Fast speed output */
+ case GPIO_SPEED_50MHz: /* 50 MHz Fast speed output */
setting = GPIO_OSPEED_50MHz;
break;
diff --git a/arch/arm/src/stm32/stm32_gpio.h b/arch/arm/src/stm32/stm32_gpio.h
index ecd96863b1ec8816e2facd51e2a2f316f837c669..86d8100b69304e6d90a87e3d802ff753fe21c38a 100644
--- a/arch/arm/src/stm32/stm32_gpio.h
+++ b/arch/arm/src/stm32/stm32_gpio.h
@@ -296,7 +296,7 @@ extern "C" {
#define GPIO_SPEED_MASK (3 << GPIO_SPEED_SHIFT)
# define GPIO_SPEED_2MHz (0 << GPIO_SPEED_SHIFT) /* 2 MHz Low speed output */
# define GPIO_SPEED_25MHz (1 << GPIO_SPEED_SHIFT) /* 25 MHz Medium speed output */
-# define GPIO_SPEED_20MHz (2 << GPIO_SPEED_SHIFT) /* 50 MHz Fast speed output */
+# define GPIO_SPEED_50MHz (2 << GPIO_SPEED_SHIFT) /* 50 MHz Fast speed output */
# define GPIO_SPEED_100MHz (3 << GPIO_SPEED_SHIFT) /* 100 MHz High speed output */
/* Output/Alt function type selection:
diff --git a/arch/arm/src/stm32/stm32_lse.c b/arch/arm/src/stm32/stm32_lse.c
new file mode 100644
index 0000000000000000000000000000000000000000..bf9d6d6f253aa04eae94fd1fcbc42adf0d6a8dbe
--- /dev/null
+++ b/arch/arm/src/stm32/stm32_lse.c
@@ -0,0 +1,93 @@
+/****************************************************************************
+ * arch/arm/src/stm32/stm32_lse.c
+ *
+ * Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "up_arch.h"
+
+#include "stm32_rcc.h"
+#include "stm32_waste.h"
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_rcc_enablelse
+ *
+ * Todo:
+ * Check for LSE good timeout and return with -1,
+ * possible ISR optimization? or at least ISR should be cough in case of\
+ * failure
+ *
+ ****************************************************************************/
+
+void stm32_rcc_enablelse(void)
+{
+ /* Enable LSE */
+
+ modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_LSEON);
+
+ /* We could wait for ISR here ... */
+
+ while ((getreg16(STM32_RCC_BDCR) & RCC_BDCR_LSERDY) == 0)
+ {
+ up_waste();
+ }
+
+ /* Select LSE as RTC Clock Source */
+
+ modifyreg16(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE);
+
+ /* Enable Clock */
+
+ modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN);
+}
diff --git a/arch/arm/src/stm32/stm32_start.c b/arch/arm/src/stm32/stm32_start.c
index ce7aeb53aef8af4ef994d3fc671fe64d5acd59c3..7209d3cb927601000861c27199f58858bf677f68 100644
--- a/arch/arm/src/stm32/stm32_start.c
+++ b/arch/arm/src/stm32/stm32_start.c
@@ -49,6 +49,9 @@
#include "stm32_internal.h"
#include "stm32_gpio.h"
+#ifdef CONFIG_ARCH_FPU
+# include "nvic.h"
+#endif
/****************************************************************************
* Name: showprogress
@@ -64,6 +67,33 @@
# define showprogress(c)
#endif
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+ /****************************************************************************
+ * Name: stm32_fpuconfig
+ *
+ * Description:
+ * Configure the FPU. The the MCU has an FPU, then enable full access
+ * to coprocessors CP10 and CP11.
+ *
+ * This is implemented as a macro because the stack has not yet been
+ * initialized.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_ARCH_FPU
+# define stm32_fpuconfig() \
+{ \
+ uint32_t regval = getreg32(NVIC_CPACR); \
+ regval |= ((3 << (2*10)) | (3 << (2*11))); \
+ putreg32(regval, NVIC_CPACR); \
+}
+#else
+# define stm32_fpuconfig()
+#endif
+
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -84,6 +114,7 @@ void __start(void)
/* Configure the uart so that we can get debug output as soon as possible */
stm32_clockconfig();
+ stm32_fpuconfig();
stm32_lowsetup();
stm32_gpioinit();
showprogress('A');
diff --git a/arch/arm/src/stm32/stm32_waste.h b/arch/arm/src/stm32/stm32_waste.h
index 11703d5a652e90e4a852c0832f06fcb056328db2..fa734f432b27c8bcea9b692b40bfc2ddf0e8bb47 100644
--- a/arch/arm/src/stm32/stm32_waste.h
+++ b/arch/arm/src/stm32/stm32_waste.h
@@ -36,13 +36,7 @@
#ifndef __ARCH_ARM_SRC_STM32_STM32_WASTE_H
#define __ARCH_ARM_SRC_STM32_STM32_WASTE_H
-/** \file
- * \author Uros Platise
- * \brief Waste CPU Time
- *
- * \addtogroup STM32_WASTE
- * \{
- */
+/* Waste CPU Time */
/****************************************************************************
* Pre-processor Definitions
@@ -58,7 +52,6 @@ extern "C" {
#define EXTERN extern
#endif
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -76,10 +69,10 @@ extern "C" {
EXTERN void up_waste(void);
-
#undef EXTERN
#if defined(__cplusplus)
}
#endif
+
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_STM32_STM32_RRC_H */
diff --git a/arch/arm/src/stm32/stm32f10xxx_rcc.c b/arch/arm/src/stm32/stm32f10xxx_rcc.c
index 73ddc44f0f862434add352652fff890fb76845c9..07dda8a592e22245e6646741724439b2c395857d 100644
--- a/arch/arm/src/stm32/stm32f10xxx_rcc.c
+++ b/arch/arm/src/stm32/stm32f10xxx_rcc.c
@@ -512,31 +512,3 @@ static inline void rcc_enableperipherals(void)
/****************************************************************************
* Public Functions
****************************************************************************/
-
-/****************************************************************************
- * Name: stm32_rcc_enablelse
- *
- * Todo:
- * Check for LSE good timeout and return with -1,
- * possible ISR optimization? or at least ISR should be cough in case of failure
- *
- ****************************************************************************/
-
-void stm32_rcc_enablelse(void)
-{
- /* Enable LSE */
-
- modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_LSEON);
-
- /* We could wait for ISR here ... */
-
- while( !(getreg16(STM32_RCC_BDCR) & RCC_BDCR_LSERDY) ) up_waste();
-
- /* Select LSE as RTC Clock Source */
-
- modifyreg16(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL_LSE);
-
- /* Enable Clock */
-
- modifyreg16(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN);
-}
diff --git a/configs/stm3240g-eval/README.txt b/configs/stm3240g-eval/README.txt
index 3062c5fd98660857220e582fab514c3b94050fd4..2cf58633a6ebfcdf55526fa584349607c3424160 100755
--- a/configs/stm3240g-eval/README.txt
+++ b/configs/stm3240g-eval/README.txt
@@ -12,6 +12,7 @@ Contents
- IDEs
- NuttX buildroot Toolchain
- STM3240G-EVAL-specific Configuration Options
+ - LEDs
- Configurations
Development Environment
@@ -160,6 +161,31 @@ NuttX buildroot Toolchain
detailed PLUS some special instructions that you will need to follow if you are
building a Cortex-M3 toolchain for Cygwin under Windows.
+LEDs
+====
+
+The STM3240G-EVAL board has four LEDs labeled. Usage of these LEDs is defined
+in include/board.h and src/up_leds.c. They are encoded as follows:
+
+ SYMBOL Meaning LED1* LED2 LED3 LED4
+ ------------------- ----------------------- ------- ------- ------- ------
+ LED_STARTED NuttX has been started ON OFF OFF OFF
+ LED_HEAPALLOCATE Heap has been allocated OFF ON OFF OFF
+ LED_IRQSENABLED Interrupts enabled ON ON OFF OFF
+ LED_STACKCREATED Idle stack created OFF OFF ON OFF
+ LED_INIRQ In an interrupt** ON N/C N/C OFF
+ LED_SIGNAL In a signal handler*** N/C ON N/C OFF
+ LED_ASSERTION An assertion failed ON ON N/C OFF
+ LED_PANIC The system has crashed N/C N/C N/C ON
+ LED_IDLE STM32 is is sleep mode (Optional, not used)
+
+ * If LED1, LED2, LED3 are statically on, then NuttX probably failed to boot
+ and these LEDs will give you some indication of where the failure was
+ ** The normal state is LED3 ON and LED1 faintly glowing. This faint glow
+ is because of timer interupts that result in the LED being illuminated
+ on a small proportion of the time.
+*** LED2 may also flicker normally if signals are processed.
+
STM3240G-EVAL-specific Configuration Options
============================================
@@ -221,6 +247,10 @@ STM3240G-EVAL-specific Configuration Options
CONFIG_ARCH_IRQPRIO=y
+ CONFIG_ARCH_FPU - The STM3240xxx supports a floating point unit (FPU)
+
+ CONFIG_ARCH_FPU=y
+
CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that
have LEDs
diff --git a/configs/stm3240g-eval/include/board.h b/configs/stm3240g-eval/include/board.h
index 5ebc54bb7f694f158d018df7e0d33e92364f1827..b66997235ef53932d3cb99a8d5087682bcf53261 100755
--- a/configs/stm3240g-eval/include/board.h
+++ b/configs/stm3240g-eval/include/board.h
@@ -174,18 +174,28 @@
/* LED definitions ******************************************************************/
-#define LED_STARTED 0
-#define LED_HEAPALLOCATE 1
-#define LED_IRQSENABLED 2
-#define LED_STACKCREATED 3
-#define LED_INIRQ 4
-#define LED_SIGNAL 5
-#define LED_ASSERTION 6
-#define LED_PANIC 7
-
-/* The STM3240G-EVAL supports several buttons */
-
-#warning "Missing logic"
+/* The STM3240G-EVAL board has 4 LEDs that we will encode as: */
+
+#define LED_STARTED 0 /* LED1 */
+#define LED_HEAPALLOCATE 1 /* LED2 */
+#define LED_IRQSENABLED 2 /* LED1 + LED2 */
+#define LED_STACKCREATED 3 /* LED3 */
+#define LED_INIRQ 4 /* LED1 + LED3 */
+#define LED_SIGNAL 5 /* LED2 + LED3 */
+#define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */
+#define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */
+
+/* The STM3240G-EVAL supports three buttons: */
+
+#define BUTTON_WAKEUP 0
+#define BUTTON_TAMPER 1
+#define BUTTON_USER 2
+
+#define NUM_BUTTONS 3
+
+#define BUTTON_WAKEUP_BIT (1 << BUTTON_WAKEUP)
+#define BUTTON_TAMPER_BIT (1 << BUTTON_TAMPER)
+#define BUTTON_USER_BIT (1 << BUTTON_USER)
/* Alternate function pin selections ************************************************/
diff --git a/configs/stm3240g-eval/ostest/defconfig b/configs/stm3240g-eval/ostest/defconfig
index a796b77d1b1440fd84ddaedb03889a3cfc557f8c..5c6aaf8b00c89eed5bfc6cb6869760fd76501da2 100755
--- a/configs/stm3240g-eval/ostest/defconfig
+++ b/configs/stm3240g-eval/ostest/defconfig
@@ -52,7 +52,8 @@
# CONFIG_DRAM_SIZE - Describes the installed DRAM.
# CONFIG_DRAM_START - The start address of DRAM (physical)
# CONFIG_DRAM_END - Last address+1 of installed RAM
-# CONFIG_ARCH_IRQPRIO - The ST32F103Z supports interrupt prioritization
+# CONFIG_ARCH_IRQPRIO - The STM3240xxx supports interrupt prioritization
+# CONFIG_ARCH_FPU - The STM3240xxx supports a floating point unit (FPU)
# CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
# stack. If defined, this symbol is the size of the interrupt
# stack in bytes. If not defined, the user task stacks will be
@@ -81,6 +82,7 @@ CONFIG_DRAM_SIZE=0x00030000
CONFIG_DRAM_START=0x20000000
CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE)
CONFIG_ARCH_IRQPRIO=y
+CONFIG_ARCH_FPU=y
CONFIG_ARCH_INTERRUPTSTACK=n
CONFIG_ARCH_STACKDUMP=y
CONFIG_ARCH_BOOTLOADER=n
@@ -372,7 +374,7 @@ CONFIG_DEBUG=n
CONFIG_DEBUG_VERBOSE=n
CONFIG_DEBUG_SYMBOLS=n
CONFIG_HAVE_CXX=n
-CONFIG_MM_REGIONS=1
+CONFIG_MM_REGIONS=2
CONFIG_ARCH_LOWPUTC=y
CONFIG_RR_INTERVAL=200
CONFIG_SCHED_INSTRUMENTATION=n
diff --git a/configs/stm3240g-eval/src/stm3240g-internal.h b/configs/stm3240g-eval/src/stm3240g-internal.h
index 00206bedd36855cada2b2bf462ee0fd609b0a895..051d0be907c102a6ed98c83ccb5e5322c5e0a702 100644
--- a/configs/stm3240g-eval/src/stm3240g-internal.h
+++ b/configs/stm3240g-eval/src/stm3240g-internal.h
@@ -64,10 +64,25 @@
/* STM3240G-EVAL GPIOs ******************************************************************************/
/* LEDs */
-#warning "Missing logic"
-/* BUTTONS -- NOTE that some have EXTI interrupts configured */
-#warning "Missing logic"
+#define GPIO_LED1 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\
+ GPIO_OUTPUT_CLEAR|GPIO_PORTG|GPIO_PIN6)
+#define GPIO_LED2 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\
+ GPIO_OUTPUT_CLEAR|GPIO_PORTG|GPIO_PIN8)
+#define GPIO_LED3 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\
+ GPIO_OUTPUT_CLEAR|GPIO_PORTI|GPIO_PIN9)
+#define GPIO_LED4 (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\
+ GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN7)
+
+/* BUTTONS -- NOTE that all have EXTI interrupts configured */
+
+#define MIN_IRQBUTTON BUTTON_WAKEUP
+#define MAX_IRQBUTTON BUTTON_USER
+#define NUM_IRQBUTTONS (BUTTON_USER - BUTTON_WAKEUP + 1)
+
+#define GPIO_BTN_WAKEUP (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTA|GPIO_PIN0)
+#define GPIO_BTN_TAMPER (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTC|GPIO_PIN13)
+#define GPIO_BTN_USER (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTG|GPIO_PIN15)
/****************************************************************************************************
* Public Types
diff --git a/configs/stm3240g-eval/src/up_buttons.c b/configs/stm3240g-eval/src/up_buttons.c
index 9cde2211ce5f84fe26e55d0e56f204ba609700d4..522b8e4d9a935ba48e1b4ba3e8ee8fc12a6cc6ee 100644
--- a/configs/stm3240g-eval/src/up_buttons.c
+++ b/configs/stm3240g-eval/src/up_buttons.c
@@ -58,6 +58,15 @@
* Private Functions
****************************************************************************/
+/* Pin configuration for each STM3210E-EVAL button. This array is indexed by
+ * the BUTTON_* and JOYSTICK_* definitions in board.h
+ */
+
+static const uint16_t g_buttons[NUM_BUTTONS] =
+{
+ GPIO_BTN_WAKEUP, GPIO_BTN_TAMPER, GPIO_BTN_USER
+};
+
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -75,7 +84,16 @@
void up_buttoninit(void)
{
-#warning "Missing logic"
+ int i;
+
+ /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are
+ * configured for all pins.
+ */
+
+ for (i = 0; i < NUM_BUTTONS; i++)
+ {
+ stm32_configgpio(g_buttons[i]);
+ }
}
/****************************************************************************
@@ -84,7 +102,32 @@ void up_buttoninit(void)
uint8_t up_buttons(void)
{
-#warning "Missing logic"
+ uint8_t ret = 0;
+ int i;
+
+ /* Check that state of each key */
+
+ for (i = 0; i < NUM_BUTTONS; i++)
+ {
+ /* A LOW value means that the key is pressed for most keys. The exception
+ * is the WAKEUP button.
+ */
+
+ bool released = stm32_gpioread(g_buttons[i]);
+ if (i == BUTTON_WAKEUP)
+ {
+ released = !released;
+ }
+
+ /* Accumulate the set of depressed (not released) keys */
+
+ if (!released)
+ {
+ ret |= (1 << i);
+ }
+ }
+
+ return ret;
}
/************************************************************************************
@@ -113,7 +156,15 @@ uint8_t up_buttons(void)
#ifdef CONFIG_ARCH_IRQBUTTONS
xcpt_t up_irqbutton(int id, xcpt_t irqhandler)
{
-#warning "Missing logic"
+ xcpt_t oldhandler = NULL;
+
+ /* The following should be atomic */
+
+ if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON)
+ {
+ oldhandler = stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler);
+ }
+ return oldhandler;
}
#endif
#endif /* CONFIG_ARCH_BUTTONS */
diff --git a/configs/stm3240g-eval/src/up_leds.c b/configs/stm3240g-eval/src/up_leds.c
index 084fb69ffaf1e4a03cae10f2dbde2f7c20fce1da..f7635f54c53c09e6c7de72fd8400c12ad15dfbee 100644
--- a/configs/stm3240g-eval/src/up_leds.c
+++ b/configs/stm3240g-eval/src/up_leds.c
@@ -70,14 +70,155 @@
# define ledvdbg(x...)
#endif
+/* The following definitions map the encoded LED setting to GPIO settings */
+
+#define STM3210E_LED1 (1 << 0)
+#define STM3210E_LED2 (1 << 1)
+#define STM3210E_LED3 (1 << 2)
+#define STM3210E_LED4 (1 << 3)
+
+#define ON_SETBITS_SHIFT (0)
+#define ON_CLRBITS_SHIFT (4)
+#define OFF_SETBITS_SHIFT (8)
+#define OFF_CLRBITS_SHIFT (12)
+
+#define ON_BITS(v) ((v) & 0xff)
+#define OFF_BITS(v) (((v) >> 8) & 0x0ff)
+#define SETBITS(b) ((b) & 0x0f)
+#define CLRBITS(b) (((b) >> 4) & 0x0f)
+
+#define ON_SETBITS(v) (SETBITS(ON_BITS(v))
+#define ON_CLRBITS(v) (CLRBITS(ON_BITS(v))
+#define OFF_SETBITS(v) (SETBITS(OFF_BITS(v))
+#define OFF_CLRBITS(v) (CLRBITS(OFF_BITS(v))
+
+#define LED_STARTED_ON_SETBITS ((STM3210E_LED1) << ON_SETBITS_SHIFT)
+#define LED_STARTED_ON_CLRBITS ((STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT)
+#define LED_STARTED_OFF_SETBITS (0 << OFF_SETBITS_SHIFT)
+#define LED_STARTED_OFF_CLRBITS ((STM3210E_LED1|STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT)
+
+#define LED_HEAPALLOCATE_ON_SETBITS ((STM3210E_LED2) << ON_SETBITS_SHIFT)
+#define LED_HEAPALLOCATE_ON_CLRBITS ((STM3210E_LED1|STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT)
+#define LED_HEAPALLOCATE_OFF_SETBITS ((STM3210E_LED1) << OFF_SETBITS_SHIFT)
+#define LED_HEAPALLOCATE_OFF_CLRBITS ((STM3210E_LED2|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT)
+
+#define LED_IRQSENABLED_ON_SETBITS ((STM3210E_LED1|STM3210E_LED2) << ON_SETBITS_SHIFT)
+#define LED_IRQSENABLED_ON_CLRBITS ((STM3210E_LED3|STM3210E_LED4) << ON_CLRBITS_SHIFT)
+#define LED_IRQSENABLED_OFF_SETBITS ((STM3210E_LED2) << OFF_SETBITS_SHIFT)
+#define LED_IRQSENABLED_OFF_CLRBITS ((STM3210E_LED1|STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT)
+
+#define LED_STACKCREATED_ON_SETBITS ((STM3210E_LED3) << ON_SETBITS_SHIFT)
+#define LED_STACKCREATED_ON_CLRBITS ((STM3210E_LED1|STM3210E_LED2|STM3210E_LED4) << ON_CLRBITS_SHIFT)
+#define LED_STACKCREATED_OFF_SETBITS ((STM3210E_LED1|STM3210E_LED2) << OFF_SETBITS_SHIFT)
+#define LED_STACKCREATED_OFF_CLRBITS ((STM3210E_LED3|STM3210E_LED4) << OFF_CLRBITS_SHIFT)
+
+#define LED_INIRQ_ON_SETBITS ((STM3210E_LED1) << ON_SETBITS_SHIFT)
+#define LED_INIRQ_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT)
+#define LED_INIRQ_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT)
+#define LED_INIRQ_OFF_CLRBITS ((STM3210E_LED1) << OFF_CLRBITS_SHIFT)
+
+#define LED_SIGNAL_ON_SETBITS ((STM3210E_LED2) << ON_SETBITS_SHIFT)
+#define LED_SIGNAL_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT)
+#define LED_SIGNAL_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT)
+#define LED_SIGNAL_OFF_CLRBITS ((STM3210E_LED2) << OFF_CLRBITS_SHIFT)
+
+#define LED_ASSERTION_ON_SETBITS ((STM3210E_LED4) << ON_SETBITS_SHIFT)
+#define LED_ASSERTION_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT)
+#define LED_ASSERTION_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT)
+#define LED_ASSERTION_OFF_CLRBITS ((STM3210E_LED4) << OFF_CLRBITS_SHIFT)
+
+#define LED_PANIC_ON_SETBITS ((STM3210E_LED4) << ON_SETBITS_SHIFT)
+#define LED_PANIC_ON_CLRBITS ((0) << ON_CLRBITS_SHIFT)
+#define LED_PANIC_OFF_SETBITS ((0) << OFF_SETBITS_SHIFT)
+#define LED_PANIC_OFF_CLRBITS ((STM3210E_LED4) << OFF_CLRBITS_SHIFT)
+
/****************************************************************************
* Private Data
****************************************************************************/
+static const uint16_t g_ledbits[8] =
+{
+ (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS |
+ LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS),
+
+ (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS |
+ LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS),
+
+ (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS |
+ LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS),
+
+ (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS |
+ LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS),
+
+ (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS |
+ LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS),
+
+ (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS |
+ LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS),
+
+ (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS |
+ LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS),
+
+ (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS |
+ LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS)
+};
+
/****************************************************************************
* Private Functions
****************************************************************************/
+static inline void led_clrbits(unsigned int clrbits)
+{
+ if ((clrbits & STM3210E_LED1) != 0)
+ {
+ stm32_gpiowrite(GPIO_LED1, false);
+ }
+
+ if ((clrbits & STM3210E_LED2) != 0)
+ {
+ stm32_gpiowrite(GPIO_LED2, false);
+ }
+
+ if ((clrbits & STM3210E_LED3) != 0)
+ {
+ stm32_gpiowrite(GPIO_LED3, false);
+ }
+
+ if ((clrbits & STM3210E_LED4) != 0)
+ {
+ stm32_gpiowrite(GPIO_LED4, false);
+ }
+}
+
+static inline void led_setbits(unsigned int setbits)
+{
+ if ((setbits & STM3210E_LED1) != 0)
+ {
+ stm32_gpiowrite(GPIO_LED1, true);
+ }
+
+ if ((setbits & STM3210E_LED2) != 0)
+ {
+ stm32_gpiowrite(GPIO_LED2, true);
+ }
+
+ if ((setbits & STM3210E_LED3) != 0)
+ {
+ stm32_gpiowrite(GPIO_LED3, true);
+ }
+
+ if ((setbits & STM3210E_LED4) != 0)
+ {
+ stm32_gpiowrite(GPIO_LED4, true);
+ }
+}
+
+static void led_setonoff(unsigned int bits)
+{
+ led_clrbits(CLRBITS(bits));
+ led_setbits(SETBITS(bits));
+}
+
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -89,7 +230,12 @@
#ifdef CONFIG_ARCH_LEDS
void up_ledinit(void)
{
-#warning "Missing logic"
+ /* Configure LED1-4 GPIOs for output */
+
+ stm32_configgpio(GPIO_LED1);
+ stm32_configgpio(GPIO_LED2);
+ stm32_configgpio(GPIO_LED3);
+ stm32_configgpio(GPIO_LED4);
}
/****************************************************************************
@@ -98,7 +244,7 @@ void up_ledinit(void)
void up_ledon(int led)
{
-#warning "Missing logic"
+ led_setonoff(ON_BITS(g_ledbits[led]));
}
/****************************************************************************
@@ -107,7 +253,7 @@ void up_ledon(int led)
void up_ledoff(int led)
{
-#warning "Missing logic"
+ led_setonoff(OFF_BITS(g_ledbits[led]));
}
#endif /* CONFIG_ARCH_LEDS */