diff --git a/arch/arm/src/stm32/chip/stm32f40xxx_rcc.h b/arch/arm/src/stm32/chip/stm32f40xxx_rcc.h
index 5dd10ff6ba4d283367af94fb4b87304488c95c10..b1e292437be4447ecca0b2ad666a39d9d236c238 100644
--- a/arch/arm/src/stm32/chip/stm32f40xxx_rcc.h
+++ b/arch/arm/src/stm32/chip/stm32f40xxx_rcc.h
@@ -51,12 +51,12 @@
#define STM32_RCC_AHB3RSTR_OFFSET 0x0018 /* AHB3 peripheral reset register */
#define STM32_RCC_APB1RSTR_OFFSET 0x0020 /* APB1 Peripheral reset register */
#define STM32_RCC_APB2RSTR_OFFSET 0x0024 /* APB2 Peripheral reset register */
-#define STM32_RCC_AH1BENR_OFFSET 0x0030 /* AHB1 Peripheral Clock enable register */
+#define STM32_RCC_AHB1ENR_OFFSET 0x0030 /* AHB1 Peripheral Clock enable register */
#define STM32_RCC_AHB2ENR_OFFSET 0x0034 /* AHB2 Peripheral Clock enable register */
#define STM32_RCC_AHB3ENR_OFFSET 0x0038 /* AHB3 Peripheral Clock enable register */
#define STM32_RCC_APB1ENR_OFFSET 0x0040 /* APB1 Peripheral Clock enable register */
#define STM32_RCC_APB2ENR_OFFSET 0x0044 /* APB2 Peripheral Clock enable register */
-#define STM32_RCC_AH1BLPENR_OFFSET 0x0050 /* RCC AHB1 low power modeperipheral clock enable register */
+#define STM32_RCC_AHB1LPENR_OFFSET 0x0050 /* RCC AHB1 low power modeperipheral clock enable register */
#define STM32_RCC_AH2BLPENR_OFFSET 0x0054 /* RCC AHB2 low power modeperipheral clock enable register */
#define STM32_RCC_AH3BLPENR_OFFSET 0x0058 /* RCC AHB3 low power modeperipheral clock enable register */
#define STM32_RCC_APB1LPENR_OFFSET 0x0060 /* RCC APB1 low power modeperipheral clock enable register */
@@ -82,7 +82,7 @@
#define STM32_RCC_AHB3ENR (STM32_RCC_BASE+STM32_RCC_AHB3ENR_OFFSET)
#define STM32_RCC_APB1ENR (STM32_RCC_BASE+STM32_RCC_APB1ENR_OFFSET)
#define STM32_RCC_APB2ENR (STM32_RCC_BASE+STM32_RCC_APB2ENR_OFFSET)
-#define STM32_RCC_AH1BLPENR (STM32_RCC_BASE+STM32_RCC_AH1BLPENR_OFFSET)
+#define STM32_RCC_AHB1LPENR (STM32_RCC_BASE+STM32_RCC_AHB1LPENR_OFFSET)
#define STM32_RCC_AH2BLPENR (STM32_RCC_BASE+STM32_RCC_AH2BLPENR)
#define STM32_RCC_AH3BLPENR (STM32_RCC_BASE+STM32_RCC_AH3BLPENR_OFFSET)
#define STM32_RCC_APB1LPENR (STM32_RCC_BASE+STM32_RCC_APB1LPENR_OFFSET)
@@ -121,18 +121,23 @@
#define RCC_PLLCFG_PLLN_MASK (0x1ff << RCC_PLLCFG_PLLN_SHIFT)
# define RCC_PLLCFG_PLLN(n) ((n) << RCC_PLLCFG_PLLN_SHIFT) /* n = 2..432 */
#define RCC_PLLCFG_PLLP_SHIFT (16) /* Bits 16-17: Main PLL (PLL) main system clock divider */
-#define RCC_PLLCFG_PLLP_MASK (3 << RCC_PLLCFG_PLLSRC)
-# define RCC_PLLCFG_PLLP_2 (0 << RCC_PLLCFG_PLLSRC) /* 00: PLLP = 2 */
-# define RCC_PLLCFG_PLLP_4 (1 << RCC_PLLCFG_PLLSRC) /* 01: PLLP = 4 */
-# define RCC_PLLCFG_PLLP_6 (2 << RCC_PLLCFG_PLLSRC) /* 10: PLLP = 6 */
-# define RCC_PLLCFG_PLLP_8 (3 << RCC_PLLCFG_PLLSRC) /* 11: PLLP = 8 */
+#define RCC_PLLCFG_PLLP_MASK (3 << RCC_PLLCFG_PLLP_SHIFT)
+# define RCC_PLLCFG_PLLP(n) ((((n)>>1)-1)<< RCC_PLLCFG_PLLP_SHIFT) /* n=2,4,6,8 */
+# define RCC_PLLCFG_PLLP_2 (0 << RCC_PLLCFG_PLLP_SHIFT) /* 00: PLLP = 2 */
+# define RCC_PLLCFG_PLLP_4 (1 << RCC_PLLCFG_PLLP_SHIFT) /* 01: PLLP = 4 */
+# define RCC_PLLCFG_PLLP_6 (2 << RCC_PLLCFG_PLLP_SHIFT) /* 10: PLLP = 6 */
+# define RCC_PLLCFG_PLLP_8 (3 << RCC_PLLCFG_PLLP_SHIFT) /* 11: PLLP = 8 */
#define RCC_PLLCFG_PLLSRC (1 << 22) /* Bit 22: Main PLL(PLL) and audio PLL (PLLI2S)
* entry clock source */
+# define RCC_PLLCFG_PLLSRC_HSI (0)
+# define RCC_PLLCFG_PLLSRC_HSE RCC_PLLCFG_PLLSRC
#define RCC_PLLCFG_PLLQ_SHIFT (24) /* Bits 24-27: Main PLL (PLL) divider
* (USB OTG FS, SDIO and RNG clocks) */
#define RCC_PLLCFG_PLLQ_MASK (15 << RCC_PLLCFG_PLLQ_SHIFT)
# define RCC_PLLCFG_PLLQ(n) ((n) << RCC_PLLCFG_PLLQ_SHIFT) /* n=2..15 */
+#define RCC_PLLCFG_RESET (0x24003010) /* PLLCFG reset value */
+
/* Clock configuration register */
#define RCC_CFGR_SW_SHIFT (0) /* Bits 0-1: System clock Switch */
@@ -294,27 +299,27 @@
/* AHB1 Peripheral Clock enable register */
-#define RCC_AH1BENR_GPIOEN(n) (1 << (n))
-#define RCC_AH1BENR_GPIOAEN (1 << 0) /* Bit 0: IO port A clock enable */
-#define RCC_AH1BENR_GPIOBEN (1 << 1) /* Bit 1: IO port B clock enable */
-#define RCC_AH1BENR_GPIOCEN (1 << 2) /* Bit 2: IO port C clock enable */
-#define RCC_AH1BENR_GPIODEN (1 << 3) /* Bit 3: IO port D clock enable */
-#define RCC_AH1BENR_GPIOEEN (1 << 4) /* Bit 4: IO port E clock enable */
-#define RCC_AH1BENR_GPIOFEN (1 << 5) /* Bit 5: IO port F clock enable */
-#define RCC_AH1BENR_GPIOGEN (1 << 6) /* Bit 6: IO port G clock enable */
-#define RCC_AH1BENR_GPIOHEN (1 << 7) /* Bit 7: IO port H clock enable */
-#define RCC_AH1BENR_GPIOIEN (1 << 8) /* Bit 8: IO port I clock enable */
-#define RCC_AH1BENR_CRCEN (1 << 12) /* Bit 12: CRC clock enable */
-#define RCC_AH1BENR_BKPSRAMEN (1 << 18) /* Bit 18: Backup SRAM interface clock enable */
-#define RCC_AH1BENR_CCMDATARAMEN (1 << 20) /* Bit 20: CCM data RAM clock enable */
-#define RCC_AH1BENR_DMA1EN (1 << 21) /* Bit 21: DMA1 clock enable */
-#define RCC_AH1BENR_DMA2EN (1 << 22) /* Bit 22: DMA2 clock enable */
-#define RCC_AH1BENR_ETHMACEN (1 << 25) /* Bit 25: Ethernet MAC clock enable */
-#define RCC_AH1BENR_ETHMACTXEN (1 << 26) /* Bit 26: Ethernet Transmission clock enable */
-#define RCC_AH1BENR_ETHMACRXEN (1 << 27) /* Bit 27: Ethernet Reception clock enable */
-#define RCC_AH1BENR_ETHMACPTPEN (1 << 28) /* Bit 28: Ethernet PTP clock enable */
-#define RCC_AH1BENR_OTGHSEN (1 << 29) /* Bit 29: USB OTG HS clock enable */
-#define RCC_AH1BENR_OTGHSULPIEN (1 << 30) /* Bit 30: USB OTG HSULPI clock enable */
+#define RCC_AHB1ENR_GPIOEN(n) (1 << (n))
+#define RCC_AHB1ENR_GPIOAEN (1 << 0) /* Bit 0: IO port A clock enable */
+#define RCC_AHB1ENR_GPIOBEN (1 << 1) /* Bit 1: IO port B clock enable */
+#define RCC_AHB1ENR_GPIOCEN (1 << 2) /* Bit 2: IO port C clock enable */
+#define RCC_AHB1ENR_GPIODEN (1 << 3) /* Bit 3: IO port D clock enable */
+#define RCC_AHB1ENR_GPIOEEN (1 << 4) /* Bit 4: IO port E clock enable */
+#define RCC_AHB1ENR_GPIOFEN (1 << 5) /* Bit 5: IO port F clock enable */
+#define RCC_AHB1ENR_GPIOGEN (1 << 6) /* Bit 6: IO port G clock enable */
+#define RCC_AHB1ENR_GPIOHEN (1 << 7) /* Bit 7: IO port H clock enable */
+#define RCC_AHB1ENR_GPIOIEN (1 << 8) /* Bit 8: IO port I clock enable */
+#define RCC_AHB1ENR_CRCEN (1 << 12) /* Bit 12: CRC clock enable */
+#define RCC_AHB1ENR_BKPSRAMEN (1 << 18) /* Bit 18: Backup SRAM interface clock enable */
+#define RCC_AHB1ENR_CCMDATARAMEN (1 << 20) /* Bit 20: CCM data RAM clock enable */
+#define RCC_AHB1ENR_DMA1EN (1 << 21) /* Bit 21: DMA1 clock enable */
+#define RCC_AHB1ENR_DMA2EN (1 << 22) /* Bit 22: DMA2 clock enable */
+#define RCC_AHB1ENR_ETHMACEN (1 << 25) /* Bit 25: Ethernet MAC clock enable */
+#define RCC_AHB1ENR_ETHMACTXEN (1 << 26) /* Bit 26: Ethernet Transmission clock enable */
+#define RCC_AHB1ENR_ETHMACRXEN (1 << 27) /* Bit 27: Ethernet Reception clock enable */
+#define RCC_AHB1ENR_ETHMACPTPEN (1 << 28) /* Bit 28: Ethernet PTP clock enable */
+#define RCC_AHB1ENR_OTGHSEN (1 << 29) /* Bit 29: USB OTG HS clock enable */
+#define RCC_AHB1ENR_OTGHSULPIEN (1 << 30) /* Bit 30: USB OTG HSULPI clock enable */
/* AHB2 Peripheral Clock enable register */
@@ -372,30 +377,30 @@
/* RCC AHB1 low power modeperipheral clock enable register */
-#define RCC_AH1BLPENR_GPIOLPEN(n) (1 << (n))
-#define RCC_AH1BLPENR_GPIOALPEN (1 << 0) /* Bit 0: IO port A clock enable during Sleep mode */
-#define RCC_AH1BLPENR_GPIOBLPEN (1 << 1) /* Bit 1: IO port B clock enable during Sleep mode */
-#define RCC_AH1BLPENR_GPIOCLPEN (1 << 2) /* Bit 2: IO port C clock enable during Sleep mode */
-#define RCC_AH1BLPENR_GPIODLPEN (1 << 3) /* Bit 3: IO port D clock enable during Sleep mode */
-#define RCC_AH1BLPENR_GPIOELPEN (1 << 4) /* Bit 4: IO port E clock enable during Sleep mode */
-#define RCC_AH1BLPENR_GPIOFLPEN (1 << 5) /* Bit 5: IO port F clock enable during Sleep mode */
-#define RCC_AH1BLPENR_GPIOGLPEN (1 << 6) /* Bit 6: IO port G clock enable during Sleep mode */
-#define RCC_AH1BLPENR_GPIOHLPEN (1 << 7) /* Bit 7: IO port H clock enable during Sleep mode */
-#define RCC_AH1BLPENR_GPIOILPEN (1 << 8) /* Bit 8: IO port I clock enable during Sleep mode */
-#define RCC_AH1BLPENR_CRCLPEN (1 << 12) /* Bit 12: CRC clock enable during Sleep mode */
-#define RCC_AH1BLPENR_FLITFLPEN (1 << 15) /* Bit 15: Flash interface clock enable during Sleep mode */
-#define RCC_AH1BLPENR_SRAM1LPEN (1 << 16) /* Bit 16: SRAM 1 interface clock enable during Sleep mode */
-#define RCC_AH1BLPENR_SRAM2LPEN (1 << 17) /* Bit 17: SRAM 2 interface clock enable during Sleep mode */
-#define RCC_AH1BLPENR_BKPSRAMLPEN (1 << 18) /* Bit 18: Backup SRAM interface clock enable during Sleep mode */
-#define RCC_AH1BLPENR_CCMDATARAMLPEN (1 << 20) /* Bit 20: CCM data RAM clock enable during Sleep mode */
-#define RCC_AH1BLPENR_DMA1LPEN (1 << 21) /* Bit 21: DMA1 clock enable during Sleep mode */
-#define RCC_AH1BLPENR_DMA2LPEN (1 << 22) /* Bit 22: DMA2 clock enable during Sleep mode */
-#define RCC_AH1BLPENR_ETHMACLPEN (1 << 25) /* Bit 25: Ethernet MAC clock enable during Sleep mode */
-#define RCC_AH1BLPENR_ETHMACTXLPEN (1 << 26) /* Bit 26: Ethernet Transmission clock enable during Sleep mode */
-#define RCC_AH1BLPENR_ETHMACRXLPEN (1 << 27) /* Bit 27: Ethernet Reception clock enable during Sleep mode */
-#define RCC_AH1BLPENR_ETHMACPTPLPEN (1 << 28) /* Bit 28: Ethernet PTP clock enable during Sleep mode */
-#define RCC_AH1BLPENR_OTGHSLPEN (1 << 29) /* Bit 29: USB OTG HS clock enable during Sleep mode */
-#define RCC_AH1BLPENR_OTGHSULPILPEN (1 << 30) /* Bit 30: USB OTG HSULPI clock enable during Sleep mode */
+#define RCC_AHB1LPENR_GPIOLPEN(n) (1 << (n))
+#define RCC_AHB1LPENR_GPIOALPEN (1 << 0) /* Bit 0: IO port A clock enable during Sleep mode */
+#define RCC_AHB1LPENR_GPIOBLPEN (1 << 1) /* Bit 1: IO port B clock enable during Sleep mode */
+#define RCC_AHB1LPENR_GPIOCLPEN (1 << 2) /* Bit 2: IO port C clock enable during Sleep mode */
+#define RCC_AHB1LPENR_GPIODLPEN (1 << 3) /* Bit 3: IO port D clock enable during Sleep mode */
+#define RCC_AHB1LPENR_GPIOELPEN (1 << 4) /* Bit 4: IO port E clock enable during Sleep mode */
+#define RCC_AHB1LPENR_GPIOFLPEN (1 << 5) /* Bit 5: IO port F clock enable during Sleep mode */
+#define RCC_AHB1LPENR_GPIOGLPEN (1 << 6) /* Bit 6: IO port G clock enable during Sleep mode */
+#define RCC_AHB1LPENR_GPIOHLPEN (1 << 7) /* Bit 7: IO port H clock enable during Sleep mode */
+#define RCC_AHB1LPENR_GPIOILPEN (1 << 8) /* Bit 8: IO port I clock enable during Sleep mode */
+#define RCC_AHB1LPENR_CRCLPEN (1 << 12) /* Bit 12: CRC clock enable during Sleep mode */
+#define RCC_AHB1LPENR_FLITFLPEN (1 << 15) /* Bit 15: Flash interface clock enable during Sleep mode */
+#define RCC_AHB1LPENR_SRAM1LPEN (1 << 16) /* Bit 16: SRAM 1 interface clock enable during Sleep mode */
+#define RCC_AHB1LPENR_SRAM2LPEN (1 << 17) /* Bit 17: SRAM 2 interface clock enable during Sleep mode */
+#define RCC_AHB1LPENR_BKPSRAMLPEN (1 << 18) /* Bit 18: Backup SRAM interface clock enable during Sleep mode */
+#define RCC_AHB1LPENR_CCMDATARAMLPEN (1 << 20) /* Bit 20: CCM data RAM clock enable during Sleep mode */
+#define RCC_AHB1LPENR_DMA1LPEN (1 << 21) /* Bit 21: DMA1 clock enable during Sleep mode */
+#define RCC_AHB1LPENR_DMA2LPEN (1 << 22) /* Bit 22: DMA2 clock enable during Sleep mode */
+#define RCC_AHB1LPENR_ETHMACLPEN (1 << 25) /* Bit 25: Ethernet MAC clock enable during Sleep mode */
+#define RCC_AHB1LPENR_ETHMACTXLPEN (1 << 26) /* Bit 26: Ethernet Transmission clock enable during Sleep mode */
+#define RCC_AHB1LPENR_ETHMACRXLPEN (1 << 27) /* Bit 27: Ethernet Reception clock enable during Sleep mode */
+#define RCC_AHB1LPENR_ETHMACPTPLPEN (1 << 28) /* Bit 28: Ethernet PTP clock enable during Sleep mode */
+#define RCC_AHB1LPENR_OTGHSLPEN (1 << 29) /* Bit 29: USB OTG HS clock enable during Sleep mode */
+#define RCC_AHB1LPENR_OTGHSULPILPEN (1 << 30) /* Bit 30: USB OTG HSULPI clock enable during Sleep mode */
/* RCC AHB2 low power modeperipheral clock enable register */
diff --git a/arch/arm/src/stm32/stm32f10xxx_rcc.c b/arch/arm/src/stm32/stm32f10xxx_rcc.c
index f970b9668e8aba496e0c366e2860393f614f9aa2..73ddc44f0f862434add352652fff890fb76845c9 100644
--- a/arch/arm/src/stm32/stm32f10xxx_rcc.c
+++ b/arch/arm/src/stm32/stm32f10xxx_rcc.c
@@ -43,7 +43,8 @@
/* Allow up to 100 milliseconds for the high speed clock to become ready.
* that is a very long delay, but if the clock does not become ready we are
- * hosed anyway.
+ * hosed anyway. Normally this is very fast, but I have seen at least one
+ * board that required this long, long timeout for the HSE to be ready.
*/
#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
diff --git a/arch/arm/src/stm32/stm32f40xxx_rcc.c b/arch/arm/src/stm32/stm32f40xxx_rcc.c
index 004a0dface216b7487974db9258dd08b3349220b..57227f08fdd758c1fb162b47066d0a4ffa6e2fb6 100644
--- a/arch/arm/src/stm32/stm32f40xxx_rcc.c
+++ b/arch/arm/src/stm32/stm32f40xxx_rcc.c
@@ -37,10 +37,20 @@
* Included Files
****************************************************************************/
+#include "stm32_pwr.h"
+
/****************************************************************************
* Definitions
****************************************************************************/
+/* Allow up to 100 milliseconds for the high speed clock to become ready.
+ * that is a very long delay, but if the clock does not become ready we are
+ * hosed anyway. Normally this is very fast, but I have seen at least one
+ * board that required this long, long timeout for the HSE to be ready.
+ */
+
+#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
+
/****************************************************************************
* Private Data
****************************************************************************/
@@ -53,13 +63,43 @@
* Name: rcc_reset
*
* Description:
- * Put all RCC registers in reset state
+ * Reset the RCC clock configuration to the default reset state
*
****************************************************************************/
static inline void rcc_reset(void)
{
-#warning "Missing logic"
+ uint32_t regval;
+
+ /* Enable the Internal High Speed clock (HSI) */
+
+ regval = getreg32(STM32_RCC_CR);
+ regval |= RCC_CR_HSION;
+ putreg32(regval, STM32_RCC_CR);
+
+ /* Reset CFGR register */
+
+ putreg32(0x00000000, STM32_RCC_CFGR);
+
+ /* Reset HSEON, CSSON and PLLON bits */
+
+ regval = getreg32(STM32_RCC_CR);
+ regval &= ~(RCC_CR_HSEON|RCC_CR_CSSON|RCC_CR_PLLON);
+ putreg32(regval, STM32_RCC_CR);
+
+ /* Reset PLLCFGR register to reset default */
+
+ putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG);
+
+ /* Reset HSEBYP bit */
+
+ regval = getreg32(STM32_RCC_CR);
+ regval &= ~RCC_CR_HSEBYP;
+ putreg32(regval, STM32_RCC_CR);
+
+ /* Disable all interrupts */
+
+ putreg32(0x00000000, STM32_RCC_CIR);
}
/****************************************************************************
@@ -72,7 +112,89 @@ static inline void rcc_reset(void)
static inline void rcc_enableahb1(void)
{
-#warning "Missing logic"
+ uint32_t regval;
+
+ /* Set the appropriate bits in the AHB1ENR register to enabled the
+ * selected AHB1 peripherals.
+ */
+
+ regval = getreg32(STM32_RCC_APB1ENR);
+
+ /* Enable GPIOA, GPIOB, .... GPIOI*/
+
+#if STM32_NGPIO > 0
+ regval |= (RCC_AHB1ENR_GPIOAEN
+#if STM32_NGPIO > 16
+ |RCC_AHB1ENR_GPIOBEN
+#endif
+#if STM32_NGPIO > 32
+ |RCC_AHB1ENR_GPIOCEN
+#endif
+#if STM32_NGPIO > 48
+ |RCC_AHB1ENR_GPIODEN
+#endif
+#if STM32_NGPIO > 64
+ |RCC_AHB1ENR_GPIOEEN
+#endif
+#if STM32_NGPIO > 80
+ |RCC_AHB1ENR_GPIOFEN
+#endif
+#if STM32_NGPIO > 96
+ |RCC_AHB1ENR_GPIOGEN
+#endif
+#if STM32_NGPIO > 112
+ |RCC_AHB1ENR_GPIOHEN
+#endif
+#if STM32_NGPIO > 128
+ |RCC_AHB1ENR_GPIOIEN
+#endif
+ );
+#endif
+
+#if CONFIG_STM32_CRC
+ /* CRC clock enable */
+
+ regval |= RCC_AHB1ENR_CRCEN;
+#endif
+
+#if CONFIG_STM32_BKPSRAM
+ /* Backup SRAM clock enable */
+
+ regval |= RCC_AHB1ENR_BKPSRAMEN;
+#endif
+
+#if CONFIG_STM32_CCMDATARAM
+ /* CCM data RAM clock enable */
+
+ regval |= RCC_AHB1ENR_CCMDATARAMEN;
+#endif
+
+#if CONFIG_STM32_DMA1
+ /* DMA 1 clock enable */
+
+ regval |= RCC_AHB1ENR_DMA1EN;
+#endif
+
+#if CONFIG_STM32_DMA2
+ /* DMA 2 clock enable */
+
+ regval |= RCC_AHB1ENR_DMA2EN;
+#endif
+
+#ifdef CONFIG_STM32_ETHMAC
+ /* Ethernet MAC clocking */
+
+ regval |= (RCC_AHB1ENR_ETHMACEN|RCC_AHB1ENR_ETHMACTXEN|
+ RCC_AHB1ENR_ETHMACRXEN|RCC_AHB1ENR_ETHMACPTPEN)
+#endif
+
+#ifdef CONFIG_STM32_OTGHS
+ /* USB OTG HS */
+
+ regval |= (RCC_AHB1ENR_OTGHSEN|RCC_AHB1ENR_OTGHSULPIEN);
+#endif
+
+ putreg32(regval, STM32_RCC_APB1ENR); /* Enable peripherals */
}
/****************************************************************************
@@ -85,7 +207,45 @@ static inline void rcc_enableahb1(void)
static inline void rcc_enableahb2(void)
{
-#warning "Missing logic"
+ uint32_t regval;
+
+ /* Set the appropriate bits in the AHB2ENR register to enabled the
+ * selected AHB2 peripherals.
+ */
+
+ regval = getreg32(STM32_RCC_AHB2ENR);
+
+#if CONFIG_STM32_DCMI
+ /* Camera interface enable */
+
+ regval |= RCC_AHB2ENR_DCMIEN;
+#endif
+
+#if CONFIG_STM32_CRYP
+ /* Cryptographic modules clock enable */
+
+ regval |= RCC_AHB2ENR_CRYPEN;
+#endif
+
+#if CONFIG_STM32_HASH
+ /* Hash modules clock enable */
+
+ regval |= RCC_AHB2ENR_HASHEN;
+#endif
+
+#if CONFIG_STM32_RNG
+ /* Random number generator clock enable */
+
+ regval |= RCC_AHB2ENR_RNGEN;
+#endif
+
+#if CONFIG_STM32_OTGFS
+ /* USB OTG FS clock enable */
+
+ regval |= RCC_AHB2ENR_OTGFSEN;
+#endif
+
+ putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */
}
/****************************************************************************
@@ -98,7 +258,21 @@ static inline void rcc_enableahb2(void)
static inline void rcc_enableahb3(void)
{
-#warning "Missing logic"
+#if CONFIG_STM32_FSMC
+ uint32_t regval;
+
+ /* Set the appropriate bits in the AHB3ENR register to enabled the
+ * selected AHB3 peripherals.
+ */
+
+ regval = getreg32(STM32_RCC_AHB3ENR);
+
+ /* Flexible static memory controller module clock enable */
+
+ regval |= RCC_AHB3ENR_FSMCEN;
+
+ putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */
+#endif
}
/****************************************************************************
@@ -111,7 +285,153 @@ static inline void rcc_enableahb3(void)
static inline void rcc_enableapb1(void)
{
-#warning "Missing logic"
+ uint32_t regval;
+
+ /* Set the appropriate bits in the APB1ENR register to enabled the
+ * selected APB1 peripherals.
+ */
+
+ regval = getreg32(STM32_RCC_APB1ENR);
+
+#if CONFIG_STM32_TIM2
+ /* TIM2 clock enable */
+
+ regval |= RCC_APB1ENR_TIM2EN;
+#endif
+
+#if CONFIG_STM32_TIM3
+ /* TIM3 clock enable */
+
+ regval |= RCC_APB1ENR_TIM3EN;
+#endif
+
+#if CONFIG_STM32_TIM4
+ /* TIM4 clock enable */
+
+ regval |= RCC_APB1ENR_TIM4EN;
+#endif
+
+#if CONFIG_STM32_TIM5
+ /* TIM5 clock enable */
+
+ regval |= RCC_APB1ENR_TIM5EN;
+#endif
+
+#if CONFIG_STM32_TIM6
+ /* TIM6 clock enable */
+
+ regval |= RCC_APB1ENR_TIM6EN;
+#endif
+
+#if CONFIG_STM32_TIM7
+ /* TIM7 clock enable */
+
+ regval |= RCC_APB1ENR_TIM7EN;
+#endif
+
+#if CONFIG_STM32_TIM12
+ /* TIM12 clock enable */
+
+ regval |= RCC_APB1ENR_TIM12EN;
+#endif
+
+#if CONFIG_STM32_TIM13
+ /* TIM13 clock enable */
+
+ regval |= RCC_APB1ENR_TIM13EN;
+#endif
+
+#if CONFIG_STM32_TIM14
+ /* TIM14 clock enable */
+
+ regval |= RCC_APB1ENR_TIM14EN;
+#endif
+
+#if CONFIG_STM32_WWDG
+ /* Window watchdog clock enable */
+
+ regval |= RCC_APB1ENR_WWDGEN;
+#endif
+
+#if CONFIG_STM32_SPI2
+ /* SPI2 clock enable */
+
+ regval |= RCC_APB1ENR_SPI2EN;
+#endif
+
+#if CONFIG_STM32_SPI3
+ /* SPI3 clock enable */
+
+ regval |= RCC_APB1ENR_SPI3EN;
+#endif
+
+#if CONFIG_STM32_USART2
+ /* USART 2 clock enable */
+
+ regval |= RCC_APB1ENR_USART2EN;
+#endif
+
+#if CONFIG_STM32_USART3
+ /* USART3 clock enable */
+
+ regval |= RCC_APB1ENR_USART3EN;
+#endif
+
+#if CONFIG_STM32_UART4
+ /* UART4 clock enable */
+
+ regval |= RCC_APB1ENR_UART4EN;
+#endif
+
+#if CONFIG_STM32_UART5
+ /* UART5 clock enable */
+
+ regval |= RCC_APB1ENR_UART5EN;
+#endif
+
+#if CONFIG_STM32_I2C1
+ /* I2C1 clock enable */
+
+ regval |= RCC_APB1ENR_I2C1EN;
+#endif
+
+#if CONFIG_STM32_I2C2
+ /* I2C2 clock enable */
+
+ regval |= RCC_APB1ENR_I2C2EN;
+#endif
+
+#if CONFIG_STM32_I2C3
+ /* I2C3 clock enable */
+
+ regval |= RCC_APB1ENR_I2C3EN;
+#endif
+
+#if CONFIG_STM32_CAN1
+ /* CAN 1 clock enable */
+
+ regval |= RCC_APB1ENR_CAN1EN;
+#endif
+
+#if CONFIG_STM32_CAN2
+ /* CAN 2 clock enable */
+
+ regval |= RCC_APB1ENR_CAN2EN;
+#endif
+
+ /* Power interface clock enable. The PWR block is always enabled so that
+ * we can set the internal voltage regulator for maximum performanc.
+ */
+
+ regval |= RCC_APB1ENR_PWREN;
+
+#if CONFIG_STM32_DAC
+ /* DAC interface clock enable */
+
+ regval |= RCC_APB1ENR_DACEN;
+#endif
+
+ putreg32(regval, STM32_RCC_APB1ENR); /* Enable peripherals */
}
/****************************************************************************
@@ -124,7 +444,93 @@ static inline void rcc_enableapb1(void)
static inline void rcc_enableapb2(void)
{
-#warning "Missing logic"
+ uint32_t regval;
+
+ /* Set the appropriate bits in the APB2ENR register to enabled the
+ * selected APB2 peripherals.
+ */
+
+ regval = getreg32(STM32_RCC_APB2ENR);
+
+#if CONFIG_STM32_TIM1
+ /* TIM1 clock enable */
+
+ regval |= RCC_APB2ENR_TIM1EN;
+#endif
+
+#if CONFIG_STM32_TIM8
+ /* TIM8 clock enable */
+
+ regval |= RCC_APB2ENR_TIM8EN;
+#endif
+
+#if CONFIG_STM32_USART1
+ /* USART1 clock enable */
+
+ regval |= RCC_APB2ENR_USART1EN;
+#endif
+
+#if CONFIG_STM32_USART6
+ /* USART6 clock enable */
+
+ regval |= RCC_APB2ENR_USART6EN;
+#endif
+
+#if CONFIG_STM32_ADC1
+ /* ADC1 clock enable */
+
+ regval |= RCC_APB2ENR_ADC1EN;
+#endif
+
+#if CONFIG_STM32_ADC2
+ /* ADC2 clock enable */
+
+ regval |= RCC_APB2ENR_ADC2EN;
+#endif
+
+#if CONFIG_STM32_ADC3
+ /* ADC3 clock enable */
+
+ regval |= RCC_APB2ENR_ADC3EN;
+#endif
+
+#if CONFIG_STM32_SDIO
+ /* SDIO clock enable */
+
+ regval |= RCC_APB2ENR_SDIOEN;
+#endif
+
+#if CONFIG_STM32_SPI1
+ /* SPI1 clock enable */
+
+ regval |= RCC_APB2ENR_SPI1EN;
+#endif
+
+#if CONFIG_STM32_SYSCFG
+ /* System configuration controller clock enable */
+
+ regval |= RCC_APB2ENR_SYSCFGEN;
+#endif
+
+#if CONFIG_STM32_TIM9
+ /* TIM9 clock enable */
+
+ regval |= RCC_APB2ENR_TIM9EN;
+#endif
+
+#if CONFIG_STM32_TIM10
+ /* TIM10 clock enable */
+
+ regval |= RCC_APB2ENR_TIM10EN;
+#endif
+
+#if CONFIG_STM32_TIM11
+ /* TIM11 clock enable */
+
+ regval |= RCC_APB2ENR_TIM11EN;
+#endif
+
+ putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */
}
/****************************************************************************
@@ -140,7 +546,101 @@ static inline void rcc_enableapb2(void)
#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
static inline void stm32_stdclockconfig(void)
{
-#warning "Missing logic"
+ uint32_t regval;
+ volatile int32_t timeout;
+
+ /* Enable External High-Speed Clock (HSE) */
+
+ regval = getreg32(STM32_RCC_CR);
+ regval |= RCC_CR_HSEON; /* Enable HSE */
+ putreg32(regval, STM32_RCC_CR);
+
+ /* Wait until the HSE is ready (or until a timeout elapsed) */
+
+ for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
+ {
+ /* Check if the HSERDY flag is the set in the CR */
+
+ if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
+ {
+ /* If so, then break-out with timeout > 0 */
+
+ break;
+ }
+ }
+
+ /* Check for a timeout. If this timeout occurs, then we are hosed. We
+ * have no real back-up plan, although the following logic makes it look
+ * as though we do.
+ */
+
+ if (timeout > 0)
+ {
+ /* Select regulator voltage output Scale 1 mode to support system
+ * frequencies up to 168 MHz.
+ */
+
+ regval = getreg32(STM32_RCC_APB1ENR);
+ regval |= RCC_APB1ENR_PWREN;
+ putreg32(regval, STM32_RCC_APB1ENR);
+
+ regval = getreg32(STM32_PWR_CR);
+ regval |= PWR_CR_VOS;
+ putreg32(regval, STM32_PWR_CR);
+
+ /* Set the HCLK source/divider */
+
+ regval = getreg32(STM32_RCC_CFGR);
+ regval &= ~RCC_CFGR_HPRE_MASK;
+ regval |= STM32_RCC_CFGR_HPRE;
+ putreg32(regval, STM32_RCC_CFGR);
+
+ /* Set the PCLK2 divider */
+
+ regval = getreg32(STM32_RCC_CFGR);
+ regval &= ~RCC_CFGR_PPRE2_MASK;
+ regval |= STM32_RCC_CFGR_PPRE2;
+ putreg32(regval, STM32_RCC_CFGR);
+
+ /* Set the PCLK1 divider */
+
+ regval = getreg32(STM32_RCC_CFGR);
+ regval &= ~RCC_CFGR_PPRE1_MASK;
+ regval |= STM32_RCC_CFGR_PPRE1;
+ putreg32(regval, STM32_RCC_CFGR);
+
+ /* Set the PLL dividers and multiplers to configure the main PLL */
+
+ regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN |STM32_PLLCFG_PLLP |
+ RCC_PLLCFG_PLLSRC_HSE | STM32_PLLCFG_PPQ);
+ putreg32(regval, STM32_RCC_PLLCFG);
+
+ /* Enable the main PLL */
+
+ regval = getreg32(STM32_RCC_CR);
+ regval |= RCC_CR_PLLON;
+ putreg32(regval, STM32_RCC_CR);
+
+ /* Wait until the PLL is ready */
+
+ while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
+
+ /* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */
+
+ regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);
+ putreg32(regval, STM32_FLASH_ACR);
+
+ /* Select the main PLL as system clock source */
+
+ regval = getreg32(STM32_RCC_CFGR);
+ regval &= ~RCC_CFGR_SW_MASK;
+ regval |= RCC_CFGR_SW_PLL;
+ putreg32(regval, STM32_RCC_CFGR);
+
+ /* Wait until the PLL source is used as the system clock source */
+
+ while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL);
+ }
}
#endif
diff --git a/configs/stm3240g-eval/README.txt b/configs/stm3240g-eval/README.txt
index 0916ad028665ae28d8e8455712ea93b863ad9de9..3062c5fd98660857220e582fab514c3b94050fd4 100755
--- a/configs/stm3240g-eval/README.txt
+++ b/configs/stm3240g-eval/README.txt
@@ -287,7 +287,6 @@ STM3240G-EVAL-specific Configuration Options
CONFIG_STM32_I2C3
CONFIG_STM32_CAN1
CONFIG_STM32_CAN2
- CONFIG_STM32_PWR
CONFIG_STM32_DAC
APB2
diff --git a/configs/stm3240g-eval/include/board.h b/configs/stm3240g-eval/include/board.h
index e3825551fd0c75d7430f460b4ce1dec436660b87..5ebc54bb7f694f158d018df7e0d33e92364f1827 100755
--- a/configs/stm3240g-eval/include/board.h
+++ b/configs/stm3240g-eval/include/board.h
@@ -54,48 +54,90 @@
************************************************************************************/
/* Clocking *************************************************************************/
-#warning "Revisit -- this is from the STM3210E-EVAL"
-
-/* On-board crystal frequency is 8MHz (HSE) */
-
-#define STM32_BOARD_XTAL 8000000ul
+/* Four clock sources are available on STM3240G-EVAL evaluation board for
+ * STM32F407IGH6 and RTC embedded:
+ *
+ * X1, 25 MHz crystal for ethernet PHY with socket. It can be removed when clock is
+ * provided by MCO pin of the MCU
+ * X2, 26 MHz crystal for USB OTG HS PHY
+ * X3, 32 kHz crystal for embedded RTC
+ * X4, 25 MHz crystal with socket for STM32F407IGH6 microcontroller (It can be removed
+ * from socket when internal RC clock is used.)
+ *
+ * This is the "standard" configuration as set up by arch/arm/src/stm32f40xx_rcc.c:
+ * System Clock source : PLL (HSE)
+ * SYSCLK(Hz) : 168000000 Determined by PLL configuration
+ * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE)
+ * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE)
+ * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1)
+ * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2)
+ * HSE Frequency(Hz) : 25000000 (STM32_BOARD_XTAL)
+ * PLLM : 25 (STM32_PLLCFG_PLLM)
+ * PLLN : 336 (STM32_PLLCFG_PLLN)
+ * PLLP : 2 (STM32_PLLCFG_PLLP)
+ * PLLQ : 7 (STM32_PLLCFG_PPQ)
+ * Main regulator output voltage : Scale1 mode Needed for high speed SYSCLK
+ * Flash Latency(WS) : 5
+ * Prefetch Buffer : OFF
+ * Instruction cache : ON
+ * Data cache : ON
+ * Require 48MHz for USB OTG FS, : Enabled
+ * SDIO and RNG clock
+ */
-/* PLL source is HSE/1, PLL multipler is 9: PLL frequency is 8MHz (XTAL) x 9 = 72MHz */
+/* HSI - 16 MHz RC factory-trimmed
+ * LSI - 32 KHz RC
+ * HSE - On-board crystal frequency is 25MHz
+ * LSE - 32.768 kHz
+ */
-#define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC
-#define STM32_CFGR_PLLXTPRE 0
-#define STM32_CFGR_PLLMUL RCC_CFGR_PLLMUL_CLKx9
-#define STM32_PLL_FREQUENCY (9*STM32_BOARD_XTAL)
+#define STM32_BOARD_XTAL 25000000ul
-/* Use the PLL and set the SYSCLK source to be the PLL */
+#define STM32_HSI_FREQUENCY 16000000ul
+#define STM32_LSI_FREQUENCY 32000
+#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
+#define STM32_LSE_FREQUENCY 32768
-#define STM32_SYSCLK_SW RCC_CFGR_SW_PLL
-#define STM32_SYSCLK_SWS RCC_CFGR_SWS_PLL
-#define STM32_SYSCLK_FREQUENCY STM32_PLL_FREQUENCY
+/* Main PLL Configuration.
+ *
+ * PLL source is HSE
+ * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN
+ * = (25,000,000 / 25) * 336
+ * = 336,000,000
+ * SYSCLK = PLL_VCO / PLLP
+ * = 336,000,000 / 2 = 168,000,000
+ * USB OTG FS, SDIO and RNG Clock
+ * = PLL_VCO / PLLQ
+ * = 48,000,000
+ */
-/* AHB clock (HCLK) is SYSCLK (72MHz) */
+#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(25)
+#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(336)
+#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2
+#define STM32_PLLCFG_PPQ RCC_PLLCFG_PLLQ(7)
-#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK
-#define STM32_HCLK_FREQUENCY STM32_PLL_FREQUENCY
-#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
+#define STM32_SYSCLK_FREQUENCY 168000000ul
-/* APB2 clock (PCLK2) is HCLK (72MHz) */
+/* AHB clock (HCLK) is SYSCLK (168MHz) */
-#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLK
-#define STM32_PCLK2_FREQUENCY STM32_HCLK_FREQUENCY
+#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
+#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
+#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */
-/* APB1 clock (PCLK1) is HCLK/2 (36MHz) */
+/* APB2 clock (PCLK2) is HCLK/2 (84MHz) */
-#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd2
-#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/2)
+#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE1_HCLKd2 /* PCLK2 = HCLK / 2 */
+#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2)
-/* USB divider -- Divide PLL clock by 1.5 */
+/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */
-#define STM32_CFGR_USBPRE 0
+#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE2_HCLKd4 /* PCLK1 = HCLK / 4 */
+#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
* otherwise frequency is 2xAPBx.
- * Note: TIM1,8 are on APB2, others on APB1 */
+ * Note: TIM1,8 are on APB2, others on APB1
+ */
#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY
#define STM32_TIM27_FREQUENCY STM32_HCLK_FREQUENCY
diff --git a/configs/stm3240g-eval/ostest/defconfig b/configs/stm3240g-eval/ostest/defconfig
index 80a4ad45b05046c1f6327e7c570938c3c3a76613..a796b77d1b1440fd84ddaedb03889a3cfc557f8c 100755
--- a/configs/stm3240g-eval/ostest/defconfig
+++ b/configs/stm3240g-eval/ostest/defconfig
@@ -157,7 +157,6 @@ CONFIG_STM32_I2C2=n
CONFIG_STM32_I2C3=n
CONFIG_STM32_CAN1=n
CONFIG_STM32_CAN2=n
-CONFIG_STM32_PWR=n
CONFIG_STM32_DAC=n
# APB2:
CONFIG_STM32_TIM1=n
@@ -169,7 +168,7 @@ CONFIG_STM32_ADC2=n
CONFIG_STM32_ADC3=n
CONFIG_STM32_SDIO=n
CONFIG_STM32_SPI1=n
-CONFIG_STM32_SYSCFG=n
+CONFIG_STM32_SYSCFG=y
CONFIG_STM32_TIM9=n
CONFIG_STM32_TIM10=n
CONFIG_STM32_TIM11=n