diff --git a/arch/sh/include/limits.h b/arch/sh/include/limits.h
index 16e63f55106eebb2f5208971378c2998bf8504f1..18860b96ee9c848ea25491ee7a2cf06772fdf6e1 100644
--- a/arch/sh/include/limits.h
+++ b/arch/sh/include/limits.h
@@ -1,7 +1,7 @@
/****************************************************************************
* arch/sh/include/limits.h
*
- * Copyright (C) 2008 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2008, 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without
@@ -40,36 +40,10 @@
* Included Files
****************************************************************************/
+#include <arch/chip/limits.h>
+
/****************************************************************************
* Definitions
****************************************************************************/
-#define CHAR_BIT 8
-#define SCHAR_MIN 0x80
-#define SCHAR_MAX 0x7f
-#define UCHAR_MAX 0xff
-
-/* These could be different on machines where char is unsigned */
-
-#define CHAR_MIN SCHAR_MIN
-#define CHAR_MAX SCHAR_MAX
-
-#define SHRT_MIN 0x8000
-#define SHRT_MAX 0x7fff
-#define USHRT_MAX 0xffff
-
-#define INT_MIN 0x80000000
-#define INT_MAX 0x7fffffff
-#define UINT_MAX 0xffffffff
-
-/* These change on 32-bit and 64-bit platforms */
-
-#define LONG_MAX 0x80000000
-#define LONG_MIN 0x7fffffff
-#define ULONG_MAX 0xffffffff
-
-#define LLONG_MAX 0x8000000000000000
-#define LLONG_MIN 0x7fffffffffffffff
-#define ULLONG_MAX 0xffffffffffffffff
-
#endif /* __ARCH_SH_INCLUDE_LIMITS_H */
diff --git a/arch/sh/include/m16c/irq.h b/arch/sh/include/m16c/irq.h
index 64ec0725fa8a04e3da026e9017aff1f9f6150328..30ffaf87bc0c34fe4afe6b8327aafa28d0c8c42f 100644
--- a/arch/sh/include/m16c/irq.h
+++ b/arch/sh/include/m16c/irq.h
@@ -64,13 +64,11 @@
# define M16C_WDOG_IRQ 5 /* ffff0: Watchdog timer */
# define M16C_DBC_IRQ 6 /* ffff4: DBC */
# define M16C_NMI_IRQ 7 /* ffff8: NMI */
-# define M16C_RESET_IRQ 8 /* ffffc: Reset */
-# define _LAST_FIXED 8
+# define _LAST_FIXED 7
#else
# define M16C_WDOG_IRQ 4 /* ffff0: Watchdog timer */
# define M16C_NMI_IRQ 5 /* ffff8: NMI */
-# define M16C_RESET_IRQ 6 /* ffffc: Reset */
-# define _LAST_FIXED 6
+# define _LAST_FIXED 5
#endif
/* Variable vector table (fixed at address 0xffd00) */
@@ -80,7 +78,8 @@
# define M16C_SWINT0_IRQ M16C_BRK_IRQ /* S/W interrupt 0 */
# define M16C_INT3_IRQ (_LAST_FIXED+2) /* ffd10: INT3 */
# define M16C_SWINT4_IRQ M16C_INT3_IRQ /* S/W interrupt 4 */
-# define M16C_SWINT5_IRQ (_LAST_FIXED+3) /* ffd14: Reserved / S/W interrupt 5 */
+# define M16C_CTXSV_SWINT (_LAST_FIXED+3) /* ffd14: Reserved -- used by NuttX */
+# define M16C_SWINT5_IRQ M16C_CTXSV_SWINT /* S/W interrupt 5 */
# define M16C_SWINT6_IRQ (_LAST_FIXED+4) /* ffd18: Reserved / S/W interrupt 6 */
# define M16C_SWINT7_IRQ (_LAST_FIXED+5) /* ffd1c: Reserved / S/W interrupt 7 */
# define M16C_INT5_IRQ (_LAST_FIXED+6) /* ffd20: INT5 */
@@ -130,7 +129,8 @@
# define M16C_INT1_IRQ (_LAST_FIXED+28) /* ffd78: INT1 */
# define M16C_SWINT30_IRQ M16C_INT1_IRQ /* S/W interrupt 30 */
# define M16C_SWINT31_IRQ (_LAST_FIXED+29) /* ffd7c: Reserved / S/W interrupt 31 */
-# define M16C_SWINT32_IRQ (_LAST_FIXED+30) /* ffd80: S/W interrupt 32 */
+# define M16C_CTXRSTR_SWINT (_LAST_FIXED+30) /* ffd80: Used by NuttX */
+# define M16C_SWINT32IRQ M16C_CTXRSTR_SWINT /* S/W interrupt 32 */
# define M16C_SWINT33_IRQ (_LAST_FIXED+31) /* ffd84: S/W interrupt 33 */
# define M16C_SWINT34_IRQ (_LAST_FIXED+32) /* ffd88: S/W interrupt 34 */
# define M16C_SWINT35_IRQ (_LAST_FIXED+33) /* ffd8c: S/W interrupt 35 */
@@ -167,31 +167,33 @@
#else
# define M16C_BRK_IRQ (_LAST_FIXED+1) /* ffd00: BRK instruction */
# define M16C_INT3_IRQ (_LAST_FIXED+2) /* ffd10: INT3 */
-# define M16C_INT5_IRQ (_LAST_FIXED+3) /* ffd20: INT5 */
-# define M16C_INT4_IRQ (_LAST_FIXED+4) /* ffd24: INT4 */
-# define M16C_UART2BCD_IRQ (_LAST_FIXED+5) /* ffd28: UART2 bus collision detection */
-# define M16C_DMA0_IRQ (_LAST_FIXED+6) /* ffd2c: DMA0 */
-# define M16C_DMA1_IRQ (_LAST_FIXED+7) /* ffd30: DMA1 */
-# define M16C_KEYINP_IRQ (_LAST_FIXED+8) /* ffd34: Key input interrupt */
-# define M16C_ADC_IRQ (_LAST_FIXED+9) /* ffd38: A-D */
-# define M16C_UARTXNAK_IRQ (_LAST_FIXED+10) /* ffd3c UART2 transmit/NACK2 */
-# define M16C_UARTRACK_IRQ (_LAST_FIXED+11) /* ffd40: UART2 receive/ACK2 */
-# define M16C_UART0XMT_IRQ (_LAST_FIXED+12) /* ffd44: UART0 transmit */
-# define M16C_UART0RCV_IRQ (_LAST_FIXED+13) /* ffd48: UART0 receive */
-# define M16C_UART1XMT_IRQ (_LAST_FIXED+14) /* ffd4c: UART1 transmit */
-# define M16C_UART1RCV_IRQ (_LAST_FIXED+15) /* ffd50: UART1 receive */
-# define M16C_TMRA0_IRQ (_LAST_FIXED+16) /* ffd54: Timer A0 */
-# define M16C_TMRA1_IRQ (_LAST_FIXED+17) /* ffd58: Timer A1 */
-# define M16C_TMRA2_IRQ (_LAST_FIXED+18) /* ffd5c: Timer A2 */
-# define M16C_TMRA3_IRQ (_LAST_FIXED+19) /* ffd60: Timer A3 */
-# define M16C_TMRA4_IRQ (_LAST_FIXED+20) /* ffd64: Timer A4 */
-# define M16C_TMRB0_IRQ (_LAST_FIXED+21) /* ffd68: Timer B0 */
-# define M16C_TMRB1_IRQ (_LAST_FIXED+22) /* ffd6c: Timer B1 */
-# define M16C_TMRB2_IRQ (_LAST_FIXED+23) /* ffd70: Timer B2 */
-# define M16C_INT0_IRQ (_LAST_FIXED+24) /* ffd74: INT0 */
-# define M16C_INT1_IRQ (_LAST_FIXED+25) /* ffd78: INT1 */
-
-# define NR_IRQS (_LAST_FIXED+26) /* Total number of supported IRQs */
+# define M16C_CTXSV_SWINT (_LAST_FIXED+3) /* ffd14: Reserved -- SWINT5 used by NuttX */
+# define M16C_INT5_IRQ (_LAST_FIXED+5) /* ffd20: INT5 */
+# define M16C_INT4_IRQ (_LAST_FIXED+6) /* ffd24: INT4 */
+# define M16C_UART2BCD_IRQ (_LAST_FIXED+7) /* ffd28: UART2 bus collision detection */
+# define M16C_DMA0_IRQ (_LAST_FIXED+8) /* ffd2c: DMA0 */
+# define M16C_DMA1_IRQ (_LAST_FIXED+9) /* ffd30: DMA1 */
+# define M16C_KEYINP_IRQ (_LAST_FIXED+10) /* ffd34: Key input interrupt */
+# define M16C_ADC_IRQ (_LAST_FIXED+11) /* ffd38: A-D */
+# define M16C_UARTXNAK_IRQ (_LAST_FIXED+12) /* ffd3c UART2 transmit/NACK2 */
+# define M16C_UARTRACK_IRQ (_LAST_FIXED+13) /* ffd40: UART2 receive/ACK2 */
+# define M16C_UART0XMT_IRQ (_LAST_FIXED+14) /* ffd44: UART0 transmit */
+# define M16C_UART0RCV_IRQ (_LAST_FIXED+15) /* ffd48: UART0 receive */
+# define M16C_UART1XMT_IRQ (_LAST_FIXED+16) /* ffd4c: UART1 transmit */
+# define M16C_UART1RCV_IRQ (_LAST_FIXED+17) /* ffd50: UART1 receive */
+# define M16C_TMRA0_IRQ (_LAST_FIXED+18) /* ffd54: Timer A0 */
+# define M16C_TMRA1_IRQ (_LAST_FIXED+19) /* ffd58: Timer A1 */
+# define M16C_TMRA2_IRQ (_LAST_FIXED+20) /* ffd5c: Timer A2 */
+# define M16C_TMRA3_IRQ (_LAST_FIXED+21) /* ffd60: Timer A3 */
+# define M16C_TMRA4_IRQ (_LAST_FIXED+22) /* ffd64: Timer A4 */
+# define M16C_TMRB0_IRQ (_LAST_FIXED+23) /* ffd68: Timer B0 */
+# define M16C_TMRB1_IRQ (_LAST_FIXED+24) /* ffd6c: Timer B1 */
+# define M16C_TMRB2_IRQ (_LAST_FIXED+25) /* ffd70: Timer B2 */
+# define M16C_INT0_IRQ (_LAST_FIXED+26) /* ffd74: INT0 */
+# define M16C_INT1_IRQ (_LAST_FIXED+27) /* ffd78: INT1 */
+# define M16C_CTXRSTR_SWINT (_LAST_FIXED+4) /* ffd80: S/W interrupt 32, used by NuttX */
+
+# define NR_IRQS (_LAST_FIXED+28) /* Total number of supported IRQs */
#endif
#define M16C_SYSTIMER_IRQ M16C_TMRA0_IRQ
@@ -199,7 +201,7 @@
/* IRQ Stack Frame Format. The M16C has a push down stack. The CPU performs
* the following actions when an interrupt is taken:
*
- * - Save FLG regsiter
+ * - Save FLG register
* - Clear I, D, and U flags in FLG register
* - Builds stack frame like:
*
@@ -212,20 +214,20 @@
* - Vectors to interrupt handler
*/
-#define REG_PC20 0 /* 20-bit PC [0]:bits 16-19 [1]:bits 8-15 [2]: bits 0-7 */
-#define REG_FLGPCHI 3 /* 8-bit FLG (bits 12-14) PC (bits 16-19) as would be
+#define REG_FLGPCHI 0 /* 8-bit FLG (bits 12-14) + PC (bits 16-19) as would be
* presented by an interrupt */
-#define REG_FLG 4 /* 8-bit FLG register (bits 0-7) */
-#define REG_PC16 5 /* 16-bit PC [0]:bits8-15 [1]:bits 0-7 */
-#define REG_FB 7 /* 16-bit FB register */
-#define REG_SB 9 /* 16-bit SB register */
-#define REG_A1 11 /* 16-bit A1 register */
-#define REG_R3 13 /* 16-bit R3 register */
-#define REG_R2 15 /* 16-bit R2 register */
-#define REG_R1 17 /* 16-bit R1 register */
-#define REG_R0 19 /* 16-bit R0 register */
-
-#define XCPTCONTEXT_SIZE 21
+#define REG_FLG 1 /* 8-bit FLG register (bits 0-7) */
+#define REG_PC16 2 /* 16-bit PC [0]:bits8-15 [1]:bits 0-7 */
+#define REG_FB 4 /* 16-bit FB register */
+#define REG_SB 6 /* 16-bit SB register */
+#define REG_A1 8 /* 16-bit A1 register */
+#define REG_R3 10 /* 16-bit R3 register */
+#define REG_R2 12 /* 16-bit R2 register */
+#define REG_R1 14 /* 16-bit R1 register */
+#define REG_R0 16 /* 16-bit R0 register */
+#define REG_SP 18 /* 16-bit user stack pointer */
+
+#define XCPTCONTEXT_SIZE 20
/************************************************************************************
* Public Types
@@ -240,7 +242,7 @@ struct xcptcontext
*/
#ifndef CONFIG_DISABLE_SIGNALS
- FAR void *sigdeliver; /* Actual type is sig_deliver_t */
+ void *sigdeliver; /* Actual type is sig_deliver_t */
/* These are saved copies of LR and SR used during signal processing. */
diff --git a/arch/sh/src/m16c/Make.defs b/arch/sh/src/m16c/Make.defs
index 39da7460b3b57776ea872a42ced161ffc475515b..fe28a2dfda874ed077d0d8f8eb9a5fc2344e85a3 100644
--- a/arch/sh/src/m16c/Make.defs
+++ b/arch/sh/src/m16c/Make.defs
@@ -42,7 +42,6 @@ CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c \
up_releasepending.c up_releasestack.c up_reprioritizertr.c \
up_udelay.c up_unblocktask.c up_usestack.c
-#CHIP_ASRCS = m16c_vectors.S m16c_saveusercontext.S m16c_restorecontext.S
CHIP_ASRCS = m16c_vectors.S
#CHIP_CSRCS = m16c_initialstate.c m16c_copystate.c m16c_lowputc.c m16c_irq.c \
# m16c_timerisr.c m16c_serial.c
diff --git a/arch/sh/src/m16c/m16c_copystate.c b/arch/sh/src/m16c/m16c_copystate.c
index e66637ab990c777e25d4f11306abb6039ae519aa..c74b576752cea116fc727abefdfaabf86b17c0ba 100644
--- a/arch/sh/src/m16c/m16c_copystate.c
+++ b/arch/sh/src/m16c/m16c_copystate.c
@@ -40,6 +40,7 @@
#include <nuttx/config.h>
#include <sys/types.h>
+#include <string.h>
#include "os_internal.h"
#include "up_internal.h"
diff --git a/arch/sh/src/m16c/m16c_head.S b/arch/sh/src/m16c/m16c_head.S
index 52b9fdb7f26693e47070aafc37902e216070b69a..919dcf2d2e6c32b7d3e5220faab45ef3e2e35f75 100644
--- a/arch/sh/src/m16c/m16c_head.S
+++ b/arch/sh/src/m16c/m16c_head.S
@@ -145,7 +145,7 @@ __start:
/* Set the interrupt and user stack pointers */
mov.w #_enbss, R0
- ldc R0, isp /* Set interrupt thread stack pointer to the end of BSS */
+ ldc R0, isp /* Set the interrupt stack pointer to the end of BSS */
add.w #CONFIG_IDLETHREAD_STACKSIZE, R0
fset U /* Set bit 7 (U) to select the user stack pointer */
ldc R0, sp /* Set the user stack pointer */
@@ -190,8 +190,8 @@ __start:
/* Initialize near .data sections (.rodata is not moved) */
- mov.w _g_enronly, a0 /* a0: Low 16 bits of source */
- mov.b _g_enronly+2, r1h /* r1h: 4 order bits of source */
+ mov.w _g_enronly, a0 /* a0: Low 16 bits of source address */
+ mov.b _g_enronly+2, r1h /* 4 MS of 20-bit source address */
mov.w _g_sndata, a1 /* a1: start of near .data */
mov.w _g_endata, r3 /* r3: end of near .data */
sub.w a1, r3 /* r3: size of near .data */
@@ -212,4 +212,5 @@ __start:
_os_exit:
jmp.s _os_exit
+ .size __start, .-__start
.end
diff --git a/arch/sh/src/m16c/m16c_initialstate.c b/arch/sh/src/m16c/m16c_initialstate.c
index 10dbd2d880a05a8e402342e86026c23b4b5e1a14..e4c5567885842db4e8d0c891689805c55765ccbe 100644
--- a/arch/sh/src/m16c/m16c_initialstate.c
+++ b/arch/sh/src/m16c/m16c_initialstate.c
@@ -48,7 +48,7 @@
* Preprocessor Definitions
****************************************************************************/
-#define M16C_DEFAULT_IPL 0 /* Global M16C Interrupt priority level */
+#define M16C_DEFAULT_IPL 0 /* Default M16C Interrupt priority level */
/****************************************************************************
* Private Data
@@ -58,24 +58,6 @@
* Private Functions
****************************************************************************/
-/****************************************************************************
- * Name: up_getsr
- ****************************************************************************/
-
-static inline irqstate_t up_getsr(void)
-{
- irqstate_t flags;
-
- __asm__ __volatile__
- (
- "stc sr, %0\n\t"
- : "=&z" (flags)
- :
- : "memory"
- );
- return flags;
-}
-
/****************************************************************************
* Public Functions
****************************************************************************/
@@ -102,22 +84,26 @@ void up_initial_state(FAR _TCB *tcb)
memset(xcp, 0, sizeof(struct xcptcontext));
- /* Offset 0-2: 20-bit PC [0]:bits 16-19 [1]:bits 8-15 [2]: bits 0-7 */
-
- *regs++ = (uint32)tcb->start >> 16; /* Bits 16-19 of PC */
- *regs++ = (uint32)tcb->start >> 8; /* Bits 8-15 of PC */
- *regs++ = (uint32)tcb->start; /* Bits 0-7 of PC */
-
- /* Offset 3: FLG (bits 12-14) PC (bits 16-19) as would be present by an interrupt */
+ /* Offset 0: FLG (bits 12-14) PC (bits 16-19) as would be present by an interrupt */
*regs++ = ((M16C_DEFAULT_IPL << 4) | ((uint32)tcb->start >> 16));
- /* Offset 4: FLG (bits 0-7) */
+ /* Offset 1: FLG (bits 0-7) */
+#ifdef CONFIG_SUPPRESS_INTERRUPTS
+ *regs++ = M16C_FLG_U;
+#else
*regs++ = M16C_FLG_U | M16C_FLG_I;
+#endif
- /* Offset 5-6: 16-bit PC [0]:bits8-15 [1]:bits 0-7 */
+ /* Offset 2-3: 16-bit PC [0]:bits8-15 [1]:bits 0-7 */
*regs++ = (uint32)tcb->start >> 8; /* Bits 8-15 of PC */
*regs++ = (uint32)tcb->start; /* Bits 0-7 of PC */
+
+ /* Offset 18-20: User stack pointer */
+
+ regs = &xcp->regs[REG_SP];
+ *regs++ = (uint32)tcb->adj_stack_ptr >> 8; /* Bits 8-15 of SP */
+ *regs = (uint32)tcb->adj_stack_ptr; /* Bits 0-7 of SP */
}
diff --git a/arch/sh/src/m16c/m16c_vectors.S b/arch/sh/src/m16c/m16c_vectors.S
index 2aec1ab8d79dcd3545e9ffe36ee702e8bd22b32d..2ffa50154d9d46accb0e8eb414a21821e663865f 100644
--- a/arch/sh/src/m16c/m16c_vectors.S
+++ b/arch/sh/src/m16c/m16c_vectors.S
@@ -38,6 +38,7 @@
************************************************************************************/
#include <nuttx/config.h>
+#include <arch/irq.h>
#include "chip.h"
/************************************************************************************
@@ -48,6 +49,15 @@
* Macro Definitions
************************************************************************************/
+/* Select register bank 1, and pass the IRQ number to _m16c_commonvector */
+
+ .macro m16c_vector, label, irqno
+\label:
+ fset b
+ mov.w #\irqno, r1
+ jmp.w _m16c_commonvector
+ .endm
+
/* Special page vectors. This macro puts the jump address of
* functions defined as special page into the special page vector table.
* See example calls below and see the M16C Software Manual or NC30
@@ -72,142 +82,79 @@
/* Variable vector section */
.section varvects /* Variable vector table */
- .globl _m16c_unexpected_isr
- .globl _m16c_brk_isr
.long _m16c_brk_isr /* ffd00: BRK instruction */
.long 0xffffffff /* ffd04 */
.long 0xffffffff /* ffd08 */
.long 0xffffffff /* ffd0c */
- .globl _m16c_int3_isr
.long _m16c_int3_isr /* ffd10: INT3 */
+ .long _m16c_contextsave /* ffd14: Reserved -- SWINT5 used by NuttX */
#ifdef CONFIG_M16C_SWINTS
- .globl _m16c_swint5_isr
- .long _m16c_swint5_isr /* ffd14: S/W interrupt 5 */
- .globl _m16c_swint6_isr
- .long _m16c_swint6_isr /* ffd18: S/W interrupt 6 */
- .globl _m16c_swint7_isr
+ .long _m16c_swint6_isr /* ffd18: S/W interrupt 7 */
.long _m16c_swint7_isr /* ffd1c: S/W interrupt 7 */
#else
- .long _m16c_unexpected_isr /* ffd14: Reserved */
- .long _m16c_unexpected_isr /* ffd18: Reserved */
+ .long _m16c_unexpected_isr /* ffd1c: Reserved */
.long _m16c_unexpected_isr /* ffd1c: Reserved */
#endif
- .globl _m16c_int5_isr
.long _m16c_int5_isr /* ffd20: INT5 */
- .globl _m16c_int4_isr
.long _m16c_int4_isr /* ffd24: INT4 */
- .globl _m16c_uart2bcd_isr
.long _m16c_uart2bcd_isr /* ffd28: UART2 bus collision detection */
- .globl _m16c_dma0_isr
.long _m16c_dma0_isr /* ffd2c: DMA0 */
- .globl _m16c_dma1_isr
.long _m16c_dma1_isr /* ffd30: DMA1 */
- .globl _m16c_keyinp_isr
.long _m16c_keyinp_isr /* ffd34: Key input interrupt */
- .globl _m16c_adc_isr
.long _m16c_adc_isr /* ffd38: A-D */
- .globl _m16c_uart2xmitnack2_isr
.long _m16c_uart2xmitnack2_isr /* ffd3c UART2 transmit/NACK2 */
- .globl _m16c_uart2rcvack2_isr
.long _m16c_uart2rcvack2_isr /* ffd40: UART2 receive/ACK2 */
- .globl _m16c_uart0xmit_isr
.long _m16c_uart0xmit_isr /* ffd44: UART0 transmit */
- .globl _m16c_uart0rcv_isr
.long _m16c_uart0rcv_isr /* ffd48: UART0 receive */
- .globl _m16c_uart1xmit_isr
.long _m16c_uart1xmit_isr /* ffd4c: UART1 transmit */
- .globl _m16c_uart1rcv_isr
.long _m16c_uart1rcv_isr /* ffd50: UART1 receive */
- .globl _m16c_tmra0_isr
.long _m16c_tmra0_isr /* ffd54: Timer A0 */
- .globl _m16c_tmra1_isr
.long _m16c_tmra1_isr /* ffd58: Timer A1 */
- .globl _m16c_tmra2_isr
.long _m16c_tmra2_isr /* ffd5c: Timer A2 */
- .globl _m16c_tmra3_isr
.long _m16c_tmra3_isr /* ffd60: Timer A3 */
- .globl _m16c_tmra4_isr
.long _m16c_tmra4_isr /* ffd64: Timer A4 */
- .globl _m16c_tmrb0_isr
.long _m16c_tmrb0_isr /* ffd68: Timer B0 */
- .globl _m16c_tmrb1_isr
.long _m16c_tmrb1_isr /* ffd6c: Timer B1 */
- .globl _m16c_tmrb2_isr
.long _m16c_tmrb2_isr /* ffd70: Timer B2 */
- .globl _m16c_int0_isr
.long _m16c_int0_isr /* ffd74: INT0 */
- .globl _m16c_int1_isr
.long _m16c_int1_isr /* ffd78: INT1 */
#ifdef CONFIG_M16C_SWINTS
- .globl _m16c_swint31_isr
.long _m16c_swint31_isr /* ffd7c: S/W interrupt 31 */
- .globl _m16c_swint32_isr
- .long _m16c_swint32_isr /* ffd80: S/W interrupt 32 */
- .globl _m16c_swint33_isr
+ .long _m16c_contextrestore /* ffd80: S/W interrupt 32 by NuttX */
.long _m16c_swint33_isr /* ffd84: S/W interrupt 33 */
- .globl _m16c_swint34_isr
.long _m16c_swint34_isr /* ffd88: S/W interrupt 34 */
- .globl _m16c_swint35_isr
.long _m16c_swint35_isr /* ffd8c: S/W interrupt 35 */
- .globl _m16c_swint36_isr
.long _m16c_swint36_isr /* ffd90: S/W interrupt 36 */
- .globl _m16c_swint37_isr
.long _m16c_swint37_isr /* ffd94: S/W interrupt 37 */
- .globl _m16c_swint38_isr
.long _m16c_swint38_isr /* ffd98: S/W interrupt 38 */
- .globl _m16c_swint39_isr
.long _m16c_swint39_isr /* ffd9c: S/W interrupt 39 */
- .globl _m16c_swint40_isr
.long _m16c_swint40_isr /* ffda0: S/W interrupt 40 */
- .globl _m16c_swint41_isr
.long _m16c_swint41_isr /* ffda4: S/W interrupt 41 */
- .globl _m16c_swint42_isr
.long _m16c_swint42_isr /* ffda8: S/W interrupt 42 */
- .globl _m16c_swint43_isr
.long _m16c_swint43_isr /* ffdac: S/W interrupt 43 */
- .globl _m16c_swint44_isr
.long _m16c_swint44_isr /* ffdb0: S/W interrupt 44 */
- .globl _m16c_swint45_isr
.long _m16c_swint45_isr /* ffdb4: S/W interrupt 45 */
- .globl _m16c_swint46_isr
.long _m16c_swint46_isr /* ffdb8: S/W interrupt 46 */
- .globl _m16c_swint47_isr
.long _m16c_swint47_isr /* ffdbc: S/W interrupt 47 */
- .globl _m16c_swint48_isr
.long _m16c_swint48_isr /* ffdc0: S/W interrupt 48 */
- .globl _m16c_swint49_isr
.long _m16c_swint49_isr /* ffdc4: S/W interrupt 49 */
- .globl _m16c_swint50_isr
.long _m16c_swint50_isr /* ffdc8: S/W interrupt 50 */
- .globl _m16c_swint51_isr
.long _m16c_swint51_isr /* ffdcc: S/W interrupt 51 */
- .globl _m16c_swint52_isr
.long _m16c_swint52_isr /* ffdd0: S/W interrupt 52 */
- .globl _m16c_swint53_isr
.long _m16c_swint53_isr /* ffdd4: S/W interrupt 53 */
- .globl _m16c_swint54_isr
.long _m16c_swint54_isr /* ffdd8: S/W interrupt 54 */
- .globl _m16c_swint55_isr
.long _m16c_swint55_isr /* ffddc: S/W interrupt 55 */
- .globl _m16c_swint56_isr
.long _m16c_swint56_isr /* ffde0: S/W interrupt 56 */
- .globl _m16c_swint57_isr
.long _m16c_swint57_isr /* ffde4: S/W interrupt 57 */
- .globl _m16c_swint58_isr
.long _m16c_swint58_isr /* ffde8: S/W interrupt 58 */
- .globl _m16c_swint59_isr
.long _m16c_swint59_isr /* ffdec: S/W interrupt 59 */
- .globl _m16c_swint60_isr
.long _m16c_swint60_isr /* ffdf0: S/W interrupt 60 */
- .globl _m16c_swint61_isr
.long _m16c_swint61_isr /* ffdf4: S/W interrupt 61 */
- .globl _m16c_swint62_isr
.long _m16c_swint62_isr /* ffdf8: S/W interrupt 62 */
- .globl _m16c_swint63_isr
.long _m16c_swint63_isr /* ffdfc: S/W interrupt 63 */
#else
.long _m16c_unexpected_isr /* ffd7c: Reserved */
- .long _m16c_unexpected_isr /* ffd80: Not supported */
+ .long _m16c_contextrestore /* ffd80: S/W interrupt 32 by NuttX */
.long _m16c_unexpected_isr /* ffd84: Not supported */
.long _m16c_unexpected_isr /* ffd88: Not supported */
.long _m16c_unexpected_isr /* ffd8c: Not supported */
@@ -248,31 +195,23 @@
* is not currently used.
*/
.section specpg /* Special page table */
-
+ /* Nothing */
.section fixvects /* Fixed vector table */
- .globl _m16c_undefinst_irq
.long _m16c_undefinst_irq /* fffdc: Undefined instruction */
- .globl _m16c_overflow_irq
.long _m16c_overflow_irq /* fffe0: Overflow */
- .globl _m16c_brkinst_irq
.long _m16c_brkinst_irq /* fffe4: BRK instruction */
- .globl _m16c_addrmatch_irq
.long _m16c_addrmatch_irq /* fffe8: Address match */
#ifdef CONFIG_M16C_DEBUGGER
- .globl _m16c_sstep_irq
.long _m16c_sstep_irq /* fffec: Single step */
#else
.long _m16c_unexpected_isr /* fffec: Not supported */
#endif
- .globl _m16c_wdog_irq
.long _m16c_wdog_irq /* ffff0: Watchdog timer */
#ifdef CONFIG_M16C_DEBUGGER
- .globl _m16c_dbc_irq
.long _m16c_dbc_irq /* ffff4: DBC */
#else
.long _m16c_unexpected_isr /* ffff4: Not supported */
#endif
- .globl _m16c_nmi_irq
.long _m16c_nmi_irq /* ffff8: NMI */
.long __start /* ffffc: Reset */
@@ -280,15 +219,15 @@
* Code
************************************************************************************/
/************************************************************************************
- * Name:
+ * Name: m16c_*isr
*
* Description:
- * The M16C has a push down stack. The CPU performs the following actions when an
+ * Handler interrupt events. The CPU performs the following actions when an
* interrupt is taken:
*
- * - Save FLG regsiter
+ * - Save FLG register
* - Clear I, D, and U flags in FLG register
- * - Builds stack frame like:
+ * - Builds stack frame like (on the push-down, interrupt stack):
*
* sp -> PC bits 0-7
* sp+1 -> PC bits 8-15
@@ -301,4 +240,273 @@
************************************************************************************/
.text
+/* The unexpected interrupt vector */
+
+ m16c_vector _m16c_unexpected_isr, NR_IRQS
+
+ /* Variable vectors */
+
+ m16c_vector _m16c_brk_isr, M16C_BRK_IRQ
+ m16c_vector _m16c_int3_isr, M16C_INT3_IRQ
+ m16c_vector _m16c_int5_isr, M16C_INT5_IRQ
+ m16c_vector _m16c_int4_isr, M16C_INT4_IRQ
+ m16c_vector _m16c_uart2bcd_isr, M16C_UART2BCD_IRQ
+ m16c_vector _m16c_dma0_isr, M16C_DMA0_IRQ
+ m16c_vector _m16c_dma1_isr, M16C_DMA1_IRQ
+ m16c_vector _m16c_keyinp_isr, M16C_KEYINP_IRQ
+ m16c_vector _m16c_adc_isr, M16C_ADC_IRQ
+ m16c_vector _m16c_uart2xmitnack2_isr, M16C_UARTXNAK_IRQ
+ m16c_vector _m16c_uart2rcvack2_isr, M16C_UARTRACK_IRQ
+ m16c_vector _m16c_uart0xmit_isr, M16C_UART0XMT_IRQ
+ m16c_vector _m16c_uart0rcv_isr, M16C_UART0RCV_IRQ
+ m16c_vector _m16c_uart1xmit_isr, M16C_UART1XMT_IRQ
+ m16c_vector _m16c_uart1rcv_isr, M16C_UART1RCV_IRQ
+ m16c_vector _m16c_tmra0_isr, M16C_TMRA0_IRQ
+ m16c_vector _m16c_tmra1_isr, M16C_TMRA1_IRQ
+ m16c_vector _m16c_tmra2_isr, M16C_TMRA2_IRQ
+ m16c_vector _m16c_tmra3_isr, M16C_TMRA3_IRQ
+ m16c_vector _m16c_tmra4_isr, M16C_TMRA4_IRQ
+ m16c_vector _m16c_tmrb0_isr, M16C_TMRB0_IRQ
+ m16c_vector _m16c_tmrb1_isr, M16C_TMRB1_IRQ
+ m16c_vector _m16c_tmrb2_isr, M16C_TMRB2_IRQ
+ m16c_vector _m16c_int0_isr, M16C_INT0_IRQ
+ m16c_vector _m16c_int1_isr, M16C_INT1_IRQ
+
+#ifdef CONFIG_M16C_SWINTS
+ m16c_vector _m16c_swint5_isr, M16C_SWINT5_IRQ
+ m16c_vector _m16c_swint6_isr, M16C_SWINT6_IRQ
+ m16c_vector _m16c_swint7_isr, M16C_SWINT7_IRQ
+ m16c_vector _m16c_swint31_isr, M16C_SWINT31_IRQ
+ m16c_vector _m16c_swint32_isr, M16C_SWINT32_IRQ
+ m16c_vector _m16c_swint33_isr, M16C_SWINT33_IRQ
+ m16c_vector _m16c_swint34_isr, M16C_SWINT34_IRQ
+ m16c_vector _m16c_swint35_isr, M16C_SWINT35_IRQ
+ m16c_vector _m16c_swint36_isr, M16C_SWINT36_IRQ
+ m16c_vector _m16c_swint37_isr, M16C_SWINT37_IRQ
+ m16c_vector _m16c_swint38_isr, M16C_SWINT38_IRQ
+ m16c_vector _m16c_swint39_isr, M16C_SWINT39_IRQ
+ m16c_vector _m16c_swint40_isr, M16C_SWINT40_IRQ
+ m16c_vector _m16c_swint41_isr, M16C_SWINT41_IRQ
+ m16c_vector _m16c_swint42_isr, M16C_SWINT42_IRQ
+ m16c_vector _m16c_swint43_isr, M16C_SWINT43_IRQ
+ m16c_vector _m16c_swint44_isr, M16C_SWINT44_IRQ
+ m16c_vector _m16c_swint45_isr, M16C_SWINT45_IRQ
+ m16c_vector _m16c_swint46_isr, M16C_SWINT46_IRQ
+ m16c_vector _m16c_swint47_isr, M16C_SWINT47_IRQ
+ m16c_vector _m16c_swint48_isr, M16C_SWINT48_IRQ
+ m16c_vector _m16c_swint49_isr, M16C_SWINT49_IRQ
+ m16c_vector _m16c_swint50_isr, M16C_SWINT50_IRQ
+ m16c_vector _m16c_swint51_isr, M16C_SWINT51_IRQ
+ m16c_vector _m16c_swint52_isr, M16C_SWINT52_IRQ
+ m16c_vector _m16c_swint53_isr, M16C_SWINT53_IRQ
+ m16c_vector _m16c_swint54_isr, M16C_SWINT54_IRQ
+ m16c_vector _m16c_swint55_isr, M16C_SWINT55_IRQ
+ m16c_vector _m16c_swint56_isr, M16C_SWINT56_IRQ
+ m16c_vector _m16c_swint57_isr, M16C_SWINT57_IRQ
+ m16c_vector _m16c_swint58_isr, M16C_SWINT58_IRQ
+ m16c_vector _m16c_swint59_isr, M16C_SWINT59_IRQ
+ m16c_vector _m16c_swint60_isr, M16C_SWINT60_IRQ
+ m16c_vector _m16c_swint61_isr, M16C_SWINT61_IRQ
+ m16c_vector _m16c_swint62_isr, M16C_SWINT62_IRQ
+ m16c_vector _m16c_swint63_isr, M16C_SWINT63_IRQ
+#endif
+
+/* Fixed vectors */
+
+ m16c_vector _m16c_undefinst_irq, M16C_UNDEFINST_IRQ
+ m16c_vector _m16c_overflow_irq, M16C_OVERFLOW_IRQ
+ m16c_vector _m16c_brkinst_irq, M16C_BRK_IRQ
+ m16c_vector _m16c_addrmatch_irq, M16C_ADDRMATCH_IRQ
+ m16c_vector _m16c_wdog_irq, M16C_WDOG_IRQ
+ m16c_vector _m16c_nmi_irq, M16C_NMI_IRQ
+#ifdef CONFIG_M16C_DEBUGGER
+ m16c_vector _m16c_sstep_irq, M16C_SSTEP_IRQ
+ m16c_vector _m16c_dbc_irq, M16C_DBC_IRQ
+#endif
+
+/* At this point, the stack remains as it was on interrupt. The interrupt
+ * stack is selected, register bank 1 is selected and r1 holds the IRQ
+ * number.
+ */
+
+_m16c_commonvector:
+
+/* At this point, the interrupt stack has 4 bytes of info on it. */
+
+/* Save all registers on the interrupt stack */
+
+ fclr b /* Switch back to Bank 0 */
+ pushm fb,sb,a1,a0,r3,r2,r1,r0 /* Save on interrupt stack */
+ fset b /* Bank to bank 1 */
+
+/* Save the user stack pointer on the interrupt stack */
+
+ fset u /* Switch to User stack */
+ stc sp, r0 /* R0 = user stack pointer */
+ fclr u /* Back to interrupt stack */
+ push.w r0 /* Save user sp on isp */
+
+/* Then call _up_doirq with r1=IRQ number, r2=address of context info. At this
+ * point, the interrupt stack holds the address of the last byte of the context
+ * info array
+ */
+
+ stc isp, r2 /* R2 = address of base of context info */
+ jsr.a _up_doirq
+
+/* Upon return, r0 will hold address of the base of the new context info structure
+ * use for return. Most of the time this will be the same as the address passed to
+ * to _up_doirg above, but will differ if a context switch occurs during interrupt
+ * processing.
+ *
+ * Of the ISP to the end of the context array:
+ */
+
+ ldc r0, isp /* ISP = address of base of new context info */
+
+ /* Restore the user stack pointer */
+
+ pop.w r0 /* R0 = saved user stack pointer */
+ fset u /* Switch to User stack */
+ ldc r0, sp /* Restore the user stack pointer */
+ fclr u /* Back to interrupt stack */
+
+/* Recover all registers and return */
+
+ fclr b /* Switch back to Bank 0 */
+ popm fb,sb,a1,a0,r3,r2,r1,r0 /* Recover registers */
+ reit /* Return from interrupt */
+
+/************************************************************************************
+ * Name: int up_saveusercontext(uint32 *regs)
+ *
+ * Description:
+ * Save the context of the calling function at the point of the return from the
+ * call. This basically a setjmp.
+ *
+ * Input Parameters:
+ * R1 = Address of register save array
+ *
+ * Returned Value:
+ * R0 = 0 on normal call; 1 on context switch
+ *
+ ************************************************************************************/
+
+ .globl _up_saveusercontext
+ .type _up_saveusercontext, #function
+
+_up_saveusercontext:
+ int #5 /* Execute S/W interrupt 5 */
+ rts /* Then return with the correct value in r0 */
+
+/* This the logic executes in response to S/W interrupt 5. The 'int 5' instruction
+ * will cause the following actions:
+ *
+ * - Save FLG register
+ * - Clear I, D, and U flags in FLG register
+ * - Builds stack frame like (on the push-down, interrupt stack):
+ *
+ * sp -> PC bits 0-7
+ * sp+1 -> PC bits 8-15
+ * sp+2 -> FLG bits 0-7
+ * sp+3 -> FLG (Bits 12-14) + PC (bits 16-19)
+ *
+ * - Set IPL
+ * - Vectors to this S/W interrupt handler:
+ */
+
+_m16c_contextsave:
+
+/* Save all registers on the interrupt stack */
+
+ mov.w #1, r0 /* Return 1 on context switch */
+ pushm fb,sb,a1,a0,r3,r2,r1,r0 /* Save on interrupt stack */
+
+/* Save the user stack pointer on the interrupt stack */
+
+ fset u /* Switch to User stack */
+ stc sp, r0 /* R0 = user stack pointer */
+ fclr u /* Back to interrupt stack */
+ push.w r0 /* Save user sp on isp */
+
+/* Then copy the stack content to the register context array pointed to by r1 */
+
+ stc isp, a0 /* A0 = address of base of context info */
+ mov.w r1, a1 /* A1 = address of register context array */
+ mov.b #0, r1h /* R1H = 4 MS of 20-bit source address */
+ mov.w #XCPTCONTEXT_SIZE, r3 /* R3 = Number of bytes to transfer */
+ smovf.b /* Copy ISP to near context array */
+
+/* Then return zero to indicate a normal function call return */
+
+ add.w #(XCPTCONTEXT_SIZE - 4), sp /* Remove stuff from stack */
+ mov.w #0, r0 /* Return zero */
+ reit /* Return from interrupt */
+ .size _up_saveusercontext, .-_up_saveusercontext
+
+/************************************************************************************
+ * Name: void up_fullcontextrestore(uint32 *regs)
+ *
+ * Description:
+ * Restore the context of the using the provided register save array.
+ *
+ * Input Parameters:
+ * R1 = Address of register save array
+ *
+ * Returned Value:
+ * None
+ *
+ ************************************************************************************/
+
+ .globl _up_fullcontextrestore
+ .type _up_fullcontextrestore, #function
+
+_up_fullcontextrestore:
+ int #32 /* Execute S/W interrupt 32 */
+ rts /* and return */
+
+/* This the logic executes in response to S/W interrupt 32. The 'int 32' instruction
+ * will cause the following actions:
+ *
+ * - Save FLG register
+ * - Clear I and D flags in FLG register (U is preserved)
+ * - Builds stack frame like (on the push-down, interrupt stack):
+ *
+ * sp -> PC bits 0-7
+ * sp+1 -> PC bits 8-15
+ * sp+2 -> FLG bits 0-7
+ * sp+3 -> FLG (Bits 12-14) + PC (bits 16-19)
+ *
+ * - Set IPL
+ * - Vectors to this S/W interrupt handler:
+ */
+
+_m16c_contextrestore:
+
+/* Set the USP to the beginning of the context save area */
+
+ ldc r1, sp /* USP = address of base of new context info */
+
+ /* Restore the user stack pointer */
+
+ fset b /* Switch to bank 1 */
+ pop.w r0 /* R0 = saved user stack pointer */
+ fclr b /* Back to bank 0 */
+
+/* Recover all registers */
+
+ popm fb,sb,a1,a0,r3,r2,r1,r0 /* Restore from registers from user stack */
+
+/* Set the USP and return */
+
+ fset b /* Switch to bank 1 */
+ popm r1,r0 /* Recover the PC and flags */
+ stc sp, r0 /* Set the correct USP */
+ pushm r1,r0 /* Put the PC and flags */
+ fclr b /* Back to bank 0 */
+
+/* The return from interrupt */
+
+ reit /* Return from interrupt */
+ .size _up_fullcontextrestore, .-_up_fullcontextrestore
.end
diff --git a/arch/sh/src/sh1/sh1_saveusercontext.S b/arch/sh/src/sh1/sh1_saveusercontext.S
index ee6952f460f2b55164e83a2ee96913299a12da3d..1514b9399258a2a701f712d209ee8148cbdab344 100644
--- a/arch/sh/src/sh1/sh1_saveusercontext.S
+++ b/arch/sh/src/sh1/sh1_saveusercontext.S
@@ -1,7 +1,7 @@
/**************************************************************************
* arch/sh/src/sh1/sh1_saveusercontext.S
*
- * Copyright (C) 2008 Gregory Nutt. All rights reserved.
+ * Copyright (C) 2008, 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
*
* Redistribution and use in source and binary forms, with or without