From cf35bb0b180b53708291c6301beabd6c0aac29de Mon Sep 17 00:00:00 2001
From: Wolfgang Reissnegger <wolfgang@jupiterfoundation.org>
Date: Tue, 9 Aug 2016 12:52:12 -0700
Subject: [PATCH] SAM3/4 GPIO: Enable peripheral clock for GPIO port when GPIO
is configured as input.
The value of a GPIO input is only sampled when the peripheral clock for
the port controller the GPIO resides in is enabled. Therefore we need
to enable the clock even when polling a GPIO.
---
arch/arm/src/sam34/sam_gpio.c | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/src/sam34/sam_gpio.c b/arch/arm/src/sam34/sam_gpio.c
index 89461c5836..5b2b65a0ee 100644
--- a/arch/arm/src/sam34/sam_gpio.c
+++ b/arch/arm/src/sam34/sam_gpio.c
@@ -54,6 +54,7 @@
#include "chip.h"
#include "sam_gpio.h"
+#include "sam_periphclks.h"
#if defined(CONFIG_ARCH_CHIP_SAM3U) || defined(CONFIG_ARCH_CHIP_SAM3X) || \
defined(CONFIG_ARCH_CHIP_SAM3A)
@@ -179,6 +180,31 @@ static inline int sam_configinput(uintptr_t base, uint32_t pin,
putreg32(pin, base + SAM_PIO_ODR_OFFSET);
putreg32(pin, base + SAM_PIO_PER_OFFSET);
+ /* Enable the peripheral clock for the GPIO's port controller.
+ * A GPIO input value is only sampled if the peripheral clock for its
+ * controller is enabled.
+ */
+
+ switch (cfgset & GPIO_PORT_MASK)
+ {
+ case GPIO_PORT_PIOA:
+ sam_pioa_enableclk();
+ break;
+
+ case GPIO_PORT_PIOB:
+ sam_piob_enableclk();
+ break;
+
+#ifdef GPIO_HAVE_PERIPHCD
+ case GPIO_PORT_PIOC:
+ sam_pioc_enableclk();
+ break;
+#endif
+
+ default:
+ return -EINVAL;
+ }
+
/* To-Do: If DEGLITCH is selected, need to configure DIFSR, SCIFSR, and
* IFDGSR registers. This would probably best be done with
* another, new API... perhaps sam_configfilter()
--
GitLab