diff --git a/ChangeLog b/ChangeLog index 226425ca8fc47c0ea564a2b4feba890d483c1ace..116684e0536c9c4246f9b895c6ad4a8aa5a6ab70 100755 --- a/ChangeLog +++ b/ChangeLog @@ -12139,14 +12139,10 @@ * arch/arm/arc/sam34: DAC bugfix: DACC_WPMR_WPKEY_MASK -> DACC_WPMR_WPKEY. Timer bugfix: Fix ops check in TCIOC_STOP. From Wolfgang Reissnegge (2016-06-23). + * configs/nucleo-144: Added SDMMC support to Nucleo-144. From David + Sidrane (2016-06-23). * arch/arm/src/stm32: Port STM32L4 CAN IOCTLs to STM32. From Sebastien Lorquet (2016-06-24). - * configs/Konfig:Add configuration logic to include a Kconfig file in - each custom configuration. Includes adding a dummy custom board - configuration directory. A consequence of this that each custom board - directory will now need to contain a Kconfig file. NOTE also that - the new board directory does not take effect in the configuration - menus until the NEXT time you run 'make menuconfig' (2016-06-24). * drivers/ioexpander: Add support for a very simple GPIO driver. It supports only pre-conrigured input and output pins and only basic input and output operations (2016-06-24). @@ -12171,3 +12167,103 @@ necessary because otherwise you cannot read back the correct line status of Open-Drain Outputs and this is needed by the twi_reset function. From Michael Spahlinger (2016-06-24) + * arch/arm/src/stm32f7: BUGFIX:PLLs IS2 and SAI P Calculation. From + David Sidrane (2016-06-24). + * arch/arm/src/stm32f7: USB support. From Lok Tep (2016-06-27). + * configs/olimex-stm32-e407: Add support for Olimex STM32 E407 + board. From Mateusz Szafoni (2016-06-27). + * drivers/ioexpander: Shadow-Mode: The output- and configuration + registers of the IO-Expander are held in the microcontrollers memory + and only written to the IO-Expander. This reduces bus traffic and + is more error-proof than the normal read-modify-write operation. Retry + Mode: If enabled and an error occurs while writing to the IO-Expander + the current transmission is automatically repeated once. From Michael + Spahlinger (2016-06-27). + * libc/hex2bin: Move the portable library portion of apps/system/hex2bin + to nuttx/libc/hex2bin where it can be shared with the OS internals + (2016-06-27). + * configs/nucleo-144: Added USB OTG device to Nucleo-144. From David + Sidrane (2016-06-27). + * arch/arm/src/stm32l4: STM32 CAN fixes need to be backported to + STM32L4 as well (2016-06-27). + * ARM stack check: Fix double fault on IDLE task with stack size = 0. + From David Sidrane (2016-06-27). + * configs/nucleo-144: Added bbsram test to Nucleo-144. From David + Sidrane (2016-06-27). + * arch/arm/src/stm32f7: Added PWR, RTC, and BBSRAM support for stm32f7. + From David Sidrane (2016-06-27). + * Build system: Fixed build of SAMV71-XULT/nsh. With the changes from + 26f7b8c the build process of the default configuration did not succeed + anymore. From Michael Spahlinger (2016-06-28). + * sched/semaphore: Need to set errno to EINVAL on errors in sem_post() + and sem_wait(). From Paul Alexander Patience (2016-06-28). + * Build system: This change fixes a build problem that only occurs when + reconfiguring from Linux to Windows or vice-versa. It is a problem + that was present but not usually experienced until two things happened: + (1) The pre_config target was added to run before the menconfig + operation and (2) the context target was added before the pre_config + target in order to set up the correct symbolic links (in the apps/platform + directory) needed by the pre_config target. + But then now if you start with a Linux system and run 'make menuconfig' + to switch to Linux, the context target will execute first and set up + POSIX style symbolic links before doing the menuconfig. Then after the + menuconfig, the make will fail on Windows if you are using a Windows + native toolchain because that native toolchain cannot follow the Cygwin- + style symbolic links. + The fix here is to also execute the clean_context AFTER executing + menuconfig. A lot more happens now: It used to be that doing 'make + menuconfig' only did the menuconfig operation. No it does context, + pre_config, menuconfig, clean_context. Not nearly as snappy as it used + to be (2016-06-28). + * arch/arm/src/efm32, lcp43, stm32, stm32l4: disable interrupts with + NVIC_IRQ_CLEAR. From Paul Alexander Patience (2016-06-28). + * arch/arm/src/stm32f7: STMF7xxx RTC: (1) Remove proxy #defines, (2) + Ensure the LSE(ON) etal are set and remembered in a) A cold start + (RTC_MAGIC invalid) of the RTC, and b) A warm start (RTC_MAGIC valid) + of the RTC but a clock change. The change was needed because in bench + testing a merge of the latest's STM32 53ec3ca (and friends) it became + apparent that the sequence of operation is wrong in the reset of the + Backup Domain in the RCC code. PWR is required before the Backup + Domain can be futzed with. !!!This Code should be tested on STM32 and + if needed rippled to the STM32 families. From David Sidrane + (2016-06-28). + * arch/arm/src/stm32f7: Added STMF7xxx RTC. From David Sidrane + (2016-06-28). + * arch/arm/src/stm32: STM32 BBSRAM fixed (and formatted) flags. From + David Sidrane (2016-06-28). + * arch/arm/src/stm32f7: STM32F7 BBSRAM fixed (and formatted) flags. + From David Sidrane (2016-06-28). + * arch/arm/src/stm32f7: Added STM32F7 DBGMCU. From David Sidrane + (2016-06-28). + * arch/arm/src/samv7: SAMV7: CAN Message Filtering fixed: (1) stdfilters + didn't work because the filter was never enabled (wrong number of bits + to shift), and (2) Filters were never used because the configuration + register cannot be written without using the initialization mode. + Both bugs are fixed by this change. Filtering has been tested with + both standard and extended identifiers and is now working properly. + From Michael Spahlinger (2016-06-29). + * configs/Kconfig and dummy/: Add logic to support custom board + directories that include a Kconfig file. During the context phase + of the build, any Kconfig file in the custom board directory is copied + into configs/dummy, replacing the existing Kconfig file with the + target Kconfig file (2016-06-29). + * arch/arm/src/stm32l4: Port support for both RX FIFOs from STM32 CAN. + From Paul Alexander Patience (2016-06-29). + * Remove all inclusion of header files from the apps/include directory. + This caused a lot of reshuffling of logic: binfmt pcode support, + usbmonitor is now a kernel thread, TZ/Olson database moved to + libc/zoneinfo (2016-06-29). + * drivers/mtd: Several MTD FLASH drivers nullify the freed 'priv' + structure and failed to return NULL as stated in the comments. + Result, will operate on a NULL pointer later. Noted by David Sidrane + (2016-06-30). + * arch/arm/src/kinetis: Add basic support for the K64 family. I + leveraged the changes from https://github.com/jmacintyre/nuttx-k64f + and merged into the existing kinetis code with a lot of changes and + additions (like pin multiplexing definitions). (2016-07-01). + * configs/freedom-k64f: Add support for the NXP Freedom-K64F board. + This is primarily the work of Jordan Macintyre. I leveraged this + code from https://github.com/jmacintyre/nuttx-k64f but with + significant corrections (LEDs, buttons, README, etc) and extensions + and updates to match more recent BSPs (2016-07-01). + * libc/signal: Add raise() (2016-07-04). diff --git a/Directories.mk b/Directories.mk index 2e42a8a435f25de41b1646e5bcea5a60787b7a86..2e55b91a94007f210ad4b6ab58700092a32e3bb3 100644 --- a/Directories.mk +++ b/Directories.mk @@ -74,7 +74,7 @@ endif NONFSDIRS = sched drivers configs $(ARCH_SRC) $(NUTTX_ADDONS) FSDIRS = fs binfmt -CONTEXTDIRS = $(APPDIR) +CONTEXTDIRS = configs $(APPDIR) USERDIRS = OTHERDIRS = lib @@ -114,6 +114,10 @@ else OTHERDIRS += syscall endif +ifeq ($(CONFIG_LIB_ZONEINFO_ROMFS),y) +CONTEXTDIRS += libc +endif + ifeq ($(CONFIG_NX),y) NONFSDIRS += graphics libnx CONTEXTDIRS += graphics libnx diff --git a/Documentation/README.html b/Documentation/README.html index 1c13c8abdd8d022245f1c87b874f95499003a93d..d9199a48271e83f98f5219d49fa39e51af8a0823 100644 --- a/Documentation/README.html +++ b/Documentation/README.html @@ -8,7 +8,7 @@

NuttX README Files

-

Last Updated: May 26, 2016

+

Last Updated: July 3, 2016

@@ -30,24 +30,24 @@ nuttx/ | | | |- arm/ | | `- src - | | `- lpc214x/README.txt + | | `- lpc214x/README.txt | |- sh/ | | |- include/ - | | | `-README.txt + | | | `-README.txt | | |- src/ - | | | `-README.txt + | | | `-README.txt | |- x86/ | | |- include/ - | | | `-README.txt + | | | `-README.txt | | `- src/ - | | `-README.txt + | | `-README.txt | |- z80/ | | |- src/z80 - | | | `- README.txt + | | | `- README.txt | | `- src/z180 - | | |- README.txt - | | `- z180_mmu.txt - | `- README.txt + | | |- README.txt + | | `- z180_mmu.txt + | `- README.txt |- binfmt/ | |- libpcode/ | `- README.txt @@ -55,263 +55,263 @@ nuttx/ | `- README.txt |- configs/ | |- amber/ - | | `- README.txt + | | `- README.txt | |- arduino-mega2560/ - | | `- README.txt + | | `- README.txt | |- arduino-due/ - | | `- README.txt + | | `- README.txt | |- avr32dev1/ - | | `- README.txt + | | `- README.txt | |- c5471evm/ - | | `- README.txt + | | `- README.txt | |- cc3200-launchpad/ - | | `- README.txt + | | `- README.txt | |- cloudctrl/ - | | `- README.txt + | | `- README.txt | |- compal_e86/ - | | `- README.txt + | | `- README.txt | |- compal_e88/ - | | `- README.txt + | | `- README.txt | |- compal_e99/ - | | `- README.txt + | | `- README.txt | |- demo9s12ne64/ - | | `- README.txt + | | `- README.txt | |- dk-tm4c129x/ - | | `- README.txt + | | `- README.txt | |- ea3131/ - | | `- README.txt + | | `- README.txt | |- ea3152/ - | | `- README.txt + | | `- README.txt | |- eagle100/ - | | `- README.txt + | | `- README.txt | |- efm32-g8xx-stk/ - | | `- README.txt + | | `- README.txt | |- efm32gg-stk3700/ - | | `- README.txt + | | `- README.txt | |- ekk-lm3s9b96/ - | | `- README.txt + | | `- README.txt | |- ez80f910200kitg/ - | | |- ostest/README.txt - | | `- README.txt + | | |- ostest/README.txt + | | `- README.txt | |- ez80f910200zco/ - | | |- dhcpd/README.txt - | | |- httpd/README.txt - | | |- nettest/README.txt - | | |- nsh/README.txt - | | |- ostest/README.txt - | | |- poll/README.txt - | | `- README.txt + | | |- dhcpd/README.txt + | | |- httpd/README.txt + | | |- nettest/README.txt + | | |- nsh/README.txt + | | |- ostest/README.txt + | | |- poll/README.txt + | | `- README.txt | |- fire-stm32v2/ - | | `- README.txt + | | `- README.txt + | |- freedom-k64f/ + | | `- README.txt | |- freedom-kl25z/ - | | `- README.txt + | | `- README.txt | |- freedom-kl26z/ - | | `- README.txt + | | `- README.txt | |- hymini-stm32v/ - | | |- RIDE/README.txt - | | `- README.txt + | | |- RIDE/README.txt + | | `- README.txt | |- kwikstik-k40/ - | | `- README.txt + | | `- README.txt | |- launchxl-tms57004/ - | | `- README.txt + | | `- README.txt | |- lincoln60/ - | | `- README.txt + | | `- README.txt | |- lm3s6432-s2e/ - | | `- README.txt + | | `- README.txt | |- lm3s6965-ek/ - | | `- README.txt + | | `- README.txt | |- lm3s8962-ek/ - | | `- README.txt + | | `- README.txt | |- lpc4330-xplorer/ - | | `- README.txt + | | `- README.txt | |- lpc4337-ws/ - | | `- README.txt + | | `- README.txt | |- lpc4357-evb/ - | | `- README.txt + | | `- README.txt | |- lpc4370-link2/ - | | `- README.txt + | | `- README.txt | |- lpcxpresso-lpc1115/ - | | `- README.txt + | | `- README.txt | |- lpcxpresso-lpc1768/ - | | `- README.txt + | | `- README.txt | |- maple/ - | | `- README.txt + | | `- README.txt | |- mbed/ - | | `- README.txt + | | `- README.txt | |- mcu123-lpc214x/ - | | `- README.txt + | | `- README.txt | |- micropendous3/ - | | `- README.txt + | | `- README.txt | |- mikroe-stm32f4/ - | | `- README.txt + | | `- README.txt | |- mirtoo/ - | | `- README.txt - | |- mt-db-x3// - | | `- README.txt + | | `- README.txt | |- moteino-mega/ - | | `- README.txt + | | `- README.txt | |- mx1ads/ - | | `- README.txt + | | `- README.txt | |- ne64badge/ - | | `- README.txt + | | `- README.txt | |- ntosd-dm320/ - | | |- doc/README.txt - | | `- README.txt + | | |- doc/README.txt + | | `- README.txt | |- nucleo-144/ - | | `- README.txt + | | `- README.txt | |- nucleo-f4x1re/ - | | `- README.txt + | | `- README.txt | |- nutiny-nuc120/ - | | `- README.txt + | | `- README.txt | |- olimex-efm32g880f129-stk/ - | | `- README.txt + | | `- README.txt | |- olimex-lpc1766stk/ - | | `- README.txt + | | `- README.txt | |- olimex-lpc2378/ - | | `- README.txt + | | `- README.txt | |- olimex-lpc-h3131/ - | | `- README.txt + | | `- README.txt | |- olimex-stm32-h405/ - | | `- README.txt + | | `- README.txt | |- olimex-stm32-h407/ - | | `- README.txt + | | `- README.txt | |- olimex-stm32-p107/ - | | `- README.txt + | | `- README.txt | |- olimex-stm32-p207/ - | | `- README.txt + | | `- README.txt | |- olimex-strp711/ - | | `- README.txt + | | `- README.txt | |- open1788/ - | | `- README.txt + | | `- README.txt | |- p112/ - | | `- README.txt + | | `- README.txt | |- pcblogic-pic32mx/ - | | `- README.txt + | | `- README.txt | |- pcduino-a10/ - | | `- README.txt + | | `- README.txt | |- pic32mx-starterkit/ - | | `- README.txt + | | `- README.txt | |- pic32mx7mmb/ - | | `- README.txt + | | `- README.txt | |- pic32mz-starterkit/ - | | `- README.txt + | | `- README.txt | |- pirelli_dpl10/ - | | `- README.txt + | | `- README.txt | |- qemu-i486/ - | | `- README.txt + | | `- README.txt | |- rgmp/ - | | `- README.txt + | | `- README.txt | |- sabre-6quad/ - | | `- README.txt + | | `- README.txt | |- sama5d2-xult/ - | | `- README.txt + | | `- README.txt | |- sama5d3x-ek/ - | | `- README.txt + | | `- README.txt | |- sama5d3-xplained/ - | | `- README.txt + | | `- README.txt | |- sama5d4-ek/ - | | `- README.txt + | | `- README.txt | |- samd20-xplained/ - | | `- README.txt + | | `- README.txt | |- samd21-xplained/ - | | `- README.txt + | | `- README.txt | |- saml21-xplained/ - | | `- README.txt + | | `- README.txt | |- sam3u-ek/ - | | `- README.txt + | | `- README.txt | |- sam4e-ek/ - | | `- README.txt + | | `- README.txt | |- sam4l-xplained/ - | | `- README.txt + | | `- README.txt | |- sam4s-xplained/ - | | `- README.txt + | | `- README.txt | |- sam4s-xplained-pro/ - | | `- README.txt + | | `- README.txt | |- same70-xplained/ - | | `- README.txt + | | `- README.txt | |- samv71-xult/ - | | `- README.txt + | | `- README.txt | |- shenzhou/ - | | `- README.txt + | | `- README.txt | |- sim/ - | | |- include/README.txt - | | `- README.txt + | | |- include/README.txt + | | `- README.txt | |- skp16c26/ - | | `- README.txt + | | `- README.txt | |- spark/ - | | `- README.txt + | | `- README.txt | |- stm3210e-eval/ - | | |- RIDE/README.txt - | | `- README.txt + | | |- RIDE/README.txt + | | `- README.txt | |- stm3220g-eval/ - | | |- ide/nsh/uvision/README.txt - | | |- ide/nsh/iar/README.txt - | | `- README.txt + | | |- ide/nsh/uvision/README.txt + | | |- ide/nsh/iar/README.txt + | | `- README.txt | |- stm3240g-eval/ - | | `- README.txt + | | `- README.txt | |- stm32_tiny/ - | | `- README.txt + | | `- README.txt | |- stm32f103-minumum/ - | | `- README.txt + | | `- README.txt | |- stm32f3discovery/ - | | `- README.txt + | | `- README.txt | |- stm32f4discovery/ - | | `- README.txt + | | `- README.txt | |- stm32f411e-disco/ - | | `- README.txt + | | `- README.txt | |- stm32f429i-disco/ - | | |- ide/ltcd/uvision/README.txt - | | |- ltdc/README.txt - | | `- README.txt + | | |- ide/ltcd/uvision/README.txt + | | |- ltdc/README.txt + | | `- README.txt | |- stm32f746g-disco/ - | | `- README.txt + | | `- README.txt | |- stm32l476vg-disco/ - | | `- README.txt + | | `- README.txt | |- stm32ldiscovery/ - | | `- README.txt + | | `- README.txt | |- stm32vldiscovery/ - | | `- README.txt + | | `- README.txt | |- sure-pic32mx/ - | | `- README.txt + | | `- README.txt | |- teensy-2.0/ - | | `- README.txt + | | `- README.txt | |- teensy-3.1/ - | | `- README.txt + | | `- README.txt | |- teensy-lc/ - | | `- README.txt + | | `- README.txt | |- tm4c123g-launchpad/ - | | `- README.txt + | | `- README.txt | |- tm4c1294-launchpad/ - | | `- README.txt + | | `- README.txt | |- twr-k60n512/ - | | `- README.txt + | | `- README.txt | |- "u-blox-c027/ - | | `- README.txt + | | `- README.txt | |- ubw32/ - | | `- README.txt + | | `- README.txt | |- us7032evb1/ - | | `- README.txt + | | `- README.txt | |- viewtool-stm32f107/ - | | `- README.txt + | | `- README.txt | |- xtrs/ - | | `- README.txt + | | `- README.txt | |- z16f2800100zcog/ - | | |- ostest/README.txt - | | |- pashello/README.txt - | | `- README.txt + | | |- ostest/README.txt + | | |- pashello/README.txt + | | `- README.txt | |- z80sim/ - | | `- README.txt + | | `- README.txt | |- z8encore000zco/ - | | |- ostest/README.txt - | | `- README.txt + | | |- ostest/README.txt + | | `- README.txt | |- z8f64200100kit/ - | | |- ostest/README.txt - | | `- README.txt + | | |- ostest/README.txt + | | `- README.txt | |- zkit-arm-1769/ - | | `- README.txt + | | `- README.txt | |- zp214xpa/ - | | `- README.txt - | `- README.txt + | | `- README.txt + | `- README.txt |- drivers/ | |- eeprom/ | | `- README.txt @@ -345,6 +345,7 @@ nuttx/ |- lib/ | `- README.txt |- libc/ + | |- zoneinfo/README.txt | `- README.txt |- libnx/ | `- README.txt @@ -402,8 +403,7 @@ apps/ |- nxplayer/README.txt |- symtab/README.txt |- usbmsc/README.txt - |- zmodem/README.txt - `- zoneinfo/README.txt + `- zmodem/README.txt

diff --git a/Documentation/UsbTrace.html b/Documentation/UsbTrace.html index a6800983d5bcb272c099f6bfba24de374b9a707a..25c8736b7b3a45d131cb0725eac59c2811b55df5 100644 --- a/Documentation/UsbTrace.html +++ b/Documentation/UsbTrace.html @@ -396,7 +396,7 @@ static int pl2303_setup(FAR struct uart_dev_s *dev) - CONFIG_SYSTEM_USBMONITOR=y + CONFIG_USBMONITOR=y Enable the USB monitor daemon @@ -404,7 +404,7 @@ static int pl2303_setup(FAR struct uart_dev_s *dev) - CONFIG_SYSTEM_USBMONITOR_STACKSIZE=nnnn + CONFIG_USBMONITOR_STACKSIZE=nnnn Sets the USB monitor daemon stack size to nnnn. @@ -413,7 +413,7 @@ static int pl2303_setup(FAR struct uart_dev_s *dev) - CONFIG_SYSTEM_USBMONITOR_PRIORITY=50 + CONFIG_USBMONITOR_PRIORITY=50 Sets the USB monitor daemon priority to nnnn. @@ -423,7 +423,7 @@ static int pl2303_setup(FAR struct uart_dev_s *dev) - CONFIG_SYSTEM_USBMONITOR_INTERVAL=nnnn + CONFIG_USBMONITOR_INTERVAL=nnnn Dump the buffered USB data every nnnn seconds. @@ -432,11 +432,11 @@ static int pl2303_setup(FAR struct uart_dev_s *dev) - CONFIG_SYSTEM_USBMONITOR_TRACEINIT=y
- CONFIG_SYSTEM_USBMONITOR_TRACECLASS=y
- CONFIG_SYSTEM_USBMONITOR_TRACETRANSFERS=y
- CONFIG_SYSTEM_USBMONITOR_TRACECONTROLLER=y
- CONFIG_SYSTEM_USBMONITOR_TRACEINTERRUPTS=y
+ CONFIG_USBMONITOR_TRACEINIT=y
+ CONFIG_USBMONITOR_TRACECLASS=y
+ CONFIG_USBMONITOR_TRACETRANSFERS=y
+ CONFIG_USBMONITOR_TRACECONTROLLER=y
+ CONFIG_USBMONITOR_TRACEINTERRUPTS=y
Selects which USB event(s) that you want to be traced. diff --git a/Makefile.unix b/Makefile.unix index a6913ad672a7a87a9b5887a426ab5303a328f8ec..6c0c46b38cfb42b722f9b8f09459872f376be8fe 100644 --- a/Makefile.unix +++ b/Makefile.unix @@ -344,6 +344,7 @@ context: check_context include/nuttx/config.h include/nuttx/version.h include/ma # and symbolic links created by the context target. clean_context: + $(Q) $(MAKE) -C configs TOPDIR="$(TOPDIR)" clean_context $(call DELFILE, include/nuttx/config.h) $(call DELFILE, include/nuttx/version.h) $(call DELFILE, include/math.h) @@ -480,24 +481,36 @@ pass2dep: context tools/mkdeps$(HOSTEXEEXT) tools/cnvwindeps$(HOSTEXEEXT) # location: http://ymorin.is-a-geek.org/projects/kconfig-frontends. See # README.txt file in the NuttX tools GIT repository for additional information. -config: context apps_preconfig +do_config: context apps_preconfig $(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-conf Kconfig -oldconfig: context apps_preconfig +config: do_config clean_context + +do_oldconfig: context apps_preconfig $(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-conf --oldconfig Kconfig -olddefconfig: context apps_preconfig +oldconfig: do_oldconfig clean_context + +do_olddefconfig: context apps_preconfig $(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-conf --olddefconfig Kconfig -menuconfig: context apps_preconfig +olddefconfig: do_olddefconfig clean_context + +do_menuconfig: context apps_preconfig $(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-mconf Kconfig -qconfig: context apps_preconfig +menuconfig: do_menuconfig clean_context + +do_qconfig: context apps_preconfig $(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-qconf Kconfig +qconfig: do_qconfig clean_context + gconfig: context apps_preconfig $(Q) APPSDIR=${CONFIG_APPS_DIR} kconfig-gconf Kconfig +gconfig: do_gconfig clean_context + # export # # The export target will package the NuttX libraries and header files into diff --git a/Makefile.win b/Makefile.win index 5556efb79ff28a9a4d183bab6dc7b3ba1bd4c4e9..484e6a938d3607bd5d97dae99b2ee15f3aafb748 100644 --- a/Makefile.win +++ b/Makefile.win @@ -480,18 +480,26 @@ pass2dep: context tools\mkdeps$(HOSTEXEEXT) # location: http://ymorin.is-a-geek.org/projects/kconfig-frontends. See # misc\tools\README.txt for additional information. -config: context apps_preconfig +do_config: context apps_preconfig $(Q) set APPSDIR=$(patsubst "%",%,${CONFIG_APPS_DIR})& kconfig-conf Kconfig -oldconfig: context apps_preconfig - $(Q) context set APPSDIR=$(patsubst "%",%,${CONFIG_APPS_DIR})& kconfig-conf --oldconfig Kconfig +config: do_config clean_context -olddefconfig: context apps_preconfig +do_oldconfig: context apps_preconfig + $(Q) set APPSDIR=$(patsubst "%",%,${CONFIG_APPS_DIR})& kconfig-conf --oldconfig Kconfig + +oldconfig: do_oldconfig clean_context + +do_olddefconfig: context apps_preconfig $(Q) set APPSDIR=$(patsubst "%",%,${CONFIG_APPS_DIR})& kconfig-conf --olddefconfig Kconfig -menuconfig: context configenv apps_preconfig +olddefconfig: do_olddefconfig clean_context + +do_menuconfig: context configenv apps_preconfig $(Q) set APPSDIR=$(patsubst "%",%,${CONFIG_APPS_DIR})& kconfig-mconf Kconfig +menuconfig: do_menuconfig clean_context + # export # # The export target will package the NuttX libraries and header files into diff --git a/README.txt b/README.txt index b3cb19a407d1186cd21c99a0e3c7c5ec67d60efc..4c12dca85ac5157cc5830d7a24eeee3e84acb2c8 100644 --- a/README.txt +++ b/README.txt @@ -1283,6 +1283,8 @@ nuttx/ | | `- README.txt | |- fire-stm32v2/ | | `- README.txt + | |- freedom-k64f/ + | | `- README.txt | |- freedom-kl25z/ | | `- README.txt | |- freedom-kl26z/ @@ -1325,8 +1327,6 @@ nuttx/ | | `- README.txt | |- mirtoo/ | | `- README.txt - | |- mt-db-x3/ - | | `- README.txt | |- moteino-mega/ | | `- README.txt | |- mx1ads/ @@ -1524,6 +1524,8 @@ nuttx/ |- lib/ | `- README.txt |- libc/ + | |- zoneinfo + | | `- README.txt | `- README.txt |- libnx/ | `- README.txt @@ -1590,9 +1592,7 @@ apps/ | | `- README.txt | |- usbmsc | | `- README.txt - | |- zmodem - | | `- README.txt - | `- zoneinfo + | `- zmodem | `- README.txt `- README.txt diff --git a/ReleaseNotes b/ReleaseNotes index c760fca73723f71cf5a0ac0ae51f45a043ffefad..5afe3d5724e0f352a9149d8b9e7e674b1d0e8d8f 100644 --- a/ReleaseNotes +++ b/ReleaseNotes @@ -2570,7 +2570,7 @@ New features and extended functionality: particular for a CDC/ACM with MSC USB composite driver). Added a new RAM logging driver. This will allow debug output into - a RAM buffer associated with a character driver at /dev/syslog. + a RAM buffer associated with a character driver at /dev/ramlog. Added the new command 'dmesg' to NSH that can be used to dump the current contents of the log. This is useful for systems that do not have the usual serial console (for example, if you only have a @@ -8991,7 +8991,7 @@ Additional new features and extended functionality: * Applications: apps/system: - - apps/system/zoneinfo: Add logic to build a ROMFS file system + - nuttx/zoneinfo: Add logic to build a ROMFS file system containing the timezone data. * Applications: apps/nshlib: diff --git a/TODO b/TODO index a4c960e2e18b5004b1242728731a7c3ee3caa424..5c67ae83acd5f6388eded9a850e59308b95444a6 100644 --- a/TODO +++ b/TODO @@ -1,4 +1,4 @@ -NuttX TODO List (Last updated June 6, 2016) +NuttX TODO List (Last updated July 3, 2016) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ This file summarizes known NuttX bugs, limitations, inconsistencies with @@ -17,7 +17,7 @@ nuttx/: (9) Kernel/Protected Build (3) C++ Support (6) Binary loaders (binfmt/) - (12) Network (net/, drivers/net) + (11) Network (net/, drivers/net) (4) USB (drivers/usbdev, drivers/usbhost) (0) Other drivers (drivers/) (11) Libraries (libc/, libm/) @@ -938,6 +938,7 @@ o Network (net/, drivers/net) TM4C YES YES eZ80 NO NO LPC17xx YES YES (not tested) + LPC43xx YES YES (not tested) DMxxx NIC NO NO PIC32 NO NO RGMP ??? ??? @@ -1352,12 +1353,6 @@ o File system / Generic drivers (fs/, drivers/) Status: Open Priority: Low - Title: CAN POLL SUPPORT - Description: At present, the CAN driver does not support the poll() method. - See drivers/can.c - Status: Open - Priority: Low - Title: ROMFS CHECKSUMS Description: The ROMFS file system does not verify checksums on either volume header on on the individual files. @@ -1602,7 +1597,7 @@ o Build system Priority: Low. Title: NATIVE WINDOWS BUILD BROKEN - Description: The way that apps/ no generates Kmenu files depends on changes added + Description: The way that apps/ now generates Kmenu files depends on changes added to apps/tools/mkkconfig.sh. Similar changes need to be made to apps/tools/mkkconfig.bat to restore the Windows Native build. UPDATE: The mkkconfig.bat script has been updated and appears to work. diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index fcc1c9ce9821b82dbbfc1f61b1bf29523a391529..12af0d6056169c7e9d04f709ff3bb196d73c647f 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -224,6 +224,7 @@ config ARCH_CHIP_STM32 select ARM_HAVE_MPU_UNIFIED select ARCH_HAVE_I2CRESET select ARCH_HAVE_HEAPCHECK + select ARCH_HAVE_TICKLESS select ARMV7M_HAVE_STACKCHECK ---help--- STMicro STM32 architectures (ARM Cortex-M3/4). diff --git a/arch/arm/include/kinetis/chip.h b/arch/arm/include/kinetis/chip.h index dd8582e564fc8e78472ed6b53c9e4eaf200d10a1..f2fa5fbb4e707b0732f369f6a4d9e0e27dc9a117 100644 --- a/arch/arm/include/kinetis/chip.h +++ b/arch/arm/include/kinetis/chip.h @@ -1,7 +1,7 @@ /************************************************************************************ * arch/arm/include/kinetis/chip.h * - * Copyright (C) 2011, 2013, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2013, 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -72,6 +72,7 @@ # define KINETIS_K20 1 /* Kinetics K20 family */ # undef KINETIS_K40 /* Not Kinetics K40 family */ # undef KINETIS_K60 /* Not Kinetis K60 family */ +# undef KINETIS_K64 /* Not Kinetis K64 family */ #if defined(CONFIG_ARCH_CHIP_MK20DN32VLH5) # define KINETIS_FLASH_SIZE (64*1024) /* 32Kb */ @@ -153,6 +154,7 @@ # define KINETIS_K20 1 /* Kinetics K20 family */ # undef KINETIS_K40 /* Not Kinetics K40 family */ # undef KINETIS_K60 /* Not Kinetis K60 family */ +# undef KINETIS_K64 /* Not Kinetis K64 family */ #if defined(CONFIG_ARCH_CHIP_MK20DX64VLH7) # define KINETIS_FLASH_SIZE (64*1024) /* 64Kb */ @@ -207,6 +209,7 @@ # undef KINETIS_K20 /* Not Kinetis K20 family */ # define KINETIS_K40 1 /* Kinetics K40 family */ # undef KINETIS_K60 /* Not Kinetis K60 family */ +# undef KINETIS_K64 /* Not Kinetis K64 family */ # define KINETIS_FLASH_SIZE (64*1024) /* 64Kb */ # define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */ # define KINETIS_SRAM_SIZE (16*1024) /* 16Kb */ @@ -257,6 +260,7 @@ # undef KINETIS_K20 /* Not Kinetis K20 family */ # define KINETIS_K40 1 /* Kinetics K40 family */ # undef KINETIS_K60 /* Not Kinetis K60 family */ +# undef KINETIS_K64 /* Not Kinetis K64 family */ # define KINETIS_FLASH_SIZE (128*1024) /* 128Kb */ # define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */ # define KINETIS_SRAM_SIZE (32*1024) /* 32Kb */ @@ -299,6 +303,7 @@ # undef KINETIS_K20 /* Not Kinetis K20 family */ # define KINETIS_K40 1 /* Kinetics K40 family */ # undef KINETIS_K60 /* Not Kinetis K60 family */ +# undef KINETIS_K64 /* Not Kinetis K64 family */ # define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ # define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */ # define KINETIS_SRAM_SIZE (32*1024) /* 64Kb */ @@ -340,6 +345,7 @@ # undef KINETIS_K20 /* Not Kinetis K20 family */ # define KINETIS_K40 1 /* Kinetics K40 family */ # undef KINETIS_K60 /* Not Kinetis K60 family */ +# undef KINETIS_K64 /* Not Kinetis K64 family */ # define KINETIS_FLASH_SIZE (128*1024) /* 128Kb */ # define KINETIS_FLEXMEM_SIZE (128*1024) /* 128Kb */ # define KINETIS_SRAM_SIZE (32*1024) /* 32Kb */ @@ -381,6 +387,7 @@ # undef KINETIS_K20 /* Not Kinetis K20 family */ # define KINETIS_K40 1 /* Kinetics K40 family */ # undef KINETIS_K60 /* Not Kinetis K60 family */ +# undef KINETIS_K64 /* Not Kinetis K64 family */ # define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ # define KINETIS_FLEXMEM_SIZE (256*1024) /* 256Kb */ # define KINETIS_SRAM_SIZE (64*1024) /* 32Kb */ @@ -424,6 +431,7 @@ # undef KINETIS_K20 /* Not Kinetis K20 family */ # define KINETIS_K40 1 /* Kinetics K40 family */ # undef KINETIS_K60 /* Not Kinetis K60 family */ +# undef KINETIS_K64 /* Not Kinetis K64 family */ # define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */ # undef KINETIS_FLEXMEM_SIZE /* No FlexMemory */ # define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */ @@ -465,6 +473,7 @@ # undef KINETIS_K20 /* Not Kinetis K20 family */ # undef KINETIS_K40 /* Not Kinetics K40 family */ # define KINETIS_K60 1 /* Kinetis K60 family */ +# undef KINETIS_K64 /* Not Kinetis K64 family */ # define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ # undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ # undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ @@ -509,6 +518,7 @@ # undef KINETIS_K20 /* Not Kinetis K20 family */ # undef KINETIS_K40 /* Not Kinetics K40 family */ # define KINETIS_K60 1 /* Kinetis K60 family */ +# undef KINETIS_K64 /* Not Kinetis K64 family */ # define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ # define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */ # define KINETIS_FLEXRAM_SIZE (4*1024) /* 32Kb */ @@ -553,6 +563,7 @@ # undef KINETIS_K20 /* Not Kinetis K20 family */ # undef KINETIS_K40 /* Not Kinetics K40 family */ # define KINETIS_K60 1 /* Kinetis K60 family */ +# undef KINETIS_K64 /* Not Kinetis K64 family */ # define KINETIS_FLASH_SIZE (512*1024) /* 256Kb */ # undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ # undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ @@ -598,6 +609,7 @@ # undef KINETIS_K20 /* Not Kinetis K20 family */ # undef KINETIS_K40 /* Not Kinetics K40 family */ # define KINETIS_K60 1 /* Kinetis K60 family */ +# undef KINETIS_K64 /* Not Kinetis K64 family */ # define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ # undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ # undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ @@ -642,6 +654,7 @@ # undef KINETIS_K20 /* Not Kinetis K20 family */ # undef KINETIS_K40 /* Not Kinetics K40 family */ # define KINETIS_K60 1 /* Kinetis K60 family */ +# undef KINETIS_K64 /* Not Kinetis K64 family */ # define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ # define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */ # define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ @@ -686,6 +699,7 @@ # undef KINETIS_K20 /* Not Kinetis K20 family */ # undef KINETIS_K40 /* Not Kinetics K40 family */ # define KINETIS_K60 1 /* Kinetis K60 family */ +# undef KINETIS_K64 /* Not Kinetis K64 family */ # define KINETIS_FLASH_SIZE (512*1024) /* 256Kb */ # undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ # undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ @@ -730,6 +744,7 @@ # undef KINETIS_K20 /* Not Kinetis K20 family */ # undef KINETIS_K40 /* Not Kinetics K40 family */ # define KINETIS_K60 1 /* Kinetis K60 family */ +# undef KINETIS_K64 /* Not Kinetis K64 family */ # define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ # undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ # undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ @@ -774,6 +789,7 @@ # undef KINETIS_K20 /* Not Kinetis K20 family */ # undef KINETIS_K40 /* Not Kinetics K40 family */ # define KINETIS_K60 1 /* Kinetis K60 family */ +# undef KINETIS_K64 /* Not Kinetis K64 family */ # define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ # define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */ # define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ @@ -818,6 +834,7 @@ # undef KINETIS_K20 /* Not Kinetis K20 family */ # undef KINETIS_K40 /* Not Kinetics K40 family */ # define KINETIS_K60 1 /* Kinetis K60 family */ +# undef KINETIS_K64 /* Not Kinetis K64 family */ # define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */ # undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ # undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ @@ -862,6 +879,7 @@ # undef KINETIS_K20 /* Not Kinetis K20 family */ # undef KINETIS_K40 /* Not Kinetics K40 family */ # define KINETIS_K60 1 /* Kinetis K60 family */ +# undef KINETIS_K64 /* Not Kinetis K64 family */ # define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ # undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ # undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ @@ -906,6 +924,7 @@ # undef KINETIS_K20 /* Not Kinetis K20 family */ # undef KINETIS_K40 /* Not Kinetics K40 family */ # define KINETIS_K60 1 /* Kinetis K60 family */ +# undef KINETIS_K64 /* Not Kinetis K64 family */ # define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */ # define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */ # define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ @@ -950,6 +969,7 @@ # undef KINETIS_K20 /* Not Kinetis K20 family */ # undef KINETIS_K40 /* Not Kinetics K40 family */ # define KINETIS_K60 1 /* Kinetis K60 family */ +# undef KINETIS_K64 /* Not Kinetis K64 family */ # define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */ # undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */ # undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */ @@ -990,6 +1010,278 @@ # undef KINETIS_NTAMPER /* No tamper detect */ # define KINETIS_NCRC 1 /* CRC */ +#elif defined(CONFIG_ARCH_CHIP_MK64FN1M0VLL12) +# undef KINETIS_K20 /* Not Kinetics K20 family */ +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# undef KINETIS_K60 /* Not Kinetis K60 family */ +# define KINETIS_K64 1 /* Kinetis K64 family */ +# define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */ +# define KINETIS_FLEXNVM_SIZE (0*1024) /* 0Kb */ +# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ +# define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NUART 6 /* Six UART modues */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 1 /* One CAN controllers */ +# define KINETIS_NI2S 1 /* One I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 2 /* Four 16-bit ADC */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# define KINETIS_NTIMERS8 2 /* Two 8 channel timers */ +# define KINETIS_NTIMERS2 2 /* Two 2 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# define KINETIS_NRNG 1 /* Random number generator */ +# define KINETIS_NMMCAU 1 /* Hardware encryption */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK64FX512VLL12) +# undef KINETIS_K20 /* Not Kinetics K20 family */ +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# undef KINETIS_K60 /* Not Kinetis K60 family */ +# define KINETIS_K64 1 /* Kinetis K64 family */ +# define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */ +# define KINETIS_FLEXNVM_SIZE (0*1024) /* 0Kb */ +# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ +# define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NUART 6 /* Six UART modues */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 1 /* One CAN controllers */ +# define KINETIS_NI2S 1 /* One I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 2 /* Four 16-bit ADC */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# define KINETIS_NTIMERS8 2 /* Two 8 channel timers */ +# define KINETIS_NTIMERS2 2 /* Two 2 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# define KINETIS_NRNG 1 /* Random number generator */ +# define KINETIS_NMMCAU 1 /* Hardware encryption */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK64FX512VDC12) +# undef KINETIS_K20 /* Not Kinetics K20 family */ +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# undef KINETIS_K60 /* Not Kinetis K60 family */ +# define KINETIS_K64 1 /* Kinetis K64 family */ +# define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */ +# define KINETIS_FLEXNVM_SIZE (0*1024) /* 0Kb */ +# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ +# define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NUART 6 /* Six UART modues */ +# define KINETIS_NSPI 3 Three SPI modules +# define KINETIS_NCAN 1 /* One CAN controllers */ +# define KINETIS_NI2S 1 /* One I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 2 /* Four 16-bit ADC */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# define KINETIS_NTIMERS8 2 /* Two 8 channel timers */ +# define KINETIS_NTIMERS2 2 /* Two 2 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# define KINETIS_NRNG 1 /* Random number generator */ +# define KINETIS_NMMCAU 1 /* Hardware encryption */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK64FN1M0VDC12) +# undef KINETIS_K20 /* Not Kinetics K20 family */ +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# undef KINETIS_K60 /* Not Kinetis K60 family */ +# define KINETIS_K64 1 /* Kinetis K64 family */ +# define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */ +# define KINETIS_FLEXNVM_SIZE (0*1024) /* 0Kb */ +# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ +# define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NUART 6 /* Six UART modues */ +# define KINETIS_NSPI 3 Three SPI modules +# define KINETIS_NCAN 1 /* One CAN controllers */ +# define KINETIS_NI2S 1 /* One I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 2 /* Four 16-bit ADC */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# define KINETIS_NTIMERS8 2 /* Two 8 channel timers */ +# define KINETIS_NTIMERS2 2 /* Two 2 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# define KINETIS_NRNG 1 /* Random number generator */ +# define KINETIS_NMMCAU 1 /* Hardware encryption */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK64FX512VLQ12) +# undef KINETIS_K20 /* Not Kinetics K20 family */ +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# undef KINETIS_K60 /* Not Kinetis K60 family */ +# define KINETIS_K64 1 /* Kinetis K64 family */ +# define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */ +# define KINETIS_FLEXNVM_SIZE (0*1024) /* 0Kb */ +# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ +# define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NUART 6 /* Six UART modues */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 1 /* One CAN controllers */ +# define KINETIS_NI2S 1 /* One I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 2 /* Four 16-bit ADC */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# define KINETIS_NTIMERS8 2 /* Two 8 channel timers */ +# define KINETIS_NTIMERS2 2 /* Two 2 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# define KINETIS_NRNG 1 /* Random number generator */ +# define KINETIS_NMMCAU 1 /* Hardware encryption */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK64FN1M0VLQ12) +# undef KINETIS_K20 /* Not Kinetics K20 family */ +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# undef KINETIS_K60 /* Not Kinetis K60 family */ +# define KINETIS_K64 1 /* Kinetis K64 family */ +# define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */ +# define KINETIS_FLEXNVM_SIZE (0*1024) /* 0Kb */ +# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ +# define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NUART 6 /* Six UART modues */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 1 /* One CAN controllers */ +# define KINETIS_NI2S 1 /* One I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 2 /* Four 16-bit ADC */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# define KINETIS_NTIMERS8 2 /* Two 8 channel timers */ +# define KINETIS_NTIMERS2 2 /* Two 2 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# define KINETIS_NRNG 1 /* Random number generator */ +# define KINETIS_NMMCAU 1 /* Hardware encryption */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK64FX512VMD12) +# undef KINETIS_K20 /* Not Kinetics K20 family */ +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# undef KINETIS_K60 /* Not Kinetis K60 family */ +# define KINETIS_K64 1 /* Kinetis K64 family */ +# define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */ +# define KINETIS_FLEXNVM_SIZE (0*1024) /* 0Kb */ +# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ +# define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NUART 6 /* Six UART modues */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 1 /* One CAN controllers */ +# define KINETIS_NI2S 1 /* One I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 2 /* Four 16-bit ADC */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# define KINETIS_NTIMERS8 2 /* Two 8 channel timers */ +# define KINETIS_NTIMERS2 2 /* Two 2 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# define KINETIS_NRNG 1 /* Random number generator */ +# define KINETIS_NMMCAU 1 /* Hardware encryption */ +# define KINETIS_NCRC 1 /* CRC */ + +#elif defined(CONFIG_ARCH_CHIP_MK64FN1M0VMD12) +# undef KINETIS_K20 /* Not Kinetics K20 family */ +# undef KINETIS_K40 /* Not Kinetics K40 family */ +# undef KINETIS_K60 /* Not Kinetis K60 family */ +# define KINETIS_K64 1 /* Kinetis K64 family */ +# define KINETIS_FLASH_SIZE (1024*1024) /* 1Mb */ +# define KINETIS_FLEXNVM_SIZE (0*1024) /* 0Kb */ +# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */ +# define KINETIS_SRAM_SIZE (256*1024) /* 256Kb */ +# define KINETIS_MPU 1 /* Memory protection unit */ +# define KINETIS_EXTBUS 1 /* External bus interface */ +# define KINETIS_NDMACH 16 /* Up to 16 DMA channels */ +# define KINETIS_NENET 1 /* One IEEE 1588 Ethernet controller */ +# define KINETIS_NUSBOTG 1 /* With USB OTG controller */ +# define KINETIS_NUSBDEV 1 /* One USB device controller */ +# define KINETIS_NSDHC 1 /* SD host controller */ +# define KINETIS_NI2C 3 /* Three I2C modules */ +# define KINETIS_NUART 6 /* Six UART modues */ +# define KINETIS_NSPI 3 /* Three SPI modules */ +# define KINETIS_NCAN 1 /* One CAN controllers */ +# define KINETIS_NI2S 1 /* One I2S modules */ +# define KINETIS_NSLCD 1 /* One segment LCD interface (up to 36x8/40x4) */ +# define KINETIS_NADC16 2 /* Four 16-bit ADC */ +# define KINETIS_NCMP 3 /* Three analog comparators */ +# define KINETIS_NDAC6 3 /* Three 6-bit DAC */ +# define KINETIS_NDAC12 2 /* Two 12-bit DAC */ +# define KINETIS_NVREF 1 /* Voltage reference */ +# define KINETIS_NTIMERS8 2 /* Two 8 channel timers */ +# define KINETIS_NTIMERS2 2 /* Two 2 channel timers */ +# define KINETIS_NRTC 1 /* Real time clock */ +# define KINETIS_NRNG 1 /* Random number generator */ +# define KINETIS_NMMCAU 1 /* Hardware encryption */ +# define KINETIS_NCRC 1 /* CRC */ + #else # error "Unsupported Kinetis chip" #endif diff --git a/arch/arm/include/kinetis/irq.h b/arch/arm/include/kinetis/irq.h index 16b59ab8ae96fc4054e91e16ac849c0cb2f2293f..1e45a5b4c63be0f1c6ee3cd1a5009fb165f02885 100644 --- a/arch/arm/include/kinetis/irq.h +++ b/arch/arm/include/kinetis/irq.h @@ -83,7 +83,7 @@ * K20P64M72SF1RM */ -#if defined(CONFIG_ARCH_CHIP_MK20DX256VLH7) +#if defined(CONFIG_ARCH_FAMILY_K20) # define KINETIS_IRQ_DMACH0 (16) /* Vector 16: DMA channel 0 transfer complete */ # define KINETIS_IRQ_DMACH1 (17) /* Vector 17: DMA channel 1 transfer complete */ # define KINETIS_IRQ_DMACH2 (18) /* Vector 18: DMA channel 2 transfer complete */ @@ -162,9 +162,7 @@ * K40P144M100SF2RM */ -#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) || \ - defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100) || \ - defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100) +#elif defined(CONFIG_ARCH_FAMILY_K40) # define KINETIS_IRQ_DMACH0 (16) /* Vector 16: DMA channel 0 transfer complete */ # define KINETIS_IRQ_DMACH1 (17) /* Vector 17: DMA channel 1 transfer complete */ @@ -274,10 +272,7 @@ * K60P144M100SF2RM */ -#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100) || defined(CONFIG_ARCH_CHIP_MK60X256VLQ100) || \ - defined(CONFIG_ARCH_CHIP_MK60N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK60N256VMD100) || \ - defined(CONFIG_ARCH_CHIP_MK60X256VMD100) || defined(CONFIG_ARCH_CHIP_MK60N512VMD100) || \ - defined(CONFIG_ARCH_CHIP_MK60N512VLL100) +#elif defined(CONFIG_ARCH_FAMILY_K60) # define KINETIS_IRQ_DMACH0 (16) /* Vector 16: DMA channel 0 transfer complete */ # define KINETIS_IRQ_DMACH1 (17) /* Vector 17: DMA channel 1 transfer complete */ @@ -383,6 +378,105 @@ # define NR_VECTORS (120) /* 120 vectors */ # define NR_IRQS (108) /* 120 interrupts but 108 IRQ numbers */ +/* K64 Family *********************************************************************** + * + * The memory map for the following parts is defined in NXP document + * K64P144M120SF5RM.pdf + */ + +#elif defined(CONFIG_ARCH_FAMILY_K64) + +# define KINETIS_IRQ_DMACH0 (16) /* Vector 16: DMA channel 0 transfer complete */ +# define KINETIS_IRQ_DMACH1 (17) /* Vector 17: DMA channel 1 transfer complete */ +# define KINETIS_IRQ_DMACH2 (18) /* Vector 18: DMA channel 2 transfer complete */ +# define KINETIS_IRQ_DMACH3 (19) /* Vector 19: DMA channel 3 transfer complete */ +# define KINETIS_IRQ_DMACH4 (20) /* Vector 20: DMA channel 4 transfer complete */ +# define KINETIS_IRQ_DMACH5 (21) /* Vector 21: DMA channel 5 transfer complete */ +# define KINETIS_IRQ_DMACH6 (22) /* Vector 22: DMA channel 6 transfer complete */ +# define KINETIS_IRQ_DMACH7 (23) /* Vector 23: DMA channel 7 transfer complete */ +# define KINETIS_IRQ_DMACH8 (24) /* Vector 24: DMA channel 8 transfer complete */ +# define KINETIS_IRQ_DMACH9 (25) /* Vector 25: DMA channel 9 transfer complete */ +# define KINETIS_IRQ_DMACH10 (26) /* Vector 26: DMA channel 10 transfer complete */ +# define KINETIS_IRQ_DMACH11 (27) /* Vector 27: DMA channel 11 transfer complete */ +# define KINETIS_IRQ_DMACH12 (28) /* Vector 28: DMA channel 12 transfer complete */ +# define KINETIS_IRQ_DMACH13 (29) /* Vector 29: DMA channel 13 transfer complete */ +# define KINETIS_IRQ_DMACH14 (30) /* Vector 30: DMA channel 14 transfer complete */ +# define KINETIS_IRQ_DMACH15 (31) /* Vector 31: DMA channel 15 transfer complete */ +# define KINETIS_IRQ_DMAERR (32) /* Vector 32: DMA error interrupt channels 0-15 */ +# define KINETIS_IRQ_MCM (33) /* Vector 33: MCM Normal interrupt */ +# define KINETIS_IRQ_FLASHCC (34) /* Vector 34: Flash memory command complete */ +# define KINETIS_IRQ_FLASHRC (35) /* Vector 35: Flash memory read collision */ +# define KINETIS_IRQ_SMCLVD (36) /* Vector 36: Mode Controller low-voltage + * detect, low-voltage warning */ +# define KINETIS_IRQ_LLWU (37) /* Vector 37: LLWU Normal Low Leakage Wakeup */ +# define KINETIS_IRQ_WDOG (38) /* Vector 38: Watchdog */ +# define KINETIS_IRQ_RNGB (39) /* Vector 39: Random number generator */ +# define KINETIS_IRQ_I2C0 (40) /* Vector 40: I2C0 */ +# define KINETIS_IRQ_I2C1 (41) /* Vector 41: I2C1 */ +# define KINETIS_IRQ_SPI0 (42) /* Vector 42: SPI0 all sources */ +# define KINETIS_IRQ_SPI1 (43) /* Vector 43: SPI1 all sources */ +# define KINETIS_IRQ_I2S0 (44) /* Vector 44: Transmit */ +# define KINETIS_IRQ_I2S1 (45) /* Vector 45: Transmit */ + /* Vector 46: Reserved */ +# define KINETIS_IRQ_UART0S (47) /* Vector 47: UART0 status */ +# define KINETIS_IRQ_UART0E (48) /* Vector 48: UART0 error */ +# define KINETIS_IRQ_UART1S (49) /* Vector 49: UART1 status */ +# define KINETIS_IRQ_UART1E (50) /* Vector 50: UART1 error */ +# define KINETIS_IRQ_UART2S (51) /* Vector 51: UART2 status */ +# define KINETIS_IRQ_UART2E (52) /* Vector 52: UART2 error */ +# define KINETIS_IRQ_UART3S (53) /* Vector 53: UART3 status */ +# define KINETIS_IRQ_UART3E (54) /* Vector 54: UART3 error */ +# define KINETIS_IRQ_ADC0 (55) /* Vector 55: ADC0 */ +# define KINETIS_IRQ_CMP0 (56) /* Vector 56: CMP0 */ +# define KINETIS_IRQ_CMP1 (57) /* Vector 57: CMP1 */ +# define KINETIS_IRQ_FTM0 (58) /* Vector 58: FTM0 all sources */ +# define KINETIS_IRQ_FTM1 (59) /* Vector 59: FTM1 all sources */ +# define KINETIS_IRQ_FTM2 (60) /* Vector 60: FTM2 all sources */ +# define KINETIS_IRQ_CMT (61) /* Vector 61: CMT */ +# define KINETIS_IRQ_RTC0 (62) /* Vector 62: RTC alarm interrupt */ +# define KINETIS_IRQ_RTC1 (63) /* Vector 63: RTC seconds interrupt */ +# define KINETIS_IRQ_PITCH0 (64) /* Vector 64: PIT channel 0 */ +# define KINETIS_IRQ_PITCH1 (65) /* Vector 65: PIT channel 1 */ +# define KINETIS_IRQ_PITCH2 (66) /* Vector 66: PIT channel 2 */ +# define KINETIS_IRQ_PITCH3 (67) /* Vector 67: PIT channel 3 */ +# define KINETIS_IRQ_PDB (68) /* Vector 68: PDB */ +# define KINETIS_IRQ_USBOTG (69) /* Vector 68: USB OTG */ +# define KINETIS_IRQ_USBCD (70) /* Vector 70: USB charger detect */ + /* Vector 71: Reserved */ +# define KINETIS_IRQ_DAC0 (72) /* Vector 72: DAC0 */ +# define KINETIS_IRQ_MCG (73) /* Vector 73: MCG */ +# define KINETIS_IRQ_LPT (74) /* Vector 74: Low power timer */ +# define KINETIS_IRQ_PORTA (75) /* Vector 75: Pin detect port A */ +# define KINETIS_IRQ_PORTB (76) /* Vector 76: Pin detect port B */ +# define KINETIS_IRQ_PORTC (77) /* Vector 77: Pin detect port C */ +# define KINETIS_IRQ_PORTD (78) /* Vector 78: Pin detect port D */ +# define KINETIS_IRQ_PORTE (79) /* Vector 79: Pin detect port E */ +# define KINETIS_IRQ_SOFTWARE (80) /* Vector 80: Software interrupt */ +# define KINETIS_IRQ_SPI2 (81) /* Vector 81: SPI2 all sources */ +# define KINETIS_IRQ_UART4S (82) /* Vector 82: UART4 status */ +# define KINETIS_IRQ_UART4E (83) /* Vector 83: UART4 error */ +# define KINETIS_IRQ_UART5S (84) /* Vector 84: UART5 status */ +# define KINETIS_IRQ_UART5E (85) /* Vector 85: UART5 error */ +# define KINETIS_IRQ_CMP2 (86) /* Vector 86: CMP2 */ +# define KINETIS_IRQ_FTM3 (87) /* Vector 87: FTM3 all sources */ +# define KINETIS_IRQ_DAC1 (88) /* Vector 88: DAC1 */ +# define KINETIS_IRQ_ADC1 (89) /* Vector 89: ADC1 */ +# define KINETIS_IRQ_I2C2 (90) /* Vector 90: I2C2 */ +# define KINETIS_IRQ_CAN0MB (91) /* Vector 91: CAN0 OR'ed Message buffer (0-15) */ +# define KINETIS_IRQ_CAN0BO (92) /* Vector 92: CAN0 Bus Off */ +# define KINETIS_IRQ_CAN0ERR (93) /* Vector 93: CAN0 Error */ +# define KINETIS_IRQ_CAN0TW (94) /* Vector 94: CAN0 Transmit Warning */ +# define KINETIS_IRQ_CAN0RW (95) /* Vector 95: CAN0 Receive Warning */ +# define KINETIS_IRQ_CAN0WU (96) /* Vector 96: CAN0 Wake UP */ +# define KINETIS_IRQ_SDHC (97) /* Vector 97: SDHC */ +# define KINETIS_IRQ_EMACTMR (98) /* Vector 91: Ethernet MAC IEEE 1588 timer interrupt */ +# define KINETIS_IRQ_EMACTX (99) /* Vector 92: Ethernet MAC transmit interrupt */ +# define KINETIS_IRQ_EMACRX (100) /* Vector 93: Ethernet MAC receive interrupt */ +# define KINETIS_IRQ_EMACMISC (101) /* Vector 94: Ethernet MAC error and misc interrupt */ + +# define NR_VECTORS (102) /* 102 vectors */ +# define NR_IRQS (102) /* 85 interrupts but 102 IRQ numbers */ + #else /* The interrupt vectors for other parts are defined in other documents and may or * may not be the same as above (the family members are all very similar) This diff --git a/arch/arm/src/common/up_checkstack.c b/arch/arm/src/common/up_checkstack.c index 55f89388e3ee983d72ce5ccabdf23acb71677733..f6b4034cbcb588c62a5e1d970d956c5573b9667d 100644 --- a/arch/arm/src/common/up_checkstack.c +++ b/arch/arm/src/common/up_checkstack.c @@ -84,7 +84,13 @@ static size_t do_stackcheck(uintptr_t alloc, size_t size) FAR uint32_t *ptr; size_t mark; + if (size == 0) + { + return 0; + } + /* Get aligned addresses of the top and bottom of the stack */ + #ifdef CONFIG_TLS /* Skip over the TLS data structure at the bottom of the stack */ @@ -122,7 +128,8 @@ static size_t do_stackcheck(uintptr_t alloc, size_t size) #if 0 if (mark + 16 > nwords) { - int i, j; + int i; + int j; ptr = (FAR uint32_t *)start; for (i = 0; i < size; i += 4*64) diff --git a/arch/arm/src/efm32/efm32_irq.c b/arch/arm/src/efm32/efm32_irq.c index 63fa4b18ec7bc2e873cfeb0a8a91215691797480..63a82b194ca197d4eb01c373a90e562667a0e7e2 100644 --- a/arch/arm/src/efm32/efm32_irq.c +++ b/arch/arm/src/efm32/efm32_irq.c @@ -251,61 +251,25 @@ static inline void efm32_prioritize_syscall(int priority) static int efm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, uintptr_t offset) { + int n; + DEBUGASSERT(irq >= EFM32_IRQ_NMI && irq < NR_IRQS); - /* Check for external interrupt or (a second level GPIO interrupt) */ + /* Check for external interrupt or a second level GPIO interrupt */ if (irq >= EFM32_IRQ_INTERRUPTS) { - /* Is this an external interrupt? */ - if (irq < NR_VECTORS) { - /* Yes.. We have support implemented for vectors 0-95 */ - - DEBUGASSERT(irq < (EFM32_IRQ_INTERRUPTS + 96)); - -#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 32) - /* Check for vectors 0-31 */ - - if (irq < EFM32_IRQ_INTERRUPTS + 32) -#endif - { - *regaddr = (NVIC_IRQ0_31_ENABLE + offset); - *bit = 1 << (irq - EFM32_IRQ_INTERRUPTS); - } -#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 32) - /* Yes.. Check for vectors 32-63 */ + n = irq - EFM32_IRQ_INTERRUPTS; + *regaddr = NVIC_IRQ_ENABLE(n) + offset; - else -#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 64) - if (irq < EFM32_IRQ_INTERRUPTS + 64) -#endif + while (n >= 32) { - *regaddr = (NVIC_IRQ32_63_ENABLE + offset); - *bit = 1 << (irq - EFM32_IRQ_INTERRUPTS - 32); + n -= 32; } -#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 64) - /* Yes.. Check for vectors 64-95 */ - - else -#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 96) - /* Yes.. Check for vectors 64-95 */ - if (irq < NR_VECTORS) -#endif - { - *regaddr = (NVIC_IRQ64_95_ENABLE + offset); - *bit = 1 << (irq - EFM32_IRQ_INTERRUPTS - 64); - } -#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 96) - else - { - return -EINVAL; /* We should never get here */ - } -#endif -#endif -#endif + *bit = 1 << n; } else { @@ -356,16 +320,14 @@ void up_irqinitialize(void) { uint32_t regaddr; int num_priority_registers; + int i; /* Disable all interrupts */ - putreg32(0, NVIC_IRQ0_31_ENABLE); -#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 32) - putreg32(0, NVIC_IRQ32_63_ENABLE); -#if NR_VECTORS >= (EFM32_IRQ_INTERRUPTS + 64) - putreg32(0, NVIC_IRQ64_95_ENABLE); -#endif -#endif + for (i = 0; i < NR_VECTORS - EFM32_IRQ_INTERRUPTS; i += 32) + { + putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); + } #if defined(CONFIG_STACK_COLORATION) && CONFIG_ARCH_INTERRUPTSTACK > 3 /* Colorize the interrupt stack for debug purposes */ diff --git a/arch/arm/src/kinetis/Kconfig b/arch/arm/src/kinetis/Kconfig index 5710c2d32ce6c7e4067fcc53e430f3aa734dde0b..55a693021108ba79bc3e62ad876d937950ee6284 100644 --- a/arch/arm/src/kinetis/Kconfig +++ b/arch/arm/src/kinetis/Kconfig @@ -98,6 +98,34 @@ config ARCH_CHIP_MK60X256VMD100 bool "MK60X256VMD100" select ARCH_FAMILY_K60 +config ARCH_CHIP_MK64FN1M0VLL12 + bool "MK64FN1M0VLL12" + select ARCH_FAMILY_K64 + +config ARCH_CHIP_MK64FX512VLL12 + bool "MK64FX512VLL12" + select ARCH_FAMILY_K64 + +config ARCH_CHIP_MK64FX512VDC12 + bool "MK64FX512VDC12" + select ARCH_FAMILY_K64 + +config ARCH_CHIP_MK64FN1M0VDC12 + bool "MK64FN1M0VDC12" + select ARCH_FAMILY_K64 + +config ARCH_CHIP_MK64FX512VLQ12 + bool "MK64FX512VLQ12" + select ARCH_FAMILY_K64 + +config ARCH_CHIP_MK64FX512VMD12 + bool "MK64FX512VMD12" + select ARCH_FAMILY_K64 + +config ARCH_CHIP_MK64FN1M0VMD12 + bool "MK64FN1M0VMD12" + select ARCH_FAMILY_K64 + endchoice # Chip families @@ -114,6 +142,10 @@ config ARCH_FAMILY_K60 bool default n +config ARCH_FAMILY_K64 + bool + default n + menu "Kinetis Peripheral Support" config KINETIS_TRACE diff --git a/arch/arm/src/kinetis/chip.h b/arch/arm/src/kinetis/chip.h index 0ed152bac2f52203fe3ac39ebe4a6a48b6eac622..26fa7e38a0daaed85b59748db1c91cf6a1ba7ac1 100644 --- a/arch/arm/src/kinetis/chip.h +++ b/arch/arm/src/kinetis/chip.h @@ -47,7 +47,7 @@ */ #include -#include "kinetis_memorymap.h" +#include "chip/kinetis_memorymap.h" /************************************************************************************ * Pre-processor Definitions diff --git a/arch/arm/src/kinetis/kinetis_adc.h b/arch/arm/src/kinetis/chip/kinetis_adc.h similarity index 93% rename from arch/arm/src/kinetis/kinetis_adc.h rename to arch/arm/src/kinetis/chip/kinetis_adc.h index a17aa06c7f4274ca8a612e933cafec3c43c9bd71..6b3b74fa9c32c51efdddcaa71d5b4bd7bbbbe0c7 100644 --- a/arch/arm/src/kinetis/kinetis_adc.h +++ b/arch/arm/src/kinetis/chip/kinetis_adc.h @@ -1,7 +1,7 @@ /******************************************************************************************** - * arch/arm/src/kinetis/kinetis_adc.h + * arch/arm/src/kinetis/chip/kinetis_adc.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ********************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_ADC_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_ADC_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_ADC_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_ADC_H /******************************************************************************************** * Included Files @@ -70,7 +70,9 @@ #define KINETIS_ADC_CLP2_OFFSET 0x0044 /* ADC plus-side general calibration value register */ #define KINETIS_ADC_CLP1_OFFSET 0x0048 /* ADC plus-side general calibration value register */ #define KINETIS_ADC_CLP0_OFFSET 0x004c /* ADC plus-side general calibration value register */ -#define KINETIS_ADC_PGA_OFFSET 0x0050 /* ADC PGA register */ +#ifndef KINETIS_K64 +# define KINETIS_ADC_PGA_OFFSET 0x0050 /* ADC PGA register */ +#endif #define KINETIS_ADC_CLMD_OFFSET 0x0054 /* ADC minus-side general calibration value register */ #define KINETIS_ADC_CLMS_OFFSET 0x0058 /* ADC minus-side general calibration value register */ #define KINETIS_ADC_CLM4_OFFSET 0x005c /* ADC minus-side general calibration value register */ @@ -80,7 +82,7 @@ #define KINETIS_ADC_CLM0_OFFSET 0x006c /* ADC minus-side general calibration value register */ /* Register Addresses ***********************************************************************/ -# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */ +# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */ #define KINETIS_ADC0_SC1A (KINETIS_ADC0_BASE+KINETIS_ADC_SC1A_OFFSET) #define KINETIS_ADC0_SC1B (KINETIS_ADC0_BASE+KINETIS_ADC_SC1B_OFFSET) @@ -102,7 +104,9 @@ #define KINETIS_ADC0_CLP2 (KINETIS_ADC0_BASE+KINETIS_ADC_CLP2_OFFSET) #define KINETIS_ADC0_CLP1 (KINETIS_ADC0_BASE+KINETIS_ADC_CLP1_OFFSET) #define KINETIS_ADC0_CLP0 (KINETIS_ADC0_BASE+KINETIS_ADC_CLP0_OFFSET) -#define KINETIS_ADC0_PGA (KINETIS_ADC0_BASE+KINETIS_ADC_PGA_OFFSET) +#ifndef KINETIS_K64 +# define KINETIS_ADC0_PGA (KINETIS_ADC0_BASE+KINETIS_ADC_PGA_OFFSET) +#endif #define KINETIS_ADC0_CLMD (KINETIS_ADC0_BASE+KINETIS_ADC_CLMD_OFFSET) #define KINETIS_ADC0_CLMS (KINETIS_ADC0_BASE+KINETIS_ADC_CLMS_OFFSET) #define KINETIS_ADC0_CLM4 (KINETIS_ADC0_BASE+KINETIS_ADC_CLM4_OFFSET) @@ -131,7 +135,9 @@ #define KINETIS_ADC1_CLP2 (KINETIS_ADC1_BASE+KINETIS_ADC_CLP2_OFFSET) #define KINETIS_ADC1_CLP1 (KINETIS_ADC1_BASE+KINETIS_ADC_CLP1_OFFSET) #define KINETIS_ADC1_CLP0 (KINETIS_ADC1_BASE+KINETIS_ADC_CLP0_OFFSET) -#define KINETIS_ADC1_PGA (KINETIS_ADC1_BASE+KINETIS_ADC_PGA_OFFSET) +#ifndef KINETIS_K64 +# define KINETIS_ADC1_PGA (KINETIS_ADC1_BASE+KINETIS_ADC_PGA_OFFSET) +#endif #define KINETIS_ADC1_CLMD (KINETIS_ADC1_BASE+KINETIS_ADC_CLMD_OFFSET) #define KINETIS_ADC1_CLMS (KINETIS_ADC1_BASE+KINETIS_ADC_CLMS_OFFSET) #define KINETIS_ADC1_CLM4 (KINETIS_ADC1_BASE+KINETIS_ADC_CLM4_OFFSET) @@ -272,22 +278,26 @@ #define ADC_CLP0_MASK (0x3f) /* Bits 0-5: Calibration value */ /* ADC PGA register */ + +#ifndef KINETIS_K64 /* Bits 0-15: Reserved */ -#define ADC_PGA_PGAG_SHIFT (16) /* Bits 16-19: PGA gain setting*/ -#define ADC_PGA_PGAG_MASK (15 << ADC_PGA_PGAG_SHIFT) -# define ADC_PGA_PGAG_1 (0 << ADC_PGA_PGAG_SHIFT) -# define ADC_PGA_PGAG_2 (1 << ADC_PGA_PGAG_SHIFT) -# define ADC_PGA_PGAG_4 (2 << ADC_PGA_PGAG_SHIFT) -# define ADC_PGA_PGAG_8 (3 << ADC_PGA_PGAG_SHIFT) -# define ADC_PGA_PGAG_16 (4 << ADC_PGA_PGAG_SHIFT) -# define ADC_PGA_PGAG_32 (5 << ADC_PGA_PGAG_SHIFT) -# define ADC_PGA_PGAG_64 (6 << ADC_PGA_PGAG_SHIFT) -#ifdef KINETIS_K40 -# define ADC_PGA_PGALP (1 << 20) /* Bit 20: PGA low-power mode control */ -#endif +# define ADC_PGA_PGAG_SHIFT (16) /* Bits 16-19: PGA gain setting*/ +# define ADC_PGA_PGAG_MASK (15 << ADC_PGA_PGAG_SHIFT) +# define ADC_PGA_PGAG_1 (0 << ADC_PGA_PGAG_SHIFT) +# define ADC_PGA_PGAG_2 (1 << ADC_PGA_PGAG_SHIFT) +# define ADC_PGA_PGAG_4 (2 << ADC_PGA_PGAG_SHIFT) +# define ADC_PGA_PGAG_8 (3 << ADC_PGA_PGAG_SHIFT) +# define ADC_PGA_PGAG_16 (4 << ADC_PGA_PGAG_SHIFT) +# define ADC_PGA_PGAG_32 (5 << ADC_PGA_PGAG_SHIFT) +# define ADC_PGA_PGAG_64 (6 << ADC_PGA_PGAG_SHIFT) +# ifdef KINETIS_K40 +# define ADC_PGA_PGALP (1 << 20) /* Bit 20: PGA low-power mode control */ +# endif /* Bits 21-22: Reserved */ -#define ADC_PGA_PGAEN (1 << 23) /* Bit 23: PGA enable*/ +# define ADC_PGA_PGAEN (1 << 23) /* Bit 23: PGA enable*/ /* Bits 24-31: Reserved */ +#endif + /* ADC minus-side general calibration value registers */ #define ADC_CLMD_MASK (0x3f) /* Bits 0-5: Calibration value */ @@ -310,4 +320,4 @@ * Public Functions ********************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_ADC_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_ADC_H */ diff --git a/arch/arm/src/kinetis/kinetis_aips.h b/arch/arm/src/kinetis/chip/kinetis_aips.h similarity index 87% rename from arch/arm/src/kinetis/kinetis_aips.h rename to arch/arm/src/kinetis/chip/kinetis_aips.h index 8f460567f76125052a24664fdc02843624729dba..a8050fb61397771f32b90c52fe0387920e39f285 100644 --- a/arch/arm/src/kinetis/kinetis_aips.h +++ b/arch/arm/src/kinetis/chip/kinetis_aips.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/kinetis/kinetis_aips.h + * arch/arm/src/kinetis/chip/kinetis_aips.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_AIPS_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_AIPS_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_AIPS_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_AIPS_H /************************************************************************************ * Included Files @@ -68,6 +68,9 @@ #define KINETIS_AIPS_PACRN_OFFSET 0x0064 /* Peripheral Access Control Register */ #define KINETIS_AIPS_PACRO_OFFSET 0x0068 /* Peripheral Access Control Register */ #define KINETIS_AIPS_PACRP_OFFSET 0x006c /* Peripheral Access Control Register */ +#ifdef KINETIS_K64 +# define KINETIS_AIPS_PACRU_OFFSET 0x0080 /* Peripheral Access Control Register */ +#endif /* Register Addresses ***************************************************************/ @@ -88,24 +91,30 @@ #define KINETIS_AIPS0_PACRN (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRN_OFFSET) #define KINETIS_AIPS0_PACRO (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRO_OFFSET) #define KINETIS_AIPS0_PACRP (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRP_OFFSET) - -#define KINETIS_AIPS1_MPRA (KINETIS_AIPS0_BASE+KINETIS_AIPS_MPRA_OFFSET) -#define KINETIS_AIPS1_PACRA (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRA_OFFSET) -#define KINETIS_AIPS1_PACRB (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRB_OFFSET) -#define KINETIS_AIPS1_PACRC (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRC_OFFSET) -#define KINETIS_AIPS1_PACRD (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRD_OFFSET) -#define KINETIS_AIPS1_PACRE (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRE_OFFSET) -#define KINETIS_AIPS1_PACRF (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRF_OFFSET) -#define KINETIS_AIPS1_PACRG (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRG_OFFSET) -#define KINETIS_AIPS1_PACRH (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRH_OFFSET) -#define KINETIS_AIPS1_PACRI (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRI_OFFSET) -#define KINETIS_AIPS1_PACRJ (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRJ_OFFSET) -#define KINETIS_AIPS1_PACRK (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRK_OFFSET) -#define KINETIS_AIPS1_PACRL (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRL_OFFSET) -#define KINETIS_AIPS1_PACRM (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRM_OFFSET) -#define KINETIS_AIPS1_PACRN (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRN_OFFSET) -#define KINETIS_AIPS1_PACRO (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRO_OFFSET) -#define KINETIS_AIPS1_PACRP (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRP_OFFSET) +#ifdef KINETIS_K64 +# define KINETIS_AIPS0_PACRU (KINETIS_AIPS0_BASE+KINETIS_AIPS_PACRU_OFFSET) +#endif + +#define KINETIS_AIPS1_MPRA (KINETIS_AIPS1_BASE+KINETIS_AIPS_MPRA_OFFSET) +#define KINETIS_AIPS1_PACRA (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRA_OFFSET) +#define KINETIS_AIPS1_PACRB (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRB_OFFSET) +#define KINETIS_AIPS1_PACRC (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRC_OFFSET) +#define KINETIS_AIPS1_PACRD (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRD_OFFSET) +#define KINETIS_AIPS1_PACRE (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRE_OFFSET) +#define KINETIS_AIPS1_PACRF (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRF_OFFSET) +#define KINETIS_AIPS1_PACRG (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRG_OFFSET) +#define KINETIS_AIPS1_PACRH (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRH_OFFSET) +#define KINETIS_AIPS1_PACRI (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRI_OFFSET) +#define KINETIS_AIPS1_PACRJ (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRJ_OFFSET) +#define KINETIS_AIPS1_PACRK (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRK_OFFSET) +#define KINETIS_AIPS1_PACRL (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRL_OFFSET) +#define KINETIS_AIPS1_PACRM (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRM_OFFSET) +#define KINETIS_AIPS1_PACRN (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRN_OFFSET) +#define KINETIS_AIPS1_PACRO (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRO_OFFSET) +#define KINETIS_AIPS1_PACRP (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRP_OFFSET) +#ifdef KINETIS_K64 +# define KINETIS_AIPS1_PACRU (KINETIS_AIPS1_BASE+KINETIS_AIPS_PACRU_OFFSET) +#endif /* Register Bit Definitions *********************************************************/ @@ -205,4 +214,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_AIPS_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_AIPS_H */ diff --git a/arch/arm/src/kinetis/kinetis_axbs.h b/arch/arm/src/kinetis/chip/kinetis_axbs.h similarity index 98% rename from arch/arm/src/kinetis/kinetis_axbs.h rename to arch/arm/src/kinetis/chip/kinetis_axbs.h index bf8543d4dac5a5dc5b13a4b110e447483d1dcdb7..7aab308593c3a3b56a32ef8c9703f55e4b9cec92 100644 --- a/arch/arm/src/kinetis/kinetis_axbs.h +++ b/arch/arm/src/kinetis/chip/kinetis_axbs.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/kinetis/kinetis_axbs.h + * arch/arm/src/kinetis/chip/kinetis_axbs.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_AXBS_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_AXBS_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_AXBS_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_AXBS_H /************************************************************************************ * Included Files @@ -248,4 +248,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_AXBS_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_AXBS_H */ diff --git a/arch/arm/src/kinetis/kinetis_cmp.h b/arch/arm/src/kinetis/chip/kinetis_cmp.h similarity index 96% rename from arch/arm/src/kinetis/kinetis_cmp.h rename to arch/arm/src/kinetis/chip/kinetis_cmp.h index 822b7a339f5de9603af3e3236f03d1e5b47068ba..09e9eb19f6a9846b58fb0be5f686a1c0c49da08f 100644 --- a/arch/arm/src/kinetis/kinetis_cmp.h +++ b/arch/arm/src/kinetis/chip/kinetis_cmp.h @@ -1,7 +1,7 @@ /******************************************************************************************** - * arch/arm/src/kinetis/kinetis_cmp.h + * arch/arm/src/kinetis/chip/kinetis_cmp.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ********************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_CMP_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_CMP_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_CMP_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_CMP_H /******************************************************************************************** * Included Files @@ -172,7 +172,9 @@ # define CMP_MUXCR_PSEL_IN5 (5 << CMP_MUXCR_PSEL_SHIFT) # define CMP_MUXCR_PSEL_IN6 (6 << CMP_MUXCR_PSEL_SHIFT) # define CMP_MUXCR_PSEL_IN7 (7 << CMP_MUXCR_PSEL_SHIFT) -#define CMP_MUXCR_MEN (1 << 6) /* Bit 6: MMUX Enable */ +#ifndef KINETIS_K64 +# define CMP_MUXCR_MEN (1 << 6) /* Bit 6: MMUX Enable */ +#endif #define CMP_MUXCR_PEN (1 << 7) /* Bit 7: PMUX Enable */ /******************************************************************************************** @@ -187,4 +189,4 @@ * Public Functions ********************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_CMP_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_CMP_H */ diff --git a/arch/arm/src/kinetis/kinetis_cmt.h b/arch/arm/src/kinetis/chip/kinetis_cmt.h similarity index 96% rename from arch/arm/src/kinetis/kinetis_cmt.h rename to arch/arm/src/kinetis/chip/kinetis_cmt.h index c3c47bb6761254a0ce4c86484a43e41809433cdf..e86720db91e02a4d55df9c9baec355c9a51f152f 100644 --- a/arch/arm/src/kinetis/kinetis_cmt.h +++ b/arch/arm/src/kinetis/chip/kinetis_cmt.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/kinetis/kinetis_cmt.h + * arch/arm/src/kinetis/chip/kinetis_cmt.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_CMT_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_CMT_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_CMT_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_CMT_H /************************************************************************************ * Included Files @@ -135,4 +135,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_CMT_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_CMT_H */ diff --git a/arch/arm/src/kinetis/kinetis_crc.h b/arch/arm/src/kinetis/chip/kinetis_crc.h similarity index 85% rename from arch/arm/src/kinetis/kinetis_crc.h rename to arch/arm/src/kinetis/chip/kinetis_crc.h index 7b590cf3a9a0c39374982f0c8b747da54bb71ccf..d2f0fc7fddb10ecae0286603b9d50c7f4139477f 100644 --- a/arch/arm/src/kinetis/kinetis_crc.h +++ b/arch/arm/src/kinetis/chip/kinetis_crc.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/kinetis/kinetis_crc.h + * arch/arm/src/kinetis/chip/kinetis_crc.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_CRC_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_CRC_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_CRC_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_CRC_H /************************************************************************************ * Included Files @@ -52,13 +52,13 @@ /* Register Offsets *****************************************************************/ -#define KINETIS_CRC_CRC_OFFSET 0x0000 /* CRC Data Register */ +#define KINETIS_CRC_DATA_OFFSET 0x0000 /* CRC Data Register */ #define KINETIS_CRC_GPOLY_OFFSET 0x0004 /* CRC Polynomial Register */ #define KINETIS_CRC_CTRL_OFFSET 0x0008 /* CRC Control Register */ /* Register Addresses ***************************************************************/ -#define KINETIS_CRC_CRC (KINETIS_CRC_BASE+KINETIS_CRC_CRC_OFFSET) +#define KINETIS_CRC_DATA (KINETIS_CRC_BASE+KINETIS_CRC_DATA_OFFSET) #define KINETIS_CRC_GPOLY (KINETIS_CRC_BASE+KINETIS_CRC_GPOLY_OFFSET) #define KINETIS_CRC_CTRL (KINETIS_CRC_BASE+KINETIS_CRC_CTRL_OFFSET) @@ -66,14 +66,14 @@ /* CRC Data Register (32-bit) */ -#define CRC_CRC_LL_SHIFT (0) /* Bits 0-7: CRC Low Lower Byte */ -#define CRC_CRC_LL_MASK (0xff << CRC_CRC_LL_SHIFT) -#define CRC_CRC_LU_SHIFT (8) /* Bits 8-15: CRC Low Upper Byte */ -#define CRC_CRC_LU_MASK (0xff << CRC_CRC_LU_SHIFT) -#define CRC_CRC_HL_SHIFT (16) /* Bits 16-23: CRC High Lower Byte */ -#define CRC_CRC_HL_MASK (0xff << CRC_CRC_HL_SHIFT) -#define CRC_CRC_HU_SHIFT (24) /* Bits 24-31: CRC High Upper Byte */ -#define CRC_CRC_HU_MASK (0xff << CRC_CRC_HU_SHIFT) +#define CRC_DATA_LL_SHIFT (0) /* Bits 0-7: CRC Low Lower Byte */ +#define CRC_DATA_LL_MASK (0xff << CRC_DATA_LL_SHIFT) +#define CRC_DATA_LU_SHIFT (8) /* Bits 8-15: CRC Low Upper Byte */ +#define CRC_DATA_LU_MASK (0xff << CRC_DATA_LU_SHIFT) +#define CRC_DATA_HL_SHIFT (16) /* Bits 16-23: CRC High Lower Byte */ +#define CRC_DATA_HL_MASK (0xff << CRC_DATA_HL_SHIFT) +#define CRC_DATA_HU_SHIFT (24) /* Bits 24-31: CRC High Upper Byte */ +#define CRC_DATA_HU_MASK (0xff << CRC_DATA_HU_SHIFT) /* CRC Polynomial Register */ @@ -114,4 +114,4 @@ ************************************************************************************/ #endif /* KINETIS_NCRC && KINETIS_NCRC > 0 */ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_CRC_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_CRC_H */ diff --git a/arch/arm/src/kinetis/kinetis_dac.h b/arch/arm/src/kinetis/chip/kinetis_dac.h similarity index 98% rename from arch/arm/src/kinetis/kinetis_dac.h rename to arch/arm/src/kinetis/chip/kinetis_dac.h index 5c3b5c0c037503fc669c2427f5581f6b2322285d..bf2184382632158f1270fec96d536a0e9ff363d7 100644 --- a/arch/arm/src/kinetis/kinetis_dac.h +++ b/arch/arm/src/kinetis/chip/kinetis_dac.h @@ -1,7 +1,7 @@ /******************************************************************************************** - * arch/arm/src/kinetis/kinetis_dac.h + * arch/arm/src/kinetis/chip/kinetis_dac.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ********************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_DACE_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_DACE_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DAC_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DAC_H /******************************************************************************************** * Included Files @@ -232,4 +232,4 @@ * Public Functions ********************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_DACE_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DAC_H */ diff --git a/arch/arm/src/kinetis/kinetis_dma.h b/arch/arm/src/kinetis/chip/kinetis_dma.h similarity index 96% rename from arch/arm/src/kinetis/kinetis_dma.h rename to arch/arm/src/kinetis/chip/kinetis_dma.h index 9876a46a0f0fdc794f55676c284e2f446ea5dd8a..aec14d32f4fd5d7e88adf8082560486bbd608345 100644 --- a/arch/arm/src/kinetis/kinetis_dma.h +++ b/arch/arm/src/kinetis/chip/kinetis_dma.h @@ -1,7 +1,7 @@ /**************************************************************************************************** - * arch/arm/src/kinetis/kinetis_dma.h + * arch/arm/src/kinetis/chip/kinetis_dma.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ****************************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_DMA_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_DMA_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DMA_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DMA_H /**************************************************************************************************** * Included Files @@ -83,18 +83,20 @@ #define KINETIS_DMA_DCHPRI13_OFFSET 0x010e /* Channel 13 Priority Register */ #define KINETIS_DMA_DCHPRI12_OFFSET 0x010f /* Channel 12 Priority Register */ -#define KINETIS_DMA_TCD_OFFSET(n) (0x0000+((n) << 5)) -#define KINETIS_DMA_TCD_SADDR_OFFSET 0x0000 /* TCD Source Address */ -#define KINETIS_DMA_TCD_SOFF_OFFSET 0x0004 /* TCD Signed Source Address Offset */ -#define KINETIS_DMA_TCD_ATTR_OFFSET 0x0006 /* TCD Transfer Attributes */ -#define KINETIS_DMA_TCD_NBYTES_OFFSET 0x0008 /* TCD Minor Byte Count */ -#define KINETIS_DMA_TCD_SLAST_OFFSET 0x000c /* TCD Last Source Address Adjustment */ -#define KINETIS_DMA_TCD_DADDR_OFFSET 0x0010 /* TCD Destination Address */ -#define KINETIS_DMA_TCD_DOFF_OFFSET 0x0014 /* TCD Signed Destination Address Offset */ -#define KINETIS_DMA_TCD_CITER_OFFSET 0x0016 /* TCD Current Minor Loop Link, Major Loop Count */ -#define KINETIS_DMA_TCD_DLASTSGA_OFFSET 0x0018 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ -#define KINETIS_DMA_TCD_CSR_OFFSET 0x001c /* TCD Control and Status */ -#define KINETIS_DMA_TCD_BITER_OFFSET 0x001e /* TCD Beginning Minor Loop Link, Major Loop Count */ +#ifndef KINETIS_K64 +# define KINETIS_DMA_TCD_OFFSET(n) (0x0000+((n) << 5)) +# define KINETIS_DMA_TCD_SADDR_OFFSET 0x0000 /* TCD Source Address */ +# define KINETIS_DMA_TCD_SOFF_OFFSET 0x0004 /* TCD Signed Source Address Offset */ +# define KINETIS_DMA_TCD_ATTR_OFFSET 0x0006 /* TCD Transfer Attributes */ +# define KINETIS_DMA_TCD_NBYTES_OFFSET 0x0008 /* TCD Minor Byte Count */ +# define KINETIS_DMA_TCD_SLAST_OFFSET 0x000c /* TCD Last Source Address Adjustment */ +# define KINETIS_DMA_TCD_DADDR_OFFSET 0x0010 /* TCD Destination Address */ +# define KINETIS_DMA_TCD_DOFF_OFFSET 0x0014 /* TCD Signed Destination Address Offset */ +# define KINETIS_DMA_TCD_CITER_OFFSET 0x0016 /* TCD Current Minor Loop Link, Major Loop Count */ +# define KINETIS_DMA_TCD_DLASTSGA_OFFSET 0x0018 /* TCD Last Destination Address Adjustment/Scatter Gather Address */ +# define KINETIS_DMA_TCD_CSR_OFFSET 0x001c /* TCD Control and Status */ +# define KINETIS_DMA_TCD_BITER_OFFSET 0x001e /* TCD Beginning Minor Loop Link, Major Loop Count */ +#endif #define KINETIS_DMA_TCD0_SADDR_OFFSET 0x0000 /* TCD Source Address */ #define KINETIS_DMA_TCD0_SOFF_OFFSET 0x0004 /* TCD Signed Source Address Offset */ @@ -323,19 +325,21 @@ #define KINETIS_DMA_DCHPRI13 (KINETIS_DMAC_BASE+KINETIS_DMA_DCHPRI13_OFFSET) #define KINETIS_DMA_DCHPRI12 (KINETIS_DMAC_BASE+KINETIS_DMA_DCHPRI12_OFFSET) -#define KINETIS_DMA_TCD_BASE(n) (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD_OFFSET(n)) - -#define KINETIS_DMA_TCD_SADDR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_SADDR_OFFSET) -#define KINETIS_DMA_TCD_SOFF(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_SOFF_OFFSET) -#define KINETIS_DMA_TCD_ATTR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_ATTR_OFFSET) -#define KINETIS_DMA_TCD_NBYTES(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_NBYTES_OFFSET) -#define KINETIS_DMA_TCD_SLAST(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_SLAST_OFFSET) -#define KINETIS_DMA_TCD_DADDR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_DADDR_OFFSET) -#define KINETIS_DMA_TCD_DOFF(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_DOFF_OFFSET) -#define KINETIS_DMA_TCD_CITER(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_CITER_OFFSET) -#define KINETIS_DMA_TCD_DLASTSGA(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_DLASTSGA_OFFSET) -#define KINETIS_DMA_TCD_CSR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_CSR_OFFSET) -#define KINETIS_DMA_TCD_BITER(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_BITER_OFFSET) +#ifndef KINETIS_K64 +# define KINETIS_DMA_TCD_BASE(n) (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD_OFFSET(n)) + +# define KINETIS_DMA_TCD_SADDR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_SADDR_OFFSET) +# define KINETIS_DMA_TCD_SOFF(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_SOFF_OFFSET) +# define KINETIS_DMA_TCD_ATTR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_ATTR_OFFSET) +# define KINETIS_DMA_TCD_NBYTES(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_NBYTES_OFFSET) +# define KINETIS_DMA_TCD_SLAST(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_SLAST_OFFSET) +# define KINETIS_DMA_TCD_DADDR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_DADDR_OFFSET) +# define KINETIS_DMA_TCD_DOFF(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_DOFF_OFFSET) +# define KINETIS_DMA_TCD_CITER(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_CITER_OFFSET) +# define KINETIS_DMA_TCD_DLASTSGA(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_DLASTSGA_OFFSET) +# define KINETIS_DMA_TCD_CSR(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_CSR_OFFSET) +# define KINETIS_DMA_TCD_BITER(n) (KINETIS_DMA_TCD_BASE(n)+KINETIS_DMA_TCD_BITER_OFFSET) +#endif #define KINETIS_DMA_TCD0_SADDR (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD0_SADDR_OFFSET) #define KINETIS_DMA_TCD0_SOFF (KINETIS_DMADESC_BASE+KINETIS_DMA_TCD0_SOFF_OFFSET) @@ -772,4 +776,4 @@ * Public Functions ****************************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_DMA_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DMA_H */ diff --git a/arch/arm/src/kinetis/kinetis_dmamux.h b/arch/arm/src/kinetis/chip/kinetis_dmamux.h similarity index 95% rename from arch/arm/src/kinetis/kinetis_dmamux.h rename to arch/arm/src/kinetis/chip/kinetis_dmamux.h index b83579180ea0ca53d2d0b99d55ac6de604ab51e8..d63feb8da31e3d562ea1c033afc094a7d1121f67 100644 --- a/arch/arm/src/kinetis/kinetis_dmamux.h +++ b/arch/arm/src/kinetis/chip/kinetis_dmamux.h @@ -1,7 +1,7 @@ /******************************************************************************************** - * arch/arm/src/kinetis/kinetis_dmamux.h + * arch/arm/src/kinetis/chip/kinetis_dmamux.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ********************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_DMAMUX_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_DMAMUX_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DMAMUX_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DMAMUX_H /******************************************************************************************** * Included Files @@ -108,4 +108,4 @@ * Public Functions ********************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_DMAMUX_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DMAMUX_H */ diff --git a/arch/arm/src/kinetis/kinetis_dspi.h b/arch/arm/src/kinetis/chip/kinetis_dspi.h similarity index 98% rename from arch/arm/src/kinetis/kinetis_dspi.h rename to arch/arm/src/kinetis/chip/kinetis_dspi.h index e682ef23e8555ab5f706903846579803d7c16e39..99507cb9e851bb1ab1c1274617205eec2c532e72 100644 --- a/arch/arm/src/kinetis/kinetis_dspi.h +++ b/arch/arm/src/kinetis/chip/kinetis_dspi.h @@ -1,7 +1,7 @@ /******************************************************************************************** - * arch/arm/src/kinetis/kinetis_dspi.h + * arch/arm/src/kinetis/chip/kinetis_dspi.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ********************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_DSPI_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_DSPI_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DSPI_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DSPI_H /******************************************************************************************** * Included Files @@ -318,4 +318,4 @@ * Public Functions ********************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_DSPI_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_DSPI_H */ diff --git a/arch/arm/src/kinetis/kinetis_enet.h b/arch/arm/src/kinetis/chip/kinetis_enet.h similarity index 99% rename from arch/arm/src/kinetis/kinetis_enet.h rename to arch/arm/src/kinetis/chip/kinetis_enet.h index cadd006d8ce114644b37fc9a77b5c2cb87dd67f3..8f34d0c7f6468ecfd1f6fd9ed32442786d240107 100644 --- a/arch/arm/src/kinetis/kinetis_enet.h +++ b/arch/arm/src/kinetis/chip/kinetis_enet.h @@ -1,7 +1,7 @@ /******************************************************************************************** - * arch/arm/src/kinetis/kinetis_enet.h + * arch/arm/src/kinetis/chip/kinetis_enet.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ********************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_ENET_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_ENET_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_ENET_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_ENET_H /******************************************************************************************** * Included Files @@ -649,4 +649,4 @@ struct enet_desc_s ********************************************************************************************/ #endif /* KINETIS_NENET && KINETIS_NENET > 0 */ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_ENET_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_ENET_H */ diff --git a/arch/arm/src/kinetis/kinetis_ewm.h b/arch/arm/src/kinetis/chip/kinetis_ewm.h similarity index 93% rename from arch/arm/src/kinetis/kinetis_ewm.h rename to arch/arm/src/kinetis/chip/kinetis_ewm.h index e259a3cf29af2f891e40532f4afd01ff3e5626bc..e91bc28c2c60fda5d1397b45092b62bd81f6618e 100644 --- a/arch/arm/src/kinetis/kinetis_ewm.h +++ b/arch/arm/src/kinetis/chip/kinetis_ewm.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/kinetis/kinetis_ewm.h + * arch/arm/src/kinetis/chip/kinetis_ewm.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_EWM_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_EWM_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_EWM_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_EWM_H /************************************************************************************ * Included Files @@ -87,4 +87,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_EWM_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_EWM_H */ diff --git a/arch/arm/src/kinetis/kinetis_flexbus.h b/arch/arm/src/kinetis/chip/kinetis_flexbus.h similarity index 97% rename from arch/arm/src/kinetis/kinetis_flexbus.h rename to arch/arm/src/kinetis/chip/kinetis_flexbus.h index 37992320fb18804f50c1d985bcfe5a3e13a85bef..7c063d086976a06e039aa101ffccfe775084b21d 100644 --- a/arch/arm/src/kinetis/kinetis_flexbus.h +++ b/arch/arm/src/kinetis/chip/kinetis_flexbus.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/kinetis/kinetis_flexbus.h + * arch/arm/src/kinetis/chip/kinetis_flexbus.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_FLEXBUS_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_FLEXBUS_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FLEXBUS_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FLEXBUS_H /************************************************************************************ * Included Files @@ -210,4 +210,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_FLEXBUS_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FLEXBUS_H */ diff --git a/arch/arm/src/kinetis/kinetis_flexcan.h b/arch/arm/src/kinetis/chip/kinetis_flexcan.h similarity index 98% rename from arch/arm/src/kinetis/kinetis_flexcan.h rename to arch/arm/src/kinetis/chip/kinetis_flexcan.h index db151d5403474d7dd1dc48ee249a8043846ae774..9d3ec74a38168c2a7ef7a0de6897dd401fdbb17e 100644 --- a/arch/arm/src/kinetis/kinetis_flexcan.h +++ b/arch/arm/src/kinetis/chip/kinetis_flexcan.h @@ -1,7 +1,7 @@ /**************************************************************************************************** - * arch/arm/src/kinetis/kinetis_flexcan.h + * arch/arm/src/kinetis/chip/kinetis_flexcan.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ****************************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_FLEXCAN_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_FLEXCAN_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FLEXCAN_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FLEXCAN_H /**************************************************************************************************** * Included Files @@ -315,4 +315,4 @@ * Public Functions ****************************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_FLEXCAN_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FLEXCAN_H */ diff --git a/arch/arm/src/kinetis/chip/kinetis_fmc.h b/arch/arm/src/kinetis/chip/kinetis_fmc.h new file mode 100644 index 0000000000000000000000000000000000000000..d189d657ddd135af9d3b45b70ee36953c5717296 --- /dev/null +++ b/arch/arm/src/kinetis/chip/kinetis_fmc.h @@ -0,0 +1,75 @@ +/******************************************************************************************** + * arch/arm/src/kinetis/chip/kinetis_fmc.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FMC_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FMC_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include + +#include "chip.h" + +/* This file is just a wrapper around pin muxing header files for the Kinetis family selected + * by the logic in chip.h. + */ + +#if defined(KINETIS_K20) || defined(KINETIS_K40) || defined(KINETIS_K60) +# include "chip/kinetis_k20k40k60fmc.h" +#elif defined(KINETIS_K64) +# include "chip/kinetis_k64fmc.h" +#else +# error "No FMC definitions for this Kinetis part" +#endif + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +/******************************************************************************************** + * Public Data + ********************************************************************************************/ + +/******************************************************************************************** + * Public Functions + ********************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FMC_H */ diff --git a/arch/arm/src/kinetis/chip/kinetis_ftfe.h b/arch/arm/src/kinetis/chip/kinetis_ftfe.h new file mode 100644 index 0000000000000000000000000000000000000000..13794d97dbe08a6ad7809ac2a5380fde12fd0c95 --- /dev/null +++ b/arch/arm/src/kinetis/chip/kinetis_ftfe.h @@ -0,0 +1,159 @@ +/************************************************************************************ + * arch/arm/src/kinetis/chip/kinetis_ftfe.h + * + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FTFE_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FTFE_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define KINETIS_FTFE_FSTAT_OFFSET 0x0000 /* Flash Status Register */ +#define KINETIS_FTFE_FCNFG_OFFSET 0x0001 /* Flash Configuration Register */ +#define KINETIS_FTFE_FSEC_OFFSET 0x0002 /* Flash Security Register */ +#define KINETIS_FTFE_FOPT_OFFSET 0x0003 /* Flash Option Register */ + +#define KINETIS_FTFE_FCCOB3_OFFSET 0x0004 /* Flash Common Command Object Registers */ +#define KINETIS_FTFE_FCCOB2_OFFSET 0x0005 /* Flash Common Command Object Registers */ +#define KINETIS_FTFE_FCCOB1_OFFSET 0x0006 /* Flash Common Command Object Registers */ +#define KINETIS_FTFE_FCCOB0_OFFSET 0x0007 /* Flash Common Command Object Registers */ +#define KINETIS_FTFE_FCCOB7_OFFSET 0x0008 /* Flash Common Command Object Registers */ +#define KINETIS_FTFE_FCCOB6_OFFSET 0x0009 /* Flash Common Command Object Registers */ +#define KINETIS_FTFE_FCCOB5_OFFSET 0x000a /* Flash Common Command Object Registers */ +#define KINETIS_FTFE_FCCOB4_OFFSET 0x000b /* Flash Common Command Object Registers */ +#define KINETIS_FTFE_FCCOBB_OFFSET 0x000c /* Flash Common Command Object Registers */ +#define KINETIS_FTFE_FCCOBA_OFFSET 0x000d /* Flash Common Command Object Registers */ +#define KINETIS_FTFE_FCCOB9_OFFSET 0x000e /* Flash Common Command Object Registers */ +#define KINETIS_FTFE_FCCOB8_OFFSET 0x000f /* Flash Common Command Object Registers */ +#define KINETIS_FTFE_FPROT3_OFFSET 0x0010 /* Program Flash Protection Registers */ +#define KINETIS_FTFE_FPROT2_OFFSET 0x0011 /* Program Flash Protection Registers */ +#define KINETIS_FTFE_FPROT1_OFFSET 0x0012 /* Program Flash Protection Registers */ +#define KINETIS_FTFE_FPROT0_OFFSET 0x0013 /* Program Flash Protection Registers */ +#define KINETIS_FTFE_FEPROT_OFFSET 0x0016 /* EEPROM Protection Register */ +#define KINETIS_FTFE_FDPROT_OFFSET 0x0017 /* Data Flash Protection Register */ + +/* Register Addresses ***************************************************************/ + +#define KINETIS_FTFE_FSTAT (KINETIS_FTFE_BASE+KINETIS_FTFE_FSTAT_OFFSET) +#define KINETIS_FTFE_FCNFG (KINETIS_FTFE_BASE+KINETIS_FTFE_FCNFG_OFFSET) +#define KINETIS_FTFE_FSEC (KINETIS_FTFE_BASE+KINETIS_FTFE_FSEC_OFFSET) +#define KINETIS_FTFE_FOPT (KINETIS_FTFE_BASE+KINETIS_FTFE_FOPT_OFFSET) +#define KINETIS_FTFE_FCCOB3 (KINETIS_FTFE_BASE+KINETIS_FTFE_FCCOB3_OFFSET) +#define KINETIS_FTFE_FCCOB2 (KINETIS_FTFE_BASE+KINETIS_FTFE_FCCOB2_OFFSET) +#define KINETIS_FTFE_FCCOB1 (KINETIS_FTFE_BASE+KINETIS_FTFE_FCCOB1_OFFSET) +#define KINETIS_FTFE_FCCOB0 (KINETIS_FTFE_BASE+KINETIS_FTFE_FCCOB0_OFFSET) +#define KINETIS_FTFE_FCCOB7 (KINETIS_FTFE_BASE+KINETIS_FTFE_FCCOB7_OFFSET) +#define KINETIS_FTFE_FCCOB6 (KINETIS_FTFE_BASE+KINETIS_FTFE_FCCOB6_OFFSET) +#define KINETIS_FTFE_FCCOB5 (KINETIS_FTFE_BASE+KINETIS_FTFE_FCCOB5_OFFSET) +#define KINETIS_FTFE_FCCOB4 (KINETIS_FTFE_BASE+KINETIS_FTFE_FCCOB4_OFFSET) +#define KINETIS_FTFE_FCCOBB (KINETIS_FTFE_BASE+KINETIS_FTFE_FCCOBB_OFFSET) +#define KINETIS_FTFE_FCCOBA (KINETIS_FTFE_BASE+KINETIS_FTFE_FCCOBA_OFFSET) +#define KINETIS_FTFE_FCCOB9 (KINETIS_FTFE_BASE+KINETIS_FTFE_FCCOB9_OFFSET) +#define KINETIS_FTFE_FCCOB8 (KINETIS_FTFE_BASE+KINETIS_FTFE_FCCOB8_OFFSET) +#define KINETIS_FTFE_FPROT3 (KINETIS_FTFE_BASE+KINETIS_FTFE_FPROT3_OFFSET) +#define KINETIS_FTFE_FPROT2 (KINETIS_FTFE_BASE+KINETIS_FTFE_FPROT2_OFFSET) +#define KINETIS_FTFE_FPROT1 (KINETIS_FTFE_BASE+KINETIS_FTFE_FPROT1_OFFSET) +#define KINETIS_FTFE_FPROT0 (KINETIS_FTFE_BASE+KINETIS_FTFE_FPROT0_OFFSET) +#define KINETIS_FTFE_FEPROT (KINETIS_FTFE_BASE+KINETIS_FTFE_FEPROT_OFFSET) +#define KINETIS_FTFE_FDPROT (KINETIS_FTFE_BASE+KINETIS_FTFE_FDPROT_OFFSET) + +/* Register Bit Definitions *********************************************************/ + +/* Flash Status Register */ + +#define FTFE_FSTAT_MGSTAT0 (1 << 0) /* Bit 0: Memory Controller Command Completion Status Flag */ + /* Bits 1-3: Reserved */ +#define FTFE_FSTAT_FPVIOL (1 << 4) /* Bit 4: Flash Protection Violation Flag */ +#define FTFE_FSTAT_ACCERR (1 << 5) /* Bit 5: Flash Access Error Flag */ +#define FTFE_FSTAT_RDCOLERR (1 << 6) /* Bit 6: FTFE Read Collision Error Flag */ +#define FTFE_FSTAT_CCIF (1 << 7) /* Bit 7: Command Complete Interrupt Flag */ + +/* Flash Configuration Register */ + +#define FTFE_FCNFG_EEERDY (1 << 0) /* Bit 0: FEEPROM backup data copied to FlexRAM */ +#define FTFE_FCNFG_RAMRDY (1 << 1) /* Bit 1: RAM Ready */ +#define FTFE_FCNFG_PFLSH (1 << 2) /* Bit 2: FTFE configuration */ +#define FTFE_FCNFG_SWAP (1 << 3) /* Bit 3: Swap */ +#define FTFE_FCNFG_ERSSUSP (1 << 4) /* Bit 4: Erase Suspend */ +#define FTFE_FCNFG_ERSAREQ (1 << 5) /* Bit 5: Erase All Request */ +#define FTFE_FCNFG_RDCOLLIE (1 << 6) /* Bit 6: Read Collision Error Interrupt Enable */ +#define FTFE_FCNFG_CCIE (1 << 7) /* Bit 7: Command Complete Interrupt Enable */ + +/* Flash Security Register */ + +#define FTFE_FSEC_SEC_SHIFT (0) /* Bits 0-1: Flash Security */ +#define FTFE_FSEC_SEC_MASK (3 << FTFE_FSEC_SEC_SHIFT) +# define FTFE_FSEC_SEC_SECURE (0 << FTFE_FSEC_SEC_SHIFT) /* 00,01,11: status is secure */ +# define FTFE_FSEC_SEC_UNSECURE (2 << FTFE_FSEC_SEC_SHIFT) /* 10: status is insecure */ +#define FTFE_FSEC_FSLACC_SHIFT (2) /* Bits 2-3: Freescale Failure Analysis Access Code */ +#define FTFE_FSEC_FSLACC_MASK (3 << FTFE_FSEC_FSLACC_SHIFT) +# define FTFE_FSEC_FSLACC_GRANTED (0 << FTFE_FSEC_FSLACC_SHIFT) /* 00 or 11: Access granted */ +# define FTFE_FSEC_FSLACC_DENIED (1 << FTFE_FSEC_FSLACC_SHIFT) /* 01 or 10: Access denied */ +#define FTFE_FSEC_MEEN_SHIFT (4) /* Bits 4-5: Mass Erase Enable Bits */ +#define FTFE_FSEC_MEEN_MASK (3 << FTFE_FSEC_MEEN_SHIFT) +# define FTFE_FSEC_MEEN_ENABLED (0 << FTFE_FSEC_MEEN_SHIFT) /* All values are enabled */ +#define FTFE_FSEC_KEYEN_SHIFT (6) /* Bits 6-7: Backdoor Key Security Enable */ +#define FTFE_FSEC_KEYEN_MASK (3 << FTFE_FSEC_KEYEN_SHIFT) +# define FTFE_FSEC_KEYEN_DISABLED (1 << FTFE_FSEC_KEYEN_SHIFT) /* All values are disabled */ + +/* Flash Option Register (32-bits, see Chip Configuration details) */ +/* Flash Common Command Object Registers (8-bit flash command data) */ +/* Program Flash Protection Registers (8-bit flash protection data) */ +/* EEPROM Protection Register (8-bit eeprom protection data) */ +/* Data Flash Protection Register (8-bit data flash protection data) */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FTFE_H */ diff --git a/arch/arm/src/kinetis/kinetis_ftm.h b/arch/arm/src/kinetis/chip/kinetis_ftm.h similarity index 90% rename from arch/arm/src/kinetis/kinetis_ftm.h rename to arch/arm/src/kinetis/chip/kinetis_ftm.h index 2f031b5dd9b68e6e1d71831b638a213f72478d04..1402f5e8d8a3af88caace4bc3e0d17d6d12b8b0d 100644 --- a/arch/arm/src/kinetis/kinetis_ftm.h +++ b/arch/arm/src/kinetis/chip/kinetis_ftm.h @@ -1,7 +1,7 @@ /******************************************************************************************** - * arch/arm/src/kinetis/kinetis_ftm.h + * arch/arm/src/kinetis/chip/kinetis_ftm.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ********************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_FTM_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_FTM_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FTM_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FTM_H /******************************************************************************************** * Included Files @@ -228,6 +228,50 @@ #define KINETIS_FTM2_SWOCTRL (KINETIS_FTM2_BASE+KINETIS_FTM_SWOCTRL_OFFSET) #define KINETIS_FTM2_PWMLOAD (KINETIS_FTM2_BASE+KINETIS_FTM_PWMLOAD_OFFSET) +#define KINETIS_FTM3_SC (KINETIS_FTM3_BASE+KINETIS_FTM_SC_OFFSET) +#define KINETIS_FTM3_CNT (KINETIS_FTM3_BASE+KINETIS_FTM_CNT_OFFSET) +#define KINETIS_FTM3_MOD (KINETIS_FTM3_BASE+KINETIS_FTM_MOD_OFFSET) + +#define KINETIS_FTM3_CSC(n) (KINETIS_FTM3_BASE+KINETIS_FTM_CSC_OFFSET(n)) +#define KINETIS_FTM3_CV(n) (KINETIS_FTM3_BASE+KINETIS_FTM_CV_OFFSET(n)) +#define KINETIS_FTM3_C0SC (KINETIS_FTM3_BASE+KINETIS_FTM_C0SC_OFFSET) +#define KINETIS_FTM3_C0V (KINETIS_FTM3_BASE+KINETIS_FTM_C0V_OFFSET) +#define KINETIS_FTM3_C1SC (KINETIS_FTM3_BASE+KINETIS_FTM_C1SC_OFFSET) +#define KINETIS_FTM3_C1V (KINETIS_FTM3_BASE+KINETIS_FTM_C1V_OFFSET) +#define KINETIS_FTM3_C2SC (KINETIS_FTM3_BASE+KINETIS_FTM_C2SC_OFFSET) +#define KINETIS_FTM3_C2V (KINETIS_FTM3_BASE+KINETIS_FTM_C2V_OFFSET) +#define KINETIS_FTM3_C3SC (KINETIS_FTM3_BASE+KINETIS_FTM_C3SC_OFFSET) +#define KINETIS_FTM3_C3V (KINETIS_FTM3_BASE+KINETIS_FTM_C3V_OFFSET) +#define KINETIS_FTM3_C4SC (KINETIS_FTM3_BASE+KINETIS_FTM_C4SC_OFFSET) +#define KINETIS_FTM3_C4V (KINETIS_FTM3_BASE+KINETIS_FTM_C4V_OFFSET) +#define KINETIS_FTM3_C5SC (KINETIS_FTM3_BASE+KINETIS_FTM_C5SC_OFFSET) +#define KINETIS_FTM3_C5V (KINETIS_FTM3_BASE+KINETIS_FTM_C5V_OFFSET) +#define KINETIS_FTM3_C6SC (KINETIS_FTM3_BASE+KINETIS_FTM_C6SC_OFFSET) +#define KINETIS_FTM3_C6V (KINETIS_FTM3_BASE+KINETIS_FTM_C6V_OFFSET) +#define KINETIS_FTM3_C7SC (KINETIS_FTM3_BASE+KINETIS_FTM_C7SC_OFFSET) +#define KINETIS_FTM3_C7V (KINETIS_FTM3_BASE+KINETIS_FTM_C7V_OFFSET) + +#define KINETIS_FTM3_CNTIN (KINETIS_FTM3_BASE+KINETIS_FTM_CNTIN_OFFSET) +#define KINETIS_FTM3_STATUS (KINETIS_FTM3_BASE+KINETIS_FTM_STATUS_OFFSET) +#define KINETIS_FTM3_MODE (KINETIS_FTM3_BASE+KINETIS_FTM_MODE_OFFSET) +#define KINETIS_FTM3_SYNC (KINETIS_FTM3_BASE+KINETIS_FTM_SYNC_OFFSET) +#define KINETIS_FTM3_OUTINIT (KINETIS_FTM3_BASE+KINETIS_FTM_OUTINIT_OFFSET) +#define KINETIS_FTM3_OUTMASK (KINETIS_FTM3_BASE+KINETIS_FTM_OUTMASK_OFFSET) +#define KINETIS_FTM3_COMBINE (KINETIS_FTM3_BASE+KINETIS_FTM_COMBINE_OFFSET) +#define KINETIS_FTM3_DEADTIME (KINETIS_FTM3_BASE+KINETIS_FTM_DEADTIME_OFFSET) +#define KINETIS_FTM3_EXTTRIG (KINETIS_FTM3_BASE+KINETIS_FTM_EXTTRIG_OFFSET) +#define KINETIS_FTM3_POL (KINETIS_FTM3_BASE+KINETIS_FTM_POL_OFFSET) +#define KINETIS_FTM3_FMS (KINETIS_FTM3_BASE+KINETIS_FTM_FMS_OFFSET) +#define KINETIS_FTM3_FILTER (KINETIS_FTM3_BASE+KINETIS_FTM_FILTER_OFFSET) +#define KINETIS_FTM3_FLTCTRL (KINETIS_FTM3_BASE+KINETIS_FTM_FLTCTRL_OFFSET) +#define KINETIS_FTM3_QDCTRL (KINETIS_FTM3_BASE+KINETIS_FTM_QDCTRL_OFFSET) +#define KINETIS_FTM3_CONF (KINETIS_FTM3_BASE+KINETIS_FTM_CONF_OFFSET) +#define KINETIS_FTM3_FLTPOL (KINETIS_FTM3_BASE+KINETIS_FTM_FLTPOL_OFFSET) +#define KINETIS_FTM3_SYNCONF (KINETIS_FTM3_BASE+KINETIS_FTM_SYNCONF_OFFSET) +#define KINETIS_FTM3_INVCTRL (KINETIS_FTM3_BASE+KINETIS_FTM_INVCTRL_OFFSET) +#define KINETIS_FTM3_SWOCTRL (KINETIS_FTM3_BASE+KINETIS_FTM_SWOCTRL_OFFSET) +#define KINETIS_FTM3_PWMLOAD (KINETIS_FTM3_BASE+KINETIS_FTM_PWMLOAD_OFFSET) + /* Register Bit Definitions *****************************************************************/ /* Status and Control */ @@ -525,4 +569,4 @@ * Public Functions ********************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_FTM_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_FTM_H */ diff --git a/arch/arm/src/kinetis/kinetis_gpio.h b/arch/arm/src/kinetis/chip/kinetis_gpio.h similarity index 100% rename from arch/arm/src/kinetis/kinetis_gpio.h rename to arch/arm/src/kinetis/chip/kinetis_gpio.h diff --git a/arch/arm/src/kinetis/kinetis_i2c.h b/arch/arm/src/kinetis/chip/kinetis_i2c.h similarity index 89% rename from arch/arm/src/kinetis/kinetis_i2c.h rename to arch/arm/src/kinetis/chip/kinetis_i2c.h index bee9ef92db16c19ffe2dc0eb1815140211295345..94d071727b36e6625a1523b0eeb4d0bae2421bff 100644 --- a/arch/arm/src/kinetis/kinetis_i2c.h +++ b/arch/arm/src/kinetis/chip/kinetis_i2c.h @@ -1,7 +1,7 @@ /******************************************************************************************** - * arch/arm/src/kinetis/kinetis_i2c.h + * arch/arm/src/kinetis/chip/kinetis_i2c.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ********************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_I2CE_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_I2CE_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_I2CE_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_I2CE_H /******************************************************************************************** * Included Files @@ -91,6 +91,19 @@ #define KINETIS_I2C1_SLTH (KINETIS_I2C1_BASE+KINETIS_I2C_SLTH_OFFSET) #define KINETIS_I2C1_SLTL (KINETIS_I2C1_BASE+KINETIS_I2C_SLTL_OFFSET) +#define KINETIS_I2C2_A1 (KINETIS_I2C2_BASE+KINETIS_I2C_A1_OFFSET) +#define KINETIS_I2C2_F (KINETIS_I2C2_BASE+KINETIS_I2C_F_OFFSET) +#define KINETIS_I2C2_C1 (KINETIS_I2C2_BASE+KINETIS_I2C_C1_OFFSET) +#define KINETIS_I2C2_S (KINETIS_I2C2_BASE+KINETIS_I2C_S_OFFSET) +#define KINETIS_I2C2_D (KINETIS_I2C2_BASE+KINETIS_I2C_D_OFFSET) +#define KINETIS_I2C2_C2 (KINETIS_I2C2_BASE+KINETIS_I2C_C2_OFFSET) +#define KINETIS_I2C2_FLT (KINETIS_I2C2_BASE+KINETIS_I2C_FLT_OFFSET) +#define KINETIS_I2C2_RA (KINETIS_I2C2_BASE+KINETIS_I2C_RA_OFFSET) +#define KINETIS_I2C2_SMB (KINETIS_I2C2_BASE+KINETIS_I2C_SMB_OFFSET) +#define KINETIS_I2C2_A2 (KINETIS_I2C2_BASE+KINETIS_I2C_A2_OFFSET) +#define KINETIS_I2C2_SLTH (KINETIS_I2C2_BASE+KINETIS_I2C_SLTH_OFFSET) +#define KINETIS_I2C2_SLTL (KINETIS_I2C2_BASE+KINETIS_I2C_SLTL_OFFSET) + /* Register Bit Definitions *****************************************************************/ /* I2C Address Register 1 (8-bit) */ @@ -182,4 +195,4 @@ * Public Functions ********************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_I2CE_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_I2CE_H */ diff --git a/arch/arm/src/kinetis/kinetis_i2s.h b/arch/arm/src/kinetis/chip/kinetis_i2s.h similarity index 98% rename from arch/arm/src/kinetis/kinetis_i2s.h rename to arch/arm/src/kinetis/chip/kinetis_i2s.h index 11bcc0995562bbb550a7380bf8191bf8534e2c42..5de08843bb078e71422f3b61270dbb821306489f 100644 --- a/arch/arm/src/kinetis/kinetis_i2s.h +++ b/arch/arm/src/kinetis/chip/kinetis_i2s.h @@ -1,7 +1,7 @@ /**************************************************************************************************** - * arch/arm/src/kinetis/kinetis_i2s.h + * arch/arm/src/kinetis/chip/kinetis_i2s.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ****************************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_I2S_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_I2S_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_I2S_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_I2S_H /**************************************************************************************************** * Included Files @@ -294,4 +294,4 @@ * Public Functions ****************************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_I2S_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_I2S_H */ diff --git a/arch/arm/src/kinetis/kinetis_fmc.h b/arch/arm/src/kinetis/chip/kinetis_k20k40k60fmc.h similarity index 97% rename from arch/arm/src/kinetis/kinetis_fmc.h rename to arch/arm/src/kinetis/chip/kinetis_k20k40k60fmc.h index 66f3a390926777330a36fed3374cc2a7632741d7..8dce4d682ef0289abb74d260a66c4b7b27b4633b 100644 --- a/arch/arm/src/kinetis/kinetis_fmc.h +++ b/arch/arm/src/kinetis/chip/kinetis_k20k40k60fmc.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/kinetis/kinetis_fmc.h + * arch/arm/src/kinetis/kinetis_k20k40k60fmc.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_FMC_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_FMC_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K20K40K60FMC_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K20K40K60FMC_H /************************************************************************************ * Included Files @@ -50,13 +50,13 @@ /* Register Offsets *****************************************************************/ -#define KINETIS_FMC_PFAPR_OFFSET 0x0000 /* Flash Access Protection Register */ -#define KINETIS_FMC_PFB0CR_OFFSET 0x0004 /* Flash Bank 0 Control Register */ -#define KINETIS_FMC_PFB1CR_OFFSET 0x0008 /* Flash Bank 1 Control Register */ +#define KINETIS_FMC_PFAPR_OFFSET 0x0000 /* Flash Access Protection Register */ +#define KINETIS_FMC_PFB0CR_OFFSET 0x0004 /* Flash Bank 0 Control Register */ +#define KINETIS_FMC_PFB1CR_OFFSET 0x0008 /* Flash Bank 1 Control Register */ /* Cache Directory Storage for way=w and set=s, w=0..3, s=0..7 */ -#define KINETIS_FMC_TAGVD_OFFSET(w,s) (0x100+((w)<<5)+((s)<<2)) +#define KINETIS_FMC_TAGVD_OFFSET(w,s) (0x100 + ((w) << 5) + ((s) << 2)) #define KINETIS_FMC_TAGVDW0S0_OFFSET 0x0100 /* Cache Directory Storage */ #define KINETIS_FMC_TAGVDW0S1_OFFSET 0x0104 /* Cache Directory Storage */ @@ -96,8 +96,8 @@ /* Cache Data Storage (upper and lower) for way=w and set=s, w=0..3, s=0..7 */ -#define KINETIS_FMC_DATAU_OFFSET(w,s) (0x200+((w)<<6)+((s)<<2)) -#define KINETIS_FMC_DATAL_OFFSET(w,s) (0x204+((w)<<6)+((s)<<2)) +#define KINETIS_FMC_DATAU_OFFSET(w,s) (0x200 + ((w) << 6) + ((s) << 2)) +#define KINETIS_FMC_DATAL_OFFSET(w,s) (0x204 + ((w) << 6) + ((s) << 2)) #define KINETIS_FMC_DATAW0S0U_OFFSET 0x0200 /* Cache Data Storage (upper word) */ #define KINETIS_FMC_DATAW0S0L_OFFSET 0x0204 /* Cache Data Storage (lower word) */ @@ -386,4 +386,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_FMC_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K20K40K60FMC_H */ diff --git a/arch/arm/src/kinetis/kinetis_mpu.h b/arch/arm/src/kinetis/chip/kinetis_k20k40k60mpu.h similarity index 100% rename from arch/arm/src/kinetis/kinetis_mpu.h rename to arch/arm/src/kinetis/chip/kinetis_k20k40k60mpu.h diff --git a/arch/arm/src/kinetis/chip/kinetis_k20memorymap.h b/arch/arm/src/kinetis/chip/kinetis_k20memorymap.h new file mode 100644 index 0000000000000000000000000000000000000000..7d5aa615cd3512c74c66304030e973ea17f3a229 --- /dev/null +++ b/arch/arm/src/kinetis/chip/kinetis_k20memorymap.h @@ -0,0 +1,180 @@ +/************************************************************************************ + * arch/arm/src/kinetis/chip/kinetis_k20memorymap.h + * + * Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K20MEMORYMAP_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K20MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" + +#ifdef KINETIS_K20 + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Memory Map ***********************************************************************/ +/* K20 Family + * + * The memory map for the following parts is defined in Freescale document + * K20P64M72SF1RM + */ + +#define KINETIS_FLASH_BASE 0x00000000 /* –0x0fffffff Program flash and read- + * only data (Includes exception + * vectors in first 1024 bytes) */ +#if !defined(KINETIS_FLEXMEM_SIZE) +# define KINETIS_FLEXNVM_BASE 0x10000000 /* –0x13ffffff FlexNVM */ +# define KINETIS_FLEXRAM_BASE 0x14000000 /* –0x17ffffff FlexRAM */ +#endif + /* 0x18000000 * –0x1bffffff Reserved */ +#define KINETIS_SRAML_BASE 0x1c000000 /* –0x1fffffff SRAM_L: Lower SRAM + * (ICODE/DCODE) */ +#define KINETIS_SRAMU_BASE 0x20000000 /* –0x200fffff SRAM_U: Upper SRAM bitband + * region */ + /* 0x20100000 * –0x21ffffff Reserved */ +#define KINETIS_SALIAS_BASE 0x22000000 /* –0x23ffffff Aliased to SRAM_U bitband */ + /* 0x24000000 * –0x3fffffff Reserved */ +#define KINETIS_BRIDGE0_BASE 0x40000000 /* –0x4007ffff Bitband region for peripheral + * bridge 0 (AIPS-Lite0) */ +#define KINETIS_BRIDGE1_BASE 0x40080000 /* –0x400fffff Bitband region for peripheral + * bridge 1 (AIPS-Lite1) */ +#define KINETIS_GPIOBB_BASE 0x400ff000 /* –0x400fffff Bitband region for general + * purpose input/output (GPIO) */ + /* 0x40100000 * –0x41ffffff Reserved */ +#define KINETIS_PALIAS_BASE 0x42000000 /* –0x43ffffff Aliased to peripheral bridge + * (AIPS-Lite) and general purpose + * input/output (GPIO) bitband */ + /* 0x44000000 * –0xdfffffff Reserved */ +#define KINETIS_PERIPH_BASE 0xe0000000 /* –0xe00fffff Private peripherals */ + /* 0xe0100000 * –0xffffffff Reserved */ + +/* Peripheral Bridge 0 Memory Map ***************************************************/ + +#define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */ +#define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */ +#define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */ +#define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */ +#define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */ +#define KINETIS_FTFL_BASE 0x40020000 /* Flash memory */ +#define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel mutiplexer 0 */ +#define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */ +#define KINETIS_SPI0_BASE 0x4002c000 /* SPI 0 */ +#define KINETIS_SPI1_BASE 0x4002d000 /* SPI 1 */ +#define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */ +#define KINETIS_CRC_BASE 0x40032000 /* CRC */ +#define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */ +#define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */ +#define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */ +#define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer 0 */ +#define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer 1 */ +#define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */ +#define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */ +#define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */ +#define KINETIS_LPTMR_BASE 0x40040000 /* Low power timer */ +#define KINETIS_SYSR_BASE 0x40041000 /* System register file */ +#define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */ +#define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */ +#define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */ +#define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12)) +#define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */ +#define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */ +#define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */ +#define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */ +#define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */ +#define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */ +#define KINETIS_EWM_BASE 0x40061000 /* External watchdog */ +#define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */ +#define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */ +#define KINETIS_OSC_BASE 0x40065000 /* System oscillator (OSC) */ +#define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */ +#define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */ +#define KINETIS_UART0_BASE 0x4006a000 /* UART0 */ +#define KINETIS_UART1_BASE 0x4006b000 /* UART1 */ +#define KINETIS_UART2_BASE 0x4006c000 /* UART2 */ +#define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */ +#define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ +#define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */ +#define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */ +#define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */ +#define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */ + +/* Peripheral Bridge 1 Memory Map ***************************************************/ + +#define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */ +#define KINETIS_FTM2_BASE 0x400b8000 /* FlexTimer 2 */ +#define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */ +#define KINETIS_DAC0_BASE 0x400cc000 /* 12-bit digital-to-analog converter (DAC) 0 */ + +#define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general + * purpose input/output module that shares the + * crossbar switch slave port with the AIPS-Lite + * is accessed at this address. */ +#define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6)) +#define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */ +#define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */ +#define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */ +#define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */ +#define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */ + +/* Private Peripheral Bus (PPB) Memory Map ******************************************/ + +#define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */ +#define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */ +#define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */ +#define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */ +#define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */ +#define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */ +#define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* KINETIS_K20 */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K20MEMORYMAP_H */ diff --git a/arch/arm/src/kinetis/kinetis_k20pinmux.h b/arch/arm/src/kinetis/chip/kinetis_k20pinmux.h similarity index 98% rename from arch/arm/src/kinetis/kinetis_k20pinmux.h rename to arch/arm/src/kinetis/chip/kinetis_k20pinmux.h index a4ca3eda29b7dfd8ee96ff4d4be9b89133adf717..ca708acfdf8aa4b6c6252384a16c0c31dfd6ac05 100644 --- a/arch/arm/src/kinetis/kinetis_k20pinmux.h +++ b/arch/arm/src/kinetis/chip/kinetis_k20pinmux.h @@ -1,7 +1,7 @@ /******************************************************************************************** - * arch/arm/src/kinetis/kinetis_k40pinmux.h + * arch/arm/src/kinetis/chip/kinetis_k20pinmux.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ********************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_K20PINMUX_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_K20PINMUX_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K20PINMUX_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K20PINMUX_H /******************************************************************************************** * Included Files @@ -349,4 +349,4 @@ * Public Functions ********************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_K20PINMUX_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K20PINMUX_H */ diff --git a/arch/arm/src/kinetis/chip/kinetis_k40memormap.h b/arch/arm/src/kinetis/chip/kinetis_k40memormap.h new file mode 100644 index 0000000000000000000000000000000000000000..65f2788ab6c3ba84c069173531f5db7cd5387ccd --- /dev/null +++ b/arch/arm/src/kinetis/chip/kinetis_k40memormap.h @@ -0,0 +1,199 @@ +/************************************************************************************ + * arch/arm/src/kinetis/chip/kinetis_k40memorymap.h + * + * Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K40MEMORYMAP_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K40MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" + +#ifdef KINETIS_K40 + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Memory Map ***********************************************************************/ +/* K40 Family + * + * The memory map for the following parts is defined in Freescale document + * K40P144M100SF2RM + */ + +#define KINETIS_FLASH_BASE 0x00000000 /* -0x0fffffff Program flash and read- + * only data (Includes exception + * vectors in first 1024 bytes) */ +# if !defined(KINETIS_FLEXMEM_SIZE) +# define KINETIS_FLEXNVM_BASE 0x10000000 /* -0x13ffffff FlexNVM */ +# define KINETIS_FLEXRAM_BASE 0x14000000 /* -0x17ffffff FlexRAM */ +# endif +#define KINETIS_SRAML_BASE 0x18000000 /* -0x1fffffff SRAM_L: Lower SRAM + * (ICODE/DCODE) */ +#define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband + * region */ + /* 0x20100000 * -0x21ffffff Reserved */ +#define KINETIS_SALIAS_BASE 0x22000000 /* -0x23ffffff Aliased to SRAM_U bitband */ + /* 0x24000000 * -0x3fffffff Reserved */ +#define KINETIS_BRIDGE0_BASE 0x40000000 /* -0x4007ffff Bitband region for peripheral + * bridge 0 (AIPS-Lite0) */ +#define KINETIS_BRIDGE1_BASE 0x40080000 /* -0x400fffff Bitband region for peripheral + * bridge 1 (AIPS-Lite1) */ +#define KINETIS_GPIOBB_BASE 0x400ff000 /* -0x400fffff Bitband region for general + * purpose input/output (GPIO) */ + /* 0x40100000 * -0x41ffffff Reserved */ +#define KINETIS_PALIAS_BASE 0x42000000 /* -0x43ffffff Aliased to peripheral bridge + * (AIPS-Lite) and general purpose + * input/output (GPIO) bitband */ + /* 0x44000000 * -0x5fffffff Reserved */ +#define KINETIS_FLEXBUS_WBBASE 0x60000000 /* -0x7fffffff FlexBus (External Memory - + * Write-back) */ +#define KINETIS_FLEXBUS_WTBASE 0x80000000 /* -0x9fffffff FlexBus (External Memory - + * Write-through) */ +#define KINETIS_FLEXBUS_NXBASE 0xa0000000 /* -0xdfffffff FlexBus (External Memory - + * Non-executable) */ +#define KINETIS_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */ + /* 0xe0100000 * -0xffffffff Reserved */ + +/* Peripheral Bridge 0 Memory Map ***************************************************/ + +#define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */ +#define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */ +#define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */ +#define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */ +#define KINETIS_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */ +#define KINETIS_MPU_BASE 0x4000d000 /* MPU */ +#define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */ +#define KINETIS_FTFL_BASE 0x40020000 /* Flash memory */ +#define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel mutiplexer 0 */ +#define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */ +#define KINETIS_SPI0_BASE 0x4002c000 /* SPI 0 */ +#define KINETIS_SPI1_BASE 0x4002d000 /* SPI 1 */ +#define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */ +#define KINETIS_CRC_BASE 0x40032000 /* CRC */ +#define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */ +#define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */ +#define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */ +#define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer 0 */ +#define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer 1 */ +#define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */ +#define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */ +#define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */ +#define KINETIS_LPTMR_BASE 0x40040000 /* Low power timer */ +#define KINETIS_SYSR_BASE 0x40041000 /* System register file */ +#define KINETIS_DRYICE_BASE 0x40042000 /* DryIce */ +#define KINETIS_DRYICESS_BASE 0x40043000 /* DryIce secure storage */ +#define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */ +#define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */ +#define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */ +#define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12)) +#define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */ +#define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */ +#define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */ +#define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */ +#define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */ +#define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */ +#define KINETIS_EWM_BASE 0x40061000 /* External watchdog */ +#define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */ +#define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */ +#define KINETIS_OSC_BASE 0x40065000 /* System oscillator (OSC) */ +#define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */ +#define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */ +#define KINETIS_UART0_BASE 0x4006a000 /* UART0 */ +#define KINETIS_UART1_BASE 0x4006b000 /* UART1 */ +#define KINETIS_UART2_BASE 0x4006c000 /* UART2 */ +#define KINETIS_UART3_BASE 0x4006d000 /* UART3 */ +#define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */ +#define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ +#define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */ +#define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */ +#define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */ +#define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */ + +/* Peripheral Bridge 1 Memory Map ***************************************************/ + +#define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */ +#define KINETIS_CAN1_BASE 0x400a4000 /* FlexCAN 1 */ +#define KINETIS_SPI2_BASE 0x400ac000 /* SPI 2 */ +#define KINETIS_SDHC_BASE 0x400b1000 /* SDHC */ +#define KINETIS_FTM2_BASE 0x400b8000 /* FlexTimer 2 */ +#define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */ +#define KINETIS_SLCD_BASE 0x400be000 /* Segment LCD */ +#define KINETIS_DAC0_BASE 0x400cc000 /* 12-bit digital-to-analog converter (DAC) 0 */ +#define KINETIS_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */ +#define KINETIS_UART4_BASE 0x400ea000 /* UART4 */ +#define KINETIS_UART5_BASE 0x400eb000 /* UART5 */ +#define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general + * purpose input/output module that shares the + * crossbar switch slave port with the AIPS-Lite + * is accessed at this address. */ +#define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6)) +#define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */ +#define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */ +#define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */ +#define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */ +#define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */ + +/* Private Peripheral Bus (PPB) Memory Map ******************************************/ + +#define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */ +#define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */ +#define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */ +#define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */ +#define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */ +#define KINETIS_ETM_BASE 0xe0041000 /* Embedded Trace Macrocell (ETM) */ +#define KINETIS_ETB_BASE 0xe0042000 /* Embedded Trace Buffer (ETB) */ +#define KINETIS_TFUN_BASE 0xe0043000 /* Embedded Trace Funnel */ +#define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */ +#define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* KINETIS_K40 */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K40MEMORYMAP_H */ diff --git a/arch/arm/src/kinetis/kinetis_k40pinmux.h b/arch/arm/src/kinetis/chip/kinetis_k40pinmux.h similarity index 99% rename from arch/arm/src/kinetis/kinetis_k40pinmux.h rename to arch/arm/src/kinetis/chip/kinetis_k40pinmux.h index 9798eda6be1522e19bf0b7fc2bc1d176a61a0fed..7083b0caf7c5dccde1573fcc508ffd8e47ef9a17 100644 --- a/arch/arm/src/kinetis/kinetis_k40pinmux.h +++ b/arch/arm/src/kinetis/chip/kinetis_k40pinmux.h @@ -1,7 +1,7 @@ /******************************************************************************************** - * arch/arm/src/kinetis/kinetis_k40pinmux.h + * arch/arm/src/kinetis/chip/kinetis_k40pinmux.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ********************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_K40PINMUX_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_K40PINMUX_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K40PINMUX_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K40PINMUX_H /******************************************************************************************** * Included Files @@ -515,4 +515,4 @@ * Public Functions ********************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_K40PINMUX_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K40PINMUX_H */ diff --git a/arch/arm/src/kinetis/chip/kinetis_k60memormap.h b/arch/arm/src/kinetis/chip/kinetis_k60memormap.h new file mode 100644 index 0000000000000000000000000000000000000000..8b00303ef7b245875c7460f2273b48d48f4609be --- /dev/null +++ b/arch/arm/src/kinetis/chip/kinetis_k60memormap.h @@ -0,0 +1,196 @@ +/************************************************************************************ + * arch/arm/src/kinetis/chip/kinetis_k60memorymap.h + * + * Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K60MEMORYMAP_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K60MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" + +#ifdef KINETIS_K64 + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Memory Map ***********************************************************************/ +/* K60 Family + * + * The memory map for the following parts is defined in Freescale document + * K60P144M100SF2RM + */ + +#define KINETIS_FLASH_BASE 0x00000000 /* -0x0fffffff Program flash and read- + * only data (Includes exception + * vectors in first 1024 bytes) */ +#if !defined(KINETIS_FLEXMEM_SIZE) +# define KINETIS_FLEXNVM_BASE 0x10000000 /* -0x13ffffff FlexNVM */ +# define KINETIS_FLEXRAM_BASE 0x14000000 /* -0x17ffffff FlexRAM */ +#endif +#define KINETIS_SRAML_BASE 0x18000000 /* -0x1fffffff SRAM_L: Lower SRAM + * (ICODE/DCODE) */ +#define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband + * region */ + /* 0x20100000 * -0x21ffffff Reserved */ +#define KINETIS_SALIAS_BASE 0x22000000 /* -0x23ffffff Aliased to SRAM_U bitband */ + /* 0x24000000 * -0x3fffffff Reserved */ +#define KINETIS_BRIDGE0_BASE 0x40000000 /* -0x4007ffff Bitband region for peripheral + * bridge 0 (AIPS-Lite0) */ +#define KINETIS_BRIDGE1_BASE 0x40080000 /* -0x400fffff Bitband region for peripheral + * bridge 1 (AIPS-Lite1) */ +#define KINETIS_GPIOBB_BASE 0x400ff000 /* -0x400fffff Bitband region for general + * purpose input/output (GPIO) */ + /* 0x40100000 * -0x41ffffff Reserved */ +#define KINETIS_PALIAS_BASE 0x42000000 /* -0x43ffffff Aliased to peripheral bridge + * (AIPS-Lite) and general purpose + * input/output (GPIO) bitband */ + /* 0x44000000 * -0x5fffffff Reserved */ +#define KINETIS_FLEXBUS_BASE 0x60000000 /* -0x7fffffff FlexBus */ +#define KINETIS_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */ + /* 0xe0100000 * -0xffffffff Reserved */ + +/* Peripheral Bridge 0 Memory Map ***************************************************/ + +#define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */ +#define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */ +#define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */ +#define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */ +#define KINETIS_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */ +#define KINETIS_MPU_BASE 0x4000d000 /* MPU */ +#define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */ +#define KINETIS_FTFL_BASE 0x40020000 /* Flash memory */ +#define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel mutiplexer 0 */ +#define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */ +#define KINETIS_SPI0_BASE 0x4002c000 /* DSPI 0 */ +#define KINETIS_SPI1_BASE 0x4002d000 /* DSPI 1 */ +#define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */ +#define KINETIS_CRC_BASE 0x40032000 /* CRC */ +#define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */ +#define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */ +#define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */ +#define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer (FTM) 0 */ +#define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer (FTM) 1 */ +#define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */ +#define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */ +#define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */ +#define KINETIS_LPTMR_BASE 0x40040000 /* Low power timer */ +#define KINETIS_SYSR_BASE 0x40041000 /* System register file */ +#define KINETIS_DRYICE_BASE 0x40042000 /* DryIce */ +#define KINETIS_DRYICESS_BASE 0x40043000 /* DryIce secure storage */ +#define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */ +#define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */ +#define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */ +#define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12)) +#define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */ +#define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */ +#define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */ +#define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */ +#define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */ +#define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */ +#define KINETIS_EWM_BASE 0x40061000 /* External watchdog */ +#define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */ +#define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */ +#define KINETIS_OSC_BASE 0x40065000 /* System oscillator (XOSC) */ +#define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */ +#define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */ +#define KINETIS_UART0_BASE 0x4006a000 /* UART0 */ +#define KINETIS_UART1_BASE 0x4006b000 /* UART1 */ +#define KINETIS_UART2_BASE 0x4006c000 /* UART2 */ +#define KINETIS_UART3_BASE 0x4006d000 /* UART3 */ +#define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */ +#define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ +#define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */ +#define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */ +#define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */ +#define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */ + +/* Peripheral Bridge 1 Memory Map ***************************************************/ + +#define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */ +#define KINETIS_RNGB_BASE 0x400a0000 /* Random number generator (RNGB) */ +#define KINETIS_CAN1_BASE 0x400a4000 /* FlexCAN 1 */ +#define KINETIS_SPI2_BASE 0x400ac000 /* DSPI 2 */ +#define KINETIS_SDHC_BASE 0x400b1000 /* SDHC */ +#define KINETIS_FTM2_BASE 0x400b8000 /* FlexTimer 2 */ +#define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */ +#define KINETIS_EMAC_BASE 0x400c0000 /* Ethernet MAC and IEEE 1588 timers */ +#define KINETIS_DAC0_BASE 0x400cc000 /* 12-bit digital-to-analog converter (DAC) 0 */ +#define KINETIS_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */ +#define KINETIS_UART4_BASE 0x400ea000 /* UART4 */ +#define KINETIS_UART5_BASE 0x400eb000 /* UART5 */ +#define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general + * purpose input/output module that shares the + * crossbar switch slave port with the AIPS-Lite + * is accessed at this address. */ +#define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6)) +#define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */ +#define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */ +#define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */ +#define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */ +#define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */ + +/* Private Peripheral Bus (PPB) Memory Map ******************************************/ + +#define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */ +#define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */ +#define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */ +#define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */ +#define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */ +#define KINETIS_ETM_BASE 0xe0041000 /* Embedded Trace Macrocell (ETM) */ +#define KINETIS_ETB_BASE 0xe0042000 /* Embedded Trace Buffer (ETB) */ +#define KINETIS_TFUN_BASE 0xe0043000 /* Embedded Trace Funnel */ +#define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */ +#define KINETIS_MMCAU_BASE 0xe0081000 /* Memory Mapped Cryptographic Acceleration Unit (MMCAU) */ +#define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* KINETIS_K64 */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K60MEMORYMAP_H */ diff --git a/arch/arm/src/kinetis/kinetis_k60pinmux.h b/arch/arm/src/kinetis/chip/kinetis_k60pinmux.h similarity index 99% rename from arch/arm/src/kinetis/kinetis_k60pinmux.h rename to arch/arm/src/kinetis/chip/kinetis_k60pinmux.h index 7fd69a0813e7f3c3bad938e38e69b5a77deb1719..5cfb3a1aa0a6918d94ed4e68d9ade2a64ae02830 100644 --- a/arch/arm/src/kinetis/kinetis_k60pinmux.h +++ b/arch/arm/src/kinetis/chip/kinetis_k60pinmux.h @@ -1,7 +1,7 @@ /******************************************************************************************** - * arch/arm/src/kinetis/kinetis_k60pinset.h + * arch/arm/src/kinetis/chip/kinetis_k60pinset.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ********************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_K60PINMUX_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_K60PINMUX_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K60PINMUX_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K60PINMUX_H /******************************************************************************************** * Included Files @@ -479,4 +479,4 @@ * Public Functions ********************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_K60PINMUX_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K60PINMUX_H */ diff --git a/arch/arm/src/kinetis/chip/kinetis_k64fmc.h b/arch/arm/src/kinetis/chip/kinetis_k64fmc.h new file mode 100644 index 0000000000000000000000000000000000000000..036e38f1299075c3268146a460b03119bfd098dc --- /dev/null +++ b/arch/arm/src/kinetis/chip/kinetis_k64fmc.h @@ -0,0 +1,293 @@ +/************************************************************************************ + * arch/arm/src/kinetis/kinetis_k64fmc.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K64FMC_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K64FMC_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define KINETIS_FMC_PFAPR_OFFSET 0x0000 /* Flash Access Protection Register */ +#define KINETIS_FMC_PFB0CR_OFFSET 0x0004 /* Flash Bank 0 Control Register */ +#define KINETIS_FMC_PFB1CR_OFFSET 0x0008 /* Flash Bank 1 Control Register */ + +/* Cache Directory Storage for way=w and set=s, w=0..3, s=0..7 */ + +#define KINETIS_FMC_TAGVD_OFFSET(w,s) (0x100 + ((w) << 5) + ((s) << 2)) + +#define KINETIS_FMC_TAGVDW0S0_OFFSET 0x0100 /* Cache Directory Storage */ +#define KINETIS_FMC_TAGVDW0S1_OFFSET 0x0104 /* Cache Directory Storage */ +#define KINETIS_FMC_TAGVDW0S2_OFFSET 0x0108 /* Cache Directory Storage */ +#define KINETIS_FMC_TAGVDW0S3_OFFSET 0x010c /* Cache Directory Storage */ + +#define KINETIS_FMC_TAGVDW1S0_OFFSET 0x0110 /* Cache Directory Storage */ +#define KINETIS_FMC_TAGVDW1S1_OFFSET 0x0114 /* Cache Directory Storage */ +#define KINETIS_FMC_TAGVDW1S2_OFFSET 0x0118 /* Cache Directory Storage */ +#define KINETIS_FMC_TAGVDW1S3_OFFSET 0x011c /* Cache Directory Storage */ + +#define KINETIS_FMC_TAGVDW2S0_OFFSET 0x0120 /* Cache Directory Storage */ +#define KINETIS_FMC_TAGVDW2S1_OFFSET 0x0124 /* Cache Directory Storage */ +#define KINETIS_FMC_TAGVDW2S2_OFFSET 0x0128 /* Cache Directory Storage */ +#define KINETIS_FMC_TAGVDW2S3_OFFSET 0x012c /* Cache Directory Storage */ + +#define KINETIS_FMC_TAGVDW3S0_OFFSET 0x0130 /* Cache Directory Storage */ +#define KINETIS_FMC_TAGVDW3S1_OFFSET 0x0134 /* Cache Directory Storage */ +#define KINETIS_FMC_TAGVDW3S2_OFFSET 0x0138 /* Cache Directory Storage */ +#define KINETIS_FMC_TAGVDW3S3_OFFSET 0x013c /* Cache Directory Storage */ + +/* Cache Data Storage (upper and lower) for way=w and set=s, w=0..3, s=0..7 */ + +#define KINETIS_FMC_DATAU_OFFSET(w,s) (0x200 + ((w) << 6) + ((s) << 2)) +#define KINETIS_FMC_DATAL_OFFSET(w,s) (0x204 + ((w) << 6) + ((s) << 2)) + +#define KINETIS_FMC_DATAW0S0U_OFFSET 0x0200 /* Cache Data Storage (upper word) */ +#define KINETIS_FMC_DATAW0S0L_OFFSET 0x0204 /* Cache Data Storage (lower word) */ +#define KINETIS_FMC_DATAW0S1U_OFFSET 0x0208 /* Cache Data Storage (upper word) */ +#define KINETIS_FMC_DATAW0S1L_OFFSET 0x020c /* Cache Data Storage (lower word) */ +#define KINETIS_FMC_DATAW0S2U_OFFSET 0x0210 /* Cache Data Storage (upper word) */ +#define KINETIS_FMC_DATAW0S2L_OFFSET 0x0214 /* Cache Data Storage (lower word) */ +#define KINETIS_FMC_DATAW0S3U_OFFSET 0x0218 /* Cache Data Storage (upper word) */ +#define KINETIS_FMC_DATAW0S3L_OFFSET 0x021c /* Cache Data Storage (lower word) */ + +#define KINETIS_FMC_DATAW1S0U_OFFSET 0x0220 /* Cache Data Storage (upper word) */ +#define KINETIS_FMC_DATAW1S0L_OFFSET 0x0224 /* Cache Data Storage (lower word) */ +#define KINETIS_FMC_DATAW1S1U_OFFSET 0x0228 /* Cache Data Storage (upper word) */ +#define KINETIS_FMC_DATAW1S1L_OFFSET 0x022c /* Cache Data Storage (lower word) */ +#define KINETIS_FMC_DATAW1S2U_OFFSET 0x0230 /* Cache Data Storage (upper word) */ +#define KINETIS_FMC_DATAW1S2L_OFFSET 0x0234 /* Cache Data Storage (lower word) */ +#define KINETIS_FMC_DATAW1S3U_OFFSET 0x0238 /* Cache Data Storage (upper word) */ +#define KINETIS_FMC_DATAW1S3L_OFFSET 0x023c /* Cache Data Storage (lower word) */ + +#define KINETIS_FMC_DATAW2S0U_OFFSET 0x0240 /* Cache Data Storage (upper word) */ +#define KINETIS_FMC_DATAW2S0L_OFFSET 0x0244 /* Cache Data Storage (lower word) */ +#define KINETIS_FMC_DATAW2S1U_OFFSET 0x0248 /* Cache Data Storage (upper word) */ +#define KINETIS_FMC_DATAW2S1L_OFFSET 0x024c /* Cache Data Storage (lower word) */ +#define KINETIS_FMC_DATAW2S2U_OFFSET 0x0250 /* Cache Data Storage (upper word) */ +#define KINETIS_FMC_DATAW2S2L_OFFSET 0x0254 /* Cache Data Storage (lower word) */ +#define KINETIS_FMC_DATAW2S3U_OFFSET 0x0258 /* Cache Data Storage (upper word) */ +#define KINETIS_FMC_DATAW2S3L_OFFSET 0x025c /* Cache Data Storage (lower word) */ + +#define KINETIS_FMC_DATAW3S0U_OFFSET 0x0260 /* Cache Data Storage (upper word) */ +#define KINETIS_FMC_DATAW3S0L_OFFSET 0x0264 /* Cache Data Storage (lower word) */ +#define KINETIS_FMC_DATAW3S1U_OFFSET 0x0268 /* Cache Data Storage (upper word) */ +#define KINETIS_FMC_DATAW3S1L_OFFSET 0x026c /* Cache Data Storage (lower word) */ +#define KINETIS_FMC_DATAW3S2U_OFFSET 0x0270 /* Cache Data Storage (upper word) */ +#define KINETIS_FMC_DATAW3S2L_OFFSET 0x0274 /* Cache Data Storage (lower word) */ +#define KINETIS_FMC_DATAW3S3U_OFFSET 0x0278 /* Cache Data Storage (upper word) */ +#define KINETIS_FMC_DATAW3S3L_OFFSET 0x027c /* Cache Data Storage (lower word) */ + +/* Register Addresses ***************************************************************/ + +#define KINETIS_FMC_PFAPR (KINETIS_FMC_BASE+KINETIS_FMC_PFAPR_OFFSET) +#define KINETIS_FMC_PFB0CR (KINETIS_FMC_BASE+KINETIS_FMC_PFB0CR_OFFSET) +#define KINETIS_FMC_PFB1CR (KINETIS_FMC_BASE+KINETIS_FMC_PFB1CR_OFFSET) + +/* Cache Directory Storage for way=w and set=s, w=0..3, s=0..7 */ + +#define KINETIS_FMC_TAGVD(w,s) (KINETIS_FMC_BASE+KINETIS_FMC_TAGVD_OFFSET(w,s)) + +#define KINETIS_FMC_TAGVDW0S0 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW0S0_OFFSET) +#define KINETIS_FMC_TAGVDW0S1 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW0S1_OFFSET) +#define KINETIS_FMC_TAGVDW0S2 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW0S2_OFFSET) +#define KINETIS_FMC_TAGVDW0S3 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW0S3_OFFSET) + +#define KINETIS_FMC_TAGVDW1S0 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW1S0_OFFSET) +#define KINETIS_FMC_TAGVDW1S1 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW1S1_OFFSET) +#define KINETIS_FMC_TAGVDW1S2 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW1S2_OFFSET) +#define KINETIS_FMC_TAGVDW1S3 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW1S3_OFFSET) + +#define KINETIS_FMC_TAGVDW2S0 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW2S0_OFFSET) +#define KINETIS_FMC_TAGVDW2S1 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW2S1_OFFSET) +#define KINETIS_FMC_TAGVDW2S2 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW2S2_OFFSET) +#define KINETIS_FMC_TAGVDW2S3 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW2S3_OFFSET) + +#define KINETIS_FMC_TAGVDW3S0 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW3S0_OFFSET) +#define KINETIS_FMC_TAGVDW3S1 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW3S1_OFFSET) +#define KINETIS_FMC_TAGVDW3S2 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW3S2_OFFSET) +#define KINETIS_FMC_TAGVDW3S3 (KINETIS_FMC_BASE+KINETIS_FMC_TAGVDW3S3_OFFSET) + +/* Cache Data Storage (upper and lower) for way=w and set=s, w=0..3, s=0..7 */ + +#define KINETIS_FMC_DATAU(w,s) (KINETIS_FMC_BASE+KINETIS_FMC_DATAU_OFFSET(w,s)) +#define KINETIS_FMC_DATAL(w,s) (KINETIS_FMC_BASE+KINETIS_FMC_DATAL_OFFSET(w,s)) + +#define KINETIS_FMC_DATAW0S0U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW0S0U_OFFSET) +#define KINETIS_FMC_DATAW0S0L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW0S0L_OFFSET) +#define KINETIS_FMC_DATAW0S1U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW0S1U_OFFSET) +#define KINETIS_FMC_DATAW0S1L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW0S1L_OFFSET) +#define KINETIS_FMC_DATAW0S2U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW0S2U_OFFSET) +#define KINETIS_FMC_DATAW0S2L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW0S2L_OFFSET) +#define KINETIS_FMC_DATAW0S3U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW0S3U_OFFSET) +#define KINETIS_FMC_DATAW0S3L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW0S3L_OFFSET) + +#define KINETIS_FMC_DATAW1S0U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW1S0U_OFFSET) +#define KINETIS_FMC_DATAW1S0L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW1S0L_OFFSET) +#define KINETIS_FMC_DATAW1S1U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW1S1U_OFFSET) +#define KINETIS_FMC_DATAW1S1L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW1S1L_OFFSET) +#define KINETIS_FMC_DATAW1S2U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW1S2U_OFFSET) +#define KINETIS_FMC_DATAW1S2L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW1S2L_OFFSET) +#define KINETIS_FMC_DATAW1S3U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW1S3U_OFFSET) +#define KINETIS_FMC_DATAW1S3L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW1S3L_OFFSET) + +#define KINETIS_FMC_DATAW2S0U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW2S0U_OFFSET) +#define KINETIS_FMC_DATAW2S0L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW2S0L_OFFSET) +#define KINETIS_FMC_DATAW2S1U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW2S1U_OFFSET) +#define KINETIS_FMC_DATAW2S1L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW2S1L_OFFSET) +#define KINETIS_FMC_DATAW2S2U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW2S2U_OFFSET) +#define KINETIS_FMC_DATAW2S2L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW2S2L_OFFSET) +#define KINETIS_FMC_DATAW2S3U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW2S3U_OFFSET) +#define KINETIS_FMC_DATAW2S3L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW2S3L_OFFSET) + +#define KINETIS_FMC_DATAW3S0U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW3S0U_OFFSET) +#define KINETIS_FMC_DATAW3S0L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW3S0L_OFFSET) +#define KINETIS_FMC_DATAW3S1U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW3S1U_OFFSET) +#define KINETIS_FMC_DATAW3S1L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW3S1L_OFFSET) +#define KINETIS_FMC_DATAW3S2U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW3S2U_OFFSET) +#define KINETIS_FMC_DATAW3S2L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW3S2L_OFFSET) +#define KINETIS_FMC_DATAW3S3U (KINETIS_FMC_BASE+KINETIS_FMC_DATAW3S3U_OFFSET) +#define KINETIS_FMC_DATAW3S3L (KINETIS_FMC_BASE+KINETIS_FMC_DATAW3S3L_OFFSET) + +/* Register Bit Definitions *********************************************************/ + +/* Flash Access Protection Register */ +/* Access protection bits (all masters) */ + +#define FMC_PFAPR_NONE 0 /* No access may be performed by this master */ +#define FMC_PFAPR_RDONLY 1 /* Only read accesses may be performed by this master */ +#define FMC_PFAPR_WRONLY 2 /* Only write accesses may be performed by this master */ +#define FMC_PFAPR_RDWR 3 /* Both read and write accesses may be performed by this master */ + +#define FMC_PFAPR_M0AP_SHIFT (0) /* Bits 0-1: Master 0 Access Protection */ +#define FMC_PFAPR_M0AP_MASK (3 << FMC_PFAPR_M0AP_SHIFT) +#define FMC_PFAPR_M1AP_SHIFT (2) /* Bits 2-3: Master 1 Access Protection */ +#define FMC_PFAPR_M1AP_MASK (3 << FMC_PFAPR_M1AP_SHIFT) +#define FMC_PFAPR_M2AP_SHIFT (4) /* Bits 4-5: Master 2 Access Protection */ +#define FMC_PFAPR_M2AP_MASK (3 << FMC_PFAPR_M2AP_SHIFT) +#define FMC_PFAPR_M3AP_SHIFT (6) /* Bits 6-7: Master 3 Access Protection */ +#define FMC_PFAPR_M3AP_MASK (3 << FMC_PFAPR_M3AP_SHIFT) +#define FMC_PFAPR_M4AP_SHIFT (8) /* Bits 8-9: Master 4 Access Protection */ +#define FMC_PFAPR_M4AP_MASK (3 << FMC_PFAPR_M4AP_SHIFT) +#define FMC_PFAPR_M5AP_SHIFT (10) /* Bits 10-11: Master 5 Access Protection */ +#define FMC_PFAPR_M5AP_MASK (3 << FMC_PFAPR_M5AP_SHIFT) +#define FMC_PFAPR_M6AP_SHIFT (12) /* Bits 12-13: Master 6 Access Protection */ +#define FMC_PFAPR_M6AP_MASK (3 << FMC_PFAPR_M6AP_SHIFT) +#define FMC_PFAPR_M7AP_SHIFT (14) /* Bits 14-15: Master 7 Access Protection */ +#define FMC_PFAPR_M7AP_MASK (3 << FMC_PFAPR_M7AP_SHIFT) +#define FMC_PFAPR_M0PFD (1 << 16) /* Bit 16: Master 0 Prefetch Disable */ +#define FMC_PFAPR_M1PFD (1 << 17) /* Bit 17: Master 1 Prefetch Disable */ +#define FMC_PFAPR_M2PFD (1 << 18) /* Bit 18: Master 2 Prefetch Disable */ +#define FMC_PFAPR_M3PFD (1 << 19) /* Bit 19: Master 3 Prefetch Disable */ +#define FMC_PFAPR_M4PFD (1 << 20) /* Bit 20: Master 4 Prefetch Disable */ +#define FMC_PFAPR_M5PFD (1 << 21) /* Bit 21: Master 5 Prefetch Disable */ +#define FMC_PFAPR_M6PFD (1 << 22) /* Bit 22: Master 6 Prefetch Disable */ +#define FMC_PFAPR_M7PFD (1 << 23) /* Bit 23: Master 7 Prefetch Disable */ + /* Bits 24-31: Reserved */ +/* Flash Bank 0 Control Register */ + +#define FMC_PFB0CR_B0SEBE (1 << 0) /* Bit 0: Bank 0 Single Entry Buffer Enable */ +#define FMC_PFB0CR_B0IPE (1 << 1) /* Bit 1: Bank 0 Instruction Prefetch Enable */ +#define FMC_PFB0CR_B0DPE (1 << 2) /* Bit 2: Bank 0 Data Prefetch Enable */ +#define FMC_PFB0CR_B0ICE (1 << 3) /* Bit 3: Bank 0 Instruction Cache Enable */ +#define FMC_PFB0CR_B0DCE (1 << 4) /* Bit 4: Bank 0 Data Cache Enable */ +#define FMC_PFB0CR_CRC_SHIFT (5) /* Bits 5-7: Cache Replacement Control */ +#define FMC_PFB0CR_CRC_MASK (7 << FMC_PFB0CR_CRC_SHIFT) +# define FMC_PFB0CR_CRC_ALL (0 << FMC_PFB0CR_CRC_SHIFT) /* LRU all four ways */ +# define FMC_PFB0CR_CRC_I01D23 (2 << FMC_PFB0CR_CRC_SHIFT) /* LRU ifetches 0-1 data 2-3 */ +# define FMC_PFB0CR_CRC_I012D3 (3 << FMC_PFB0CR_CRC_SHIFT) /* LRU ifetches 0-3 data 3 */ + /* Bits 8-16: Reserved */ +#define FMC_PFB0CR_B0MW_SHIFT (17) /* Bits 17-18: Bank 0 Memory Width */ +#define FMC_PFB0CR_B0MW_MASK (3 << FMC_PFB0CR_B0MW_SHIFT) +# define FMC_PFB0CR_B0MW_32BITS (0 << FMC_PFB0CR_B0MW_SHIFT) /* 32 bits */ +# define FMC_PFB0CR_B0MW_64BITS (1 << FMC_PFB0CR_B0MW_SHIFT) /* 64 bits */ +#define FMC_PFB0CR_S_B_INV (1 << 19) /* Bit 19: Invalidate Prefetch Speculation Buffer */ +#define FMC_PFB0CR_CINV_WAY_SHIFT (20) /* Bits 20-23: Cache Invalidate Way x */ +#define FMC_PFB0CR_CINV_WAY_MASK (15 << FMC_PFB0CR_CINV_WAY_SHIFT) +#define FMC_PFB0CR_CLCK_WAY_SHIFT (24) /* Bits 24-27: Cache Lock Way x */ +#define FMC_PFB0CR_CLCK_WAY_MASK (15 << FMC_PFB0CR_CLCK_WAY_SHIFT) +#define FMC_PFB0CR_B0RWSC_SHIFT (28) /* Bits 28-31: Bank 0 Read Wait State Control */ +#define FMC_PFB0CR_B0RWSC_MASK (15 << FMC_PFB0CR_B0RWSC_SHIFT) + +/* Flash Bank 1 Control Register */ + +#define FMC_PFB1CR_B1SEBE (1 << 0) /* Bit 0: Bank 1 Single Entry Buffer Enable */ +#define FMC_PFB1CR_B1IPE (1 << 1) /* Bit 1: Bank 1 Instruction Prefetch Enable */ +#define FMC_PFB1CR_B1DPE (1 << 2) /* Bit 2: Bank 1 Data Prefetch Enable */ +#define FMC_PFB1CR_B1ICE (1 << 3) /* Bit 3: Bank 1 Instruction Cache Enable */ +#define FMC_PFB1CR_B1DCE (1 << 4) /* Bit 4: Bank 1 Data Cache Enable */ + /* Bits 5-16: Reserved */ +#define FMC_PFB1CR_B1MW_SHIFT (17) /* Bits 17-18: Bank 1 Memory Width */ +#define FMC_PFB1CR_B1MW_MASK (3 << FMC_PFB1CR_B1MW_SHIFT) +# define FMC_PFB1CR_B1MW_32BITS (0 << FMC_PFB1CR_B1MW_SHIFT) /* 32 bits */ +# define FMC_PFB1CR_B1MW_64BITS (1 << FMC_PFB1CR_B1MW_SHIFT) /* 64 bits */ + /* Bits 19-27: Reserved */ +#define FMC_PFB1CR_B1RWSC_SHIFT (28) /* Bits 28-31: Bank 1 Read Wait State Control */ +#define FMC_PFB1CR_B1RWSC_MASK (15 << FMC_PFB1CR_B0RWSC_SHIFT) + +/* Cache Directory Storage for way=w and set=s, w=0..3, s=0..7 */ + +#define FMC_TAGVD_VALID (1 << 0) /* Bit 0: 1-bit valid for cache entry */ + /* Bits 1-4: Reserved */ +#define FMC_TAGVD_TAG_SHIFT (5) /* Bits 5-18: 13-bit tag for cache entry */ +#define FMC_TAGVD_TAG_MASK (0x1fff << FMC_TAGVD_TAG_SHIFT) + /* Bits 19-31: Reserved */ + +/* Cache Data Storage (upper and lower) for way=w and set=s, w=0..3, s=0..7. + * 64-bit data in two 32-bit registers. + */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K64FMC_H */ diff --git a/arch/arm/src/kinetis/chip/kinetis_k64memorymap.h b/arch/arm/src/kinetis/chip/kinetis_k64memorymap.h new file mode 100644 index 0000000000000000000000000000000000000000..235343de89dca36385c028a03ea5223e80c9903b --- /dev/null +++ b/arch/arm/src/kinetis/chip/kinetis_k64memorymap.h @@ -0,0 +1,213 @@ +/************************************************************************************ + * arch/arm/src/kinetis/chip/kinetis_k64memorymap.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K64MEMORYMAP_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K64MEMORYMAP_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include "chip.h" + +#ifdef KINETIS_K64 + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Memory Map ***********************************************************************/ +/* K64 Family + * + * The memory map for the following parts is defined in NXP document + * K64P144M120SF5RM.pdf + */ + +#if defined(CONFIG_ARCH_CHIP_MK64FX512VLL12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VLL12) || \ + defined(CONFIG_ARCH_CHIP_MK64FX512VDC12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VDC12) || \ + defined(CONFIG_ARCH_CHIP_MK64FX512VLQ12) || defined(CONFIG_ARCH_CHIP_MK64FX512VMD12) || \ + defined(CONFIG_ARCH_CHIP_MK64FN1M0VLQ12) || defined(CONFIG_ARCH_CHIP_MK64FN1M0VMD12) + +# define KINETIS_FLASH_BASE 0x00000000 /* -0x0fffffff Program flash and read- + * only data (Includes exception + * vectors in first 1024 bytes) */ +# if !defined(KINETIS_FLEXMEM_SIZE) +# define KINETIS_FLEXNVM_BASE 0x10000000 /* -0x13ffffff FlexNVM */ +# define KINETIS_FLEXRAM_BASE 0x14000000 /* -0x17ffffff FlexRAM */ +# endif +# define KINETIS_SRAML_BASE 0x18000000 /* -0x1fffffff SRAM_L: Lower SRAM + * (ICODE/DCODE) */ +# define KINETIS_SRAMU_BASE 0x20000000 /* -0x200fffff SRAM_U: Upper SRAM bitband + * region */ + /* 0x20100000 * -0x21ffffff Reserved */ +# define KINETIS_SALIAS_BASE 0x22000000 /* -0x23ffffff Aliased to SRAM_U bitband */ + /* 0x24000000 * -0x3fffffff Reserved */ +# define KINETIS_BRIDGE0_BASE 0x40000000 /* -0x4007ffff Bitband region for peripheral + * bridge 0 (AIPS-Lite0) */ +# define KINETIS_BRIDGE1_BASE 0x40080000 /* -0x400fffff Bitband region for peripheral + * bridge 1 (AIPS-Lite1) */ +# define KINETIS_GPIOBB_BASE 0x400ff000 /* -0x400fffff Bitband region for general + * purpose input/output (GPIO) */ + /* 0x40100000 * -0x41ffffff Reserved */ +# define KINETIS_PALIAS_BASE 0x42000000 /* -0x43ffffff Aliased to peripheral bridge + * (AIPS-Lite) and general purpose + * input/output (GPIO) bitband */ + /* 0x44000000 * -0x5fffffff Reserved */ +# define KINETIS_FLEXBUS_BASE 0x60000000 /* -0x7fffffff FlexBus */ +# define KINETIS_PERIPH_BASE 0xe0000000 /* -0xe00fffff Private peripherals */ + /* 0xe0100000 * -0xffffffff Reserved */ + +/* Peripheral Bridge 0 Memory Map ***************************************************/ + +# define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */ +# define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */ +# define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */ +# define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */ +# define KINETIS_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */ +# define KINETIS_MPU_BASE 0x4000d000 /* MPU */ +# define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */ +# define KINETIS_FTFE_BASE 0x40020000 /* Flash memory */ +# define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel mutiplexer 0 */ +# define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */ +# define KINETIS_SPI0_BASE 0x4002c000 /* DSPI 0 */ +# define KINETIS_SPI1_BASE 0x4002d000 /* DSPI 1 */ +# define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */ +# define KINETIS_CRC_BASE 0x40032000 /* CRC */ +# define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */ +# define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */ +# define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */ +# define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer (FTM) 0 */ +# define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer (FTM) 1 */ +# define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */ +# define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */ +# define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */ +# define KINETIS_LPTMR_BASE 0x40040000 /* Low power timer */ +# define KINETIS_SYSR_BASE 0x40041000 /* System register file */ +# define KINETIS_DRYICE_BASE 0x40042000 /* DryIce */ +# define KINETIS_DRYICESS_BASE 0x40043000 /* DryIce secure storage */ +# define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */ +# define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */ +# define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */ +# define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12)) +# define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */ +# define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */ +# define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */ +# define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */ +# define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */ +# define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */ +# define KINETIS_EWM_BASE 0x40061000 /* External watchdog */ +# define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */ +# define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */ +# define KINETIS_OSC_BASE 0x40065000 /* System oscillator (XOSC) */ +# define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */ +# define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */ +# define KINETIS_I2C2_BASE 0x400E6000 /* I2C 2 */ +# define KINETIS_UART0_BASE 0x4006a000 /* UART0 */ +# define KINETIS_UART1_BASE 0x4006b000 /* UART1 */ +# define KINETIS_UART2_BASE 0x4006c000 /* UART2 */ +# define KINETIS_UART3_BASE 0x4006d000 /* UART3 */ +# define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */ +# define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ +# define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */ +# define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */ +# define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */ +# define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */ + +/* Peripheral Bridge 1 Memory Map ***************************************************/ + +# define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */ +# define KINETIS_RNGB_BASE 0x400a0000 /* Random number generator (RNGB) */ +# define KINETIS_CAN1_BASE 0x400a4000 /* FlexCAN 1 */ +# define KINETIS_SPI2_BASE 0x400ac000 /* DSPI 2 */ +# define KINETIS_SDHC_BASE 0x400b1000 /* SDHC */ +# define KINETIS_FTM2_BASE 0x4003a000 /* FlexTimer 2 */ +# define KINETIS_FTM3_BASE 0x400b9000 /* FlexTimer 3 */ +# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */ +# define KINETIS_EMAC_BASE 0x400c0000 /* Ethernet MAC and IEEE 1588 timers */ +# define KINETIS_DAC0_BASE 0x400cc000 /* 12-bit digital-to-analog converter (DAC) 0 */ +# define KINETIS_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */ +# define KINETIS_UART4_BASE 0x400ea000 /* UART4 */ +# define KINETIS_UART5_BASE 0x400eb000 /* UART5 */ +# define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general + * purpose input/output module that shares the + * crossbar switch slave port with the AIPS-Lite + * is accessed at this address. */ +# define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6)) +# define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */ +# define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */ +# define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */ +# define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */ +# define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */ + +/* Private Peripheral Bus (PPB) Memory Map ******************************************/ + +# define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */ +# define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */ +# define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */ +# define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */ +# define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */ +# define KINETIS_ETM_BASE 0xe0041000 /* Embedded Trace Macrocell (ETM) */ +# define KINETIS_ETB_BASE 0xe0042000 /* Embedded Trace Buffer (ETB) */ +# define KINETIS_TFUN_BASE 0xe0043000 /* Embedded Trace Funnel */ +# define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */ +# define KINETIS_MMCAU_BASE 0xe0081000 /* Memory Mapped Cryptographic Acceleration Unit (MMCAU) */ +# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */ + +#else + /* The memory map for other parts is defined in other documents and may or may not + * be the same as above (the family members are all very similar) This error just + * means that you have to look at the document and determine for yourself if the + * memory map is the same. + */ + +# error "No memory map for this K64 part" +#endif + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#endif /* KINETIS_K64 */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_K64MEMORYMAP_H */ diff --git a/arch/arm/src/kinetis/chip/kinetis_k64mpu.h b/arch/arm/src/kinetis/chip/kinetis_k64mpu.h new file mode 100644 index 0000000000000000000000000000000000000000..808ff15be220fd21526815e5ed769eff8f95e638 --- /dev/null +++ b/arch/arm/src/kinetis/chip/kinetis_k64mpu.h @@ -0,0 +1,358 @@ +/**************************************************************************************************** + * arch/arm/src/kinetis/kinetis_mpu.h + * + * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_MPU_H +#define __ARCH_ARM_SRC_KINETIS_KINETIS_MPU_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ + +/* Register Offsets *********************************************************************************/ + +#define KINETIS_MPU_CESR_OFFSET 0x0000 /* Control/Error Status Register */ + +#define KINETIS_MPU_EAR_OFFSET(n) (0x0010+((n)<<3)) /* Error Address Register, Slave Port n */ +#define KINETIS_MPU_EDR_OFFSET(n) (0x0014+((n)<<3)) /* Error Detail Register, Slave Port n */ + +#define KINETIS_MPU_EAR0_OFFSET 0x0010 /* Error Address Register, Slave Port 0 */ +#define KINETIS_MPU_EDR0_OFFSET 0x0014 /* Error Detail Register, Slave Port 0 */ +#define KINETIS_MPU_EAR1_OFFSET 0x0018 /* Error Address Register, Slave Port 1 */ +#define KINETIS_MPU_EDR1_OFFSET 0x001c /* Error Detail Register, Slave Port 1 */ +#define KINETIS_MPU_EAR2_OFFSET 0x0020 /* Error Address Register, Slave Port 2 */ +#define KINETIS_MPU_EDR2_OFFSET 0x0024 /* Error Detail Register, Slave Port 2 */ +#define KINETIS_MPU_EAR3_OFFSET 0x0028 /* Error Address Register, Slave Port 3 */ +#define KINETIS_MPU_EDR3_OFFSET 0x002c /* Error Detail Register, Slave Port 3 */ +#define KINETIS_MPU_EAR4_OFFSET 0x0030 /* Error Address Register, Slave Port 4 */ +#define KINETIS_MPU_EDR4_OFFSET 0x0034 /* Error Detail Register, Slave Port 4 */ + +#define KINETIS_MPU_RGD_WORD_OFFSET(n,m) (x0400+((n)<<4)+((m)<< 2) /* Region Descriptor n, Word m */ + +#define KINETIS_MPU_RGD0_WORD0_OFFSET 0x0400 /* Region Descriptor 0, Word 0 */ +#define KINETIS_MPU_RGD0_WORD1_OFFSET 0x0404 /* Region Descriptor 0, Word 1 */ +#define KINETIS_MPU_RGD0_WORD2_OFFSET 0x0408 /* Region Descriptor 0, Word 2 */ +#define KINETIS_MPU_RGD0_WORD3_OFFSET 0x040c /* Region Descriptor 0, Word 3 */ +#define KINETIS_MPU_RGD1_WORD0_OFFSET 0x0410 /* Region Descriptor 1, Word 0 */ +#define KINETIS_MPU_RGD1_WORD1_OFFSET 0x0414 /* Region Descriptor 1, Word 1 */ +#define KINETIS_MPU_RGD1_WORD2_OFFSET 0x0418 /* Region Descriptor 1, Word 2 */ +#define KINETIS_MPU_RGD1_WORD3_OFFSET 0x041c /* Region Descriptor 1, Word 3 */ +#define KINETIS_MPU_RGD2_WORD0_OFFSET 0x0420 /* Region Descriptor 2, Word 0 */ +#define KINETIS_MPU_RGD2_WORD1_OFFSET 0x0424 /* Region Descriptor 2, Word 1 */ +#define KINETIS_MPU_RGD2_WORD2_OFFSET 0x0428 /* Region Descriptor 2, Word 2 */ +#define KINETIS_MPU_RGD2_WORD3_OFFSET 0x042c /* Region Descriptor 2, Word 3 */ +#define KINETIS_MPU_RGD3_WORD0_OFFSET 0x0430 /* Region Descriptor 3, Word 0 */ +#define KINETIS_MPU_RGD3_WORD1_OFFSET 0x0434 /* Region Descriptor 3, Word 1 */ +#define KINETIS_MPU_RGD3_WORD2_OFFSET 0x0438 /* Region Descriptor 3, Word 2 */ +#define KINETIS_MPU_RGD3_WORD3_OFFSET 0x043c /* Region Descriptor 3, Word 3 */ +#define KINETIS_MPU_RGD4_WORD0_OFFSET 0x0440 /* Region Descriptor 4, Word 0 */ +#define KINETIS_MPU_RGD4_WORD1_OFFSET 0x0444 /* Region Descriptor 4, Word 1 */ +#define KINETIS_MPU_RGD4_WORD2_OFFSET 0x0448 /* Region Descriptor 4, Word 2 */ +#define KINETIS_MPU_RGD4_WORD3_OFFSET 0x044c /* Region Descriptor 4, Word 3 */ +#define KINETIS_MPU_RGD5_WORD0_OFFSET 0x0450 /* Region Descriptor 5, Word 0 */ +#define KINETIS_MPU_RGD5_WORD1_OFFSET 0x0454 /* Region Descriptor 5, Word 1 */ +#define KINETIS_MPU_RGD5_WORD2_OFFSET 0x0458 /* Region Descriptor 5, Word 2 */ +#define KINETIS_MPU_RGD5_WORD3_OFFSET 0x045c /* Region Descriptor 5, Word 3 */ +#define KINETIS_MPU_RGD6_WORD0_OFFSET 0x0460 /* Region Descriptor 6, Word 0 */ +#define KINETIS_MPU_RGD6_WORD1_OFFSET 0x0464 /* Region Descriptor 6, Word 1 */ +#define KINETIS_MPU_RGD6_WORD2_OFFSET 0x0468 /* Region Descriptor 6, Word 2 */ +#define KINETIS_MPU_RGD6_WORD3_OFFSET 0x046c /* Region Descriptor 6, Word 3 */ +#define KINETIS_MPU_RGD7_WORD0_OFFSET 0x0470 /* Region Descriptor 7, Word 0 */ +#define KINETIS_MPU_RGD7_WORD1_OFFSET 0x0474 /* Region Descriptor 7, Word 1 */ +#define KINETIS_MPU_RGD7_WORD2_OFFSET 0x0478 /* Region Descriptor 7, Word 2 */ +#define KINETIS_MPU_RGD7_WORD3_OFFSET 0x047c /* Region Descriptor 7, Word 3 */ +#define KINETIS_MPU_RGD8_WORD0_OFFSET 0x0480 /* Region Descriptor 8, Word 0 */ +#define KINETIS_MPU_RGD8_WORD1_OFFSET 0x0484 /* Region Descriptor 8, Word 1 */ +#define KINETIS_MPU_RGD8_WORD2_OFFSET 0x0488 /* Region Descriptor 8, Word 2 */ +#define KINETIS_MPU_RGD8_WORD3_OFFSET 0x048c /* Region Descriptor 8, Word 3 */ +#define KINETIS_MPU_RGD9_WORD0_OFFSET 0x0490 /* Region Descriptor 9, Word 0 */ +#define KINETIS_MPU_RGD9_WORD1_OFFSET 0x0494 /* Region Descriptor 9, Word 1 */ +#define KINETIS_MPU_RGD9_WORD2_OFFSET 0x0498 /* Region Descriptor 9, Word 2 */ +#define KINETIS_MPU_RGD9_WORD3_OFFSET 0x049c /* Region Descriptor 9, Word 3 */ +#define KINETIS_MPU_RGD10_WORD0_OFFSET 0x04a0 /* Region Descriptor 10, Word 0 */ +#define KINETIS_MPU_RGD10_WORD1_OFFSET 0x04a4 /* Region Descriptor 10, Word 1 */ +#define KINETIS_MPU_RGD10_WORD2_OFFSET 0x04a8 /* Region Descriptor 10, Word 2 */ +#define KINETIS_MPU_RGD10_WORD3_OFFSET 0x04ac /* Region Descriptor 10, Word 3 */ +#define KINETIS_MPU_RGD11_WORD0_OFFSET 0x04b0 /* Region Descriptor 11, Word 0 */ +#define KINETIS_MPU_RGD11_WORD1_OFFSET 0x04b4 /* Region Descriptor 11, Word 1 */ +#define KINETIS_MPU_RGD11_WORD2_OFFSET 0x04b8 /* Region Descriptor 11, Word 2 */ +#define KINETIS_MPU_RGD11_WORD3_OFFSET 0x04bc /* Region Descriptor 11, Word 3 */ + +#define KINETIS_MPU_RGDAAC_OFFSET(n) (0x0800+((n)<<2)) /* Region Descriptor Alternate Access Control n */ + +#define KINETIS_MPU_RGDAAC0_OFFSET 0x0800 /* Region Descriptor Alternate Access Control 0 */ +#define KINETIS_MPU_RGDAAC1_OFFSET 0x0804 /* Region Descriptor Alternate Access Control 1 */ +#define KINETIS_MPU_RGDAAC2_OFFSET 0x0808 /* Region Descriptor Alternate Access Control 2 */ +#define KINETIS_MPU_RGDAAC3_OFFSET 0x080c /* Region Descriptor Alternate Access Control 3 */ +#define KINETIS_MPU_RGDAAC4_OFFSET 0x0810 /* Region Descriptor Alternate Access Control 4 */ +#define KINETIS_MPU_RGDAAC5_OFFSET 0x0814 /* Region Descriptor Alternate Access Control 5 */ +#define KINETIS_MPU_RGDAAC6_OFFSET 0x0818 /* Region Descriptor Alternate Access Control 6 */ +#define KINETIS_MPU_RGDAAC7_OFFSET 0x081c /* Region Descriptor Alternate Access Control 7 */ +#define KINETIS_MPU_RGDAAC8_OFFSET 0x0820 /* Region Descriptor Alternate Access Control 8 */ +#define KINETIS_MPU_RGDAAC9_OFFSET 0x0824 /* Region Descriptor Alternate Access Control 9 */ +#define KINETIS_MPU_RGDAAC10_OFFSET 0x0828 /* Region Descriptor Alternate Access Control 10 */ +#define KINETIS_MPU_RGDAAC11_OFFSET 0x082c /* Region Descriptor Alternate Access Control 11 */ + +/* Register Addresses *******************************************************************************/ + +#define KINETIS_MPU_CESR (KINETIS_MPU_BASE+KINETIS_MPU_CESR_OFFSET) + +#define KINETIS_MPU_EAR(n) (KINETIS_MPU_BASE+KINETIS_MPU_EAR_OFFSET(n)) +#define KINETIS_MPU_EDR(n) (KINETIS_MPU_BASE+KINETIS_MPU_EDR_OFFSET(n)) + +#define KINETIS_MPU_EAR0 (KINETIS_MPU_BASE+KINETIS_MPU_EAR0_OFFSET) +#define KINETIS_MPU_EDR0 (KINETIS_MPU_BASE+KINETIS_MPU_EDR0_OFFSET) +#define KINETIS_MPU_EAR1 (KINETIS_MPU_BASE+KINETIS_MPU_EAR1_OFFSET) +#define KINETIS_MPU_EDR1 (KINETIS_MPU_BASE+KINETIS_MPU_EDR1_OFFSET) +#define KINETIS_MPU_EAR2 (KINETIS_MPU_BASE+KINETIS_MPU_EAR2_OFFSET) +#define KINETIS_MPU_EDR2 (KINETIS_MPU_BASE+KINETIS_MPU_EDR2_OFFSET) +#define KINETIS_MPU_EAR3 (KINETIS_MPU_BASE+KINETIS_MPU_EAR3_OFFSET) +#define KINETIS_MPU_EDR3 (KINETIS_MPU_BASE+KINETIS_MPU_EDR3_OFFSET) +#define KINETIS_MPU_EAR4 (KINETIS_MPU_BASE+KINETIS_MPU_EAR4_OFFSET) +#define KINETIS_MPU_EDR4 (KINETIS_MPU_BASE+KINETIS_MPU_EDR4_OFFSET) + +#define KINETIS_MPU_RGD_WORD(n,m) (KINETIS_MPU_BASE+KINETIS_MPU_RGD_WORD_OFFSET(n,m)) + +#define KINETIS_MPU_RGD0_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD0_WORD0_OFFSET) +#define KINETIS_MPU_RGD0_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD0_WORD1_OFFSET) +#define KINETIS_MPU_RGD0_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD0_WORD2_OFFSET) +#define KINETIS_MPU_RGD0_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD0_WORD3_OFFSET) +#define KINETIS_MPU_RGD1_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD1_WORD0_OFFSET) +#define KINETIS_MPU_RGD1_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD1_WORD1_OFFSET) +#define KINETIS_MPU_RGD1_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD1_WORD2_OFFSET) +#define KINETIS_MPU_RGD1_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD1_WORD3_OFFSET) +#define KINETIS_MPU_RGD2_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD2_WORD0_OFFSET) +#define KINETIS_MPU_RGD2_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD2_WORD1_OFFSET) +#define KINETIS_MPU_RGD2_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD2_WORD2_OFFSET) +#define KINETIS_MPU_RGD2_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD2_WORD3_OFFSET) +#define KINETIS_MPU_RGD3_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD3_WORD0_OFFSET) +#define KINETIS_MPU_RGD3_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD3_WORD1_OFFSET) +#define KINETIS_MPU_RGD3_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD3_WORD2_OFFSET) +#define KINETIS_MPU_RGD3_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD3_WORD3_OFFSET) +#define KINETIS_MPU_RGD4_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD4_WORD0_OFFSET) +#define KINETIS_MPU_RGD4_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD4_WORD1_OFFSET) +#define KINETIS_MPU_RGD4_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD4_WORD2_OFFSET) +#define KINETIS_MPU_RGD4_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD4_WORD3_OFFSET) +#define KINETIS_MPU_RGD5_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD5_WORD0_OFFSET) +#define KINETIS_MPU_RGD5_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD5_WORD1_OFFSET) +#define KINETIS_MPU_RGD5_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD5_WORD2_OFFSET) +#define KINETIS_MPU_RGD5_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD5_WORD3_OFFSET) +#define KINETIS_MPU_RGD6_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD6_WORD0_OFFSET) +#define KINETIS_MPU_RGD6_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD6_WORD1_OFFSET) +#define KINETIS_MPU_RGD6_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD6_WORD2_OFFSET) +#define KINETIS_MPU_RGD6_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD6_WORD3_OFFSET) +#define KINETIS_MPU_RGD7_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD7_WORD0_OFFSET) +#define KINETIS_MPU_RGD7_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD7_WORD1_OFFSET) +#define KINETIS_MPU_RGD7_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD7_WORD2_OFFSET) +#define KINETIS_MPU_RGD7_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD7_WORD3_OFFSET) +#define KINETIS_MPU_RGD8_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD8_WORD0_OFFSET) +#define KINETIS_MPU_RGD8_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD8_WORD1_OFFSET) +#define KINETIS_MPU_RGD8_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD8_WORD2_OFFSET) +#define KINETIS_MPU_RGD8_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD8_WORD3_OFFSET) +#define KINETIS_MPU_RGD9_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD9_WORD0_OFFSET) +#define KINETIS_MPU_RGD9_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD9_WORD1_OFFSET) +#define KINETIS_MPU_RGD9_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD9_WORD2_OFFSET) +#define KINETIS_MPU_RGD9_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD9_WORD3_OFFSET) +#define KINETIS_MPU_RGD10_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD10_WORD0_OFFSET) +#define KINETIS_MPU_RGD10_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD10_WORD1_OFFSET) +#define KINETIS_MPU_RGD10_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD10_WORD2_OFFSET) +#define KINETIS_MPU_RGD10_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD10_WORD3_OFFSET) +#define KINETIS_MPU_RGD11_WORD0 (KINETIS_MPU_BASE+KINETIS_MPU_RGD11_WORD0_OFFSET) +#define KINETIS_MPU_RGD11_WORD1 (KINETIS_MPU_BASE+KINETIS_MPU_RGD11_WORD1_OFFSET) +#define KINETIS_MPU_RGD11_WORD2 (KINETIS_MPU_BASE+KINETIS_MPU_RGD11_WORD2_OFFSET) +#define KINETIS_MPU_RGD11_WORD3 (KINETIS_MPU_BASE+KINETIS_MPU_RGD11_WORD3_OFFSET) + +#define KINETIS_MPU_RGDAAC(n) (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC_OFFSET(n)) + +#define KINETIS_MPU_RGDAAC0 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC0_OFFSET) +#define KINETIS_MPU_RGDAAC1 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC1_OFFSET) +#define KINETIS_MPU_RGDAAC2 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC2_OFFSET) +#define KINETIS_MPU_RGDAAC3 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC3_OFFSET) +#define KINETIS_MPU_RGDAAC4 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC4_OFFSET) +#define KINETIS_MPU_RGDAAC5 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC5_OFFSET) +#define KINETIS_MPU_RGDAAC6 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC6_OFFSET) +#define KINETIS_MPU_RGDAAC7 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC7_OFFSET) +#define KINETIS_MPU_RGDAAC8 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC8_OFFSET) +#define KINETIS_MPU_RGDAAC9 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC9_OFFSET) +#define KINETIS_MPU_RGDAAC10 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC10_OFFSET) +#define KINETIS_MPU_RGDAAC11 (KINETIS_MPU_BASE+KINETIS_MPU_RGDAAC11_OFFSET) + +/* Register Bit Definitions *************************************************************************/ + +/* Control/Error Status Register */ + +#define MPU_CESR_VLD (1 << 0) /* Bit 0: Valid (global enable/disable for the MPU) */ + /* Bits 1-7: Reserved */ +#define MPU_CESR_NRGD_SHIFT (8) /* Bits 8-11: Number of region descriptors */ +#define MPU_CESR_NRGD_MASK (15 << MPU_CESR_NRGD_SHIFT) +# define MPU_CESR_NRGD_8DESC (0 << MPU_CESR_NRGD_SHIFT) /* 8 region descriptors */ +# define MPU_CESR_NRGD_12DESC (1 << MPU_CESR_NRGD_SHIFT) /* 12 region descriptors */ +# define MPU_CESR_NRGD_16DESC (2 << MPU_CESR_NRGD_SHIFT) /* 16 region descriptors */ +#define MPU_CESR_NSP_SHIFT (12) /* Bits 12-15: Number of slave ports */ +#define MPU_CESR_NSP_MASK (15 << MPU_CESR_NSP_SHIFT) +#define MPU_CESR_HRL_SHIFT (16) /* Bits 16-19: Hardware revision level */ +#define MPU_CESR_HRL_MASK (15 << MPU_CESR_HRL_SHIFT) + /* Bits 20-26: Reserved */ +#define MPU_CESR_SPERR_SHIFT (27) /* Bits 27-31: Slave port n error */ +#define MPU_CESR_SPERR_MASK (31 << MPU_CESR_SPERR_SHIFT) +# define MPU_CESR_SPERR_SPORT(n) ((1 << (4-(n))) << MPU_CESR_SPERR_SHIFT) /* Slave port nn */ +# define MPU_CESR_SPERR_SPORT0 (16 << MPU_CESR_SPERR_SHIFT) /* Slave port 0 */ +# define MPU_CESR_SPERR_SPORT1 (8 << MPU_CESR_SPERR_SHIFT) /* Slave port 1 */ +# define MPU_CESR_SPERR_SPORT2 (4 << MPU_CESR_SPERR_SHIFT) /* Slave port 2 */ +# define MPU_CESR_SPERR_SPORT3 (2 << MPU_CESR_SPERR_SHIFT) /* Slave port 3 */ +# define MPU_CESR_SPERR_SPORT4 (1 << MPU_CESR_SPERR_SHIFT) /* Slave port 4 */ + +/* Error Address Register, Slave Port n. 32-bit error address. */ + +/* Error Detail Register, Slave Port n */ + +#define MPU_EDR_ERW (1 << 0) /* Bit 0: Error read/write */ +#define MPU_EDR_EATTR_SHIFT (1) /* Bits 1-3: Error attributes */ +#define MPU_EDR_EATTR_MASK (7 << MPU_EDR_EATTR_SHIFT) +# define MPU_EDR_EATTR_USRINST (0 << MPU_EDR_EATTR_SHIFT) /* User mode, instruction access */ +# define MPU_EDR_EATTR_USRDATA (1 << MPU_EDR_EATTR_SHIFT) /* User mode, data access */ +# define MPU_EDR_EATTR_SUPINST (2 << MPU_EDR_EATTR_SHIFT) /* Supervisor mode, instruction access */ +# define MPU_EDR_EATTR_SUPDATA (3 << MPU_EDR_EATTR_SHIFT) /* Supervisor mode, data access */ +#define MPU_EDR_EMN_SHIFT (4) /* Bits 4-7: Error master number */ +#define MPU_EDR_EMN_MASK (15 << MPU_EDR_EMN_SHIFT) + /* Bits 8-15: Reserved */ +#define MPU_EDR_EACD_SHIFT (26) /* Bits 16-31: Error access control detail */ +#define MPU_EDR_EACD_MASK (0xffff << MPU_EDR_EACD_SHIFT) + +/* Region Descriptor n, Word 0 */ + /* Bits 0-4: Reserved */ +#define MPU_RGD_WORD0_SRTADDR_SHIFT (5) /* Bits 5-31: Start address */ +#define MPU_RGD_WORD0_SRTADDR_MASK (0xffffffe0) + +/* Region Descriptor n, Word 1 */ + /* Bits 0-4: Reserved */ +#define MPU_RGD_WORD1_ENDADDR_SHIFT (5) /* Bits 5-31: End address */ +#define MPU_RGD_WORD1_ENDADDR_MASK (0xffffffe0) + +/* Region Descriptor n, Word 2 */ + +#define MPU_RGD_MSM_RWX 0 /* R/W/X; read, write and execute allowed */ +#define MPU_RGD_MSM_RX 1 /* R/X; read and execute allowed, but no write */ +#define MPU_RGD_MSM_RW 2 /* R/W; read and write allowed, but no execute */ +#define MPU_RGD_MSM_UM 3 /* Same as user mode defined in MUM */ + +#define MPU_RGD_MUM_R 4 /* Read allowed */ +#define MPU_RGD_MUM_W 2 /* Write allowed */ +#define MPU_RGD_MUM_X 1 /* Execute allocated */ + +#define MPU_RGD_WORD2_M0UM_SHIFT (0) /* Bits 0-2: Bus master 0 user mode access control */ +#define MPU_RGD_WORD2_M0UM_MASK (7 << MPU_RGD_WORD2_M0UM_SHIFT) +#define MPU_RGD_WORD2_M0SM_SHIFT (3) /* Bits 3-4: Bus master 0 supervisor mode access control */ +#define MPU_RGD_WORD2_M0SM_MASK (3 << MPU_RGD_WORD2_M0SM_SHIFT) +#define MPU_RGD_WORD2_M0PE (1 << 5) /* Bit 5: Bus Master 0 Process Identifier Enable */ +#define MPU_RGD_WORD2_M1UM_SHIFT (6) /* Bits 6-8: Bus master 1 user mode access control */ +#define MPU_RGD_WORD2_M1UM_MASK (7 << MPU_RGD_WORD2_M1UM_SHIFT) +#define MPU_RGD_WORD2_M1SM_SHIFT (9) /* Bits 9-10: Bus master 1 supervisor mode access control */ +#define MPU_RGD_WORD2_M1SM_MASK (3 << MPU_RGD_WORD2_M1SM_SHIFT) +#define MPU_RGD_WORD2_M1PE (1 << 11) /* Bit 11: Bus Master 1 Process Identifier Enable */ +#define MPU_RGD_WORD2_M2UM_SHIFT (12) /* Bits 12-14: Bus master 2 user mode access control */ +#define MPU_RGD_WORD2_M2UM_MASK (7 << MPU_RGD_WORD2_M2UM_SHIFT) +#define MPU_RGD_WORD2_M2SM_SHIFT (15) /* Bits 15-16: Bus master 2 supervisor mode access control */ +#define MPU_RGD_WORD2_M2SM_MASK (3 << MPU_RGD_WORD2_M2SM_SHIFT) +#define MPU_RGD_WORD2_M2PE (1 << 17) /* Bit 17: Bus Master 2 Process Identifier Enable */ +#define MPU_RGD_WORD2_M3UM_SHIFT (18) /* Bits 18-20: Bus master 3 user mode access control */ +#define MPU_RGD_WORD2_M3UM_MASK (7 << MPU_RGD_WORD2_M3UM_SHIFT) +#define MPU_RGD_WORD2_M3SM_SHIFT (21) /* Bits 21-22: Bus master 3 supervisor mode access control */ +#define MPU_RGD_WORD2_M3SM_MASK (3 << MPU_RGD_WORD2_M3SM_SHIFT) +#define MPU_RGD_WORD2_M3PE (1 << 23) /* Bit 23: Bus Master 3 Process Identifier Enable */ +#define MPU_RGD_WORD2_M4WE (1 << 24) /* Bit 24: Bus master 4 write enable */ +#define MPU_RGD_WORD2_M4RE (1 << 25) /* Bit 25: Bus master 4 read enable */ +#define MPU_RGD_WORD2_M5WE (1 << 26) /* Bit 26: Bus master 5 write enable */ +#define MPU_RGD_WORD2_M5RE (1 << 27) /* Bit 27: Bus master 5 read enable */ +#define MPU_RGD_WORD2_M6WE (1 << 28) /* Bit 28: Bus master 6 write enable */ +#define MPU_RGD_WORD2_M6RE (1 << 29) /* Bit 29: Bus master 6 read enable */ +#define MPU_RGD_WORD2_M7WE (1 << 30) /* Bit 30: Bus master 7 write enable */ +#define MPU_RGD_WORD2_M7RE (1 << 31) /* Bit 31: Bus master 7 read enable */ + +/* Region Descriptor n, Word 3 */ + +#define MPU_RGD_WORD3_VLD (1 << 0) /* Bit 0: Valid */ + /* Bits 1-31: Reserved */ +/* Region Descriptor Alternate Access Control n */ + +#define MPU_RGD_RBDACC_M0UM_SHIFT (0) /* Bits 0-2: Bus master 0 user mode access control */ +#define MPU_RGD_RBDACC_M0UM_MASK (7 << MPU_RGD_RBDACC_M0UM_SHIFT) +#define MPU_RGD_RBDACC_M0SM_SHIFT (3) /* Bits 3-4: Bus master 0 supervisor mode access control */ +#define MPU_RGD_RBDACC_M0SM_MASK (3 << MPU_RGD_RBDACC_M0SM_SHIFT) + /* Bit 5: Reserved */ +#define MPU_RGD_RBDACC_M1UM_SHIFT (6) /* Bits 6-8: Bus master 1 user mode access control */ +#define MPU_RGD_RBDACC_M1UM_MASK (7 << MPU_RGD_RBDACC_M1UM_SHIFT) +#define MPU_RGD_RBDACC_M1SM_SHIFT (9) /* Bits 9-10: Bus master 1 supervisor mode access control */ +#define MPU_RGD_RBDACC_M1SM_MASK (3 << MPU_RGD_RBDACC_M1SM_SHIFT) + /* Bit 11: Reserved */ +#define MPU_RGD_RBDACC_M2UM_SHIFT (12) /* Bits 12-14: Bus master 2 user mode access control */ +#define MPU_RGD_RBDACC_M2UM_MASK (7 << MPU_RGD_RBDACC_M2UM_SHIFT) +#define MPU_RGD_RBDACC_M2SM_SHIFT (15) /* Bits 15-16: Bus master 2 supervisor mode access control */ +#define MPU_RGD_RBDACC_M2SM_MASK (3 << MPU_RGD_RBDACC_M2SM_SHIFT) + /* Bit 17: Reserved */ +#define MPU_RGD_RBDACC_M3UM_SHIFT (18) /* Bits 18-20: Bus master 3 user mode access control */ +#define MPU_RGD_RBDACC_M3UM_MASK (7 << MPU_RGD_RBDACC_M3UM_SHIFT) +#define MPU_RGD_RBDACC_M3SM_SHIFT (21) /* Bits 21-22: Bus master 3 supervisor mode access control */ +#define MPU_RGD_RBDACC_M3SM_MASK (3 << MPU_RGD_RBDACC_M3SM_SHIFT) + /* Bit 23: Reserved */ +#define MPU_RGD_RBDACC_M4WE (1 << 24) /* Bit 24: Bus master 4 write enable */ +#define MPU_RGD_RBDACC_M4RE (1 << 25) /* Bit 25: Bus master 4 read enable */ +#define MPU_RGD_RBDACC_M5WE (1 << 26) /* Bit 26: Bus master 5 write enable */ +#define MPU_RGD_RBDACC_M5RE (1 << 27) /* Bit 27: Bus master 5 read enable */ +#define MPU_RGD_RBDACC_M6WE (1 << 28) /* Bit 28: Bus master 6 write enable */ +#define MPU_RGD_RBDACC_M6RE (1 << 29) /* Bit 29: Bus master 6 read enable */ +#define MPU_RGD_RBDACC_M7WE (1 << 30) /* Bit 30: Bus master 7 write enable */ +#define MPU_RGD_RBDACC_M7RE (1 << 31) /* Bit 31: Bus master 7 read enable */ + +/**************************************************************************************************** + * Public Types + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Data + ****************************************************************************************************/ + +/**************************************************************************************************** + * Public Functions + ****************************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_MPU_H */ diff --git a/arch/arm/src/kinetis/chip/kinetis_k64pinmux.h b/arch/arm/src/kinetis/chip/kinetis_k64pinmux.h new file mode 100644 index 0000000000000000000000000000000000000000..724761a6e835cf811277655718a92c3548a32f75 --- /dev/null +++ b/arch/arm/src/kinetis/chip/kinetis_k64pinmux.h @@ -0,0 +1,624 @@ +/******************************************************************************************** + * arch/arm/src/kinetis/chip/kinetis_k64pinmux.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KINETIS_CHP_KINETIS_K64PINMUX_H +#define __ARCH_ARM_SRC_KINETIS_CHP_KINETIS_K64PINMUX_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include + +#include "chip.h" + +#ifdef KINETIS_K64 + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ +/* In most cases, there are alternative configurations for various pins. Those alternative + * pins are labeled with a suffix like _1, _2, etc. in order to distinguish them. Logic in + * the board.h file must select the correct pin configuration for the board by defining a pin + * configuration (with no suffix) that maps to the correct alternative. + * + * WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! WARNING!!! + * Additional effort is required to select specific GPIO options such as frequency, + * open-drain/push-pull, and pull-up/down! Just the basics are defined for most + * pins in the initial version of this file. + */ + +/* ADC */ + +#define PIN_ADC0_DM2 (PIN_ANALOG | PIN_PORTE | PIN3) +#define PIN_ADC0_DP2 (PIN_ANALOG | PIN_PORTE | PIN2) +#define PIN_ADC0_SE4B (PIN_ANALOG | PIN_PORTC | PIN2) +#define PIN_ADC0_SE5B (PIN_ANALOG | PIN_PORTD | PIN1) +#define PIN_ADC0_SE6B (PIN_ANALOG | PIN_PORTD | PIN5) +#define PIN_ADC0_SE7B (PIN_ANALOG | PIN_PORTD | PIN6) +#define PIN_ADC0_SE8 (PIN_ANALOG | PIN_PORTB | PIN0) +#define PIN_ADC0_SE9 (PIN_ANALOG | PIN_PORTB | PIN1) +#define PIN_ADC0_SE10 (PIN_ANALOG | PIN_PORTA | PIN7) +#define PIN_ADC0_SE11 (PIN_ANALOG | PIN_PORTA | PIN8) +#define PIN_ADC0_SE12 (PIN_ANALOG | PIN_PORTB | PIN2) +#define PIN_ADC0_SE13 (PIN_ANALOG | PIN_PORTB | PIN3) +#define PIN_ADC0_SE14 (PIN_ANALOG | PIN_PORTC | PIN0) +#define PIN_ADC0_SE15 (PIN_ANALOG | PIN_PORTC | PIN1) +#define PIN_ADC0_SE17 (PIN_ANALOG | PIN_PORTE | PIN24) +#define PIN_ADC0_SE18 (PIN_ANALOG | PIN_PORTE | PIN25) + +#define PIN_ADC1_SE4A (PIN_ANALOG | PIN_PORTE | PIN0) +#define PIN_ADC1_SE4B (PIN_ANALOG | PIN_PORTC | PIN8) +#define PIN_ADC1_SE5A (PIN_ANALOG | PIN_PORTE | PIN1) +#define PIN_ADC1_SE5B (PIN_ANALOG | PIN_PORTC | PIN9) +#define PIN_ADC1_SE6A (PIN_ANALOG | PIN_PORTE | PIN2) +#define PIN_ADC1_SE6B (PIN_ANALOG | PIN_PORTC | PIN10) +#define PIN_ADC1_SE7A (PIN_ANALOG | PIN_PORTE | PIN3) +#define PIN_ADC1_SE7B (PIN_ANALOG | PIN_PORTC | PIN11) +#define PIN_ADC1_SE8 (PIN_ANALOG | PIN_PORTB | PIN0) +#define PIN_ADC1_SE9 (PIN_ANALOG | PIN_PORTB | PIN1) +#define PIN_ADC1_SE10 (PIN_ANALOG | PIN_PORTB | PIN4) +#define PIN_ADC1_SE11 (PIN_ANALOG | PIN_PORTB | PIN5) +#define PIN_ADC1_SE12 (PIN_ANALOG | PIN_PORTB | PIN6) +#define PIN_ADC1_SE13 (PIN_ANALOG | PIN_PORTB | PIN7) +#define PIN_ADC1_SE14 (PIN_ANALOG | PIN_PORTB | PIN10) +#define PIN_ADC1_SE15 (PIN_ANALOG | PIN_PORTB | PIN11) +#define PIN_ADC1_SE17 (PIN_ANALOG | PIN_PORTA | PIN17) + +/* CAN */ + +#define PIN_CAN0_RX_1 (PIN_ALT2 | PIN_PORTA | PIN13) +#define PIN_CAN0_RX_2 (PIN_ALT2 | PIN_PORTB | PIN19) +#define PIN_CAN0_TX_1 (PIN_ALT2 | PIN_PORTA | PIN12) +#define PIN_CAN0_TX_2 (PIN_ALT2 | PIN_PORTB | PIN18) + +/* Output clock */ + +#define PIN_CLKOUT_1 (PIN_ALT5 | PIN_PORTA | PIN6) +#define PIN_CLKOUT_2 (PIN_ALT5 | PIN_PORTC | PIN3) + +/* Comparators */ + +#define PIN_CMP0_IN0 (PIN_ANALOG | PIN_PORTC | PIN6) +#define PIN_CMP0_IN1 (PIN_ANALOG | PIN_PORTC | PIN7) +#define PIN_CMP0_IN2 (PIN_ANALOG | PIN_PORTC | PIN8) +#define PIN_CMP0_IN3 (PIN_ANALOG | PIN_PORTC | PIN9) +#define PIN_CMP0_OUT_1 (PIN_ALT6 | PIN_PORTB | PIN20) +#define PIN_CMP0_OUT_2 (PIN_ALT6 | PIN_PORTC | PIN5) + +#define PIN_CMP1_IN0 (PIN_ANALOG | PIN_PORTC | PIN2) +#define PIN_CMP1_IN1 (PIN_ANALOG | PIN_PORTC | PIN3) +#define PIN_CMP1_OUT_1 (PIN_ALT6 | PIN_PORTB | PIN21) +#define PIN_CMP1_OUT_2 (PIN_ALT6 | PIN_PORTC | PIN4) + +#define PIN_CMP2_IN0 (PIN_ANALOG | PIN_PORTA | PIN12) +#define PIN_CMP2_IN1 (PIN_ANALOG | PIN_PORTA | PIN13) +#define PIN_CMP2_OUT_1 (PIN_ALT5 | PIN_PORTA | PIN5) +#define PIN_CMP2_OUT_2 (PIN_ALT6 | PIN_PORTB | PIN22) + +/* Carrier Modulator Transmittor (CMT) */ + +#define PIN_CMT_IRO (PIN_ALT2 | PIN_PORTD | PIN7) + +/* Ethernet */ + +#define PIN_ENET_1588_CLKIN (PIN_ALT2 | PIN_PORTE | PIN26) +#define PIN_ENET0_1588_TMR0_1 (PIN_ALT4 | PIN_PORTB | PIN2) +#define PIN_ENET0_1588_TMR0_2 (PIN_ALT4 | PIN_PORTC | PIN16) +#define PIN_ENET0_1588_TMR1_1 (PIN_ALT4 | PIN_PORTB | PIN3) +#define PIN_ENET0_1588_TMR1_2 (PIN_ALT4 | PIN_PORTC | PIN17) +#define PIN_ENET0_1588_TMR2_1 (PIN_ALT4 | PIN_PORTB | PIN4) +#define PIN_ENET0_1588_TMR2_2 (PIN_ALT4 | PIN_PORTC | PIN18) +#define PIN_ENET0_1588_TMR3_1 (PIN_ALT4 | PIN_PORTB | PIN5) +#define PIN_ENET0_1588_TMR3_2 (PIN_ALT4 | PIN_PORTC | PIN19) + +/* External Watchdog Monitor (EWM) */ + +#define PIN_EWM_IN_1 (PIN_ALT6 | PIN_PORTB | PIN16) +#define PIN_EWM_IN_2 (PIN_ALT6 | PIN_PORTD | PIN4) +#define PIN_EWM_IN_3 (PIN_ALT6 | PIN_PORTE | PIN25) +#define PIN_EWM_OUT_1 (PIN_ALT6 | PIN_PORTB | PIN17) +#define PIN_EWM_OUT_2 (PIN_ALT6 | PIN_PORTD | PIN5) +#define PIN_EWM_OUT_3 (PIN_ALT6 | PIN_PORTE | PIN24) + +/* FlexBus */ + +#define PIN_FB_A16 (PIN_ALT6 | PIN_PORTD | PIN8) +#define PIN_FB_A17 (PIN_ALT6 | PIN_PORTD | PIN9) +#define PIN_FB_A18 (PIN_ALT6 | PIN_PORTD | PIN10) +#define PIN_FB_A19 (PIN_ALT6 | PIN_PORTD | PIN11) +#define PIN_FB_A20 (PIN_ALT6 | PIN_PORTD | PIN12) +#define PIN_FB_A21 (PIN_ALT6 | PIN_PORTD | PIN13) +#define PIN_FB_A22 (PIN_ALT6 | PIN_PORTD | PIN14) +#define PIN_FB_A23 (PIN_ALT6 | PIN_PORTD | PIN15) +#define PIN_FB_A24 (PIN_ALT6 | PIN_PORTA | PIN29) +#define PIN_FB_A25 (PIN_ALT6 | PIN_PORTA | PIN28) +#define PIN_FB_A26 (PIN_ALT6 | PIN_PORTA | PIN27) +#define PIN_FB_A27 (PIN_ALT6 | PIN_PORTA | PIN26) +#define PIN_FB_A28 (PIN_ALT6 | PIN_PORTA | PIN25) +#define PIN_FB_A29 (PIN_ALT6 | PIN_PORTA | PIN24) +#define PIN_FB_AD0 (PIN_ALT5 | PIN_PORTD | PIN6) +#define PIN_FB_AD1 (PIN_ALT5 | PIN_PORTD | PIN5) +#define PIN_FB_AD2 (PIN_ALT5 | PIN_PORTD | PIN4) +#define PIN_FB_AD3 (PIN_ALT5 | PIN_PORTD | PIN3) +#define PIN_FB_AD4 (PIN_ALT5 | PIN_PORTD | PIN2) +#define PIN_FB_AD5 (PIN_ALT5 | PIN_PORTC | PIN10) +#define PIN_FB_AD6 (PIN_ALT5 | PIN_PORTC | PIN9) +#define PIN_FB_AD7 (PIN_ALT5 | PIN_PORTC | PIN8) +#define PIN_FB_AD8 (PIN_ALT5 | PIN_PORTC | PIN7) +#define PIN_FB_AD9 (PIN_ALT5 | PIN_PORTC | PIN6) +#define PIN_FB_AD10 (PIN_ALT5 | PIN_PORTC | PIN5) +#define PIN_FB_AD11 (PIN_ALT5 | PIN_PORTC | PIN4) +#define PIN_FB_AD12 (PIN_ALT5 | PIN_PORTC | PIN2) +#define PIN_FB_AD13 (PIN_ALT5 | PIN_PORTC | PIN1) +#define PIN_FB_AD14 (PIN_ALT5 | PIN_PORTC | PIN0) +#define PIN_FB_AD15 (PIN_ALT5 | PIN_PORTB | PIN18) +#define PIN_FB_AD16 (PIN_ALT5 | PIN_PORTB | PIN17) +#define PIN_FB_AD17 (PIN_ALT5 | PIN_PORTB | PIN16) +#define PIN_FB_AD18 (PIN_ALT5 | PIN_PORTB | PIN11) +#define PIN_FB_AD19 (PIN_ALT5 | PIN_PORTB | PIN10) +#define PIN_FB_AD20 (PIN_ALT5 | PIN_PORTB | PIN9) +#define PIN_FB_AD21 (PIN_ALT5 | PIN_PORTB | PIN8) +#define PIN_FB_AD22 (PIN_ALT5 | PIN_PORTB | PIN7) +#define PIN_FB_AD23 (PIN_ALT5 | PIN_PORTB | PIN6) +#define PIN_FB_AD24 (PIN_ALT5 | PIN_PORTC | PIN15) +#define PIN_FB_AD25 (PIN_ALT5 | PIN_PORTC | PIN14) +#define PIN_FB_AD26 (PIN_ALT5 | PIN_PORTC | PIN13) +#define PIN_FB_AD27 (PIN_ALT5 | PIN_PORTC | PIN12) +#define PIN_FB_AD28 (PIN_ALT5 | PIN_PORTB | PIN23) +#define PIN_FB_AD29 (PIN_ALT5 | PIN_PORTB | PIN22) +#define PIN_FB_AD30 (PIN_ALT5 | PIN_PORTB | PIN21) +#define PIN_FB_AD31 (PIN_ALT5 | PIN_PORTB | PIN20) +#define PIN_FB_ALE (PIN_ALT5 | PIN_PORTD | PIN0) +#define PIN_FB_BE15_8_BLS23_16 (PIN_ALT5 | PIN_PORTC | PIN18) +#define PIN_FB_BE23_16_BLS15_8 (PIN_ALT5 | PIN_PORTC | PIN16) +#define PIN_FB_BE31_24_BLS7_0 (PIN_ALT5 | PIN_PORTC | PIN17) +#define PIN_FB_BE7_0_BLS31_24 (PIN_ALT5 | PIN_PORTC | PIN19) +#define PIN_FB_CS0 (PIN_ALT5 | PIN_PORTD | PIN1) +#define PIN_FB_CS1 (PIN_ALT5 | PIN_PORTD | PIN0) +#define PIN_FB_CS2 (PIN_ALT5 | PIN_PORTC | PIN18) +#define PIN_FB_CS3 (PIN_ALT5 | PIN_PORTC | PIN19) +#define PIN_FB_CS4 (PIN_ALT5 | PIN_PORTC | PIN17) +#define PIN_FB_CS5 (PIN_ALT5 | PIN_PORTC | PIN16) +#define PIN_FB_OE (PIN_ALT5 | PIN_PORTB | PIN19) +#define PIN_FB_RW (PIN_ALT5 | PIN_PORTC | PIN11) +#define PIN_FB_TA (PIN_ALT6 | PIN_PORTC | PIN19) +#define PIN_FB_TBST (PIN_ALT5 | PIN_PORTC | PIN18) +#define PIN_FB_TS (PIN_ALT5 | PIN_PORTD | PIN0) +#define PIN_FB_TSIZ0 (PIN_ALT5 | PIN_PORTC | PIN17) +#define PIN_FB_TSIZ1 (PIN_ALT5 | PIN_PORTC | PIN16) + +/* FlexTimer Module (FTM) */ + +#define PIN_FTM_CLKIN0_1 (PIN_ALT4 | PIN_PORTA | PIN18) +#define PIN_FTM_CLKIN0_2 (PIN_ALT4 | PIN_PORTB | PIN16) +#define PIN_FTM_CLKIN1_1 (PIN_ALT4 | PIN_PORTA | PIN19) +#define PIN_FTM_CLKIN1_2 (PIN_ALT4 | PIN_PORTB | PIN17) + +#define PIN_FTM0_CH0_1 (PIN_ALT3 | PIN_PORTA | PIN3) +#define PIN_FTM0_CH0_2 (PIN_ALT4 | PIN_PORTC | PIN1) +#define PIN_FTM0_CH1_1 (PIN_ALT3 | PIN_PORTA | PIN4) +#define PIN_FTM0_CH1_2 (PIN_ALT4 | PIN_PORTC | PIN2) +#define PIN_FTM0_CH2_1 (PIN_ALT3 | PIN_PORTA | PIN5) +#define PIN_FTM0_CH2_2 (PIN_ALT4 | PIN_PORTC | PIN3) +#define PIN_FTM0_CH2_3 (PIN_ALT7 | PIN_PORTC | PIN5) +#define PIN_FTM0_CH3_1 (PIN_ALT3 | PIN_PORTA | PIN6) +#define PIN_FTM0_CH3_2 (PIN_ALT4 | PIN_PORTC | PIN4) +#define PIN_FTM0_CH4_1 (PIN_ALT3 | PIN_PORTA | PIN7) +#define PIN_FTM0_CH4_2 (PIN_ALT4 | PIN_PORTB | PIN12) +#define PIN_FTM0_CH4_3 (PIN_ALT4 | PIN_PORTD | PIN4) +#define PIN_FTM0_CH5_1 (PIN_ALT3 | PIN_PORTA | PIN0) +#define PIN_FTM0_CH5_2 (PIN_ALT4 | PIN_PORTB | PIN13) +#define PIN_FTM0_CH5_3 (PIN_ALT4 | PIN_PORTD | PIN5) +#define PIN_FTM0_CH6_1 (PIN_ALT3 | PIN_PORTA | PIN1) +#define PIN_FTM0_CH6_2 (PIN_ALT4 | PIN_PORTD | PIN6) +#define PIN_FTM0_CH7_1 (PIN_ALT3 | PIN_PORTA | PIN2) +#define PIN_FTM0_CH7_2 (PIN_ALT4 | PIN_PORTD | PIN7) +#define PIN_FTM0_FLT0_1 (PIN_ALT6 | PIN_PORTB | PIN3) +#define PIN_FTM0_FLT0_2 (PIN_ALT6 | PIN_PORTD | PIN6) +#define PIN_FTM0_FLT1_1 (PIN_ALT6 | PIN_PORTB | PIN10) +#define PIN_FTM0_FLT1_2 (PIN_ALT6 | PIN_PORTD | PIN7) +#define PIN_FTM0_FLT2_1 (PIN_ALT3 | PIN_PORTA | PIN18) +#define PIN_FTM0_FLT2_2 (PIN_ALT6 | PIN_PORTB | PIN11) +#define PIN_FTM0_FLT3 (PIN_ALT6 | PIN_PORTB | PIN2) + +#define PIN_FTM1_CH0_1 (PIN_ALT3 | PIN_PORTA | PIN12) +#define PIN_FTM1_CH0_2 (PIN_ALT3 | PIN_PORTA | PIN8) +#define PIN_FTM1_CH0_3 (PIN_ALT3 | PIN_PORTB | PIN0) +#define PIN_FTM1_CH0_4 (PIN_ALT3 | PIN_PORTB | PIN12) +#define PIN_FTM1_CH1_1 (PIN_ALT3 | PIN_PORTA | PIN13) +#define PIN_FTM1_CH1_2 (PIN_ALT3 | PIN_PORTA | PIN9) +#define PIN_FTM1_CH1_3 (PIN_ALT3 | PIN_PORTB | PIN1) +#define PIN_FTM1_CH1_4 (PIN_ALT3 | PIN_PORTB | PIN13) +#define PIN_FTM1_FLT0_1 (PIN_ALT3 | PIN_PORTA | PIN19) +#define PIN_FTM1_FLT0_2 (PIN_ALT6 | PIN_PORTB | PIN4) +#define PIN_FTM1_QD_PHA_1 (PIN_ALT6 | PIN_PORTA | PIN8) +#define PIN_FTM1_QD_PHA_2 (PIN_ALT6 | PIN_PORTB | PIN0) +#define PIN_FTM1_QD_PHA_3 (PIN_ALT6 | PIN_PORTB | PIN12) +#define PIN_FTM1_QD_PHA_4 (PIN_ALT7 | PIN_PORTA | PIN12) +#define PIN_FTM1_QD_PHB_1 (PIN_ALT6 | PIN_PORTA | PIN9) +#define PIN_FTM1_QD_PHB_2 (PIN_ALT6 | PIN_PORTB | PIN1) +#define PIN_FTM1_QD_PHB_3 (PIN_ALT6 | PIN_PORTB | PIN13) +#define PIN_FTM1_QD_PHB_4 (PIN_ALT7 | PIN_PORTA | PIN13) + +#define PIN_FTM2_CH0_1 (PIN_ALT3 | PIN_PORTA | PIN10) +#define PIN_FTM2_CH0_2 (PIN_ALT3 | PIN_PORTB | PIN18) +#define PIN_FTM2_CH1_1 (PIN_ALT3 | PIN_PORTA | PIN11) +#define PIN_FTM2_CH1_2 (PIN_ALT3 | PIN_PORTB | PIN19) +#define PIN_FTM2_FLT0_1 (PIN_ALT6 | PIN_PORTB | PIN5) +#define PIN_FTM2_FLT0_2 (PIN_ALT6 | PIN_PORTC | PIN9) +#define PIN_FTM2_QD_PHA_1 (PIN_ALT6 | PIN_PORTA | PIN10) +#define PIN_FTM2_QD_PHA_2 (PIN_ALT6 | PIN_PORTB | PIN18) +#define PIN_FTM2_QD_PHB_1 (PIN_ALT6 | PIN_PORTA | PIN11) +#define PIN_FTM2_QD_PHB_2 (PIN_ALT6 | PIN_PORTB | PIN19) + +#define PIN_FTM3_CH0_1 (PIN_ALT4 | PIN_PORTD | PIN0) +#define PIN_FTM3_CH0_2 (PIN_ALT6 | PIN_PORTE | PIN5) +#define PIN_FTM3_CH1_1 (PIN_ALT4 | PIN_PORTD | PIN1) +#define PIN_FTM3_CH1_2 (PIN_ALT6 | PIN_PORTE | PIN6) +#define PIN_FTM3_CH2_1 (PIN_ALT4 | PIN_PORTD | PIN2) +#define PIN_FTM3_CH2_2 (PIN_ALT6 | PIN_PORTE | PIN7) +#define PIN_FTM3_CH3_1 (PIN_ALT4 | PIN_PORTD | PIN3) +#define PIN_FTM3_CH3_2 (PIN_ALT6 | PIN_PORTE | PIN8) +#define PIN_FTM3_CH4_1 (PIN_ALT3 | PIN_PORTC | PIN8) +#define PIN_FTM3_CH4_2 (PIN_ALT6 | PIN_PORTE | PIN9) +#define PIN_FTM3_CH5_1 (PIN_ALT3 | PIN_PORTC | PIN9) +#define PIN_FTM3_CH5_2 (PIN_ALT6 | PIN_PORTE | PIN10) +#define PIN_FTM3_CH6_1 (PIN_ALT3 | PIN_PORTC | PIN10) +#define PIN_FTM3_CH6_2 (PIN_ALT6 | PIN_PORTE | PIN11) +#define PIN_FTM3_CH7_1 (PIN_ALT3 | PIN_PORTC | PIN11) +#define PIN_FTM3_CH7_2 (PIN_ALT6 | PIN_PORTE | PIN12) +#define PIN_FTM3_FLT0_1 (PIN_ALT3 | PIN_PORTD | PIN12) +#define PIN_FTM3_FLT0_2 (PIN_ALT6 | PIN_PORTC | PIN12) + +/* I2C */ + +#define PIN_I2C0_SCL_1 (PIN_ALT2 | PIN_PORTB | PIN0) +#define PIN_I2C0_SCL_2 (PIN_ALT2 | PIN_PORTB | PIN2) +#define PIN_I2C0_SCL_3 (PIN_ALT2 | PIN_PORTD | PIN8) +#define PIN_I2C0_SCL_4 (PIN_ALT5 | PIN_PORTE | PIN24) +#define PIN_I2C0_SCL_5 (PIN_ALT7 | PIN_PORTD | PIN2) +#define PIN_I2C0_SDA_1 (PIN_ALT2 | PIN_PORTB | PIN1) +#define PIN_I2C0_SDA_2 (PIN_ALT2 | PIN_PORTB | PIN3) +#define PIN_I2C0_SDA_3 (PIN_ALT2 | PIN_PORTD | PIN9) +#define PIN_I2C0_SDA_4 (PIN_ALT5 | PIN_PORTE | PIN25) +#define PIN_I2C0_SDA_5 (PIN_ALT7 | PIN_PORTD | PIN3) + +#define PIN_I2C1_SCL_1 (PIN_ALT2 | PIN_PORTC | PIN10) +#define PIN_I2C1_SCL_2 (PIN_ALT6 | PIN_PORTE | PIN1) +#define PIN_I2C1_SDA_1 (PIN_ALT2 | PIN_PORTC | PIN11) +#define PIN_I2C1_SDA_2 (PIN_ALT6 | PIN_PORTE | PIN0) + +#define PIN_I2C2_SCL_1 (PIN_ALT5 | PIN_PORTA | PIN12) +#define PIN_I2C2_SCL_2 (PIN_ALT5 | PIN_PORTA | PIN14) +#define PIN_I2C2_SDA_1 (PIN_ALT5 | PIN_PORTA | PIN11) +#define PIN_I2C2_SDA_2 (PIN_ALT5 | PIN_PORTA | PIN13) + +/* I2S */ + +#define PIN_I2S0_MCLK_1 (PIN_ALT4 | PIN_PORTC | PIN8) +#define PIN_I2S0_MCLK_2 (PIN_ALT4 | PIN_PORTE | PIN6) +#define PIN_I2S0_MCLK_3 (PIN_ALT6 | PIN_PORTA | PIN17) +#define PIN_I2S0_MCLK_4 (PIN_ALT6 | PIN_PORTC | PIN6) +#define PIN_I2S0_RX_BCLK_1 (PIN_ALT4 | PIN_PORTC | PIN6) +#define PIN_I2S0_RX_BCLK_2 (PIN_ALT4 | PIN_PORTC | PIN9) +#define PIN_I2S0_RX_BCLK_3 (PIN_ALT4 | PIN_PORTE | PIN9) +#define PIN_I2S0_RX_BCLK_4 (PIN_ALT6 | PIN_PORTA | PIN14) +#define PIN_I2S0_RX_FS_1 (PIN_ALT4 | PIN_PORTC | PIN10) +#define PIN_I2S0_RX_FS_2 (PIN_ALT4 | PIN_PORTC | PIN7) +#define PIN_I2S0_RX_FS_3 (PIN_ALT4 | PIN_PORTE | PIN8) +#define PIN_I2S0_RX_FS_4 (PIN_ALT6 | PIN_PORTA | PIN16) +#define PIN_I2S0_RXD0_1 (PIN_ALT4 | PIN_PORTC | PIN5) +#define PIN_I2S0_RXD0_2 (PIN_ALT4 | PIN_PORTE | PIN7) +#define PIN_I2S0_RXD0_3 (PIN_ALT6 | PIN_PORTA | PIN15) +#define PIN_I2S0_RXD1_1 (PIN_ALT2 | PIN_PORTE | PIN8) +#define PIN_I2S0_RXD1_2 (PIN_ALT4 | PIN_PORTC | PIN11) +#define PIN_I2S0_RXD1_3 (PIN_ALT7 | PIN_PORTA | PIN16) +#define PIN_I2S0_TX_BCLK_1 (PIN_ALT4 | PIN_PORTB | PIN18) +#define PIN_I2S0_TX_BCLK_2 (PIN_ALT4 | PIN_PORTE | PIN12) +#define PIN_I2S0_TX_BCLK_3 (PIN_ALT6 | PIN_PORTA | PIN5) +#define PIN_I2S0_TX_BCLK_4 (PIN_ALT6 | PIN_PORTC | PIN3) +#define PIN_I2S0_TX_FS_1 (PIN_ALT4 | PIN_PORTB | PIN19) +#define PIN_I2S0_TX_FS_2 (PIN_ALT4 | PIN_PORTE | PIN11) +#define PIN_I2S0_TX_FS_3 (PIN_ALT6 | PIN_PORTA | PIN13) +#define PIN_I2S0_TX_FS_4 (PIN_ALT6 | PIN_PORTC | PIN2) +#define PIN_I2S0_TXD0_1 (PIN_ALT4 | PIN_PORTE | PIN10) +#define PIN_I2S0_TXD0_2 (PIN_ALT6 | PIN_PORTA | PIN12) +#define PIN_I2S0_TXD0_3 (PIN_ALT6 | PIN_PORTC | PIN1) +#define PIN_I2S0_TXD1_1 (PIN_ALT2 | PIN_PORTE | PIN9) +#define PIN_I2S0_TXD1_2 (PIN_ALT6 | PIN_PORTC | PIN0) +#define PIN_I2S0_TXD1_3 (PIN_ALT7 | PIN_PORTA | PIN14) + +/* JTAG */ + +#define PIN_JTAG_TCLK (PIN_ALT7 | PIN_PORTA | PIN0) +#define PIN_JTAG_TDI (PIN_ALT7 | PIN_PORTA | PIN1) +#define PIN_JTAG_TDO (PIN_ALT7 | PIN_PORTA | PIN2) +#define PIN_JTAG_TMS (PIN_ALT7 | PIN_PORTA | PIN3) +#define PIN_JTAG_TRST (PIN_ALT7 | PIN_PORTA | PIN5) + +/* Low-leakage wakeup module (LLWU, actually GPIO configurations) */ + +#define PIN_LLWU_P0 (PIN_ALT1 | PIN_PORTE | PIN1) +#define PIN_LLWU_P1 (PIN_ALT1 | PIN_PORTE | PIN2) +#define PIN_LLWU_P2 (PIN_ALT1 | PIN_PORTE | PIN4) +#define PIN_LLWU_P3 (PIN_ALT1 | PIN_PORTA | PIN4) +#define PIN_LLWU_P4 (PIN_ALT1 | PIN_PORTA | PIN13) +#define PIN_LLWU_P5 (PIN_ALT1 | PIN_PORTB | PIN0) +#define PIN_LLWU_P6 (PIN_ALT1 | PIN_PORTC | PIN1) +#define PIN_LLWU_P7 (PIN_ALT1 | PIN_PORTC | PIN3) +#define PIN_LLWU_P8 (PIN_ALT1 | PIN_PORTC | PIN4) +#define PIN_LLWU_P9 (PIN_ALT1 | PIN_PORTC | PIN5) +#define PIN_LLWU_P10 (PIN_ALT1 | PIN_PORTC | PIN6) +#define PIN_LLWU_P11 (PIN_ALT1 | PIN_PORTC | PIN11) +#define PIN_LLWU_P12 (PIN_ALT1 | PIN_PORTD | PIN0) +#define PIN_LLWU_P13 (PIN_ALT1 | PIN_PORTD | PIN2) +#define PIN_LLWU_P14 (PIN_ALT1 | PIN_PORTD | PIN4) +#define PIN_LLWU_P15 (PIN_ALT1 | PIN_PORTD | PIN6) + +/* Low-Power Timer (LPTMR) */ + +#define PIN_LPTMR0_ALT1 (PIN_ALT6 | PIN_PORTA | PIN19) +#define PIN_LPTMR0_ALT2 (PIN_ALT3 | PIN_PORTC | PIN5) + +/* MII */ + +#define PIN_MII0_COL (PIN_ALT4 | PIN_PORTA | PIN29) +#define PIN_MII0_CRS (PIN_ALT4 | PIN_PORTA | PIN27) +#define PIN_MII0_MDC (PIN_ALT4 | PIN_PORTB | PIN1) +#define PIN_MII0_MDIO (PIN_ALT4 | PIN_PORTB | PIN0) +#define PIN_MII0_RXCLK (PIN_ALT4 | PIN_PORTA | PIN11) +#define PIN_MII0_RXD0 (PIN_ALT4 | PIN_PORTA | PIN13) +#define PIN_MII0_RXD1 (PIN_ALT4 | PIN_PORTA | PIN12) +#define PIN_MII0_RXD2 (PIN_ALT4 | PIN_PORTA | PIN10) +#define PIN_MII0_RXD3 (PIN_ALT4 | PIN_PORTA | PIN9) +#define PIN_MII0_RXDV (PIN_ALT4 | PIN_PORTA | PIN14) +#define PIN_MII0_RXER (PIN_ALT4 | PIN_PORTA | PIN5) +#define PIN_MII0_TXCLK (PIN_ALT4 | PIN_PORTA | PIN25) +#define PIN_MII0_TXD0 (PIN_ALT4 | PIN_PORTA | PIN16) +#define PIN_MII0_TXD1 (PIN_ALT4 | PIN_PORTA | PIN17) +#define PIN_MII0_TXD2 (PIN_ALT4 | PIN_PORTA | PIN24) +#define PIN_MII0_TXD3 (PIN_ALT4 | PIN_PORTA | PIN26) +#define PIN_MII0_TXEN (PIN_ALT4 | PIN_PORTA | PIN15) +#define PIN_MII0_TXER (PIN_ALT4 | PIN_PORTA | PIN28) + +/* NMI */ + +#define PIN_NMI (PIN_ALT7 | PIN_PORTA | PIN4) + +/* Programmable Delay Block (PDB) */ + +#define PIN_PDB0_EXTRG_1 (PIN_ALT3 | PIN_PORTC | PIN0) +#define PIN_PDB0_EXTRG_2 (PIN_ALT3 | PIN_PORTC | PIN6) + +/* RMII */ + +#define PIN_RMII0_CRS_DV (PIN_ALT4 | PIN_PORTA | PIN14) +#define PIN_RMII0_MDC (PIN_ALT4 | PIN_PORTB | PIN1) +#define PIN_RMII0_MDIO (PIN_ALT4 | PIN_PORTB | PIN0) +#define PIN_RMII0_RXD0 (PIN_ALT4 | PIN_PORTA | PIN13) +#define PIN_RMII0_RXD1 (PIN_ALT4 | PIN_PORTA | PIN12) +#define PIN_RMII0_RXER (PIN_ALT4 | PIN_PORTA | PIN5) +#define PIN_RMII0_TXD0 (PIN_ALT4 | PIN_PORTA | PIN16) +#define PIN_RMII0_TXD1 (PIN_ALT4 | PIN_PORTA | PIN17) +#define PIN_RMII0_TXEN (PIN_ALT4 | PIN_PORTA | PIN15) + +/* Real-Time Clock (RTC) */ + +#define PIN_RTC_CLKOUT_1 (PIN_ALT6 | PIN_PORTE | PIN26) +#define PIN_RTC_CLKOUT_2 (PIN_ALT7 | PIN_PORTE | PIN0) + +/* Secured digital host controller (SDHC) */ + +#define PIN_SDHC0_CLKIN (PIN_ALT4 | PIN_PORTD | PIN11) +#define PIN_SDHC0_CMD (PIN_ALT4 | PIN_PORTE | PIN3) +#define PIN_SDHC0_D0 (PIN_ALT4 | PIN_PORTE | PIN1) +#define PIN_SDHC0_D1 (PIN_ALT4 | PIN_PORTE | PIN0) +#define PIN_SDHC0_D2 (PIN_ALT4 | PIN_PORTE | PIN5) +#define PIN_SDHC0_D3 (PIN_ALT4 | PIN_PORTE | PIN4) +#define PIN_SDHC0_D4 (PIN_ALT4 | PIN_PORTD | PIN12) +#define PIN_SDHC0_D5 (PIN_ALT4 | PIN_PORTD | PIN13) +#define PIN_SDHC0_D6 (PIN_ALT4 | PIN_PORTD | PIN14) +#define PIN_SDHC0_D7 (PIN_ALT4 | PIN_PORTD | PIN15) +#define PIN_SDHC0_DCLK (PIN_ALT4 | PIN_PORTE | PIN2) + +/* SPI */ + +#define PIN_SPI0_PCS0_1 (PIN_ALT2 | PIN_PORTA | PIN14) +#define PIN_SPI0_PCS0_2 (PIN_ALT2 | PIN_PORTC | PIN4) +#define PIN_SPI0_PCS0_3 (PIN_ALT2 | PIN_PORTD | PIN0) +#define PIN_SPI0_PCS1_1 (PIN_ALT2 | PIN_PORTC | PIN3) +#define PIN_SPI0_PCS1_2 (PIN_ALT2 | PIN_PORTD | PIN4) +#define PIN_SPI0_PCS2_1 (PIN_ALT2 | PIN_PORTC | PIN2) +#define PIN_SPI0_PCS2_3 (PIN_ALT2 | PIN_PORTD | PIN5) +#define PIN_SPI0_PCS3_1 (PIN_ALT2 | PIN_PORTC | PIN1) +#define PIN_SPI0_PCS3_2 (PIN_ALT2 | PIN_PORTD | PIN6) +#define PIN_SPI0_PCS4 (PIN_ALT2 | PIN_PORTC | PIN0) +#define PIN_SPI0_PCS5 (PIN_ALT3 | PIN_PORTB | PIN23) +#define PIN_SPI0_SCK_1 (PIN_ALT2 | PIN_PORTA | PIN15) +#define PIN_SPI0_SCK_2 (PIN_ALT2 | PIN_PORTC | PIN5) +#define PIN_SPI0_SCK_3 (PIN_ALT2 | PIN_PORTD | PIN1) +#define PIN_SPI0_SIN_1 (PIN_ALT2 | PIN_PORTA | PIN17) +#define PIN_SPI0_SIN_2 (PIN_ALT2 | PIN_PORTC | PIN7) +#define PIN_SPI0_SIN_3 (PIN_ALT2 | PIN_PORTD | PIN3) +#define PIN_SPI0_SOUT_1 (PIN_ALT2 | PIN_PORTA | PIN16) +#define PIN_SPI0_SOUT_2 (PIN_ALT2 | PIN_PORTC | PIN6) +#define PIN_SPI0_SOUT_3 (PIN_ALT2 | PIN_PORTD | PIN2) + +#define PIN_SPI1_PCS0_1 (PIN_ALT2 | PIN_PORTB | PIN10) +#define PIN_SPI1_PCS0_2 (PIN_ALT2 | PIN_PORTE | PIN4) +#define PIN_SPI1_PCS0_3 (PIN_ALT7 | PIN_PORTD | PIN4) +#define PIN_SPI1_PCS1_1 (PIN_ALT2 | PIN_PORTB | PIN9) +#define PIN_SPI1_PCS1_2 (PIN_ALT2 | PIN_PORTE | PIN0) +#define PIN_SPI1_PCS2 (PIN_ALT2 | PIN_PORTE | PIN5) +#define PIN_SPI1_PCS3 (PIN_ALT2 | PIN_PORTE | PIN6) +#define PIN_SPI1_SCK_1 (PIN_ALT2 | PIN_PORTB | PIN11) +#define PIN_SPI1_SCK_2 (PIN_ALT2 | PIN_PORTE | PIN2) +#define PIN_SPI1_SCK_3 (PIN_ALT7 | PIN_PORTD | PIN5) +#define PIN_SPI1_SIN_1 (PIN_ALT2 | PIN_PORTB | PIN17) +#define PIN_SPI1_SIN_2 (PIN_ALT2 | PIN_PORTE | PIN3) +#define PIN_SPI1_SIN_3 (PIN_ALT7 | PIN_PORTD | PIN7) +#define PIN_SPI1_SIN_4 (PIN_ALT7 | PIN_PORTE | PIN1) +#define PIN_SPI1_SOUT_1 (PIN_ALT2 | PIN_PORTB | PIN16) +#define PIN_SPI1_SOUT_2 (PIN_ALT2 | PIN_PORTE | PIN1) +#define PIN_SPI1_SOUT_3 (PIN_ALT7 | PIN_PORTD | PIN6) +#define PIN_SPI1_SOUT_4 (PIN_ALT7 | PIN_PORTE | PIN3) + +#define PIN_SPI2_PCS0_1 (PIN_ALT2 | PIN_PORTB | PIN20) +#define PIN_SPI2_PCS0_2 (PIN_ALT2 | PIN_PORTD | PIN11) +#define PIN_SPI2_PCS1 (PIN_ALT2 | PIN_PORTD | PIN15) +#define PIN_SPI2_SCK_1 (PIN_ALT2 | PIN_PORTB | PIN21) +#define PIN_SPI2_SCK_2 (PIN_ALT2 | PIN_PORTD | PIN12) +#define PIN_SPI2_SIN_1 (PIN_ALT2 | PIN_PORTB | PIN23) +#define PIN_SPI2_SIN_2 (PIN_ALT2 | PIN_PORTD | PIN14) +#define PIN_SPI2_SOUT_1 (PIN_ALT2 | PIN_PORTB | PIN22) +#define PIN_SPI2_SOUT_2 (PIN_ALT2 | PIN_PORTD | PIN13) + +/* SWD */ + +#define PIN_SWD_CLK (PIN_ALT7 | PIN_PORTA | PIN0) +#define PIN_SWD_DIO (PIN_ALT7 | PIN_PORTA | PIN3) + +/* Trace */ + +#define PIN_TRACE_CLKOUT_1 (PIN_ALT5 | PIN_PORTE | PIN0) +#define PIN_TRACE_CLKOUT_2 (PIN_ALT7 | PIN_PORTA | PIN6) +#define PIN_TRACE_D0_1 (PIN_ALT5 | PIN_PORTE | PIN4) +#define PIN_TRACE_D0_2 (PIN_ALT7 | PIN_PORTA | PIN10) +#define PIN_TRACE_D1_1 (PIN_ALT5 | PIN_PORTE | PIN3) +#define PIN_TRACE_D1_2 (PIN_ALT7 | PIN_PORTA | PIN9) +#define PIN_TRACE_D2_1 (PIN_ALT5 | PIN_PORTE | PIN2) +#define PIN_TRACE_D2_2 (PIN_ALT7 | PIN_PORTA | PIN8) +#define PIN_TRACE_D3_1 (PIN_ALT5 | PIN_PORTE | PIN1) +#define PIN_TRACE_D3_2 (PIN_ALT7 | PIN_PORTA | PIN7) +#define PIN_TRACE_SWO (PIN_ALT7 | PIN_PORTA | PIN2) + +/* UARTs */ + +#define PIN_UART0_COL_1 (PIN_ALT2 | PIN_PORTA | PIN0) +#define PIN_UART0_COL_2 (PIN_ALT3 | PIN_PORTA | PIN16) +#define PIN_UART0_COL_3 (PIN_ALT3 | PIN_PORTB | PIN3) +#define PIN_UART0_COL_4 (PIN_ALT3 | PIN_PORTD | PIN5) +#define PIN_UART0_CTS_1 (PIN_ALT2 | PIN_PORTA | PIN0) +#define PIN_UART0_CTS_2 (PIN_ALT3 | PIN_PORTA | PIN16) +#define PIN_UART0_CTS_3 (PIN_ALT3 | PIN_PORTB | PIN3) +#define PIN_UART0_CTS_4 (PIN_ALT3 | PIN_PORTD | PIN5) +#define PIN_UART0_RTS_1 (PIN_ALT2 | PIN_PORTA | PIN3) +#define PIN_UART0_RTS_2 (PIN_ALT3 | PIN_PORTA | PIN17) +#define PIN_UART0_RTS_3 (PIN_ALT3 | PIN_PORTB | PIN2) +#define PIN_UART0_RTS_4 (PIN_ALT3 | PIN_PORTD | PIN4) +#define PIN_UART0_RX_1 (PIN_ALT2 | PIN_PORTA | PIN1) +#define PIN_UART0_RX_2 (PIN_ALT3 | PIN_PORTA | PIN15) +#define PIN_UART0_RX_3 (PIN_ALT3 | PIN_PORTB | PIN16) +#define PIN_UART0_RX_4 (PIN_ALT3 | PIN_PORTD | PIN6) +#define PIN_UART0_TX_1 (PIN_ALT2 | PIN_PORTA | PIN2) +#define PIN_UART0_TX_2 (PIN_ALT3 | PIN_PORTA | PIN14) +#define PIN_UART0_TX_3 (PIN_ALT3 | PIN_PORTB | PIN17) +#define PIN_UART0_TX_4 (PIN_ALT3 | PIN_PORTD | PIN7) + +#define PIN_UART1_CTS_1 (PIN_ALT3 | PIN_PORTC | PIN2) +#define PIN_UART1_CTS_2 (PIN_ALT3 | PIN_PORTE | PIN2) +#define PIN_UART1_RTS_1 (PIN_ALT3 | PIN_PORTC | PIN1) +#define PIN_UART1_RTS_2 (PIN_ALT3 | PIN_PORTE | PIN3) +#define PIN_UART1_RX_1 (PIN_ALT3 | PIN_PORTC | PIN3) +#define PIN_UART1_RX_2 (PIN_ALT3 | PIN_PORTE | PIN1) +#define PIN_UART1_TX_1 (PIN_ALT3 | PIN_PORTC | PIN4) +#define PIN_UART1_TX_2 (PIN_ALT3 | PIN_PORTE | PIN0) + +#define PIN_UART2_CTS (PIN_ALT3 | PIN_PORTD | PIN1) +#define PIN_UART2_RTS (PIN_ALT3 | PIN_PORTD | PIN0) +#define PIN_UART2_RX (PIN_ALT3 | PIN_PORTD | PIN2) +#define PIN_UART2_TX (PIN_ALT3 | PIN_PORTD | PIN3) + +#define PIN_UART3_CTS_1 (PIN_ALT2 | PIN_PORTB | PIN13) +#define PIN_UART3_CTS_2 (PIN_ALT3 | PIN_PORTB | PIN9) +#define PIN_UART3_CTS_3 (PIN_ALT3 | PIN_PORTC | PIN19) +#define PIN_UART3_CTS_4 (PIN_ALT3 | PIN_PORTE | PIN6) +#define PIN_UART3_RTS_1 (PIN_ALT2 | PIN_PORTB | PIN12) +#define PIN_UART3_RTS_2 (PIN_ALT3 | PIN_PORTB | PIN8) +#define PIN_UART3_RTS_3 (PIN_ALT3 | PIN_PORTC | PIN18) +#define PIN_UART3_RTS_4 (PIN_ALT3 | PIN_PORTE | PIN7) +#define PIN_UART3_RX_1 (PIN_ALT3 | PIN_PORTB | PIN10) +#define PIN_UART3_RX_2 (PIN_ALT3 | PIN_PORTC | PIN16) +#define PIN_UART3_RX_3 (PIN_ALT3 | PIN_PORTE | PIN5) +#define PIN_UART3_TX_1 (PIN_ALT3 | PIN_PORTB | PIN11) +#define PIN_UART3_TX_2 (PIN_ALT3 | PIN_PORTC | PIN17) +#define PIN_UART3_TX_3 (PIN_ALT3 | PIN_PORTE | PIN4) + +#define PIN_UART4_CTS_1 (PIN_ALT3 | PIN_PORTC | PIN13) +#define PIN_UART4_CTS_2 (PIN_ALT3 | PIN_PORTE | PIN26) +#define PIN_UART4_RTS_1 (PIN_ALT3 | PIN_PORTC | PIN12) +#define PIN_UART4_RTS_2 (PIN_ALT3 | PIN_PORTE | PIN27) +#define PIN_UART4_RX_1 (PIN_ALT3 | PIN_PORTC | PIN14) +#define PIN_UART4_RX_2 (PIN_ALT3 | PIN_PORTE | PIN25) +#define PIN_UART4_TX_1 (PIN_ALT3 | PIN_PORTC | PIN15) +#define PIN_UART4_TX_2 (PIN_ALT3 | PIN_PORTE | PIN24) + +#define PIN_UART5_CTS_1 (PIN_ALT3 | PIN_PORTD | PIN11) +#define PIN_UART5_CTS_2 (PIN_ALT3 | PIN_PORTE | PIN10) +#define PIN_UART5_RTS_1 (PIN_ALT3 | PIN_PORTD | PIN10) +#define PIN_UART5_RTS_2 (PIN_ALT3 | PIN_PORTE | PIN11) +#define PIN_UART5_RX_1 (PIN_ALT3 | PIN_PORTD | PIN8) +#define PIN_UART5_RX_2 (PIN_ALT3 | PIN_PORTE | PIN9) +#define PIN_UART5_TX_1 (PIN_ALT3 | PIN_PORTD | PIN9) +#define PIN_UART5_TX_2 (PIN_ALT3 | PIN_PORTE | PIN8) + +/* USB */ + +#define PIN_USB_CLKIN_1 (PIN_ALT2 | PIN_PORTA | PIN5) +#define PIN_USB_CLKIN_2 (PIN_ALT7 | PIN_PORTE | PIN26) +#define PIN_USB_SOF_OUT_1 (PIN_ALT3 | PIN_PORTC | PIN7) +#define PIN_USB_SOF_OUT_2 (PIN_ALT4 | PIN_PORTC | PIN0) +#define PIN_USB_SOF_OUT_3 (PIN_ALT7 | PIN_PORTE | PIN6) + +/* External Crystal */ + +#define PIN_EXTAL0 (PIN_ANALOG | PIN_PORTA | PIN18) +#define PIN_XTAL0 (PIN_ANALOG | PIN_PORTA | PIN19) + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +/******************************************************************************************** + * Public Data + ********************************************************************************************/ + +/******************************************************************************************** + * Public Functions + ********************************************************************************************/ + +#endif /* KINETIS_K64 */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHP_KINETIS_K64PINMUX_H */ diff --git a/arch/arm/src/kinetis/kinetis_llwu.h b/arch/arm/src/kinetis/chip/kinetis_llwu.h similarity index 98% rename from arch/arm/src/kinetis/kinetis_llwu.h rename to arch/arm/src/kinetis/chip/kinetis_llwu.h index 4324a76251b412e0a542816025f408c85514f8a2..ae5c6c8b04c1edf2e7031037505af25869e55b51 100644 --- a/arch/arm/src/kinetis/kinetis_llwu.h +++ b/arch/arm/src/kinetis/chip/kinetis_llwu.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/kinetis/kinetis_llwu.h + * arch/arm/src/kinetis/chip/kinetis_llwu.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_LLWU_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_LLWU_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_LLWU_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_LLWU_H /************************************************************************************ * Included Files @@ -249,4 +249,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_LLWU_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_LLWU_H */ diff --git a/arch/arm/src/kinetis/kinetis_lptmr.h b/arch/arm/src/kinetis/chip/kinetis_lptmr.h similarity index 96% rename from arch/arm/src/kinetis/kinetis_lptmr.h rename to arch/arm/src/kinetis/chip/kinetis_lptmr.h index 863b24108eacec47e4808534cc2a7e93ff602132..15aeb4a5614c386f5a78b8a8c321ca6acf139fce 100644 --- a/arch/arm/src/kinetis/kinetis_lptmr.h +++ b/arch/arm/src/kinetis/chip/kinetis_lptmr.h @@ -1,7 +1,7 @@ /**************************************************************************************************** - * arch/arm/src/kinetis/kinetis_lptmr.h + * arch/arm/src/kinetis/chip/kinetis_lptmr.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ****************************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_LPTMR_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_LPTMR_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_LPTMR_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_LPTMR_H /**************************************************************************************************** * Included Files @@ -130,4 +130,4 @@ * Public Functions ****************************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_LPTMR_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_LPTMR_H */ diff --git a/arch/arm/src/kinetis/kinetis_mcg.h b/arch/arm/src/kinetis/chip/kinetis_mcg.h similarity index 92% rename from arch/arm/src/kinetis/kinetis_mcg.h rename to arch/arm/src/kinetis/chip/kinetis_mcg.h index 60f13cd2a0b788ef8e897b0c9adbeee28387aae0..fe8dccc60e1d8419634d008d9af9aa184c32bbe7 100644 --- a/arch/arm/src/kinetis/kinetis_mcg.h +++ b/arch/arm/src/kinetis/chip/kinetis_mcg.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/kinetis/kinetis_mcg.h + * arch/arm/src/kinetis/chip/kinetis_mcg.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_MCG_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_MCG_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MCG_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MCG_H /************************************************************************************ * Included Files @@ -60,6 +60,10 @@ #define KINETIS_MCG_ATC_OFFSET 0x0008 /* MCG Auto Trim Control Register */ #define KINETIS_MCG_ATCVH_OFFSET 0x000a /* MCG Auto Trim Compare Value High Register */ #define KINETIS_MCG_ATCVL_OFFSET 0x000b /* MCG Auto Trim Compare Value Low Register */ +#ifdef KINETIS_K64 +# define KINETIS_MCG_C7_OFFSET 0x000c /* MCG Control 7 Register */ +# define KINETIS_MCG_C8_OFFSET 0x000d /* MCG Control 8 Register */ +#endif /* Register Addresses ***************************************************************/ @@ -73,6 +77,10 @@ #define KINETIS_MCG_ATC (KINETIS_MCG_BASE+KINETIS_MCG_ATC_OFFSET) #define KINETIS_MCG_ATCVH (KINETIS_MCG_BASE+KINETIS_MCG_ATCVH_OFFSET) #define KINETIS_MCG_ATCVL (KINETIS_MCG_BASE+KINETIS_MCG_ATCVL_OFFSET) +#ifdef KINETIS_K64 +# define KINETIS_MCG_C7 (KINETIS_MCG_BASE+KINETIS_MCG_C7_OFFSET) +# define KINETIS_MCG_C8 (KINETIS_MCG_BASE+KINETIS_MCG_C8_OFFSET) +#endif /* Register Bit Definitions *********************************************************/ @@ -134,7 +142,7 @@ #define MCG_C5_PRDIV_SHIFT (0) /* Bits 0-4: PLL External Reference Divider */ #define MCG_C5_PRDIV_MASK (31 << MCG_C5_PRDIV_SHIFT) -# define MCG_C5_PRDIV(n) (((n)-1) << MCG_C5_PRDIV_SHIFT) /* Divide factor n=1..25 */ +# define MCG_C5_PRDIV(n) ((uint32_t)((n)-1) << MCG_C5_PRDIV_SHIFT) /* n=1..25 */ #define MCG_C5_PLLSTEN (1 << 5) /* Bit 5: PLL Stop Enable */ #define MCG_C5_PLLCLKEN (1 << 6) /* Bit 6: PLL Clock Enable */ /* Bit 7: Reserved */ @@ -143,7 +151,7 @@ #define MCG_C6_VDIV_SHIFT (0) /* Bits 0-4: VCO Divider */ #define MCG_C6_VDIV_MASK (31 << MCG_C6_VDIV_SHIFT) -# define MCG_C6_VDIV(n) (((n)-24) << MCG_C6_VDIV_SHIFT) /* Divide factor n=24..55 */ +# define MCG_C6_VDIV(n) ((uint32_t)((n)-24) << MCG_C6_VDIV_SHIFT) /* n=24..55 */ #define MCG_C6_CME (1 << 5) /* Bit 5: Clock Monitor Enable */ #define MCG_C6_PLLS (1 << 6) /* Bit 6: PLL Select */ #define MCG_C6_LOLIE (1 << 7) /* Bit 7: Loss of Lock Interrrupt Enable */ @@ -171,6 +179,10 @@ /* MCG Auto Trim Compare Value High/Low Registers (8-bit compare value) */ +/* MCG Control 7 Register */ + +/* MCG Control 8 Register */ + /************************************************************************************ * Public Types ************************************************************************************/ @@ -183,4 +195,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_MCG_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MCG_H */ diff --git a/arch/arm/src/kinetis/kinetis_mcm.h b/arch/arm/src/kinetis/chip/kinetis_mcm.h similarity index 94% rename from arch/arm/src/kinetis/kinetis_mcm.h rename to arch/arm/src/kinetis/chip/kinetis_mcm.h index d899b77027ac135150314bfaf214ef3cc7ba6c29..f46305056ef84f13d7cc8766a0ecfdaf26c45f9e 100644 --- a/arch/arm/src/kinetis/kinetis_mcm.h +++ b/arch/arm/src/kinetis/chip/kinetis_mcm.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/kinetis/kinetis_mcm.h + * arch/arm/src/kinetis/chip/kinetis_mcm.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_MCM_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_MCM_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MCM_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MCM_H /************************************************************************************ * Included Files @@ -57,6 +57,9 @@ #define KINETIS_MCM_ETBCC_OFFSET 0x0014 /* ETB counter control register */ #define KINETIS_MCM_ETBRL_OFFSET 0x0018 /* ETB reload register */ #define KINETIS_MCM_ETBCNT_OFFSET 0x001c /* ETB counter value register */ +#ifdef KINETIS_K64 +# define KINETIS_MCM_PID_OFFSET 0x0030 /* Process ID register */ +#endif /* Register Addresses ***************************************************************/ @@ -67,6 +70,9 @@ #define KINETIS_MCM_ETBCC (KINETIS_MCM_BASE+KINETIS_MCM_ETBCC_OFFSET) #define KINETIS_MCM_ETBRL (KINETIS_MCM_BASE+KINETIS_MCM_ETBRL_OFFSET) #define KINETIS_MCM_ETBCNT (KINETIS_MCM_BASE+KINETIS_MCM_ETBCNT_OFFSET) +#ifdef KINETIS_K64 +# define KINETIS_MCM_PID (KINETIS_MCM_BASE+KINETIS_MCM_PID_OFFSET) +#endif /* Register Bit Definitions *********************************************************/ @@ -148,4 +154,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_MCM_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MCM_H */ diff --git a/arch/arm/src/kinetis/chip/kinetis_memorymap.h b/arch/arm/src/kinetis/chip/kinetis_memorymap.h new file mode 100644 index 0000000000000000000000000000000000000000..ec67d42820dc8cbea8c1a60409314365a3a28c06 --- /dev/null +++ b/arch/arm/src/kinetis/chip/kinetis_memorymap.h @@ -0,0 +1,79 @@ +/******************************************************************************************** + * arch/arm/src/kinetis/chip/kinetis_memorymap.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MEMORYMAP_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MEMORYMAP_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include + +#include "chip.h" + +/* This file is just a wrapper around pin muxing header files for the Kinetis family selected + * by the logic in chip.h. + */ + +#if defined(KINETIS_K20) +# include "chip/kinetis_k20memorymap.h" +#elif defined(KINETIS_K40) +# include "chip/kinetis_k40memorymap.h" +#elif defined(KINETIS_K60) +# include "chip/kinetis_k60memorymap.h" +#elif defined(KINETIS_K64) +# include "chip/kinetis_k64memorymap.h" +#else +# error "No memory map for this Kinetis part" +#endif + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +/******************************************************************************************** + * Public Data + ********************************************************************************************/ + +/******************************************************************************************** + * Public Functions + ********************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MEMORYMAP_H */ diff --git a/arch/arm/src/kinetis/kinetis_mmcau.h b/arch/arm/src/kinetis/chip/kinetis_mmcau.h similarity index 89% rename from arch/arm/src/kinetis/kinetis_mmcau.h rename to arch/arm/src/kinetis/chip/kinetis_mmcau.h index 7468a1d0bfe3b3563918e57adf8a99bdfb0aed86..90c9cf6552cdf60eafd0b00f4d924d3aac2f2326 100644 --- a/arch/arm/src/kinetis/kinetis_mmcau.h +++ b/arch/arm/src/kinetis/chip/kinetis_mmcau.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/kinetis/kinetis_mmcau.h + * arch/arm/src/kinetis/chip/kinetis_mmcau.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_MMCAU_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_MMCAU_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MMCAU_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MMCAU_H /************************************************************************************ * Included Files @@ -61,9 +61,11 @@ #define KINETIS_CAU_CA3_OFFSET 0x0005 /* General Purpose Register 3 */ #define KINETIS_CAU_CA4_OFFSET 0x0006 /* General Purpose Register 4 */ #define KINETIS_CAU_CA5_OFFSET 0x0007 /* General Purpose Register 5 */ -#define KINETIS_CAU_CA6_OFFSET 0x0008 /* General Purpose Register 6 */ -#define KINETIS_CAU_CA7_OFFSET 0x0009 /* General Purpose Register 7 */ -#define KINETIS_CAU_CA8_OFFSET 0x000a /* General Purpose Register 8 */ +#ifndef KINETIS_K64 +# define KINETIS_CAU_CA6_OFFSET 0x0008 /* General Purpose Register 6 */ +# define KINETIS_CAU_CA7_OFFSET 0x0009 /* General Purpose Register 7 */ +# define KINETIS_CAU_CA8_OFFSET 0x000a /* General Purpose Register 8 */ +#endif /* Register Addresses ***************************************************************/ @@ -77,9 +79,11 @@ #define KINETIS_CAU_CA3 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA3_OFFSET) #define KINETIS_CAU_CA4 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA4_OFFSET) #define KINETIS_CAU_CA5 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA5_OFFSET) -#define KINETIS_CAU_CA6 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA6_OFFSET) -#define KINETIS_CAU_CA7 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA7_OFFSET) -#define KINETIS_CAU_CA8 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA8_OFFSET) +#ifndef KINETIS_K64 +# define KINETIS_CAU_CA6 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA6_OFFSET) +# define KINETIS_CAU_CA7 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA7_OFFSET) +# define KINETIS_CAU_CA8 (KINETIS_MMCAU_BASE+KINETIS_CAU_CA8_OFFSET) +#endif /* Register Bit Definitions *********************************************************/ @@ -135,4 +139,4 @@ ************************************************************************************/ #endif /* KINETIS_NMMCAU && KINETIS_NMMCAU > 0 */ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_MMCAU_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MMCAU_H */ diff --git a/arch/arm/src/kinetis/chip/kinetis_mpu.h b/arch/arm/src/kinetis/chip/kinetis_mpu.h new file mode 100644 index 0000000000000000000000000000000000000000..1faa605d75bc91be58b7425930549c7facd947d6 --- /dev/null +++ b/arch/arm/src/kinetis/chip/kinetis_mpu.h @@ -0,0 +1,75 @@ +/******************************************************************************************** + * arch/arm/src/kinetis/chip/kinetis_mpu.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MPU_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MPU_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include + +#include "chip.h" + +/* This file is just a wrapper around pin muxing header files for the Kinetis family selected + * by the logic in chip.h. + */ + +#if defined(KINETIS_K20) || defined(KINETIS_K40) || defined(KINETIS_K60) +# include "chip/kinetis_k20k40k60mpu.h" +#elif defined(KINETIS_K64) +# include "chip/kinetis_k64mpu.h" +#else +# error "No MPU definitions for this Kinetis part" +#endif + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ + +/******************************************************************************************** + * Public Types + ********************************************************************************************/ + +/******************************************************************************************** + * Public Data + ********************************************************************************************/ + +/******************************************************************************************** + * Public Functions + ********************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_MPU_H */ diff --git a/arch/arm/src/kinetis/kinetis_osc.h b/arch/arm/src/kinetis/chip/kinetis_osc.h similarity index 93% rename from arch/arm/src/kinetis/kinetis_osc.h rename to arch/arm/src/kinetis/chip/kinetis_osc.h index 16efcf328266055cf0ac411838a8b948dd520f93..69a7b8a30c8cabb5d7fd8ea17946893363f1437e 100644 --- a/arch/arm/src/kinetis/kinetis_osc.h +++ b/arch/arm/src/kinetis/chip/kinetis_osc.h @@ -1,7 +1,7 @@ /******************************************************************************************** - * arch/arm/src/kinetis/kinetis_osc.h + * arch/arm/src/kinetis/chip/kinetis_osc.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ********************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_OSC_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_OSC_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIHP_KINETIS_OSC_H +#define __ARCH_ARM_SRC_KINETIS_CHIHP_KINETIS_OSC_H /******************************************************************************************** * Included Files @@ -81,4 +81,4 @@ * Public Functions ********************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_OSC_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIHP_KINETIS_OSC_H */ diff --git a/arch/arm/src/kinetis/kinetis_pdb.h b/arch/arm/src/kinetis/chip/kinetis_pdb.h similarity index 95% rename from arch/arm/src/kinetis/kinetis_pdb.h rename to arch/arm/src/kinetis/chip/kinetis_pdb.h index 9cfab9b99f187b3dbe0440f2c486d32c84784ce5..d0238240dfabe07583762fbc2a77cc1d94fbb4bd 100644 --- a/arch/arm/src/kinetis/kinetis_pdb.h +++ b/arch/arm/src/kinetis/chip/kinetis_pdb.h @@ -1,7 +1,7 @@ /******************************************************************************************** - * arch/arm/src/kinetis/kinetis_pdb.h + * arch/arm/src/kinetis/chip/kinetis_pdb.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ********************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_PDB_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_PDB_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PDB_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PDB_H /******************************************************************************************** * Included Files @@ -83,6 +83,10 @@ #define KINETIS_PDB_PO0EN_OFFSET 0x0190 /* Pulse-Out 0 Enable Register */ #define KINETIS_PDB_PO0DLY_OFFSET 0x0194 /* Pulse-Out 0 Delay Register */ +#ifdef KINETIS_K64 +# define KINETIS_PDB_PO1DLY_OFFSET 0x0198 /* Pulse-Out 1 Delay Register */ +# define KINETIS_PDB_PO2DLY_OFFSET 0x019c /* Pulse-Out 2 Delay Register */ +#endif /* Register Addresses ***********************************************************************/ @@ -119,6 +123,10 @@ #define KINETIS_PDB0_PO0EN (KINETIS_PDB0_BASE+KINETIS_PDB_PO0EN_OFFSET) #define KINETIS_PDB0_PO0DLY (KINETIS_PDB0_BASE+KINETIS_PDB_PO0DLY_OFFSET) +#ifdef KINETIS_K64 +# define KINETIS_PDB0_PO1DLY (KINETIS_PDB0_BASE+KINETIS_PDB_PO1DLY_OFFSET) +# define KINETIS_PDB0_PO2DLY (KINETIS_PDB0_BASE+KINETIS_PDB_PO2DLY_OFFSET) +#endif /* Register Bit Definitions *****************************************************************/ @@ -252,4 +260,4 @@ * Public Functions ********************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_PDB_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PDB_H */ diff --git a/arch/arm/src/kinetis/kinetis_pinmux.h b/arch/arm/src/kinetis/chip/kinetis_pinmux.h similarity index 87% rename from arch/arm/src/kinetis/kinetis_pinmux.h rename to arch/arm/src/kinetis/chip/kinetis_pinmux.h index 589184ffdd2ceb507fa865da22fd9f0b37d54bb0..0a6aeb82532b8c506b5aa07c4434d36d2683748b 100644 --- a/arch/arm/src/kinetis/kinetis_pinmux.h +++ b/arch/arm/src/kinetis/chip/kinetis_pinmux.h @@ -1,7 +1,7 @@ /******************************************************************************************** - * arch/arm/src/kinetis/kinetis_pinmux.h + * arch/arm/src/kinetis/chip/kinetis_pinmux.h * - * Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ********************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_PINMUX_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_PINMUX_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PINMUX_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PINMUX_H /******************************************************************************************** * Included Files @@ -49,11 +49,13 @@ */ #if defined(KINETIS_K20) -# include "kinetis_k20pinmux.h" +# include "chip/kinetis_k20pinmux.h" #elif defined(KINETIS_K40) -# include "kinetis_k40pinmux.h" +# include "chip/kinetis_k40pinmux.h" #elif defined(KINETIS_K60) -# include "kinetis_k60pinmux.h" +# include "chip/kinetis_k60pinmux.h" +#elif defined(KINETIS_K64) +# include "chip/kinetis_k64pinmux.h" #else # error "No pin multiplexing for this Kinetis part" #endif @@ -74,4 +76,4 @@ * Public Functions ********************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_PINMUX_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PINMUX_H */ diff --git a/arch/arm/src/kinetis/kinetis_pit.h b/arch/arm/src/kinetis/chip/kinetis_pit.h similarity index 96% rename from arch/arm/src/kinetis/kinetis_pit.h rename to arch/arm/src/kinetis/chip/kinetis_pit.h index 808508f8fedd17be9e6af540338c248095be02fc..26cd6caea6dd16ed146060852473da3708811cb9 100644 --- a/arch/arm/src/kinetis/kinetis_pit.h +++ b/arch/arm/src/kinetis/chip/kinetis_pit.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/kinetis/kinetis_pit.h + * arch/arm/src/kinetis/chip/kinetis_pit.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_PIT_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_PIT_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PIT_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PIT_H /************************************************************************************ * Included Files @@ -121,4 +121,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_PIT_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PIT_H */ diff --git a/arch/arm/src/kinetis/kinetis_pmc.h b/arch/arm/src/kinetis/chip/kinetis_pmc.h similarity index 95% rename from arch/arm/src/kinetis/kinetis_pmc.h rename to arch/arm/src/kinetis/chip/kinetis_pmc.h index 065847da3d5a6f5bc702e8f7f44b8b1d7273ccad..c0ffe575b3615a691239db95ba764631c63dd686 100644 --- a/arch/arm/src/kinetis/kinetis_pmc.h +++ b/arch/arm/src/kinetis/chip/kinetis_pmc.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/kinetis/kinetis_pmc.h + * arch/arm/src/kinetis/chip/kinetis_pmc.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_PMC_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_PMC_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PMC_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PMC_H /************************************************************************************ * Included Files @@ -108,4 +108,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_PMC_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PMC_H */ diff --git a/arch/arm/src/kinetis/kinetis_port.h b/arch/arm/src/kinetis/chip/kinetis_port.h similarity index 99% rename from arch/arm/src/kinetis/kinetis_port.h rename to arch/arm/src/kinetis/chip/kinetis_port.h index 5a568537b01ed8845c61eaa891734226a191ca2d..36dfa4e0983aed0df88034a7acebace36d123ad2 100644 --- a/arch/arm/src/kinetis/kinetis_port.h +++ b/arch/arm/src/kinetis/chip/kinetis_port.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/kinetis/kinetis_port.h + * arch/arm/src/kinetis/chip/kinetis_port.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_PORT_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_PORT_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PORT_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PORT_H /************************************************************************************ * Included Files @@ -426,4 +426,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_PORT_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_PORT_H */ diff --git a/arch/arm/src/kinetis/kinetis_rngb.h b/arch/arm/src/kinetis/chip/kinetis_rngb.h similarity index 97% rename from arch/arm/src/kinetis/kinetis_rngb.h rename to arch/arm/src/kinetis/chip/kinetis_rngb.h index a4f677555030cd5be5f25fd5898407986aeeb40e..1e005c08ae30a1b2a95b7991a7b42bf38ff1da8a 100644 --- a/arch/arm/src/kinetis/kinetis_rngb.h +++ b/arch/arm/src/kinetis/chip/kinetis_rngb.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/kinetis/kinetis_rngb.h + * arch/arm/src/kinetis/chip/kinetis_rngb.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_RNGB_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_RNGB_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_RNGB_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_RNGB_H /************************************************************************************ * Included Files @@ -158,4 +158,4 @@ ************************************************************************************/ #endif /* KINETIS_NRNG && KINETIS_NRNG > 0 */ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_RNGB_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_RNGB_H */ diff --git a/arch/arm/src/kinetis/kinetis_rtc.h b/arch/arm/src/kinetis/chip/kinetis_rtc.h similarity index 95% rename from arch/arm/src/kinetis/kinetis_rtc.h rename to arch/arm/src/kinetis/chip/kinetis_rtc.h index 69c097a7c950627992f577b40e61cede1480ccf4..d00c02a6974d9ecd76e138a23677aaad98fd3f0c 100644 --- a/arch/arm/src/kinetis/kinetis_rtc.h +++ b/arch/arm/src/kinetis/chip/kinetis_rtc.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/kinetis/kinetis_rtc.h + * arch/arm/src/kinetis/chip/kinetis_rtc.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_RTC_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_RTC_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_RTC_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_RTC_H /************************************************************************************ * Included Files @@ -59,7 +59,7 @@ #define KINETIS_RTC_CR_OFFSET 0x0010 /* RTC Control Register */ #define KINETIS_RTC_SR_OFFSET 0x0014 /* RTC Status Register */ #define KINETIS_RTC_LR_OFFSET 0x0018 /* RTC Lock Register */ -#ifdef KINETIS_K40 +#if defined(KINETIS_K40) || defined(KINETIS_K64) # define KINETIS_RTC_IER_OFFSET 0x001c /* RTC Interrupt Enable Register (K40) */ #endif #ifdef KINETIS_K60 @@ -77,7 +77,7 @@ #define KINETIS_RTC_CR (KINETIS_RTC_BASE+KINETIS_RTC_CR_OFFSET) #define KINETIS_RTC_SR (KINETIS_RTC_BASE+KINETIS_RTC_SR_OFFSET) #define KINETIS_RTC_LR (KINETIS_RTC_BASE+KINETIS_RTC_LR_OFFSET) -#ifdef KINETIS_K40 +#if defined(KINETIS_K40) || defined(KINETIS_K64) # define KINETIS_RTC_IER (KINETIS_RTC_BASE+KINETIS_RTC_IER_OFFSET) #endif #ifdef KINETIS_K60 @@ -141,7 +141,7 @@ /* Bits 7-31: Reserved */ /* RTC Interrupt Enable Register (32-bits, K40) */ -#ifdef KINETIS_K40 +#if defined(KINETIS_K40) || defined(KINETIS_K64) # define RTC_IER_TIIE (1 << 0) /* Bit 0: Time Invalid Interrupt Enable */ # define RTC_IER_TOIE (1 << 1) /* Bit 1: Time Overflow Interrupt Enable */ # define RTC_IER_TAIE (1 << 2) /* Bit 2: Time Alarm Interrupt Enable */ @@ -167,7 +167,7 @@ #define RTC_WAR_CRW (1 << 4) /* Bit 4: Control Register Write */ #define RTC_WAR_SRW (1 << 5) /* Bit 5: Status Register Write */ #define RTC_WAR_LRW (1 << 6) /* Bit 6: Lock Register Write */ -#ifdef KINETIS_K40 +#if defined(KINETIS_K40) || defined(KINETIS_K64) # define RTC_WAR_IERW (1 << 7) /* Bit 7: Interrupt Enable Register Write */ #endif #ifdef KINETIS_K60 @@ -183,7 +183,7 @@ #define RTC_RAR_CRR (1 << 4) /* Bit 4: Control Register Read */ #define RTC_RAR_SRR (1 << 5) /* Bit 5: Status Register Read */ #define RTC_RAR_LRR (1 << 6) /* Bit 6: Lock Register Read */ -#ifdef KINETIS_K40 +#if defined(KINETIS_K40) || defined(KINETIS_K64) # define RTC_RAR_IERR (1 << 7) /* Bit 7: Interrupt Enable Register Read */ #endif #ifdef KINETIS_K60 @@ -204,4 +204,4 @@ ************************************************************************************/ #endif /* KINETIS_NRTC && KINETIS_NRTC > 0 */ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_RTC_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_RTC_H */ diff --git a/arch/arm/src/kinetis/kinetis_sdhc.h b/arch/arm/src/kinetis/chip/kinetis_sdhc.h similarity index 99% rename from arch/arm/src/kinetis/kinetis_sdhc.h rename to arch/arm/src/kinetis/chip/kinetis_sdhc.h index 5d122315a9d2efa426865fd396748ac3e0372434..b57b85c94e70e83d72f12e2e6101ca42c3c83c35 100644 --- a/arch/arm/src/kinetis/kinetis_sdhc.h +++ b/arch/arm/src/kinetis/chip/kinetis_sdhc.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/kinetis/kinetis_sdhc.h + * arch/arm/src/kinetis/chip/kinetis_sdhc.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_SDHC_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_SDHC_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SDHC_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SDHC_H /************************************************************************************ * Included Files @@ -385,4 +385,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_SDHC_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SDHC_H */ diff --git a/arch/arm/src/kinetis/kinetis_sim.h b/arch/arm/src/kinetis/chip/kinetis_sim.h similarity index 95% rename from arch/arm/src/kinetis/kinetis_sim.h rename to arch/arm/src/kinetis/chip/kinetis_sim.h index aad17e923e80c2bc7513fba4ff707c3825e2d5a3..ae56504ff085ac1be8929e0275125f04b19a29c4 100644 --- a/arch/arm/src/kinetis/kinetis_sim.h +++ b/arch/arm/src/kinetis/chip/kinetis_sim.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/kinetis/kinetis_sim.h + * arch/arm/src/kinetis/chip/kinetis_sim.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_SIM_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_SIM_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SIM_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SIM_H /************************************************************************************ * Included Files @@ -207,7 +207,7 @@ /* Bits 0-23: Reserved */ #define SIM_SOPT6_RSTFLTSEL_SHIFT (24) /* Bits 24-28: Reset pin filter select */ #define SIM_SOPT6_RSTFLTSEL_MASK (31 << SIM_SOPT6_RSTFLTSEL_SHIFT) -# define SIM_SOPT6_RSTFLTSEL(n) (((n)-1) << SIM_SOPT6_RSTFLTSEL_SHIFT) /* Bux clock filter count n, n=1..32 */ +# define SIM_SOPT6_RSTFLTSEL(n) ((uint32_t)((n)-1) << SIM_SOPT6_RSTFLTSEL_SHIFT) /* n=1..32 */ #define SIM_SOPT6_RSTFLTEN_SHIFT (29) /* Bits 29-31: Reset pin filter enable */ #define SIM_SOPT6_RSTFLTEN_MASK (7 << SIM_SOPT6_RSTFLTEN_SHIFT) #define SIM_SOPT6_RSTFLTEN_DISABLED (0 << SIM_SOPT6_RSTFLTEN_SHIFT) /* All filtering disabled */ @@ -385,7 +385,7 @@ /* Bits 0-15: Reserved */ #define SIM_CLKDIV1_OUTDIV4_SHIFT (16) /* Bits 16-19: Clock 4 output divider value */ #define SIM_CLKDIV1_OUTDIV4_MASK (15 << SIM_CLKDIV1_OUTDIV4_SHIFT) -# define SIM_CLKDIV1_OUTDIV4(n) (((n)-1) << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by n, n=1..16 */ +# define SIM_CLKDIV1_OUTDIV4(n) ((uint32_t)((n)-1) << SIM_CLKDIV1_OUTDIV4_SHIFT) /* n=1..16 */ # define SIM_CLKDIV1_OUTDIV4_1 (0 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 1 */ # define SIM_CLKDIV1_OUTDIV4_2 (1 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 2 */ # define SIM_CLKDIV1_OUTDIV4_3 (2 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 3 */ @@ -404,7 +404,7 @@ # define SIM_CLKDIV1_OUTDIV4_16 (15 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 16 */ #define SIM_CLKDIV1_OUTDIV3_SHIFT (20) /* Bits 20-23: Clock 3 output divider value */ #define SIM_CLKDIV1_OUTDIV3_MASK (15 << SIM_CLKDIV1_OUTDIV3_SHIFT) -# define SIM_CLKDIV1_OUTDIV3(n) (((n)-1) << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by n, n=1..16 */ +# define SIM_CLKDIV1_OUTDIV3(n) ((uint32_t)((n)-1) << SIM_CLKDIV1_OUTDIV3_SHIFT) /* n=1..16 */ # define SIM_CLKDIV1_OUTDIV3_1 (0 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 1 */ # define SIM_CLKDIV1_OUTDIV3_2 (1 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 2 */ # define SIM_CLKDIV1_OUTDIV3_3 (2 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 3 */ @@ -423,7 +423,7 @@ # define SIM_CLKDIV1_OUTDIV3_16 (15 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 16 */ #define SIM_CLKDIV1_OUTDIV2_SHIFT (24) /* Bits 24-27: Clock 2 output divider value */ #define SIM_CLKDIV1_OUTDIV2_MASK (15 << SIM_CLKDIV1_OUTDIV2_SHIFT) -# define SIM_CLKDIV1_OUTDIV2(n) (((n)-1) << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by n, n=1..16 */ +# define SIM_CLKDIV1_OUTDIV2(n) ((uint32_t)((n)-1) << SIM_CLKDIV1_OUTDIV2_SHIFT) /* n=1..16 */ # define SIM_CLKDIV1_OUTDIV2_1 (0 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 1 */ # define SIM_CLKDIV1_OUTDIV2_2 (1 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 2 */ # define SIM_CLKDIV1_OUTDIV2_3 (2 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 3 */ @@ -442,7 +442,7 @@ # define SIM_CLKDIV1_OUTDIV2_16 (15 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 16 */ #define SIM_CLKDIV1_OUTDIV1_SHIFT (28) /* Bits 28-31: Clock 1 output divider value */ #define SIM_CLKDIV1_OUTDIV1_MASK (15 << SIM_CLKDIV1_OUTDIV1_SHIFT) -# define SIM_CLKDIV1_OUTDIV1(n) (((n)-1) << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by n, n=1..16 */ +# define SIM_CLKDIV1_OUTDIV1(n) ((uint32_t)((n)-1) << SIM_CLKDIV1_OUTDIV1_SHIFT) /* n=1..16 */ # define SIM_CLKDIV1_OUTDIV1_1 (0 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 1 */ # define SIM_CLKDIV1_OUTDIV1_2 (1 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 2 */ # define SIM_CLKDIV1_OUTDIV1_3 (2 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 3 */ @@ -489,29 +489,29 @@ # define SIM_FCFG1_EESIZE_32B (9 << SIM_FCFG1_EESIZE_SHIFT) /* 32 Bytes */ # define SIM_FCFG1_EESIZE_NONE (15 << SIM_FCFG1_EESIZE_SHIFT) /* 0 Bytes */ /* Bits 20-23: Reserved */ -#ifdef KINETIS_K40 -#define SIM_FCFG1_PFSIZE_SHIFT (24) /* Bits 24-27: Program flash size (K40) */ -#define SIM_FCFG1_PFSIZE_MASK (15 << SIM_FCFG1_PFSIZE_SHIFT) -# define SIM_FCFG1_PFSIZE_128KB (7 << SIM_FCFG1_PFSIZE_SHIFT) /* 128KB program flash, 4KB protection region */ -# define SIM_FCFG1_PFSIZE_256KB (9 << SIM_FCFG1_PFSIZE_SHIFT) /* 256KB program flash, 8KB protection region */ -# define SIM_FCFG1_PFSIZE_512KB (11 << SIM_FCFG1_PFSIZE_SHIFT) /* 512KB program flash, 16KB protection region */ -# define SIM_FCFG1_PFSIZE_512KB2 (15 << SIM_FCFG1_PFSIZE_SHIFT) /* 512KB program flash, 16KB protection region */ -#define SIM_FCFG1_NVMSIZE_SHIFT (28) /* Bits 28-31: FlexNVM size (K40)*/ -#define SIM_FCFG1_NVMSIZE_MASK (15 << SIM_FCFG1_NVMSIZE_SHIFT) -# define SIM_FCFG1_NVMSIZE_NONE (0 << SIM_FCFG1_NVMSIZE_SHIFT) /* 0KB FlexNVM */ -# define SIM_FCFG1_NVMSIZE_128KB (7 << SIM_FCFG1_NVMSIZE_SHIFT) /* 128KB FlexNVM, 16KB protection region */ -# define SIM_FCFG1_NVMSIZE_256KB (9 << SIM_FCFG1_NVMSIZE_SHIFT) /* 256KB FlexNVM, 32KB protection region */ -# define SIM_FCFG1_NVMSIZE_256KB2 (15 << SIM_FCFG1_NVMSIZE_SHIFT) /* 256KB FlexNVM, 32KB protection region */ +#if defined(KINETIS_K40) || defined(KINETIS_K64) +# define SIM_FCFG1_PFSIZE_SHIFT (24) /* Bits 24-27: Program flash size (K40) */ +# define SIM_FCFG1_PFSIZE_MASK (15 << SIM_FCFG1_PFSIZE_SHIFT) +# define SIM_FCFG1_PFSIZE_128KB (7 << SIM_FCFG1_PFSIZE_SHIFT) /* 128KB program flash, 4KB protection region */ +# define SIM_FCFG1_PFSIZE_256KB (9 << SIM_FCFG1_PFSIZE_SHIFT) /* 256KB program flash, 8KB protection region */ +# define SIM_FCFG1_PFSIZE_512KB (11 << SIM_FCFG1_PFSIZE_SHIFT) /* 512KB program flash, 16KB protection region */ +# define SIM_FCFG1_PFSIZE_512KB2 (15 << SIM_FCFG1_PFSIZE_SHIFT) /* 512KB program flash, 16KB protection region */ +# define SIM_FCFG1_NVMSIZE_SHIFT (28) /* Bits 28-31: FlexNVM size (K40)*/ +# define SIM_FCFG1_NVMSIZE_MASK (15 << SIM_FCFG1_NVMSIZE_SHIFT) +# define SIM_FCFG1_NVMSIZE_NONE (0 << SIM_FCFG1_NVMSIZE_SHIFT) /* 0KB FlexNVM */ +# define SIM_FCFG1_NVMSIZE_128KB (7 << SIM_FCFG1_NVMSIZE_SHIFT) /* 128KB FlexNVM, 16KB protection region */ +# define SIM_FCFG1_NVMSIZE_256KB (9 << SIM_FCFG1_NVMSIZE_SHIFT) /* 256KB FlexNVM, 32KB protection region */ +# define SIM_FCFG1_NVMSIZE_256KB2 (15 << SIM_FCFG1_NVMSIZE_SHIFT) /* 256KB FlexNVM, 32KB protection region */ #endif #ifdef KINETIS_K60 -#define SIM_FCFG1_FSIZE_SHIFT (24) /* Bits 24-31: Flash size (K60)*/ -#define SIM_FCFG1_FSIZE_MASK (0xff << SIM_FCFG1_FSIZE_SHIFT) -# define SIM_FCFG1_FSIZE_32KB (2 << SIM_FCFG1_FSIZE_SHIFT) /* 32KB program flash, 1KB protection region */ -# define SIM_FCFG1_FSIZE_64KB (4 << SIM_FCFG1_FSIZE_SHIFT) /* 64KB program flash, 2KB protection region */ -# define SIM_FCFG1_FSIZE_128KB (6 << SIM_FCFG1_FSIZE_SHIFT) /* 128KB program flash, 4KB protection region */ -# define SIM_FCFG1_FSIZE_256KB (8 << SIM_FCFG1_FSIZE_SHIFT) /* 256KB program flash, 8KB protection region */ -# define SIM_FCFG1_FSIZE_512KB (12 << SIM_FCFG1_FSIZE_SHIFT) /* 512KB program flash, 16KB protection region */ +# define SIM_FCFG1_FSIZE_SHIFT (24) /* Bits 24-31: Flash size (K60)*/ +# define SIM_FCFG1_FSIZE_MASK (0xff << SIM_FCFG1_FSIZE_SHIFT) +# define SIM_FCFG1_FSIZE_32KB (2 << SIM_FCFG1_FSIZE_SHIFT) /* 32KB program flash, 1KB protection region */ +# define SIM_FCFG1_FSIZE_64KB (4 << SIM_FCFG1_FSIZE_SHIFT) /* 64KB program flash, 2KB protection region */ +# define SIM_FCFG1_FSIZE_128KB (6 << SIM_FCFG1_FSIZE_SHIFT) /* 128KB program flash, 4KB protection region */ +# define SIM_FCFG1_FSIZE_256KB (8 << SIM_FCFG1_FSIZE_SHIFT) /* 256KB program flash, 8KB protection region */ +# define SIM_FCFG1_FSIZE_512KB (12 << SIM_FCFG1_FSIZE_SHIFT) /* 512KB program flash, 16KB protection region */ #endif /* Flash Configuration Register 2 */ @@ -542,4 +542,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_SIM_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SIM_H */ diff --git a/arch/arm/src/kinetis/kinetis_slcd.h b/arch/arm/src/kinetis/chip/kinetis_slcd.h similarity index 99% rename from arch/arm/src/kinetis/kinetis_slcd.h rename to arch/arm/src/kinetis/chip/kinetis_slcd.h index d56ee5c41eac0e547aeb67874a94d8b76bf95d34..d4a68f07f5a977efaa980bde2dfd00e3edd72b7c 100644 --- a/arch/arm/src/kinetis/kinetis_slcd.h +++ b/arch/arm/src/kinetis/chip/kinetis_slcd.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/kinetis/kinetis_slcd.h + * arch/arm/src/kinetis/chip/kinetis_slcd.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_SLCD_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_SLCD_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SLCD_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SLCD_H /************************************************************************************ * Included Files @@ -417,4 +417,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_SLCD_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SLCD_H */ diff --git a/arch/arm/src/kinetis/kinetis_smc.h b/arch/arm/src/kinetis/chip/kinetis_smc.h similarity index 96% rename from arch/arm/src/kinetis/kinetis_smc.h rename to arch/arm/src/kinetis/chip/kinetis_smc.h index 213ea80775972d3f6537b77ec3b36e492b1a0e2d..19a9d9d14b81dbe4c45ce8188adf3bc19c3d4ea1 100644 --- a/arch/arm/src/kinetis/kinetis_smc.h +++ b/arch/arm/src/kinetis/chip/kinetis_smc.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/kinetis/kinetis_smc.h + * arch/arm/src/kinetis/chip/kinetis_smc.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_SMC_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_SMC_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SMC_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SMC_H /************************************************************************************ * Included Files @@ -119,4 +119,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_SMC_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SMC_H */ diff --git a/arch/arm/src/kinetis/kinetis_tsi.h b/arch/arm/src/kinetis/chip/kinetis_tsi.h similarity index 98% rename from arch/arm/src/kinetis/kinetis_tsi.h rename to arch/arm/src/kinetis/chip/kinetis_tsi.h index ea52c0fd1db765848316645b2d9a5b9be5c1e56d..6881150160fe0ef2e41ae4b47b7942dfa3f5937b 100644 --- a/arch/arm/src/kinetis/kinetis_tsi.h +++ b/arch/arm/src/kinetis/chip/kinetis_tsi.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/kinetis/kinetis_tsi.h + * arch/arm/src/kinetis/chip/kinetis_tsi.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_TSI_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_TSI_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_TSI_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_TSI_H /************************************************************************************ * Included Files @@ -308,4 +308,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_TSI_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_TSI_H */ diff --git a/arch/arm/src/kinetis/kinetis_uart.h b/arch/arm/src/kinetis/chip/kinetis_uart.h similarity index 99% rename from arch/arm/src/kinetis/kinetis_uart.h rename to arch/arm/src/kinetis/chip/kinetis_uart.h index fbdf7a3192a86cb4536100ef092b38beed3256a8..537332ee78644febc3f678add0b43675fffa0b85 100644 --- a/arch/arm/src/kinetis/kinetis_uart.h +++ b/arch/arm/src/kinetis/chip/kinetis_uart.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/kinetis/kinetis_uart.h + * arch/arm/src/kinetis/chip/kinetis_uart.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_UART_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_UART_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_UART_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_UART_H /************************************************************************************ * Included Files @@ -42,7 +42,7 @@ #include -#include "kinetis_memorymap.h" +#include "chip/kinetis_memorymap.h" /************************************************************************************ * Pre-processor Definitions @@ -508,4 +508,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_UART_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_UART_H */ diff --git a/arch/arm/src/kinetis/kinetis_usbdcd.h b/arch/arm/src/kinetis/chip/kinetis_usbdcd.h similarity index 87% rename from arch/arm/src/kinetis/kinetis_usbdcd.h rename to arch/arm/src/kinetis/chip/kinetis_usbdcd.h index fad76d1500e8771666c3dc123a676dd905d72712..6c4297ff7afec566aa555d6dcc8c875db18bedbe 100644 --- a/arch/arm/src/kinetis/kinetis_usbdcd.h +++ b/arch/arm/src/kinetis/chip/kinetis_usbdcd.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/kinetis/kinetis_usbdcd.h + * arch/arm/src/kinetis/chip/kinetis_usbdcd.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_USBDCD_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_USBDCD_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_USBDCD_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_USBDCD_H /************************************************************************************ * Included Files @@ -50,12 +50,17 @@ /* Register Offsets *****************************************************************/ -#define KINETIS_USBDCD_CONTROL_OFFSET 0x0000 /* Control Register */ -#define KINETIS_USBDCD_CLOCK_OFFSET 0x0004 /* Clock Register */ -#define KINETIS_USBDCD_STATUS_OFFSET 0x0008 /* Status Register */ -#define KINETIS_USBDCD_TIMER0_OFFSET 0x0010 /* TIMER0 Register */ -#define KINETIS_USBDCD_TIMER1_OFFSET 0x0014 /* TIMER1 Register */ -#define KINETIS_USBDCD_TIMER2_OFFSET 0x0018 /* TIMER2 Register */ +#define KINETIS_USBDCD_CONTROL_OFFSET 0x0000 /* Control Register */ +#define KINETIS_USBDCD_CLOCK_OFFSET 0x0004 /* Clock Register */ +#define KINETIS_USBDCD_STATUS_OFFSET 0x0008 /* Status Register */ +#define KINETIS_USBDCD_TIMER0_OFFSET 0x0010 /* TIMER0 Register */ +#define KINETIS_USBDCD_TIMER1_OFFSET 0x0014 /* TIMER1 Register */ +#ifdef KINETIS_K64 +# define KINETIS_USBDCD_TIMER2_BC11_OFFSET 0x0018 /* TIMER2_BC11 Register */ +# define KINETIS_USBDCD_TIMER2_BC12_OFFSET 0x001c /* TIMER2_BC12 Register */ +#else +# define KINETIS_USBDCD_TIMER2_OFFSET 0x0018 /* TIMER2 Register */ +#endif /* Register Addresses ***************************************************************/ @@ -64,7 +69,12 @@ #define KINETIS_USBDCD_STATUS (KINETIS_USBDCD_BASE+KINETIS_USBDCD_STATUS_OFFSET) #define KINETIS_USBDCD_TIMER0 (KINETIS_USBDCD_BASE+KINETIS_USBDCD_TIMER0_OFFSET) #define KINETIS_USBDCD_TIMER1 (KINETIS_USBDCD_BASE+KINETIS_USBDCD_TIMER1_OFFSET) -#define KINETIS_USBDCD_TIMER2 (KINETIS_USBDCD_BASE+KINETIS_USBDCD_TIMER2_OFFSET) +#ifdef KINETIS_K64 +# define KINETIS_USBDCD_TIMER2_BC11 (KINETIS_USBDCD_BASE+KINETIS_USBDCD_TIMER2_BC11_OFFSET) +# define KINETIS_USBDCD_TIMER2_BC12 (KINETIS_USBDCD_BASE+KINETIS_USBDCD_TIMER2_BC12_OFFSET) +#else +# define KINETIS_USBDCD_TIMER2 (KINETIS_USBDCD_BASE+KINETIS_USBDCD_TIMER2_OFFSET) +#endif /* Register Bit Definitions *********************************************************/ @@ -138,4 +148,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_USBDCD_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_USBDCD_H */ diff --git a/arch/arm/src/kinetis/chip/kinetis_usbotg.h b/arch/arm/src/kinetis/chip/kinetis_usbotg.h new file mode 100644 index 0000000000000000000000000000000000000000..16cecc22610fb3c0a9a75adbf2c89d7bbe6f25f6 --- /dev/null +++ b/arch/arm/src/kinetis/chip/kinetis_usbotg.h @@ -0,0 +1,377 @@ +/******************************************************************************************** + * arch/arm/src/kinetis/chip/kinetis_usbotg.h + * + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_USBOTG_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_USBOTG_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include + +#include "chip.h" + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ + +/* Register Offsets *************************************************************************/ + +#define KINETIS_USB_PERID_OFFSET 0x0000 /* Peripheral ID Register */ +#define KINETIS_USB_IDCOMP_OFFSET 0x0004 /* Peripheral ID Complement Register */ +#define KINETIS_USB_REV_OFFSET 0x0008 /* Peripheral Revision Register */ +#define KINETIS_USB_ADDINFO_OFFSET 0x000c /* Peripheral Additional Info Register */ +#define KINETIS_USB_OTGISTAT_OFFSET 0x0010 /* OTG Interrupt Status Register */ +#define KINETIS_USB_OTGICR_OFFSET 0x0014 /* OTG Interrupt Control Register */ +#define KINETIS_USB_OTGSTAT_OFFSET 0x0018 /* OTG Status Register */ +#define KINETIS_USB_OTGCTL_OFFSET 0x001c /* OTG Control Register */ +#define KINETIS_USB_ISTAT_OFFSET 0x0080 /* Interrupt Status Register */ +#define KINETIS_USB_INTEN_OFFSET 0x0084 /* Interrupt Enable Register */ +#define KINETIS_USB_ERRSTAT_OFFSET 0x0088 /* Error Interrupt Status Register */ +#define KINETIS_USB_ERREN_OFFSET 0x008c /* Error Interrupt Enable Register */ +#define KINETIS_USB_STAT_OFFSET 0x0090 /* Status Register */ +#define KINETIS_USB_CTL_OFFSET 0x0094 /* Control Register */ +#define KINETIS_USB_ADDR_OFFSET 0x0098 /* Address Register */ +#define KINETIS_USB_BDTPAGE1_OFFSET 0x009c /* BDT Page Register 1 */ +#define KINETIS_USB_FRMNUML_OFFSET 0x00a0 /* Frame Number Register Low */ +#define KINETIS_USB_FRMNUMH_OFFSET 0x00a4 /* Frame Number Register High */ +#define KINETIS_USB_TOKEN_OFFSET 0x00a8 /* Token Register */ +#define KINETIS_USB_SOFTHLD_OFFSET 0x00ac /* SOF Threshold Register */ +#define KINETIS_USB_BDTPAGE2_OFFSET 0x00b0 /* BDT Page Register 2 */ +#define KINETIS_USB_BDTPAGE3_OFFSET 0x00b4 /* BDT Page Register 3 */ + +#define KINETIS_USB_ENDPT_OFFSET(n) (0x00c0+((n)<<2)) /* Endpoint n Control Register */ +#define KINETIS_USB_ENDPT0_OFFSET 0x00c0 /* Endpoint 0 Control Register */ +#define KINETIS_USB_ENDPT1_OFFSET 0x00c4 /* Endpoint 1 Control Register */ +#define KINETIS_USB_ENDPT2_OFFSET 0x00c8 /* Endpoint 2 Control Register */ +#define KINETIS_USB_ENDPT3_OFFSET 0x00cc /* Endpoint 3 Control Register */ +#define KINETIS_USB_ENDPT4_OFFSET 0x00d0 /* Endpoint 4 Control Register */ +#define KINETIS_USB_ENDPT5_OFFSET 0x00d4 /* Endpoint 5 Control Register */ +#define KINETIS_USB_ENDPT6_OFFSET 0x00d8 /* Endpoint 6 Control Register */ +#define KINETIS_USB_ENDPT7_OFFSET 0x00dc /* Endpoint 7 Control Register */ +#define KINETIS_USB_ENDPT8_OFFSET 0x00e0 /* Endpoint 8 Control Register */ +#define KINETIS_USB_ENDPT9_OFFSET 0x00e4 /* Endpoint 9 Control Register */ +#define KINETIS_USB_ENDPT10_OFFSET 0x00e8 /* Endpoint 10 Control Register */ +#define KINETIS_USB_ENDPT11_OFFSET 0x00ec /* Endpoint 11 Control Register */ +#define KINETIS_USB_ENDPT12_OFFSET 0x00f0 /* Endpoint 12 Control Register */ +#define KINETIS_USB_ENDPT13_OFFSET 0x00f4 /* Endpoint 13 Control Register */ +#define KINETIS_USB_ENDPT14_OFFSET 0x00f8 /* Endpoint 14 Control Register */ +#define KINETIS_USB_ENDPT15_OFFSET 0x00fc /* Endpoint 15 Control Register */ + +#define KINETIS_USB_USBCTRL_OFFSET 0x0100 /* USB Control Register */ +#define KINETIS_USB_OBSERVE_OFFSET 0x0104 /* USB OTG Observe Register */ +#define KINETIS_USB_CONTROL_OFFSET 0x0108 /* USB OTG Control Register */ +#define KINETIS_USB_USBTRC0_OFFSET 0x010c /* USB Transceiver Control Register 0 */ + +#ifdef KINETIS_K64 +# define KINETIS_USB_USBFRMADJUST_OFFSET 0x114 /* Frame Adjust Register */ +# define KINETIS_USB_USB0_CLK_RECOVER_CTRL_OFFSET 0x140 /* USB Clock recovery control */ +# define KINETIS_USB_USB0_CLK_RECOVER_IRC_EN_OFFSET 0x144 /* IRC48M oscillator enable register */ +# define KINETIS_USB_USB0_CLK_RECOVER_INT_STATUS_OFFSET 0x15c /* Clock recovery sperated interrupt status */ +#endif + +/* Register Addresses ***********************************************************************/ + +#define KINETIS_USB0_PERID (KINETIS_USB0_BASE+KINETIS_USB_PERID_OFFSET) +#define KINETIS_USB0_IDCOMP (KINETIS_USB0_BASE+KINETIS_USB_IDCOMP_OFFSET) +#define KINETIS_USB0_REV (KINETIS_USB0_BASE+KINETIS_USB_REV_OFFSET) +#define KINETIS_USB0_ADDINFO (KINETIS_USB0_BASE+KINETIS_USB_ADDINFO_OFFSET) +#define KINETIS_USB0_OTGISTAT (KINETIS_USB0_BASE+KINETIS_USB_OTGISTAT_OFFSET) +#define KINETIS_USB0_OTGICR (KINETIS_USB0_BASE+KINETIS_USB_OTGICR_OFFSET) +#define KINETIS_USB0_OTGSTAT (KINETIS_USB0_BASE+KINETIS_USB_OTGSTAT_OFFSET) +#define KINETIS_USB0_OTGCTL (KINETIS_USB0_BASE+KINETIS_USB_OTGCTL_OFFSET) +#define KINETIS_USB0_ISTAT (KINETIS_USB0_BASE+KINETIS_USB_ISTAT_OFFSET) +#define KINETIS_USB0_INTEN (KINETIS_USB0_BASE+KINETIS_USB_INTEN_OFFSET) +#define KINETIS_USB0_ERRSTAT (KINETIS_USB0_BASE+KINETIS_USB_ERRSTAT_OFFSET) +#define KINETIS_USB0_ERREN (KINETIS_USB0_BASE+KINETIS_USB_ERREN_OFFSET) +#define KINETIS_USB0_STAT (KINETIS_USB0_BASE+KINETIS_USB_STAT_OFFSET) +#define KINETIS_USB0_CTL (KINETIS_USB0_BASE+KINETIS_USB_CTL_OFFSET) +#define KINETIS_USB0_ADDR (KINETIS_USB0_BASE+KINETIS_USB_ADDR_OFFSET) +#define KINETIS_USB0_BDTPAGE1 (KINETIS_USB0_BASE+KINETIS_USB_BDTPAGE1_OFFSET) +#define KINETIS_USB0_FRMNUML (KINETIS_USB0_BASE+KINETIS_USB_FRMNUML_OFFSET) +#define KINETIS_USB0_FRMNUMH (KINETIS_USB0_BASE+KINETIS_USB_FRMNUMH_OFFSET) +#define KINETIS_USB0_TOKEN (KINETIS_USB0_BASE+KINETIS_USB_TOKEN_OFFSET) +#define KINETIS_USB0_SOFTHLD (KINETIS_USB0_BASE+KINETIS_USB_SOFTHLD_OFFSET) +#define KINETIS_USB0_BDTPAGE2 (KINETIS_USB0_BASE+KINETIS_USB_BDTPAGE2_OFFSET) +#define KINETIS_USB0_BDTPAGE3 (KINETIS_USB0_BASE+KINETIS_USB_BDTPAGE3_OFFSET) + +#define KINETIS_USB0_ENDPT(n) (KINETIS_USB0_BASE+KINETIS_USB_ENDPT_OFFSET(n)) +#define KINETIS_USB0_ENDPT0 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT0_OFFSET) +#define KINETIS_USB0_ENDPT1 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT1_OFFSET) +#define KINETIS_USB0_ENDPT2 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT2_OFFSET) +#define KINETIS_USB0_ENDPT3 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT3_OFFSET) +#define KINETIS_USB0_ENDPT4 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT4_OFFSET) +#define KINETIS_USB0_ENDPT5 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT5_OFFSET) +#define KINETIS_USB0_ENDPT6 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT6_OFFSET) +#define KINETIS_USB0_ENDPT7 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT7_OFFSET) +#define KINETIS_USB0_ENDPT8 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT8_OFFSET) +#define KINETIS_USB0_ENDPT9 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT9_OFFSET) +#define KINETIS_USB0_ENDPT10 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT10_OFFSET) +#define KINETIS_USB0_ENDPT11 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT11_OFFSET) +#define KINETIS_USB0_ENDPT12 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT12_OFFSET) +#define KINETIS_USB0_ENDPT13 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT13_OFFSET) +#define KINETIS_USB0_ENDPT14 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT14_OFFSET) +#define KINETIS_USB0_ENDPT15 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT15_OFFSET) + +#define KINETIS_USB0_USBCTRL (KINETIS_USB0_BASE+KINETIS_USB_USBCTRL_OFFSET) +#define KINETIS_USB0_OBSERVE (KINETIS_USB0_BASE+KINETIS_USB_OBSERVE_OFFSET) +#define KINETIS_USB0_CONTROL (KINETIS_USB0_BASE+KINETIS_USB_CONTROL_OFFSET) +#define KINETIS_USB0_USBTRC0 (KINETIS_USB0_BASE+KINETIS_USB_USBTRC0_OFFSET) + +#ifdef KINETIS_K64 +# define KINETIS_USB_USBFRMADJUST \ + (KINETIS_USB0_BASE+KINETIS_USB_USBFRMADJUST_OFFSET) +# define KINETIS_USB_USB0_CLK_RECOVER_CTRL \ + (KINETIS_USB0_BASE+KINETIS_USB_USB0_CLK_RECOVER_CTRL_OFFSET) +# define KINETIS_USB_USB0_CLK_RECOVER_IRC_EN \ + (KINETIS_USB0_BASE+KINETIS_USB_USB0_CLK_RECOVER_IRC_EN_OFFSET) +# define KINETIS_USB_USB0_CLK_RECOVER_INT_STATUS \ + (KINETIS_USB0_BASE+KINETIS_USB_USB0_CLK_RECOVER_INT_STATUS_OFFSET) +#endif + +/* Register Bit Definitions *****************************************************************/ + +/* Peripheral ID Register (8-bit) */ + /* Bits 6-7: Reserved */ +#define USB_PERID_MASK (0x3f) /* Bits 0-5: Peripheral identification bits */ + +/* Peripheral ID Complement Register (8-bit) */ +#define USB_IDCOMP_ + /* Bits 6-7: Reserved */ +#define USB_IDCOMP_MASK (0x3f) /* Bits 0-5: Ones complement of peripheral identification bits */ + +/* Peripheral Revision Register (8-bit revision number) */ + +/* Peripheral Additional Info Register (8-bit) */ + +#define USB_ADDINFO_IEHOST (1 << 0) /* Bit 0: This bit is set if host mode is enabled */ + /* Bits 1-2: Reserved */ +#define USB_ADDINFO_IRQNUM_SHIFT (3) /* Bits 3-7: Assigned Interrupt Request Number */ +#define USB_ADDINFO_IRQNUM_MASK (31 << USB_ADDINFO_IRQNUM_SHIFT) + +/* OTG Interrupt Status Register(8-bit) */ + +#define USB_OTGISTAT_AVBUSCHG (1 << 0) /* Bit 0: Change in VBUS is detected on an A device */ + /* Bit 1: Reserved */ +#define USB_OTGISTAT_B_SESS_CHG (1 << 2) /* Bit 2: Change in VBUS is detected on a B device */ +#define USB_OTGISTAT_SESSVLDCHG (1 << 3) /* Bit 3: Change in VBUS is detected */ + /* Bit 4: Reserved */ +#define USB_OTGISTAT_LINE_STATE_CHG (1 << 5) /* Bit 5: Change USB line state */ +#define USB_OTGISTAT_ONEMSEC (1 << 6) /* Bit 6: Set when the 1 millisecond timer expires */ +#define USB_OTGISTAT_IDCHG (1 << 7) /* Bit 7: Change in ID Signal from the USB connector */ + +/* OTG Interrupt Control Register (8-bit) */ + +#define USB_OTGICR_AVBUSEN (1 << 0) /* Bit 0: A VBUS Valid interrupt enable */ + /* Bit 1: Reserved */ +#define USB_OTGICR_BSESSEN (1 << 2) /* Bit 2: B Session END interrupt enable */ +#define USB_OTGICR_SESSVLDEN (1 << 3) /* Bit 3: Session valid interrupt enable */ + /* Bit 4: Reserved */ +#define USB_OTGICR_LINESTATEEN (1 << 5) /* Bit 5: Line State change interrupt enable */ +#define USB_OTGICR_ONEMSECEN (1 << 6) /* Bit 6: 1 millisecond interrupt enable */ +#define USB_OTGICR_IDEN (1 << 7) /* Bit 7: ID interrupt enable */ + +/* OTG Status Register (8-bit) */ + +#define USB_OTGSTAT_AVBUSVLD (1 << 0) /* Bit 0: A VBUS Valid */ + /* Bit 1: Reserved */ +#define USB_OTGSTAT_BSESSEND (1 << 2) /* Bit 2: B Session END */ +#define USB_OTGSTAT_SESS_VLD (1 << 3) /* Bit 3: Session valid */ + /* Bit 4: Reserved */ +#define USB_OTGSTAT_LINESTATESTABLE (1 << 5) /* Bit 5: OTGISTAT LINE_STATE_CHG bit stable */ +#define USB_OTGSTAT_ONEMSECEN (1 << 6) /* Bit 6: Reserved for the 1msec count */ +#define USB_OTGSTAT_ID (1 << 7) /* Bit 7: Current state of the ID pin on the USB connector */ + +/* OTG Control Register (8-bit) */ + /* Bits 0-1: Reserved */ +#define USB_OTGCTL_OTGEN (1 << 2) /* Bit 2: On-The-Go pullup/pulldown resistor enable */ + /* Bit 3: Reserved */ +#define USB_OTGCTL_DMLOW (1 << 4) /* Bit 4: D- Data Line pull-down resistor enable */ +#define USB_OTGCTL_DPLOW (1 << 5) /* Bit 5: D+ Data Line pull-down resistor enable */ + /* Bit 6: Reserved */ +#define USB_OTGCTL_DPHIGH (1 << 7) /* Bit 7: D+ Data Line pullup resistor enable */ + +/* Interrupt Status Register Interrupt Enable Register (8-bit) */ + +#define USB_INT_USBRST (1 << 0) /* Bit 0: USB Module has decoded a valid USB reset */ +#define USB_INT_ERROR (1 << 1) /* Bit 1: Any of the error conditions within the ERRSTAT register */ +#define USB_INT_SOFTOK (1 << 2) /* Bit 2: USB Module received a Start Of Frame (SOF) token */ +#define USB_INT_TOKDNE (1 << 3) /* Bit 3: Current token being processed has completed */ +#define USB_INT_SLEEP (1 << 4) /* Bit 4: Constant idle on the USB bus for 3 milliseconds */ +#define USB_INT_RESUME (1 << 5) /* Bit 5: Signal remote wake-up signaling */ +#define USB_INT_ATTACH (1 << 6) /* Bit 6: Attach Interrupt */ +#define USB_INT_STALL (1 << 7) /* Bit 7: Stall Interrupt */ + +#define USB_INT_ALL 0xFF + +/* Error Interrupt Status Register and Error Interrupt Enable Register (8-bit) */ + +#define USB_ERRSTAT_PIDERR (1 << 0) /* Bit 0: This bit is set when the PID check field fails */ +#define USB_ERRSTAT_CRC5EOF (1 << 1) /* Bit 1: Host data CRC error or End of frame errors */ +#define USB_ERRSTAT_CRC16 (1 << 2) /* Bit 2: Data packet is rejected due to a CRC16 error */ +#define USB_ERRSTAT_DFN8 (1 << 3) /* Bit 3: Data field received was not 8 bits in length */ +#define USB_ERRSTAT_BTOERR (1 << 4) /* Bit 4: Bus turnaround timeout error occurred */ +#define USB_ERRSTAT_DMAERR (1 << 5) /* Bit 5: DMA error */ + /* Bit 6: Reserved */ +#define USB_ERRSTAT_BTSERR (1 << 7) /* Bit 7: Bit stuff error is detected */ + +#define USB_EINT_ALL 0xBF + +/* Status Register (8-bit) */ + + /* Bits 0-1: Reserved */ +#define USB_STAT_ODD (1 << 2) /* Bit 2: Last Buffer Descriptor was in the odd bank of the BDT */ +#define USB_STAT_TX (1 << 3) /* Bit 3: Transmit Indicator */ +#define USB_STAT_ENDP_SHIFT (4) /* Bits 4-7: Endpoint address that received or transmitted the token */ +#define USB_STAT_ENDP_MASK (15 << USB_STAT_ENDP_SHIFT) + +/* Control Register (8-bit) */ + +#define USB_CTL_USBENSOFEN (1 << 0) /* Bit 0: USB Enable */ +#define USB_CTL_ODDRST (1 << 1) /* Bit 1: Resets all the BDT ODD ping/pong bits to 0 */ +#define USB_CTL_RESUME (1 << 2) /* Bit 2: Enables the USB Module to execute resume signaling */ +#define USB_CTL_HOSTMODEEN (1 << 3) /* Bit 3: Enables the USB Module to operate in Host mode */ +#define USB_CTL_RESET (1 << 4) /* Bit 4: Enables the USB Module to generate USB reset signaling */ +#define USB_CTL_TXSUSPENDTOKENBUSY (1 << 5) /* Bit 5: USB Module is busy executing a USB token */ +#define USB_CTL_SE0 (1 << 6) /* Bit 6: Live USB Single Ended Zero signal */ +#define USB_CTL_JSTATE (1 << 7) /* Bit 7: Live USB differential receiver JSTATE signal */ + +/* Address Register (8-bit) */ + +#define USB_ADDR_LSEN (1 << 7) /* Bit 7: Low Speed Enable bit */ +#define USB_ADDR_SHIFT (0) /* Bits 0-6: USB address */ +#define USB_ADDR_MASK (0x7f << USB_ADDR_SHIFT) + +/* BDT Page Register 1 (8-bit) */ + /* Bit 0: Reserved */ +#define USB_BDTPAGE1_SHIFT (1) /* Bits 1-7: Address bits 9-15 of the BDT base address */ +#define USB_BDTPAGE1_MASK (0x7f << USB_BDTPAGE1_SHIFT) + +/* Frame Number Register Low (8-bit, bits 0-7 of the 11 bit frame number) */ +#define USB_FRMNUML_MASK 0xFF +/* Frame Number Register High (8-bit) */ + /* Bits 3-7: Reserved */ +#define USB_FRMNUMH_SHIFT (0) /* Bits 0-2: Bits 8-10 of the 11-bit frame number */ +#define USB_FRMNUMH_MASK (7 << USB_FRMNUMH_SHIFT) + +/* Token Register (8-bit) */ + +#define USB_TOKEN_ENDPT_SHIFT (0) /* Bits 0-3: Endpoint address for the token command */ +#define USB_TOKEN_ENDPT_MASK (15 << USB_TOKEN_ENDPT_SHIFT) +#define USB_TOKEN_PID_SHIFT (4) /* Bits 4-7: Token type executed by the USB Module */ +#define USB_TOKEN_PID_MASK (15 << USB_TOKEN_PID_SHIFT) +# define USB_TOKEN_PID_OUT (1 << USB_TOKEN_PID_SHIFT) /* OUT Token */ +# define USB_TOKEN_PID_IN (9 << USB_TOKEN_PID_SHIFT) /* IN Token */ +# define USB_TOKEN_PID_SETUP (13 << USB_TOKEN_PID_SHIFT) /* SETUP Token */ + +/* SOF Threshold Register (8-bit count value) */ +/* BDT Page Register 2/3 (16 bit address in two 8-bit registers) */ + +/* Endpoint n Control Register (8-bit) */ + +#define USB_ENDPT_EPHSHK (1 << 0) /* Bit 0: Enable handshaking during a transaction to the endpoint */ +#define USB_ENDPT_EPSTALL (1 << 1) /* Bit 1: Endpoint is stalled */ +#define USB_ENDPT_EPTXEN (1 << 2) /* Bit 2: Enable the endpoint for TX transfers */ +#define USB_ENDPT_EPRXEN (1 << 3) /* Bit 3: Enable the endpoint for RX transfers */ +#define USB_ENDPT_EPCTLDIS (1 << 4) /* Bit 4: Disable control (SETUP) transfers */ + /* Bit 5: Reserved */ +#define USB_ENDPT_RETRYDIS (1 << 6) /* Bit 6: Disable host retry NAK'ed transactions (host EP0) */ +#define USB_ENDPT_HOSTWOHUB (1 << 7) /* Bit 7: Allows the host to communicate to a low speed device (host EP0) */ + +/* USB Control Register (8-bit) */ + /* Bits 0-5: Reserved */ +#define USB_USBCTRL_PDE (1 << 6) /* Bit 6: Enables the weak pulldowns on the USB transceiver */ +#define USB_USBCTRL_SUSP (1 << 7) /* Bit 7: Places the USB transceiver into the suspend state */ + +/* USB OTG Observe Register (8-bit) */ + /* Bits 0-3: Reserved */ +#define USB_OBSERVE_DMPD (1 << 4) /* Bit 4: D- Pull Down signal output from the USB OTG module */ + /* Bit 5: Reserved */ +#define USB_OBSERVE_DPPD (1 << 6) /* Bit 6: D+ Pull Down signal output from the USB OTG module */ +#define USB_OBSERVE_DPPU (1 << 7) /* Bit 7: D+ Pull Up signal output from the USB OTG module */ + +/* USB OTG Control Register (8-bit) */ + /* Bits 0-3: Reserved */ +#define USB_CONTROL_DPPULLUPNONOTG (1 << 4) /* Bit 4: Controls of the DP PULLUP in the USB OTG module */ + /* Bits 5-7: Reserved */ +/* USB Transceiver Control Register 0 (8-bit) */ + +#define USB_USBTRC0_USBRESET (1 << 7) /* Bit 7: USB reset */ + /* Bit 6: Reserved */ +#define USB_USBTRC0_USBRESMEN (1 << 5) /* Bit 5: Asynchronous Resume Interrupt Enable */ + /* Bits 2-4: Reserved */ +#define USB_USBTRC0_SYNC_DET (1 << 1) /* Bit 1: Synchronous USB Interrupt Detect */ +#define USB_USBTRC0_RESUME_INT (1 << 0) /* Bit 0: USB Asynchronous Interrupt */ + +/* Buffer Descriptor Table (BDT) ****************************************************/ +/* Offset 0: On write (software->hardware) */ + +#define USB_BDT_STATUS_MASK 0xfc /* Bits 2-7: Status bits */ +#define USB_BDT_BSTALL (1 << 2) /* Bit 2: Buffer Stall Enable bit */ +#define USB_BDT_DTS (1 << 3) /* Bit 3: Data Toggle Synchronization Enable bit */ +#define USB_BDT_NINC (1 << 4) /* Bit 4: DMA Address Increment Disable bit */ +#define USB_BDT_KEEP (1 << 5) /* Bit 5: BD Keep Enable bit */ +#define USB_BDT_DATA01 (1 << 6) /* Bit 6: Data Toggle Packet bit */ +#define USB_BDT_UOWN (1 << 7) /* Bit 7: USB Own bit */ +#define USB_BDT_BYTECOUNT_SHIFT (16) /* Bits 16-25: Byte Count bits */ +#define USB_BDT_BYTECOUNT_MASK (0x3ff << USB_BDT_BYTECOUNT_SHIFT) + +#define USB_BDT_DATA0 0 /* DATA0 packet expected next */ +#define USB_BDT_DATA1 USB_BDT_DATA01 /* DATA1 packet expected next */ +#define USB_BDT_COWN 0 /* CPU owns the descriptor */ + +/* Offset 0: On read (hardware->software) */ + +#define USB_BDT_PID_SHIFT (2) /* Bits 2-5: Packet Identifier bits */ +#define USB_BDT_PID_MASK (15 << USB_BDT_PID_SHIFT) + /* Bit 7: USB Own bit (same) */ + /* Bits 16-25: Byte Count bits (same) */ + +/* Offset 4: BUFFER_ADDRESS, 32-bit Buffer Address bits */ + +#define USB_BDT_BYTES_SIZE 8 /* Eight bytes per BDT */ +#define USB_BDT_WORD_SIZE 2 /* Two 32-bit words per BDT */ +#define USB_NBDTS_PER_EP 4 /* Number of BDTS per endpoint: IN/OUT and EVEN/ODD */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/******************************************************************************************** + * Public Functions + ********************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_USBOTG_H */ diff --git a/arch/arm/src/kinetis/kinetis_vrefv1.h b/arch/arm/src/kinetis/chip/kinetis_vrefv1.h similarity index 94% rename from arch/arm/src/kinetis/kinetis_vrefv1.h rename to arch/arm/src/kinetis/chip/kinetis_vrefv1.h index ed9a1ff95c5dc51779b89864f9ac29f5f73f371c..29c871dd22d10fb2066d2ea564a93be9eadc036d 100644 --- a/arch/arm/src/kinetis/kinetis_vrefv1.h +++ b/arch/arm/src/kinetis/chip/kinetis_vrefv1.h @@ -1,7 +1,7 @@ /******************************************************************************************** - * arch/arm/src/kinetis/kinetis_vrefv1.h + * arch/arm/src/kinetis/chip/kinetis_vrefv1.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ********************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_VREFV1_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_VREFV1_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_VREFV1_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_VREFV1_H /******************************************************************************************** * Included Files @@ -89,4 +89,4 @@ * Public Functions ********************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_VREFV1_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_VREFV1_H */ diff --git a/arch/arm/src/kinetis/kinetis_wdog.h b/arch/arm/src/kinetis/chip/kinetis_wdog.h similarity index 95% rename from arch/arm/src/kinetis/kinetis_wdog.h rename to arch/arm/src/kinetis/chip/kinetis_wdog.h index 326c2cf628fe360fc904dc2f51ebe09008fd24ed..6f50386049900167f4930e4ab19dc3775a51e696 100644 --- a/arch/arm/src/kinetis/kinetis_wdog.h +++ b/arch/arm/src/kinetis/chip/kinetis_wdog.h @@ -1,7 +1,7 @@ /******************************************************************************************** - * arch/arm/src/kinetis/kinetis_wdog.h + * arch/arm/src/kinetis/chip/kinetis_wdog.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ********************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_WDOG_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_WDOG_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_WDOG_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_WDOG_H /******************************************************************************************** * Included Files @@ -90,7 +90,9 @@ #define WDOG_STCTRLH_DBGEN (1 << 5) /* Bit 5: Enables or disables WDOG in Debug mode */ #define WDOG_STCTRLH_STOPEN (1 << 6) /* Bit 6: Enables or disables WDOG in stop mode */ #define WDOG_STCTRLH_WAITEN (1 << 7) /* Bit 7: Enables or disables WDOG in wait mode */ -#define WDOG_STCTRLH_STNDBYEN (1 << 8) /* Bit 8: Enables or disables WDOG in Standby mode */ +#ifndef KINETIS_K64 +# define WDOG_STCTRLH_STNDBYEN (1 << 8) /* Bit 8: Enables or disables WDOG in Standby mode */ +#endif /* Bit 9: Reserved */ #define WDOG_STCTRLH_TESTWDOG (1 << 10) /* Bit 10: Selects functional test mode */ #define WDOG_STCTRLH_TESTSEL (1 << 11) /* Bit 11: Selects the test to be run */ @@ -132,4 +134,4 @@ * Public Functions ********************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_WDOG_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_WDOG_H */ diff --git a/arch/arm/src/kinetis/kinetis.h b/arch/arm/src/kinetis/kinetis.h index ae02ce7e4f81aae52892db227f2874b25d47dd0b..fccd4b90af7bfa964d59d3169636b9d92ba82d05 100644 --- a/arch/arm/src/kinetis/kinetis.h +++ b/arch/arm/src/kinetis/kinetis.h @@ -52,7 +52,7 @@ #include "up_internal.h" #include "kinetis_config.h" #include "chip.h" -#include "kinetis_port.h" +#include "chip/kinetis_port.h" /************************************************************************************ * Pre-processor Definitions diff --git a/arch/arm/src/kinetis/kinetis_clockconfig.c b/arch/arm/src/kinetis/kinetis_clockconfig.c index 7221b9dc6e76416e6edc83b1ef9b1ddac09e7f34..2f703ea96e7fc502409a4b5e1f63c152995f991d 100644 --- a/arch/arm/src/kinetis/kinetis_clockconfig.c +++ b/arch/arm/src/kinetis/kinetis_clockconfig.c @@ -44,11 +44,11 @@ #include "up_arch.h" #include "kinetis.h" -#include "kinetis_mcg.h" -#include "kinetis_sim.h" -#include "kinetis_fmc.h" -#include "kinetis_llwu.h" -#include "kinetis_pinmux.h" +#include "chip/kinetis_mcg.h" +#include "chip/kinetis_sim.h" +#include "chip/kinetis_fmc.h" +#include "chip/kinetis_llwu.h" +#include "chip/kinetis_pinmux.h" /**************************************************************************** * Pre-processor Definitions @@ -373,6 +373,3 @@ kinesis_setdividers(uint32_t div1, uint32_t div2, uint32_t div3, uint32_t div4) putreg32(regval, KINETIS_FMC_PFAPR); } - - - diff --git a/arch/arm/src/kinetis/kinetis_config.h b/arch/arm/src/kinetis/kinetis_config.h index ce1c6efedf79b6d7348ef4a04fb77b12d3cc1d15..1ce2e7ee5e3e6b80a4a27aec8b5d92e861e44791 100644 --- a/arch/arm/src/kinetis/kinetis_config.h +++ b/arch/arm/src/kinetis/kinetis_config.h @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETISXX_KINETIS_CONFIG_H -#define __ARCH_ARM_SRC_KINETISXX_KINETIS_CONFIG_H +#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_CONFIG_H +#define __ARCH_ARM_SRC_KINETIS_KINETIS_CONFIG_H /************************************************************************************ * Included Files @@ -232,4 +232,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETISXX_KINETIS_CONFIG_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_CONFIG_H */ diff --git a/arch/arm/src/kinetis/kinetis_enet.c b/arch/arm/src/kinetis/kinetis_enet.c index aa4b3cf10165271bcfb3acb4dd3e1817f8692d4f..4a263a8c37836ca61c8da1e959aaacdc5915e8ed 100644 --- a/arch/arm/src/kinetis/kinetis_enet.c +++ b/arch/arm/src/kinetis/kinetis_enet.c @@ -1,5 +1,5 @@ /**************************************************************************** - * drivers/net/kinetis_enet.c + * arch/arm/src/kinetis/kinetis_enet.c * * Copyright (C) 2011-2012, 2014-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -65,10 +65,10 @@ #include "chip.h" #include "kinetis.h" #include "kinetis_config.h" -#include "kinetis_pinmux.h" -#include "kinetis_sim.h" -#include "kinetis_mpu.h" -#include "kinetis_enet.h" +#include "chip/kinetis_pinmux.h" +#include "chip/kinetis_sim.h" +#include "chip/kinetis_mpu.h" +#include "chip/kinetis_enet.h" #if defined(KINETIS_NENET) && KINETIS_NENET > 0 diff --git a/arch/arm/src/kinetis/kinetis_ftfl.h b/arch/arm/src/kinetis/kinetis_ftfl.h deleted file mode 100644 index 92e53b650d03d2cfbaf6ba3b3cd9427304069d8d..0000000000000000000000000000000000000000 --- a/arch/arm/src/kinetis/kinetis_ftfl.h +++ /dev/null @@ -1,159 +0,0 @@ -/************************************************************************************ - * arch/arm/src/kinetis/kinetis_ftfl.h - * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_FTFL_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_FTFL_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register Offsets *****************************************************************/ - -#define KINETIS_FTFL_FSTAT_OFFSET 0x0000 /* Flash Status Register */ -#define KINETIS_FTFL_FCNFG_OFFSET 0x0001 /* Flash Configuration Register */ -#define KINETIS_FTFL_FSEC_OFFSET 0x0002 /* Flash Security Register */ -#define KINETIS_FTFL_FOPT_OFFSET 0x0003 /* Flash Option Register */ - -#define KINETIS_FTFL_FCCOB3_OFFSET 0x0004 /* Flash Common Command Object Registers */ -#define KINETIS_FTFL_FCCOB2_OFFSET 0x0005 /* Flash Common Command Object Registers */ -#define KINETIS_FTFL_FCCOB1_OFFSET 0x0006 /* Flash Common Command Object Registers */ -#define KINETIS_FTFL_FCCOB0_OFFSET 0x0007 /* Flash Common Command Object Registers */ -#define KINETIS_FTFL_FCCOB7_OFFSET 0x0008 /* Flash Common Command Object Registers */ -#define KINETIS_FTFL_FCCOB6_OFFSET 0x0009 /* Flash Common Command Object Registers */ -#define KINETIS_FTFL_FCCOB5_OFFSET 0x000a /* Flash Common Command Object Registers */ -#define KINETIS_FTFL_FCCOB4_OFFSET 0x000b /* Flash Common Command Object Registers */ -#define KINETIS_FTFL_FCCOBB_OFFSET 0x000c /* Flash Common Command Object Registers */ -#define KINETIS_FTFL_FCCOBA_OFFSET 0x000d /* Flash Common Command Object Registers */ -#define KINETIS_FTFL_FCCOB9_OFFSET 0x000e /* Flash Common Command Object Registers */ -#define KINETIS_FTFL_FCCOB8_OFFSET 0x000f /* Flash Common Command Object Registers */ -#define KINETIS_FTFL_FPROT3_OFFSET 0x0010 /* Program Flash Protection Registers */ -#define KINETIS_FTFL_FPROT2_OFFSET 0x0011 /* Program Flash Protection Registers */ -#define KINETIS_FTFL_FPROT1_OFFSET 0x0012 /* Program Flash Protection Registers */ -#define KINETIS_FTFL_FPROT0_OFFSET 0x0013 /* Program Flash Protection Registers */ -#define KINETIS_FTFL_FEPROT_OFFSET 0x0016 /* EEPROM Protection Register */ -#define KINETIS_FTFL_FDPROT_OFFSET 0x0017 /* Data Flash Protection Register */ - -/* Register Addresses ***************************************************************/ - -#define KINETIS_FTFL_FSTAT (KINETIS_FTFL_BASE+KINETIS_FTFL_FSTAT_OFFSET) -#define KINETIS_FTFL_FCNFG (KINETIS_FTFL_BASE+KINETIS_FTFL_FCNFG_OFFSET) -#define KINETIS_FTFL_FSEC (KINETIS_FTFL_BASE+KINETIS_FTFL_FSEC_OFFSET) -#define KINETIS_FTFL_FOPT (KINETIS_FTFL_BASE+KINETIS_FTFL_FOPT_OFFSET) -#define KINETIS_FTFL_FCCOB3 (KINETIS_FTFL_BASE+KINETIS_FTFL_FCCOB3_OFFSET) -#define KINETIS_FTFL_FCCOB2 (KINETIS_FTFL_BASE+KINETIS_FTFL_FCCOB2_OFFSET) -#define KINETIS_FTFL_FCCOB1 (KINETIS_FTFL_BASE+KINETIS_FTFL_FCCOB1_OFFSET) -#define KINETIS_FTFL_FCCOB0 (KINETIS_FTFL_BASE+KINETIS_FTFL_FCCOB0_OFFSET) -#define KINETIS_FTFL_FCCOB7 (KINETIS_FTFL_BASE+KINETIS_FTFL_FCCOB7_OFFSET) -#define KINETIS_FTFL_FCCOB6 (KINETIS_FTFL_BASE+KINETIS_FTFL_FCCOB6_OFFSET) -#define KINETIS_FTFL_FCCOB5 (KINETIS_FTFL_BASE+KINETIS_FTFL_FCCOB5_OFFSET) -#define KINETIS_FTFL_FCCOB4 (KINETIS_FTFL_BASE+KINETIS_FTFL_FCCOB4_OFFSET) -#define KINETIS_FTFL_FCCOBB (KINETIS_FTFL_BASE+KINETIS_FTFL_FCCOBB_OFFSET) -#define KINETIS_FTFL_FCCOBA (KINETIS_FTFL_BASE+KINETIS_FTFL_FCCOBA_OFFSET) -#define KINETIS_FTFL_FCCOB9 (KINETIS_FTFL_BASE+KINETIS_FTFL_FCCOB9_OFFSET) -#define KINETIS_FTFL_FCCOB8 (KINETIS_FTFL_BASE+KINETIS_FTFL_FCCOB8_OFFSET) -#define KINETIS_FTFL_FPROT3 (KINETIS_FTFL_BASE+KINETIS_FTFL_FPROT3_OFFSET) -#define KINETIS_FTFL_FPROT2 (KINETIS_FTFL_BASE+KINETIS_FTFL_FPROT2_OFFSET) -#define KINETIS_FTFL_FPROT1 (KINETIS_FTFL_BASE+KINETIS_FTFL_FPROT1_OFFSET) -#define KINETIS_FTFL_FPROT0 (KINETIS_FTFL_BASE+KINETIS_FTFL_FPROT0_OFFSET) -#define KINETIS_FTFL_FEPROT (KINETIS_FTFL_BASE+KINETIS_FTFL_FEPROT_OFFSET) -#define KINETIS_FTFL_FDPROT (KINETIS_FTFL_BASE+KINETIS_FTFL_FDPROT_OFFSET) - -/* Register Bit Definitions *********************************************************/ - -/* Flash Status Register */ - -#define FTFL_FSTAT_MGSTAT0 (1 << 0) /* Bit 0: Memory Controller Command Completion Status Flag */ - /* Bits 1-3: Reserved */ -#define FTFL_FSTAT_FPVIOL (1 << 4) /* Bit 4: Flash Protection Violation Flag */ -#define FTFL_FSTAT_ACCERR (1 << 5) /* Bit 5: Flash Access Error Flag */ -#define FTFL_FSTAT_RDCOLERR (1 << 6) /* Bit 6: FTFL Read Collision Error Flag */ -#define FTFL_FSTAT_CCIF (1 << 7) /* Bit 7: Command Complete Interrupt Flag */ - -/* Flash Configuration Register */ - -#define FTFL_FCNFG_EEERDY (1 << 0) /* Bit 0: FEEPROM backup data copied to FlexRAM */ -#define FTFL_FCNFG_RAMRDY (1 << 1) /* Bit 1: RAM Ready */ -#define FTFL_FCNFG_PFLSH (1 << 2) /* Bit 2: FTFL configuration */ -#define FTFL_FCNFG_SWAP (1 << 3) /* Bit 3: Swap */ -#define FTFL_FCNFG_ERSSUSP (1 << 4) /* Bit 4: Erase Suspend */ -#define FTFL_FCNFG_ERSAREQ (1 << 5) /* Bit 5: Erase All Request */ -#define FTFL_FCNFG_RDCOLLIE (1 << 6) /* Bit 6: Read Collision Error Interrupt Enable */ -#define FTFL_FCNFG_CCIE (1 << 7) /* Bit 7: Command Complete Interrupt Enable */ - -/* Flash Security Register */ - -#define FTFL_FSEC_SEC_SHIFT (0) /* Bits 0-1: Flash Security */ -#define FTFL_FSEC_SEC_MASK (3 << FTFL_FSEC_SEC_SHIFT) -# define FTFL_FSEC_SEC_SECURE (0 << FTFL_FSEC_SEC_SHIFT) /* 00,01,11: status is secure */ -# define FTFL_FSEC_SEC_UNSECURE (2 << FTFL_FSEC_SEC_SHIFT) /* 10: status is insecure */ -#define FTFL_FSEC_FSLACC_SHIFT (2) /* Bits 2-3: Freescale Failure Analysis Access Code */ -#define FTFL_FSEC_FSLACC_MASK (3 << FTFL_FSEC_FSLACC_SHIFT) -# define FTFL_FSEC_FSLACC_GRANTED (0 << FTFL_FSEC_FSLACC_SHIFT) /* 00 or 11: Access granted */ -# define FTFL_FSEC_FSLACC_DENIED (1 << FTFL_FSEC_FSLACC_SHIFT) /* 01 or 10: Access denied */ -#define FTFL_FSEC_MEEN_SHIFT (4) /* Bits 4-5: Mass Erase Enable Bits */ -#define FTFL_FSEC_MEEN_MASK (3 << FTFL_FSEC_MEEN_SHIFT) -# define FTFL_FSEC_MEEN_ENABLED (0 << FTFL_FSEC_MEEN_SHIFT) /* All values are enabled */ -#define FTFL_FSEC_KEYEN_SHIFT (6) /* Bits 6-7: Backdoor Key Security Enable */ -#define FTFL_FSEC_KEYEN_MASK (3 << FTFL_FSEC_KEYEN_SHIFT) -# define FTFL_FSEC_KEYEN_DISABLED (1 << FTFL_FSEC_KEYEN_SHIFT) /* All values are disabled */ - -/* Flash Option Register (32-bits, see Chip Configuration details) */ -/* Flash Common Command Object Registers (8-bit flash command data) */ -/* Program Flash Protection Registers (8-bit flash protection data) */ -/* EEPROM Protection Register (8-bit eeprom protection data) */ -/* Data Flash Protection Register (8-bit data flash protection data) */ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_FTFL_H */ diff --git a/arch/arm/src/kinetis/kinetis_lowputc.c b/arch/arm/src/kinetis/kinetis_lowputc.c index bd3b27a8769bd97d4945ad5d32e2d6e3637bfd52..ec85713c9331564ff3c7a2c6baed916ef561faff 100644 --- a/arch/arm/src/kinetis/kinetis_lowputc.c +++ b/arch/arm/src/kinetis/kinetis_lowputc.c @@ -49,9 +49,9 @@ #include "kinetis_config.h" #include "kinetis.h" -#include "kinetis_uart.h" -#include "kinetis_sim.h" -#include "kinetis_pinmux.h" +#include "chip/kinetis_uart.h" +#include "chip/kinetis_sim.h" +#include "chip/kinetis_pinmux.h" /**************************************************************************** * Pre-processor Definitions diff --git a/arch/arm/src/kinetis/kinetis_memorymap.h b/arch/arm/src/kinetis/kinetis_memorymap.h deleted file mode 100644 index 1e7d2820de451ebfd117c086c31a2de30e2ba3ff..0000000000000000000000000000000000000000 --- a/arch/arm/src/kinetis/kinetis_memorymap.h +++ /dev/null @@ -1,461 +0,0 @@ -/************************************************************************************ - * arch/arm/src/kinetis/kinetis_memorymap.h - * - * Copyright (C) 2011, 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_MEMORYMAP_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_MEMORYMAP_H - -/************************************************************************************ - * Included Files - ************************************************************************************/ - -#include - -#include "chip.h" - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Memory Map ***********************************************************************/ -/* K20 Family - * - * The memory map for the following parts is defined in Freescale document - * K20P64M72SF1RM - */ - -#if defined(CONFIG_ARCH_CHIP_MK20DX256VLH7) - -# define KINETIS_FLASH_BASE 0x00000000 /* –0x0fffffff Program flash and read- - * only data (Includes exception - * vectors in first 1024 bytes) */ -# if !defined(KINETIS_FLEXMEM_SIZE) -# define KINETIS_FLEXNVM_BASE 0x10000000 /* –0x13ffffff FlexNVM */ -# define KINETIS_FLEXRAM_BASE 0x14000000 /* –0x17ffffff FlexRAM */ -# endif - /* 0x18000000 * –0x1bffffff Reserved */ -# define KINETIS_SRAML_BASE 0x1c000000 /* –0x1fffffff SRAM_L: Lower SRAM - * (ICODE/DCODE) */ -# define KINETIS_SRAMU_BASE 0x20000000 /* –0x200fffff SRAM_U: Upper SRAM bitband - * region */ - /* 0x20100000 * –0x21ffffff Reserved */ -# define KINETIS_SALIAS_BASE 0x22000000 /* –0x23ffffff Aliased to SRAM_U bitband */ - /* 0x24000000 * –0x3fffffff Reserved */ -# define KINETIS_BRIDGE0_BASE 0x40000000 /* –0x4007ffff Bitband region for peripheral - * bridge 0 (AIPS-Lite0) */ -# define KINETIS_BRIDGE1_BASE 0x40080000 /* –0x400fffff Bitband region for peripheral - * bridge 1 (AIPS-Lite1) */ -# define KINETIS_GPIOBB_BASE 0x400ff000 /* –0x400fffff Bitband region for general - * purpose input/output (GPIO) */ - /* 0x40100000 * –0x41ffffff Reserved */ -# define KINETIS_PALIAS_BASE 0x42000000 /* –0x43ffffff Aliased to peripheral bridge - * (AIPS-Lite) and general purpose - * input/output (GPIO) bitband */ - /* 0x44000000 * –0xdfffffff Reserved */ -# define KINETIS_PERIPH_BASE 0xe0000000 /* –0xe00fffff Private peripherals */ - /* 0xe0100000 * –0xffffffff Reserved */ - -/* Peripheral Bridge 0 Memory Map ***************************************************/ - -# define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */ -# define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */ -# define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */ -# define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */ -# define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */ -# define KINETIS_FTFL_BASE 0x40020000 /* Flash memory */ -# define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel mutiplexer 0 */ -# define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */ -# define KINETIS_SPI0_BASE 0x4002c000 /* SPI 0 */ -# define KINETIS_SPI1_BASE 0x4002d000 /* SPI 1 */ -# define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */ -# define KINETIS_CRC_BASE 0x40032000 /* CRC */ -# define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */ -# define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */ -# define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */ -# define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer 0 */ -# define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer 1 */ -# define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */ -# define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */ -# define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */ -# define KINETIS_LPTMR_BASE 0x40040000 /* Low power timer */ -# define KINETIS_SYSR_BASE 0x40041000 /* System register file */ -# define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */ -# define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */ -# define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */ -# define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12)) -# define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */ -# define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */ -# define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */ -# define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */ -# define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */ -# define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */ -# define KINETIS_EWM_BASE 0x40061000 /* External watchdog */ -# define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */ -# define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */ -# define KINETIS_OSC_BASE 0x40065000 /* System oscillator (OSC) */ -# define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */ -# define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */ -# define KINETIS_UART0_BASE 0x4006a000 /* UART0 */ -# define KINETIS_UART1_BASE 0x4006b000 /* UART1 */ -# define KINETIS_UART2_BASE 0x4006c000 /* UART2 */ -# define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */ -# define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ -# define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */ -# define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */ -# define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */ -# define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */ - -/* Peripheral Bridge 1 Memory Map ***************************************************/ - -# define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */ -# define KINETIS_FTM2_BASE 0x400b8000 /* FlexTimer 2 */ -# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */ -# define KINETIS_DAC0_BASE 0x400cc000 /* 12-bit digital-to-analog converter (DAC) 0 */ - -# define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general - * purpose input/output module that shares the - * crossbar switch slave port with the AIPS-Lite - * is accessed at this address. */ -# define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6)) -# define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */ -# define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */ -# define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */ -# define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */ -# define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */ - -/* Private Peripheral Bus (PPB) Memory Map ******************************************/ - -# define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */ -# define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */ -# define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */ -# define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */ -# define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */ -# define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */ -# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */ - -/* Memory Map ***********************************************************************/ -/* K40 Family - * - * The memory map for the following parts is defined in Freescale document - * K40P144M100SF2RM - */ - -#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) || \ - defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100) || \ - defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100) - -# define KINETIS_FLASH_BASE 0x00000000 /* –0x0fffffff Program flash and read- - * only data (Includes exception - * vectors in first 1024 bytes) */ -# if !defined(KINETIS_FLEXMEM_SIZE) -# define KINETIS_FLEXNVM_BASE 0x10000000 /* –0x13ffffff FlexNVM */ -# define KINETIS_FLEXRAM_BASE 0x14000000 /* –0x17ffffff FlexRAM */ -# endif -# define KINETIS_SRAML_BASE 0x18000000 /* –0x1fffffff SRAM_L: Lower SRAM - * (ICODE/DCODE) */ -# define KINETIS_SRAMU_BASE 0x20000000 /* –0x200fffff SRAM_U: Upper SRAM bitband - * region */ - /* 0x20100000 * –0x21ffffff Reserved */ -# define KINETIS_SALIAS_BASE 0x22000000 /* –0x23ffffff Aliased to SRAM_U bitband */ - /* 0x24000000 * –0x3fffffff Reserved */ -# define KINETIS_BRIDGE0_BASE 0x40000000 /* –0x4007ffff Bitband region for peripheral - * bridge 0 (AIPS-Lite0) */ -# define KINETIS_BRIDGE1_BASE 0x40080000 /* –0x400fffff Bitband region for peripheral - * bridge 1 (AIPS-Lite1) */ -# define KINETIS_GPIOBB_BASE 0x400ff000 /* –0x400fffff Bitband region for general - * purpose input/output (GPIO) */ - /* 0x40100000 * –0x41ffffff Reserved */ -# define KINETIS_PALIAS_BASE 0x42000000 /* –0x43ffffff Aliased to peripheral bridge - * (AIPS-Lite) and general purpose - * input/output (GPIO) bitband */ - /* 0x44000000 * –0x5fffffff Reserved */ -# define KINETIS_FLEXBUS_WBBASE 0x60000000 /* –0x7fffffff FlexBus (External Memory - - * Write-back) */ -# define KINETIS_FLEXBUS_WTBASE 0x80000000 /* –0x9fffffff FlexBus (External Memory - - * Write-through) */ -# define KINETIS_FLEXBUS_NXBASE 0xa0000000 /* –0xdfffffff FlexBus (External Memory - - * Non-executable) */ -# define KINETIS_PERIPH_BASE 0xe0000000 /* –0xe00fffff Private peripherals */ - /* 0xe0100000 * –0xffffffff Reserved */ - -/* Peripheral Bridge 0 Memory Map ***************************************************/ - -# define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */ -# define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */ -# define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */ -# define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */ -# define KINETIS_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */ -# define KINETIS_MPU_BASE 0x4000d000 /* MPU */ -# define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */ -# define KINETIS_FTFL_BASE 0x40020000 /* Flash memory */ -# define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel mutiplexer 0 */ -# define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */ -# define KINETIS_SPI0_BASE 0x4002c000 /* SPI 0 */ -# define KINETIS_SPI1_BASE 0x4002d000 /* SPI 1 */ -# define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */ -# define KINETIS_CRC_BASE 0x40032000 /* CRC */ -# define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */ -# define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */ -# define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */ -# define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer 0 */ -# define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer 1 */ -# define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */ -# define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */ -# define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */ -# define KINETIS_LPTMR_BASE 0x40040000 /* Low power timer */ -# define KINETIS_SYSR_BASE 0x40041000 /* System register file */ -# define KINETIS_DRYICE_BASE 0x40042000 /* DryIce */ -# define KINETIS_DRYICESS_BASE 0x40043000 /* DryIce secure storage */ -# define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */ -# define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */ -# define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */ -# define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12)) -# define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */ -# define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */ -# define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */ -# define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */ -# define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */ -# define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */ -# define KINETIS_EWM_BASE 0x40061000 /* External watchdog */ -# define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */ -# define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */ -# define KINETIS_OSC_BASE 0x40065000 /* System oscillator (OSC) */ -# define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */ -# define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */ -# define KINETIS_UART0_BASE 0x4006a000 /* UART0 */ -# define KINETIS_UART1_BASE 0x4006b000 /* UART1 */ -# define KINETIS_UART2_BASE 0x4006c000 /* UART2 */ -# define KINETIS_UART3_BASE 0x4006d000 /* UART3 */ -# define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */ -# define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ -# define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */ -# define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */ -# define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */ -# define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */ - -/* Peripheral Bridge 1 Memory Map ***************************************************/ - -# define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */ -# define KINETIS_CAN1_BASE 0x400a4000 /* FlexCAN 1 */ -# define KINETIS_SPI2_BASE 0x400ac000 /* SPI 2 */ -# define KINETIS_SDHC_BASE 0x400b1000 /* SDHC */ -# define KINETIS_FTM2_BASE 0x400b8000 /* FlexTimer 2 */ -# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */ -# define KINETIS_SLCD_BASE 0x400be000 /* Segment LCD */ -# define KINETIS_DAC0_BASE 0x400cc000 /* 12-bit digital-to-analog converter (DAC) 0 */ -# define KINETIS_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */ -# define KINETIS_UART4_BASE 0x400ea000 /* UART4 */ -# define KINETIS_UART5_BASE 0x400eb000 /* UART5 */ -# define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general - * purpose input/output module that shares the - * crossbar switch slave port with the AIPS-Lite - * is accessed at this address. */ -# define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6)) -# define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */ -# define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */ -# define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */ -# define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */ -# define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */ - -/* Private Peripheral Bus (PPB) Memory Map ******************************************/ - -# define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */ -# define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */ -# define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */ -# define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */ -# define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */ -# define KINETIS_ETM_BASE 0xe0041000 /* Embedded Trace Macrocell (ETM) */ -# define KINETIS_ETB_BASE 0xe0042000 /* Embedded Trace Buffer (ETB) */ -# define KINETIS_TFUN_BASE 0xe0043000 /* Embedded Trace Funnel */ -# define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */ -# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */ - -/* Memory Map ***********************************************************************/ -/* K60 Family - * - * The memory map for the following parts is defined in Freescale document - * K60P144M100SF2RM - */ - -#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100) || defined(CONFIG_ARCH_CHIP_MK60X256VLQ100) || \ - defined(CONFIG_ARCH_CHIP_MK60N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK60N256VMD100) || \ - defined(CONFIG_ARCH_CHIP_MK60X256VMD100) || defined(CONFIG_ARCH_CHIP_MK60N512VMD100) || \ - defined(CONFIG_ARCH_CHIP_MK60N512VLL100) - -# define KINETIS_FLASH_BASE 0x00000000 /* –0x0fffffff Program flash and read- - * only data (Includes exception - * vectors in first 1024 bytes) */ -# if !defined(KINETIS_FLEXMEM_SIZE) -# define KINETIS_FLEXNVM_BASE 0x10000000 /* –0x13ffffff FlexNVM */ -# define KINETIS_FLEXRAM_BASE 0x14000000 /* –0x17ffffff FlexRAM */ -# endif -# define KINETIS_SRAML_BASE 0x18000000 /* –0x1fffffff SRAM_L: Lower SRAM - * (ICODE/DCODE) */ -# define KINETIS_SRAMU_BASE 0x20000000 /* –0x200fffff SRAM_U: Upper SRAM bitband - * region */ - /* 0x20100000 * –0x21ffffff Reserved */ -# define KINETIS_SALIAS_BASE 0x22000000 /* –0x23ffffff Aliased to SRAM_U bitband */ - /* 0x24000000 * –0x3fffffff Reserved */ -# define KINETIS_BRIDGE0_BASE 0x40000000 /* –0x4007ffff Bitband region for peripheral - * bridge 0 (AIPS-Lite0) */ -# define KINETIS_BRIDGE1_BASE 0x40080000 /* –0x400fffff Bitband region for peripheral - * bridge 1 (AIPS-Lite1) */ -# define KINETIS_GPIOBB_BASE 0x400ff000 /* –0x400fffff Bitband region for general - * purpose input/output (GPIO) */ - /* 0x40100000 * –0x41ffffff Reserved */ -# define KINETIS_PALIAS_BASE 0x42000000 /* –0x43ffffff Aliased to peripheral bridge - * (AIPS-Lite) and general purpose - * input/output (GPIO) bitband */ - /* 0x44000000 * –0x5fffffff Reserved */ -# define KINETIS_FLEXBUS_BASE 0x60000000 /* –0x7fffffff FlexBus */ -# define KINETIS_PERIPH_BASE 0xe0000000 /* –0xe00fffff Private peripherals */ - /* 0xe0100000 * –0xffffffff Reserved */ - -/* Peripheral Bridge 0 Memory Map ***************************************************/ - -# define KINETIS_AIPS0_BASE 0x40000000 /* Peripheral bridge 0 (AIPS-Lite 0) */ -# define KINETIS_XBAR_BASE 0x40004000 /* Crossbar switch */ -# define KINETIS_DMAC_BASE 0x40008000 /* DMA controller */ -# define KINETIS_DMADESC_BASE 0x40009000 /* DMA controller transfer control descriptors */ -# define KINETIS_FLEXBUSC_BASE 0x4000c000 /* FlexBus controller */ -# define KINETIS_MPU_BASE 0x4000d000 /* MPU */ -# define KINETIS_FMC_BASE 0x4001f000 /* Flash memory controller */ -# define KINETIS_FTFL_BASE 0x40020000 /* Flash memory */ -# define KINETIS_DMAMUX0_BASE 0x40021000 /* DMA channel mutiplexer 0 */ -# define KINETIS_CAN0_BASE 0x40024000 /* FlexCAN 0 */ -# define KINETIS_SPI0_BASE 0x4002c000 /* DSPI 0 */ -# define KINETIS_SPI1_BASE 0x4002d000 /* DSPI 1 */ -# define KINETIS_I2S0_BASE 0x4002f000 /* I2S 0 */ -# define KINETIS_CRC_BASE 0x40032000 /* CRC */ -# define KINETIS_USBDCD_BASE 0x40035000 /* USB DCD */ -# define KINETIS_PDB0_BASE 0x40036000 /* Programmable delay block */ -# define KINETIS_PIT_BASE 0x40037000 /* Periodic interrupt timers (PIT) */ -# define KINETIS_FTM0_BASE 0x40038000 /* FlexTimer (FTM) 0 */ -# define KINETIS_FTM1_BASE 0x40039000 /* FlexTimer (FTM) 1 */ -# define KINETIS_ADC0_BASE 0x4003b000 /* Analog-to-digital converter (ADC) 0 */ -# define KINETIS_RTC_BASE 0x4003d000 /* Real time clock */ -# define KINETIS_VBATR_BASE 0x4003e000 /* VBAT register file */ -# define KINETIS_LPTMR_BASE 0x40040000 /* Low power timer */ -# define KINETIS_SYSR_BASE 0x40041000 /* System register file */ -# define KINETIS_DRYICE_BASE 0x40042000 /* DryIce */ -# define KINETIS_DRYICESS_BASE 0x40043000 /* DryIce secure storage */ -# define KINETIS_TSI0_BASE 0x40045000 /* Touch sense interface */ -# define KINETIS_SIMLP_BASE 0x40047000 /* SIM low-power logic */ -# define KINETIS_SIM_BASE 0x40048000 /* System integration module (SIM) */ -# define KINETIS_PORT_BASE(n) (0x40049000 + ((n) << 12)) -# define KINETIS_PORTA_BASE 0x40049000 /* Port A multiplexing control */ -# define KINETIS_PORTB_BASE 0x4004a000 /* Port B multiplexing control */ -# define KINETIS_PORTC_BASE 0x4004b000 /* Port C multiplexing control */ -# define KINETIS_PORTD_BASE 0x4004c000 /* Port D multiplexing control */ -# define KINETIS_PORTE_BASE 0x4004d000 /* Port E multiplexing control */ -# define KINETIS_WDOG_BASE 0x40052000 /* Software watchdog */ -# define KINETIS_EWM_BASE 0x40061000 /* External watchdog */ -# define KINETIS_CMT_BASE 0x40062000 /* Carrier modulator timer (CMT) */ -# define KINETIS_MCG_BASE 0x40064000 /* Multi-purpose Clock Generator (MCG) */ -# define KINETIS_OSC_BASE 0x40065000 /* System oscillator (XOSC) */ -# define KINETIS_I2C0_BASE 0x40066000 /* I2C 0 */ -# define KINETIS_I2C1_BASE 0x40067000 /* I2C 1 */ -# define KINETIS_UART0_BASE 0x4006a000 /* UART0 */ -# define KINETIS_UART1_BASE 0x4006b000 /* UART1 */ -# define KINETIS_UART2_BASE 0x4006c000 /* UART2 */ -# define KINETIS_UART3_BASE 0x4006d000 /* UART3 */ -# define KINETIS_USB0_BASE 0x40072000 /* USB OTG FS/LS */ -# define KINETIS_CMP_BASE 0x40073000 /* Analog comparator (CMP) / 6-bit digital-to-analog converter (DAC) */ -# define KINETIS_VREF_BASE 0x40074000 /* Voltage reference (VREF) */ -# define KINETIS_LLWU_BASE 0x4007c000 /* Low-leakage wakeup unit (LLWU) */ -# define KINETIS_PMC_BASE 0x4007d000 /* Power management controller (PMC) */ -# define KINETIS_SMC_BASE 0x4007e000 /* System Mode controller (SMC) */ - -/* Peripheral Bridge 1 Memory Map ***************************************************/ - -# define KINETIS_AIPS1_BASE 0x40080000 /* Peripheral bridge 1 (AIPS-Lite 1) */ -# define KINETIS_RNGB_BASE 0x400a0000 /* Random number generator (RNGB) */ -# define KINETIS_CAN1_BASE 0x400a4000 /* FlexCAN 1 */ -# define KINETIS_SPI2_BASE 0x400ac000 /* DSPI 2 */ -# define KINETIS_SDHC_BASE 0x400b1000 /* SDHC */ -# define KINETIS_FTM2_BASE 0x400b8000 /* FlexTimer 2 */ -# define KINETIS_ADC1_BASE 0x400bb000 /* Analog-to-digital converter (ADC) 1 */ -# define KINETIS_EMAC_BASE 0x400c0000 /* Ethernet MAC and IEEE 1588 timers */ -# define KINETIS_DAC0_BASE 0x400cc000 /* 12-bit digital-to-analog converter (DAC) 0 */ -# define KINETIS_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */ -# define KINETIS_UART4_BASE 0x400ea000 /* UART4 */ -# define KINETIS_UART5_BASE 0x400eb000 /* UART5 */ -# define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general - * purpose input/output module that shares the - * crossbar switch slave port with the AIPS-Lite - * is accessed at this address. */ -# define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6)) -# define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */ -# define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */ -# define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */ -# define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */ -# define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */ - -/* Private Peripheral Bus (PPB) Memory Map ******************************************/ - -# define KINETIS_ITM_BASE 0xe0000000 /* Instrumentation Trace Macrocell (ITM) */ -# define KINETIS_DWT_BASE 0xe0001000 /* Data Watchpoint and Trace (DWT) */ -# define KINETIS_FPB_BASE 0xe0002000 /* Flash Patch and Breakpoint (FPB) */ -# define KINETIS_SCS_BASE 0xe000e000 /* System Control Space (SCS) (for NVIC) */ -# define KINETIS_TPIU_BASE 0xe0040000 /* Trace Port Interface Unit (TPIU) */ -# define KINETIS_ETM_BASE 0xe0041000 /* Embedded Trace Macrocell (ETM) */ -# define KINETIS_ETB_BASE 0xe0042000 /* Embedded Trace Buffer (ETB) */ -# define KINETIS_TFUN_BASE 0xe0043000 /* Embedded Trace Funnel */ -# define KINETIS_MCM_BASE 0xe0080000 /* Miscellaneous Control Module (including ETB Almost Full) */ -# define KINETIS_MMCAU_BASE 0xe0081000 /* Memory Mapped Cryptographic Acceleration Unit (MMCAU) */ -# define KINETIS_ROMTAB_BASE 0xe00ff000 /* ROM Table - allows auto-detection of debug components */ - -#else - /* The memory map for other parts is defined in other documents and may or may not - * be the same as above (the family members are all very similar) This error just - * means that you have to look at the document and determine for yourself if the - * memory map is the same. - */ - -# error "No memory map for this Kinetis part" -#endif - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - -/************************************************************************************ - * Public Functions - ************************************************************************************/ - -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_MEMORYMAP_H */ diff --git a/arch/arm/src/kinetis/kinetis_mpuinit.h b/arch/arm/src/kinetis/kinetis_mpuinit.h index f3cf95370efc9addeb53f17871c50b370aa1239f..3327176841b742c3c652ceb7539e3ce3d5bf84fb 100644 --- a/arch/arm/src/kinetis/kinetis_mpuinit.h +++ b/arch/arm/src/kinetis/kinetis_mpuinit.h @@ -42,18 +42,6 @@ #include -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/************************************************************************************ - * Public Types - ************************************************************************************/ - -/************************************************************************************ - * Public Data - ************************************************************************************/ - /************************************************************************************ * Public Functions ************************************************************************************/ diff --git a/arch/arm/src/kinetis/kinetis_pin.c b/arch/arm/src/kinetis/kinetis_pin.c index 851d0c9d9cf885a9eab330d5d06502dc10535183..8a2e3294321a6ce237c2dd19be73404fa4751d50 100644 --- a/arch/arm/src/kinetis/kinetis_pin.c +++ b/arch/arm/src/kinetis/kinetis_pin.c @@ -48,22 +48,9 @@ #include "up_arch.h" #include "up_internal.h" -#include "kinetis_memorymap.h" #include "kinetis.h" -#include "kinetis_port.h" -#include "kinetis_gpio.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ +#include "chip/kinetis_port.h" +#include "chip/kinetis_gpio.h" /**************************************************************************** * Public Functions diff --git a/arch/arm/src/kinetis/kinetis_pindump.c b/arch/arm/src/kinetis/kinetis_pindump.c index 579c01bb4d2c9d1752e29d6002664b4d9e910500..a660c87307c014bcb1ae255116d7124a1f63fa2c 100644 --- a/arch/arm/src/kinetis/kinetis_pindump.c +++ b/arch/arm/src/kinetis/kinetis_pindump.c @@ -46,8 +46,8 @@ #include "up_arch.h" #include "kinetis.h" -#include "kinetis_gpio.h" -#include "kinetis_port.h" +#include "chip/kinetis_gpio.h" +#include "chip/kinetis_port.h" #ifdef CONFIG_DEBUG_GPIO_INFO diff --git a/arch/arm/src/kinetis/kinetis_pingpio.c b/arch/arm/src/kinetis/kinetis_pingpio.c index 3663a92399f8c58e6523394970d5285912889ba0..b8879208164ef1bb05e36ac126e6e3624df41681 100644 --- a/arch/arm/src/kinetis/kinetis_pingpio.c +++ b/arch/arm/src/kinetis/kinetis_pingpio.c @@ -48,21 +48,8 @@ #include "up_arch.h" #include "up_internal.h" -#include "kinetis_memorymap.h" #include "kinetis.h" -#include "kinetis_gpio.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ +#include "chip/kinetis_gpio.h" /**************************************************************************** * Public Functions diff --git a/arch/arm/src/kinetis/kinetis_pinirq.c b/arch/arm/src/kinetis/kinetis_pinirq.c index 0ec0d64176b30e8882154adc9fb6a4261745ab07..919d51e67c9498bdb905e187599557191ad2c82d 100644 --- a/arch/arm/src/kinetis/kinetis_pinirq.c +++ b/arch/arm/src/kinetis/kinetis_pinirq.c @@ -50,7 +50,7 @@ #include "up_internal.h" #include "kinetis.h" -#include "kinetis_port.h" +#include "chip/kinetis_port.h" #ifdef CONFIG_GPIO_IRQ diff --git a/arch/arm/src/kinetis/kinetis_pwm.c b/arch/arm/src/kinetis/kinetis_pwm.c index 0730bf8dd835beb841ae70c14eea92e4f0ced95f..19de382634eea0319f02b553c71921a5985a679f 100644 --- a/arch/arm/src/kinetis/kinetis_pwm.c +++ b/arch/arm/src/kinetis/kinetis_pwm.c @@ -58,10 +58,10 @@ #include "chip.h" #include "kinetis.h" -#include "kinetis_pwm.h" -#include "kinetis_gpio.h" -#include "kinetis_ftm.h" -#include "kinetis_sim.h" +#include "chip/kinetis_pwm.h" +#include "chip/kinetis_gpio.h" +#include "chip/kinetis_ftm.h" +#include "chip/kinetis_sim.h" /* This module then only compiles if there is at least one enabled timer * intended for use with the PWM upper half driver. diff --git a/arch/arm/src/kinetis/kinetis_pwm.h b/arch/arm/src/kinetis/kinetis_pwm.h index 09508d4bfea7a1433bb7865600a1d924c4fa4e63..8e6070279634ecff1ec4494debeed76e4a989e2f 100644 --- a/arch/arm/src/kinetis/kinetis_pwm.h +++ b/arch/arm/src/kinetis/kinetis_pwm.h @@ -73,7 +73,7 @@ defined(CONFIG_KINETIS_FTM2_PWM) #include -#include "kinetis_pinmux.h" +#include "chip/kinetis_pinmux.h" /* For each timer that is enabled for PWM usage, we need the following additional * configuration settings: diff --git a/arch/arm/src/kinetis/kinetis_sdhc.c b/arch/arm/src/kinetis/kinetis_sdhc.c index aff35be9b4d8fc82346d9c92666c3b7ff8fce837..afc85f5989255db19d3fd3d22273eef1f5e792ce 100644 --- a/arch/arm/src/kinetis/kinetis_sdhc.c +++ b/arch/arm/src/kinetis/kinetis_sdhc.c @@ -61,9 +61,9 @@ #include "up_arch.h" #include "kinetis.h" -#include "kinetis_pinmux.h" -#include "kinetis_sim.h" -#include "kinetis_sdhc.h" +#include "chip/kinetis_pinmux.h" +#include "chip/kinetis_sim.h" +#include "chip/kinetis_sdhc.h" #ifdef CONFIG_KINETIS_SDHC diff --git a/arch/arm/src/kinetis/kinetis_serial.c b/arch/arm/src/kinetis/kinetis_serial.c index d47235ba90b8055f2217be0b0b18b3293e3a2b3b..53fd7e2b4ab32418dd048d393a7ca5dd1c1771c7 100644 --- a/arch/arm/src/kinetis/kinetis_serial.c +++ b/arch/arm/src/kinetis/kinetis_serial.c @@ -59,7 +59,7 @@ #include "kinetis_config.h" #include "chip.h" -#include "kinetis_uart.h" +#include "chip/kinetis_uart.h" #include "kinetis.h" /**************************************************************************** diff --git a/arch/arm/src/kinetis/kinetis_start.c b/arch/arm/src/kinetis/kinetis_start.c index 8de2524ef5600670e156c6369017d490dac20016..21885d926823fdaaaf592fff9639b81b11fd6ef3 100644 --- a/arch/arm/src/kinetis/kinetis_start.c +++ b/arch/arm/src/kinetis/kinetis_start.c @@ -51,7 +51,7 @@ #include "up_internal.h" #include "kinetis.h" -#include "kinetis_smc.h" +#include "chip/kinetis_smc.h" #include "kinetis_userspace.h" /**************************************************************************** diff --git a/arch/arm/src/kinetis/kinetis_usbdev.c b/arch/arm/src/kinetis/kinetis_usbdev.c index 8deedb7603c99ecbd06bf8bd25c39ff9ea4abf85..d8d9512cabf2255d4e510f20b4bf03779a1eae91 100644 --- a/arch/arm/src/kinetis/kinetis_usbdev.c +++ b/arch/arm/src/kinetis/kinetis_usbdev.c @@ -67,8 +67,8 @@ #include "up_arch.h" #include "kinetis.h" #include "kinetis_usbotg.h" -#include "kinetis_sim.h" -#include "kinetis_fmc.h" +#include "chip/kinetis_sim.h" +#include "chip/kinetis_fmc.h" #if defined(CONFIG_USBDEV) && defined(CONFIG_KINETIS_USBOTG) diff --git a/arch/arm/src/kinetis/kinetis_usbotg.h b/arch/arm/src/kinetis/kinetis_usbotg.h index de53d512933301f567c5089c9276d7480d544b7d..655c7ccee9c622e1aaa6a4cb4528f52c43b7c054 100644 --- a/arch/arm/src/kinetis/kinetis_usbotg.h +++ b/arch/arm/src/kinetis/kinetis_usbotg.h @@ -42,311 +42,7 @@ #include -#include "chip.h" - -/******************************************************************************************** - * Pre-processor Definitions - ********************************************************************************************/ - -/* Register Offsets *************************************************************************/ - -#define KINETIS_USB_PERID_OFFSET 0x0000 /* Peripheral ID Register */ -#define KINETIS_USB_IDCOMP_OFFSET 0x0004 /* Peripheral ID Complement Register */ -#define KINETIS_USB_REV_OFFSET 0x0008 /* Peripheral Revision Register */ -#define KINETIS_USB_ADDINFO_OFFSET 0x000c /* Peripheral Additional Info Register */ -#define KINETIS_USB_OTGISTAT_OFFSET 0x0010 /* OTG Interrupt Status Register */ -#define KINETIS_USB_OTGICR_OFFSET 0x0014 /* OTG Interrupt Control Register */ -#define KINETIS_USB_OTGSTAT_OFFSET 0x0018 /* OTG Status Register */ -#define KINETIS_USB_OTGCTL_OFFSET 0x001c /* OTG Control Register */ -#define KINETIS_USB_ISTAT_OFFSET 0x0080 /* Interrupt Status Register */ -#define KINETIS_USB_INTEN_OFFSET 0x0084 /* Interrupt Enable Register */ -#define KINETIS_USB_ERRSTAT_OFFSET 0x0088 /* Error Interrupt Status Register */ -#define KINETIS_USB_ERREN_OFFSET 0x008c /* Error Interrupt Enable Register */ -#define KINETIS_USB_STAT_OFFSET 0x0090 /* Status Register */ -#define KINETIS_USB_CTL_OFFSET 0x0094 /* Control Register */ -#define KINETIS_USB_ADDR_OFFSET 0x0098 /* Address Register */ -#define KINETIS_USB_BDTPAGE1_OFFSET 0x009c /* BDT Page Register 1 */ -#define KINETIS_USB_FRMNUML_OFFSET 0x00a0 /* Frame Number Register Low */ -#define KINETIS_USB_FRMNUMH_OFFSET 0x00a4 /* Frame Number Register High */ -#define KINETIS_USB_TOKEN_OFFSET 0x00a8 /* Token Register */ -#define KINETIS_USB_SOFTHLD_OFFSET 0x00ac /* SOF Threshold Register */ -#define KINETIS_USB_BDTPAGE2_OFFSET 0x00b0 /* BDT Page Register 2 */ -#define KINETIS_USB_BDTPAGE3_OFFSET 0x00b4 /* BDT Page Register 3 */ - -#define KINETIS_USB_ENDPT_OFFSET(n) (0x00c0+((n)<<2)) /* Endpoint n Control Register */ -#define KINETIS_USB_ENDPT0_OFFSET 0x00c0 /* Endpoint 0 Control Register */ -#define KINETIS_USB_ENDPT1_OFFSET 0x00c4 /* Endpoint 1 Control Register */ -#define KINETIS_USB_ENDPT2_OFFSET 0x00c8 /* Endpoint 2 Control Register */ -#define KINETIS_USB_ENDPT3_OFFSET 0x00cc /* Endpoint 3 Control Register */ -#define KINETIS_USB_ENDPT4_OFFSET 0x00d0 /* Endpoint 4 Control Register */ -#define KINETIS_USB_ENDPT5_OFFSET 0x00d4 /* Endpoint 5 Control Register */ -#define KINETIS_USB_ENDPT6_OFFSET 0x00d8 /* Endpoint 6 Control Register */ -#define KINETIS_USB_ENDPT7_OFFSET 0x00dc /* Endpoint 7 Control Register */ -#define KINETIS_USB_ENDPT8_OFFSET 0x00e0 /* Endpoint 8 Control Register */ -#define KINETIS_USB_ENDPT9_OFFSET 0x00e4 /* Endpoint 9 Control Register */ -#define KINETIS_USB_ENDPT10_OFFSET 0x00e8 /* Endpoint 10 Control Register */ -#define KINETIS_USB_ENDPT11_OFFSET 0x00ec /* Endpoint 11 Control Register */ -#define KINETIS_USB_ENDPT12_OFFSET 0x00f0 /* Endpoint 12 Control Register */ -#define KINETIS_USB_ENDPT13_OFFSET 0x00f4 /* Endpoint 13 Control Register */ -#define KINETIS_USB_ENDPT14_OFFSET 0x00f8 /* Endpoint 14 Control Register */ -#define KINETIS_USB_ENDPT15_OFFSET 0x00fc /* Endpoint 15 Control Register */ - -#define KINETIS_USB_USBCTRL_OFFSET 0x0100 /* USB Control Register */ -#define KINETIS_USB_OBSERVE_OFFSET 0x0104 /* USB OTG Observe Register */ -#define KINETIS_USB_CONTROL_OFFSET 0x0108 /* USB OTG Control Register */ -#define KINETIS_USB_USBTRC0_OFFSET 0x010c /* USB Transceiver Control Register 0 */ - -/* Register Addresses ***********************************************************************/ - -#define KINETIS_USB0_PERID (KINETIS_USB0_BASE+KINETIS_USB_PERID_OFFSET) -#define KINETIS_USB0_IDCOMP (KINETIS_USB0_BASE+KINETIS_USB_IDCOMP_OFFSET) -#define KINETIS_USB0_REV (KINETIS_USB0_BASE+KINETIS_USB_REV_OFFSET) -#define KINETIS_USB0_ADDINFO (KINETIS_USB0_BASE+KINETIS_USB_ADDINFO_OFFSET) -#define KINETIS_USB0_OTGISTAT (KINETIS_USB0_BASE+KINETIS_USB_OTGISTAT_OFFSET) -#define KINETIS_USB0_OTGICR (KINETIS_USB0_BASE+KINETIS_USB_OTGICR_OFFSET) -#define KINETIS_USB0_OTGSTAT (KINETIS_USB0_BASE+KINETIS_USB_OTGSTAT_OFFSET) -#define KINETIS_USB0_OTGCTL (KINETIS_USB0_BASE+KINETIS_USB_OTGCTL_OFFSET) -#define KINETIS_USB0_ISTAT (KINETIS_USB0_BASE+KINETIS_USB_ISTAT_OFFSET) -#define KINETIS_USB0_INTEN (KINETIS_USB0_BASE+KINETIS_USB_INTEN_OFFSET) -#define KINETIS_USB0_ERRSTAT (KINETIS_USB0_BASE+KINETIS_USB_ERRSTAT_OFFSET) -#define KINETIS_USB0_ERREN (KINETIS_USB0_BASE+KINETIS_USB_ERREN_OFFSET) -#define KINETIS_USB0_STAT (KINETIS_USB0_BASE+KINETIS_USB_STAT_OFFSET) -#define KINETIS_USB0_CTL (KINETIS_USB0_BASE+KINETIS_USB_CTL_OFFSET) -#define KINETIS_USB0_ADDR (KINETIS_USB0_BASE+KINETIS_USB_ADDR_OFFSET) -#define KINETIS_USB0_BDTPAGE1 (KINETIS_USB0_BASE+KINETIS_USB_BDTPAGE1_OFFSET) -#define KINETIS_USB0_FRMNUML (KINETIS_USB0_BASE+KINETIS_USB_FRMNUML_OFFSET) -#define KINETIS_USB0_FRMNUMH (KINETIS_USB0_BASE+KINETIS_USB_FRMNUMH_OFFSET) -#define KINETIS_USB0_TOKEN (KINETIS_USB0_BASE+KINETIS_USB_TOKEN_OFFSET) -#define KINETIS_USB0_SOFTHLD (KINETIS_USB0_BASE+KINETIS_USB_SOFTHLD_OFFSET) -#define KINETIS_USB0_BDTPAGE2 (KINETIS_USB0_BASE+KINETIS_USB_BDTPAGE2_OFFSET) -#define KINETIS_USB0_BDTPAGE3 (KINETIS_USB0_BASE+KINETIS_USB_BDTPAGE3_OFFSET) - -#define KINETIS_USB0_ENDPT(n) (KINETIS_USB0_BASE+KINETIS_USB_ENDPT_OFFSET(n)) -#define KINETIS_USB0_ENDPT0 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT0_OFFSET) -#define KINETIS_USB0_ENDPT1 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT1_OFFSET) -#define KINETIS_USB0_ENDPT2 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT2_OFFSET) -#define KINETIS_USB0_ENDPT3 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT3_OFFSET) -#define KINETIS_USB0_ENDPT4 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT4_OFFSET) -#define KINETIS_USB0_ENDPT5 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT5_OFFSET) -#define KINETIS_USB0_ENDPT6 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT6_OFFSET) -#define KINETIS_USB0_ENDPT7 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT7_OFFSET) -#define KINETIS_USB0_ENDPT8 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT8_OFFSET) -#define KINETIS_USB0_ENDPT9 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT9_OFFSET) -#define KINETIS_USB0_ENDPT10 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT10_OFFSET) -#define KINETIS_USB0_ENDPT11 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT11_OFFSET) -#define KINETIS_USB0_ENDPT12 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT12_OFFSET) -#define KINETIS_USB0_ENDPT13 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT13_OFFSET) -#define KINETIS_USB0_ENDPT14 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT14_OFFSET) -#define KINETIS_USB0_ENDPT15 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT15_OFFSET) - -#define KINETIS_USB0_USBCTRL (KINETIS_USB0_BASE+KINETIS_USB_USBCTRL_OFFSET) -#define KINETIS_USB0_OBSERVE (KINETIS_USB0_BASE+KINETIS_USB_OBSERVE_OFFSET) -#define KINETIS_USB0_CONTROL (KINETIS_USB0_BASE+KINETIS_USB_CONTROL_OFFSET) -#define KINETIS_USB0_USBTRC0 (KINETIS_USB0_BASE+KINETIS_USB_USBTRC0_OFFSET) - -/* Register Bit Definitions *****************************************************************/ - -/* Peripheral ID Register (8-bit) */ - /* Bits 6-7: Reserved */ -#define USB_PERID_MASK (0x3f) /* Bits 0-5: Peripheral identification bits */ - -/* Peripheral ID Complement Register (8-bit) */ -#define USB_IDCOMP_ - /* Bits 6-7: Reserved */ -#define USB_IDCOMP_MASK (0x3f) /* Bits 0-5: Ones complement of peripheral identification bits */ - -/* Peripheral Revision Register (8-bit revision number) */ - -/* Peripheral Additional Info Register (8-bit) */ - -#define USB_ADDINFO_IEHOST (1 << 0) /* Bit 0: This bit is set if host mode is enabled */ - /* Bits 1-2: Reserved */ -#define USB_ADDINFO_IRQNUM_SHIFT (3) /* Bits 3-7: Assigned Interrupt Request Number */ -#define USB_ADDINFO_IRQNUM_MASK (31 << USB_ADDINFO_IRQNUM_SHIFT) - -/* OTG Interrupt Status Register(8-bit) */ - -#define USB_OTGISTAT_AVBUSCHG (1 << 0) /* Bit 0: Change in VBUS is detected on an A device */ - /* Bit 1: Reserved */ -#define USB_OTGISTAT_B_SESS_CHG (1 << 2) /* Bit 2: Change in VBUS is detected on a B device */ -#define USB_OTGISTAT_SESSVLDCHG (1 << 3) /* Bit 3: Change in VBUS is detected */ - /* Bit 4: Reserved */ -#define USB_OTGISTAT_LINE_STATE_CHG (1 << 5) /* Bit 5: Change USB line state */ -#define USB_OTGISTAT_ONEMSEC (1 << 6) /* Bit 6: Set when the 1 millisecond timer expires */ -#define USB_OTGISTAT_IDCHG (1 << 7) /* Bit 7: Change in ID Signal from the USB connector */ - -/* OTG Interrupt Control Register (8-bit) */ - -#define USB_OTGICR_AVBUSEN (1 << 0) /* Bit 0: A VBUS Valid interrupt enable */ - /* Bit 1: Reserved */ -#define USB_OTGICR_BSESSEN (1 << 2) /* Bit 2: B Session END interrupt enable */ -#define USB_OTGICR_SESSVLDEN (1 << 3) /* Bit 3: Session valid interrupt enable */ - /* Bit 4: Reserved */ -#define USB_OTGICR_LINESTATEEN (1 << 5) /* Bit 5: Line State change interrupt enable */ -#define USB_OTGICR_ONEMSECEN (1 << 6) /* Bit 6: 1 millisecond interrupt enable */ -#define USB_OTGICR_IDEN (1 << 7) /* Bit 7: ID interrupt enable */ - -/* OTG Status Register (8-bit) */ - -#define USB_OTGSTAT_AVBUSVLD (1 << 0) /* Bit 0: A VBUS Valid */ - /* Bit 1: Reserved */ -#define USB_OTGSTAT_BSESSEND (1 << 2) /* Bit 2: B Session END */ -#define USB_OTGSTAT_SESS_VLD (1 << 3) /* Bit 3: Session valid */ - /* Bit 4: Reserved */ -#define USB_OTGSTAT_LINESTATESTABLE (1 << 5) /* Bit 5: OTGISTAT LINE_STATE_CHG bit stable */ -#define USB_OTGSTAT_ONEMSECEN (1 << 6) /* Bit 6: Reserved for the 1msec count */ -#define USB_OTGSTAT_ID (1 << 7) /* Bit 7: Current state of the ID pin on the USB connector */ - -/* OTG Control Register (8-bit) */ - /* Bits 0-1: Reserved */ -#define USB_OTGCTL_OTGEN (1 << 2) /* Bit 2: On-The-Go pullup/pulldown resistor enable */ - /* Bit 3: Reserved */ -#define USB_OTGCTL_DMLOW (1 << 4) /* Bit 4: D- Data Line pull-down resistor enable */ -#define USB_OTGCTL_DPLOW (1 << 5) /* Bit 5: D+ Data Line pull-down resistor enable */ - /* Bit 6: Reserved */ -#define USB_OTGCTL_DPHIGH (1 << 7) /* Bit 7: D+ Data Line pullup resistor enable */ - -/* Interrupt Status Register Interrupt Enable Register (8-bit) */ - -#define USB_INT_USBRST (1 << 0) /* Bit 0: USB Module has decoded a valid USB reset */ -#define USB_INT_ERROR (1 << 1) /* Bit 1: Any of the error conditions within the ERRSTAT register */ -#define USB_INT_SOFTOK (1 << 2) /* Bit 2: USB Module received a Start Of Frame (SOF) token */ -#define USB_INT_TOKDNE (1 << 3) /* Bit 3: Current token being processed has completed */ -#define USB_INT_SLEEP (1 << 4) /* Bit 4: Constant idle on the USB bus for 3 milliseconds */ -#define USB_INT_RESUME (1 << 5) /* Bit 5: Signal remote wake-up signaling */ -#define USB_INT_ATTACH (1 << 6) /* Bit 6: Attach Interrupt */ -#define USB_INT_STALL (1 << 7) /* Bit 7: Stall Interrupt */ - -#define USB_INT_ALL 0xFF - -/* Error Interrupt Status Register and Error Interrupt Enable Register (8-bit) */ - -#define USB_ERRSTAT_PIDERR (1 << 0) /* Bit 0: This bit is set when the PID check field fails */ -#define USB_ERRSTAT_CRC5EOF (1 << 1) /* Bit 1: Host data CRC error or End of frame errors */ -#define USB_ERRSTAT_CRC16 (1 << 2) /* Bit 2: Data packet is rejected due to a CRC16 error */ -#define USB_ERRSTAT_DFN8 (1 << 3) /* Bit 3: Data field received was not 8 bits in length */ -#define USB_ERRSTAT_BTOERR (1 << 4) /* Bit 4: Bus turnaround timeout error occurred */ -#define USB_ERRSTAT_DMAERR (1 << 5) /* Bit 5: DMA error */ - /* Bit 6: Reserved */ -#define USB_ERRSTAT_BTSERR (1 << 7) /* Bit 7: Bit stuff error is detected */ - -#define USB_EINT_ALL 0xBF - -/* Status Register (8-bit) */ - - /* Bits 0-1: Reserved */ -#define USB_STAT_ODD (1 << 2) /* Bit 2: Last Buffer Descriptor was in the odd bank of the BDT */ -#define USB_STAT_TX (1 << 3) /* Bit 3: Transmit Indicator */ -#define USB_STAT_ENDP_SHIFT (4) /* Bits 4-7: Endpoint address that received or transmitted the token */ -#define USB_STAT_ENDP_MASK (15 << USB_STAT_ENDP_SHIFT) - -/* Control Register (8-bit) */ - -#define USB_CTL_USBENSOFEN (1 << 0) /* Bit 0: USB Enable */ -#define USB_CTL_ODDRST (1 << 1) /* Bit 1: Resets all the BDT ODD ping/pong bits to 0 */ -#define USB_CTL_RESUME (1 << 2) /* Bit 2: Enables the USB Module to execute resume signaling */ -#define USB_CTL_HOSTMODEEN (1 << 3) /* Bit 3: Enables the USB Module to operate in Host mode */ -#define USB_CTL_RESET (1 << 4) /* Bit 4: Enables the USB Module to generate USB reset signaling */ -#define USB_CTL_TXSUSPENDTOKENBUSY (1 << 5) /* Bit 5: USB Module is busy executing a USB token */ -#define USB_CTL_SE0 (1 << 6) /* Bit 6: Live USB Single Ended Zero signal */ -#define USB_CTL_JSTATE (1 << 7) /* Bit 7: Live USB differential receiver JSTATE signal */ - -/* Address Register (8-bit) */ - -#define USB_ADDR_LSEN (1 << 7) /* Bit 7: Low Speed Enable bit */ -#define USB_ADDR_SHIFT (0) /* Bits 0-6: USB address */ -#define USB_ADDR_MASK (0x7f << USB_ADDR_SHIFT) - -/* BDT Page Register 1 (8-bit) */ - /* Bit 0: Reserved */ -#define USB_BDTPAGE1_SHIFT (1) /* Bits 1-7: Address bits 9-15 of the BDT base address */ -#define USB_BDTPAGE1_MASK (0x7f << USB_BDTPAGE1_SHIFT) - -/* Frame Number Register Low (8-bit, bits 0-7 of the 11 bit frame number) */ -#define USB_FRMNUML_MASK 0xFF -/* Frame Number Register High (8-bit) */ - /* Bits 3-7: Reserved */ -#define USB_FRMNUMH_SHIFT (0) /* Bits 0-2: Bits 8-10 of the 11-bit frame number */ -#define USB_FRMNUMH_MASK (7 << USB_FRMNUMH_SHIFT) - -/* Token Register (8-bit) */ - -#define USB_TOKEN_ENDPT_SHIFT (0) /* Bits 0-3: Endpoint address for the token command */ -#define USB_TOKEN_ENDPT_MASK (15 << USB_TOKEN_ENDPT_SHIFT) -#define USB_TOKEN_PID_SHIFT (4) /* Bits 4-7: Token type executed by the USB Module */ -#define USB_TOKEN_PID_MASK (15 << USB_TOKEN_PID_SHIFT) -# define USB_TOKEN_PID_OUT (1 << USB_TOKEN_PID_SHIFT) /* OUT Token */ -# define USB_TOKEN_PID_IN (9 << USB_TOKEN_PID_SHIFT) /* IN Token */ -# define USB_TOKEN_PID_SETUP (13 << USB_TOKEN_PID_SHIFT) /* SETUP Token */ - -/* SOF Threshold Register (8-bit count value) */ -/* BDT Page Register 2/3 (16 bit address in two 8-bit registers) */ - -/* Endpoint n Control Register (8-bit) */ - -#define USB_ENDPT_EPHSHK (1 << 0) /* Bit 0: Enable handshaking during a transaction to the endpoint */ -#define USB_ENDPT_EPSTALL (1 << 1) /* Bit 1: Endpoint is stalled */ -#define USB_ENDPT_EPTXEN (1 << 2) /* Bit 2: Enable the endpoint for TX transfers */ -#define USB_ENDPT_EPRXEN (1 << 3) /* Bit 3: Enable the endpoint for RX transfers */ -#define USB_ENDPT_EPCTLDIS (1 << 4) /* Bit 4: Disable control (SETUP) transfers */ - /* Bit 5: Reserved */ -#define USB_ENDPT_RETRYDIS (1 << 6) /* Bit 6: Disable host retry NAK'ed transactions (host EP0) */ -#define USB_ENDPT_HOSTWOHUB (1 << 7) /* Bit 7: Allows the host to communicate to a low speed device (host EP0) */ - -/* USB Control Register (8-bit) */ - /* Bits 0-5: Reserved */ -#define USB_USBCTRL_PDE (1 << 6) /* Bit 6: Enables the weak pulldowns on the USB transceiver */ -#define USB_USBCTRL_SUSP (1 << 7) /* Bit 7: Places the USB transceiver into the suspend state */ - -/* USB OTG Observe Register (8-bit) */ - /* Bits 0-3: Reserved */ -#define USB_OBSERVE_DMPD (1 << 4) /* Bit 4: D- Pull Down signal output from the USB OTG module */ - /* Bit 5: Reserved */ -#define USB_OBSERVE_DPPD (1 << 6) /* Bit 6: D+ Pull Down signal output from the USB OTG module */ -#define USB_OBSERVE_DPPU (1 << 7) /* Bit 7: D+ Pull Up signal output from the USB OTG module */ - -/* USB OTG Control Register (8-bit) */ - /* Bits 0-3: Reserved */ -#define USB_CONTROL_DPPULLUPNONOTG (1 << 4) /* Bit 4: Controls of the DP PULLUP in the USB OTG module */ - /* Bits 5-7: Reserved */ -/* USB Transceiver Control Register 0 (8-bit) */ - -#define USB_USBTRC0_USBRESET (1 << 7) /* Bit 7: USB reset */ - /* Bit 6: Reserved */ -#define USB_USBTRC0_USBRESMEN (1 << 5) /* Bit 5: Asynchronous Resume Interrupt Enable */ - /* Bits 2-4: Reserved */ -#define USB_USBTRC0_SYNC_DET (1 << 1) /* Bit 1: Synchronous USB Interrupt Detect */ -#define USB_USBTRC0_RESUME_INT (1 << 0) /* Bit 0: USB Asynchronous Interrupt */ - -/* Buffer Descriptor Table (BDT) ****************************************************/ -/* Offset 0: On write (software->hardware) */ - -#define USB_BDT_STATUS_MASK 0xfc /* Bits 2-7: Status bits */ -#define USB_BDT_BSTALL (1 << 2) /* Bit 2: Buffer Stall Enable bit */ -#define USB_BDT_DTS (1 << 3) /* Bit 3: Data Toggle Synchronization Enable bit */ -#define USB_BDT_NINC (1 << 4) /* Bit 4: DMA Address Increment Disable bit */ -#define USB_BDT_KEEP (1 << 5) /* Bit 5: BD Keep Enable bit */ -#define USB_BDT_DATA01 (1 << 6) /* Bit 6: Data Toggle Packet bit */ -#define USB_BDT_UOWN (1 << 7) /* Bit 7: USB Own bit */ -#define USB_BDT_BYTECOUNT_SHIFT (16) /* Bits 16-25: Byte Count bits */ -#define USB_BDT_BYTECOUNT_MASK (0x3ff << USB_BDT_BYTECOUNT_SHIFT) - -#define USB_BDT_DATA0 0 /* DATA0 packet expected next */ -#define USB_BDT_DATA1 USB_BDT_DATA01 /* DATA1 packet expected next */ -#define USB_BDT_COWN 0 /* CPU owns the descriptor */ - -/* Offset 0: On read (hardware->software) */ - -#define USB_BDT_PID_SHIFT (2) /* Bits 2-5: Packet Identifier bits */ -#define USB_BDT_PID_MASK (15 << USB_BDT_PID_SHIFT) - /* Bit 7: USB Own bit (same) */ - /* Bits 16-25: Byte Count bits (same) */ - -/* Offset 4: BUFFER_ADDRESS, 32-bit Buffer Address bits */ - -#define USB_BDT_BYTES_SIZE 8 /* Eight bytes per BDT */ -#define USB_BDT_WORD_SIZE 2 /* Two 32-bit words per BDT */ -#define USB_NBDTS_PER_EP 4 /* Number of BDTS per endpoint: IN/OUT and EVEN/ODD */ +#include "chip/kinetis_usbotg.h" /************************************************************************************ * Public Types diff --git a/arch/arm/src/kinetis/kinetis_vectors.S b/arch/arm/src/kinetis/kinetis_vectors.S index 75c295ae033342bc25f0f64c80aa99beee7e3372..39f07fc000f041f11ddcaaf0293f876aa2b12faa 100644 --- a/arch/arm/src/kinetis/kinetis_vectors.S +++ b/arch/arm/src/kinetis/kinetis_vectors.S @@ -42,6 +42,7 @@ #include +#include "chip.h" #include "exc_return.h" /************************************************************************************************ @@ -160,7 +161,7 @@ _vectors: * K20P64M72SF1RM */ -#if defined(CONFIG_ARCH_CHIP_MK20DX256VLH7) +#if defined(KINETIS_K20) .word kinetis_dmach0 /* Vector 16: DMA channel 0 transfer complete */ .word kinetis_dmach1 /* Vector 17: DMA channel 1 transfer complete */ .word kinetis_dmach2 /* Vector 18: DMA channel 2 transfer complete */ @@ -263,9 +264,7 @@ _vectors: * K40P144M100SF2RM */ -#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) || \ - defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100) || \ - defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100) +#elif defined(KINETIS_K40) .word kinetis_dmach0 /* Vector 16: DMA channel 0 transfer complete */ .word kinetis_dmach1 /* Vector 17: DMA channel 1 transfer complete */ @@ -369,10 +368,7 @@ _vectors: * K60P144M100SF2RM */ -#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100) || defined(CONFIG_ARCH_CHIP_MK60X256VLQ100) || \ - defined(CONFIG_ARCH_CHIP_MK60N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK60N256VMD100) || \ - defined(CONFIG_ARCH_CHIP_MK60X256VMD100) || defined(CONFIG_ARCH_CHIP_MK60N512VMD100) || \ - defined(CONFIG_ARCH_CHIP_MK60N512VLL100) +#elif defined(KINETIS_K60) .word kinetis_dmach0 /* Vector 16: DMA channel 0 transfer complete */ .word kinetis_dmach1 /* Vector 17: DMA channel 1 transfer complete */ @@ -478,6 +474,102 @@ _vectors: .word kinetis_reserved /* Vector 117: Reserved */ .word kinetis_reserved /* Vector 118: Reserved */ .word kinetis_reserved /* Vector 119: Reserved */ + +/* K64 Family *********************************************************************************** + * + * The memory map for the following parts is defined in Freescale document + * MK64FX512VLL12 + */ + +#elif defined(KINETIS_K64) + + .word kinetis_dmach0 /* Vector 16: DMA channel 0 transfer complete */ + .word kinetis_dmach1 /* Vector 17: DMA channel 1 transfer complete */ + .word kinetis_dmach2 /* Vector 18: DMA channel 2 transfer complete */ + .word kinetis_dmach3 /* Vector 19: DMA channel 3 transfer complete */ + .word kinetis_dmach4 /* Vector 20: DMA channel 4 transfer complete */ + .word kinetis_dmach5 /* Vector 21: DMA channel 5 transfer complete */ + .word kinetis_dmach6 /* Vector 22: DMA channel 6 transfer complete */ + .word kinetis_dmach7 /* Vector 23: DMA channel 7 transfer complete */ + .word kinetis_dmach8 /* Vector 24: DMA channel 8 transfer complete */ + .word kinetis_dmach9 /* Vector 25: DMA channel 9 transfer complete */ + .word kinetis_dmach10 /* Vector 26: DMA channel 10 transfer complete */ + .word kinetis_dmach11 /* Vector 27: DMA channel 11 transfer complete */ + .word kinetis_dmach12 /* Vector 28: DMA channel 12 transfer complete */ + .word kinetis_dmach13 /* Vector 29: DMA channel 13 transfer complete */ + .word kinetis_dmach14 /* Vector 30: DMA channel 14 transfer complete */ + .word kinetis_dmach15 /* Vector 31: DMA channel 15 transfer complete */ + .word kinetis_dmaerr /* Vector 32: DMA error interrupt channels 0-15 */ + .word kinetis_mcm /* Vector 33: MCM Normal interrupt */ + .word kinetis_flashcc /* Vector 34: Flash memory command complete */ + .word kinetis_flashrc /* Vector 35: Flash memory read collision */ + .word kinetis_smclvd /* Vector 36: Mode Controller low-voltage detect, low-voltage warning */ + .word kinetis_llwu /* Vector 37: LLWU Normal Low Leakage Wakeup */ + .word kinetis_wdog /* Vector 38: Watchdog */ + .word kinetis_rngb /* Vector 39: Random number generator */ + .word kinetis_i2c0 /* Vector 40: I2C0 */ + .word kinetis_i2c1 /* Vector 41: I2C1 */ + .word kinetis_spi0 /* Vector 42: SPI0 all sources */ + .word kinetis_spi1 /* Vector 43: SPI1 all sources */ + .word kinetis_i2s0 /* Vector 44: Transmit */ + .word kinetis_i2s1 /* Vector 45: Transmit */ + .word kinetis_reserved /* Vector 46: Reserved */ + .word kinetis_uart0s /* Vector 47: UART0 status */ + .word kinetis_uart0e /* Vector 48: UART0 error */ + .word kinetis_uart1s /* Vector 49: UART1 status */ + .word kinetis_uart1e /* Vector 50: UART1 error */ + .word kinetis_uart2s /* Vector 51: UART2 status */ + .word kinetis_uart2e /* Vector 52: UART2 error */ + .word kinetis_uart3s /* Vector 53: UART3 status */ + .word kinetis_uart3e /* Vector 54: UART3 error */ + .word kinetis_adc0 /* Vector 55: ADC0 */ + .word kinetis_cmp0 /* Vector 56: CMP0 */ + .word kinetis_cmp1 /* Vector 57: CMP1 */ + .word kinetis_ftm0 /* Vector 58: FTM0 all sources */ + .word kinetis_ftm1 /* Vector 59: FTM1 all sources */ + .word kinetis_ftm2 /* Vector 60: FTM2 all sources */ + .word kinetis_cmt /* Vector 61: CMT */ + .word kinetis_rtc0 /* Vector 62: RTC alarm interrupt */ + .word kinetis_rtc1 /* Vector 63: RTC seconds interrupt */ + .word kinetis_pitch0 /* Vector 64: PIT channel 0 */ + .word kinetis_pitch1 /* Vector 65: PIT channel 1 */ + .word kinetis_pitch2 /* Vector 66: PIT channel 2 */ + .word kinetis_pitch3 /* Vector 67: PIT channel 3 */ + .word kinetis_pdb /* Vector 68: PDB */ + .word kinetis_usbotg /* Vector 68: USB OTG */ + .word kinetis_usbcd /* Vector 70: USB charger detect */ + .word kinetis_reserved /* Vector 71: Reserved */ + .word kinetis_dac0 /* Vector 72: DAC0 */ + .word kinetis_mcg /* Vector 73: MCG */ + .word kinetis_lpt /* Vector 74: Low power timer */ + .word kinetis_porta /* Vector 75: Pin detect port A */ + .word kinetis_portb /* Vector 76: Pin detect port B */ + .word kinetis_portc /* Vector 77: Pin detect port C */ + .word kinetis_portd /* Vector 78: Pin detect port D */ + .word kinetis_porte /* Vector 79: Pin detect port E */ + .word kinetis_software /* Vector 80: Software interrupt */ + .word kinetis_spi2 /* Vector 81: SPI2 all sources */ + .word kinetis_uart4s /* Vector 82: UART4 status */ + .word kinetis_uart4e /* Vector 83: UART4 error */ + .word kinetis_uart5s /* Vector 84: UART5 status */ + .word kinetis_uart5e /* Vector 85: UART5 error */ + .word kinetis_cmp2 /* Vector 86: CMP2 */ + .word kinetis_ftm3 /* Vector 87: FTM3 all sources */ + .word kinetis_dac1 /* Vector 88: DAC1 */ + .word kinetis_adc1 /* Vector 89: ADC1 */ + .word kinetis_i2c2 /* Vector 90: I2C2 */ + .word kinetis_can0mb /* Vector 91: CAN0 ORed Message buffer (0-15) */ + .word kinetis_can0bo /* Vector 92: CAN0 Bus Off */ + .word kinetis_can0err /* Vector 93: CAN0 Error */ + .word kinetis_can0tw /* Vector 94: CAN0 Transmit Warning */ + .word kinetis_can0rw /* Vector 95: CAN0 Receive Warning */ + .word kinetis_can0wu /* Vector 96: CAN0 Wake UP */ + .word kinetis_sdhc /* Vector 97: SDHC */ + .word kinetis_emactmr /* Vector 91: Ethernet MAC IEEE 1588 timer interrupt */ + .word kinetis_emactx /* Vector 92: Ethernet MAC transmit interrupt */ + .word kinetis_emacrx /* Vector 93: Ethernet MAC receive interrupt */ + .word kinetis_emacmisc /* Vector 94: Ethernet MAC error and misc interrupt */ + #else # error "No vectors for this Kinetis part" #endif @@ -505,13 +597,13 @@ handlers: HANDLER kinetis_systick, KINETIS_IRQ_SYSTICK /* Vector 15: System tick */ /* External Interrupts **************************************************************************/ -/* K40 Family *********************************************************************************** +/* K20 Family *********************************************************************************** * * The interrupt vectors for the following parts is defined in Freescale document * K20P64M72SF1RM */ -#if defined(CONFIG_ARCH_CHIP_MK20DX256VLH7) +#if defined(KINETIS_K20) HANDLER kinetis_dmach0, KINETIS_IRQ_DMACH0 /* Vector 16: DMA channel 0 transfer complete */ HANDLER kinetis_dmach1, KINETIS_IRQ_DMACH1 /* Vector 17: DMA channel 1 transfer complete */ @@ -585,9 +677,7 @@ handlers: * K40P144M100SF2RM */ -#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) || \ - defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100) || \ - defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100) +#elif defined(KINETIS_K40) HANDLER kinetis_dmach0, KINETIS_IRQ_DMACH0 /* Vector 16: DMA channel 0 transfer complete */ HANDLER kinetis_dmach1, KINETIS_IRQ_DMACH1 /* Vector 17: DMA channel 1 transfer complete */ @@ -679,10 +769,7 @@ handlers: * K60P144M100SF2RM */ -#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100) || defined(CONFIG_ARCH_CHIP_MK60X256VLQ100) || \ - defined(CONFIG_ARCH_CHIP_MK60N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK60N256VMD100) || \ - defined(CONFIG_ARCH_CHIP_MK60X256VMD100) || defined(CONFIG_ARCH_CHIP_MK60N512VMD100) || \ - defined(CONFIG_ARCH_CHIP_MK60N512VLL100) +#elif defined(KINETIS_K60) HANDLER kinetis_dmach0, KINETIS_IRQ_DMACH0 /* Vector 16: DMA channel 0 transfer complete */ HANDLER kinetis_dmach1, KINETIS_IRQ_DMACH1 /* Vector 17: DMA channel 1 transfer complete */ @@ -771,6 +858,99 @@ handlers: HANDLER kinetis_portd, KINETIS_IRQ_PORTD /* Vector 106: Pin detect port D */ HANDLER kinetis_porte, KINETIS_IRQ_PORTE /* Vector 107: Pin detect port E */ +/* K64 Family *********************************************************************************** + * + * The memory map for the following parts is defined in Freescale document + * MK64FX512VLL12 + */ + +#elif defined(KINETIS_K64) + + HANDLER kinetis_dmach0, KINETIS_IRQ_DMACH0 /* Vector 16: DMA channel 0 transfer complete */ + HANDLER kinetis_dmach1, KINETIS_IRQ_DMACH1 /* Vector 17: DMA channel 1 transfer complete */ + HANDLER kinetis_dmach2, KINETIS_IRQ_DMACH2 /* Vector 18: DMA channel 2 transfer complete */ + HANDLER kinetis_dmach3, KINETIS_IRQ_DMACH3 /* Vector 19: DMA channel 3 transfer complete */ + HANDLER kinetis_dmach4, KINETIS_IRQ_DMACH4 /* Vector 20: DMA channel 4 transfer complete */ + HANDLER kinetis_dmach5, KINETIS_IRQ_DMACH5 /* Vector 21: DMA channel 5 transfer complete */ + HANDLER kinetis_dmach6, KINETIS_IRQ_DMACH6 /* Vector 22: DMA channel 6 transfer complete */ + HANDLER kinetis_dmach7, KINETIS_IRQ_DMACH7 /* Vector 23: DMA channel 7 transfer complete */ + HANDLER kinetis_dmach8, KINETIS_IRQ_DMACH8 /* Vector 24: DMA channel 8 transfer complete */ + HANDLER kinetis_dmach9, KINETIS_IRQ_DMACH9 /* Vector 25: DMA channel 9 transfer complete */ + HANDLER kinetis_dmach10, KINETIS_IRQ_DMACH10 /* Vector 26: DMA channel 10 transfer complete */ + HANDLER kinetis_dmach11, KINETIS_IRQ_DMACH11 /* Vector 27: DMA channel 11 transfer complete */ + HANDLER kinetis_dmach12, KINETIS_IRQ_DMACH12 /* Vector 28: DMA channel 12 transfer complete */ + HANDLER kinetis_dmach13, KINETIS_IRQ_DMACH13 /* Vector 29: DMA channel 13 transfer complete */ + HANDLER kinetis_dmach14, KINETIS_IRQ_DMACH14 /* Vector 30: DMA channel 14 transfer complete */ + HANDLER kinetis_dmach15, KINETIS_IRQ_DMACH15 /* Vector 31: DMA channel 15 transfer complete */ + HANDLER kinetis_dmaerr, KINETIS_IRQ_DMAERR /* Vector 32: DMA error interrupt channels 0-15 */ + HANDLER kinetis_mcm, KINETIS_IRQ_MCM /* Vector 33: MCM Normal interrupt */ + HANDLER kinetis_flashcc, KINETIS_IRQ_FLASHCC /* Vector 34: Flash memory command complete */ + HANDLER kinetis_flashrc, KINETIS_IRQ_FLASHRC /* Vector 35: Flash memory read collision */ + HANDLER kinetis_smclvd, KINETIS_IRQ_SMCLVD /* Vector 36: Mode Controller low-voltage detect, low-voltage warning */ + HANDLER kinetis_llwu, KINETIS_IRQ_LLWU /* Vector 37: LLWU Normal Low Leakage Wakeup */ + HANDLER kinetis_wdog, KINETIS_IRQ_WDOG /* Vector 38: Watchdog */ + HANDLER kinetis_rngb, KINETIS_IRQ_RNGB /* Vector 39: Random number generator */ + HANDLER kinetis_i2c0, KINETIS_IRQ_I2C0 /* Vector 40: I2C0 */ + HANDLER kinetis_i2c1, KINETIS_IRQ_I2C1 /* Vector 41: I2C1 */ + HANDLER kinetis_spi0, KINETIS_IRQ_SPI0 /* Vector 42: SPI0 all sources */ + HANDLER kinetis_spi1, KINETIS_IRQ_SPI1 /* Vector 43: SPI1 all sources */ + HANDLER kinetis_i2s0, KINETIS_IRQ_I2S0 /* Vector 44: Transmit */ + HANDLER kinetis_i2s1, KINETIS_IRQ_I2S1 /* Vector 45: Transmit */ + HANDLER kinetis_uart0s, KINETIS_IRQ_UART0S /* Vector 47: UART0 status */ + HANDLER kinetis_uart0e, KINETIS_IRQ_UART0E /* Vector 48: UART0 error */ + HANDLER kinetis_uart1s, KINETIS_IRQ_UART1S /* Vector 49: UART1 status */ + HANDLER kinetis_uart1e, KINETIS_IRQ_UART1E /* Vector 50: UART1 error */ + HANDLER kinetis_uart2s, KINETIS_IRQ_UART2S /* Vector 51: UART2 status */ + HANDLER kinetis_uart2e, KINETIS_IRQ_UART2E /* Vector 52: UART2 error */ + HANDLER kinetis_uart3s, KINETIS_IRQ_UART3S /* Vector 53: UART3 status */ + HANDLER kinetis_uart3e, KINETIS_IRQ_UART3E /* Vector 54: UART3 error */ + HANDLER kinetis_adc0, KINETIS_IRQ_ADC0 /* Vector 55: ADC0 */ + HANDLER kinetis_cmp0, KINETIS_IRQ_CMP0 /* Vector 56: CMP0 */ + HANDLER kinetis_cmp1, KINETIS_IRQ_CMP1 /* Vector 57: CMP1 */ + HANDLER kinetis_ftm0, KINETIS_IRQ_FTM0 /* Vector 58: FTM0 all sources */ + HANDLER kinetis_ftm1, KINETIS_IRQ_FTM1 /* Vector 59: FTM1 all sources */ + HANDLER kinetis_ftm2, KINETIS_IRQ_FTM2 /* Vector 60: FTM2 all sources */ + HANDLER kinetis_cmt, KINETIS_IRQ_CMT /* Vector 61: CMT */ + HANDLER kinetis_rtc0, KINETIS_IRQ_RTC0 /* Vector 62: RTC alarm interrupt */ + HANDLER kinetis_rtc1, KINETIS_IRQ_RTC1 /* Vector 63: RTC seconds interrupt */ + HANDLER kinetis_pitch0, KINETIS_IRQ_PITCH0 /* Vector 64: PIT channel 0 */ + HANDLER kinetis_pitch1, KINETIS_IRQ_PITCH1 /* Vector 65: PIT channel 1 */ + HANDLER kinetis_pitch2, KINETIS_IRQ_PITCH2 /* Vector 66: PIT channel 2 */ + HANDLER kinetis_pitch3, KINETIS_IRQ_PITCH3 /* Vector 67: PIT channel 3 */ + HANDLER kinetis_pdb, KINETIS_IRQ_PDB /* Vector 68: PDB */ + HANDLER kinetis_usbotg, KINETIS_IRQ_USBOTG /* Vector 68: USB OTG */ + HANDLER kinetis_usbcd, KINETIS_IRQ_USBCD /* Vector 70: USB charger detect */ + HANDLER kinetis_dac0, KINETIS_IRQ_DAC0 /* Vector 72: DAC0 */ + HANDLER kinetis_mcg, KINETIS_IRQ_MCG /* Vector 73: MCG */ + HANDLER kinetis_lpt, KINETIS_IRQ_LPT /* Vector 74: Low power timer */ + HANDLER kinetis_porta, KINETIS_IRQ_PORTA /* Vector 75: Pin detect port A */ + HANDLER kinetis_portb, KINETIS_IRQ_PORTB /* Vector 76: Pin detect port B */ + HANDLER kinetis_portc, KINETIS_IRQ_PORTC /* Vector 77: Pin detect port C */ + HANDLER kinetis_portd, KINETIS_IRQ_PORTD /* Vector 78: Pin detect port D */ + HANDLER kinetis_porte, KINETIS_IRQ_PORTE /* Vector 79: Pin detect port E */ + HANDLER kinetis_software, KINETIS_IRQ_SOFTWARE /* Vector 80: Software interrupt */ + HANDLER kinetis_spi2, KINETIS_IRQ_SPI2 /* Vector 81: SPI2 all sources */ + HANDLER kinetis_uart4s, KINETIS_IRQ_UART4S /* Vector 82: UART4 status */ + HANDLER kinetis_uart4e, KINETIS_IRQ_UART4E /* Vector 83: UART4 error */ + HANDLER kinetis_uart5s, KINETIS_IRQ_UART5S /* Vector 84: UART5 status */ + HANDLER kinetis_uart5e, KINETIS_IRQ_UART5E /* Vector 85: UART5 error */ + HANDLER kinetis_cmp2, KINETIS_IRQ_CMP2 /* Vector 86: CMP2 */ + HANDLER kinetis_ftm3, KINETIS_IRQ_FTM3 /* Vector 87: FTM3 all sources */ + HANDLER kinetis_dac1, KINETIS_IRQ_DAC1 /* Vector 88: DAC1 */ + HANDLER kinetis_adc1, KINETIS_IRQ_ADC1 /* Vector 89: ADC1 */ + HANDLER kinetis_i2c2, KINETIS_IRQ_I2C2 /* Vector 90: I2C2 */ + HANDLER kinetis_can0mb, KINETIS_IRQ_CAN0MB /* Vector 91: CAN0 ORed Message buffer (0-15) */ + HANDLER kinetis_can0bo, KINETIS_IRQ_CAN0BO /* Vector 92: CAN0 Bus Off */ + HANDLER kinetis_can0err, KINETIS_IRQ_CAN0ERR /* Vector 93: CAN0 Error */ + HANDLER kinetis_can0tw, KINETIS_IRQ_CAN0TW /* Vector 94: CAN0 Transmit Warning */ + HANDLER kinetis_can0rw, KINETIS_IRQ_CAN0RW /* Vector 95: CAN0 Receive Warning */ + HANDLER kinetis_can0wu, KINETIS_IRQ_CAN0WU /* Vector 96: CAN0 Wake UP */ + HANDLER kinetis_sdhc, KINETIS_IRQ_SDHC /* Vector 97: SDHC */ + HANDLER kinetis_emactmr, KINETIS_IRQ_EMACTMR /* Vector 91: Ethernet MAC IEEE 1588 timer interrupt */ + HANDLER kinetis_emactx, KINETIS_IRQ_EMACTX /* Vector 92: Ethernet MAC transmit interrupt */ + HANDLER kinetis_emacrx, KINETIS_IRQ_EMACRX /* Vector 93: Ethernet MAC receive interrupt */ + HANDLER kinetis_emacmisc, KINETIS_IRQ_EMACMISC /* Vector 94: Ethernet MAC error and misc interrupt */ + #else # error "No handlers for this Kinetis part" #endif diff --git a/arch/arm/src/kinetis/kinetis_wdog.c b/arch/arm/src/kinetis/kinetis_wdog.c index 9dc29b80d8963576c400758580b4fa4edecb5945..3beaad8d4bce5d1e0db6153578fe1d9290903f67 100644 --- a/arch/arm/src/kinetis/kinetis_wdog.c +++ b/arch/arm/src/kinetis/kinetis_wdog.c @@ -1,6 +1,5 @@ /**************************************************************************** * arch/arm/src/kinetis/kinetis_wdog.c - * arch/arm/src/chip/kinetis_wdog.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -44,19 +43,7 @@ #include "up_arch.h" #include "kinetis.h" -#include "kinetis_wdog.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ +#include "chip/kinetis_wdog.h" /**************************************************************************** * Private Functions diff --git a/arch/arm/src/lpc43xx/lpc43_irq.c b/arch/arm/src/lpc43xx/lpc43_irq.c index 345f63b5c24eb8f639da0c47e9dfe3ed04f1a5d4..26881472c8d15ec3395fdc454f9a391d2bca1b2c 100644 --- a/arch/arm/src/lpc43xx/lpc43_irq.c +++ b/arch/arm/src/lpc43xx/lpc43_irq.c @@ -242,53 +242,23 @@ static inline void lpc43_prioritize_syscall(int priority) static int lpc43_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, uintptr_t offset) { + int n; + DEBUGASSERT(irq >= LPC43_IRQ_NMI && irq < NR_IRQS); /* Check for external interrupt */ if (irq >= LPC43_IRQ_EXTINT) { - /* NOTE: We assume that there are at least 32 interrupts */ - - if (irq < (LPC43_IRQ_EXTINT + 32)) - { - /* Interrupt in range {0-31} */ - - *regaddr = (NVIC_IRQ0_31_ENABLE + offset); - *bit = 1 << (irq - LPC43_IRQ_EXTINT); - } -#if LPC43M4_IRQ_NEXTINT > 95 -# error Extension to interrupt logic needed -#elif LPC43M4_IRQ_NEXTINT > 63 - else if (irq < (LPC43_IRQ_EXTINT + 64)) - { - /* Interrupt in range {32-63} */ + n = irq - LPC43_IRQ_EXTINT; + *regaddr = NVIC_IRQ_ENABLE(n) + offset; - *regaddr = (NVIC_IRQ32_63_ENABLE + offset); - *bit = 1 << (irq - LPC43_IRQ_EXTINT - 32); - } - else if (irq < LPC43M4_IRQ_NIRQS) + while (n >= 32) { - /* Interrupt in range {64-LPC43M4_IRQ_NIRQS}, LPC43M4_IRQ_NIRQS <= 95 */ - - *regaddr = (NVIC_IRQ64_95_ENABLE + offset); - *bit = 1 << (irq - LPC43_IRQ_EXTINT - 64); + n -= 32; } -#else /* if LPC43M4_IRQ_NEXTINT > 31 */ - else if (irq < LPC43M4_IRQ_NIRQS) - { - /* Interrupt in range {32-LPC43M4_IRQ_NIRQS}, LPC43M4_IRQ_NIRQS <= 63 */ - *regaddr = (NVIC_IRQ32_63_ENABLE + offset); - *bit = 1 << (irq - LPC43_IRQ_EXTINT - 32); - } -#endif - else - { - /* Interrupt >= LPC43M4_IRQ_NIRQS */ - - return ERROR; /* Invalid interrupt */ - } + *bit = 1 << n; } /* Handle processor exceptions. Only a few can be disabled */ @@ -342,16 +312,14 @@ void up_irqinitialize(void) uint32_t regval; #endif int num_priority_registers; + int i; /* Disable all interrupts */ - putreg32(0, NVIC_IRQ0_31_ENABLE); -#if LPC43M4_IRQ_NEXTINT > 31 - putreg32(0, NVIC_IRQ32_63_ENABLE); -#if LPC43M4_IRQ_NEXTINT > 63 - putreg32(0, NVIC_IRQ64_95_ENABLE); -#endif -#endif + for (i = 0; i < LPC43M4_IRQ_NEXTINT; i += 32) + { + putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); + } /* Make sure that we are using the correct vector table. The default * vector address is 0x0000:0000 but if we are executing code that is diff --git a/arch/arm/src/samv7/chip/sam_mcan.h b/arch/arm/src/samv7/chip/sam_mcan.h index b3951aef703890ae6597eb7e2ac15516e15c774d..4212ca3c291d7877a2003488c401bbcd9e514130 100644 --- a/arch/arm/src/samv7/chip/sam_mcan.h +++ b/arch/arm/src/samv7/chip/sam_mcan.h @@ -747,7 +747,7 @@ #define STDFILTER_S0_SFID1_SHIFT (16) /* Bits 16-26: Standard Filter ID 2 */ #define STDFILTER_S0_SFID1_MASK (0x3ff << STDFILTER_S0_SFID1_SHIFT) # define STDFILTER_S0_SFID1(n) ((uint32_t)(n) << STDFILTER_S0_SFID1_SHIFT) -#define STDFILTER_S0_SFEC_SHIFT (17) /* Bits 27-29: Standard Filter Element Configuration */ +#define STDFILTER_S0_SFEC_SHIFT (27) /* Bits 27-29: Standard Filter Element Configuration */ #define STDFILTER_S0_SFEC_MASK (7 << STDFILTER_S0_SFEC_SHIFT) # define STDFILTER_S0_SFEC_DISABLE (0 << STDFILTER_S0_SFEC_SHIFT) /* Disable filter element */ # define STDFILTER_S0_SFEC_FIFO0 (1 << STDFILTER_S0_SFEC_SHIFT) /* Store in Rx FIFO 0 on match */ diff --git a/arch/arm/src/samv7/sam_mcan.c b/arch/arm/src/samv7/sam_mcan.c index 2091390cab257f0bdd125995525bd9da35316e72..748b01b10b3545e22edea228cd2c1cf12bcb0393 100644 --- a/arch/arm/src/samv7/sam_mcan.c +++ b/arch/arm/src/samv7/sam_mcan.c @@ -802,6 +802,7 @@ /**************************************************************************** * Private Types ****************************************************************************/ + /* CAN mode of operation */ enum sam_canmode_e @@ -1833,6 +1834,22 @@ static int mcan_add_extfilter(FAR struct sam_mcan_s *priv, if (priv->nextalloc == 1) { + /* Enable the Initialization state */ + + regval = mcan_getreg(priv, SAM_MCAN_CCCR_OFFSET); + regval |= MCAN_CCCR_INIT; + mcan_putreg(priv, SAM_MCAN_CCCR_OFFSET, regval); + + /* Wait for initialization mode to take effect */ + + while ((mcan_getreg(priv, SAM_MCAN_CCCR_OFFSET) & MCAN_CCCR_INIT) == 0); + + /* Enable writing to configuration registers */ + + regval = mcan_getreg(priv, SAM_MCAN_CCCR_OFFSET); + regval |= (MCAN_CCCR_INIT | MCAN_CCCR_CCE); + mcan_putreg(priv, SAM_MCAN_CCCR_OFFSET, regval); + /* Update the Global Filter Configuration so that received * messages are rejected if they do not match the acceptance * filter. @@ -1844,6 +1861,12 @@ static int mcan_add_extfilter(FAR struct sam_mcan_s *priv, regval &= ~MCAN_GFC_ANFE_MASK; regval |= MCAN_GFC_ANFE_REJECTED; mcan_putreg(priv, SAM_MCAN_GFC_OFFSET, regval); + + /* Disable writing to configuration registers */ + + regval = mcan_getreg(priv, SAM_MCAN_CCCR_OFFSET); + regval &= ~(MCAN_CCCR_INIT | MCAN_CCCR_CCE); + mcan_putreg(priv, SAM_MCAN_CCCR_OFFSET, regval); } mcan_dev_unlock(priv); @@ -1903,6 +1926,22 @@ static int mcan_del_extfilter(FAR struct sam_mcan_s *priv, int ndx) if (priv->nextalloc == 0) { + /* Enable the Initialization state */ + + regval = mcan_getreg(priv, SAM_MCAN_CCCR_OFFSET); + regval |= MCAN_CCCR_INIT; + mcan_putreg(priv, SAM_MCAN_CCCR_OFFSET, regval); + + /* Wait for initialization mode to take effect */ + + while ((mcan_getreg(priv, SAM_MCAN_CCCR_OFFSET) & MCAN_CCCR_INIT) == 0); + + /* Enable writing to configuration registers */ + + regval = mcan_getreg(priv, SAM_MCAN_CCCR_OFFSET); + regval |= (MCAN_CCCR_INIT | MCAN_CCCR_CCE); + mcan_putreg(priv, SAM_MCAN_CCCR_OFFSET, regval); + /* If there are no extended filters, then modify Global Filter * Configuration so that all rejected messages are places in RX * FIFO0. @@ -1914,6 +1953,12 @@ static int mcan_del_extfilter(FAR struct sam_mcan_s *priv, int ndx) regval &= ~MCAN_GFC_ANFE_MASK; regval |= MCAN_GFC_ANFE_RX_FIFO0; mcan_putreg(priv, SAM_MCAN_GFC_OFFSET, regval); + + /* Disable writing to configuration registers */ + + regval = mcan_getreg(priv, SAM_MCAN_CCCR_OFFSET); + regval &= ~(MCAN_CCCR_INIT | MCAN_CCCR_CCE); + mcan_putreg(priv, SAM_MCAN_CCCR_OFFSET, regval); } /* Deactivate the filter last so that no messages are lost. */ @@ -2021,6 +2066,22 @@ static int mcan_add_stdfilter(FAR struct sam_mcan_s *priv, if (priv->nstdalloc == 1) { + /* Enable the Initialization state */ + + regval = mcan_getreg(priv, SAM_MCAN_CCCR_OFFSET); + regval |= MCAN_CCCR_INIT; + mcan_putreg(priv, SAM_MCAN_CCCR_OFFSET, regval); + + /* Wait for initialization mode to take effect */ + + while ((mcan_getreg(priv, SAM_MCAN_CCCR_OFFSET) & MCAN_CCCR_INIT) == 0); + + /* Enable writing to configuration registers */ + + regval = mcan_getreg(priv, SAM_MCAN_CCCR_OFFSET); + regval |= (MCAN_CCCR_INIT | MCAN_CCCR_CCE); + mcan_putreg(priv, SAM_MCAN_CCCR_OFFSET, regval); + /* Update the Global Filter Configuration so that received * messages are rejected if they do not match the acceptance * filter. @@ -2032,6 +2093,12 @@ static int mcan_add_stdfilter(FAR struct sam_mcan_s *priv, regval &= ~MCAN_GFC_ANFS_MASK; regval |= MCAN_GFC_ANFS_REJECTED; mcan_putreg(priv, SAM_MCAN_GFC_OFFSET, regval); + + /* Disable writing to configuration registers */ + + regval = mcan_getreg(priv, SAM_MCAN_CCCR_OFFSET); + regval &= ~(MCAN_CCCR_INIT | MCAN_CCCR_CCE); + mcan_putreg(priv, SAM_MCAN_CCCR_OFFSET, regval); } mcan_dev_unlock(priv); @@ -2089,6 +2156,22 @@ static int mcan_del_stdfilter(FAR struct sam_mcan_s *priv, int ndx) if (priv->nstdalloc == 0) { + /* Enable the Initialization state */ + + regval = mcan_getreg(priv, SAM_MCAN_CCCR_OFFSET); + regval |= MCAN_CCCR_INIT; + mcan_putreg(priv, SAM_MCAN_CCCR_OFFSET, regval); + + /* Wait for initialization mode to take effect */ + + while ((mcan_getreg(priv, SAM_MCAN_CCCR_OFFSET) & MCAN_CCCR_INIT) == 0); + + /* Enable writing to configuration registers */ + + regval = mcan_getreg(priv, SAM_MCAN_CCCR_OFFSET); + regval |= (MCAN_CCCR_INIT | MCAN_CCCR_CCE); + mcan_putreg(priv, SAM_MCAN_CCCR_OFFSET, regval); + /* If there are no standard filters, then modify Global Filter * Configuration so that all rejected messages are places in RX * FIFO0. @@ -2100,6 +2183,12 @@ static int mcan_del_stdfilter(FAR struct sam_mcan_s *priv, int ndx) regval &= ~MCAN_GFC_ANFS_MASK; regval |= MCAN_GFC_ANFS_RX_FIFO0; mcan_putreg(priv, SAM_MCAN_GFC_OFFSET, regval); + + /* Disable writing to configuration registers */ + + regval = mcan_getreg(priv, SAM_MCAN_CCCR_OFFSET); + regval &= ~(MCAN_CCCR_INIT | MCAN_CCCR_CCE); + mcan_putreg(priv, SAM_MCAN_CCCR_OFFSET, regval); } /* Deactivate the filter last so that no messages are lost. */ diff --git a/arch/arm/src/samv7/sam_twihs.c b/arch/arm/src/samv7/sam_twihs.c index 032d2eaa4a4b3361e015b45b8387d2d1031efc0d..6800ecbba89dc0d9f5c00c03ed97199152a4233a 100644 --- a/arch/arm/src/samv7/sam_twihs.c +++ b/arch/arm/src/samv7/sam_twihs.c @@ -133,9 +133,9 @@ struct twi_attr_s { uint8_t twi; /* TWIHS device number (for debug output) */ uint8_t pid; /* TWIHS peripheral ID */ - uint16_t irq; /* IRQ number for this TWIHS bus */ uint8_t glitchfltr; /* Pulse width of a glich to be suppressed by the filter */ - uint8_t s_master; /* Single-Master Mode active */ + bool s_master; /* true: Single-Master Mode active */ + uint16_t irq; /* IRQ number for this TWIHS bus */ gpio_pinset_t sclcfg; /* TWIHS CK pin configuration (SCL in I2C-ese) */ gpio_pinset_t sdacfg; /* TWIHS D pin configuration (SDA in I2C-ese) */ uintptr_t base; /* Base address of TWIHS registers */ @@ -237,19 +237,19 @@ static void twi_hw_initialize(struct twi_dev_s *priv, uint32_t frequency); #ifdef CONFIG_SAMV7_TWIHS0 static const struct twi_attr_s g_twi0attr = { - .twi = 0, - .pid = SAM_PID_TWIHS0, - .irq = SAM_IRQ_TWIHS0, + .twi = 0, + .pid = SAM_PID_TWIHS0, + .irq = SAM_IRQ_TWIHS0, .glitchfltr = CONFIG_SAMV7_TWIHS0_GLITCH_FILTER, #ifdef CONFIG_SAMV7_TWIHS0_SINGLE_MASTER - .s_master = 1, + .s_master = true, #else - .s_master = 0, + .s_master = false, #endif - .sclcfg = GPIO_TWIHS0_CK, - .sdacfg = GPIO_TWIHS0_D, - .base = SAM_TWIHS0_BASE, - .handler = twi0_interrupt, + .sclcfg = GPIO_TWIHS0_CK, + .sdacfg = GPIO_TWIHS0_D, + .base = SAM_TWIHS0_BASE, + .handler = twi0_interrupt, }; static struct twi_dev_s g_twi0; @@ -258,19 +258,19 @@ static struct twi_dev_s g_twi0; #ifdef CONFIG_SAMV7_TWIHS1 static const struct twi_attr_s g_twi1attr = { - .twi = 1, - .pid = SAM_PID_TWIHS1, - .irq = SAM_IRQ_TWIHS1, + .twi = 1, + .pid = SAM_PID_TWIHS1, + .irq = SAM_IRQ_TWIHS1, .glitchfltr = CONFIG_SAMV7_TWIHS1_GLITCH_FILTER, #ifdef CONFIG_SAMV7_TWIHS1_SINGLE_MASTER - .s_master = 1, + .s_master = true, #else - .s_master = 0, + .s_master = false, #endif - .sclcfg = GPIO_TWIHS1_CK, - .sdacfg = GPIO_TWIHS1_D, - .base = SAM_TWIHS1_BASE, - .handler = twi1_interrupt, + .sclcfg = GPIO_TWIHS1_CK, + .sdacfg = GPIO_TWIHS1_D, + .base = SAM_TWIHS1_BASE, + .handler = twi1_interrupt, }; static struct twi_dev_s g_twi1; @@ -279,19 +279,19 @@ static struct twi_dev_s g_twi1; #ifdef CONFIG_SAMV7_TWIHS2 static const struct twi_attr_s g_twi2attr = { - .twi = 2, - .pid = SAM_PID_TWIHS2, - .irq = SAM_IRQ_TWIHS2, + .twi = 2, + .pid = SAM_PID_TWIHS2, + .irq = SAM_IRQ_TWIHS2, .glitchfltr = CONFIG_SAMV7_TWIHS2_GLITCH_FILTER, -#ifdef CONFIG_SAMV7_TWIHS0_SINGLE_MASTER - .s_master = 1, +#ifdef CONFIG_SAMV7_TWIHS2_SINGLE_MASTER + .s_master = true, #else - .s_master = 0, + .s_master = false, #endif - .sclcfg = GPIO_TWIHS2_CK, - .sdacfg = GPIO_TWIHS2_D, - .base = SAM_TWIHS2_BASE, - .handler = twi2_interrupt, + .sclcfg = GPIO_TWIHS2_CK, + .sdacfg = GPIO_TWIHS2_D, + .base = SAM_TWIHS2_BASE, + .handler = twi2_interrupt, }; static struct twi_dev_s g_twi2; @@ -299,9 +299,9 @@ static struct twi_dev_s g_twi2; static const struct i2c_ops_s g_twiops = { - .transfer = twi_transfer + .transfer = twi_transfer #ifdef CONFIG_I2C_RESET - , .reset = twi_reset + , .reset = twi_reset #endif }; @@ -515,6 +515,7 @@ static int twi_wait(struct twi_dev_s *priv, unsigned int size) * all further interrupts for the TWIHS have been disabled. */ +#ifdef CONFIG_I2C_RESET /* Check if an Arbitration Lost has occured */ if (priv->result == -EUSERS) @@ -532,6 +533,7 @@ static int twi_wait(struct twi_dev_s *priv, unsigned int size) priv->result = -EIO; } } +#endif return priv->result; } @@ -646,6 +648,7 @@ static int twi_interrupt(struct twi_dev_s *priv) } } +#ifdef CONFIG_I2C_RESET /* If Single-Master Mode is enabled and we lost arbitration (someone else or * an EMC-Pulse did something on the bus) something went very wrong. So we end * the current transfer with an EUSERS. The wait function will then reset @@ -656,9 +659,10 @@ static int twi_interrupt(struct twi_dev_s *priv) { /* Wake up the thread with an Arbitration Lost error indication */ - i2cllerr("ERROR: TWIHS%d Arbitration Lost\n"); + i2cerr("ERROR: TWIHS%d Arbitration Lost\n"); twi_wakeup(priv, -EUSERS); } +#endif /* Check for errors. We must check for errors *before* checking TXRDY or * TXCMP because the error can be signaled in combination with TXRDY or @@ -909,7 +913,9 @@ static int twi_transfer(FAR struct i2c_master_s *dev, struct twi_dev_s *priv = (struct twi_dev_s *)dev; irqstate_t flags; unsigned int size; +#ifdef CONFIG_I2C_RESET uint32_t sr; +#endif int i; int ret; @@ -945,6 +951,7 @@ static int twi_transfer(FAR struct i2c_master_s *dev, twi_setfrequency(priv, msgs->frequency); +#ifdef CONFIG_I2C_RESET /* When we are in Single Master Mode check if the bus is ready (no stuck * DATA or CLK line). * Otherwise initiate a bus reset. @@ -957,9 +964,12 @@ static int twi_transfer(FAR struct i2c_master_s *dev, { ret = twi_reset_internal(&priv->dev); if (ret != OK) - goto errout; + { + goto errout; + } } } +#endif /* Initiate the transfer. The rest will be handled from interrupt * logic. Interrupts must be disabled to prevent re-entrance from the @@ -976,7 +986,9 @@ static int twi_transfer(FAR struct i2c_master_s *dev, ret = twi_wait(priv, size); leave_critical_section(flags); +#ifdef CONFIG_I2C_RESET errout: +#endif if (ret < 0) { i2cerr("ERROR: Transfer failed: %d\n", ret); diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index 4a838eb07d6a3cef477984d896e5b04f5e905cfc..932e74c81b5f34cfe1f7d721db66faffa8b2daf0 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -2544,6 +2544,54 @@ config STM32_FSMC_SRAM menu "Timer Configuration" +if SCHED_TICKLESS + +config STM32_ONESHOT + bool + default y + +config STM32_FREERUN + bool + default y + +endif # SCHED_TICKLESS + +if !SCHED_TICKLESS + +config STM32_ONESHOT + bool "TIM one-shot wrapper" + default n + ---help--- + Enable a wrapper around the low level timer/counter functions to + support one-shot timer. + +config STM32_FREERUN + bool "TIM free-running wrapper" + default n + ---help--- + Enable a wrapper around the low level timer/counter functions to + support a free-running timer. + +endif # !SCHED_TICKLESS + +config STM32_TICKLESS_ONESHOT + int "Tickless one-shot timer channel" + default 2 + range 1 14 + depends on STM32_ONESHOT + ---help--- + If the Tickless OS feature is enabled, the one clock must be + assigned to provided the one-shot timer needed by the OS. + +config STM32_TICKLESS_FREERUN + int "Tickless free-running timer channel" + default 5 + range 1 14 + depends on STM32_FREERUN + ---help--- + If the Tickless OS feature is enabled, the one clock must be + assigned to provided the free-running timer needed by the OS. + config STM32_TIM1_PWM bool "TIM1 PWM" default n diff --git a/arch/arm/src/stm32/Make.defs b/arch/arm/src/stm32/Make.defs index 1a3355d24d446ddf1b0e7e5c0d3c096207cdc355..aef4ef081552e0ca842838d713704463cea0dd8b 100644 --- a/arch/arm/src/stm32/Make.defs +++ b/arch/arm/src/stm32/Make.defs @@ -120,6 +120,16 @@ endif ifneq ($(CONFIG_SCHED_TICKLESS),y) CHIP_CSRCS += stm32_timerisr.c +else +CHIP_CSRCS += stm32_tickless.c +endif + +ifeq ($(CONFIG_STM32_ONESHOT),y) +CHIP_CSRCS += stm32_oneshot.c +endif + +ifeq ($(CONFIG_STM32_FREERUN),y) +CHIP_CSRCS += stm32_freerun.c endif ifeq ($(CONFIG_ARMV7M_CMNVECTOR),y) diff --git a/arch/arm/src/stm32/chip/stm32_can.h b/arch/arm/src/stm32/chip/stm32_can.h index 6b4a12a855e8d442119699ee32ee9adf9581396d..c1e3500d5e68bc1217b820a5fe88435d31fe0b5a 100644 --- a/arch/arm/src/stm32/chip/stm32_can.h +++ b/arch/arm/src/stm32/chip/stm32_can.h @@ -360,7 +360,7 @@ #define CAN_BTR_SJW_SHIFT (24) /* Bits 25-24: Resynchronization Jump Width */ #define CAN_BTR_SJW_MASK (3 << CAN_BTR_SJW_SHIFT) #define CAN_BTR_LBKM (1 << 30) /* Bit 30: Loop Back Mode (Debug) */ -#define CAN_BTR_SILM (1 << 31) /* Bit 31: Silent Mode (Debug) */ +#define CAN_BTR_SILM (1ul << 31) /* Bit 31: Silent Mode (Debug) */ #define CAN_BTR_BRP_MAX (1024) /* Maximum BTR value (without decrement) */ #define CAN_BTR_TSEG1_MAX (16) /* Maximum TSEG1 value (without decrement) */ diff --git a/arch/arm/src/stm32/stm32_bbsram.c b/arch/arm/src/stm32/stm32_bbsram.c index e35f5e05a7ec83189cc95f5554a1dc7291d558c4..81c49340ae9e6b20dd76babd5fca731867763bbc 100644 --- a/arch/arm/src/stm32/stm32_bbsram.c +++ b/arch/arm/src/stm32/stm32_bbsram.c @@ -593,8 +593,9 @@ static int stm32_bbsram_ioctl(FAR struct file *filep, int cmd, bbrr->fileno = bbr->bbf->fileno; bbrr->lastwrite = bbr->bbf->lastwrite; bbrr->len = bbr->bbf->len; - bbrr->flags = (bbr->bbf->crc == stm32_bbsram_crc(bbr->bbf)) ? eCRCValid : 0; - bbrr->flags = (bbr->bbf->dirty) ? eDirty : 0; + bbrr->flags = ((bbr->bbf->crc == stm32_bbsram_crc(bbr->bbf)) + ? BBSRAM_CRC_VALID : 0); + bbrr->flags |= ((bbr->bbf->dirty) ? BBSRAM_DIRTY : 0); ret = OK; } diff --git a/arch/arm/src/stm32/stm32_bbsram.h b/arch/arm/src/stm32/stm32_bbsram.h index 69d0046f5cfba0136aed5c1030790ba054aa380a..bcb813d6fa1675269ffab47a3614a28d5729d6e0 100644 --- a/arch/arm/src/stm32/stm32_bbsram.h +++ b/arch/arm/src/stm32/stm32_bbsram.h @@ -83,9 +83,8 @@ enum bbsramdf_e { - eCRCValid = 1, /* The crc is valid */ - eDirty = 2, /* The file was closed */ - + BBSRAM_CRC_VALID = 1, /* The crc is valid */ + BBSRAM_DIRTY = 2, /* The file was closed */ }; struct bbsramd_s diff --git a/arch/arm/src/stm32/stm32_can.c b/arch/arm/src/stm32/stm32_can.c index c8193f65f4048b96f54c9e4dd2382d5e305c3519..334c7337d62eb89cd5e43922446af7de9bace7e8 100644 --- a/arch/arm/src/stm32/stm32_can.c +++ b/arch/arm/src/stm32/stm32_can.c @@ -58,16 +58,17 @@ #include "up_internal.h" #include "up_arch.h" - #include "chip.h" #include "stm32.h" #include "stm32_can.h" -#if defined(CONFIG_CAN) && (defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2)) +#if defined(CONFIG_CAN) && \ + (defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2)) /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Delays *******************************************************************/ /* Time out for INAK bit */ @@ -106,19 +107,21 @@ struct stm32_can_s /* CAN Register access */ -static uint32_t stm32can_getreg(FAR struct stm32_can_s *priv, int offset); -static uint32_t stm32can_getfreg(FAR struct stm32_can_s *priv, int offset); +static uint32_t stm32can_getreg(FAR struct stm32_can_s *priv, + int offset); +static uint32_t stm32can_getfreg(FAR struct stm32_can_s *priv, + int offset); static void stm32can_putreg(FAR struct stm32_can_s *priv, int offset, - uint32_t value); + uint32_t value); static void stm32can_putfreg(FAR struct stm32_can_s *priv, int offset, - uint32_t value); + uint32_t value); #ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32can_dumpctrlregs(FAR struct stm32_can_s *priv, - FAR const char *msg); + FAR const char *msg); static void stm32can_dumpmbregs(FAR struct stm32_can_s *priv, - FAR const char *msg); + FAR const char *msg); static void stm32can_dumpfiltregs(FAR struct stm32_can_s *priv, - FAR const char *msg); + FAR const char *msg); #else # define stm32can_dumpctrlregs(priv,msg) # define stm32can_dumpmbregs(priv,msg) @@ -127,14 +130,16 @@ static void stm32can_dumpfiltregs(FAR struct stm32_can_s *priv, /* Filtering (todo) */ -static int stm32l4can_addextfilter(FAR struct stm32l4_can_s *priv, - FAR struct canioc_extfilter_s *arg); -static int stm32l4can_delextfilter(FAR struct stm32l4_can_s *priv, - int arg); -static int stm32l4can_addstdfilter(FAR struct stm32l4_can_s *priv, - FAR struct canioc_stdfilter_s *arg); -static int stm32l4can_delstdfilter(FAR struct stm32l4_can_s *priv, - int arg); +#ifdef CONFIG_CAN_EXTID +static int stm32can_addextfilter(FAR struct stm32_can_s *priv, + FAR struct canioc_extfilter_s *arg); +static int stm32can_delextfilter(FAR struct stm32_can_s *priv, + int arg); +#endif +static int stm32can_addstdfilter(FAR struct stm32_can_s *priv, + FAR struct canioc_stdfilter_s *arg); +static int stm32can_delstdfilter(FAR struct stm32_can_s *priv, + int arg); /* CAN driver methods */ @@ -144,10 +149,11 @@ static void stm32can_shutdown(FAR struct can_dev_s *dev); static void stm32can_rxint(FAR struct can_dev_s *dev, bool enable); static void stm32can_txint(FAR struct can_dev_s *dev, bool enable); static int stm32can_ioctl(FAR struct can_dev_s *dev, int cmd, - unsigned long arg); -static int stm32can_remoterequest(FAR struct can_dev_s *dev, uint16_t id); + unsigned long arg); +static int stm32can_remoterequest(FAR struct can_dev_s *dev, + uint16_t id); static int stm32can_send(FAR struct can_dev_s *dev, - FAR struct can_msg_s *msg); + FAR struct can_msg_s *msg); static bool stm32can_txready(FAR struct can_dev_s *dev); static bool stm32can_txempty(FAR struct can_dev_s *dev); @@ -160,6 +166,8 @@ static int stm32can_txinterrupt(int irq, FAR void *context); /* Initialization */ +static int stm32can_enterinitmode(FAR struct stm32_can_s *priv); +static int stm32can_exitinitmode(FAR struct stm32_can_s *priv); static int stm32can_bittiming(FAR struct stm32_can_s *priv); static int stm32can_cellinit(FAR struct stm32_can_s *priv); static int stm32can_filterinit(FAR struct stm32_can_s *priv); @@ -344,7 +352,6 @@ static uint32_t stm32can_getfreg(FAR struct stm32_can_s *priv, int offset) #ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32can_vputreg(uint32_t addr, uint32_t value) { - /* Show the register value being written */ caninfo("%08x<-%08x\n", addr, value); @@ -396,7 +403,7 @@ static void stm32can_putfreg(FAR struct stm32_can_s *priv, int offset, #ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32can_dumpctrlregs(FAR struct stm32_can_s *priv, - FAR const char *msg) + FAR const char *msg) { if (msg) { @@ -441,7 +448,7 @@ static void stm32can_dumpctrlregs(FAR struct stm32_can_s *priv, #ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32can_dumpmbregs(FAR struct stm32_can_s *priv, - FAR const char *msg) + FAR const char *msg) { if (msg) { @@ -502,7 +509,7 @@ static void stm32can_dumpmbregs(FAR struct stm32_can_s *priv, #ifdef CONFIG_STM32_CAN_REGDEBUG static void stm32can_dumpfiltregs(FAR struct stm32_can_s *priv, - FAR const char *msg) + FAR const char *msg) { int i; @@ -623,7 +630,8 @@ static int stm32can_setup(FAR struct can_dev_s *dev) ret = stm32can_cellinit(priv); if (ret < 0) { - canerr("ERROR: CAN%d cell initialization failed: %d\n", priv->port, ret); + canerr("ERROR: CAN%d cell initialization failed: %d\n", + priv->port, ret); return ret; } @@ -635,7 +643,8 @@ static int stm32can_setup(FAR struct can_dev_s *dev) ret = stm32can_filterinit(priv); if (ret < 0) { - canerr("ERROR: CAN%d filter initialization failed: %d\n", priv->port, ret); + canerr("ERROR: CAN%d filter initialization failed: %d\n", + priv->port, ret); return ret; } @@ -648,7 +657,7 @@ static int stm32can_setup(FAR struct can_dev_s *dev) ret = irq_attach(priv->canrx[0], stm32can_rx0interrupt); if (ret < 0) { - canerr(ERROR: "Failed to attach CAN%d RX0 IRQ (%d)", + canerr("ERROR: Failed to attach CAN%d RX0 IRQ (%d)", priv->port, priv->canrx[0]); return ret; } @@ -750,6 +759,7 @@ static void stm32can_rxint(FAR struct can_dev_s *dev, bool enable) { regval &= ~(CAN_IER_FMPIE0 | CAN_IER_FMPIE1); } + stm32can_putreg(priv, STM32_CAN_IER_OFFSET, regval); } @@ -892,6 +902,7 @@ static int stm32can_ioctl(FAR struct can_dev_s *dev, int cmd, /* This timing is not possible */ ret = -EINVAL; + break; } /* Otherwise, nquanta is can_bit_quanta, ts1 and ts2 are @@ -905,11 +916,13 @@ static int stm32can_ioctl(FAR struct can_dev_s *dev, int cmd, DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX); } - caninfo("TS1: %d TS2: %d BRP: %d\n", bt->bt_tseg1, bt->bt_tseg2, brp); + caninfo("TS1: %d TS2: %d BRP: %d\n", + bt->bt_tseg1, bt->bt_tseg2, brp); /* Configure bit timing. */ - regval &= ~(CAN_BTR_BRP_MASK | CAN_BTR_TS1_MASK | CAN_BTR_TS2_MASK | CAN_BTR_SJW_MASK); + regval &= ~(CAN_BTR_BRP_MASK | CAN_BTR_TS1_MASK | + CAN_BTR_TS2_MASK | CAN_BTR_SJW_MASK); regval |= ((brp - 1) << CAN_BTR_BRP_SHIFT) | ((bt->bt_tseg1 - 1) << CAN_BTR_TS1_SHIFT) | ((bt->bt_tseg2 - 1) << CAN_BTR_TS2_SHIFT) | @@ -918,7 +931,7 @@ static int stm32can_ioctl(FAR struct can_dev_s *dev, int cmd, /* Bit timing can only be configured in init mode. */ ret = stm32can_enterinitmode(priv); - if (ret != 0) + if (ret < 0) { break; } @@ -926,10 +939,10 @@ static int stm32can_ioctl(FAR struct can_dev_s *dev, int cmd, stm32can_putreg(priv, STM32_CAN_BTR_OFFSET, regval); ret = stm32can_exitinitmode(priv); - - if (ret == 0) + if (ret >= 0) { - priv->baud = STM32_PCLK1_FREQUENCY / (brp * (bt->bt_tseg1 + bt->bt_tseg2 + 1)); + priv->baud = STM32_PCLK1_FREQUENCY / + (brp * (bt->bt_tseg1 + bt->bt_tseg2 + 1)); } } break; @@ -984,26 +997,26 @@ static int stm32can_ioctl(FAR struct can_dev_s *dev, int cmd, if (bm->bm_loopback) { - regval |= CAN_BTR_LBKM; + regval |= CAN_BTR_LBKM; } else { - regval &= ~CAN_BTR_LBKM; + regval &= ~CAN_BTR_LBKM; } if (bm->bm_silent) { - regval |= CAN_BTR_SILM; + regval |= CAN_BTR_SILM; } else { - regval &= ~CAN_BTR_SILM; + regval &= ~CAN_BTR_SILM; } /* This register can only be configured in init mode. */ ret = stm32can_enterinitmode(priv); - if (ret != 0) + if (ret < 0) { break; } @@ -1027,7 +1040,8 @@ static int stm32can_ioctl(FAR struct can_dev_s *dev, int cmd, case CANIOC_ADD_EXTFILTER: { DEBUGASSERT(arg != 0); - ret = stm32can_addextfilter(priv, (FAR struct canioc_extfilter_s *)arg); + ret = stm32can_addextfilter(priv, + (FAR struct canioc_extfilter_s *)arg); } break; @@ -1043,7 +1057,9 @@ static int stm32can_ioctl(FAR struct can_dev_s *dev, int cmd, case CANIOC_DEL_EXTFILTER: { +#if 0 /* Unimplemented */ DEBUGASSERT(arg <= priv->config->nextfilters); +#endif ret = stm32can_delextfilter(priv, (int)arg); } break; @@ -1061,7 +1077,8 @@ static int stm32can_ioctl(FAR struct can_dev_s *dev, int cmd, case CANIOC_ADD_STDFILTER: { DEBUGASSERT(arg != 0); - ret = stm32can_addstdfilter(priv, (FAR struct canioc_stdfilter_s *)arg); + ret = stm32can_addstdfilter(priv, + (FAR struct canioc_stdfilter_s *)arg); } break; @@ -1077,7 +1094,9 @@ static int stm32can_ioctl(FAR struct can_dev_s *dev, int cmd, case CANIOC_DEL_STDFILTER: { +#if 0 /* Unimplemented */ DEBUGASSERT(arg <= priv->config->nstdfilters); +#endif ret = stm32can_delstdfilter(priv, (int)arg); } break; @@ -1135,7 +1154,8 @@ static int stm32can_remoterequest(FAR struct can_dev_s *dev, uint16_t id) * ****************************************************************************/ -static int stm32can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg) +static int stm32can_send(FAR struct can_dev_s *dev, + FAR struct can_msg_s *msg) { FAR struct stm32_can_s *priv = dev->cd_priv; FAR uint8_t *ptr; @@ -1231,6 +1251,7 @@ static int stm32can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg) } } } + stm32can_putreg(priv, STM32_CAN_TDLR_OFFSET(txmb), regval); regval = 0; @@ -1257,6 +1278,7 @@ static int stm32can_send(FAR struct can_dev_s *dev, FAR struct can_msg_s *msg) } } } + stm32can_putreg(priv, STM32_CAN_TDHR_OFFSET(txmb), regval); /* Enable the transmit mailbox empty interrupt (may already be enabled) */ @@ -1661,6 +1683,7 @@ static int stm32can_txinterrupt(int irq, FAR void *context) * Tbs1 = Tq * ts1 * Tbs2 = Tq * ts2 * Tq = brp * Tpclk1 + * baud = Fpclk1 / (brp * (1 + ts1 + ts2)) * * Where: * Tpclk1 is the period of the APB1 clock (PCLK1). @@ -1757,10 +1780,12 @@ static int stm32can_bittiming(FAR struct stm32_can_s *priv) } /**************************************************************************** - * Name: stm32can_cellinit + * Name: stm32can_enterinitmode * * Description: - * CAN cell initialization + * Put the CAN cell in Initialization mode. This only disconnects the CAN + * peripheral, no registers are changed. The initialization mode is + * required to change the baud rate. * * Input Parameter: * priv - A pointer to the private data structure for this CAN block @@ -1770,22 +1795,16 @@ static int stm32can_bittiming(FAR struct stm32_can_s *priv) * ****************************************************************************/ -static int stm32can_cellinit(FAR struct stm32_can_s *priv) +static int stm32can_enterinitmode(FAR struct stm32_can_s *priv) { - volatile uint32_t timeout; uint32_t regval; - int ret; + volatile uint32_t timeout; caninfo("CAN%d\n", priv->port); - /* Exit from sleep mode */ - - regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET); - regval &= ~CAN_MCR_SLEEP; - stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); - /* Enter initialization mode */ + regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET); regval |= CAN_MCR_INRQ; stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); @@ -1810,31 +1829,29 @@ static int stm32can_cellinit(FAR struct stm32_can_s *priv) return -ETIMEDOUT; } - /* Disable the following modes: - * - * - Time triggered communication mode - * - Automatic bus-off management - * - Automatic wake-up mode - * - No automatic retransmission - * - Receive FIFO locked mode - * - Transmit FIFO priority - */ - - regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET); - regval &= ~(CAN_MCR_TXFP | CAN_MCR_RFLM | CAN_MCR_NART | - CAN_MCR_AWUM | CAN_MCR_ABOM | CAN_MCR_TTCM); - stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); + return OK; +} - /* Configure bit timing. */ +/**************************************************************************** + * Name: stm32can_exitinitmode + * + * Description: + * Put the CAN cell out of the Initialization mode (to Normal mode) + * + * Input Parameter: + * priv - A pointer to the private data structure for this CAN block + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ - ret = stm32can_bittiming(priv); - if (ret < 0) - { - canerr("ERROR: Failed to set bit timing: %d\n", ret); - return ret; - } +static int stm32can_exitinitmode(FAR struct stm32_can_s *priv) +{ + uint32_t regval; + volatile uint32_t timeout; - /* Exit initialization mode */ + /* Exit Initialization mode, enter Normal mode */ regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET); regval &= ~CAN_MCR_INRQ; @@ -1861,9 +1878,70 @@ static int stm32can_cellinit(FAR struct stm32_can_s *priv) regval); return -ETIMEDOUT; } + return OK; } +/**************************************************************************** + * Name: stm32can_cellinit + * + * Description: + * CAN cell initialization + * + * Input Parameter: + * priv - A pointer to the private data structure for this CAN block + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static int stm32can_cellinit(FAR struct stm32_can_s *priv) +{ + uint32_t regval; + int ret; + + caninfo("CAN%d\n", priv->port); + + /* Exit from sleep mode */ + + regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET); + regval &= ~CAN_MCR_SLEEP; + stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); + + ret = stm32can_enterinitmode(priv); + if(ret != 0) + { + return ret; + } + + /* Disable the following modes: + * + * - Time triggered communication mode + * - Automatic bus-off management + * - Automatic wake-up mode + * - No automatic retransmission + * - Receive FIFO locked mode + * - Transmit FIFO priority + */ + + regval = stm32can_getreg(priv, STM32_CAN_MCR_OFFSET); + regval &= ~(CAN_MCR_TXFP | CAN_MCR_RFLM | CAN_MCR_NART | + CAN_MCR_AWUM | CAN_MCR_ABOM | CAN_MCR_TTCM); + stm32can_putreg(priv, STM32_CAN_MCR_OFFSET, regval); + + /* Configure bit timing. */ + + ret = stm32can_bittiming(priv); + if (ret < 0) + { + canerr("ERROR: Failed to set bit timing: %d\n", ret); + return ret; + } + + return stm32can_exitinitmode(priv); +} + /**************************************************************************** * Name: stm32can_filterinit * @@ -1987,11 +2065,13 @@ static int stm32can_filterinit(FAR struct stm32_can_s *priv) * ****************************************************************************/ -static int stm32can_addextfilter(FAR struct stm32_can_s *priv, - FAR struct canioc_extfilter_s *arg) +#ifdef CONFIG_CAN_EXTID +static int stm32can_addextfilter(FAR struct stm32_can_s *priv, + FAR struct canioc_extfilter_s *arg) { return -ENOTTY; } +#endif /**************************************************************************** * Name: stm32can_delextfilter @@ -2011,13 +2091,15 @@ static int stm32can_addextfilter(FAR struct stm32_can_s *priv, * ****************************************************************************/ -static int stm32can_delextfilter(FAR struct stm32_can_s *priv, int arg) +#ifdef CONFIG_CAN_EXTID +static int stm32can_delextfilter(FAR struct stm32_can_s *priv, int arg) { return -ENOTTY; } +#endif /**************************************************************************** - * Name: stm32can_addextfilter + * Name: stm32can_addstdfilter * * Description: * Add a filter for standard CAN IDs @@ -2033,8 +2115,8 @@ static int stm32can_delextfilter(FAR struct stm32_can_s *priv, int arg) * ****************************************************************************/ -static int stm32can_addstdfilter(FAR struct stm32_can_s *priv, - FAR struct canioc_stdfilter_s *arg) +static int stm32can_addstdfilter(FAR struct stm32_can_s *priv, + FAR struct canioc_stdfilter_s *arg) { return -ENOTTY; } @@ -2057,7 +2139,7 @@ static int stm32can_addstdfilter(FAR struct stm32_can_s *priv, * ****************************************************************************/ -static int stm32can_delstdfilter(FAR struct stm32_can_s *priv, int arg) +static int stm32can_delstdfilter(FAR struct stm32_can_s *priv, int arg) { return -ENOTTY; } diff --git a/arch/arm/src/stm32/stm32_freerun.c b/arch/arm/src/stm32/stm32_freerun.c new file mode 100644 index 0000000000000000000000000000000000000000..836df043ad79478b17307d8fb7808b81717bfb71 --- /dev/null +++ b/arch/arm/src/stm32/stm32_freerun.c @@ -0,0 +1,296 @@ +/**************************************************************************** + * arch/arm/src/stm32/stm32_freerun.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the names NuttX nor Atmel nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "stm32_freerun.h" + +#ifdef CONFIG_STM32_FREERUN + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +static struct stm32_freerun_s *g_freerun; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_freerun_handler + * + * Description: + * Timer interrupt callback. When the freerun timer counter overflows, + * this interrupt will occur. We will just increment an overflow count. + * + * Input Parameters: + * tch - The handle that represents the timer state + * arg - An opaque argument provided when the interrupt was registered + * sr - The value of the timer interrupt status register at the time + * that the interrupt occurred. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static int stm32_freerun_handler(int irq, void *context) +{ + struct stm32_freerun_s *freerun = g_freerun; + + DEBUGASSERT(freerun != NULL && freerun->overflow < UINT32_MAX); + freerun->overflow++; + + STM32_TIM_ACKINT(freerun->tch, 0); + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_freerun_initialize + * + * Description: + * Initialize the freerun timer wrapper + * + * Input Parameters: + * freerun Caller allocated instance of the freerun state structure + * chan Timer counter channel to be used. + * resolution The required resolution of the timer in units of + * microseconds. NOTE that the range is restricted to the + * range of uint16_t (excluding zero). + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, + uint16_t resolution) +{ + uint32_t frequency; + + tmrinfo("chan=%d resolution=%d usec\n", chan, resolution); + DEBUGASSERT(freerun != NULL && resolution > 0); + + /* Get the TC frequency the corresponds to the requested resolution */ + + frequency = USEC_PER_SEC / (uint32_t)resolution; + freerun->frequency = frequency; + + freerun->tch = stm32_tim_init(chan); + if (!freerun->tch) + { + tmrerr("ERROR: Failed to allocate TIM%d\n", chan); + return -EBUSY; + } + + STM32_TIM_SETCLOCK(freerun->tch, frequency); + + /* Initialize the remaining fields in the state structure and return + * success. + */ + + freerun->chan = chan; + freerun->running = false; + freerun->overflow = 0; + + g_freerun = freerun; + + /* Set up to receive the callback when the counter overflow occurs */ + + STM32_TIM_SETISR(freerun->tch, stm32_freerun_handler, 0); + + /* Set timer period */ + + STM32_TIM_SETPERIOD(freerun->tch, UINT32_MAX); + + /* Start the counter */ + + STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_UP); + STM32_TIM_ACKINT(freerun->tch, 0); + STM32_TIM_ENABLEINT(freerun->tch, 0); + + return OK; +} + +/**************************************************************************** + * Name: stm32_freerun_counter + * + * Description: + * Read the counter register of the free-running timer. + * + * Input Parameters: + * freerun Caller allocated instance of the freerun state structure. This + * structure must have been previously initialized via a call to + * stm32_freerun_initialize(); + * ts The location in which to return the time from the free-running + * timer. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int stm32_freerun_counter(struct stm32_freerun_s *freerun, + struct timespec *ts) +{ + uint64_t usec; + uint32_t counter; + uint32_t verify; + uint32_t overflow; + uint32_t sec; + int pending; + irqstate_t flags; + + DEBUGASSERT(freerun && freerun->tch && ts); + + /* Temporarily disable the overflow counter. NOTE that we have to be + * careful here because stm32_tc_getpending() will reset the pending + * interrupt status. If we do not handle the overflow here then, it will + * be lost. + */ + + flags = enter_critical_section(); + + overflow = freerun->overflow; + counter = STM32_TIM_GETCOUNTER(freerun->tch); + pending = STM32_TIM_CHECKINT(freerun->tch, 0); + verify = STM32_TIM_GETCOUNTER(freerun->tch); + + /* If an interrupt was pending before we re-enabled interrupts, + * then the overflow needs to be incremented. + */ + + if (pending) + { + STM32_TIM_ACKINT(freerun->tch, 0); + + /* Increment the overflow count and use the value of the + * guaranteed to be AFTER the overflow occurred. + */ + + overflow++; + counter = verify; + + /* Update freerun overflow counter. */ + + freerun->overflow = overflow; + } + + leave_critical_section(flags); + + tmrinfo("counter=%lu (%lu) overflow=%lu, pending=%i\n", + (unsigned long)counter, (unsigned long)verify, + (unsigned long)overflow, pending); + tmrinfo("frequency=%u\n", freerun->frequency); + + /* Convert the whole thing to units of microseconds. + * + * frequency = ticks / second + * seconds = ticks * frequency + * usecs = (ticks * USEC_PER_SEC) / frequency; + */ + + usec = ((((uint64_t)overflow << 32) + (uint64_t)counter) * USEC_PER_SEC) / + freerun->frequency; + + /* And return the value of the timer */ + + sec = (uint32_t)(usec / USEC_PER_SEC); + ts->tv_sec = sec; + ts->tv_nsec = (usec - (sec * USEC_PER_SEC)) * NSEC_PER_USEC; + + tmrinfo("usec=%llu ts=(%u, %lu)\n", + usec, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec); + + return OK; +} + +/**************************************************************************** + * Name: stm32_freerun_uninitialize + * + * Description: + * Stop the free-running timer and release all resources that it uses. + * + * Input Parameters: + * freerun Caller allocated instance of the freerun state structure. This + * structure must have been previously initialized via a call to + * stm32_freerun_initialize(); + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun) +{ + DEBUGASSERT(freerun && freerun->tch); + + /* Now we can disable the timer interrupt and disable the timer. */ + + STM32_TIM_DISABLEINT(freerun->tch, 0); + STM32_TIM_SETMODE(freerun->tch, STM32_TIM_MODE_DISABLED); + STM32_TIM_SETISR(freerun->tch, NULL, 0); + + /* Free the timer */ + + stm32_tim_deinit(freerun->tch); + freerun->tch = NULL; + + g_freerun = NULL; + return OK; +} + +#endif /* CONFIG_STM32_ONESHOT */ diff --git a/arch/arm/src/stm32/stm32_freerun.h b/arch/arm/src/stm32/stm32_freerun.h new file mode 100644 index 0000000000000000000000000000000000000000..08dd1786da7cb3d73e95913e7c5a6abf9e44b757 --- /dev/null +++ b/arch/arm/src/stm32/stm32_freerun.h @@ -0,0 +1,158 @@ +/**************************************************************************** + * arch/arm/src/stm32/stm32_freerun.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_FREERUN_H +#define __ARCH_ARM_SRC_STM32_FREERUN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "stm32_tim.h" + +#ifdef CONFIG_STM32_FREERUN + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* The freerun client must allocate an instance of this structure and called + * stm32_freerun_initialize() before using the freerun facilities. The client + * should not access the contents of this structure directly since the + * contents are subject to change. + */ + +struct stm32_freerun_s +{ + uint8_t chan; /* The timer/counter in use */ + bool running; /* True: the timer is running */ + uint32_t overflow; /* Timer counter overflow */ + FAR struct stm32_tim_dev_s *tch; /* Handle returned by stm32_tim_init() */ + uint32_t frequency; +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_freerun_initialize + * + * Description: + * Initialize the freerun timer wrapper + * + * Input Parameters: + * freerun Caller allocated instance of the freerun state structure + * chan Timer counter channel to be used. + * resolution The required resolution of the timer in units of + * microseconds. NOTE that the range is restricted to the + * range of uint16_t (excluding zero). + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int stm32_freerun_initialize(struct stm32_freerun_s *freerun, int chan, + uint16_t resolution); + +/**************************************************************************** + * Name: stm32_freerun_counter + * + * Description: + * Read the counter register of the free-running timer. + * + * Input Parameters: + * freerun Caller allocated instance of the freerun state structure. This + * structure must have been previously initialized via a call to + * stm32_freerun_initialize(); + * ts The location in which to return the time remaining on the + * oneshot timer. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int stm32_freerun_counter(struct stm32_freerun_s *freerun, + struct timespec *ts); + +/**************************************************************************** + * Name: stm32_freerun_uninitialize + * + * Description: + * Stop the free-running timer and release all resources that it uses. + * + * Input Parameters: + * freerun Caller allocated instance of the freerun state structure. This + * structure must have been previously initialized via a call to + * stm32_freerun_initialize(); + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int stm32_freerun_uninitialize(struct stm32_freerun_s *freerun); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* CONFIG_STM32_FREERUN */ +#endif /* __ARCH_ARM_SRC_STM32_FREERUN_H */ diff --git a/arch/arm/src/stm32/stm32_irq.c b/arch/arm/src/stm32/stm32_irq.c index 062d63fb7499afddac41d1dfac7f9b0b31f45e7e..ea7c4ddfcbe1d1039a2ab46567ef8beb772e815e 100644 --- a/arch/arm/src/stm32/stm32_irq.c +++ b/arch/arm/src/stm32/stm32_irq.c @@ -245,31 +245,23 @@ static inline void stm32_prioritize_syscall(int priority) static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, uintptr_t offset) { + int n; + DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS); /* Check for external interrupt */ if (irq >= STM32_IRQ_FIRST) { - if (irq < STM32_IRQ_FIRST + 32) - { - *regaddr = (NVIC_IRQ0_31_ENABLE + offset); - *bit = 1 << (irq - STM32_IRQ_FIRST); - } - else if (irq < STM32_IRQ_FIRST + 64) - { - *regaddr = (NVIC_IRQ32_63_ENABLE + offset); - *bit = 1 << (irq - STM32_IRQ_FIRST - 32); - } - else if (irq < NR_IRQS) - { - *regaddr = (NVIC_IRQ64_95_ENABLE + offset); - *bit = 1 << (irq - STM32_IRQ_FIRST - 64); - } - else + n = irq - STM32_IRQ_FIRST; + *regaddr = NVIC_IRQ_ENABLE(n) + offset; + + while (n >= 32) { - return ERROR; /* Invalid interrupt */ + n -= 32; } + + *bit = 1 << n; } /* Handle processor exceptions. Only a few can be disabled */ @@ -315,11 +307,14 @@ void up_irqinitialize(void) { uint32_t regaddr; int num_priority_registers; + int i; /* Disable all interrupts */ - putreg32(0, NVIC_IRQ0_31_ENABLE); - putreg32(0, NVIC_IRQ32_63_ENABLE); + for (i = 0; i < NR_IRQS - STM32_IRQ_FIRST; i += 32) + { + putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); + } /* Colorize the interrupt stack for debug purposes */ diff --git a/arch/arm/src/stm32/stm32_oneshot.c b/arch/arm/src/stm32/stm32_oneshot.c new file mode 100644 index 0000000000000000000000000000000000000000..8f5e89df6229ebff2cee0a7c966254b82bca4311 --- /dev/null +++ b/arch/arm/src/stm32/stm32_oneshot.c @@ -0,0 +1,415 @@ +/**************************************************************************** + * arch/arm/src/stm32/stm32_oneshot.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the names NuttX nor Atmel nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "stm32_oneshot.h" + +#ifdef CONFIG_STM32_ONESHOT + +/**************************************************************************** + * Private Date + ****************************************************************************/ + +static struct stm32_oneshot_s *g_oneshot; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_oneshot_handler + * + * Description: + * Timer interrupt callback. When the oneshot timer interrupt expires, + * this function will be called. It will forward the call to the next + * level up. + * + * Input Parameters: + * tch - The handle that represents the timer state + * arg - An opaque argument provided when the interrupt was registered + * sr - The value of the timer interrupt status register at the time + * that the interrupt occurred. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static int stm32_oneshot_handler(int irq, void *context) +{ + struct stm32_oneshot_s *oneshot = g_oneshot; + oneshot_handler_t oneshot_handler; + void *oneshot_arg; + + tmrinfo("Expired...\n"); + DEBUGASSERT(oneshot != NULL && oneshot->handler); + + /* The clock was stopped, but not disabled when the RC match occurred. + * Disable the TC now and disable any further interrupts. + */ + + STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); + STM32_TIM_ACKINT(oneshot->tch, 0); + STM32_TIM_DISABLEINT(oneshot->tch, 0); + + /* The timer is no longer running */ + + oneshot->running = false; + + /* Forward the event, clearing out any vestiges */ + + oneshot_handler = (oneshot_handler_t)oneshot->handler; + oneshot->handler = NULL; + oneshot_arg = (void *)oneshot->arg; + oneshot->arg = NULL; + + oneshot_handler(oneshot_arg); + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_oneshot_initialize + * + * Description: + * Initialize the oneshot timer wrapper + * + * Input Parameters: + * oneshot Caller allocated instance of the oneshot state structure + * chan Timer counter channel to be used. + * resolution The required resolution of the timer in units of + * microseconds. NOTE that the range is restricted to the + * range of uint16_t (excluding zero). + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, + uint16_t resolution) +{ + uint32_t frequency; + + tmrinfo("chan=%d resolution=%d usec\n", chan, resolution); + DEBUGASSERT(oneshot && resolution > 0); + + /* Get the TC frequency the corresponds to the requested resolution */ + + frequency = USEC_PER_SEC / (uint32_t)resolution; + oneshot->frequency = frequency; + + oneshot->tch = stm32_tim_init(chan); + if (!oneshot->tch) + { + tmrerr("ERROR: Failed to allocate TIM%d\n", chan); + return -EBUSY; + } + + STM32_TIM_SETCLOCK(oneshot->tch, frequency); + + /* Initialize the remaining fields in the state structure and return + * success. + */ + + oneshot->chan = chan; + oneshot->running = false; + oneshot->handler = NULL; + oneshot->arg = NULL; + + g_oneshot = oneshot; + return OK; +} + +/**************************************************************************** + * Name: stm32_oneshot_max_delay + * + * Description: + * Determine the maximum delay of the one-shot timer (in microseconds) + * + ****************************************************************************/ + +int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec) +{ + DEBUGASSERT(oneshot != NULL && usec != NULL); + + *usec = (uint64_t)(UINT32_MAX / oneshot->frequency) * + (uint64_t)USEC_PER_SEC; + return OK; +} + +/**************************************************************************** + * Name: stm32_oneshot_start + * + * Description: + * Start the oneshot timer + * + * Input Parameters: + * oneshot Caller allocated instance of the oneshot state structure. This + * structure must have been previously initialized via a call to + * stm32_oneshot_initialize(); + * handler The function to call when when the oneshot timer expires. + * arg An opaque argument that will accompany the callback. + * ts Provides the duration of the one shot timer. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, + oneshot_handler_t handler, void *arg, + const struct timespec *ts) +{ + uint64_t usec; + uint64_t period; + irqstate_t flags; + + tmrinfo("handler=%p arg=%p, ts=(%lu, %lu)\n", + handler, arg, (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec); + DEBUGASSERT(oneshot && handler && ts); + DEBUGASSERT(oneshot->tch); + + /* Was the oneshot already running? */ + + flags = enter_critical_section(); + if (oneshot->running) + { + /* Yes.. then cancel it */ + + tmrinfo("Already running... cancelling\n"); + (void)stm32_oneshot_cancel(oneshot, NULL); + } + + /* Save the new handler and its argument */ + + oneshot->handler = handler; + oneshot->arg = arg; + + /* Express the delay in microseconds */ + + usec = (uint64_t)ts->tv_sec * USEC_PER_SEC + + (uint64_t)(ts->tv_nsec / NSEC_PER_USEC); + + /* Get the timer counter frequency and determine the number of counts need + * to achieve the requested delay. + * + * frequency = ticks / second + * ticks = seconds * frequency + * = (usecs * frequency) / USEC_PER_SEC; + */ + + period = (usec * (uint64_t)oneshot->frequency) / USEC_PER_SEC; + + tmrinfo("usec=%llu period=%08llx\n", usec, period); + DEBUGASSERT(period <= UINT32_MAX); + + /* Set up to receive the callback when the interrupt occurs */ + + STM32_TIM_SETISR(oneshot->tch, stm32_oneshot_handler, 0); + + /* Set timer period */ + + oneshot->period = (uint32_t)period; + STM32_TIM_SETPERIOD(oneshot->tch, (uint32_t)period); + + /* Start the counter */ + + STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_PULSE); + + STM32_TIM_ACKINT(oneshot->tch, 0); + STM32_TIM_ENABLEINT(oneshot->tch, 0); + + /* Enable interrupts. We should get the callback when the interrupt + * occurs. + */ + + oneshot->running = true; + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_oneshot_cancel + * + * Description: + * Cancel the oneshot timer and return the time remaining on the timer. + * + * NOTE: This function may execute at a high rate with no timer running (as + * when pre-emption is enabled and disabled). + * + * Input Parameters: + * oneshot Caller allocated instance of the oneshot state structure. This + * structure must have been previously initialized via a call to + * stm32_oneshot_initialize(); + * ts The location in which to return the time remaining on the + * oneshot timer. A time of zero is returned if the timer is + * not running. ts may be zero in which case the time remaining + * is not returned. + * + * Returned Value: + * Zero (OK) is returned on success. A call to up_timer_cancel() when + * the timer is not active should also return success; a negated errno + * value is returned on any failure. + * + ****************************************************************************/ + +int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, + struct timespec *ts) +{ + irqstate_t flags; + uint64_t usec; + uint64_t sec; + uint64_t nsec; + uint32_t count; + uint32_t period; + + /* Was the timer running? */ + + flags = enter_critical_section(); + if (!oneshot->running) + { + /* No.. Just return zero timer remaining and successful cancellation. + * This function may execute at a high rate with no timer running + * (as when pre-emption is enabled and disabled). + */ + + ts->tv_sec = 0; + ts->tv_nsec = 0; + leave_critical_section(flags); + return OK; + } + + /* Yes.. Get the timer counter and period registers and stop the counter. + * If the counter expires while we are doing this, the counter clock will + * be stopped, but the clock will not be disabled. + * + * The expected behavior is that the the counter register will freezes at + * a value equal to the RC register when the timer expires. The counter + * should have values between 0 and RC in all other cased. + * + * REVISIT: This does not appear to be the case. + */ + + tmrinfo("Cancelling...\n"); + + count = STM32_TIM_GETCOUNTER(oneshot->tch); + period = oneshot->period; + + /* Now we can disable the interrupt and stop the timer. */ + + STM32_TIM_DISABLEINT(oneshot->tch, 0); + STM32_TIM_SETMODE(oneshot->tch, STM32_TIM_MODE_DISABLED); + + oneshot->running = false; + oneshot->handler = NULL; + oneshot->arg = NULL; + leave_critical_section(flags); + + /* Did the caller provide us with a location to return the time + * remaining? + */ + + if (ts) + { + /* Yes.. then calculate and return the time remaining on the + * oneshot timer. + */ + + tmrinfo("period=%lu count=%lu\n", + (unsigned long)period, (unsigned long)count); + + /* REVISIT: I am not certain why the timer counter value sometimes + * exceeds RC. Might be a bug, or perhaps the counter does not stop + * in all cases. + */ + + if (count >= period) + { + /* No time remaining (?) */ + + ts->tv_sec = 0; + ts->tv_nsec = 0; + } + else + { + /* The total time remaining is the difference. Convert the that + * to units of microseconds. + * + * frequency = ticks / second + * seconds = ticks * frequency + * usecs = (ticks * USEC_PER_SEC) / frequency; + */ + + usec = (((uint64_t)(period - count)) * USEC_PER_SEC) / + oneshot->frequency; + + /* Return the time remaining in the correct form */ + + sec = usec / USEC_PER_SEC; + nsec = ((usec) - (sec * USEC_PER_SEC)) * NSEC_PER_USEC; + + ts->tv_sec = (time_t)sec; + ts->tv_nsec = (unsigned long)nsec; + } + + tmrinfo("remaining (%lu, %lu)\n", + (unsigned long)ts->tv_sec, (unsigned long)ts->tv_nsec); + } + + return OK; +} + +#endif /* CONFIG_STM32_ONESHOT */ diff --git a/arch/arm/src/stm32/stm32_oneshot.h b/arch/arm/src/stm32/stm32_oneshot.h new file mode 100644 index 0000000000000000000000000000000000000000..bff21319393237845d02b0522ce0f36886838c05 --- /dev/null +++ b/arch/arm/src/stm32/stm32_oneshot.h @@ -0,0 +1,189 @@ +/**************************************************************************** + * arch/arm/src/stm32/stm32_oneshot.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_ONESHOT_H +#define __ARCH_ARM_SRC_STM32_ONESHOT_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "stm32_tim.h" + +#ifdef CONFIG_STM32_ONESHOT + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* This describes the callback function that will be invoked when the oneshot + * timer expires. The oneshot fires, the client will receive: + * + * arg - The opaque argument provided when the interrupt was registered + */ + +typedef void (*oneshot_handler_t)(void *arg); + +/* The oneshot client must allocate an instance of this structure and called + * stm32_oneshot_initialize() before using the oneshot facilities. The client + * should not access the contents of this structure directly since the + * contents are subject to change. + */ + +struct stm32_oneshot_s +{ + uint8_t chan; /* The timer/counter in use */ + volatile bool running; /* True: the timer is running */ + FAR struct stm32_tim_dev_s *tch; /* Pointer returned by + * stm32_tim_init() */ + volatile oneshot_handler_t handler; /* Oneshot expiration callback */ + volatile void *arg; /* The argument that will accompany + * the callback */ + uint32_t frequency; + uint32_t period; +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_oneshot_initialize + * + * Description: + * Initialize the oneshot timer wrapper + * + * Input Parameters: + * oneshot Caller allocated instance of the oneshot state structure + * chan Timer counter channel to be used. + * resolution The required resolution of the timer in units of + * microseconds. NOTE that the range is restricted to the + * range of uint16_t (excluding zero). + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int stm32_oneshot_initialize(struct stm32_oneshot_s *oneshot, int chan, + uint16_t resolution); + +/**************************************************************************** + * Name: stm32_oneshot_max_delay + * + * Description: + * Determine the maximum delay of the one-shot timer (in microseconds) + * + ****************************************************************************/ + +int stm32_oneshot_max_delay(struct stm32_oneshot_s *oneshot, uint64_t *usec); + +/**************************************************************************** + * Name: stm32_oneshot_start + * + * Description: + * Start the oneshot timer + * + * Input Parameters: + * oneshot Caller allocated instance of the oneshot state structure. This + * structure must have been previously initialized via a call to + * stm32_oneshot_initialize(); + * handler The function to call when when the oneshot timer expires. + * arg An opaque argument that will accompany the callback. + * ts Provides the duration of the one shot timer. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on failure. + * + ****************************************************************************/ + +int stm32_oneshot_start(struct stm32_oneshot_s *oneshot, + oneshot_handler_t handler, void *arg, + const struct timespec *ts); + +/**************************************************************************** + * Name: stm32_oneshot_cancel + * + * Description: + * Cancel the oneshot timer and return the time remaining on the timer. + * + * NOTE: This function may execute at a high rate with no timer running (as + * when pre-emption is enabled and disabled). + * + * Input Parameters: + * oneshot Caller allocated instance of the oneshot state structure. This + * structure must have been previously initialized via a call to + * stm32_oneshot_initialize(); + * ts The location in which to return the time remaining on the + * oneshot timer. A time of zero is returned if the timer is + * not running. + * + * Returned Value: + * Zero (OK) is returned on success. A call to up_timer_cancel() when + * the timer is not active should also return success; a negated errno + * value is returned on any failure. + * + ****************************************************************************/ + +int stm32_oneshot_cancel(struct stm32_oneshot_s *oneshot, + struct timespec *ts); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* CONFIG_STM32_ONESHOT */ +#endif /* __ARCH_ARM_SRC_STM32_ONESHOT_H */ diff --git a/arch/arm/src/stm32/stm32_tickless.c b/arch/arm/src/stm32/stm32_tickless.c new file mode 100644 index 0000000000000000000000000000000000000000..eadef5ce90db97c91eb797d5e03648a495ce44ed --- /dev/null +++ b/arch/arm/src/stm32/stm32_tickless.c @@ -0,0 +1,350 @@ +/**************************************************************************** + * arch/arm/src/stm32/stm32_tickless.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ +/**************************************************************************** + * Tickless OS Support. + * + * When CONFIG_SCHED_TICKLESS is enabled, all support for timer interrupts + * is suppressed and the platform specific code is expected to provide the + * following custom functions. + * + * void up_timer_initialize(void): Initializes the timer facilities. + * Called early in the initialization sequence (by up_intialize()). + * int up_timer_gettime(FAR struct timespec *ts): Returns the current + * time from the platform specific time source. + * int up_timer_cancel(void): Cancels the interval timer. + * int up_timer_start(FAR const struct timespec *ts): Start (or re-starts) + * the interval timer. + * + * The RTOS will provide the following interfaces for use by the platform- + * specific interval timer implementation: + * + * void sched_timer_expiration(void): Called by the platform-specific + * logic when the interval timer expires. + * + ****************************************************************************/ +/**************************************************************************** + * SAM34 Timer Usage + * + * This current implementation uses two timers: A one-shot timer to provide + * the timed events and a free running timer to provide the current time. + * Since timers are a limited resource, that could be an issue on some + * systems. + * + * We could do the job with a single timer if we were to keep the single + * timer in a free-running at all times. The STM32 timer/counters have + * 16-bit/32-bit counters with the capability to generate a compare interrupt + * when the timer matches a compare value but also to continue counting + * without stopping (giving another, different interrupt when the timer + * rolls over from 0xffffffff to zero). So we could potentially just set + * the compare at the number of ticks you want PLUS the current value of + * timer. Then you could have both with a single timer: An interval timer + * and a free-running counter with the same timer! + * + * Patches are welcome! + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "stm32_oneshot.h" +#include "stm32_freerun.h" + +#ifdef CONFIG_SCHED_TICKLESS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_STM32_ONESHOT +# error CONFIG_STM32_ONESHOT must be selected for the Tickless OS option +#endif + +#ifndef CONFIG_STM32_FREERUN +# error CONFIG_STM32_FREERUN must be selected for the Tickless OS option +#endif + +#ifndef CONFIG_STM32_TICKLESS_FREERUN +# error CONFIG_STM32_TICKLESS_FREERUN must be selected for the Tickless OS option +#endif + +#ifndef CONFIG_STM32_TICKLESS_ONESHOT +# error CONFIG_STM32_TICKLESS_ONESHOT must be selected for the Tickless OS option +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct stm32_tickless_s +{ + struct stm32_oneshot_s oneshot; + struct stm32_freerun_s freerun; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct stm32_tickless_s g_tickless; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_oneshot_handler + * + * Description: + * Called when the one shot timer expires + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + * Assumptions: + * Called early in the initialization sequence before any special + * concurrency protections are required. + * + ****************************************************************************/ + +static void stm32_oneshot_handler(void *arg) +{ + tmrinfo("Expired...\n"); + sched_timer_expiration(); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_timer_initialize + * + * Description: + * Initializes all platform-specific timer facilities. This function is + * called early in the initialization sequence by up_intialize(). + * On return, the current up-time should be available from + * up_timer_gettime() and the interval timer is ready for use (but not + * actively timing. + * + * Provided by platform-specific code and called from the architecture- + * specific logic. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + * Assumptions: + * Called early in the initialization sequence before any special + * concurrency protections are required. + * + ****************************************************************************/ + +void up_timer_initialize(void) +{ +#ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP + uint64_t max_delay; +#endif + int ret; + + /* Initialize the one-shot timer */ + + ret = stm32_oneshot_initialize(&g_tickless.oneshot, + CONFIG_STM32_TICKLESS_ONESHOT, + CONFIG_USEC_PER_TICK); + if (ret < 0) + { + tmrerr("ERROR: stm32_oneshot_initialize failed\n"); + PANIC(); + } + +#ifdef CONFIG_SCHED_TICKLESS_LIMIT_MAX_SLEEP + /* Get the maximum delay of the one-shot timer in microseconds */ + + ret = stm32_oneshot_max_delay(&g_tickless.oneshot, &max_delay); + if (ret < 0) + { + tmrerr("ERROR: stm32_oneshot_max_delay failed\n"); + PANIC(); + } + + /* Convert this to configured clock ticks for use by the OS timer logic */ + + max_delay /= CONFIG_USEC_PER_TICK; + if (max_delay > UINT32_MAX) + { + g_oneshot_maxticks = UINT32_MAX; + } + else + { + g_oneshot_maxticks = max_delay; + } +#endif + + /* Initialize the free-running timer */ + + ret = stm32_freerun_initialize(&g_tickless.freerun, + CONFIG_STM32_TICKLESS_FREERUN, + CONFIG_USEC_PER_TICK); + if (ret < 0) + { + tmrerr("ERROR: stm32_freerun_initialize failed\n"); + PANIC(); + } +} + +/**************************************************************************** + * Name: up_timer_gettime + * + * Description: + * Return the elapsed time since power-up (or, more correctly, since + * up_timer_initialize() was called). This function is functionally + * equivalent to: + * + * int clock_gettime(clockid_t clockid, FAR struct timespec *ts); + * + * when clockid is CLOCK_MONOTONIC. + * + * This function provides the basis for reporting the current time and + * also is used to eliminate error build-up from small errors in interval + * time calculations. + * + * Provided by platform-specific code and called from the RTOS base code. + * + * Input Parameters: + * ts - Provides the location in which to return the up-time. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + * Assumptions: + * Called from the the normal tasking context. The implementation must + * provide whatever mutual exclusion is necessary for correct operation. + * This can include disabling interrupts in order to assure atomic register + * operations. + * + ****************************************************************************/ + +int up_timer_gettime(FAR struct timespec *ts) +{ + return stm32_freerun_counter(&g_tickless.freerun, ts); +} + +/**************************************************************************** + * Name: up_timer_cancel + * + * Description: + * Cancel the interval timer and return the time remaining on the timer. + * These two steps need to be as nearly atomic as possible. + * sched_timer_expiration() will not be called unless the timer is + * restarted with up_timer_start(). + * + * If, as a race condition, the timer has already expired when this + * function is called, then that pending interrupt must be cleared so + * that up_timer_start() and the remaining time of zero should be + * returned. + * + * NOTE: This function may execute at a high rate with no timer running (as + * when pre-emption is enabled and disabled). + * + * Provided by platform-specific code and called from the RTOS base code. + * + * Input Parameters: + * ts - Location to return the remaining time. Zero should be returned + * if the timer is not active. ts may be zero in which case the + * time remaining is not returned. + * + * Returned Value: + * Zero (OK) is returned on success. A call to up_timer_cancel() when + * the timer is not active should also return success; a negated errno + * value is returned on any failure. + * + * Assumptions: + * May be called from interrupt level handling or from the normal tasking + * level. Interrupts may need to be disabled internally to assure + * non-reentrancy. + * + ****************************************************************************/ + +int up_timer_cancel(FAR struct timespec *ts) +{ + return stm32_oneshot_cancel(&g_tickless.oneshot, ts); +} + +/**************************************************************************** + * Name: up_timer_start + * + * Description: + * Start the interval timer. sched_timer_expiration() will be + * called at the completion of the timeout (unless up_timer_cancel + * is called to stop the timing. + * + * Provided by platform-specific code and called from the RTOS base code. + * + * Input Parameters: + * ts - Provides the time interval until sched_timer_expiration() is + * called. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure. + * + * Assumptions: + * May be called from interrupt level handling or from the normal tasking + * level. Interrupts may need to be disabled internally to assure + * non-reentrancy. + * + ****************************************************************************/ + +int up_timer_start(FAR const struct timespec *ts) +{ + return stm32_oneshot_start(&g_tickless.oneshot, stm32_oneshot_handler, NULL, ts); +} +#endif /* CONFIG_SCHED_TICKLESS */ diff --git a/arch/arm/src/stm32/stm32_tim.c b/arch/arm/src/stm32/stm32_tim.c index 62e2783e3a8ff1281fad5e58e35f2259a7ff0128..b001f10cd5e794ff84cb138255ab76eca180f53d 100644 --- a/arch/arm/src/stm32/stm32_tim.c +++ b/arch/arm/src/stm32/stm32_tim.c @@ -64,8 +64,9 @@ #include "stm32_tim.h" /************************************************************************************ - * Private Types + * Pre-processor Definitions ************************************************************************************/ + /* Configuration ********************************************************************/ /* Timer devices may be used for different purposes. Such special purposes include: * @@ -284,16 +285,240 @@ struct stm32_tim_priv_s { - struct stm32_tim_ops_s *ops; - stm32_tim_mode_t mode; - uint32_t base; /* TIMn base address */ + const struct stm32_tim_ops_s *ops; + stm32_tim_mode_t mode; + uint32_t base; /* TIMn base address */ }; +/************************************************************************************ + * Private Function prototypes + ************************************************************************************/ + +/* Register helpers */ + +static inline uint16_t stm32_getreg16(FAR struct stm32_tim_dev_s *dev, + uint8_t offset); +static inline void stm32_putreg16(FAR struct stm32_tim_dev_s *dev, uint8_t offset, + uint16_t value); +static inline void stm32_modifyreg16(FAR struct stm32_tim_dev_s *dev, + uint8_t offset, uint16_t clearbits, + uint16_t setbits); +static inline uint32_t stm32_getreg32(FAR struct stm32_tim_dev_s *dev, + uint8_t offset); +static inline void stm32_putreg32(FAR struct stm32_tim_dev_s *dev, uint8_t offset, + uint32_t value); + +/* Timer helpers */ + +static void stm32_tim_reload_counter(FAR struct stm32_tim_dev_s *dev); +static void stm32_tim_enable(FAR struct stm32_tim_dev_s *dev); +static void stm32_tim_disable(FAR struct stm32_tim_dev_s *dev); +static void stm32_tim_reset(FAR struct stm32_tim_dev_s *dev); +static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode); + +/* Timer methods */ + +static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode); +static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq); +static void stm32_tim_setperiod(FAR struct stm32_tim_dev_s *dev, + uint32_t period); +static uint32_t stm32_tim_getcounter(FAR struct stm32_tim_dev_s *dev); +static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel, + stm32_tim_channel_t mode); +static int stm32_tim_setcompare(FAR struct stm32_tim_dev_s *dev, uint8_t channel, + uint32_t compare); +static int stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev, uint8_t channel); +static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, + int (*handler)(int irq, void *context), + int source); +static void stm32_tim_enableint(FAR struct stm32_tim_dev_s *dev, int source); +static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev, int source); +static void stm32_tim_ackint(FAR struct stm32_tim_dev_s *dev, int source); +static int stm32_tim_checkint(FAR struct stm32_tim_dev_s *dev, int source); + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +static const struct stm32_tim_ops_s stm32_tim_ops = +{ + .setmode = stm32_tim_setmode, + .setclock = stm32_tim_setclock, + .setperiod = stm32_tim_setperiod, + .getcounter = stm32_tim_getcounter, + .setchannel = stm32_tim_setchannel, + .setcompare = stm32_tim_setcompare, + .getcapture = stm32_tim_getcapture, + .setisr = stm32_tim_setisr, + .enableint = stm32_tim_enableint, + .disableint = stm32_tim_disableint, + .ackint = stm32_tim_ackint, + .checkint = stm32_tim_checkint, +}; + +#ifdef CONFIG_STM32_TIM1 +struct stm32_tim_priv_s stm32_tim1_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM1_BASE, +}; +#endif +#ifdef CONFIG_STM32_TIM2 +struct stm32_tim_priv_s stm32_tim2_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM2_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM3 +struct stm32_tim_priv_s stm32_tim3_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM3_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM4 +struct stm32_tim_priv_s stm32_tim4_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM4_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM5 +struct stm32_tim_priv_s stm32_tim5_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM5_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM6 +struct stm32_tim_priv_s stm32_tim6_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM6_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM7 +struct stm32_tim_priv_s stm32_tim7_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM7_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM8 +struct stm32_tim_priv_s stm32_tim8_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM8_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM9 +struct stm32_tim_priv_s stm32_tim9_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM9_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM10 +struct stm32_tim_priv_s stm32_tim10_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM10_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM11 +struct stm32_tim_priv_s stm32_tim11_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM11_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM12 +struct stm32_tim_priv_s stm32_tim12_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM12_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM13 +struct stm32_tim_priv_s stm32_tim13_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM13_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM14 +struct stm32_tim_priv_s stm32_tim14_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM14_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM15 +struct stm32_tim_priv_s stm32_tim15_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM15_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM16 +struct stm32_tim_priv_s stm32_tim16_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM16_BASE, +}; +#endif + +#ifdef CONFIG_STM32_TIM17 +struct stm32_tim_priv_s stm32_tim17_priv = +{ + .ops = &stm32_tim_ops, + .mode = STM32_TIM_MODE_UNUSED, + .base = STM32_TIM17_BASE, +}; +#endif + /************************************************************************************ * Private Functions ************************************************************************************/ -/* Get a 16-bit register value by offset */ +/************************************************************************************ + * Name: stm32_getreg16 + * + * Description: + * Get a 16-bit register value by offset + * + ************************************************************************************/ static inline uint16_t stm32_getreg16(FAR struct stm32_tim_dev_s *dev, uint8_t offset) @@ -301,7 +526,13 @@ static inline uint16_t stm32_getreg16(FAR struct stm32_tim_dev_s *dev, return getreg16(((struct stm32_tim_priv_s *)dev)->base + offset); } -/* Put a 16-bit register value by offset */ +/************************************************************************************ + * Name: stm32_putreg16 + * + * Description: + * Put a 16-bit register value by offset + * + ************************************************************************************/ static inline void stm32_putreg16(FAR struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t value) @@ -309,7 +540,13 @@ static inline void stm32_putreg16(FAR struct stm32_tim_dev_s *dev, uint8_t offse putreg16(value, ((struct stm32_tim_priv_s *)dev)->base + offset); } -/* Modify a 16-bit register value by offset */ +/************************************************************************************ + * Name: stm32_modifyreg16 + * + * Description: + * Modify a 16-bit register value by offset + * + ************************************************************************************/ static inline void stm32_modifyreg16(FAR struct stm32_tim_dev_s *dev, uint8_t offset, uint16_t clearbits, @@ -318,9 +555,14 @@ static inline void stm32_modifyreg16(FAR struct stm32_tim_dev_s *dev, modifyreg16(((struct stm32_tim_priv_s *)dev)->base + offset, clearbits, setbits); } -/* Get a 32-bit register value by offset. This applies only for the STM32 F4 - * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - */ +/************************************************************************************ + * Name: stm32_getreg32 + * + * Description: + * Get a 32-bit register value by offset. This applies only for the STM32 F4 + * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. + * + ************************************************************************************/ static inline uint32_t stm32_getreg32(FAR struct stm32_tim_dev_s *dev, uint8_t offset) @@ -328,9 +570,14 @@ static inline uint32_t stm32_getreg32(FAR struct stm32_tim_dev_s *dev, return getreg32(((struct stm32_tim_priv_s *)dev)->base + offset); } -/* Put a 32-bit register value by offset. This applies only for the STM32 F4 - * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. - */ +/************************************************************************************ + * Name: stm32_putreg32 + * + * Description: + * Put a 32-bit register value by offset. This applies only for the STM32 F4 + * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. + * + ************************************************************************************/ static inline void stm32_putreg32(FAR struct stm32_tim_dev_s *dev, uint8_t offset, uint32_t value) @@ -338,6 +585,10 @@ static inline void stm32_putreg32(FAR struct stm32_tim_dev_s *dev, uint8_t offse putreg32(value, ((struct stm32_tim_priv_s *)dev)->base + offset); } +/************************************************************************************ + * Name: stm32_tim_reload_counter + ************************************************************************************/ + static void stm32_tim_reload_counter(FAR struct stm32_tim_dev_s *dev) { uint16_t val = stm32_getreg16(dev, STM32_BTIM_EGR_OFFSET); @@ -345,6 +596,10 @@ static void stm32_tim_reload_counter(FAR struct stm32_tim_dev_s *dev) stm32_putreg16(dev, STM32_BTIM_EGR_OFFSET, val); } +/************************************************************************************ + * Name: stm32_tim_enable + ************************************************************************************/ + static void stm32_tim_enable(FAR struct stm32_tim_dev_s *dev) { uint16_t val = stm32_getreg16(dev, STM32_BTIM_CR1_OFFSET); @@ -353,6 +608,10 @@ static void stm32_tim_enable(FAR struct stm32_tim_dev_s *dev) stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val); } +/************************************************************************************ + * Name: stm32_tim_disable + ************************************************************************************/ + static void stm32_tim_disable(FAR struct stm32_tim_dev_s *dev) { uint16_t val = stm32_getreg16(dev, STM32_BTIM_CR1_OFFSET); @@ -360,7 +619,13 @@ static void stm32_tim_disable(FAR struct stm32_tim_dev_s *dev) stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val); } -/* Reset timer into system default state, but do not affect output/input pins */ +/************************************************************************************ + * Name: stm32_tim_reset + * + * Description: + * Reset timer into system default state, but do not affect output/input pins + * + ************************************************************************************/ static void stm32_tim_reset(FAR struct stm32_tim_dev_s *dev) { @@ -368,6 +633,10 @@ static void stm32_tim_reset(FAR struct stm32_tim_dev_s *dev) stm32_tim_disable(dev); } +/************************************************************************************ + * Name: stm32_tim_gpioconfig + ************************************************************************************/ + #if defined(HAVE_TIM1_GPIOCONFIG)||defined(HAVE_TIM2_GPIOCONFIG)||\ defined(HAVE_TIM3_GPIOCONFIG)||defined(HAVE_TIM4_GPIOCONFIG)||\ defined(HAVE_TIM5_GPIOCONFIG)||defined(HAVE_TIM8_GPIOCONFIG) @@ -387,7 +656,77 @@ static void stm32_tim_gpioconfig(uint32_t cfg, stm32_tim_channel_t mode) #endif /************************************************************************************ - * Basic Functions + * Name: stm32_tim_setmode + ************************************************************************************/ + +static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode) +{ + uint16_t val = ATIM_CR1_CEN | ATIM_CR1_ARPE; + + DEBUGASSERT(dev != NULL); + + /* This function is not supported on basic timers. To enable or + * disable it, simply set its clock to valid frequency or zero. + */ + +#if STM32_NBTIM > 0 + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE +#endif +#if STM32_NBTIM > 1 + || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE +#endif +#if STM32_NBTIM > 0 + ) + { + return -EINVAL; + } +#endif + + /* Decode operational modes */ + + switch (mode & STM32_TIM_MODE_MASK) + { + case STM32_TIM_MODE_DISABLED: + val = 0; + break; + + case STM32_TIM_MODE_DOWN: + val |= ATIM_CR1_DIR; + + case STM32_TIM_MODE_UP: + break; + + case STM32_TIM_MODE_UPDOWN: + val |= ATIM_CR1_CENTER1; + // Our default: Interrupts are generated on compare, when counting down + break; + + case STM32_TIM_MODE_PULSE: + val |= ATIM_CR1_OPM; + break; + + default: + return -EINVAL; + } + + stm32_tim_reload_counter(dev); + stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val); + +#if STM32_NATIM > 0 + /* Advanced registers require Main Output Enable */ + + if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || + ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) + { + stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + } +#endif + + return OK; +} + +/************************************************************************************ + * Name: stm32_tim_setclock ************************************************************************************/ static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq) @@ -531,6 +870,10 @@ static int stm32_tim_setclock(FAR struct stm32_tim_dev_s *dev, uint32_t freq) return prescaler; } +/************************************************************************************ + * Name: stm32_tim_setperiod + ************************************************************************************/ + static void stm32_tim_setperiod(FAR struct stm32_tim_dev_s *dev, uint32_t period) { @@ -538,217 +881,20 @@ static void stm32_tim_setperiod(FAR struct stm32_tim_dev_s *dev, stm32_putreg32(dev, STM32_BTIM_ARR_OFFSET, period); } -static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, - int (*handler)(int irq, void *context), - int source) -{ - int vectorno; - - DEBUGASSERT(dev != NULL); - DEBUGASSERT(source == 0); - - switch (((struct stm32_tim_priv_s *)dev)->base) - { -#ifdef CONFIG_STM32_TIM1 - case STM32_TIM1_BASE: - vectorno = STM32_IRQ_TIM1UP; - break; -#endif -#ifdef CONFIG_STM32_TIM2 - case STM32_TIM2_BASE: - vectorno = STM32_IRQ_TIM2; - break; -#endif -#ifdef CONFIG_STM32_TIM3 - case STM32_TIM3_BASE: - vectorno = STM32_IRQ_TIM3; - break; -#endif -#ifdef CONFIG_STM32_TIM4 - case STM32_TIM4_BASE: - vectorno = STM32_IRQ_TIM4; - break; -#endif -#ifdef CONFIG_STM32_TIM5 - case STM32_TIM5_BASE: - vectorno = STM32_IRQ_TIM5; - break; -#endif -#ifdef CONFIG_STM32_TIM6 - case STM32_TIM6_BASE: - vectorno = STM32_IRQ_TIM6; - break; -#endif -#ifdef CONFIG_STM32_TIM7 - case STM32_TIM7_BASE: - vectorno = STM32_IRQ_TIM7; - break; -#endif -#ifdef CONFIG_STM32_TIM8 - case STM32_TIM8_BASE: - vectorno = STM32_IRQ_TIM8UP; - break; -#endif -#ifdef CONFIG_STM32_TIM9 - case STM32_TIM9_BASE: - vectorno = STM32_IRQ_TIM9; - break; -#endif -#ifdef CONFIG_STM32_TIM10 - case STM32_TIM10_BASE: - vectorno = STM32_IRQ_TIM10; - break; -#endif -#ifdef CONFIG_STM32_TIM11 - case STM32_TIM11_BASE: - vectorno = STM32_IRQ_TIM11; - break; -#endif -#ifdef CONFIG_STM32_TIM12 - case STM32_TIM12_BASE: - vectorno = STM32_IRQ_TIM12; - break; -#endif -#ifdef CONFIG_STM32_TIM13 - case STM32_TIM13_BASE: - vectorno = STM32_IRQ_TIM13; - break; -#endif -#ifdef CONFIG_STM32_TIM14 - case STM32_TIM14_BASE: - vectorno = STM32_IRQ_TIM14; - break; -#endif -#ifdef CONFIG_STM32_TIM15 - case STM32_TIM15_BASE: - vectorno = STM32_IRQ_TIM15; - break; -#endif -#ifdef CONFIG_STM32_TIM16 - case STM32_TIM16_BASE: - vectorno = STM32_IRQ_TIM16; - break; -#endif -#ifdef CONFIG_STM32_TIM17 - case STM32_TIM17_BASE: - vectorno = STM32_IRQ_TIM17; - break; -#endif - - default: - return -EINVAL; - } - - /* Disable interrupt when callback is removed */ - - if (!handler) - { - up_disable_irq(vectorno); - irq_detach(vectorno); - return OK; - } - - /* Otherwise set callback and enable interrupt */ - - irq_attach(vectorno, handler); - up_enable_irq(vectorno); - -#ifdef CONFIG_ARCH_IRQPRIO - /* Set the interrupt priority */ - - up_prioritize_irq(vectorno, NVIC_SYSH_PRIORITY_DEFAULT); -#endif - - return OK; -} - -static void stm32_tim_enableint(FAR struct stm32_tim_dev_s *dev, int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, 0, ATIM_DIER_UIE); -} - -static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev, int source) -{ - DEBUGASSERT(dev != NULL); - stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, ATIM_DIER_UIE, 0); -} - -static void stm32_tim_ackint(FAR struct stm32_tim_dev_s *dev, int source) -{ - stm32_putreg16(dev, STM32_BTIM_SR_OFFSET, ~ATIM_SR_UIF); -} - /************************************************************************************ - * General Functions + * Name: stm32_tim_getcounter ************************************************************************************/ -static int stm32_tim_setmode(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode) +static uint32_t stm32_tim_getcounter(FAR struct stm32_tim_dev_s *dev) { - uint16_t val = ATIM_CR1_CEN | ATIM_CR1_ARPE; - DEBUGASSERT(dev != NULL); - - /* This function is not supported on basic timers. To enable or - * disable it, simply set its clock to valid frequency or zero. - */ - -#if STM32_NBTIM > 0 - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM6_BASE -#endif -#if STM32_NBTIM > 1 - || ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM7_BASE -#endif -#if STM32_NBTIM > 0 - ) - { - return -EINVAL; - } -#endif - - /* Decode operational modes */ - - switch (mode & STM32_TIM_MODE_MASK) - { - case STM32_TIM_MODE_DISABLED: - val = 0; - break; - - case STM32_TIM_MODE_DOWN: - val |= ATIM_CR1_DIR; - - case STM32_TIM_MODE_UP: - break; - - case STM32_TIM_MODE_UPDOWN: - val |= ATIM_CR1_CENTER1; - // Our default: Interrupts are generated on compare, when counting down - break; - - case STM32_TIM_MODE_PULSE: - val |= ATIM_CR1_OPM; - break; - - default: - return -EINVAL; - } - - stm32_tim_reload_counter(dev); - stm32_putreg16(dev, STM32_BTIM_CR1_OFFSET, val); - -#if STM32_NATIM > 0 - /* Advanced registers require Main Output Enable */ - - if (((struct stm32_tim_priv_s *)dev)->base == STM32_TIM1_BASE || - ((struct stm32_tim_priv_s *)dev)->base == STM32_TIM8_BASE) - { - stm32_modifyreg16(dev, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); - } -#endif - - return OK; + return stm32_getreg32(dev, STM32_BTIM_CNT_OFFSET); } +/************************************************************************************ + * Name: stm32_tim_setchannel + ************************************************************************************/ + static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel, stm32_tim_channel_t mode) { @@ -1268,6 +1414,10 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel return OK; } +/************************************************************************************ + * Name: stm32_tim_setcompare + ************************************************************************************/ + static int stm32_tim_setcompare(FAR struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare) { @@ -1293,6 +1443,10 @@ static int stm32_tim_setcompare(FAR struct stm32_tim_dev_s *dev, uint8_t channel return OK; } +/************************************************************************************ + * Name: stm32_tim_getcapture + ************************************************************************************/ + static int stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev, uint8_t channel) { DEBUGASSERT(dev != NULL); @@ -1313,183 +1467,178 @@ static int stm32_tim_getcapture(FAR struct stm32_tim_dev_s *dev, uint8_t channel } /************************************************************************************ - * Advanced Functions + * Name: stm32_tim_setisr ************************************************************************************/ -/* TODO: Advanced functions for the STM32_ATIM */ - -/************************************************************************************ - * Device Structures, Instantiation - ************************************************************************************/ - -struct stm32_tim_ops_s stm32_tim_ops = +static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev, + int (*handler)(int irq, void *context), + int source) { - .setmode = &stm32_tim_setmode, - .setclock = &stm32_tim_setclock, - .setperiod = &stm32_tim_setperiod, - .setchannel = &stm32_tim_setchannel, - .setcompare = &stm32_tim_setcompare, - .getcapture = &stm32_tim_getcapture, - .setisr = &stm32_tim_setisr, - .enableint = &stm32_tim_enableint, - .disableint = &stm32_tim_disableint, - .ackint = &stm32_tim_ackint -}; + int vectorno; + + DEBUGASSERT(dev != NULL); + DEBUGASSERT(source == 0); + switch (((struct stm32_tim_priv_s *)dev)->base) + { #ifdef CONFIG_STM32_TIM1 -struct stm32_tim_priv_s stm32_tim1_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM1_BASE, -}; + case STM32_TIM1_BASE: + vectorno = STM32_IRQ_TIM1UP; + break; #endif #ifdef CONFIG_STM32_TIM2 -struct stm32_tim_priv_s stm32_tim2_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM2_BASE, -}; + case STM32_TIM2_BASE: + vectorno = STM32_IRQ_TIM2; + break; #endif - #ifdef CONFIG_STM32_TIM3 -struct stm32_tim_priv_s stm32_tim3_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM3_BASE, -}; + case STM32_TIM3_BASE: + vectorno = STM32_IRQ_TIM3; + break; #endif - #ifdef CONFIG_STM32_TIM4 -struct stm32_tim_priv_s stm32_tim4_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM4_BASE, -}; + case STM32_TIM4_BASE: + vectorno = STM32_IRQ_TIM4; + break; #endif - #ifdef CONFIG_STM32_TIM5 -struct stm32_tim_priv_s stm32_tim5_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM5_BASE, -}; + case STM32_TIM5_BASE: + vectorno = STM32_IRQ_TIM5; + break; #endif - #ifdef CONFIG_STM32_TIM6 -struct stm32_tim_priv_s stm32_tim6_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM6_BASE, -}; + case STM32_TIM6_BASE: + vectorno = STM32_IRQ_TIM6; + break; #endif - #ifdef CONFIG_STM32_TIM7 -struct stm32_tim_priv_s stm32_tim7_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM7_BASE, -}; + case STM32_TIM7_BASE: + vectorno = STM32_IRQ_TIM7; + break; #endif - #ifdef CONFIG_STM32_TIM8 -struct stm32_tim_priv_s stm32_tim8_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM8_BASE, -}; + case STM32_TIM8_BASE: + vectorno = STM32_IRQ_TIM8UP; + break; #endif - #ifdef CONFIG_STM32_TIM9 -struct stm32_tim_priv_s stm32_tim9_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM9_BASE, -}; + case STM32_TIM9_BASE: + vectorno = STM32_IRQ_TIM9; + break; #endif - #ifdef CONFIG_STM32_TIM10 -struct stm32_tim_priv_s stm32_tim10_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM10_BASE, -}; + case STM32_TIM10_BASE: + vectorno = STM32_IRQ_TIM10; + break; #endif - #ifdef CONFIG_STM32_TIM11 -struct stm32_tim_priv_s stm32_tim11_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM11_BASE, -}; + case STM32_TIM11_BASE: + vectorno = STM32_IRQ_TIM11; + break; #endif - #ifdef CONFIG_STM32_TIM12 -struct stm32_tim_priv_s stm32_tim12_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM12_BASE, -}; + case STM32_TIM12_BASE: + vectorno = STM32_IRQ_TIM12; + break; #endif - #ifdef CONFIG_STM32_TIM13 -struct stm32_tim_priv_s stm32_tim13_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM13_BASE, -}; + case STM32_TIM13_BASE: + vectorno = STM32_IRQ_TIM13; + break; #endif - #ifdef CONFIG_STM32_TIM14 -struct stm32_tim_priv_s stm32_tim14_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM14_BASE, -}; + case STM32_TIM14_BASE: + vectorno = STM32_IRQ_TIM14; + break; #endif - #ifdef CONFIG_STM32_TIM15 -struct stm32_tim_priv_s stm32_tim15_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM15_BASE, -}; + case STM32_TIM15_BASE: + vectorno = STM32_IRQ_TIM15; + break; #endif - #ifdef CONFIG_STM32_TIM16 -struct stm32_tim_priv_s stm32_tim16_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM16_BASE, -}; + case STM32_TIM16_BASE: + vectorno = STM32_IRQ_TIM16; + break; #endif - #ifdef CONFIG_STM32_TIM17 -struct stm32_tim_priv_s stm32_tim17_priv = -{ - .ops = &stm32_tim_ops, - .mode = STM32_TIM_MODE_UNUSED, - .base = STM32_TIM17_BASE, -}; + case STM32_TIM17_BASE: + vectorno = STM32_IRQ_TIM17; + break; +#endif + + default: + return -EINVAL; + } + + /* Disable interrupt when callback is removed */ + + if (!handler) + { + up_disable_irq(vectorno); + irq_detach(vectorno); + return OK; + } + + /* Otherwise set callback and enable interrupt */ + + irq_attach(vectorno, handler); + up_enable_irq(vectorno); + +#ifdef CONFIG_ARCH_IRQPRIO + /* Set the interrupt priority */ + + up_prioritize_irq(vectorno, NVIC_SYSH_PRIORITY_DEFAULT); #endif + return OK; +} + +/************************************************************************************ + * Name: stm32_tim_enableint + ************************************************************************************/ + +static void stm32_tim_enableint(FAR struct stm32_tim_dev_s *dev, int source) +{ + DEBUGASSERT(dev != NULL); + stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, 0, ATIM_DIER_UIE); +} + +/************************************************************************************ + * Name: stm32_tim_disableint + ************************************************************************************/ + +static void stm32_tim_disableint(FAR struct stm32_tim_dev_s *dev, int source) +{ + DEBUGASSERT(dev != NULL); + stm32_modifyreg16(dev, STM32_BTIM_DIER_OFFSET, ATIM_DIER_UIE, 0); +} + +/************************************************************************************ + * Name: stm32_tim_ackint + ************************************************************************************/ + +static void stm32_tim_ackint(FAR struct stm32_tim_dev_s *dev, int source) +{ + stm32_putreg16(dev, STM32_BTIM_SR_OFFSET, ~ATIM_SR_UIF); +} + +/************************************************************************************ + * Name: stm32_tim_checkint + ************************************************************************************/ + +static int stm32_tim_checkint(FAR struct stm32_tim_dev_s *dev, int source) +{ + uint16_t regval = stm32_getreg16(dev, STM32_BTIM_SR_OFFSET); + return (regval & ATIM_SR_UIF) ? 1 : 0; +} + +/************************************************************************************ + * Pubic Functions + ************************************************************************************/ + /************************************************************************************ - * Public Function - Initialization + * Name: stm32_tim_init ************************************************************************************/ FAR struct stm32_tim_dev_s *stm32_tim_init(int timer) @@ -1618,7 +1767,12 @@ FAR struct stm32_tim_dev_s *stm32_tim_init(int timer) return dev; } -/* TODO: Detach interrupts, and close down all TIM Channels */ +/************************************************************************************ + * Name: stm32_tim_deinit + * + * TODO: Detach interrupts, and close down all TIM Channels + * + ************************************************************************************/ int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev) { diff --git a/arch/arm/src/stm32/stm32_tim.h b/arch/arm/src/stm32/stm32_tim.h index 2d3b01a683b71c835641b858bbed7006151e1ebe..e31250537b4727201681adfad2b368b40fa2aa45 100644 --- a/arch/arm/src/stm32/stm32_tim.h +++ b/arch/arm/src/stm32/stm32_tim.h @@ -6,7 +6,7 @@ * * With modifications and updates by: * - * Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. + * Copyright (C) 2011-2012, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -58,6 +58,7 @@ #define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode)) #define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) #define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period)) +#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d)) #define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) #define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp)) #define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) @@ -65,6 +66,7 @@ #define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s)) #define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s)) #define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) +#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s)) /************************************************************************************ * Public Types @@ -158,19 +160,24 @@ struct stm32_tim_ops_s int (*setmode)(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode); int (*setclock)(FAR struct stm32_tim_dev_s *dev, uint32_t freq); void (*setperiod)(FAR struct stm32_tim_dev_s *dev, uint32_t period); + uint32_t (*getcounter)(FAR struct stm32_tim_dev_s *dev); /* General and Advanced Timers Adds */ - int (*setchannel)(FAR struct stm32_tim_dev_s *dev, uint8_t channel, stm32_tim_channel_t mode); - int (*setcompare)(FAR struct stm32_tim_dev_s *dev, uint8_t channel, uint32_t compare); + int (*setchannel)(FAR struct stm32_tim_dev_s *dev, uint8_t channel, + stm32_tim_channel_t mode); + int (*setcompare)(FAR struct stm32_tim_dev_s *dev, uint8_t channel, + uint32_t compare); int (*getcapture)(FAR struct stm32_tim_dev_s *dev, uint8_t channel); /* Timer interrupts */ - int (*setisr)(FAR struct stm32_tim_dev_s *dev, int (*handler)(int irq, void *context), int source); + int (*setisr)(FAR struct stm32_tim_dev_s *dev, + int (*handler)(int irq, void *context), int source); void (*enableint)(FAR struct stm32_tim_dev_s *dev, int source); void (*disableint)(FAR struct stm32_tim_dev_s *dev, int source); void (*ackint)(FAR struct stm32_tim_dev_s *dev, int source); + int (*checkint)(FAR struct stm32_tim_dev_s *dev, int source); }; /************************************************************************************ diff --git a/arch/arm/src/stm32/stm32f40xxx_rtcc.c b/arch/arm/src/stm32/stm32f40xxx_rtcc.c index 0e55a4ad7dd7976f86c674028b66b8f10da74fb0..c20024d8b1a4bd2e6ea790c7031af1d6d8bd9484 100644 --- a/arch/arm/src/stm32/stm32f40xxx_rtcc.c +++ b/arch/arm/src/stm32/stm32f40xxx_rtcc.c @@ -1,4 +1,4 @@ -/************************************************************************************ +/**************************************************************************** * arch/arm/src/stm32/stm32f40xxx_rtcc.c * * Copyright (C) 2012-2016 Gregory Nutt. All rights reserved. @@ -32,11 +32,11 @@ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE * POSSIBILITY OF SUCH DAMAGE. * - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Included Files - ************************************************************************************/ + ****************************************************************************/ #include @@ -60,10 +60,11 @@ #ifdef CONFIG_RTC -/************************************************************************************ +/**************************************************************************** * Pre-processor Definitions - ************************************************************************************/ -/* Configuration ********************************************************************/ + ****************************************************************************/ + +/* Configuration ************************************************************/ /* This RTC implementation supports * - date/time RTC hardware * - extended functions Alarm A and B for STM32F4xx and onwards @@ -81,12 +82,12 @@ # error "CONFIG_STM32_PWR must selected to use this driver" #endif -/* Constants ************************************************************************/ +/* Constants ****************************************************************/ #define SYNCHRO_TIMEOUT (0x00020000) #define INITMODE_TIMEOUT (0x00010000) -/* Proxy definitions to make the same code work for all the STM32 series ************/ +/* Proxy definitions to make the same code work for all the STM32 series ****/ # define STM32_RCC_XXX STM32_RCC_BDCR # define RCC_XXX_YYYRST RCC_BDCR_BDRST @@ -101,10 +102,6 @@ #define MINUTES_IN_HOUR 60 #define HOURS_IN_DAY 24 -/* Can't exceed 24hours-2min without providing extra logic for carry over for day. */ - -#define MAX_RTC_ALARM_REL_MINUTES (24*MINUTES_IN_HOUR)-2 - #define hours_add(parm_hrs) \ time->tm_hour += parm_hrs;\ if ((HOURS_IN_DAY-1) < (time->tm_hour))\ @@ -117,9 +114,9 @@ #define RTC_ALRMR_DIS_DATE_MASK (RTC_ALRMR_MSK4) #define RTC_ALRMR_ENABLE (0) -/************************************************************************************ +/**************************************************************************** * Private Types - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_RTC_ALARM typedef unsigned int rtc_alarmreg_t; @@ -131,9 +128,9 @@ struct alm_cbinfo_s }; #endif -/************************************************************************************ +/**************************************************************************** * Private Data - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_RTC_ALARM /* Callback to use when an EXTI is activated */ @@ -141,17 +138,17 @@ struct alm_cbinfo_s static struct alm_cbinfo_s g_alarmcb[RTC_ALARM_LAST]; #endif -/************************************************************************************ +/**************************************************************************** * Public Data - ************************************************************************************/ + ****************************************************************************/ /* g_rtc_enabled is set true after the RTC has successfully initialized */ volatile bool g_rtc_enabled = false; -/************************************************************************************ +/**************************************************************************** * Private Function Prototypes - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_RTC_ALARM static int rtchw_check_alrawf(void); @@ -162,11 +159,11 @@ static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg); #endif #endif -/************************************************************************************ +/**************************************************************************** * Private Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: rtc_dumpregs * * Description: @@ -178,7 +175,7 @@ static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg); * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_RTC_INFO static void rtc_dumpregs(FAR const char *msg) @@ -215,7 +212,7 @@ static void rtc_dumpregs(FAR const char *msg) # define rtc_dumpregs(msg) #endif -/************************************************************************************ +/**************************************************************************** * Name: rtc_dumptime * * Description: @@ -227,7 +224,7 @@ static void rtc_dumpregs(FAR const char *msg) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_DEBUG_RTC_INFO static void rtc_dumptime(FAR const struct tm *tp, FAR const char *msg) @@ -244,7 +241,7 @@ static void rtc_dumptime(FAR const struct tm *tp, FAR const char *msg) # define rtc_dumptime(tp, msg) #endif -/************************************************************************************ +/**************************************************************************** * Name: rtc_wprunlock * * Description: @@ -256,7 +253,7 @@ static void rtc_dumptime(FAR const struct tm *tp, FAR const char *msg) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ static void rtc_wprunlock(void) { @@ -279,7 +276,7 @@ static void rtc_wprunlock(void) putreg32(0x53, STM32_RTC_WPR); } -/************************************************************************************ +/**************************************************************************** * Name: rtc_wprlock * * Description: @@ -291,7 +288,7 @@ static void rtc_wprunlock(void) * Returned Value: * None * - ************************************************************************************/ + ****************************************************************************/ static inline void rtc_wprlock(void) { @@ -299,14 +296,14 @@ static inline void rtc_wprlock(void) putreg32(0xff, STM32_RTC_WPR); - /* Disable write access to the backup domain (RTC registers, RTC backup data - * registers and backup SRAM). + /* Disable write access to the backup domain (RTC registers, RTC backup + * data registers and backup SRAM). */ (void)stm32_pwr_enablebkp(false); } -/************************************************************************************ +/**************************************************************************** * Name: rtc_synchwait * * Description: @@ -319,7 +316,7 @@ static inline void rtc_wprlock(void) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ static int rtc_synchwait(void) { @@ -358,7 +355,7 @@ static int rtc_synchwait(void) return ret; } -/************************************************************************************ +/**************************************************************************** * Name: rtc_enterinit * * Description: @@ -370,7 +367,7 @@ static int rtc_synchwait(void) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ static int rtc_enterinit(void) { @@ -406,7 +403,7 @@ static int rtc_enterinit(void) return ret; } -/************************************************************************************ +/**************************************************************************** * Name: rtc_exitinit * * Description: @@ -418,7 +415,7 @@ static int rtc_enterinit(void) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ static void rtc_exitinit(void) { @@ -429,7 +426,7 @@ static void rtc_exitinit(void) putreg32(regval, STM32_RTC_ISR); } -/************************************************************************************ +/**************************************************************************** * Name: rtc_bin2bcd * * Description: @@ -441,7 +438,7 @@ static void rtc_exitinit(void) * Returned Value: * The value in BCD representation * - ************************************************************************************/ + ****************************************************************************/ static uint32_t rtc_bin2bcd(int value) { @@ -456,7 +453,7 @@ static uint32_t rtc_bin2bcd(int value) return (msbcd << 4) | value; } -/************************************************************************************ +/**************************************************************************** * Name: rtc_bin2bcd * * Description: @@ -468,7 +465,7 @@ static uint32_t rtc_bin2bcd(int value) * Returned Value: * The value in binary representation * - ************************************************************************************/ + ****************************************************************************/ static int rtc_bcd2bin(uint32_t value) { @@ -476,13 +473,13 @@ static int rtc_bcd2bin(uint32_t value) return (int)(tens + (value & 0x0f)); } -/************************************************************************************ +/**************************************************************************** * Name: rtc_setup * * Description: - * Performs first time configuration of the RTC. A special value written into - * back-up register 0 will prevent this function from being called on sub-sequent - * resets or power up. + * Performs first time configuration of the RTC. A special value written + * into back-up register 0 will prevent this function from being called on + * sub-sequent resets or power up. * * Input Parameters: * None @@ -490,7 +487,7 @@ static int rtc_bcd2bin(uint32_t value) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ static int rtc_setup(void) { @@ -544,12 +541,12 @@ static int rtc_setup(void) return ret; } -/************************************************************************************ +/**************************************************************************** * Name: rtc_resume * * Description: - * Called when the RTC was already initialized on a previous power cycle. This - * just brings the RTC back into full operation. + * Called when the RTC was already initialized on a previous power cycle. + * This just brings the RTC back into full operation. * * Input Parameters: * None @@ -557,7 +554,7 @@ static int rtc_setup(void) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ static void rtc_resume(void) { @@ -576,7 +573,7 @@ static void rtc_resume(void) #endif } -/************************************************************************************ +/**************************************************************************** * Name: stm32_rtc_alarm_handler * * Description: @@ -589,7 +586,7 @@ static void rtc_resume(void) * Returned Value: * Zero (OK) on success; A negated errno value on failure. * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_RTC_ALARM static int stm32_rtc_alarm_handler(int irq, void *context) @@ -659,7 +656,7 @@ static int stm32_rtc_alarm_handler(int irq, void *context) } #endif -/************************************************************************************ +/**************************************************************************** * Name: rtchw_check_alrXwf X= a or B * * Description: @@ -671,7 +668,7 @@ static int stm32_rtc_alarm_handler(int irq, void *context) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_RTC_ALARM static int rtchw_check_alrawf(void) @@ -725,12 +722,12 @@ static int rtchw_check_alrbwf(void) } #endif -/************************************************************************************ +/**************************************************************************** * Name: stm32_rtchw_set_alrmXr X is a or b * * Description: - * Set the alarm (A or B) hardware registers, using the required hardware access - * protocol + * Set the alarm (A or B) hardware registers, using the required hardware + * access protocol * * Input Parameters: * alarmreg - the register @@ -738,7 +735,7 @@ static int rtchw_check_alrbwf(void) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_RTC_ALARM static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg) @@ -814,16 +811,16 @@ rtchw_set_alrmbr_exit: } #endif -/************************************************************************************ +/**************************************************************************** * Public Functions - ************************************************************************************/ + ****************************************************************************/ -/************************************************************************************ +/**************************************************************************** * Name: up_rtc_initialize * * Description: - * Initialize the hardware RTC per the selected configuration. This function is - * called once during the OS initialization sequence + * Initialize the hardware RTC per the selected configuration. This + * function is called once during the OS initialization sequence * * Input Parameters: * None @@ -831,7 +828,7 @@ rtchw_set_alrmbr_exit: * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ int up_rtc_initialize(void) { @@ -843,9 +840,9 @@ int up_rtc_initialize(void) int nretry = 0; /* Clocking for the PWR block must be provided. However, this is done - * unconditionally in stm32f40xxx_rcc.c on power up. This done unconditionally - * because the PWR block is also needed to set the internal voltage regulator for - * maximum performance. + * unconditionally in stm32f40xxx_rcc.c on power up. This done + * unconditionally because the PWR block is also needed to set the + * internal voltage regulator for maximum performance. */ /* Select the clock source */ @@ -857,9 +854,9 @@ int up_rtc_initialize(void) if (regval != RTC_MAGIC) { - /* Some boards do not have the external 32khz oscillator installed, for those - * boards we must fallback to the crummy internal RC clock or the external high - * rate clock + /* Some boards do not have the external 32khz oscillator installed, + * for those boards we must fallback to the crummy internal RC clock + * or the external high rate clock */ #ifdef CONFIG_RTC_HSECLOCK @@ -942,8 +939,8 @@ int up_rtc_initialize(void) do { - /* Wait for the RTC Time and Date registers to be synchronized with RTC APB - * clock. + /* Wait for the RTC Time and Date registers to be synchronized with RTC + * APB clock. */ ret = rtc_synchwait(); @@ -1014,12 +1011,12 @@ int up_rtc_initialize(void) } #ifdef CONFIG_RTC_ALARM - /* Configure RTC interrupt to catch alarm interrupts. All RTC interrupts are - * connected to the EXTI controller. To enable the RTC Alarm interrupt, the - * following sequence is required: + /* Configure RTC interrupt to catch alarm interrupts. All RTC interrupts + * are connected to the EXTI controller. To enable the RTC Alarm + * interrupt, the following sequence is required: * - * 1. Configure and enable the EXTI Line 17 RTC ALARM in interrupt mode and select the - * rising edge sensitivity. + * 1. Configure and enable the EXTI Line 17 RTC ALARM in interrupt mode + * and select the rising edge sensitivity. * For STM32F4xx * EXTI line 21 RTC Tamper & Timestamp * EXTI line 22 RTC Wakeup @@ -1037,18 +1034,18 @@ int up_rtc_initialize(void) return OK; } -/************************************************************************************ +/**************************************************************************** * Name: stm32_rtc_getdatetime_with_subseconds * * Description: * Get the current date and time from the date/time RTC. This interface * is only supported by the date/time RTC hardware implementation. - * It is used to replace the system timer. It is only used by the RTOS during - * initialization to set up the system time when CONFIG_RTC and CONFIG_RTC_DATETIME - * are selected (and CONFIG_RTC_HIRES is not). + * It is used to replace the system timer. It is only used by the RTOS + * during initialization to set up the system time when CONFIG_RTC and + * CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not). * - * NOTE: Some date/time RTC hardware is capability of sub-second accuracy. That - * sub-second accuracy is returned through 'nsec'. + * NOTE: Some date/time RTC hardware is capability of sub-second accuracy. + * That sub-second accuracy is returned through 'nsec'. * * Input Parameters: * tp - The location to return the high resolution time value. @@ -1057,7 +1054,7 @@ int up_rtc_initialize(void) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS int stm32_rtc_getdatetime_with_subseconds(FAR struct tm *tp, FAR long *nsec) @@ -1072,9 +1069,9 @@ int up_rtc_getdatetime(FAR struct tm *tp) uint32_t tr; uint32_t tmp; - /* Sample the data time registers. There is a race condition here... If we sample - * the time just before midnight on December 31, the date could be wrong because - * the day rolled over while were sampling. + /* Sample the data time registers. There is a race condition here... If + * we sample the time just before midnight on December 31, the date could + * be wrong because the day rolled over while were sampling. */ do @@ -1158,20 +1155,20 @@ int up_rtc_getdatetime(FAR struct tm *tp) return OK; } -/************************************************************************************ +/**************************************************************************** * Name: up_rtc_getdatetime * * Description: * Get the current date and time from the date/time RTC. This interface * is only supported by the date/time RTC hardware implementation. - * It is used to replace the system timer. It is only used by the RTOS during - * initialization to set up the system time when CONFIG_RTC and CONFIG_RTC_DATETIME - * are selected (and CONFIG_RTC_HIRES is not). + * It is used to replace the system timer. It is only used by the RTOS + * during initialization to set up the system time when CONFIG_RTC and + * CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not). * - * NOTE: Some date/time RTC hardware is capability of sub-second accuracy. That - * sub-second accuracy is lost in this interface. However, since the system time - * is reinitialized on each power-up/reset, there will be no timing inaccuracy in - * the long run. + * NOTE: Some date/time RTC hardware is capability of sub-second accuracy. + * That sub-second accuracy is lost in this interface. However, since the + * system time is reinitialized on each power-up/reset, there will be no + * timing inaccuracy in the long run. * * Input Parameters: * tp - The location to return the high resolution time value. @@ -1179,7 +1176,7 @@ int up_rtc_getdatetime(FAR struct tm *tp) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS int up_rtc_getdatetime(FAR struct tm *tp) @@ -1188,13 +1185,13 @@ int up_rtc_getdatetime(FAR struct tm *tp) } #endif -/************************************************************************************ +/**************************************************************************** * Name: stm32_rtc_setdatetime * * Description: * Set the RTC to the provided time. RTC implementations which provide - * up_rtc_getdatetime() (CONFIG_RTC_DATETIME is selected) should provide this - * function. + * up_rtc_getdatetime() (CONFIG_RTC_DATETIME is selected) should provide + * this function. * * Input Parameters: * tp - the time to use @@ -1202,7 +1199,7 @@ int up_rtc_getdatetime(FAR struct tm *tp) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ int stm32_rtc_setdatetime(FAR const struct tm *tp) { @@ -1223,11 +1220,14 @@ int stm32_rtc_setdatetime(FAR const struct tm *tp) (rtc_bin2bcd(tp->tm_min) << RTC_TR_MNU_SHIFT) | (rtc_bin2bcd(tp->tm_hour) << RTC_TR_HU_SHIFT); - /* Now convert the fields in struct tm format to the RTC date register fields: - * Days: 1-31 match in both cases. - * Month: STM32 is 1-12, struct tm is 0-11. - * Years: STM32 is 00-99, struct tm is years since 1900. - * WeekDay: STM32 is 1 = Mon - 7 = Sun + /* Now convert the fields in struct tm format to the RTC date register + * fields: + * + * Days: 1-31 match in both cases. + * Month: STM32 is 1-12, struct tm is 0-11. + * Years: STM32 is 00-99, struct tm is years since 1900. + * WeekDay: STM32 is 1 = Mon - 7 = Sun + * * Issue: I am not sure what the STM32 years mean. Are these the * years 2000-2099? I'll assume so. */ @@ -1270,12 +1270,12 @@ int stm32_rtc_setdatetime(FAR const struct tm *tp) return ret; } -/************************************************************************************ +/**************************************************************************** * Name: up_rtc_settime * * Description: - * Set the RTC to the provided time. All RTC implementations must be able to - * set their time based on a standard timespec. + * Set the RTC to the provided time. All RTC implementations must be able + * to set their time based on a standard timespec. * * Input Parameters: * tp - the time to use @@ -1283,13 +1283,15 @@ int stm32_rtc_setdatetime(FAR const struct tm *tp) * Returned Value: * Zero (OK) on success; a negated errno on failure * - ************************************************************************************/ + ****************************************************************************/ int up_rtc_settime(FAR const struct timespec *tp) { FAR struct tm newtime; - /* Break out the time values (not that the time is set only to units of seconds) */ + /* Break out the time values (not that the time is set only to units of + * seconds) + */ (void)gmtime_r(&tp->tv_sec, &newtime); return stm32_rtc_setdatetime(&newtime); diff --git a/arch/arm/src/stm32f7/Kconfig b/arch/arm/src/stm32f7/Kconfig index 0f2f65f84a2a973aa45634b99ccf7f66359525e5..75dd21454b4319ab8d0f6448bbefba0d8b9349f0 100644 --- a/arch/arm/src/stm32f7/Kconfig +++ b/arch/arm/src/stm32f7/Kconfig @@ -1195,6 +1195,10 @@ config STM32F7_QUADSPI bool "QuadSPI" default n +config STM32F7_PWR + bool "PWR" + default n + config STM32F7_RNG bool "RNG" default n @@ -1215,12 +1219,16 @@ config STM32F7_SDMMC1 bool "SDMMC1" default n select ARCH_HAVE_SDIO + select ARCH_HAVE_SDIOWAIT_WRCOMPLETE + select SDIO_PREFLIGHT config STM32F7_SDMMC2 bool "SDMMC2" default n depends on STM32F7_HAVE_SDMMC2 select ARCH_HAVE_SDIO + select ARCH_HAVE_SDIOWAIT_WRCOMPLETE + select SDIO_PREFLIGHT config STM32F7_SPDIFRX bool "SPDIFRX" @@ -1710,12 +1718,157 @@ config STM32F7_I2C_DUTY16_9 endmenu # "I2C Configuration" +config STM32F7_SDMMC_XFRDEBUG + bool "SDMMC transfer debug" + depends on DEBUG_FS_INFO && (STM32F7_SDMMC1 || STM32F7_SDMMC2) + default n + ---help--- + Enable special debug instrumentation analyze SDMMC data transfers. + This logic is as non-invasive as possible: It samples SDMMC + registers at key points in the data transfer and then dumps all of + the registers at the end of the transfer. If DEBUG_DMA is also + enabled, then DMA register will be collected as well. Requires also + DEBUG_FS and CONFIG_DEBUG_INFO. + +menu "SDMMC1 Configuration" + depends on STM32F7_SDMMC1 + +config SDMMC1_DMA + bool "Support DMA data transfers on SDMMC1" + default y if STM32F7_DMA2 + depends on STM32F7_DMA2 + ---help--- + Support DMA data transfers on SDMMC1. Requires STM32F7_SDMMC1 and config STM32F7_DMA2. + +config SDMMC1_PRI + hex "SDMMC1 interrupt priority" + default 128 + depends on ARCH_IRQPRIO && EXPERIMENTAL + ---help--- + Select SDMMC1 interrupt priority. Default: 128. + +config SDMMC1_DMAPRIO + hex "SDMMC1 DMA priority" + default 0x00010000 + ---help--- + Select SDMMC1 DMA prority. + + Options are: 0x00000000 low, 0x00010000 medium, + 0x00020000 high, 0x00030000 very high. Default: medium. + +config SDMMC1_WIDTH_D1_ONLY + bool "Use D1 only on SDMMC1" + default n + ---help--- + Select 1-bit transfer mode. Default: 4-bit transfer mode. + +endmenu # "SDMMC1 Configuration" + +menu "SDMMC2 Configuration" + depends on STM32F7_SDMMC2 + +config SDMMC2_DMA + bool "Support DMA data transfers on SDMMC2" + default y if STM32F7_DMA2 + depends on STM32F7_DMA2 + ---help--- + Support DMA data transfers on SDMMC2. Requires STM32F7_SDMMC2 and config STM32F7_DMA2. + +config SDMMC2_PRI + hex "SDMMC2 interrupt priority" + default 128 + depends on ARCH_IRQPRIO && EXPERIMENTAL + ---help--- + Select SDMMC2 interrupt priority. Default: 128. + +config SDMMC2_DMAPRIO + hex "SDMMC2 DMA priority" + default 0x00010000 + ---help--- + Select SDMMC1 DMA prority. + + Options are: 0x00000000 low, 0x00010000 medium, + 0x00020000 high, 0x00030000 very high. Default: medium. + +config SDMMC2_WIDTH_D1_ONLY + bool "Use D1 only on SDMMC2" + default n + ---help--- + Select 1-bit transfer mode. Default: 4-bit transfer mode. + +endmenu # "SDMMC2 Configuration" + +if STM32F7_BKPSRAM + +config STM32F7_BBSRAM + bool "BBSRAM File Support" + default n + +config STM32F7_BBSRAM_FILES + int "Max Files to support in BBSRAM" + default 4 + +config STM32F7_SAVE_CRASHDUMP + bool "Enable Saving Panic to BBSRAM" + default n + +endif # STM32F7_BKPSRAM + +config STM32F7_HAVE_RTC_COUNTER + bool + default n + +config STM32F7_HAVE_RTC_SUBSECONDS + bool + default n + +config RTC_MAGIC_REG + int "The BKP register used to store/check the Magic value to determine if RTC is set already" + default 0 + range 0 31 + depends on RTC && !STM32F7_HAVE_RTC_COUNTER + +config RTC_MAGIC + hex "Value used as Magic to determine if RTC is set already" + default 0xfacefeee + depends on RTC && !STM32F7_HAVE_RTC_COUNTER + +choice + prompt "RTC clock source" + default STM32F7_RTC_LSECLOCK + depends on RTC + +config STM32F7_RTC_HSECLOCK + bool "HSE clock" + ---help--- + Drive the RTC with the HSE clock, divided down to 1MHz. + +config STM32F7_RTC_LSECLOCK + bool "LSE clock" + ---help--- + Drive the RTC with the LSE clock + +config STM32F7_RTC_LSICLOCK + bool "LSI clock" + ---help--- + Drive the RTC with the LSI clock + +endchoice #"RTC clock source" + config STM32F7_CUSTOM_CLOCKCONFIG bool "Custom clock configuration" default n ---help--- Enables special, board-specific STM32 clock configuration. +config STM32F7_DTCMEXCLUDE + bool "Exclude DTCM SRAM from the heap" + default y if ELF + depends on ARMV7M_HAVE_DTCM + ---help--- + Exclude DTCM SRAM from the HEAP because it appears to be impossible + to execute ELF modules from DTCM RAM (REVISIT!). + config STM32F7_DTCM_PROCFS bool "DTCM SRAM PROCFS support" default n @@ -3364,222 +3517,10 @@ endif # !STM32F7_PWM_MULTICHAN endif # STM32F7_TIM14_PWM -config STM32F7_TIM15_PWM - bool "TIM15 PWM" - default n - depends on STM32F7_TIM15 - ---help--- - Reserve timer 15 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM15 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM15_PWM - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM15_CHANNEL1 - bool "TIM15 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM15_CHANNEL1 - -config STM32F7_TIM15_CH1MODE - int "TIM15 Channel 1 Mode" - default 0 - range 0 3 if STM32F7_STM32F30XX - range 0 1 if !STM32F7_STM32F30XX - ---help--- - Specifies the channel mode. - -config STM32F7_TIM15_CH1OUT - bool "TIM15 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM15_CHANNEL1 - -config STM32F7_TIM15_CHANNEL2 - bool "TIM15 Channel 2" - default n - ---help--- - Enables channel 2. - -if STM32F7_TIM15_CHANNEL2 - -config STM32F7_TIM15_CH2MODE - int "TIM15 Channel 2 Mode" - default 0 - range 0 3 if STM32F7_STM32F30XX - range 0 1 if !STM32F7_STM32F30XX - ---help--- - Specifies the channel mode. - -config STM32F7_TIM15_CH2OUT - bool "TIM15 Channel 2 Output" - default n - ---help--- - Enables channel 2 output. - -endif # STM32F7_TIM15_CHANNEL2 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM15_CHANNEL - int "TIM15 PWM Output Channel" - default 1 - range 1 2 - ---help--- - If TIM15 is enabled for PWM usage, you also need specifies the timer output - channel {1,2} - -config STM32F7_TIM15_CHMODE - int "TIM15 Channel Mode" - default 0 - range 0 3 if STM32F7_STM32F30XX - range 0 1 if !STM32F7_STM32F30XX - ---help--- - Specifies the channel mode. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM15_PWM - -config STM32F7_TIM16_PWM - bool "TIM16 PWM" - default n - depends on STM32F7_TIM16 - ---help--- - Reserve timer 16 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM16 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM16_PWM - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM16_CHANNEL1 - bool "TIM16 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM16_CHANNEL1 - -config STM32F7_TIM16_CH1MODE - int "TIM16 Channel 1 Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -config STM32F7_TIM16_CH1OUT - bool "TIM16 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM16_CHANNEL1 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM16_CHANNEL - int "TIM16 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM16 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32F7_TIM16_CHMODE - int "TIM16 Channel Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM16_PWM - -config STM32F7_TIM17_PWM - bool "TIM17 PWM" - default n - depends on STM32F7_TIM17 - ---help--- - Reserve timer 17 for use by PWM - - Timer devices may be used for different purposes. One special purpose is - to generate modulated outputs for such things as motor control. If STM32F7_TIM17 - is defined then THIS following may also be defined to indicate that - the timer is intended to be used for pulsed output modulation. - -if STM32F7_TIM17_PWM - -if STM32F7_PWM_MULTICHAN - -config STM32F7_TIM17_CHANNEL1 - bool "TIM17 Channel 1" - default n - ---help--- - Enables channel 1. - -if STM32F7_TIM17_CHANNEL1 - -config STM32F7_TIM17_CH1MODE - int "TIM17 Channel 1 Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -config STM32F7_TIM17_CH1OUT - bool "TIM17 Channel 1 Output" - default n - ---help--- - Enables channel 1 output. - -endif # STM32F7_TIM17_CHANNEL1 - -endif # STM32F7_PWM_MULTICHAN - -if !STM32F7_PWM_MULTICHAN - -config STM32F7_TIM17_CHANNEL - int "TIM17 PWM Output Channel" - default 1 - range 1 1 - ---help--- - If TIM17 is enabled for PWM usage, you also need specifies the timer output - channel {1} - -config STM32F7_TIM17_CHMODE - int "TIM17 Channel Mode" - default 0 - range 0 1 - ---help--- - Specifies the channel mode. - -endif # !STM32F7_PWM_MULTICHAN - -endif # STM32F7_TIM17_PWM - config STM32F7_PWM_MULTICHAN bool "PWM Multiple Output Channels" default n - depends on STM32F7_TIM1_PWM || STM32F7_TIM2_PWM || STM32F7_TIM3_PWM || STM32F7_TIM4_PWM || STM32F7_TIM5_PWM || STM32F7_TIM8_PWM || STM32F7_TIM9_PWM || STM32F7_TIM10_PWM || STM32F7_TIM11_PWM || STM32F7_TIM12_PWM || STM32F7_TIM13_PWM || STM32F7_TIM14_PWM || STM32F7_TIM15_PWM || STM32F7_TIM16_PWM || STM32F7_TIM17_PWM + depends on STM32F7_TIM1_PWM || STM32F7_TIM2_PWM || STM32F7_TIM3_PWM || STM32F7_TIM4_PWM || STM32F7_TIM5_PWM || STM32F7_TIM8_PWM || STM32F7_TIM9_PWM || STM32F7_TIM10_PWM || STM32F7_TIM11_PWM || STM32F7_TIM12_PWM || STM32F7_TIM13_PWM || STM32F7_TIM14_PWM select ARCH_HAVE_PWM_MULTICHAN ---help--- Specifies that the PWM driver supports multiple output diff --git a/arch/arm/src/stm32f7/Make.defs b/arch/arm/src/stm32f7/Make.defs index ba56b9aea41eb1736cdab5f69378f1b21f02d49a..ee6b3e0687e7ee026cd25428c71c721b9cce0aab 100644 --- a/arch/arm/src/stm32f7/Make.defs +++ b/arch/arm/src/stm32f7/Make.defs @@ -135,8 +135,22 @@ ifeq ($(CONFIG_STM32F7_DMA),y) CHIP_CSRCS += stm32_dma.c endif -ifeq ($(CONFIG_STM32_PWR),y) -CHIP_CSRCS += stm32_exti_pwr.c +ifeq ($(CONFIG_STM32F7_PWR),y) +CHIP_CSRCS += stm32_pwr.c stm32_exti_pwr.c +endif + +ifeq ($(CONFIG_RTC),y) +CHIP_CSRCS += stm32_rtc.c +ifeq ($(CONFIG_RTC_ALARM),y) +CHIP_CSRCS += stm32_exti_alarm.c +endif +ifeq ($(CONFIG_RTC_DRIVER),y) +CHIP_CSRCS += stm32_rtc_lowerhalf.c +endif +endif + +ifeq ($(filter y,$(CONFIG_STM32F7_IWDG) $(CONFIG_STM32F7_RTC_LSICLOCK)),y) +CHIP_CSRCS += stm32_lsi.c endif ifeq ($(CONFIG_STM32F7_I2C),y) @@ -151,6 +165,14 @@ ifeq ($(CONFIG_STM32F7_SDMMC1),y) CHIP_CSRCS += stm32_sdmmc.c endif +ifeq ($(CONFIG_USBDEV),y) +CHIP_CSRCS += stm32_otgdev.c +endif + +ifeq ($(CONFIG_USBHOST),y) +CHIP_CSRCS += stm32_otghost.c +endif + ifeq ($(CONFIG_STM32F7_TIM),y) CHIP_CSRCS += stm32_tim.c endif @@ -172,3 +194,7 @@ endif ifeq ($(CONFIG_DEBUG_FEATURES),y) CHIP_CSRCS += stm32_dumpgpio.c endif + +ifeq ($(CONFIG_STM32F7_BBSRAM),y) +CHIP_CSRCS += stm32_bbsram.c +endif diff --git a/arch/arm/src/stm32f7/chip/stm32_dbgmcu.h b/arch/arm/src/stm32f7/chip/stm32_dbgmcu.h new file mode 100644 index 0000000000000000000000000000000000000000..73fcd64dccb157d3efd0db9e13ffaf37c05327ae --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32_dbgmcu.h @@ -0,0 +1,55 @@ +/**************************************************************************** + * arch/arm/src/stm32f7/chip/stm32_dbgmcu.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_DBGMCU_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_DBGMCU_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "chip.h" + +#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +# include "chip/stm32f74xx75xx_dbgmcu.h" +#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +# include "chip/stm32f76xx77xx_dbgmcu.h" +#else +# error "Unsupported STM32 F7 part" +#endif + +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_DBGMCU_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32_otg.h b/arch/arm/src/stm32f7/chip/stm32_otg.h new file mode 100644 index 0000000000000000000000000000000000000000..874dd2656397497af2fb810dc06795ab42e48dde --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32_otg.h @@ -0,0 +1,874 @@ +/**************************************************************************************************** + * arch/arm/src/stm32f7/chip/stm32f_otg.h + * + * Copyright (C) 2012, 2014-2016 Gregory Nutt. All rights reserved. + * Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved. + * Author: Gregory Nutt + * Paul Alexander Patience + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_OTG_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_OTG_H + +/**************************************************************************************************** + * Included Files + ****************************************************************************************************/ +/**************************************************************************************************** + * Pre-processor Definitions + ****************************************************************************************************/ +/* General definitions */ + +#define OTG_EPTYPE_CTRL (0) /* Control */ +#define OTG_EPTYPE_ISOC (1) /* Isochronous */ +#define OTG_EPTYPE_BULK (2) /* Bulk */ +#define OTG_EPTYPE_INTR (3) /* Interrupt */ + +#define OTG_PID_DATA0 (0) +#define OTG_PID_DATA2 (1) +#define OTG_PID_DATA1 (2) +#define OTG_PID_MDATA (3) /* Non-control */ +#define OTG_PID_SETUP (3) /* Control */ + +/* Register Offsets *********************************************************************************/ +/* Core global control and status registers */ + +#define STM32_OTG_GOTGCTL_OFFSET 0x0000 /* Control and status register */ +#define STM32_OTG_GOTGINT_OFFSET 0x0004 /* Interrupt register */ +#define STM32_OTG_GAHBCFG_OFFSET 0x0008 /* AHB configuration register */ +#define STM32_OTG_GUSBCFG_OFFSET 0x000c /* USB configuration register */ +#define STM32_OTG_GRSTCTL_OFFSET 0x0010 /* Reset register */ +#define STM32_OTG_GINTSTS_OFFSET 0x0014 /* Core interrupt register */ +#define STM32_OTG_GINTMSK_OFFSET 0x0018 /* Interrupt mask register */ +#define STM32_OTG_GRXSTSR_OFFSET 0x001c /* Receive status debug read/OTG status read register */ +#define STM32_OTG_GRXSTSP_OFFSET 0x0020 /* Receive status debug read/OTG status pop register */ +#define STM32_OTG_GRXFSIZ_OFFSET 0x0024 /* Receive FIFO size register */ +#define STM32_OTG_HNPTXFSIZ_OFFSET 0x0028 /* Host non-periodic transmit FIFO size register */ +#define STM32_OTG_DIEPTXF0_OFFSET 0x0028 /* Endpoint 0 Transmit FIFO size */ +#define STM32_OTG_HNPTXSTS_OFFSET 0x002c /* Non-periodic transmit FIFO/queue status register */ +#define STM32_OTG_GCCFG_OFFSET 0x0038 /* General core configuration register */ +#define STM32_OTG_CID_OFFSET 0x003c /* Core ID register */ +#define STM32_OTG_HPTXFSIZ_OFFSET 0x0100 /* Host periodic transmit FIFO size register */ + +#define STM32_OTG_DIEPTXF_OFFSET(n) (104+(((n)-1) << 2)) + +/* Host-mode control and status registers */ + +#define STM32_OTG_HCFG_OFFSET 0x0400 /* Host configuration register */ +#define STM32_OTG_HFIR_OFFSET 0x0404 /* Host frame interval register */ +#define STM32_OTG_HFNUM_OFFSET 0x0408 /* Host frame number/frame time remaining register */ +#define STM32_OTG_HPTXSTS_OFFSET 0x0410 /* Host periodic transmit FIFO/queue status register */ +#define STM32_OTG_HAINT_OFFSET 0x0414 /* Host all channels interrupt register */ +#define STM32_OTG_HAINTMSK_OFFSET 0x0418 /* Host all channels interrupt mask register */ +#define STM32_OTG_HPRT_OFFSET 0x0440 /* Host port control and status register */ + +#define STM32_OTG_CHAN_OFFSET(n) (0x500 + ((n) << 5) +#define STM32_OTG_HCCHAR_CHOFFSET 0x0000 /* Host channel characteristics register */ +#define STM32_OTG_HCINT_CHOFFSET 0x0008 /* Host channel interrupt register */ +#define STM32_OTG_HCINTMSK_CHOFFSET 0x000c /* Host channel interrupt mask register */ +#define STM32_OTG_HCTSIZ_CHOFFSET 0x0010 /* Host channel interrupt register */ + +#define STM32_OTG_HCCHAR_OFFSET(n) (0x500 + ((n) << 5)) + +#define STM32_OTG_HCINT_OFFSET(n) (0x508 + ((n) << 5)) + +#define STM32_OTG_HCINTMSK_OFFSET(n) (0x50c + ((n) << 5)) + +#define STM32_OTG_HCTSIZ_OFFSET(n) (0x510 + ((n) << 5)) + +/* Device-mode control and status registers */ + +#define STM32_OTG_DCFG_OFFSET 0x0800 /* Device configuration register */ +#define STM32_OTG_DCTL_OFFSET 0x0804 /* Device control register */ +#define STM32_OTG_DSTS_OFFSET 0x0808 /* Device status register */ +#define STM32_OTG_DIEPMSK_OFFSET 0x0810 /* Device IN endpoint common interrupt mask register */ +#define STM32_OTG_DOEPMSK_OFFSET 0x0814 /* Device OUT endpoint common interrupt mask register */ +#define STM32_OTG_DAINT_OFFSET 0x0818 /* Device all endpoints interrupt register */ +#define STM32_OTG_DAINTMSK_OFFSET 0x081c /* All endpoints interrupt mask register */ +#define STM32_OTG_DVBUSDIS_OFFSET 0x0828 /* Device VBUS discharge time register */ +#define STM32_OTG_DVBUSPULSE_OFFSET 0x082c /* Device VBUS pulsing time register */ +#define STM32_OTG_DIEPEMPMSK_OFFSET 0x0834 /* Device IN endpoint FIFO empty interrupt mask register */ + +#define STM32_OTG_DIEP_OFFSET(n) (0x0900 + ((n) << 5)) +#define STM32_OTG_DIEPCTL_EPOFFSET 0x0000 /* Device endpoint control register */ +#define STM32_OTG_DIEPINT_EPOFFSET 0x0008 /* Device endpoint interrupt register */ +#define STM32_OTG_DIEPTSIZ_EPOFFSET 0x0010 /* Device IN endpoint transfer size register */ +#define STM32_OTG_DTXFSTS_EPOFFSET 0x0018 /* Device IN endpoint transmit FIFO status register */ + +#define STM32_OTG_DIEPCTL_OFFSET(n) (0x0900 + ((n) << 5)) + +#define STM32_OTG_DIEPINT_OFFSET(n) (0x0908 + ((n) << 5)) + +#define STM32_OTG_DIEPTSIZ_OFFSET(n) (0x910 + ((n) << 5)) + +#define STM32_OTG_DTXFSTS_OFFSET(n) (0x0918 + ((n) << 5)) + +#define STM32_OTG_DOEP_OFFSET(n) (0x0b00 + ((n) << 5)) +#define STM32_OTG_DOEPCTL_EPOFFSET 0x0000 /* Device control OUT endpoint 0 control register */ +#define STM32_OTG_DOEPINT_EPOFFSET 0x0008 /* Device endpoint-x interrupt register */ + +#define STM32_OTG_DOEPCTL_OFFSET(n) (0x0b00 + ((n) << 5)) + +#define STM32_OTG_DOEPINT_OFFSET(n) (0x0b08 + ((n) << 5)) + +#define STM32_OTG_DOEPTSIZ_OFFSET(n) (0x0b10 + ((n) << 5)) + +/* Power and clock gating registers */ + +#define STM32_OTG_PCGCCTL_OFFSET 0x0e00 /* Power and clock gating control register */ + +/* Data FIFO (DFIFO) access registers */ + +#define STM32_OTG_DFIFO_DEP_OFFSET(n) (0x1000 + ((n) << 12)) +#define STM32_OTG_DFIFO_HCH_OFFSET(n) (0x1000 + ((n) << 12)) + + +/* Register Addresses *******************************************************************************/ + +#define STM32_OTG_GOTGCTL (STM32_OTG_BASE+STM32_OTG_GOTGCTL_OFFSET) +#define STM32_OTG_GOTGINT (STM32_OTG_BASE+STM32_OTG_GOTGINT_OFFSET) +#define STM32_OTG_GAHBCFG (STM32_OTG_BASE+STM32_OTG_GAHBCFG_OFFSET) +#define STM32_OTG_GUSBCFG (STM32_OTG_BASE+STM32_OTG_GUSBCFG_OFFSET) +#define STM32_OTG_GRSTCTL (STM32_OTG_BASE+STM32_OTG_GRSTCTL_OFFSET) +#define STM32_OTG_GINTSTS (STM32_OTG_BASE+STM32_OTG_GINTSTS_OFFSET) +#define STM32_OTG_GINTMSK (STM32_OTG_BASE+STM32_OTG_GINTMSK_OFFSET) +#define STM32_OTG_GRXSTSR (STM32_OTG_BASE+STM32_OTG_GRXSTSR_OFFSET) +#define STM32_OTG_GRXSTSP (STM32_OTG_BASE+STM32_OTG_GRXSTSP_OFFSET) +#define STM32_OTG_GRXFSIZ (STM32_OTG_BASE+STM32_OTG_GRXFSIZ_OFFSET) +#define STM32_OTG_HNPTXFSIZ (STM32_OTG_BASE+STM32_OTG_HNPTXFSIZ_OFFSET) +#define STM32_OTG_DIEPTXF0 (STM32_OTG_BASE+STM32_OTG_DIEPTXF0_OFFSET) +#define STM32_OTG_HNPTXSTS (STM32_OTG_BASE+STM32_OTG_HNPTXSTS_OFFSET) +#define STM32_OTG_GCCFG (STM32_OTG_BASE+STM32_OTG_GCCFG_OFFSET) +#define STM32_OTG_CID (STM32_OTG_BASE+STM32_OTG_CID_OFFSET) +#define STM32_OTG_HPTXFSIZ (STM32_OTG_BASE+STM32_OTG_HPTXFSIZ_OFFSET) + +#define STM32_OTG_DIEPTXF(n) (STM32_OTG_BASE+STM32_OTG_DIEPTXF_OFFSET(n)) + +/* Host-mode control and status registers */ + +#define STM32_OTG_HCFG (STM32_OTG_BASE+STM32_OTG_HCFG_OFFSET) +#define STM32_OTG_HFIR (STM32_OTG_BASE+STM32_OTG_HFIR_OFFSET) +#define STM32_OTG_HFNUM (STM32_OTG_BASE+STM32_OTG_HFNUM_OFFSET) +#define STM32_OTG_HPTXSTS (STM32_OTG_BASE+STM32_OTG_HPTXSTS_OFFSET) +#define STM32_OTG_HAINT (STM32_OTG_BASE+STM32_OTG_HAINT_OFFSET) +#define STM32_OTG_HAINTMSK (STM32_OTG_BASE+STM32_OTG_HAINTMSK_OFFSET) +#define STM32_OTG_HPRT (STM32_OTG_BASE+STM32_OTG_HPRT_OFFSET) + +#define STM32_OTG_CHAN(n) (STM32_OTG_BASE+STM32_OTG_CHAN_OFFSET(n)) + +#define STM32_OTG_HCCHAR(n) (STM32_OTG_BASE+STM32_OTG_HCCHAR_OFFSET(n)) + +#define STM32_OTG_HCINT(n) (STM32_OTG_BASE+STM32_OTG_HCINT_OFFSET(n)) + +#define STM32_OTG_HCINTMSK(n) (STM32_OTG_BASE+STM32_OTG_HCINTMSK_OFFSET(n)) + +#define STM32_OTG_HCTSIZ(n) (STM32_OTG_BASE+STM32_OTG_HCTSIZ_OFFSET(n)) + +/* Device-mode control and status registers */ + +#define STM32_OTG_DCFG (STM32_OTG_BASE+STM32_OTG_DCFG_OFFSET) +#define STM32_OTG_DCTL (STM32_OTG_BASE+STM32_OTG_DCTL_OFFSET) +#define STM32_OTG_DSTS (STM32_OTG_BASE+STM32_OTG_DSTS_OFFSET) +#define STM32_OTG_DIEPMSK (STM32_OTG_BASE+STM32_OTG_DIEPMSK_OFFSET) +#define STM32_OTG_DOEPMSK (STM32_OTG_BASE+STM32_OTG_DOEPMSK_OFFSET) +#define STM32_OTG_DAINT (STM32_OTG_BASE+STM32_OTG_DAINT_OFFSET) +#define STM32_OTG_DAINTMSK (STM32_OTG_BASE+STM32_OTG_DAINTMSK_OFFSET) +#define STM32_OTG_DVBUSDIS (STM32_OTG_BASE+STM32_OTG_DVBUSDIS_OFFSET) +#define STM32_OTG_DVBUSPULSE (STM32_OTG_BASE+STM32_OTG_DVBUSPULSE_OFFSET) +#define STM32_OTG_DIEPEMPMSK (STM32_OTG_BASE+STM32_OTG_DIEPEMPMSK_OFFSET) + +#define STM32_OTG_DIEP(n) (STM32_OTG_BASE+STM32_OTG_DIEP_OFFSET(n)) + +#define STM32_OTG_DIEPCTL(n) (STM32_OTG_BASE+STM32_OTG_DIEPCTL_OFFSET(n)) + +#define STM32_OTG_DIEPINT(n) (STM32_OTG_BASE+STM32_OTG_DIEPINT_OFFSET(n)) + +#define STM32_OTG_DIEPTSIZ(n) (STM32_OTG_BASE+STM32_OTG_DIEPTSIZ_OFFSET(n)) + +#define STM32_OTG_DTXFSTS(n) (STM32_OTG_BASE+STM32_OTG_DTXFSTS_OFFSET(n)) + +#define STM32_OTG_DOEP(n) (STM32_OTG_BASE+STM32_OTG_DOEP_OFFSET(n)) + +#define STM32_OTG_DOEPCTL(n) (STM32_OTG_BASE+STM32_OTG_DOEPCTL_OFFSET(n)) + +#define STM32_OTG_DOEPINT(n) (STM32_OTG_BASE+STM32_OTG_DOEPINT_OFFSET(n)) + +#define STM32_OTG_DOEPTSIZ(n) (STM32_OTG_BASE+STM32_OTG_DOEPTSIZ_OFFSET(n)) + +/* Power and clock gating registers */ + +#define STM32_OTG_PCGCCTL (STM32_OTG_BASE+STM32_OTG_PCGCCTL_OFFSET) + +/* Data FIFO (DFIFO) access registers */ + +#define STM32_OTG_DFIFO_DEP(n) (STM32_OTG_BASE+STM32_OTG_DFIFO_DEP_OFFSET(n)) +#define STM32_OTG_DFIFO_HCH(n) (STM32_OTG_BASE+STM32_OTG_DFIFO_HCH_OFFSET(n)) + + +/* Register Bitfield Definitions ********************************************************************/ +/* Core global control and status registers */ + +/* Control and status register */ + +#define OTG_GOTGCTL_SRQSCS (1 << 0) /* Bit 0: Session request success */ +#define OTG_GOTGCTL_SRQ (1 << 1) /* Bit 1: Session request */ +#define OTG_GOTGCTL_VBVALOEN (1 << 2) /* Bit 2: VBUS valid override enable */ +#define OTG_GOTGCTL_VBVALOVAL (1 << 3) /* Bit 3: VBUS valid override value */ +#define OTG_GOTGCTL_AVALOEN (1 << 4) /* Bit 4: A-peripheral session valid override enable */ +#define OTG_GOTGCTL_AVALOVAL (1 << 5) /* Bit 5: A-peripheral session valid override value */ +#define OTG_GOTGCTL_BVALOEN (1 << 6) /* Bit 6: B-peripheral session valid override enable */ +#define OTG_GOTGCTL_BVALOVAL (1 << 7) /* Bit 7: B-peripheral session valid override value */ +#define OTG_GOTGCTL_HNGSCS (1 << 8) /* Bit 8: Host negotiation success */ +#define OTG_GOTGCTL_HNPRQ (1 << 9) /* Bit 9: HNP request */ +#define OTG_GOTGCTL_HSHNPEN (1 << 10) /* Bit 10: host set HNP enable */ +#define OTG_GOTGCTL_DHNPEN (1 << 11) /* Bit 11: Device HNP enabled */ +#define OTG_GOTGCTL_EHEN (1 << 12) /* Bit 12: Embedded host enable */ + /* Bits 13-15: Reserved, must be kept at reset value */ +#define OTG_GOTGCTL_CIDSTS (1 << 16) /* Bit 16: Connector ID status */ +#define OTG_GOTGCTL_DBCT (1 << 17) /* Bit 17: Long/short debounce time */ +#define OTG_GOTGCTL_ASVLD (1 << 18) /* Bit 18: A-session valid */ +#define OTG_GOTGCTL_BSVLD (1 << 19) /* Bit 19: B-session valid */ +#define OTG_GOTGCTL_OTGVER (1 << 20) /* Bit 20: OTG version */ + /* Bits 21-31: Reserved, must be kept at reset value */ +/* Interrupt register */ + /* Bits 1:0 Reserved, must be kept at reset value */ +#define OTG_GOTGINT_SEDET (1 << 2) /* Bit 2: Session end detected */ + /* Bits 3-7: Reserved, must be kept at reset value */ +#define OTG_GOTGINT_SRSSCHG (1 << 8) /* Bit 8: Session request success status change */ +#define OTG_GOTGINT_HNSSCHG (1 << 9) /* Bit 9: Host negotiation success status change */ + /* Bits 16:10 Reserved, must be kept at reset value */ +#define OTG_GOTGINT_HNGDET (1 << 17) /* Bit 17: Host negotiation detected */ +#define OTG_GOTGINT_ADTOCHG (1 << 18) /* Bit 18: A-device timeout change */ +#define OTG_GOTGINT_DBCDNE (1 << 19) /* Bit 19: Debounce done */ +#define OTG_GOTGINT_IDCHNG (1 << 20) /* Bit 20: Change in ID pin input value */ + /* Bits 21-31: Reserved, must be kept at reset value */ + +/* AHB configuration register */ + +#define OTG_GAHBCFG_GINTMSK (1 << 0) /* Bit 0: Global interrupt mask */ + /* Bits 1-6: Reserved, must be kept at reset value */ +#define OTG_GAHBCFG_TXFELVL (1 << 7) /* Bit 7: TxFIFO empty level */ +#define OTG_GAHBCFG_PTXFELVL (1 << 8) /* Bit 8: Periodic TxFIFO empty level */ + /* Bits 20-31: Reserved, must be kept at reset value */ +/* USB configuration register */ + +#define OTG_GUSBCFG_TOCAL_SHIFT (0) /* Bits 0-2: FS timeout calibration */ +#define OTG_GUSBCFG_TOCAL_MASK (7 << OTG_GUSBCFG_TOCAL_SHIFT) + /* Bits 3-5: Reserved, must be kept at reset value */ +#define OTG_GUSBCFG_PHYSEL (1 << 6) /* Bit 6: Full Speed serial transceiver select */ + /* Bit 7: Reserved, must be kept at reset value */ +#define OTG_GUSBCFG_SRPCAP (1 << 8) /* Bit 8: SRP-capable */ +#define OTG_GUSBCFG_HNPCAP (1 << 9) /* Bit 9: HNP-capable */ +#define OTG_GUSBCFG_TRDT_SHIFT (10) /* Bits 10-13: USB turnaround time */ +#define OTG_GUSBCFG_TRDT_MASK (15 << OTG_GUSBCFG_TRDT_SHIFT) +# define OTG_GUSBCFG_TRDT(n) ((n) << OTG_GUSBCFG_TRDT_SHIFT) + /* Bits 14-28: Reserved, must be kept at reset value */ +#define OTG_GUSBCFG_FHMOD (1 << 29) /* Bit 29: Force host mode */ +#define OTG_GUSBCFG_FDMOD (1 << 30) /* Bit 30: Force device mode */ +#define OTG_GUSBCFG_CTXPKT (1 << 31) /* Bit 31: Corrupt Tx packet */ + /* Bits 20-31: Reserved, must be kept at reset value */ +/* Reset register */ + +#define OTG_GRSTCTL_CSRST (1 << 0) /* Bit 0: Core soft reset */ +#define OTG_GRSTCTL_HSRST (1 << 1) /* Bit 1: HCLK soft reset */ +#define OTG_GRSTCTL_FCRST (1 << 2) /* Bit 2: Host frame counter reset */ + /* Bit 3 Reserved, must be kept at reset value */ +#define OTG_GRSTCTL_RXFFLSH (1 << 4) /* Bit 4: RxFIFO flush */ +#define OTG_GRSTCTL_TXFFLSH (1 << 5) /* Bit 5: TxFIFO flush */ +#define OTG_GRSTCTL_TXFNUM_SHIFT (6) /* Bits 6-10: TxFIFO number */ +#define OTG_GRSTCTL_TXFNUM_MASK (31 << OTG_GRSTCTL_TXFNUM_SHIFT) +# define OTG_GRSTCTL_TXFNUM_HNONPER (0 << OTG_GRSTCTL_TXFNUM_SHIFT) /* Non-periodic TxFIFO flush in host mode */ +# define OTG_GRSTCTL_TXFNUM_HPER (1 << OTG_GRSTCTL_TXFNUM_SHIFT) /* Periodic TxFIFO flush in host mode */ +# define OTG_GRSTCTL_TXFNUM_HALL (16 << OTG_GRSTCTL_TXFNUM_SHIFT) /* Flush all the transmit FIFOs in host mode.*/ +# define OTG_GRSTCTL_TXFNUM_D(n) ((n) << OTG_GRSTCTL_TXFNUM_SHIFT) /* TXFIFO n flush in device mode, n=0-15 */ +# define OTG_GRSTCTL_TXFNUM_DALL (16 << OTG_GRSTCTL_TXFNUM_SHIFT) /* Flush all the transmit FIFOs in device mode.*/ + /* Bits 11-31: Reserved, must be kept at reset value */ +#define OTG_GRSTCTL_AHBIDL (1 << 31) /* Bit 31: AHB master idle */ + +/* Core interrupt and Interrupt mask registers */ + +#define OTG_GINTSTS_CMOD (1 << 0) /* Bit 0: Current mode of operation */ +# define OTG_GINTSTS_DEVMODE (0) +# define OTG_GINTSTS_HOSTMODE (OTG_GINTSTS_CMOD) +#define OTG_GINT_MMIS (1 << 1) /* Bit 1: Mode mismatch interrupt */ +#define OTG_GINT_OTG (1 << 2) /* Bit 2: OTG interrupt */ +#define OTG_GINT_SOF (1 << 3) /* Bit 3: Start of frame */ +#define OTG_GINT_RXFLVL (1 << 4) /* Bit 4: RxFIFO non-empty */ +#define OTG_GINT_NPTXFE (1 << 5) /* Bit 5: Non-periodic TxFIFO empty */ +#define OTG_GINT_GINAKEFF (1 << 6) /* Bit 6: Global IN non-periodic NAK effective */ +#define OTG_GINT_GONAKEFF (1 << 7) /* Bit 7: Global OUT NAK effective */ + /* Bits 8-9: Reserved, must be kept at reset value */ +#define OTG_GINT_ESUSP (1 << 10) /* Bit 10: Early suspend */ +#define OTG_GINT_USBSUSP (1 << 11) /* Bit 11: USB suspend */ +#define OTG_GINT_USBRST (1 << 12) /* Bit 12: USB reset */ +#define OTG_GINT_ENUMDNE (1 << 13) /* Bit 13: Enumeration done */ +#define OTG_GINT_ISOODRP (1 << 14) /* Bit 14: Isochronous OUT packet dropped interrupt */ +#define OTG_GINT_EOPF (1 << 15) /* Bit 15: End of periodic frame interrupt */ + /* Bits 16 Reserved, must be kept at reset value */ +#define OTG_GINTMSK_EPMISM (1 << 17) /* Bit 17: Endpoint mismatch interrupt mask */ +#define OTG_GINT_IEP (1 << 18) /* Bit 18: IN endpoint interrupt */ +#define OTG_GINT_OEP (1 << 19) /* Bit 19: OUT endpoint interrupt */ +#define OTG_GINT_IISOIXFR (1 << 20) /* Bit 20: Incomplete isochronous IN transfer */ +#define OTG_GINT_IISOOXFR (1 << 21) /* Bit 21: Incomplete isochronous OUT transfer (device) */ +#define OTG_GINT_IPXFR (1 << 21) /* Bit 21: Incomplete periodic transfer (host) */ + /* Bit 22: Reserved, must be kept at reset value */ +#define OTG_GINT_RSTDET (1 << 23) /* Bit 23: Reset detected interrupt */ +#define OTG_GINT_HPRT (1 << 24) /* Bit 24: Host port interrupt */ +#define OTG_GINT_HC (1 << 25) /* Bit 25: Host channels interrupt */ +#define OTG_GINT_PTXFE (1 << 26) /* Bit 26: Periodic TxFIFO empty */ +#define OTG_GINT_LPMINT (1 << 27) /* Bit 27: LPM interrupt */ +#define OTG_GINT_CIDSCHG (1 << 28) /* Bit 28: Connector ID status change */ +#define OTG_GINT_DISC (1 << 29) /* Bit 29: Disconnect detected interrupt */ +#define OTG_GINT_SRQ (1 << 30) /* Bit 30: Session request/new session detected interrupt */ +#define OTG_GINT_WKUP (1 << 31) /* Bit 31: Resume/remote wakeup detected interrupt */ + +/* Receive status debug read/OTG status read and pop registers (host mode) */ + +#define OTG_GRXSTSH_CHNUM_SHIFT (0) /* Bits 0-3: Channel number */ +#define OTG_GRXSTSH_CHNUM_MASK (15 << OTG_GRXSTSH_CHNUM_SHIFT) +#define OTG_GRXSTSH_BCNT_SHIFT (4) /* Bits 4-14: Byte count */ +#define OTG_GRXSTSH_BCNT_MASK (0x7ff << OTG_GRXSTSH_BCNT_SHIFT) +#define OTG_GRXSTSH_DPID_SHIFT (15) /* Bits 15-16: Data PID */ +#define OTG_GRXSTSH_DPID_MASK (3 << OTG_GRXSTSH_DPID_SHIFT) +# define OTG_GRXSTSH_DPID_DATA0 (0 << OTG_GRXSTSH_DPID_SHIFT) +# define OTG_GRXSTSH_DPID_DATA2 (1 << OTG_GRXSTSH_DPID_SHIFT) +# define OTG_GRXSTSH_DPID_DATA1 (2 << OTG_GRXSTSH_DPID_SHIFT) +# define OTG_GRXSTSH_DPID_MDATA (3 << OTG_GRXSTSH_DPID_SHIFT) +#define OTG_GRXSTSH_PKTSTS_SHIFT (17) /* Bits 17-20: Packet status */ +#define OTG_GRXSTSH_PKTSTS_MASK (15 << OTG_GRXSTSH_PKTSTS_SHIFT) +# define OTG_GRXSTSH_PKTSTS_INRECVD (2 << OTG_GRXSTSH_PKTSTS_SHIFT) /* IN data packet received */ +# define OTG_GRXSTSH_PKTSTS_INDONE (3 << OTG_GRXSTSH_PKTSTS_SHIFT) /* IN transfer completed */ +# define OTG_GRXSTSH_PKTSTS_DTOGERR (5 << OTG_GRXSTSH_PKTSTS_SHIFT) /* Data toggle error */ +# define OTG_GRXSTSH_PKTSTS_HALTED (7 << OTG_GRXSTSH_PKTSTS_SHIFT) /* Channel halted */ + /* Bits 21-31: Reserved, must be kept at reset value */ +/* Receive status debug read/OTG status read and pop registers (device mode) */ + +#define OTG_GRXSTSD_EPNUM_SHIFT (0) /* Bits 0-3: Endpoint number */ +#define OTG_GRXSTSD_EPNUM_MASK (15 << OTG_GRXSTSD_EPNUM_SHIFT) +#define OTG_GRXSTSD_BCNT_SHIFT (4) /* Bits 4-14: Byte count */ +#define OTG_GRXSTSD_BCNT_MASK (0x7ff << OTG_GRXSTSD_BCNT_SHIFT) +#define OTG_GRXSTSD_DPID_SHIFT (15) /* Bits 15-16: Data PID */ +#define OTG_GRXSTSD_DPID_MASK (3 << OTG_GRXSTSD_DPID_SHIFT) +# define OTG_GRXSTSD_DPID_DATA0 (0 << OTG_GRXSTSD_DPID_SHIFT) +# define OTG_GRXSTSD_DPID_DATA2 (1 << OTG_GRXSTSD_DPID_SHIFT) +# define OTG_GRXSTSD_DPID_DATA1 (2 << OTG_GRXSTSD_DPID_SHIFT) +# define OTG_GRXSTSD_DPID_MDATA (3 << OTG_GRXSTSD_DPID_SHIFT) +#define OTG_GRXSTSD_PKTSTS_SHIFT (17) /* Bits 17-20: Packet status */ +#define OTG_GRXSTSD_PKTSTS_MASK (15 << OTG_GRXSTSD_PKTSTS_SHIFT) +# define OTG_GRXSTSD_PKTSTS_OUTNAK (1 << OTG_GRXSTSD_PKTSTS_SHIFT) /* Global OUT NAK */ +# define OTG_GRXSTSD_PKTSTS_OUTRECVD (2 << OTG_GRXSTSD_PKTSTS_SHIFT) /* OUT data packet received */ +# define OTG_GRXSTSD_PKTSTS_OUTDONE (3 << OTG_GRXSTSD_PKTSTS_SHIFT) /* OUT transfer completed */ +# define OTG_GRXSTSD_PKTSTS_SETUPDONE (4 << OTG_GRXSTSD_PKTSTS_SHIFT) /* SETUP transaction completed */ +# define OTG_GRXSTSD_PKTSTS_SETUPRECVD (6 << OTG_GRXSTSD_PKTSTS_SHIFT) /* SETUP data packet received */ +#define OTG_GRXSTSD_FRMNUM_SHIFT (21) /* Bits 21-24: Frame number */ +#define OTG_GRXSTSD_FRMNUM_MASK (15 << OTG_GRXSTSD_FRMNUM_SHIFT) + /* Bits 25-31: Reserved, must be kept at reset value */ +/* Receive FIFO size register */ + +#define OTG_GRXFSIZ_MASK (0xffff) + +/* Host non-periodic transmit FIFO size register */ + +#define OTG_HNPTXFSIZ_NPTXFSA_SHIFT (0) /* Bits 0-15: Non-periodic transmit RAM start address */ +#define OTG_HNPTXFSIZ_NPTXFSA_MASK (0xffff << OTG_HNPTXFSIZ_NPTXFSA_SHIFT) +#define OTG_HNPTXFSIZ_NPTXFD_SHIFT (16) /* Bits 16-31: Non-periodic TxFIFO depth */ +#define OTG_HNPTXFSIZ_NPTXFD_MASK (0xffff << OTG_HNPTXFSIZ_NPTXFD_SHIFT) +# define OTG_HNPTXFSIZ_NPTXFD_MIN (16 << OTG_HNPTXFSIZ_NPTXFD_SHIFT) +# define OTG_HNPTXFSIZ_NPTXFD_MAX (256 << OTG_HNPTXFSIZ_NPTXFD_SHIFT) + +/* Endpoint 0 Transmit FIFO size */ + +#define OTG_DIEPTXF0_TX0FD_SHIFT (0) /* Bits 0-15: Endpoint 0 transmit RAM start address */ +#define OTG_DIEPTXF0_TX0FD_MASK (0xffff << OTG_DIEPTXF0_TX0FD_SHIFT) +#define OTG_DIEPTXF0_TX0FSA_SHIFT (16) /* Bits 16-31: Endpoint 0 TxFIFO depth */ +#define OTG_DIEPTXF0_TX0FSA_MASK (0xffff << OTG_DIEPTXF0_TX0FSA_SHIFT) +# define OTG_DIEPTXF0_TX0FSA_MIN (16 << OTG_DIEPTXF0_TX0FSA_SHIFT) +# define OTG_DIEPTXF0_TX0FSA_MAX (256 << OTG_DIEPTXF0_TX0FSA_SHIFT) + +/* Non-periodic transmit FIFO/queue status register */ + +#define OTG_HNPTXSTS_NPTXFSAV_SHIFT (0) /* Bits 0-15: Non-periodic TxFIFO space available */ +#define OTG_HNPTXSTS_NPTXFSAV_MASK (0xffff << OTG_HNPTXSTS_NPTXFSAV_SHIFT) +# define OTG_HNPTXSTS_NPTXFSAV_FULL (0 << OTG_HNPTXSTS_NPTXFSAV_SHIFT) +#define OTG_HNPTXSTS_NPTQXSAV_SHIFT (16) /* Bits 16-23: Non-periodic transmit request queue space available */ +#define OTG_HNPTXSTS_NPTQXSAV_MASK (0xff << OTG_HNPTXSTS_NPTQXSAV_SHIFT) +# define OTG_HNPTXSTS_NPTQXSAV_FULL (0 << OTG_HNPTXSTS_NPTQXSAV_SHIFT) +#define OTG_HNPTXSTS_NPTXQTOP_SHIFT (24) /* Bits 24-30: Top of the non-periodic transmit request queue */ +#define OTG_HNPTXSTS_NPTXQTOP_MASK (0x7f << OTG_HNPTXSTS_NPTXQTOP_SHIFT) +# define OTG_HNPTXSTS_TERMINATE (1 << 24) /* Bit 24: Terminate (last entry for selected channel/endpoint) */ +# define OTG_HNPTXSTS_TYPE_SHIFT (25) /* Bits 25-26: Status */ +# define OTG_HNPTXSTS_TYPE_MASK (3 << OTG_HNPTXSTS_TYPE_SHIFT) +# define OTG_HNPTXSTS_TYPE_INOUT (0 << OTG_HNPTXSTS_TYPE_SHIFT) /* IN/OUT token */ +# define OTG_HNPTXSTS_TYPE_ZLP (1 << OTG_HNPTXSTS_TYPE_SHIFT) /* Zero-length transmit packet (device IN/host OUT) */ +# define OTG_HNPTXSTS_TYPE_HALT (3 << OTG_HNPTXSTS_TYPE_SHIFT) /* Channel halt command */ +# define OTG_HNPTXSTS_CHNUM_SHIFT (27) /* Bits 27-30: Channel number */ +# define OTG_HNPTXSTS_CHNUM_MASK (15 << OTG_HNPTXSTS_CHNUM_SHIFT) +# define OTG_HNPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */ +# define OTG_HNPTXSTS_EPNUM_MASK (15 << OTG_HNPTXSTS_EPNUM_SHIFT) + /* Bit 31 Reserved, must be kept at reset value */ +/* General core configuration register */ + /* Bits 0-15: Reserved, must be kept at reset value */ +#define OTG_GCCFG_PWRDWN (1 << 16) /* Bit 16: Power down */ + /* Bit 17 Reserved, must be kept at reset value */ +#define OTG_GCCFG_VBDEN (1 << 21) /* Bit 21: USB VBUS detection enable */ + /* Bits 22-31: Reserved, must be kept at reset value */ +/* Core ID register (32-bit product ID) */ + +/* Host periodic transmit FIFO size register */ + +#define OTG_HPTXFSIZ_PTXSA_SHIFT (0) /* Bits 0-15: Host periodic TxFIFO start address */ +#define OTG_HPTXFSIZ_PTXSA_MASK (0xffff << OTG_HPTXFSIZ_PTXSA_SHIFT) +#define OTG_HPTXFSIZ_PTXFD_SHIFT (16) /* Bits 16-31: Host periodic TxFIFO depth */ +#define OTG_HPTXFSIZ_PTXFD_MASK (0xffff << OTG_HPTXFSIZ_PTXFD_SHIFT) + +/* Device IN endpoint transmit FIFOn size register */ + +#define OTG_DIEPTXF_INEPTXSA_SHIFT (0) /* Bits 0-15: IN endpoint FIFOx transmit RAM start address */ +#define OTG_DIEPTXF_INEPTXSA_MASK (0xffff << OTG_DIEPTXF_INEPTXSA_SHIFT) +#define OTG_DIEPTXF_INEPTXFD_SHIFT (16) /* Bits 16-31: IN endpoint TxFIFO depth */ +#define OTG_DIEPTXF_INEPTXFD_MASK (0xffff << OTG_DIEPTXF_INEPTXFD_SHIFT) +# define OTG_DIEPTXF_INEPTXFD_MIN (16 << OTG_DIEPTXF_INEPTXFD_MASK) + +/* Host-mode control and status registers */ + +/* Host configuration register */ + +#define OTG_HCFG_FSLSPCS_SHIFT (0) /* Bits 0-1: FS/LS PHY clock select */ +#define OTG_HCFG_FSLSPCS_MASK (3 << OTG_HCFG_FSLSPCS_SHIFT) +# define OTG_HCFG_FSLSPCS_FS48MHz (1 << OTG_HCFG_FSLSPCS_SHIFT) /* FS host mode, PHY clock is running at 48 MHz */ +# define OTG_HCFG_FSLSPCS_LS48MHz (1 << OTG_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 48 MHz PHY clock frequency */ +# define OTG_HCFG_FSLSPCS_LS6MHz (2 << OTG_HCFG_FSLSPCS_SHIFT) /* LS host mode, Select 6 MHz PHY clock frequency */ +#define OTG_HCFG_FSLSS (1 << 2) /* Bit 2: FS- and LS-only support */ + /* Bits 31:3 Reserved, must be kept at reset value */ +/* Host frame interval register */ + +#define OTG_HFIR_MASK (0xffff) + +/* Host frame number/frame time remaining register */ + +#define OTG_HFNUM_FRNUM_SHIFT (0) /* Bits 0-15: Frame number */ +#define OTG_HFNUM_FRNUM_MASK (0xffff << OTG_HFNUM_FRNUM_SHIFT) +#define OTG_HFNUM_FTREM_SHIFT (16) /* Bits 16-31: Frame time remaining */ +#define OTG_HFNUM_FTREM_MASK (0xffff << OTG_HFNUM_FTREM_SHIFT) + +/* Host periodic transmit FIFO/queue status register */ + +#define OTG_HPTXSTS_PTXFSAVL_SHIFT (0) /* Bits 0-15: Periodic transmit data FIFO space available */ +#define OTG_HPTXSTS_PTXFSAVL_MASK (0xffff << OTG_HPTXSTS_PTXFSAVL_SHIFT) +# define OTG_HPTXSTS_PTXFSAVL_FULL (0 << OTG_HPTXSTS_PTXFSAVL_SHIFT) +#define OTG_HPTXSTS_PTXQSAV_SHIFT (16) /* Bits 16-23: Periodic transmit request queue space available */ +#define OTG_HPTXSTS_PTXQSAV_MASK (0xff << OTG_HPTXSTS_PTXQSAV_SHIFT) +# define OTG_HPTXSTS_PTXQSAV_FULL (0 << OTG_HPTXSTS_PTXQSAV_SHIFT) +#define OTG_HPTXSTS_PTXQTOP_SHIFT (24) /* Bits 24-31: Top of the periodic transmit request queue */ +#define OTG_HPTXSTS_PTXQTOP_MASK (0x7f << OTG_HPTXSTS_PTXQTOP_SHIFT) +# define OTG_HPTXSTS_TERMINATE (1 << 24) /* Bit 24: Terminate (last entry for selected channel/endpoint) */ +# define OTG_HPTXSTS_TYPE_SHIFT (25) /* Bits 25-26: Type */ +# define OTG_HPTXSTS_TYPE_MASK (3 << OTG_HPTXSTS_TYPE_SHIFT) +# define OTG_HPTXSTS_TYPE_INOUT (0 << OTG_HPTXSTS_TYPE_SHIFT) /* IN/OUT token */ +# define OTG_HPTXSTS_TYPE_ZLP (1 << OTG_HPTXSTS_TYPE_SHIFT) /* Zero-length transmit packet */ +# define OTG_HPTXSTS_TYPE_HALT (3 << OTG_HPTXSTS_TYPE_SHIFT) /* Disable channel command */ +# define OTG_HPTXSTS_EPNUM_SHIFT (27) /* Bits 27-30: Endpoint number */ +# define OTG_HPTXSTS_EPNUM_MASK (15 << OTG_HPTXSTS_EPNUM_SHIFT) +# define OTG_HPTXSTS_CHNUM_SHIFT (27) /* Bits 27-30: Channel number */ +# define OTG_HPTXSTS_CHNUM_MASK (15 << OTG_HPTXSTS_CHNUM_SHIFT) +# define OTG_HPTXSTS_ODD (1 << 24) /* Bit 31: Send in odd (vs even) frame */ + +/* Host all channels interrupt and all channels interrupt mask registers */ + +#define OTG_HAINT(n) (1 << (n)) /* Bits 15:0 HAINTM: Channel interrupt */ + +/* Host port control and status register */ + +#define OTG_HPRT_PCSTS (1 << 0) /* Bit 0: Port connect status */ +#define OTG_HPRT_PCDET (1 << 1) /* Bit 1: Port connect detected */ +#define OTG_HPRT_PENA (1 << 2) /* Bit 2: Port enable */ +#define OTG_HPRT_PENCHNG (1 << 3) /* Bit 3: Port enable/disable change */ +#define OTG_HPRT_POCA (1 << 4) /* Bit 4: Port overcurrent active */ +#define OTG_HPRT_POCCHNG (1 << 5) /* Bit 5: Port overcurrent change */ +#define OTG_HPRT_PRES (1 << 6) /* Bit 6: Port resume */ +#define OTG_HPRT_PSUSP (1 << 7) /* Bit 7: Port suspend */ +#define OTG_HPRT_PRST (1 << 8) /* Bit 8: Port reset */ + /* Bit 9: Reserved, must be kept at reset value */ +#define OTG_HPRT_PLSTS_SHIFT (10) /* Bits 10-11: Port line status */ +#define OTG_HPRT_PLSTS_MASK (3 << OTG_HPRT_PLSTS_SHIFT) +# define OTG_HPRT_PLSTS_DP (1 << 10) /* Bit 10: Logic level of OTG_FS_FS_DP */ +# define OTG_HPRT_PLSTS_DM (1 << 11) /* Bit 11: Logic level of OTG_FS_FS_DM */ +#define OTG_HPRT_PPWR (1 << 12) /* Bit 12: Port power */ +#define OTG_HPRT_PTCTL_SHIFT (13) /* Bits 13-16: Port test control */ +#define OTG_HPRT_PTCTL_MASK (15 << OTG_HPRT_PTCTL_SHIFT) +# define OTG_HPRT_PTCTL_DISABLED (0 << OTG_HPRT_PTCTL_SHIFT) /* Test mode disabled */ +# define OTG_HPRT_PTCTL_J (1 << OTG_HPRT_PTCTL_SHIFT) /* Test_J mode */ +# define OTG_HPRT_PTCTL_L (2 << OTG_HPRT_PTCTL_SHIFT) /* Test_K mode */ +# define OTG_HPRT_PTCTL_SE0_NAK (3 << OTG_HPRT_PTCTL_SHIFT) /* Test_SE0_NAK mode */ +# define OTG_HPRT_PTCTL_PACKET (4 << OTG_HPRT_PTCTL_SHIFT) /* Test_Packet mode */ +# define OTG_HPRT_PTCTL_FORCE (5 << OTG_HPRT_PTCTL_SHIFT) /* Test_Force_Enable */ +#define OTG_HPRT_PSPD_SHIFT (17) /* Bits 17-18: Port speed */ +#define OTG_HPRT_PSPD_MASK (3 << OTG_HPRT_PSPD_SHIFT) +# define OTG_HPRT_PSPD_FS (1 << OTG_HPRT_PSPD_SHIFT) /* Full speed */ +# define OTG_HPRT_PSPD_LS (2 << OTG_HPRT_PSPD_SHIFT) /* Low speed */ + /* Bits 19-31: Reserved, must be kept at reset value */ + +/* Host channel-n characteristics register */ + +#define OTG_HCCHAR_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */ +#define OTG_HCCHAR_MPSIZ_MASK (0x7ff << OTG_HCCHAR_MPSIZ_SHIFT) +#define OTG_HCCHAR_EPNUM_SHIFT (11) /* Bits 11-14: Endpoint number */ +#define OTG_HCCHAR_EPNUM_MASK (15 << OTG_HCCHAR_EPNUM_SHIFT) +#define OTG_HCCHAR_EPDIR (1 << 15) /* Bit 15: Endpoint direction */ +# define OTG_HCCHAR_EPDIR_OUT (0) +# define OTG_HCCHAR_EPDIR_IN OTG_HCCHAR_EPDIR + /* Bit 16 Reserved, must be kept at reset value */ +#define OTG_HCCHAR_LSDEV (1 << 17) /* Bit 17: Low-speed device */ +#define OTG_HCCHAR_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ +#define OTG_HCCHAR_EPTYP_MASK (3 << OTG_HCCHAR_EPTYP_SHIFT) +# define OTG_HCCHAR_EPTYP_CTRL (0 << OTG_HCCHAR_EPTYP_SHIFT) /* Control */ +# define OTG_HCCHAR_EPTYP_ISOC (1 << OTG_HCCHAR_EPTYP_SHIFT) /* Isochronous */ +# define OTG_HCCHAR_EPTYP_BULK (2 << OTG_HCCHAR_EPTYP_SHIFT) /* Bulk */ +# define OTG_HCCHAR_EPTYP_INTR (3 << OTG_HCCHAR_EPTYP_SHIFT) /* Interrupt */ +#define OTG_HCCHAR_MCNT_SHIFT (20) /* Bits 20-21: Multicount */ +#define OTG_HCCHAR_MCNT_MASK (3 << OTG_HCCHAR_MCNT_SHIFT) +#define OTG_HCCHAR_DAD_SHIFT (22) /* Bits 22-28: Device address */ +#define OTG_HCCHAR_DAD_MASK (0x7f << OTG_HCCHAR_DAD_SHIFT) +#define OTG_HCCHAR_ODDFRM (1 << 29) /* Bit 29: Odd frame */ +#define OTG_HCCHAR_CHDIS (1 << 30) /* Bit 30: Channel disable */ +#define OTG_HCCHAR_CHENA (1 << 31) /* Bit 31: Channel enable */ + +/* Host channel-n interrupt and Host channel-0 interrupt mask registers */ + +#define OTG_HCINT_XFRC (1 << 0) /* Bit 0: Transfer completed */ +#define OTG_HCINT_CHH (1 << 1) /* Bit 1: Channel halted */ + /* Bit 2: Reserved, must be kept at reset value */ +#define OTG_HCINT_STALL (1 << 3) /* Bit 3: STALL response received interrupt */ +#define OTG_HCINT_NAK (1 << 4) /* Bit 4: NAK response received interrupt */ +#define OTG_HCINT_ACK (1 << 5) /* Bit 5: ACK response received/transmitted interrupt */ +#define OTG_HCINT_NYET (1 << 6) /* Bit 6: Response received interrupt */ +#define OTG_HCINT_TXERR (1 << 7) /* Bit 7: Transaction error */ +#define OTG_HCINT_BBERR (1 << 8) /* Bit 8: Babble error */ +#define OTG_HCINT_FRMOR (1 << 9) /* Bit 9: Frame overrun */ +#define OTG_HCINT_DTERR (1 << 10) /* Bit 10: Data toggle error */ + /* Bits 11-31 Reserved, must be kept at reset value */ +/* Host channel-n interrupt register */ + +#define OTG_HCTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */ +#define OTG_HCTSIZ_XFRSIZ_MASK (0x7ffff << OTG_HCTSIZ_XFRSIZ_SHIFT) +#define OTG_HCTSIZ_PKTCNT_SHIFT (19) /* Bits 19-28: Packet count */ +#define OTG_HCTSIZ_PKTCNT_MASK (0x3ff << OTG_HCTSIZ_PKTCNT_SHIFT) +#define OTG_HCTSIZ_DPID_SHIFT (29) /* Bits 29-30: Data PID */ +#define OTG_HCTSIZ_DPID_MASK (3 << OTG_HCTSIZ_DPID_SHIFT) +# define OTG_HCTSIZ_DPID_DATA0 (0 << OTG_HCTSIZ_DPID_SHIFT) +# define OTG_HCTSIZ_DPID_DATA2 (1 << OTG_HCTSIZ_DPID_SHIFT) +# define OTG_HCTSIZ_DPID_DATA1 (2 << OTG_HCTSIZ_DPID_SHIFT) +# define OTG_HCTSIZ_DPID_MDATA (3 << OTG_HCTSIZ_DPID_SHIFT) /* Non-control */ +# define OTG_HCTSIZ_PID_SETUP (3 << OTG_HCTSIZ_DPID_SHIFT) /* Control */ + /* Bit 31 Reserved, must be kept at reset value */ +/* Device-mode control and status registers */ + +/* Device configuration register */ + +#define OTG_DCFG_DSPD_SHIFT (0) /* Bits 0-1: Device speed */ +#define OTG_DCFG_DSPD_MASK (3 << OTG_DCFG_DSPD_SHIFT) +# define OTG_DCFG_DSPD_FS (3 << OTG_DCFG_DSPD_SHIFT) /* Full speed */ +#define OTG_DCFG_NZLSOHSK (1 << 2) /* Bit 2: Non-zero-length status OUT handshake */ + /* Bit 3: Reserved, must be kept at reset value */ +#define OTG_DCFG_DAD_SHIFT (4) /* Bits 4-10: Device address */ +#define OTG_DCFG_DAD_MASK (0x7f << OTG_DCFG_DAD_SHIFT) +#define OTG_DCFG_PFIVL_SHIFT (11) /* Bits 11-12: Periodic frame interval */ +#define OTG_DCFG_PFIVL_MASK (3 << OTG_DCFG_PFIVL_SHIFT) +# define OTG_DCFG_PFIVL_80PCT (0 << OTG_DCFG_PFIVL_SHIFT) /* 80% of the frame interval */ +# define OTG_DCFG_PFIVL_85PCT (1 << OTG_DCFG_PFIVL_SHIFT) /* 85% of the frame interval */ +# define OTG_DCFG_PFIVL_90PCT (2 << OTG_DCFG_PFIVL_SHIFT) /* 90% of the frame interval */ +# define OTG_DCFG_PFIVL_95PCT (3 << OTG_DCFG_PFIVL_SHIFT) /* 95% of the frame interval */ + /* Bits 13-31 Reserved, must be kept at reset value */ +/* Device control register */ + +#define OTG_TESTMODE_DISABLED (0) /* Test mode disabled */ +#define OTG_TESTMODE_J (1) /* Test_J mode */ +#define OTG_TESTMODE_K (2) /* Test_K mode */ +#define OTG_TESTMODE_SE0_NAK (3) /* Test_SE0_NAK mode */ +#define OTG_TESTMODE_PACKET (4) /* Test_Packet mode */ +#define OTG_TESTMODE_FORCE (5) /* Test_Force_Enable */ + +#define OTG_DCTL_RWUSIG (1 << 0) /* Bit 0: Remote wakeup signaling */ +#define OTG_DCTL_SDIS (1 << 1) /* Bit 1: Soft disconnect */ +#define OTG_DCTL_GINSTS (1 << 2) /* Bit 2: Global IN NAK status */ +#define OTG_DCTL_GONSTS (1 << 3) /* Bit 3: Global OUT NAK status */ +#define OTG_DCTL_TCTL_SHIFT (4) /* Bits 4-6: Test control */ +#define OTG_DCTL_TCTL_MASK (7 << OTG_DCTL_TCTL_SHIFT) +# define OTG_DCTL_TCTL_DISABLED (0 << OTG_DCTL_TCTL_SHIFT) /* Test mode disabled */ +# define OTG_DCTL_TCTL_J (1 << OTG_DCTL_TCTL_SHIFT) /* Test_J mode */ +# define OTG_DCTL_TCTL_K (2 << OTG_DCTL_TCTL_SHIFT) /* Test_K mode */ +# define OTG_DCTL_TCTL_SE0_NAK (3 << OTG_DCTL_TCTL_SHIFT) /* Test_SE0_NAK mode */ +# define OTG_DCTL_TCTL_PACKET (4 << OTG_DCTL_TCTL_SHIFT) /* Test_Packet mode */ +# define OTG_DCTL_TCTL_FORCE (5 << OTG_DCTL_TCTL_SHIFT) /* Test_Force_Enable */ +#define OTG_DCTL_SGINAK (1 << 7) /* Bit 7: Set global IN NAK */ +#define OTG_DCTL_CGINAK (1 << 8) /* Bit 8: Clear global IN NAK */ +#define OTG_DCTL_SGONAK (1 << 9) /* Bit 9: Set global OUT NAK */ +#define OTG_DCTL_CGONAK (1 << 10) /* Bit 10: Clear global OUT NAK */ +#define OTG_DCTL_POPRGDNE (1 << 11) /* Bit 11: Power-on programming done */ + /* Bits 12-31: Reserved, must be kept at reset value */ +/* Device status register */ + +#define OTG_DSTS_SUSPSTS (1 << 0) /* Bit 0: Suspend status */ +#define OTG_DSTS_ENUMSPD_SHIFT (1) /* Bits 1-2: Enumerated speed */ +#define OTG_DSTS_ENUMSPD_MASK (3 << OTG_DSTS_ENUMSPD_SHIFT) +# define OTG_DSTS_ENUMSPD_FS (3 << OTG_DSTS_ENUMSPD_MASK) /* Full speed */ + /* Bits 4-7: Reserved, must be kept at reset value */ +#define OTG_DSTS_EERR (1 << 3) /* Bit 3: Erratic error */ +#define OTG_DSTS_SOFFN_SHIFT (8) /* Bits 8-21: Frame number of the received SOF */ +#define OTG_DSTS_SOFFN_MASK (0x3fff << OTG_DSTS_SOFFN_SHIFT) +#define OTG_DSTS_SOFFN0 (1 << 8) /* Bits 8: Frame number even/odd bit */ +#define OTG_DSTS_SOFFN_EVEN 0 +#define OTG_DSTS_SOFFN_ODD OTG_DSTS_SOFFN0 + /* Bits 22-31: Reserved, must be kept at reset value */ +/* Device IN endpoint common interrupt mask register */ + +#define OTG_DIEPMSK_XFRCM (1 << 0) /* Bit 0: Transfer completed interrupt mask */ +#define OTG_DIEPMSK_EPDM (1 << 1) /* Bit 1: Endpoint disabled interrupt mask */ + /* Bit 2: Reserved, must be kept at reset value */ +#define OTG_DIEPMSK_TOM (1 << 3) /* Bit 3: Timeout condition mask (Non-isochronous endpoints) */ +#define OTG_DIEPMSK_ITTXFEMSK (1 << 4) /* Bit 4: IN token received when TxFIFO empty mask */ +#define OTG_DIEPMSK_INEPNMM (1 << 5) /* Bit 5: IN token received with EP mismatch mask */ +#define OTG_DIEPMSK_INEPNEM (1 << 6) /* Bit 6: IN endpoint NAK effective mask */ + /* Bits 7-31: Reserved, must be kept at reset value */ +/* Device OUT endpoint common interrupt mask register */ + +#define OTG_DOEPMSK_XFRCM (1 << 0) /* Bit 0: Transfer completed interrupt mask */ +#define OTG_DOEPMSK_EPDM (1 << 1) /* Bit 1: Endpoint disabled interrupt mask */ + /* Bit 2: Reserved, must be kept at reset value */ +#define OTG_DOEPMSK_STUPM (1 << 3) /* Bit 3: SETUP phase done mask */ +#define OTG_DOEPMSK_OTEPDM (1 << 4) /* Bit 4: OUT token received when endpoint disabled mask */ + /* Bits 5-31: Reserved, must be kept at reset value */ +/* Device all endpoints interrupt and All endpoints interrupt mask registers */ + +#define OTG_DAINT_IEP_SHIFT (0) /* Bits 0-15: IN endpoint interrupt bits */ +#define OTG_DAINT_IEP_MASK (0xffff << OTG_DAINT_IEP_SHIFT) +# define OTG_DAINT_IEP(n) (1 << (n)) +#define OTG_DAINT_OEP_SHIFT (16) /* Bits 16-31: OUT endpoint interrupt bits */ +#define OTG_DAINT_OEP_MASK (0xffff << OTG_DAINT_OEP_SHIFT) +# define OTG_DAINT_OEP(n) (1 << ((n)+16)) + +/* Device VBUS discharge time register */ + +#define OTG_DVBUSDIS_MASK (0xffff) + +/* Device VBUS pulsing time register */ + +#define OTG_DVBUSPULSE_MASK (0xfff) + +/* Device IN endpoint FIFO empty interrupt mask register */ + +#define OTG_DIEPEMPMSK(n) (1 << (n)) + +/* Device control IN endpoint 0 control register */ + +#define OTG_DIEPCTL0_MPSIZ_SHIFT (0) /* Bits 0-1: Maximum packet size */ +#define OTG_DIEPCTL0_MPSIZ_MASK (3 << OTG_DIEPCTL0_MPSIZ_SHIFT) +# define OTG_DIEPCTL0_MPSIZ_64 (0 << OTG_DIEPCTL0_MPSIZ_SHIFT) /* 64 bytes */ +# define OTG_DIEPCTL0_MPSIZ_32 (1 << OTG_DIEPCTL0_MPSIZ_SHIFT) /* 32 bytes */ +# define OTG_DIEPCTL0_MPSIZ_16 (2 << OTG_DIEPCTL0_MPSIZ_SHIFT) /* 16 bytes */ +# define OTG_DIEPCTL0_MPSIZ_8 (3 << OTG_DIEPCTL0_MPSIZ_SHIFT) /* 8 bytes */ + /* Bits 2-14: Reserved, must be kept at reset value */ +#define OTG_DIEPCTL0_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ + /* Bit 16: Reserved, must be kept at reset value */ +#define OTG_DIEPCTL0_NAKSTS (1 << 17) /* Bit 17: NAK status */ +#define OTG_DIEPCTL0_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ +#define OTG_DIEPCTL0_EPTYP_MASK (3 << OTG_DIEPCTL0_EPTYP_SHIFT) +# define OTG_DIEPCTL0_EPTYP_CTRL (0 << OTG_DIEPCTL0_EPTYP_SHIFT) /* Control (hard-coded) */ + /* Bit 20: Reserved, must be kept at reset value */ +#define OTG_DIEPCTL0_STALL (1 << 21) /* Bit 21: STALL handshake */ +#define OTG_DIEPCTL0_TXFNUM_SHIFT (22) /* Bits 22-25: TxFIFO number */ +#define OTG_DIEPCTL0_TXFNUM_MASK (15 << OTG_DIEPCTL0_TXFNUM_SHIFT) +#define OTG_DIEPCTL0_CNAK (1 << 26) /* Bit 26: Clear NAK */ +#define OTG_DIEPCTL0_SNAK (1 << 27) /* Bit 27: Set NAK */ + /* Bits 28-29: Reserved, must be kept at reset value */ +#define OTG_DIEPCTL0_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ +#define OTG_DIEPCTL0_EPENA (1 << 31) /* Bit 31: Endpoint enable */ + +/* Device control IN endpoint n control register */ + +#define OTG_DIEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */ +#define OTG_DIEPCTL_MPSIZ_MASK (0x7ff << OTG_DIEPCTL_MPSIZ_SHIFT) + /* Bits 11-14: Reserved, must be kept at reset value */ +#define OTG_DIEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ +#define OTG_DIEPCTL_EONUM (1 << 16) /* Bit 16: Even/odd frame */ +# define OTG_DIEPCTL_EVEN (0) +# define OTG_DIEPCTL_ODD OTG_DIEPCTL_EONUM +# define OTG_DIEPCTL_DATA0 (0) +# define OTG_DIEPCTL_DATA1 OTG_DIEPCTL_EONUM +#define OTG_DIEPCTL_NAKSTS (1 << 17) /* Bit 17: NAK status */ +#define OTG_DIEPCTL_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ +#define OTG_DIEPCTL_EPTYP_MASK (3 << OTG_DIEPCTL_EPTYP_SHIFT) +# define OTG_DIEPCTL_EPTYP_CTRL (0 << OTG_DIEPCTL_EPTYP_SHIFT) /* Control */ +# define OTG_DIEPCTL_EPTYP_ISOC (1 << OTG_DIEPCTL_EPTYP_SHIFT) /* Isochronous */ +# define OTG_DIEPCTL_EPTYP_BULK (2 << OTG_DIEPCTL_EPTYP_SHIFT) /* Bulk */ +# define OTG_DIEPCTL_EPTYP_INTR (3 << OTG_DIEPCTL_EPTYP_SHIFT) /* Interrupt */ + /* Bit 20: Reserved, must be kept at reset value */ +#define OTG_DIEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */ +#define OTG_DIEPCTL_TXFNUM_SHIFT (22) /* Bits 22-25: TxFIFO number */ +#define OTG_DIEPCTL_TXFNUM_MASK (15 << OTG_DIEPCTL_TXFNUM_SHIFT) +#define OTG_DIEPCTL_CNAK (1 << 26) /* Bit 26: Clear NAK */ +#define OTG_DIEPCTL_SNAK (1 << 27) /* Bit 27: Set NAK */ +#define OTG_DIEPCTL_SD0PID (1 << 28) /* Bit 28: Set DATA0 PID (interrupt/bulk) */ +#define OTG_DIEPCTL_SEVNFRM (1 << 28) /* Bit 28: Set even frame (isochronous)) */ +#define OTG_DIEPCTL_SODDFRM (1 << 29) /* Bit 29: Set odd frame (isochronous) */ +#define OTG_DIEPCTL_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ +#define OTG_DIEPCTL_EPENA (1 << 31) /* Bit 31: Endpoint enable */ + +/* Device endpoint-n interrupt register */ + +#define OTG_DIEPINT_XFRC (1 << 0) /* Bit 0: Transfer completed interrupt */ +#define OTG_DIEPINT_EPDISD (1 << 1) /* Bit 1: Endpoint disabled interrupt */ + /* Bit 2: Reserved, must be kept at reset value */ +#define OTG_DIEPINT_TOC (1 << 3) /* Bit 3: Timeout condition */ +#define OTG_DIEPINT_ITTXFE (1 << 4) /* Bit 4: IN token received when TxFIFO is empty */ + /* Bit 5: Reserved, must be kept at reset value */ +#define OTG_DIEPINT_INEPNE (1 << 6) /* Bit 6: IN endpoint NAK effective */ +#define OTG_DIEPINT_TXFE (1 << 7) /* Bit 7: Transmit FIFO empty */ + /* Bits 8-31: Reserved, must be kept at reset value */ +/* Device IN endpoint 0 transfer size register */ + +#define OTG_DIEPTSIZ0_XFRSIZ_SHIFT (0) /* Bits 0-6: Transfer size */ +#define OTG_DIEPTSIZ0_XFRSIZ_MASK (0x7f << OTG_DIEPTSIZ0_XFRSIZ_SHIFT) + /* Bits 7-18: Reserved, must be kept at reset value */ +#define OTG_DIEPTSIZ0_PKTCNT_SHIFT (19) /* Bits 19-20: Packet count */ +#define OTG_DIEPTSIZ0_PKTCNT_MASK (3 << OTG_DIEPTSIZ0_PKTCNT_SHIFT) + /* Bits 21-31: Reserved, must be kept at reset value */ +/* Device IN endpoint n transfer size register */ + +#define OTG_DIEPTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */ +#define OTG_DIEPTSIZ_XFRSIZ_MASK (0x7ffff << OTG_DIEPTSIZ_XFRSIZ_SHIFT) +#define OTG_DIEPTSIZ_PKTCNT_SHIFT (19) /* Bit 19-28: Packet count */ +#define OTG_DIEPTSIZ_PKTCNT_MASK (0x3ff << OTG_DIEPTSIZ_PKTCNT_SHIFT) +#define OTG_DIEPTSIZ_MCNT_SHIFT (29) /* Bits 29-30: Multi count */ +#define OTG_DIEPTSIZ_MCNT_MASK (3 << OTG_DIEPTSIZ_MCNT_SHIFT) + /* Bit 31: Reserved, must be kept at reset value */ +/* Device OUT endpoint TxFIFO status register */ + +#define OTG_DTXFSTS_MASK (0xffff) + +/* Device OUT endpoint 0 control register */ + +#define OTG_DOEPCTL0_MPSIZ_SHIFT (0) /* Bits 0-1: Maximum packet size */ +#define OTG_DOEPCTL0_MPSIZ_MASK (3 << OTG_DOEPCTL0_MPSIZ_SHIFT) +# define OTG_DOEPCTL0_MPSIZ_64 (0 << OTG_DOEPCTL0_MPSIZ_SHIFT) /* 64 bytes */ +# define OTG_DOEPCTL0_MPSIZ_32 (1 << OTG_DOEPCTL0_MPSIZ_SHIFT) /* 32 bytes */ +# define OTG_DOEPCTL0_MPSIZ_16 (2 << OTG_DOEPCTL0_MPSIZ_SHIFT) /* 16 bytes */ +# define OTG_DOEPCTL0_MPSIZ_8 (3 << OTG_DOEPCTL0_MPSIZ_SHIFT) /* 8 bytes */ + /* Bits 2-14: Reserved, must be kept at reset value */ +#define OTG_DOEPCTL0_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ + /* Bit 16: Reserved, must be kept at reset value */ +#define OTG_DOEPCTL0_NAKSTS (1 << 17) /* Bit 17: NAK status */ +#define OTG_DOEPCTL0_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ +#define OTG_DOEPCTL0_EPTYP_MASK (3 << OTG_DOEPCTL0_EPTYP_SHIFT) +# define OTG_DOEPCTL0_EPTYP_CTRL (0 << OTG_DOEPCTL0_EPTYP_SHIFT) /* Control (hard-coded) */ +#define OTG_DOEPCTL0_SNPM (1 << 20) /* Bit 20: Snoop mode */ +#define OTG_DOEPCTL0_STALL (1 << 21) /* Bit 21: STALL handshake */ + /* Bits 22-25: Reserved, must be kept at reset value */ +#define OTG_DOEPCTL0_CNAK (1 << 26) /* Bit 26: Clear NAK */ +#define OTG_DOEPCTL0_SNAK (1 << 27) /* Bit 27: Set NAK */ + /* Bits 28-29: Reserved, must be kept at reset value */ +#define OTG_DOEPCTL0_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ +#define OTG_DOEPCTL0_EPENA (1 << 31) /* Bit 31: Endpoint enable */ + +/* Device OUT endpoint n control register */ + +#define OTG_DOEPCTL_MPSIZ_SHIFT (0) /* Bits 0-10: Maximum packet size */ +#define OTG_DOEPCTL_MPSIZ_MASK (0x7ff << OTG_DOEPCTL_MPSIZ_SHIFT) + /* Bits 11-14: Reserved, must be kept at reset value */ +#define OTG_DOEPCTL_USBAEP (1 << 15) /* Bit 15: USB active endpoint */ +#define OTG_DOEPCTL_DPID (1 << 16) /* Bit 16: Endpoint data PID (interrupt/buld) */ +# define OTG_DOEPCTL_DATA0 (0) +# define OTG_DOEPCTL_DATA1 OTG_DOEPCTL_DPID +#define OTG_DOEPCTL_EONUM (1 << 16) /* Bit 16: Even/odd frame (isochronous) */ +# define OTG_DOEPCTL_EVEN (0) +# define OTG_DOEPCTL_ODD OTG_DOEPCTL_EONUM +#define OTG_DOEPCTL_NAKSTS (1 << 17) /* Bit 17: NAK status */ +#define OTG_DOEPCTL_EPTYP_SHIFT (18) /* Bits 18-19: Endpoint type */ +#define OTG_DOEPCTL_EPTYP_MASK (3 << OTG_DOEPCTL_EPTYP_SHIFT) +# define OTG_DOEPCTL_EPTYP_CTRL (0 << OTG_DOEPCTL_EPTYP_SHIFT) /* Control */ +# define OTG_DOEPCTL_EPTYP_ISOC (1 << OTG_DOEPCTL_EPTYP_SHIFT) /* Isochronous */ +# define OTG_DOEPCTL_EPTYP_BULK (2 << OTG_DOEPCTL_EPTYP_SHIFT) /* Bulk */ +# define OTG_DOEPCTL_EPTYP_INTR (3 << OTG_DOEPCTL_EPTYP_SHIFT) /* Interrupt */ +#define OTG_DOEPCTL_SNPM (1 << 20) /* Bit 20: Snoop mode */ +#define OTG_DOEPCTL_STALL (1 << 21) /* Bit 21: STALL handshake */ + /* Bits 22-25: Reserved, must be kept at reset value */ +#define OTG_DOEPCTL_CNAK (1 << 26) /* Bit 26: Clear NAK */ +#define OTG_DOEPCTL_SNAK (1 << 27) /* Bit 27: Set NAK */ +#define OTG_DOEPCTL_SD0PID (1 << 28) /* Bit 28: Set DATA0 PID (interrupt/bulk) */ +#define OTG_DOEPCTL_SEVNFRM (1 << 28) /* Bit 28: Set even frame (isochronous) */ +#define OTG_DOEPCTL_SD1PID (1 << 29) /* Bit 29: Set DATA1 PID (interrupt/bulk) */ +#define OTG_DOEPCTL_SODDFRM (1 << 29) /* Bit 29: Set odd frame (isochronous */ +#define OTG_DOEPCTL_EPDIS (1 << 30) /* Bit 30: Endpoint disable */ +#define OTG_DOEPCTL_EPENA (1 << 31) /* Bit 31: Endpoint enable */ + +/* Device endpoint-n interrupt register */ + +#define OTG_DOEPINT_XFRC (1 << 0) /* Bit 0: Transfer completed interrupt */ +#define OTG_DOEPINT_EPDISD (1 << 1) /* Bit 1: Endpoint disabled interrupt */ + /* Bit 2: Reserved, must be kept at reset value */ +#define OTG_DOEPINT_SETUP (1 << 3) /* Bit 3: SETUP phase done */ +#define OTG_DOEPINT_OTEPDIS (1 << 4) /* Bit 4: OUT token received when endpoint disabled */ + /* Bit 5: Reserved, must be kept at reset value */ +#define OTG_DOEPINT_B2BSTUP (1 << 6) /* Bit 6: Back-to-back SETUP packets received */ + /* Bits 7-31: Reserved, must be kept at reset value */ +/* Device OUT endpoint-0 transfer size register */ + +#define OTG_DOEPTSIZ0_XFRSIZ_SHIFT (0) /* Bits 0-6: Transfer size */ +#define OTG_DOEPTSIZ0_XFRSIZ_MASK (0x7f << OTG_DOEPTSIZ0_XFRSIZ_SHIFT) + /* Bits 7-18: Reserved, must be kept at reset value */ +#define OTG_DOEPTSIZ0_PKTCNT (1 << 19) /* Bit 19 PKTCNT: Packet count */ + /* Bits 20-28: Reserved, must be kept at reset value */ +#define OTG_DOEPTSIZ0_STUPCNT_SHIFT (29) /* Bits 29-30: SETUP packet count */ +#define OTG_DOEPTSIZ0_STUPCNT_MASK (3 << OTG_DOEPTSIZ0_STUPCNT_SHIFT) + /* Bit 31: Reserved, must be kept at reset value */ +/* Device OUT endpoint-n transfer size register */ + +#define OTG_DOEPTSIZ_XFRSIZ_SHIFT (0) /* Bits 0-18: Transfer size */ +#define OTG_DOEPTSIZ_XFRSIZ_MASK (0x7ffff << OTG_DOEPTSIZ_XFRSIZ_SHIFT) +#define OTG_DOEPTSIZ_PKTCNT_SHIFT (19) /* Bit 19-28: Packet count */ +#define OTG_DOEPTSIZ_PKTCNT_MASK (0x3ff << OTG_DOEPTSIZ_PKTCNT_SHIFT) +#define OTG_DOEPTSIZ_STUPCNT_SHIFT (29) /* Bits 29-30: SETUP packet count */ +#define OTG_DOEPTSIZ_STUPCNT_MASK (3 << OTG_DOEPTSIZ_STUPCNT_SHIFT) +#define OTG_DOEPTSIZ_RXDPID_SHIFT (29) /* Bits 29-30: Received data PID */ +#define OTG_DOEPTSIZ_RXDPID_MASK (3 << OTG_DOEPTSIZ_RXDPID_SHIFT) +# define OTG_DOEPTSIZ_RXDPID_DATA0 (0 << OTG_DOEPTSIZ_RXDPID_SHIFT) +# define OTG_DOEPTSIZ_RXDPID_DATA2 (1 << OTG_DOEPTSIZ_RXDPID_SHIFT) +# define OTG_DOEPTSIZ_RXDPID_DATA1 (2 << OTG_DOEPTSIZ_RXDPID_SHIFT) +# define OTG_DOEPTSIZ_RXDPID_MDATA (3 << OTG_DOEPTSIZ_RXDPID_SHIFT) + /* Bit 31: Reserved, must be kept at reset value */ +/* Power and clock gating control register */ + +#define OTG_PCGCCTL_STPPCLK (1 << 0) /* Bit 0: Stop PHY clock */ +#define OTG_PCGCCTL_GATEHCLK (1 << 1) /* Bit 1: Gate HCLK */ + /* Bits 2-3: Reserved, must be kept at reset value */ +#define OTG_PCGCCTL_PHYSUSP (1 << 4) /* Bit 4: PHY Suspended */ + /* Bits 5-31: Reserved, must be kept at reset value */ + +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_OTG_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32_rtcc.h b/arch/arm/src/stm32f7/chip/stm32_rtcc.h new file mode 100644 index 0000000000000000000000000000000000000000..262a48633cbbafd8b4502f9490030ca6d560876b --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32_rtcc.h @@ -0,0 +1,405 @@ +/************************************************************************************ + * arch/arm/src/stm32f7/chip/stm32_rtcc.h + * + * Copyright (C) 2011-2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_RTCC_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_RTCC_H + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define STM32_RTC_TR_OFFSET 0x0000 /* RTC time register */ +#define STM32_RTC_DR_OFFSET 0x0004 /* RTC date register */ +#define STM32_RTC_CR_OFFSET 0x0008 /* RTC control register */ +#define STM32_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */ +#define STM32_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */ +#define STM32_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */ +#define STM32_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */ +#define STM32_RTC_ALRMBR_OFFSET 0x0020 /* RTC alarm B register */ +#define STM32_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */ +#define STM32_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */ +#define STM32_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */ +#define STM32_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */ +#define STM32_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */ +#define STM32_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */ +#define STM32_RTC_CALR_OFFSET 0x003c /* RTC calibration register */ +#define STM32_RTC_TAMPCR_OFFSET 0x0040 /* RTC tamper configuration register */ +#define STM32_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */ +#define STM32_RTC_ALRMBSSR_OFFSET 0x0048 /* RTC alarm B sub second register */ +#define STM32_RTC_OR_OFFSET 0x004c /* RTC option register */ + +#define STM32_RTC_BKR_OFFSET(n) (0x0050+((n)<<2)) +#define STM32_RTC_BK0R_OFFSET 0x0050 /* RTC backup register 0 */ +#define STM32_RTC_BK1R_OFFSET 0x0054 /* RTC backup register 1 */ +#define STM32_RTC_BK2R_OFFSET 0x0058 /* RTC backup register 2 */ +#define STM32_RTC_BK3R_OFFSET 0x005c /* RTC backup register 3 */ +#define STM32_RTC_BK4R_OFFSET 0x0060 /* RTC backup register 4 */ +#define STM32_RTC_BK5R_OFFSET 0x0064 /* RTC backup register 5 */ +#define STM32_RTC_BK6R_OFFSET 0x0068 /* RTC backup register 6 */ +#define STM32_RTC_BK7R_OFFSET 0x006c /* RTC backup register 7 */ +#define STM32_RTC_BK8R_OFFSET 0x0070 /* RTC backup register 8 */ +#define STM32_RTC_BK9R_OFFSET 0x0074 /* RTC backup register 9 */ +#define STM32_RTC_BK10R_OFFSET 0x0078 /* RTC backup register 10 */ +#define STM32_RTC_BK11R_OFFSET 0x007c /* RTC backup register 11 */ +#define STM32_RTC_BK12R_OFFSET 0x0080 /* RTC backup register 12 */ +#define STM32_RTC_BK13R_OFFSET 0x0084 /* RTC backup register 13 */ +#define STM32_RTC_BK14R_OFFSET 0x0088 /* RTC backup register 14 */ +#define STM32_RTC_BK15R_OFFSET 0x008c /* RTC backup register 15 */ +#define STM32_RTC_BK16R_OFFSET 0x0090 /* RTC backup register 16 */ +#define STM32_RTC_BK17R_OFFSET 0x0094 /* RTC backup register 17 */ +#define STM32_RTC_BK18R_OFFSET 0x0098 /* RTC backup register 18 */ +#define STM32_RTC_BK19R_OFFSET 0x009c /* RTC backup register 19 */ +#define STM32_RTC_BK20R_OFFSET 0x00a0 /* RTC backup register 20 */ +#define STM32_RTC_BK21R_OFFSET 0x00a4 /* RTC backup register 21 */ +#define STM32_RTC_BK22R_OFFSET 0x00a8 /* RTC backup register 22 */ +#define STM32_RTC_BK23R_OFFSET 0x00ac /* RTC backup register 23 */ +#define STM32_RTC_BK24R_OFFSET 0x00b0 /* RTC backup register 24 */ +#define STM32_RTC_BK25R_OFFSET 0x00b4 /* RTC backup register 25 */ +#define STM32_RTC_BK26R_OFFSET 0x00b8 /* RTC backup register 26 */ +#define STM32_RTC_BK27R_OFFSET 0x00bc /* RTC backup register 27 */ +#define STM32_RTC_BK28R_OFFSET 0x00c0 /* RTC backup register 28 */ +#define STM32_RTC_BK29R_OFFSET 0x00c4 /* RTC backup register 29 */ +#define STM32_RTC_BK30R_OFFSET 0x00c8 /* RTC backup register 30 */ +#define STM32_RTC_BK31R_OFFSET 0x00cc /* RTC backup register 31 */ + +/* Register Addresses ***************************************************************/ + +#define STM32_RTC_TR (STM32_RTC_BASE+STM32_RTC_TR_OFFSET) +#define STM32_RTC_DR (STM32_RTC_BASE+STM32_RTC_DR_OFFSET) +#define STM32_RTC_CR (STM32_RTC_BASE+STM32_RTC_CR_OFFSET) +#define STM32_RTC_ISR (STM32_RTC_BASE+STM32_RTC_ISR_OFFSET) +#define STM32_RTC_PRER (STM32_RTC_BASE+STM32_RTC_PRER_OFFSET) +#define STM32_RTC_WUTR (STM32_RTC_BASE+STM32_RTC_WUTR_OFFSET) +#define STM32_RTC_ALRMAR (STM32_RTC_BASE+STM32_RTC_ALRMAR_OFFSET) +#define STM32_RTC_ALRMBR (STM32_RTC_BASE+STM32_RTC_ALRMBR_OFFSET) +#define STM32_RTC_WPR (STM32_RTC_BASE+STM32_RTC_WPR_OFFSET) +#define STM32_RTC_SSR (STM32_RTC_BASE+STM32_RTC_SSR_OFFSET) +#define STM32_RTC_SHIFTR (STM32_RTC_BASE+STM32_RTC_SHIFTR_OFFSET) +#define STM32_RTC_TSTR (STM32_RTC_BASE+STM32_RTC_TSTR_OFFSET) +#define STM32_RTC_TSDR (STM32_RTC_BASE+STM32_RTC_TSDR_OFFSET) +#define STM32_RTC_TSSSR (STM32_RTC_BASE+STM32_RTC_TSSSR_OFFSET) +#define STM32_RTC_CALR (STM32_RTC_BASE+STM32_RTC_CALR_OFFSET) +#define STM32_RTC_TAMPCR (STM32_RTC_BASE+STM32_RTC_TAMPCR_OFFSET) +#define STM32_RTC_ALRMASSR (STM32_RTC_BASE+STM32_RTC_ALRMASSR_OFFSET) +#define STM32_RTC_ALRMBSSR (STM32_RTC_BASE+STM32_RTC_ALRMBSSR_OFFSET) + +#define STM32_RTC_BKR(n) (STM32_RTC_BASE+STM32_RTC_BKR_OFFSET(n)) +#define STM32_RTC_BK0R (STM32_RTC_BASE+STM32_RTC_BK0R_OFFSET) +#define STM32_RTC_BK1R (STM32_RTC_BASE+STM32_RTC_BK1R_OFFSET) +#define STM32_RTC_BK2R (STM32_RTC_BASE+STM32_RTC_BK2R_OFFSET) +#define STM32_RTC_BK3R (STM32_RTC_BASE+STM32_RTC_BK3R_OFFSET) +#define STM32_RTC_BK4R (STM32_RTC_BASE+STM32_RTC_BK4R_OFFSET) +#define STM32_RTC_BK5R (STM32_RTC_BASE+STM32_RTC_BK5R_OFFSET) +#define STM32_RTC_BK6R (STM32_RTC_BASE+STM32_RTC_BK6R_OFFSET) +#define STM32_RTC_BK7R (STM32_RTC_BASE+STM32_RTC_BK7R_OFFSET) +#define STM32_RTC_BK8R (STM32_RTC_BASE+STM32_RTC_BK8R_OFFSET) +#define STM32_RTC_BK9R (STM32_RTC_BASE+STM32_RTC_BK9R_OFFSET) +#define STM32_RTC_BK10R (STM32_RTC_BASE+STM32_RTC_BK10R_OFFSET) +#define STM32_RTC_BK11R (STM32_RTC_BASE+STM32_RTC_BK11R_OFFSET) +#define STM32_RTC_BK12R (STM32_RTC_BASE+STM32_RTC_BK12R_OFFSET) +#define STM32_RTC_BK13R (STM32_RTC_BASE+STM32_RTC_BK13R_OFFSET) +#define STM32_RTC_BK14R (STM32_RTC_BASE+STM32_RTC_BK14R_OFFSET) +#define STM32_RTC_BK15R (STM32_RTC_BASE+STM32_RTC_BK15R_OFFSET) +#define STM32_RTC_BK16R (STM32_RTC_BASE+STM32_RTC_BK16R_OFFSET) +#define STM32_RTC_BK17R (STM32_RTC_BASE+STM32_RTC_BK17R_OFFSET) +#define STM32_RTC_BK18R (STM32_RTC_BASE+STM32_RTC_BK18R_OFFSET) +#define STM32_RTC_BK19R (STM32_RTC_BASE+STM32_RTC_BK19R_OFFSET) +#define STM32_RTC_BK20R (STM32_RTC_BASE+STM32_RTC_BK20R_OFFSET) +#define STM32_RTC_BK21R (STM32_RTC_BASE+STM32_RTC_BK21R_OFFSET) +#define STM32_RTC_BK22R (STM32_RTC_BASE+STM32_RTC_BK22R_OFFSET) +#define STM32_RTC_BK23R (STM32_RTC_BASE+STM32_RTC_BK23R_OFFSET) +#define STM32_RTC_BK24R (STM32_RTC_BASE+STM32_RTC_BK24R_OFFSET) +#define STM32_RTC_BK25R (STM32_RTC_BASE+STM32_RTC_BK25R_OFFSET) +#define STM32_RTC_BK26R (STM32_RTC_BASE+STM32_RTC_BK26R_OFFSET) +#define STM32_RTC_BK27R (STM32_RTC_BASE+STM32_RTC_BK27R_OFFSET) +#define STM32_RTC_BK28R (STM32_RTC_BASE+STM32_RTC_BK28R_OFFSET) +#define STM32_RTC_BK29R (STM32_RTC_BASE+STM32_RTC_BK29R_OFFSET) +#define STM32_RTC_BK30R (STM32_RTC_BASE+STM32_RTC_BK30R_OFFSET) +#define STM32_RTC_BK31R (STM32_RTC_BASE+STM32_RTC_BK31R_OFFSET) + +#define STM32_RTC_BKCOUNT 32 + +/* Register Bitfield Definitions ****************************************************/ + +/* RTC time register */ + +#define RTC_TR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format */ +#define RTC_TR_SU_MASK (15 << RTC_TR_SU_SHIFT) +#define RTC_TR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format */ +#define RTC_TR_ST_MASK (7 << RTC_TR_ST_SHIFT) +#define RTC_TR_MNU_SHIFT (8) /* Bit 8-11: Minute units in BCD format */ +#define RTC_TR_MNU_MASK (15 << RTC_TR_MNU_SHIFT) +#define RTC_TR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format */ +#define RTC_TR_MNT_MASK (7 << RTC_TR_MNT_SHIFT) +#define RTC_TR_HU_SHIFT (16) /* Bit 16-19: Hour units in BCD format */ +#define RTC_TR_HU_MASK (15 << RTC_TR_HU_SHIFT) +#define RTC_TR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format */ +#define RTC_TR_HT_MASK (3 << RTC_TR_HT_SHIFT) +#define RTC_TR_PM (1 << 22) /* Bit 22: AM/PM notation */ +#define RTC_TR_RESERVED_BITS (0xff808080) + +/* RTC date register */ + +#define RTC_DR_DU_SHIFT (0) /* Bits 0-3: Date units in BCD format */ +#define RTC_DR_DU_MASK (15 << RTC_DR_DU_SHIFT) +#define RTC_DR_DT_SHIFT (4) /* Bits 4-5: Date tens in BCD format */ +#define RTC_DR_DT_MASK (3 << RTC_DR_DT_SHIFT) +#define RTC_DR_MU_SHIFT (8) /* Bits 8-11: Month units in BCD format */ +#define RTC_DR_MU_MASK (15 << RTC_DR_MU_SHIFT) +#define RTC_DR_MT (1 << 12) /* Bit 12: Month tens in BCD format */ +#define RTC_DR_WDU_SHIFT (13) /* Bits 13-15: Week day units */ +#define RTC_DR_WDU_MASK (7 << RTC_DR_WDU_SHIFT) +# define RTC_DR_WDU_MONDAY (1 << RTC_DR_WDU_SHIFT) +# define RTC_DR_WDU_TUESDAY (2 << RTC_DR_WDU_SHIFT) +# define RTC_DR_WDU_WEDNESDAY (3 << RTC_DR_WDU_SHIFT) +# define RTC_DR_WDU_THURSDAY (4 << RTC_DR_WDU_SHIFT) +# define RTC_DR_WDU_FRIDAY (5 << RTC_DR_WDU_SHIFT) +# define RTC_DR_WDU_SATURDAY (6 << RTC_DR_WDU_SHIFT) +# define RTC_DR_WDU_SUNDAY (7 << RTC_DR_WDU_SHIFT) +#define RTC_DR_YU_SHIFT (16) /* Bits 16-19: Year units in BCD format */ +#define RTC_DR_YU_MASK (15 << RTC_DR_YU_SHIFT) +#define RTC_DR_YT_SHIFT (20) /* Bits 20-23: Year tens in BCD format */ +#define RTC_DR_YT_MASK (15 << RTC_DR_YT_SHIFT) +#define RTC_DR_RESERVED_BITS (0xff0000c0) + +/* RTC control register */ + +#define RTC_CR_WUCKSEL_SHIFT (0) /* Bits 0-2: Wakeup clock selection */ +#define RTC_CR_WUCKSEL_MASK (7 << RTC_CR_WUCKSEL_SHIFT) +# define RTC_CR_WUCKSEL_RTCDIV16 (0 << RTC_CR_WUCKSEL_SHIFT) /* 000: RTC/16 clock is selected */ +# define RTC_CR_WUCKSEL_RTCDIV8 (1 << RTC_CR_WUCKSEL_SHIFT) /* 001: RTC/8 clock is selected */ +# define RTC_CR_WUCKSEL_RTCDIV4 (2 << RTC_CR_WUCKSEL_SHIFT) /* 010: RTC/4 clock is selected */ +# define RTC_CR_WUCKSEL_RTCDIV2 (3 << RTC_CR_WUCKSEL_SHIFT) /* 011: RTC/2 clock is selected */ +# define RTC_CR_WUCKSEL_CKSPRE (4 << RTC_CR_WUCKSEL_SHIFT) /* 10x: ck_spre clock is selected */ +# define RTC_CR_WUCKSEL_CKSPREADD (6 << RTC_CR_WUCKSEL_SHIFT) /* 11x: ck_spr clock and 216 added WUT counter */ +#define RTC_CR_TSEDGE (1 << 3) /* Bit 3: Timestamp event active edge */ +#define RTC_CR_REFCKON (1 << 4) /* Bit 4: Reference clock detection enable (50 or 60 Hz) */ +#define RTC_CR_BYPSHAD (1 << 5) /* Bit 5: Bypass the shadow registers */ +#define RTC_CR_FMT (1 << 6) /* Bit 6: Hour format */ +#define RTC_CR_ALRAE (1 << 8) /* Bit 8: Alarm A enable */ +#define RTC_CR_ALRBE (1 << 9) /* Bit 9: Alarm B enable */ +#define RTC_CR_WUTE (1 << 10) /* Bit 10: Wakeup timer enable */ +#define RTC_CR_TSE (1 << 11) /* Bit 11: Time stamp enable */ +#define RTC_CR_ALRAIE (1 << 12) /* Bit 12: Alarm A interrupt enable */ +#define RTC_CR_ALRBIE (1 << 13) /* Bit 13: Alarm B interrupt enable */ +#define RTC_CR_WUTIE (1 << 14) /* Bit 14: Wakeup timer interrupt enable */ +#define RTC_CR_TSIE (1 << 15) /* Bit 15: Timestamp interrupt enable */ +#define RTC_CR_ADD1H (1 << 16) /* Bit 16: Add 1 hour (summer time change) */ +#define RTC_CR_SUB1H (1 << 17) /* Bit 17: Subtract 1 hour (winter time change) */ +#define RTC_CR_BKP (1 << 18) /* Bit 18: Backup */ +#define RTC_CR_COSEL (1 << 19) /* Bit 19 : Calibration output selection */ +#define RTC_CR_POL (1 << 20) /* Bit 20: Output polarity */ +#define RTC_CR_OSEL_SHIFT (21) /* Bits 21-22: Output selection */ +#define RTC_CR_OSEL_MASK (3 << RTC_CR_OSEL_SHIFT) +# define RTC_CR_OSEL_DISABLED (0 << RTC_CR_OSEL_SHIFT) /* 00: Output disabled */ +# define RTC_CR_OSEL_ALRMA (1 << RTC_CR_OSEL_SHIFT) /* 01: Alarm A output enabled */ +# define RTC_CR_OSEL_ALRMB (2 << RTC_CR_OSEL_SHIFT) /* 10: Alarm B output enabled */ +# define RTC_CR_OSEL_WUT (3 << RTC_CR_OSEL_SHIFT) /* 11: Wakeup output enabled */ +#define RTC_CR_COE (1 << 23) /* Bit 23: Calibration output enable */ +#define RTC_CR_ITSE (1 << 24) /* Bit 24: Timestamp on internal event enable */ + +/* RTC initialization and status register */ + +#define RTC_ISR_ALRAWF (1 << 0) /* Bit 0: Alarm A write flag */ +#define RTC_ISR_ALRBWF (1 << 1) /* Bit 1: Alarm B write flag */ +#define RTC_ISR_WUTWF (1 << 2) /* Bit 2: Wakeup timer write flag */ +#define RTC_ISR_SHPF (1 << 3) /* Bit 3: Shift operation pending */ +#define RTC_ISR_INITS (1 << 4) /* Bit 4: Initialization status flag */ +#define RTC_ISR_RSF (1 << 5) /* Bit 5: Registers synchronization flag */ +#define RTC_ISR_INITF (1 << 6) /* Bit 6: Initialization flag */ +#define RTC_ISR_INIT (1 << 7) /* Bit 7: Initialization mode */ +#define RTC_ISR_ALRAF (1 << 8) /* Bit 8: Alarm A flag */ +#define RTC_ISR_ALRBF (1 << 9) /* Bit 9: Alarm B flag */ +#define RTC_ISR_WUTF (1 << 10) /* Bit 10: Wakeup timer flag */ +#define RTC_ISR_TSF (1 << 11) /* Bit 11: Timestamp flag */ +#define RTC_ISR_TSOVF (1 << 12) /* Bit 12: Timestamp overflow flag */ +#define RTC_ISR_TAMP1F (1 << 13) /* Bit 13: Tamper detection flag */ +#define RTC_ISR_TAMP2F (1 << 14) /* Bit 14: TAMPER2 detection flag */ +#define RTC_ISR_TAMP3F (1 << 15) /* Bit 15: TAMPER3 detection flag */ +#define RTC_ISR_RECALPF (1 << 16) /* Bit 16: Recalibration pending Flag */ +#define RTC_ISR_ITSF (1 << 17) /* Bit 17:Internal tTime-stamp flagg */ +#define RTC_ISR_ALLFLAGS (0x0003ffff) + +/* RTC prescaler register */ + +#define RTC_PRER_PREDIV_S_SHIFT (0) /* Bits 0-14: Synchronous prescaler factor */ +#define RTC_PRER_PREDIV_S_MASK (0x7fff << RTC_PRER_PREDIV_S_SHIFT) +#define RTC_PRER_PREDIV_A_SHIFT (16) /* Bits 16-22: Asynchronous prescaler factor */ +#define RTC_PRER_PREDIV_A_MASK (0x7f << RTC_PRER_PREDIV_A_SHIFT) + +/* RTC wakeup timer register */ + +#define RTC_WUTR_MASK (0xffff) /* Bits 15:0 Wakeup auto-reload value bits */ + +/* RTC alarm A/B registers */ + +#define RTC_ALRMR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format. */ +#define RTC_ALRMR_SU_MASK (15 << RTC_ALRMR_SU_SHIFT) +#define RTC_ALRMR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format. */ +#define RTC_ALRMR_ST_MASK (7 << RTC_ALRMR_ST_SHIFT) +#define RTC_ALRMR_MSK1 (1 << 7) /* Bit 7 : Alarm A seconds mask */ +#define RTC_ALRMR_MNU_SHIFT (8) /* Bits 8-11: Minute units in BCD format. */ +#define RTC_ALRMR_MNU_MASK (15 << RTC_ALRMR_MNU_SHIFT) +#define RTC_ALRMR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format. */ +#define RTC_ALRMR_MNT_MASK (7 << RTC_ALRMR_MNT_SHIFT) +#define RTC_ALRMR_MSK2 (1 << 15) /* Bit 15 : Alarm A minutes mask */ +#define RTC_ALRMR_HU_SHIFT (16) /* Bits 16-19: Hour units in BCD format. */ +#define RTC_ALRMR_HU_MASK (15 << RTC_ALRMR_HU_SHIFT) +#define RTC_ALRMR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format. */ +#define RTC_ALRMR_HT_MASK (3 << RTC_ALRMR_HT_SHIFT) +#define RTC_ALRMR_PM (1 << 22) /* Bit 22 : AM/PM notation */ +#define RTC_ALRMR_MSK3 (1 << 23) /* Bit 23 : Alarm A hours mask */ +#define RTC_ALRMR_DU_SHIFT (24) /* Bits 24-27: Date units or day in BCD format. */ +#define RTC_ALRMR_DU_MASK (15 << RTC_ALRMR_DU_SHIFT) +#define RTC_ALRMR_DT_SHIFT (28) /* Bits 28-29: Date tens in BCD format. */ +#define RTC_ALRMR_DT_MASK (3 << RTC_ALRMR_DT_SHIFT) +#define RTC_ALRMR_WDSEL (1 << 30) /* Bit 30: Week day selection */ +#define RTC_ALRMR_MSK4 (1 << 31) /* Bit 31: Alarm A date mask */ + +/* RTC write protection register */ + +#define RTC_WPR_MASK (0xff) /* Bits 0-7: Write protection key */ + +/* RTC sub second register */ + +#define RTC_SSR_MASK (0xffff) /* Bits 0-15: Sub second value */ + +/* RTC shift control register */ + +#define RTC_SHIFTR_SUBFS_SHIFT (0) /* Bits 0-14: Subtract a fraction of a second */ +#define RTC_SHIFTR_SUBFS_MASK (0x7ffff << RTC_SHIFTR_SUBFS_SHIFT) +#define RTC_SHIFTR_ADD1S (1 << 31) /* Bit 31: Add one second */ + +/* RTC time stamp time register */ + +#define RTC_TSTR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format. */ +#define RTC_TSTR_SU_MASK (15 << RTC_TSTR_SU_SHIFT) +#define RTC_TSTR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format. */ +#define RTC_TSTR_ST_MASK (7 << RTC_TSTR_ST_SHIFT) +#define RTC_TSTR_MNU_SHIFT (8) /* Bits 8-11: Minute units in BCD format. */ +#define RTC_TSTR_MNU_MASK (15 << RTC_TSTR_MNU_SHIFT) +#define RTC_TSTR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format. */ +#define RTC_TSTR_MNT_MASK (7 << RTC_TSTR_MNT_SHIFT) +#define RTC_TSTR_HU_SHIFT (16) /* Bits 16-19: Hour units in BCD format. */ +#define RTC_TSTR_HU_MASK (15 << RTC_TSTR_HU_SHIFT) +#define RTC_TSTR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format. */ +#define RTC_TSTR_HT_MASK (3 << RTC_TSTR_HT_SHIFT) +#define RTC_TSTR_PM (1 << 22) /* Bit 22: AM/PM notation */ + +/* RTC time stamp date register */ + +#define RTC_TSDR_DU_SHIFT (0) /* Bit 0-3: Date units in BCD format */ +#define RTC_TSDR_DU_MASK (15 << RTC_TSDR_DU_SHIFT) */ +#define RTC_TSDR_DT_SHIFT (4) /* Bits 4-5: Date tens in BCD format */ +#define RTC_TSDR_DT_MASK (3 << RTC_TSDR_DT_SHIFT) +#define RTC_TSDR_MU_SHIFT (8) /* Bits 8-11: Month units in BCD format */ +#define RTC_TSDR_MU_MASK (xx << RTC_TSDR_MU_SHIFT) +#define RTC_TSDR_MT (1 << 12) /* Bit 12: Month tens in BCD format */ +#define RTC_TSDR_WDU_SHIFT (13) /* Bits 13-15: Week day units */ +#define RTC_TSDR_WDU_MASK (7 << RTC_TSDR_WDU_SHIFT) + +/* RTC timestamp sub second register */ + +#define RTC_TSSSR_MASK (0xffff) /* Bits 0-15: Sub second value */ + +/* RTC calibration register */ + +#define RTC_CALR_CALM_SHIFT (0) /* Bits 0-8: Calibration minus */ +#define RTC_CALR_CALM_MASK (0x1ff << RTC_CALR_CALM_SHIFT) +#define RTC_CALR_CALW16 (1 << 13) /* Bit 13: Use a 16-second calibration cycle period */ +#define RTC_CALR_CALW8 (1 << 14) /* Bit 14: Use an 8-second calibration cycle period */ +#define RTC_CALR_CALP (1 << 15) /* Bit 15: Increase frequency of RTC by 488.5 ppm */ + +/* RTC tamper configuration register */ + +#define RTC_TAMPCR_TAMP1E (1 << 0) /* Bit 0: RTC_TAMP1 input detection enable */ +#define RTC_TAMPCR_TAMP1TRG (1 << 1) /* Bit 1: Active level for RTC_TAMP1 input */ +#define RTC_TAMPCR_TAMPIE (1 << 2) /* Bit 2: Tamper interrupt enable */ +#define RTC_TAMPCR_TAMP2E (1 << 3) /* Bit 3: RTC_TAMP2 input detection enable */ +#define RTC_TAMPCR_TAMP2TRG (1 << 4) /* Bit 4: Active level for RTC_TAMP2 input */ +#define RTC_TAMPCR_TAMP3E (1 << 5) /* Bit 5: RTC_TAMP3 detection enable */ +#define RTC_TAMPCR_TAMP3TRG (1 << 6) /* Bit 6: Active level for RTC_TAMP3 input */ +#define RTC_TAMPCR_TAMPTS (1 << 7) /* Bit 7: Activate timestamp on tamper detection event */ +#define RTC_TAMPCR_TAMPFREQ_SHIFT (8) /* Bits 8-10: Tamper sampling frequency */ +#define RTC_TAMPCR_TAMPFREQ_MASK (7 << RTC_TAMPCR_TAMPFREQ_SHIFT) +# define RTC_TAMPCR_TAMPFREQ_DIV32768 (0 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 32768 (1 Hz) */ +# define RTC_TAMPCR_TAMPFREQ_DIV16384 (1 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 16384 (2 Hz) */ +# define RTC_TAMPCR_TAMPFREQ_DIV8192 (2 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 8192 (4 Hz) */ +# define RTC_TAMPCR_TAMPFREQ_DIV4096 (3 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 4096 (8 Hz) */ +# define RTC_TAMPCR_TAMPFREQ_DIV2048 (4 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 2048 (16 Hz) */ +# define RTC_TAMPCR_TAMPFREQ_DIV1024 (5 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 1024 (32 Hz) */ +# define RTC_TAMPCR_TAMPFREQ_DIV512 (6 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 512 (64 Hz) */ +# define RTC_TAMPCR_TAMPFREQ_DIV256 (7 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 256 (128 Hz) */ +#define RTC_TAMPCR_TAMPFLT_SHIFT (11) /* Bits 11-12: RTC_TAMPx filter count */ +#define RTC_TAMPCR_TAMPFLT_MASK (3 << RTC_TAMPCR_TAMPFLT_SHIFT) +#define RTC_TAMPCR_TAMPPRCH_SHIFT (13) /* Bits 13-14: RTC_TAMPx precharge duration */ +#define RTC_TAMPCR_TAMPPRCH_MASK (3 << RTC_TAMPCR_TAMPPRCH_SHIFT) +# define RTC_TAMPCR_TAMPPRCH_1CYCLE (0 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 1 RTCCLK cycle */ +# define RTC_TAMPCR_TAMPPRCH_2CYCLES (1 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 2 RTCCLK cycles */ +# define RTC_TAMPCR_TAMPPRCH_4CYCLES (2 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 4 RTCCLK cycles */ +# define RTC_TAMPCR_TAMPPRCH_5CYCLES (3 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 8 RTCCLK cycles */ +#define RTC_TAMPCR_TAMPPUDIS (1 << 15) /* Bit 15: RTC_TAMPx pull-up disable */ +#define RTC_TAMPCR_TAMP1IE (1 << 16) /* Bit 16: Tamper 1 interrupt enable */ +#define RTC_TAMPCR_TAMP1NOERASE (1 << 17) /* Bit 17: Tamper 1 no erase */ +#define RTC_TAMPCR_TAMP1MF (1 << 18) /* Bit 18: Tamper 1 mask flag */ +#define RTC_TAMPCR_TAMP2IE (1 << 19) /* Bit 19: Tamper 2 interrupt enable */ +#define RTC_TAMPCR_TAMP2NOERASE (1 << 20) /* Bit 20: Tamper 2 no erase */ +#define RTC_TAMPCR_TAMP2MF (1 << 21) /* Bit 21: Tamper 2 mask flag */ +#define RTC_TAMPCR_TAMP3IE (1 << 22) /* Bit 22: Tamper 3 interrupt enable */ +#define RTC_TAMPCR_TAMP3NOERASE (1 << 23) /* Bit 23: Tamper 3 no erase */ +#define RTC_TAMPCR_TAMP3MF (1 << 24) /* Bit 24: Tamper 3 mask flag */ + +/* RTC alarm A/B sub second register */ + +#define RTC_ALRMSSR_SS_SHIFT (0) /* Bits 0-14: Sub second value */ +#define RTC_ALRMSSR_SS_MASK (0x7fff << RTC_ALRMSSR_SS_SHIFT) +#define RTC_ALRMSSR_MASKSS_SHIFT (24) /* Bits 24-27: Mask the most-significant bits starting at this bit */ +#define RTC_ALRMSSR_MASKSS_MASK (0xf << RTC_ALRMSSR_MASKSS_SHIFT) + +/* RTC option register */ + +#define RTC_OR_TSINSEL_SHIFT (1) /* Bits 1-2: TIMESTAMP mapping */ +#define RTC_OR_TSINSEL_MASK (3 << RTC_OR_TSINSEL_SHIFT) +# define RTC_OR_PC13 (0 << RTC_OR_TSINSEL_SHIFT) /* TIMESTAMP is mapped on PC13*/ +# define RTC_OR_PI8 (1 << RTC_OR_TSINSEL_SHIFT) /* TIMESTAMP is mapped on PI8 */ +# define RTC_OR_PC1 (2 << RTC_OR_TSINSEL_SHIFT) /* TIMESTAMP is mapped on PC1 */ +# define RTC_OR_PC1_1 (3 << RTC_OR_TSINSEL_SHIFT) /* TIMESTAMP is mapped on PC1 */ +#define RTC_OR_RTC_ALARM_TYPE (1 << 3) /* RTC_ALARM on PC13 output type */ + + +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_RTCC_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32_sdmmc.h b/arch/arm/src/stm32f7/chip/stm32_sdmmc.h index 10ed29f2384d09e12473a5140e538e44148e31cb..016ddb18fb9eba5cd86a35b1c4829d398354ab29 100644 --- a/arch/arm/src/stm32f7/chip/stm32_sdmmc.h +++ b/arch/arm/src/stm32f7/chip/stm32_sdmmc.h @@ -2,7 +2,8 @@ * arch/arm/src/stm32f7/chip/stm32_sdmmc.h * * Copyright (C) 2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -43,8 +44,9 @@ #include #include "chip.h" -#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) -# include "stm32f74xx75xx_sdmmc.h" +#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ + defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +# include "stm32f74xx77xx_sdmmc.h" #else # error "Unsupported STM32 F7 part" #endif diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_dbgmcu.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_dbgmcu.h new file mode 100644 index 0000000000000000000000000000000000000000..33842b73410302c3d6bd587c420b79dc0e58313b --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_dbgmcu.h @@ -0,0 +1,112 @@ +/**************************************************************************** + * arch/arm/src/stm32f7/chip/stm32f74xx75xx_dbgmcu.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XXDBGMCU_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XXDBGMCU_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Addresses *******************************************************/ + +#define STM32_DBGMCU_IDCODE 0xe0042000 /* MCU identifier */ +#define STM32_DBGMCU_CR 0xe0042004 /* MCU debug */ +#define STM32_DBGMCU_APB1_FZ 0xe0042008 /* Debug MCU APB1 freeze register */ +#define STM32_DBGMCU_APB2_FZ 0xe004200c /* Debug MCU APB2 freeze register */ + +/* Register Bitfield Definitions ********************************************/ + +/* MCU identifier */ + +#define DBGMCU_IDCODE_DEVID_SHIFT (0) /* Bits 11-0: Device Identifier */ +#define DBGMCU_IDCODE_DEVID_MASK (0x0fff << DBGMCU_IDCODE_DEVID_SHIFT) +#define DBGMCU_IDCODE_REVID_SHIFT (16) /* Bits 31-16: Revision Identifier */ +#define DBGMCU_IDCODE_REVID_MASK (0xffff << DBGMCU_IDCODE_REVID_SHIFT) + +/* MCU debug */ + +#define DBGMCU_CR_SLEEP (1 << 0) /* Bit 0: Debug Sleep Mode */ +#define DBGMCU_CR_STOP (1 << 1) /* Bit 1: Debug Stop Mode */ +#define DBGMCU_CR_STANDBY (1 << 2) /* Bit 2: Debug Standby mode */ +#define DBGMCU_CR_TRACEIOEN (1 << 5) /* Bit 5: Trace enabled */ + +#define DBGMCU_CR_TRACEMODE_SHIFT (6) /* Bits 7-6: Trace mode pin assignement */ +#define DBGMCU_CR_TRACEMODE_MASK (3 << DBGMCU_CR_TRACEMODE_SHIFT) +#define DBGMCU_CR_ASYNCH (0 << DBGMCU_CR_TRACEMODE_SHIFT) /* Asynchronous Mode */ +#define DBGMCU_CR_SYNCH1 (1 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=1 */ +#define DBGMCU_CR_SYNCH2 (2 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=2 */ +#define DBGMCU_CR_SYNCH4 (3 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=4 */ + +/* Debug MCU APB1 freeze register */ + +#define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */ +#define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */ +#define DBGMCU_APB1_TIM4STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */ +#define DBGMCU_APB1_TIM5STOP (1 << 3) /* Bit 3: TIM5 stopped when core is halted */ +#define DBGMCU_APB1_TIM6STOP (1 << 4) /* Bit 4: TIM6 stopped when core is halted */ +#define DBGMCU_APB1_TIM7STOP (1 << 5) /* Bit 5: TIM7 stopped when core is halted */ +#define DBGMCU_APB1_TIM12STOP (1 << 6) /* Bit 6: TIM12 stopped when core is halted */ +#define DBGMCU_APB1_TIM13STOP (1 << 7) /* Bit 7: TIM13 stopped when core is halted */ +#define DBGMCU_APB1_TIM14STOP (1 << 8) /* Bit 8: TIM14 stopped when core is halted */ +#define DBGMCU_APB1_LPTIM1STOP (1 << 9) /* Bit 9: LPTIM1 stopped when core is halted */ +#define DBGMCU_APB1_RTCSTOP (1 << 10) /* Bit 10: RTC stopped when Core is halted */ +#define DBGMCU_APB1_WWDGSTOP (1 << 11) /* Bit 11: Window Watchdog stopped when core is halted */ +#define DBGMCU_APB1_IWDGSTOP (1 << 12) /* Bit 12: Independent Watchdog stopped when core is halted */ +#define DBGMCU_APB1_I2C1STOP (1 << 21) /* Bit 21: I2C1 SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_APB1_I2C2STOP (1 << 22) /* Bit 22: I2C2 SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_APB1_I2C3STOP (1 << 23) /* Bit 23: I2C3 SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_APB1_I2C4STOP (1 << 24) /* Bit 24: I2C4 SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_APB1_CAN1STOP (1 << 25) /* Bit 25: CAN1 stopped when core is halted */ +#define DBGMCU_APB1_CAN2STOP (1 << 26) /* Bit 26: CAN2 stopped when core is halted */ + +/* Debug MCU APB2 freeze register */ + +#define DBGMCU_APB2_TIM1STOP (1 << 0) /* Bit 0: TIM1 stopped when core is halted */ +#define DBGMCU_APB2_TIM8STOP (1 << 1) /* Bit 1: TIM8 stopped when core is halted */ +#define DBGMCU_APB2_TIM9STOP (1 << 16) /* Bit 16: TIM9 stopped when core is halted */ +#define DBGMCU_APB2_TIM10STOP (1 << 17) /* Bit 17: TIM10 stopped when core is halted */ +#define DBGMCU_APB2_TIM11STOP (1 << 18) /* Bit 18: TIM11 stopped when core is halted */ + +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XXDBGMCU_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h index b68797d00683ec158816aa976e805924e256bdb5..889cf23192e98ec539b09377de48cd48cbe1bda0 100644 --- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h +++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_memorymap.h @@ -49,7 +49,7 @@ * Pre-processor Definitions ************************************************************************************/ -/* STM32F40XXX Address Blocks *******************************************************/ +/* STM32F7XXXX STM32F75XXX Address Blocks *******************************************/ #define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ #define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */ diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h index 881f17dc560a47e47ac32e9dbdcaa8204d8d63b3..70c9a2a5aa7cdd347d72f93dfa4d0621568ccba1 100644 --- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h +++ b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_rcc.h @@ -574,7 +574,7 @@ # define RCC_PLLI2SCFGR_PLLI2SN(n) ((uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SN_SHIFT) #define RCC_PLLI2SCFGR_PLLI2SP_SHIFT (16) /* Bits 16-17: PLLI2S division factor for SPDIFRX clock */ #define RCC_PLLI2SCFGR_PLLI2SP_MASK (3 << RCC_PLLI2SCFGR_PLLI2SP_SHIFT) -# define RCC_PLLI2SCFGR_PLLI2SP(n) ((uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SP_SHIFT) +# define RCC_PLLI2SCFGR_PLLI2SP(n) ((((n)>>1)-1) << RCC_PLLI2SCFGR_PLLI2SP_SHIFT) #define RCC_PLLI2SCFGR_PLLI2SQ_SHIFT (24) /* Bits 24-27: PLLI2S division factor for SAIs clock */ #define RCC_PLLI2SCFGR_PLLI2SQ_MASK (15 << RCC_PLLI2SCFGR_PLLI2SQ_SHIFT) # define RCC_PLLI2SCFGR_PLLI2SQ(n) ((uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SQ_SHIFT) @@ -589,7 +589,7 @@ # define RCC_PLLSAICFGR_PLLSAIN(n) ((n) << RCC_PLLSAICFGR_PLLSAIN_SHIFT) #define RCC_PLLSAICFGR_PLLSAIP_SHIFT (16) /* Bits 16-17: PLLSAI division factor for 48MHz clock */ #define RCC_PLLSAICFGR_PLLSAIP_MASK (3 << RCC_PLLSAICFGR_PLLSAIP_SHIFT) -# define RCC_PLLSAICFGR_PLLSAIP(n) ((n) << RCC_PLLSAICFGR_PLLSAIP_SHIFT) +# define RCC_PLLSAICFGR_PLLSAIP(n) ((((n)>>1)-1) << RCC_PLLSAICFGR_PLLSAIP_SHIFT) #define RCC_PLLSAICFGR_PLLSAIQ_SHIFT (24) /* Bits 24-27: PLLSAI division factor for SAI clock */ #define RCC_PLLSAICFGR_PLLSAIQ_MASK (0x0F << RCC_PLLSAICFGR_PLLSAIQ_SHIFT) # define RCC_PLLSAICFGR_PLLSAIQ(n) ((n) << RCC_PLLSAICFGR_PLLSAIQ_SHIFT) diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_sdmmc.h b/arch/arm/src/stm32f7/chip/stm32f74xx75xx_sdmmc.h deleted file mode 100644 index 117c4da2faf7782ce2e33c4cf9056bc8b33c4f34..0000000000000000000000000000000000000000 --- a/arch/arm/src/stm32f7/chip/stm32f74xx75xx_sdmmc.h +++ /dev/null @@ -1,268 +0,0 @@ -/************************************************************************************ - * arch/arm/src/stm32f7/chip/stm32_sdmmc.h - * - * Copyright (C) 2009, 2011-2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the - * distribution. - * 3. Neither the name NuttX nor the names of its contributors may be - * used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS - * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE - * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, - * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, - * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS - * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED - * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN - * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - ************************************************************************************/ - -#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SDMMC_H -#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SDMMC_H - -/************************************************************************************ - * Pre-processor Definitions - ************************************************************************************/ - -/* Register Offsets *****************************************************************/ - -#define STM32_SDMMC1_POWER_OFFSET 0x0000 /* SDIO power control register */ -#define STM32_SDMMC1_CLKCR_OFFSET 0x0004 /* SDI clock control register */ -#define STM32_SDMMC1_ARG_OFFSET 0x0008 /* SDIO argument register */ -#define STM32_SDMMC1_CMD_OFFSET 0x000c /* SDIO command register */ -#define STM32_SDMMC1_RESPCMD_OFFSET 0x0010 /* SDIO command response register */ -#define STM32_SDMMC1_RESP_OFFSET(n) (0x0010+4*(n)) -#define STM32_SDMMC1_RESP1_OFFSET 0x0014 /* SDIO response 1 register */ -#define STM32_SDMMC1_RESP2_OFFSET 0x0018 /* SDIO response 2 register */ -#define STM32_SDMMC1_RESP3_OFFSET 0x001c /* SDIO response 3 register */ -#define STM32_SDMMC1_RESP4_OFFSET 0x0020 /* SDIO response 4 register */ -#define STM32_SDMMC1_DTIMER_OFFSET 0x0024 /* SDIO data timer register */ -#define STM32_SDMMC1_DLEN_OFFSET 0x0028 /* SDIO data length register */ -#define STM32_SDMMC1_DCTRL_OFFSET 0x002c /* SDIO data control register */ -#define STM32_SDMMC1_DCOUNT_OFFSET 0x0030 /* SDIO data counter register */ -#define STM32_SDMMC1_STA_OFFSET 0x0034 /* SDIO status register */ -#define STM32_SDMMC1_ICR_OFFSET 0x0038 /* SDIO interrupt clear register */ -#define STM32_SDMMC1_MASK_OFFSET 0x003c /* SDIO mask register */ -#define STM32_SDMMC1_FIFOCNT_OFFSET 0x0048 /* SDIO FIFO counter register */ -#define STM32_SDMMC1_FIFO_OFFSET 0x0080 /* SDIO data FIFO register */ - -/* Register Addresses ***************************************************************/ - -#define STM32_SDMMC1_POWER (STM32_SDMMC1_BASE+STM32_SDMMC1_POWER_OFFSET) -#define STM32_SDMMC1_CLKCR (STM32_SDMMC1_BASE+STM32_SDMMC1_CLKCR_OFFSET) -#define STM32_SDMMC1_ARG (STM32_SDMMC1_BASE+STM32_SDMMC1_ARG_OFFSET) -#define STM32_SDMMC1_CMD (STM32_SDMMC1_BASE+STM32_SDMMC1_CMD_OFFSET) -#define STM32_SDMMC1_RESPCMD (STM32_SDMMC1_BASE+STM32_SDMMC1_RESPCMD_OFFSET) -#define STM32_SDMMC1_RESP(n) (STM32_SDMMC1_BASE+STM32_SDMMC1_RESP_OFFSET(n)) -#define STM32_SDMMC1_RESP1 (STM32_SDMMC1_BASE+STM32_SDMMC1_RESP1_OFFSET) -#define STM32_SDMMC1_RESP2 (STM32_SDMMC1_BASE+STM32_SDMMC1_RESP2_OFFSET) -#define STM32_SDMMC1_RESP3 (STM32_SDMMC1_BASE+STM32_SDMMC1_RESP3_OFFSET) -#define STM32_SDMMC1_RESP4 (STM32_SDMMC1_BASE+STM32_SDMMC1_RESP4_OFFSET) -#define STM32_SDMMC1_DTIMER (STM32_SDMMC1_BASE+STM32_SDMMC1_DTIMER_OFFSET) -#define STM32_SDMMC1_DLEN (STM32_SDMMC1_BASE+STM32_SDMMC1_DLEN_OFFSET) -#define STM32_SDMMC1_DCTRL (STM32_SDMMC1_BASE+STM32_SDMMC1_DCTRL_OFFSET) -#define STM32_SDMMC1_DCOUNT (STM32_SDMMC1_BASE+STM32_SDMMC1_DCOUNT_OFFSET) -#define STM32_SDMMC1_STA (STM32_SDMMC1_BASE+STM32_SDMMC1_STA_OFFSET) -#define STM32_SDMMC1_ICR (STM32_SDMMC1_BASE+STM32_SDMMC1_ICR_OFFSET) -#define STM32_SDMMC1_MASK (STM32_SDMMC1_BASE+STM32_SDMMC1_MASK_OFFSET) -#define STM32_SDMMC1_FIFOCNT (STM32_SDMMC1_BASE+STM32_SDMMC1_FIFOCNT_OFFSET) -#define STM32_SDMMC1_FIFO (STM32_SDMMC1_BASE+STM32_SDMMC1_FIFO_OFFSET) - - -/* Register Bitfield Definitions ****************************************************/ - -#define SDIO_POWER_PWRCTRL_SHIFT (0) /* Bits 0-1: Power supply control bits */ -#define SDIO_POWER_PWRCTRL_MASK (3 << SDIO_POWER_PWRCTRL_SHIFT) -# define SDIO_POWER_PWRCTRL_OFF (0 << SDIO_POWER_PWRCTRL_SHIFT) /* 00: Power-off: card clock stopped */ -# define SDIO_POWER_PWRCTRL_PWRUP (2 << SDIO_POWER_PWRCTRL_SHIFT) /* 10: Reserved power-up */ -# define SDIO_POWER_PWRCTRL_ON (3 << SDIO_POWER_PWRCTRL_SHIFT) /* 11: Power-on: card is clocked */ - -#define SDIO_POWER_RESET (0) /* Reset value */ - -#define SDIO_CLKCR_CLKDIV_SHIFT (0) /* Bits 7-0: Clock divide factor */ -#define SDIO_CLKCR_CLKDIV_MASK (0xff << SDIO_CLKCR_CLKDIV_SHIFT) -#define SDIO_CLKCR_CLKEN (1 << 8) /* Bit 8: Clock enable bit */ -#define SDIO_CLKCR_PWRSAV (1 << 9) /* Bit 9: Power saving configuration bit */ -#define SDIO_CLKCR_BYPASS (1 << 10) /* Bit 10: Clock divider bypass enable bit */ -#define SDIO_CLKCR_WIDBUS_SHIFT (11) /* Bits 12-11: Wide bus mode enable bits */ -#define SDIO_CLKCR_WIDBUS_MASK (3 << SDIO_CLKCR_WIDBUS_SHIFT) -# define SDIO_CLKCR_WIDBUS_D1 (0 << SDIO_CLKCR_WIDBUS_SHIFT) /* 00: Default (SDIO_D0) */ -# define SDIO_CLKCR_WIDBUS_D4 (1 << SDIO_CLKCR_WIDBUS_SHIFT) /* 01: 4-wide (SDIO_D[3:0]) */ -# define SDIO_CLKCR_WIDBUS_D8 (2 << SDIO_CLKCR_WIDBUS_SHIFT) /* 10: 8-wide (SDIO_D[7:0]) */ -#define SDIO_CLKCR_NEGEDGE (1 << 13) /* Bit 13: SDIO_CK dephasing selection bit */ -#define SDIO_CLKCR_HWFC_EN (1 << 14) /* Bit 14: HW Flow Control enable */ - -#define SDIO_CLKCR_RESET (0) /* Reset value */ -#define SDIO_ARG_RESET (0) /* Reset value */ - -#define SDIO_CLKCR_CLKEN_BB (STM32_SDMMC1_CLKCR_BB + (8 * 4)) -#define SDIO_CLKCR_PWRSAV_BB (STM32_SDMMC1_CLKCR_BB + (9 * 4)) -#define SDIO_CLKCR_BYPASS_BB (STM32_SDMMC1_CLKCR_BB + (10 * 4)) -#define SDIO_CLKCR_NEGEDGE_BB (STM32_SDMMC1_CLKCR_BB + (13 * 4)) -#define SDIO_CLKCR_HWFC_EN_BB (STM32_SDMMC1_CLKCR_BB + (14 * 4)) - -#define SDIO_CMD_CMDINDEX_SHIFT (0) -#define SDIO_CMD_CMDINDEX_MASK (0x3f << SDIO_CMD_CMDINDEX_SHIFT) -#define SDIO_CMD_WAITRESP_SHIFT (6) /* Bits 7-6: Wait for response bits */ -#define SDIO_CMD_WAITRESP_MASK (3 << SDIO_CMD_WAITRESP_SHIFT) -# define SDIO_CMD_NORESPONSE (0 << SDIO_CMD_WAITRESP_SHIFT) /* 00/10: No response */ -# define SDIO_CMD_SHORTRESPONSE (1 << SDIO_CMD_WAITRESP_SHIFT) /* 01: Short response */ -# define SDIO_CMD_LONGRESPONSE (3 << SDIO_CMD_WAITRESP_SHIFT) /* 11: Long response */ -#define SDIO_CMD_WAITINT (1 << 8) /* Bit 8: CPSM waits for interrupt request */ -#define SDIO_CMD_WAITPEND (1 << 9) /* Bit 9: CPSM Waits for ends of data transfer */ -#define SDIO_CMD_CPSMEN (1 << 10) /* Bit 10: Command path state machine enable */ -#define SDIO_CMD_SUSPEND (1 << 11) /* Bit 11: SD I/O suspend command */ -#define SDIO_CMD_ENDCMD (1 << 12) /* Bit 12: Enable CMD completion */ -#define SDIO_CMD_NIEN (1 << 13) /* Bit 13: not Interrupt Enable */ -#define SDIO_CMD_ATACMD (1 << 14) /* Bit 14: CE-ATA command */ - -#define SDIO_CMD_RESET (0) /* Reset value */ - -#define SDIO_CMD_WAITINT_BB (STM32_SDMMC1_CMD_BB + (8 * 4)) -#define SDIO_CMD_WAITPEND_BB (STM32_SDMMC1_CMD_BB + (9 * 4)) -#define SDIO_CMD_CPSMEN_BB (STM32_SDMMC1_CMD_BB + (10 * 4)) -#define SDIO_CMD_SUSPEND_BB (STM32_SDMMC1_CMD_BB + (11 * 4)) -#define SDIO_CMD_ENCMD_BB (STM32_SDMMC1_CMD_BB + (12 * 4)) -#define SDIO_CMD_NIEN_BB (STM32_SDMMC1_CMD_BB + (13 * 4)) -#define SDIO_CMD_ATACMD_BB (STM32_SDMMC1_CMD_BB + (14 * 4)) - -#define SDIO_RESPCMD_SHIFT (0) -#define SDIO_RESPCMD_MASK (0x3f << SDIO_RESPCMD_SHIFT) - -#define SDIO_DTIMER_RESET (0) /* Reset value */ - -#define SDIO_DLEN_SHIFT (0) -#define SDIO_DLEN_MASK (0x01ffffff << SDIO_DLEN_SHIFT) - -#define SDIO_DLEN_RESET (0) /* Reset value */ - -#define SDIO_DCTRL_DTEN (1 << 0) /* Bit 0: Data transfer enabled bit */ -#define SDIO_DCTRL_DTDIR (1 << 1) /* Bit 1: Data transfer direction */ -#define SDIO_DCTRL_DTMODE (1 << 2) /* Bit 2: Data transfer mode */ -#define SDIO_DCTRL_DMAEN (1 << 3) /* Bit 3: DMA enable bit */ -#define SDIO_DCTRL_DBLOCKSIZE_SHIFT (4) /* Bits 7-4: Data block size */ -#define SDIO_DCTRL_DBLOCKSIZE_MASK (15 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_1BYTE (0 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_2BYTES (1 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_4BYTES (2 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_8BYTES (3 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_16BYTES (4 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_32BYTES (5 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_64BYTES (6 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_128BYTES (7 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_256BYTES (8 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_512BYTES (9 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_1KBYTE (10 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_2KBYTES (11 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_4KBYTES (12 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_8KBYTES (13 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -# define SDIO_DCTRL_16KBYTES (14 << SDIO_DCTRL_DBLOCKSIZE_SHIFT) -#define SDIO_DCTRL_RWSTART (1 << 8) /* Bit 8: Read wait start */ -#define SDIO_DCTRL_RWSTOP (1 << 9) /* Bit 9: Read wait stop */ -#define SDIO_DCTRL_RWMOD (1 << 10) /* Bit 10: Read wait mode */ -#define SDIO_DCTRL_SDIOEN (1 << 11) /* Bit 11: SD I/O enable functions */ - -#define SDIO_DCTRL_RESET (0) /* Reset value */ - -#define SDIO_DCTRL_DTEN_BB (STM32_SDMMC1_DCTRL_BB + (0 * 4)) -#define SDIO_DCTRL_DTDIR_BB (STM32_SDMMC1_DCTRL_BB + (1 * 4)) -#define SDIO_DCTRL_DTMODE_BB (STM32_SDMMC1_DCTRL_BB + (2 * 4)) -#define SDIO_DCTRL_DMAEN_BB (STM32_SDMMC1_DCTRL_BB + (3 * 4)) -#define SDIO_DCTRL_RWSTART_BB (STM32_SDMMC1_DCTRL_BB + (8 * 4)) -#define SDIO_DCTRL_RWSTOP_BB (STM32_SDMMC1_DCTRL_BB + (9 * 4)) -#define SDIO_DCTRL_RWMOD_BB (STM32_SDMMC1_DCTRL_BB + (10 * 4)) -#define SDIO_DCTRL_SDIOEN_BB (STM32_SDMMC1_DCTRL_BB + (11 * 4)) - -#define SDIO_DATACOUNT_SHIFT (0) -#define SDIO_DATACOUNT_MASK (0x01ffffff << SDIO_DATACOUNT_SHIFT) - -#define SDIO_STA_CCRCFAIL (1 << 0) /* Bit 0: Command response CRC fail */ -#define SDIO_STA_DCRCFAIL (1 << 1) /* Bit 1: Data block CRC fail */ -#define SDIO_STA_CTIMEOUT (1 << 2) /* Bit 2: Command response timeout */ -#define SDIO_STA_DTIMEOUT (1 << 3) /* Bit 3: Data timeout */ -#define SDIO_STA_TXUNDERR (1 << 4) /* Bit 4: Transmit FIFO underrun error */ -#define SDIO_STA_RXOVERR (1 << 5) /* Bit 5: Received FIFO overrun error */ -#define SDIO_STA_CMDREND (1 << 6) /* Bit 6: Command response received */ -#define SDIO_STA_CMDSENT (1 << 7) /* Bit 7: Command sent */ -#define SDIO_STA_DATAEND (1 << 8) /* Bit 8: Data end */ -#define SDIO_STA_STBITERR (1 << 9) /* Bit 9: Start bit not detected */ -#define SDIO_STA_DBCKEND (1 << 10) /* Bit 10: Data block sent/received */ -#define SDIO_STA_CMDACT (1 << 11) /* Bit 11: Command transfer in progress */ -#define SDIO_STA_TXACT (1 << 12) /* Bit 12: Data transmit in progress */ -#define SDIO_STA_RXACT (1 << 13) /* Bit 13: Data receive in progress */ -#define SDIO_STA_TXFIFOHE (1 << 14) /* Bit 14: Transmit FIFO half empty */ -#define SDIO_STA_RXFIFOHF (1 << 15) /* Bit 15: Receive FIFO half full */ -#define SDIO_STA_TXFIFOF (1 << 16) /* Bit 16: Transmit FIFO full */ -#define SDIO_STA_RXFIFOF (1 << 17) /* Bit 17: Receive FIFO full */ -#define SDIO_STA_TXFIFOE (1 << 18) /* Bit 18: Transmit FIFO empty */ -#define SDIO_STA_RXFIFOE (1 << 19) /* Bit 19: Receive FIFO empty */ -#define SDIO_STA_TXDAVL (1 << 20) /* Bit 20: Data available in transmit FIFO */ -#define SDIO_STA_RXDAVL (1 << 21) /* Bit 21: Data available in receive FIFO */ -#define SDIO_STA_SDIOIT (1 << 22) /* Bit 22: SDIO interrupt received */ -#define SDIO_STA_CEATAEND (1 << 23) /* Bit 23: CMD6 CE-ATA command completion */ - -#define SDIO_ICR_CCRCFAILC (1 << 0) /* Bit 0: CCRCFAIL flag clear bit */ -#define SDIO_ICR_DCRCFAILC (1 << 1) /* Bit 1: DCRCFAIL flag clear bit */ -#define SDIO_ICR_CTIMEOUTC (1 << 2) /* Bit 2: CTIMEOUT flag clear bit */ -#define SDIO_ICR_DTIMEOUTC (1 << 3) /* Bit 3: DTIMEOUT flag clear bit */ -#define SDIO_ICR_TXUNDERRC (1 << 4) /* Bit 4: TXUNDERR flag clear bit */ -#define SDIO_ICR_RXOVERRC (1 << 5) /* Bit 5: RXOVERR flag clear bit */ -#define SDIO_ICR_CMDRENDC (1 << 6) /* Bit 6: CMDREND flag clear bit */ -#define SDIO_ICR_CMDSENTC (1 << 7) /* Bit 7: CMDSENT flag clear bit */ -#define SDIO_ICR_DATAENDC (1 << 8) /* Bit 8: DATAEND flag clear bit */ -#define SDIO_ICR_STBITERRC (1 << 9) /* Bit 9: STBITERR flag clear bit */ -#define SDIO_ICR_DBCKENDC (1 << 10) /* Bit 10: DBCKEND flag clear bit */ -#define SDIO_ICR_SDIOITC (1 << 22) /* Bit 22: SDIOIT flag clear bit */ -#define SDIO_ICR_CEATAENDC (1 << 23) /* Bit 23: CEATAEND flag clear bit */ - -#define SDIO_ICR_RESET 0x00c007ff -#define SDIO_ICR_STATICFLAGS 0x000005ff - -#define SDIO_MASK_CCRCFAILIE (1 << 0) /* Bit 0: Command CRC fail interrupt enable */ -#define SDIO_MASK_DCRCFAILIE (1 << 1) /* Bit 1: Data CRC fail interrupt enable */ -#define SDIO_MASK_CTIMEOUTIE (1 << 2) /* Bit 2: Command timeout interrupt enable */ -#define SDIO_MASK_DTIMEOUTIE (1 << 3) /* Bit 3: Data timeout interrupt enable */ -#define SDIO_MASK_TXUNDERRIE (1 << 4) /* Bit 4: Tx FIFO underrun error interrupt enable */ -#define SDIO_MASK_RXOVERRIE (1 << 5) /* Bit 5: Rx FIFO overrun error interrupt enable */ -#define SDIO_MASK_CMDRENDIE (1 << 6) /* Bit 6: Command response received interrupt enable */ -#define SDIO_MASK_CMDSENTIE (1 << 7) /* Bit 7: Command sent interrupt enable */ -#define SDIO_MASK_DATAENDIE (1 << 8) /* Bit 8: Data end interrupt enable */ -#define SDIO_MASK_STBITERRIE (1 << 9) /* Bit 9: Start bit error interrupt enable */ -#define SDIO_MASK_DBCKENDIE (1 << 10) /* Bit 10: Data block end interrupt enable */ -#define SDIO_MASK_CMDACTIE (1 << 11) /* Bit 11: Command acting interrupt enable */ -#define SDIO_MASK_TXACTIE (1 << 12) /* Bit 12: Data transmit acting interrupt enable */ -#define SDIO_MASK_RXACTIE (1 << 13) /* Bit 13: Data receive acting interrupt enable */ -#define SDIO_MASK_TXFIFOHEIE (1 << 14) /* Bit 14: Tx FIFO half empty interrupt enable */ -#define SDIO_MASK_RXFIFOHFIE (1 << 15) /* Bit 15: Rx FIFO half full interrupt enable */ -#define SDIO_MASK_TXFIFOFIE (1 << 16) /* Bit 16: Tx FIFO full interrupt enable */ -#define SDIO_MASK_RXFIFOFIE (1 << 17) /* Bit 17: Rx FIFO full interrupt enable */ -#define SDIO_MASK_TXFIFOEIE (1 << 18) /* Bit 18: Tx FIFO empty interrupt enable */ -#define SDIO_MASK_RXFIFOEIE (1 << 19) /* Bit 19: Rx FIFO empty interrupt enable */ -#define SDIO_MASK_TXDAVLIE (1 << 20) /* Bit 20: Data available in Tx FIFO interrupt enable */ -#define SDIO_MASK_RXDAVLIE (1 << 21) /* Bit 21: Data available in Rx FIFO interrupt enable */ -#define SDIO_MASK_SDIOITIE (1 << 22) /* Bit 22: SDIO mode interrupt received interrupt enable */ -#define SDIO_MASK_CEATAENDIE (1 << 23) /* Bit 23: CE-ATA command completion interrupt enable */ - -#define SDIO_MASK_RESET (0) - -#define SDIO_FIFOCNT_SHIFT (0) -#define SDIO_FIFOCNT_MASK (0x01ffffff << SDIO_FIFOCNT_SHIFT) - -#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XX_SDMMC_H */ - diff --git a/arch/arm/src/stm32f7/chip/stm32f74xx77xx_sdmmc.h b/arch/arm/src/stm32f7/chip/stm32f74xx77xx_sdmmc.h new file mode 100644 index 0000000000000000000000000000000000000000..e0d52edc4ef756e39978be194f4b12f409450301 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f74xx77xx_sdmmc.h @@ -0,0 +1,224 @@ + /* arch/arm/src/stm32f7/chip/stm32f74xx77xx_sdmmc.h + * + * Copyright (C) 2009, 2011-2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_SDMMC_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_SDMMC_H + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define STM32_SDMMC_POWER_OFFSET 0x0000 /* SDMMC power control register */ +#define STM32_SDMMC_CLKCR_OFFSET 0x0004 /* SDMMC clock control register */ +#define STM32_SDMMC_ARG_OFFSET 0x0008 /* SDMMC argument register */ +#define STM32_SDMMC_CMD_OFFSET 0x000c /* SDMMC command register */ +#define STM32_SDMMC_RESPCMD_OFFSET 0x0010 /* SDMMC command response register */ +#define STM32_SDMMC_RESP_OFFSET(n) (0x0010+4*(n)) +#define STM32_SDMMC_RESP1_OFFSET 0x0014 /* SDMMC response 1 register */ +#define STM32_SDMMC_RESP2_OFFSET 0x0018 /* SDMMC response 2 register */ +#define STM32_SDMMC_RESP3_OFFSET 0x001c /* SDMMC response 3 register */ +#define STM32_SDMMC_RESP4_OFFSET 0x0020 /* SDMMC response 4 register */ +#define STM32_SDMMC_DTIMER_OFFSET 0x0024 /* SDMMC data timer register */ +#define STM32_SDMMC_DLEN_OFFSET 0x0028 /* SDMMC data length register */ +#define STM32_SDMMC_DCTRL_OFFSET 0x002c /* SDMMC data control register */ +#define STM32_SDMMC_DCOUNT_OFFSET 0x0030 /* SDMMC data counter register */ +#define STM32_SDMMC_STA_OFFSET 0x0034 /* SDMMC status register */ +#define STM32_SDMMC_ICR_OFFSET 0x0038 /* SDMMC interrupt clear register */ +#define STM32_SDMMC_MASK_OFFSET 0x003c /* SDMMC mask register */ +#define STM32_SDMMC_FIFOCNT_OFFSET 0x0048 /* SDMMC FIFO counter register */ +#define STM32_SDMMC_FIFO_OFFSET 0x0080 /* SDMMC data FIFO register */ + + +/* Register Bitfield Definitions ****************************************************/ + +#define STM32_SDMMC_POWER_PWRCTRL_SHIFT (0) /* Bits 0-1: Power supply control bits */ +#define STM32_SDMMC_POWER_PWRCTRL_MASK (3 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) +# define STM32_SDMMC_POWER_PWRCTRL_OFF (0 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) /* 00: Power-off: card clock stopped */ +# define STM32_SDMMC_POWER_PWRCTRL_PWRUP (2 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) /* 10: Reserved power-up */ +# define STM32_SDMMC_POWER_PWRCTRL_ON (3 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) /* 11: Power-on: card is clocked */ + +#define STM32_SDMMC_POWER_RESET (0) /* Reset value */ + +#define STM32_SDMMC_CLKCR_CLKDIV_SHIFT (0) /* Bits 7-0: Clock divide factor */ +#define STM32_SDMMC_CLKCR_CLKDIV_MASK (0xff << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#define STM32_SDMMC_CLKCR_CLKEN (1 << 8) /* Bit 8: Clock enable bit */ +#define STM32_SDMMC_CLKCR_PWRSAV (1 << 9) /* Bit 9: Power saving configuration bit */ +#define STM32_SDMMC_CLKCR_BYPASS (1 << 10) /* Bit 10: Clock divider bypass enable bit */ +#define STM32_SDMMC_CLKCR_WIDBUS_SHIFT (11) /* Bits 12-11: Wide bus mode enable bits */ +#define STM32_SDMMC_CLKCR_WIDBUS_MASK (3 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) +# define STM32_SDMMC_CLKCR_WIDBUS_D1 (0 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 00: Default (STM32_SDMMC_D0) */ +# define STM32_SDMMC_CLKCR_WIDBUS_D4 (1 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 01: 4-wide (STM32_SDMMC_D[3:0]) */ +# define STM32_SDMMC_CLKCR_WIDBUS_D8 (2 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 10: 8-wide (STM32_SDMMC_D[7:0]) */ +#define STM32_SDMMC_CLKCR_NEGEDGE (1 << 13) /* Bit 13: STM32_SDMMC_CK dephasing selection bit */ +#define STM32_SDMMC_CLKCR_HWFC_EN (1 << 14) /* Bit 14: HW Flow Control enable */ + +#define STM32_SDMMC_CLKCR_RESET (0) /* Reset value */ + +#define STM32_SDMMC_ARG_RESET (0) /* Reset value */ + +#define STM32_SDMMC_CMD_CMDINDEX_SHIFT (0) +#define STM32_SDMMC_CMD_CMDINDEX_MASK (0x3f << STM32_SDMMC_CMD_CMDINDEX_SHIFT) +#define STM32_SDMMC_CMD_WAITRESP_SHIFT (6) /* Bits 7-6: Wait for response bits */ +#define STM32_SDMMC_CMD_WAITRESP_MASK (3 << STM32_SDMMC_CMD_WAITRESP_SHIFT) +# define STM32_SDMMC_CMD_NORESPONSE (0 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 00/10: No response */ +# define STM32_SDMMC_CMD_SHORTRESPONSE (1 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 01: Short response */ +# define STM32_SDMMC_CMD_LONGRESPONSE (3 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 11: Long response */ +#define STM32_SDMMC_CMD_WAITINT (1 << 8) /* Bit 8: CPSM waits for interrupt request */ +#define STM32_SDMMC_CMD_WAITPEND (1 << 9) /* Bit 9: CPSM Waits for ends of data transfer */ +#define STM32_SDMMC_CMD_CPSMEN (1 << 10) /* Bit 10: Command path state machine enable */ +#define STM32_SDMMC_CMD_SUSPEND (1 << 11) /* Bit 11: SD I/O suspend command */ +#define STM32_SDMMC_CMD_ENDCMD (1 << 12) /* Bit 12: Enable CMD completion */ +#define STM32_SDMMC_CMD_NIEN (1 << 13) /* Bit 13: not Interrupt Enable */ +#define STM32_SDMMC_CMD_ATACMD (1 << 14) /* Bit 14: CE-ATA command */ + +#define STM32_SDMMC_CMD_RESET (0) /* Reset value */ + +#define STM32_SDMMC_RESPCMD_SHIFT (0) +#define STM32_SDMMC_RESPCMD_MASK (0x3f << STM32_SDMMC_RESPCMD_SHIFT) + +#define STM32_SDMMC_DTIMER_RESET (0) /* Reset value */ + +#define STM32_SDMMC_DLEN_SHIFT (0) +#define STM32_SDMMC_DLEN_MASK (0x01ffffff << STM32_SDMMC_DLEN_SHIFT) + +#define STM32_SDMMC_DLEN_RESET (0) /* Reset value */ + +#define STM32_SDMMC_DCTRL_DTEN (1 << 0) /* Bit 0: Data transfer enabled bit */ +#define STM32_SDMMC_DCTRL_DTDIR (1 << 1) /* Bit 1: Data transfer direction */ +#define STM32_SDMMC_DCTRL_DTMODE (1 << 2) /* Bit 2: Data transfer mode */ +#define STM32_SDMMC_DCTRL_DMAEN (1 << 3) /* Bit 3: DMA enable bit */ +#define STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT (4) /* Bits 7-4: Data block size */ +#define STM32_SDMMC_DCTRL_DBLOCKSIZE_MASK (15 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_1BYTE (0 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_2BYTES (1 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_4BYTES (2 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_8BYTES (3 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_16BYTES (4 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_32BYTES (5 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_64BYTES (6 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_128BYTES (7 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_256BYTES (8 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_512BYTES (9 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_1KBYTE (10 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_2KBYTES (11 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_4KBYTES (12 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_8KBYTES (13 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +# define STM32_SDMMC_DCTRL_16KBYTES (14 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT) +#define STM32_SDMMC_DCTRL_RWSTART (1 << 8) /* Bit 8: Read wait start */ +#define STM32_SDMMC_DCTRL_RWSTOP (1 << 9) /* Bit 9: Read wait stop */ +#define STM32_SDMMC_DCTRL_RWMOD (1 << 10) /* Bit 10: Read wait mode */ +#define STM32_SDMMC_DCTRL_SDIOEN (1 << 11) /* Bit 11: SD I/O enable functions */ + +#define STM32_SDMMC_DCTRL_RESET (0) /* Reset value */ + +#define STM32_SDMMC_DCOUNT_SHIFT (0) +#define STM32_SDMMC_DCOUNT_MASK (0x01ffffff << STM32_SDMMC_DCOUNT_SHIFT) + +#define STM32_SDMMC_STA_CCRCFAIL (1 << 0) /* Bit 0: Command response CRC fail */ +#define STM32_SDMMC_STA_DCRCFAIL (1 << 1) /* Bit 1: Data block CRC fail */ +#define STM32_SDMMC_STA_CTIMEOUT (1 << 2) /* Bit 2: Command response timeout */ +#define STM32_SDMMC_STA_DTIMEOUT (1 << 3) /* Bit 3: Data timeout */ +#define STM32_SDMMC_STA_TXUNDERR (1 << 4) /* Bit 4: Transmit FIFO underrun error */ +#define STM32_SDMMC_STA_RXOVERR (1 << 5) /* Bit 5: Received FIFO overrun error */ +#define STM32_SDMMC_STA_CMDREND (1 << 6) /* Bit 6: Command response received */ +#define STM32_SDMMC_STA_CMDSENT (1 << 7) /* Bit 7: Command sent */ +#define STM32_SDMMC_STA_DATAEND (1 << 8) /* Bit 8: Data end */ +#define STM32_SDMMC_STA_STBITERR (1 << 9) /* Bit 9: Start bit not detected */ +#define STM32_SDMMC_STA_DBCKEND (1 << 10) /* Bit 10: Data block sent/received */ +#define STM32_SDMMC_STA_CMDACT (1 << 11) /* Bit 11: Command transfer in progress */ +#define STM32_SDMMC_STA_TXACT (1 << 12) /* Bit 12: Data transmit in progress */ +#define STM32_SDMMC_STA_RXACT (1 << 13) /* Bit 13: Data receive in progress */ +#define STM32_SDMMC_STA_TXFIFOHE (1 << 14) /* Bit 14: Transmit FIFO half empty */ +#define STM32_SDMMC_STA_RXFIFOHF (1 << 15) /* Bit 15: Receive FIFO half full */ +#define STM32_SDMMC_STA_TXFIFOF (1 << 16) /* Bit 16: Transmit FIFO full */ +#define STM32_SDMMC_STA_RXFIFOF (1 << 17) /* Bit 17: Receive FIFO full */ +#define STM32_SDMMC_STA_TXFIFOE (1 << 18) /* Bit 18: Transmit FIFO empty */ +#define STM32_SDMMC_STA_RXFIFOE (1 << 19) /* Bit 19: Receive FIFO empty */ +#define STM32_SDMMC_STA_TXDAVL (1 << 20) /* Bit 20: Data available in transmit FIFO */ +#define STM32_SDMMC_STA_RXDAVL (1 << 21) /* Bit 21: Data available in receive FIFO */ +#define STM32_SDMMC_STA_SDIOIT (1 << 22) /* Bit 22: SDIO interrupt received */ +#define STM32_SDMMC_STA_CEATAEND (1 << 23) /* Bit 23: CMD6 CE-ATA command completion */ + +#define STM32_SDMMC_ICR_CCRCFAILC (1 << 0) /* Bit 0: CCRCFAIL flag clear bit */ +#define STM32_SDMMC_ICR_DCRCFAILC (1 << 1) /* Bit 1: DCRCFAIL flag clear bit */ +#define STM32_SDMMC_ICR_CTIMEOUTC (1 << 2) /* Bit 2: CTIMEOUT flag clear bit */ +#define STM32_SDMMC_ICR_DTIMEOUTC (1 << 3) /* Bit 3: DTIMEOUT flag clear bit */ +#define STM32_SDMMC_ICR_TXUNDERRC (1 << 4) /* Bit 4: TXUNDERR flag clear bit */ +#define STM32_SDMMC_ICR_RXOVERRC (1 << 5) /* Bit 5: RXOVERR flag clear bit */ +#define STM32_SDMMC_ICR_CMDRENDC (1 << 6) /* Bit 6: CMDREND flag clear bit */ +#define STM32_SDMMC_ICR_CMDSENTC (1 << 7) /* Bit 7: CMDSENT flag clear bit */ +#define STM32_SDMMC_ICR_DATAENDC (1 << 8) /* Bit 8: DATAEND flag clear bit */ +#define STM32_SDMMC_ICR_STBITERRC (1 << 9) /* Bit 9: STBITERR flag clear bit */ +#define STM32_SDMMC_ICR_DBCKENDC (1 << 10) /* Bit 10: DBCKEND flag clear bit */ +#define STM32_SDMMC_ICR_SDIOITC (1 << 22) /* Bit 22: SDIOIT flag clear bit */ +#define STM32_SDMMC_ICR_CEATAENDC (1 << 23) /* Bit 23: CEATAEND flag clear bit */ + +#define STM32_SDMMC_ICR_RESET 0x00c007ff +#define STM32_SDMMC_ICR_STATICFLAGS 0x000005ff + +#define STM32_SDMMC_MASK_CCRCFAILIE (1 << 0) /* Bit 0: Command CRC fail interrupt enable */ +#define STM32_SDMMC_MASK_DCRCFAILIE (1 << 1) /* Bit 1: Data CRC fail interrupt enable */ +#define STM32_SDMMC_MASK_CTIMEOUTIE (1 << 2) /* Bit 2: Command timeout interrupt enable */ +#define STM32_SDMMC_MASK_DTIMEOUTIE (1 << 3) /* Bit 3: Data timeout interrupt enable */ +#define STM32_SDMMC_MASK_TXUNDERRIE (1 << 4) /* Bit 4: Tx FIFO underrun error interrupt enable */ +#define STM32_SDMMC_MASK_RXOVERRIE (1 << 5) /* Bit 5: Rx FIFO overrun error interrupt enable */ +#define STM32_SDMMC_MASK_CMDRENDIE (1 << 6) /* Bit 6: Command response received interrupt enable */ +#define STM32_SDMMC_MASK_CMDSENTIE (1 << 7) /* Bit 7: Command sent interrupt enable */ +#define STM32_SDMMC_MASK_DATAENDIE (1 << 8) /* Bit 8: Data end interrupt enable */ +#define STM32_SDMMC_MASK_STBITERRIE (1 << 9) /* Bit 9: Start bit error interrupt enable */ +#define STM32_SDMMC_MASK_DBCKENDIE (1 << 10) /* Bit 10: Data block end interrupt enable */ +#define STM32_SDMMC_MASK_CMDACTIE (1 << 11) /* Bit 11: Command acting interrupt enable */ +#define STM32_SDMMC_MASK_TXACTIE (1 << 12) /* Bit 12: Data transmit acting interrupt enable */ +#define STM32_SDMMC_MASK_RXACTIE (1 << 13) /* Bit 13: Data receive acting interrupt enable */ +#define STM32_SDMMC_MASK_TXFIFOHEIE (1 << 14) /* Bit 14: Tx FIFO half empty interrupt enable */ +#define STM32_SDMMC_MASK_RXFIFOHFIE (1 << 15) /* Bit 15: Rx FIFO half full interrupt enable */ +#define STM32_SDMMC_MASK_TXFIFOFIE (1 << 16) /* Bit 16: Tx FIFO full interrupt enable */ +#define STM32_SDMMC_MASK_RXFIFOFIE (1 << 17) /* Bit 17: Rx FIFO full interrupt enable */ +#define STM32_SDMMC_MASK_TXFIFOEIE (1 << 18) /* Bit 18: Tx FIFO empty interrupt enable */ +#define STM32_SDMMC_MASK_RXFIFOEIE (1 << 19) /* Bit 19: Rx FIFO empty interrupt enable */ +#define STM32_SDMMC_MASK_TXDAVLIE (1 << 20) /* Bit 20: Data available in Tx FIFO interrupt enable */ +#define STM32_SDMMC_MASK_RXDAVLIE (1 << 21) /* Bit 21: Data available in Rx FIFO interrupt enable */ +#define STM32_SDMMC_MASK_SDIOITIE (1 << 22) /* Bit 22: SDIO mode interrupt received interrupt enable */ +#define STM32_SDMMC_MASK_CEATAENDIE (1 << 23) /* Bit 23: CE-ATA command completion interrupt enable */ + +#define STM32_SDMMC_MASK_RESET (0) + +#define STM32_SDMMC_FIFOCNT_SHIFT (0) +#define STM32_SDMMC_FIFOCNT_MASK (0x0ffffff << STM32_SDMMC_FIFOCNT_SHIFT) + +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX77XX_SDMMC_H */ + diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_dbgmcu.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_dbgmcu.h new file mode 100644 index 0000000000000000000000000000000000000000..6804dc2574891d0e8233f868dc6a61d2bb51c7f1 --- /dev/null +++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_dbgmcu.h @@ -0,0 +1,113 @@ +/**************************************************************************** + * arch/arm/src/stm32f7/chip/stm32f76xx77xx_dbgmcu.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XXDBGMCU_H +#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XXDBGMCU_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register Addresses *******************************************************/ + +#define STM32_DBGMCU_IDCODE 0xe0042000 /* MCU identifier */ +#define STM32_DBGMCU_CR 0xe0042004 /* MCU debug */ +#define STM32_DBGMCU_APB1_FZ 0xe0042008 /* Debug MCU APB1 freeze register */ +#define STM32_DBGMCU_APB2_FZ 0xe004200c /* Debug MCU APB2 freeze register */ + +/* Register Bitfield Definitions ********************************************/ + +/* MCU identifier */ + +#define DBGMCU_IDCODE_DEVID_SHIFT (0) /* Bits 11-0: Device Identifier */ +#define DBGMCU_IDCODE_DEVID_MASK (0x0fff << DBGMCU_IDCODE_DEVID_SHIFT) +#define DBGMCU_IDCODE_REVID_SHIFT (16) /* Bits 31-16: Revision Identifier */ +#define DBGMCU_IDCODE_REVID_MASK (0xffff << DBGMCU_IDCODE_REVID_SHIFT) + +/* MCU debug */ + +#define DBGMCU_CR_SLEEP (1 << 0) /* Bit 0: Debug Sleep Mode */ +#define DBGMCU_CR_STOP (1 << 1) /* Bit 1: Debug Stop Mode */ +#define DBGMCU_CR_STANDBY (1 << 2) /* Bit 2: Debug Standby mode */ +#define DBGMCU_CR_TRACEIOEN (1 << 5) /* Bit 5: Trace enabled */ + +#define DBGMCU_CR_TRACEMODE_SHIFT (6) /* Bits 7-6: Trace mode pin assignement */ +#define DBGMCU_CR_TRACEMODE_MASK (3 << DBGMCU_CR_TRACEMODE_SHIFT) +#define DBGMCU_CR_ASYNCH (0 << DBGMCU_CR_TRACEMODE_SHIFT) /* Asynchronous Mode */ +#define DBGMCU_CR_SYNCH1 (1 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=1 */ +#define DBGMCU_CR_SYNCH2 (2 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=2 */ +#define DBGMCU_CR_SYNCH4 (3 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=4 */ + +/* Debug MCU APB1 freeze register */ + +#define DBGMCU_APB1_TIM2STOP (1 << 0) /* Bit 0: TIM2 stopped when core is halted */ +#define DBGMCU_APB1_TIM3STOP (1 << 1) /* Bit 1: TIM3 stopped when core is halted */ +#define DBGMCU_APB1_TIM4STOP (1 << 2) /* Bit 2: TIM4 stopped when core is halted */ +#define DBGMCU_APB1_TIM5STOP (1 << 3) /* Bit 3: TIM5 stopped when core is halted */ +#define DBGMCU_APB1_TIM6STOP (1 << 4) /* Bit 4: TIM6 stopped when core is halted */ +#define DBGMCU_APB1_TIM7STOP (1 << 5) /* Bit 5: TIM7 stopped when core is halted */ +#define DBGMCU_APB1_TIM12STOP (1 << 6) /* Bit 6: TIM12 stopped when core is halted */ +#define DBGMCU_APB1_TIM13STOP (1 << 7) /* Bit 7: TIM13 stopped when core is halted */ +#define DBGMCU_APB1_TIM14STOP (1 << 8) /* Bit 8: TIM14 stopped when core is halted */ +#define DBGMCU_APB1_LPTIM1STOP (1 << 9) /* Bit 9: LPTIM1 stopped when core is halted */ +#define DBGMCU_APB1_RTCSTOP (1 << 10) /* Bit 10: RTC stopped when Core is halted */ +#define DBGMCU_APB1_WWDGSTOP (1 << 11) /* Bit 11: Window Watchdog stopped when core is halted */ +#define DBGMCU_APB1_IWDGSTOP (1 << 12) /* Bit 12: Independent Watchdog stopped when core is halted */ +#define DBGMCU_APB1_CAN3STOP (1 << 13) /* Bit 13: CAN3 stopped when Core is halted */ +#define DBGMCU_APB1_I2C1STOP (1 << 21) /* Bit 21: I2C1 SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_APB1_I2C2STOP (1 << 22) /* Bit 22: I2C2 SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_APB1_I2C3STOP (1 << 23) /* Bit 23: I2C3 SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_APB1_I2C4STOP (1 << 24) /* Bit 24: I2C4 SMBUS timeout mode stopped when Core is halted */ +#define DBGMCU_APB1_CAN1STOP (1 << 25) /* Bit 25: CAN1 stopped when core is halted */ +#define DBGMCU_APB1_CAN2STOP (1 << 26) /* Bit 26: CAN2 stopped when core is halted */ + +/* Debug MCU APB2 freeze register */ + +#define DBGMCU_APB2_TIM1STOP (1 << 0) /* Bit 0: TIM1 stopped when core is halted */ +#define DBGMCU_APB2_TIM8STOP (1 << 1) /* Bit 1: TIM8 stopped when core is halted */ +#define DBGMCU_APB2_TIM9STOP (1 << 16) /* Bit 16: TIM9 stopped when core is halted */ +#define DBGMCU_APB2_TIM10STOP (1 << 17) /* Bit 17: TIM10 stopped when core is halted */ +#define DBGMCU_APB2_TIM11STOP (1 << 18) /* Bit 18: TIM11 stopped when core is halted */ + +#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XXDBGMCU_H */ diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h index fd1a41f36de6567bf23bb05bf27ee5a2cedf01db..81f3512fe6aa1af501df775da1ea7346b046b4b5 100644 --- a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h +++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_memorymap.h @@ -49,7 +49,7 @@ * Pre-processor Definitions ************************************************************************************/ -/* STM32F40XXX Address Blocks *******************************************************/ +/* STM32F76XXX STM32F77XXX Address Blocks *******************************************/ #define STM32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */ #define STM32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */ diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h index 4c60603c95a1d9b55317a36f2a9fbc685f3455b8..b2ded840dfbe9b42d98ae3fb2a09252a87893c8a 100644 --- a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h +++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_pinmap.h @@ -943,7 +943,7 @@ #define GPIO_SDMMC2_CMD (GPIO_ALT|GPIO_AF11|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTD|GPIO_PIN7) #define GPIO_SDMMC2_D0_1 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN14) #define GPIO_SDMMC2_D1_1 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN15) -#define GPIO_SDMMC2_D2_1 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN) +#define GPIO_SDMMC2_D2_1 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN3) #define GPIO_SDMMC2_D3_1 (GPIO_ALT|GPIO_AF10|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN4) #define GPIO_SDMMC2_D0_2 (GPIO_ALT|GPIO_AF11|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN9) #define GPIO_SDMMC2_D1_2 (GPIO_ALT|GPIO_AF11|GPIO_PULLUP|GPIO_SPEED_50MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN10) diff --git a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h index a63cc1911a46610233b14a9e06d7689c55caaef1..a1b9ed4e321aa78a42b106e18af5d988a39a1d64 100644 --- a/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h +++ b/arch/arm/src/stm32f7/chip/stm32f76xx77xx_rcc.h @@ -595,7 +595,7 @@ # define RCC_PLLI2SCFGR_PLLI2SN(n) ((uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SN_SHIFT) #define RCC_PLLI2SCFGR_PLLI2SP_SHIFT (16) /* Bits 16-17: PLLI2S division factor for SPDIFRX clock */ #define RCC_PLLI2SCFGR_PLLI2SP_MASK (3 << RCC_PLLI2SCFGR_PLLI2SP_SHIFT) -# define RCC_PLLI2SCFGR_PLLI2SP(n) ((uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SP_SHIFT) +# define RCC_PLLI2SCFGR_PLLI2SP(n) ((((n)>>1)-1) << RCC_PLLI2SCFGR_PLLI2SP_SHIFT) #define RCC_PLLI2SCFGR_PLLI2SQ_SHIFT (24) /* Bits 24-27: PLLI2S division factor for SAIs clock */ #define RCC_PLLI2SCFGR_PLLI2SQ_MASK (15 << RCC_PLLI2SCFGR_PLLI2SQ_SHIFT) # define RCC_PLLI2SCFGR_PLLI2SQ(n) ((uint32_t)(n) << RCC_PLLI2SCFGR_PLLI2SQ_SHIFT) @@ -610,7 +610,7 @@ # define RCC_PLLSAICFGR_PLLSAIN(n) ((n) << RCC_PLLSAICFGR_PLLSAIN_SHIFT) #define RCC_PLLSAICFGR_PLLSAIP_SHIFT (16) /* Bits 16-17: PLLSAI division factor for 48MHz clock */ #define RCC_PLLSAICFGR_PLLSAIP_MASK (3 << RCC_PLLSAICFGR_PLLSAIP_SHIFT) -# define RCC_PLLSAICFGR_PLLSAIP(n) ((n) << RCC_PLLSAICFGR_PLLSAIP_SHIFT) +# define RCC_PLLSAICFGR_PLLSAIP(n) ((((n)>>1)-1) << RCC_PLLSAICFGR_PLLSAIP_SHIFT) #define RCC_PLLSAICFGR_PLLSAIQ_SHIFT (24) /* Bits 24-27: PLLSAI division factor for SAI clock */ #define RCC_PLLSAICFGR_PLLSAIQ_MASK (0x0F << RCC_PLLSAICFGR_PLLSAIQ_SHIFT) # define RCC_PLLSAICFGR_PLLSAIQ(n) ((n) << RCC_PLLSAICFGR_PLLSAIQ_SHIFT) diff --git a/arch/arm/src/stm32f7/stm32_alarm.h b/arch/arm/src/stm32f7/stm32_alarm.h new file mode 100644 index 0000000000000000000000000000000000000000..ee0b8b89164b480fcf44e80be348a901522baa85 --- /dev/null +++ b/arch/arm/src/stm32f7/stm32_alarm.h @@ -0,0 +1,112 @@ +/**************************************************************************** + * arch/arm/src/include/stm32f7/stm32_alarm.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Neil hancock - delegated to Gregory Nutt Mar 30, 2016 + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_STM32_ALARM_H +#define __ARCH_ARM_SRC_STM32F7_STM32_ALARM_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#ifdef CONFIG_RTC_ALARM + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +typedef CODE void (*alm_callback_t)(FAR void *arg, unsigned int alarmid); + +/* These features map to STM32 RTC from stm32F7xx + */ + +enum alm_id_e +{ + RTC_ALARMA = 0, /* RTC ALARM A */ + RTC_ALARMB, /* RTC ALARM B */ + RTC_ALARM_LAST +}; + +/* Structure used to pass parameters to set an alarm */ + +struct alm_setalarm_s +{ + int as_id; /* enum alm_id_e */ + struct tm as_time; /* Alarm expiration time */ + alm_callback_t as_cb; /* Callback (if non-NULL) */ + FAR void *as_arg; /* Argument for callback */ +}; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_rtc_setalarm + * + * Description: + * Set an alarm to an absolute time using associated hardware. + * + * Input Parameters: + * alminfo - Information about the alarm configuration. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int stm32_rtc_setalarm(FAR struct alm_setalarm_s *alminfo); + +/**************************************************************************** + * Name: stm32_rtc_cancelalarm + * + * Description: + * Cancel an alarm. + * + * Input Parameters: + * alarmid - Identifies the alarm to be cancelled + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int stm32_rtc_cancelalarm(enum alm_id_e alarmid); + +#endif /* CONFIG_RTC_ALARM */ +#endif /* __ARCH_ARM_SRC_STM32F7_STM32_ALARM_H */ diff --git a/arch/arm/src/stm32f7/stm32_allocateheap.c b/arch/arm/src/stm32f7/stm32_allocateheap.c index 541e0654b1fd42c68d1f67139b3334157ab78e88..8b21ad68b762db71e7969c8f92e8429bdb3d6525 100644 --- a/arch/arm/src/stm32f7/stm32_allocateheap.c +++ b/arch/arm/src/stm32f7/stm32_allocateheap.c @@ -41,6 +41,7 @@ #include #include +#include #include #include diff --git a/arch/arm/src/stm32f7/stm32_bbsram.c b/arch/arm/src/stm32f7/stm32_bbsram.c new file mode 100644 index 0000000000000000000000000000000000000000..bd653cfe56855ad3d97a57ee7f31dea8a0f513d0 --- /dev/null +++ b/arch/arm/src/stm32f7/stm32_bbsram.c @@ -0,0 +1,886 @@ +/**************************************************************************** + * arch/arm/src/stm32f7/stm32_bbsram.c + * + * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* This will driver create a set of files in the STM32's Battery backed up + * SRAM. That can be used to store data retained across power cycles. + * + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "stm32_bbsram.h" +#include "chip.h" +#include "stm32_pwr.h" +#include "stm32_rtc.h" + +#ifdef CONFIG_STM32F7_BBSRAM + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if !defined(CONFIG_STM32F7_BKPSRAM) +#error Driver Requires CONFIG_STM32F7_BKPSRAM to be enabled +#endif + +#define MAX_OPENCNT (255) /* Limit of uint8_t */ + +#ifndef CONFIG_DEBUG_INFO +# undef CONFIG_BBSRAM_DEBUG +#endif + +#if defined(CONFIG_BBSRAM_DEBUG) +# define BBSRAM_DEBUG_READ() stm32_bbsram_rd() +# define BBSRAM_DUMP(p,s) stm32_bbsram_dump(p,s) +#else +# define BBSRAM_DEBUG_READ() +# define BBSRAM_DUMP(p,s) +#endif + +#define BBSRAM_HEADER_SIZE (sizeof(struct bbsramfh_s)) +#define BBSRAM_CRCED_OFFSET (sizeof(((struct bbsramfh_s *)0)->crc)) +#define BBSRAM_CRCED_SIZE(l) (BBSRAM_HEADER_SIZE-(BBSRAM_CRCED_OFFSET)+(l)) +#define BBSRAM_ALIGNMENT (sizeof(((struct bbsramfh_s *)0)->crc)) +#define BBSRAM_ALIGNMENT_MASK (BBSRAM_ALIGNMENT-1) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* File Header */ + +struct bbsramfh_s +{ + uint32_t crc; /* CRC calculated over data and this struct + * starting at fileno */ + uint8_t fileno; /* The minor number */ + uint8_t dirty; /* Data has been written to the file */ + uint16_t len; /* Total Bytes in this file */ + struct timespec lastwrite; /* Last write time */ + uint8_t data[]; /* Data in the file */ +}; + +struct stm32_bbsram_s +{ + sem_t exclsem; /* For atomic accesses to this structure */ + uint8_t refs; /* Number of references */ + FAR struct bbsramfh_s *bbf; /* File in bbram */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int stm32_bbsram_open(FAR struct file *filep); +static int stm32_bbsram_close(FAR struct file *filep); +static off_t stm32_bbsram_seek(FAR struct file *filep, off_t offset, + int whence); +static ssize_t stm32_bbsram_read(FAR struct file *filep, FAR char *buffer, + size_t len); +static ssize_t stm32_bbsram_write(FAR struct file *filep, + FAR const char *buffer, size_t len); +static int stm32_bbsram_ioctl(FAR struct file *filep, int cmd, + unsigned long arg); +#ifndef CONFIG_DISABLE_POLL +static int stm32_bbsram_poll(FAR struct file *filep, FAR struct pollfd *fds, + bool setup); +#endif +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS +static int stm32_bbsram_unlink(FAR struct inode *inode); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#if defined(CONFIG_BBSRAM_DEBUG) +static uint8_t debug[STM32F7_BBSRAM_SIZE]; +#endif + +static const struct file_operations stm32_bbsram_fops = +{ + .open = stm32_bbsram_open, + .close = stm32_bbsram_close, + .read = stm32_bbsram_read, + .write = stm32_bbsram_write, + .seek = stm32_bbsram_seek, + .ioctl = stm32_bbsram_ioctl, +#ifndef CONFIG_DISABLE_POLL + .poll = stm32_bbsram_poll, +#endif +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS + .unlink = stm32_bbsram_unlink, +#endif +}; + +static struct stm32_bbsram_s g_bbsram[CONFIG_STM32F7_BBSRAM_FILES]; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bbsram_rd + ****************************************************************************/ + +#if defined(CONFIG_BBSRAM_DEBUG) +static void stm32_bbsram_rd(void) +{ + memcpy(&debug, (uint8_t *)STM32_BKPSRAM_BASE, sizeof debug); +} +#endif + +/**************************************************************************** + * Name: stm32_bbsram_rd + ****************************************************************************/ + +#if defined(CONFIG_BBSRAM_DEBUG) +static void stm32_bbsram_dump(FAR struct bbsramfh_s *bbf, char *op) +{ + BBSRAM_DEBUG_READ(); + _info("%s:\n", op); + _info(" File Address:0x%8x\n", bbf); + _info(" crc:0x%8x\n", bbf->crc); + _info(" fileno:%d\n", (int) bbf->fileno); + _info(" dirty:%d\n", (int) bbf->dirty); + _info(" length:%d\n", (int) bbf->len); + _info(" time:%ld:%ld\n", bbf->lastwrite.tv_sec, bbf->lastwrite.tv_nsec); + _info(" data: 0x%2x 0x%2x 0x%2x 0x%2x 0x%2x\n", + bbf->data[0], bbf->data[1], bbf->data[2], bbf->data[3], bbf->data[4]); +} +#endif + +/**************************************************************************** + * Name: stm32_bbsram_semgive + ****************************************************************************/ + +static void stm32_bbsram_semgive(FAR struct stm32_bbsram_s *priv) +{ + sem_post(&priv->exclsem); +} + +/**************************************************************************** + * Name: stm32_bbsram_semtake + * + * Description: + * Take a semaphore handling any exceptional conditions + * + * Input Parameters: + * priv - A reference to the CAN peripheral state + * + * Returned Value: + * None + * +****************************************************************************/ + +static void stm32_bbsram_semtake(FAR struct stm32_bbsram_s *priv) +{ + int ret; + + /* Wait until we successfully get the semaphore. EINTR is the only + * expected 'failure' (meaning that the wait for the semaphore was + * interrupted by a signal. + */ + + do + { + ret = sem_wait(&priv->exclsem); + DEBUGASSERT(ret == 0 || errno == EINTR); + } + while (ret < 0); +} + +/**************************************************************************** + * Name: stm32_bbsram_ulock + * + * Description: + * Unprotects RTC registers, RTC backup data registers and backup SRAM + * against parasitic write access + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void stm32_bbsram_unlock(void) +{ + (void)stm32_pwr_enablebkp(true); +} + +/**************************************************************************** + * Name: stm32_bbsram_lock + * + * Description: + * Protects RTC registers, RTC backup data registers and backup SRAM + * against parasitic write access + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void stm32_bbsram_lock(void) +{ + (void)stm32_pwr_enablebkp(false); +} + +/**************************************************************************** + * Name: stm32_bbsram_crc + * + * Description: + * Calculates the CRC of the block + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static uint32_t stm32_bbsram_crc(FAR struct bbsramfh_s *pf) +{ + return crc32((uint8_t *)pf + BBSRAM_CRCED_OFFSET, BBSRAM_CRCED_SIZE(pf->len)); +} + +/**************************************************************************** + * Name: stm32_bbsram_open + * + * Description: Open the device + * + ****************************************************************************/ + +static int stm32_bbsram_open(FAR struct file *filep) +{ + FAR struct inode *inode = filep->f_inode; + FAR struct stm32_bbsram_s *bbr; + + DEBUGASSERT(inode && inode->i_private); + bbr = (FAR struct stm32_bbsram_s *)inode->i_private; + + /* Increment the reference count */ + + stm32_bbsram_semtake(bbr); + if (bbr->refs == MAX_OPENCNT) + { + return -EMFILE; + } + else + { + bbr->refs++; + } + + stm32_bbsram_semgive(bbr); + return OK; +} + +/**************************************************************************** + * Name: stm32_bbsram_internal_close + * + * Description: + * Close BBSRAM entry; Recalculate the time and crc + * + ****************************************************************************/ + +static int stm32_bbsram_internal_close(FAR struct bbsramfh_s *bbf) +{ + bbf->dirty = 0; + (void)clock_gettime(CLOCK_REALTIME, &bbf->lastwrite); + bbf->crc = stm32_bbsram_crc(bbf); + + BBSRAM_DUMP(bbf, "close done"); + return bbf->len; +} + +/**************************************************************************** + * Name: stm32_bbsram_close + * + * Description: close the device + * + ****************************************************************************/ + +static int stm32_bbsram_close(FAR struct file *filep) +{ + FAR struct inode *inode = filep->f_inode; + FAR struct stm32_bbsram_s *bbr; + int ret = OK; + + DEBUGASSERT(inode && inode->i_private); + bbr = (FAR struct stm32_bbsram_s *)inode->i_private; + + stm32_bbsram_semtake(bbr); + + BBSRAM_DUMP(bbr->bbf, "close"); + + if (bbr->refs == 0) + { + ret = -EIO; + } + else + { + bbr->refs--; + + if (bbr->refs == 0) + { + if (bbr->bbf->dirty) + { + /* Recalculate the time and crc */ + + stm32_bbsram_unlock(); + stm32_bbsram_internal_close(bbr->bbf); + stm32_bbsram_lock(); + } + } + } + + stm32_bbsram_semgive(bbr); + return ret; +} + +/**************************************************************************** + * Name: stm32_bbsram_seek + ****************************************************************************/ + +static off_t stm32_bbsram_seek(FAR struct file *filep, off_t offset, + int whence) +{ + FAR struct inode *inode = filep->f_inode; + FAR struct stm32_bbsram_s *bbr; + off_t newpos; + int ret; + + DEBUGASSERT(inode && inode->i_private); + bbr = (FAR struct stm32_bbsram_s *)inode->i_private; + + stm32_bbsram_semtake(bbr); + + /* Determine the new, requested file position */ + + switch (whence) + { + case SEEK_CUR: + newpos = filep->f_pos + offset; + break; + + case SEEK_SET: + newpos = offset; + break; + + case SEEK_END: + newpos = bbr->bbf->len + offset; + break; + + default: + /* Return EINVAL if the whence argument is invalid */ + + stm32_bbsram_semgive(bbr); + return -EINVAL; + } + + /* Opengroup.org: + * + * "The lseek() function shall allow the file offset to be set beyond the end + * of the existing data in the file. If data is later written at this point, + * subsequent reads of data in the gap shall return bytes with the value 0 + * until data is actually written into the gap." + * + * We can conform to the first part, but not the second. But return EINVAL if + * + * "...the resulting file offset would be negative for a regular file, block + * special file, or directory." + */ + + if (newpos >= 0) + { + filep->f_pos = newpos; + ret = newpos; + } + else + { + ret = -EINVAL; + } + + stm32_bbsram_semgive(bbr); + return ret; +} + +/**************************************************************************** + * Name: stm32_bbsram_read + ****************************************************************************/ + +static ssize_t stm32_bbsram_read(FAR struct file *filep, FAR char *buffer, + size_t len) +{ + FAR struct inode *inode = filep->f_inode; + FAR struct stm32_bbsram_s *bbr; + + DEBUGASSERT(inode && inode->i_private); + bbr = (FAR struct stm32_bbsram_s *)inode->i_private; + + stm32_bbsram_semtake(bbr); + + /* Trim len if read would go beyond end of device */ + + if ((filep->f_pos + len) > bbr->bbf->len) + { + len = bbr->bbf->len - filep->f_pos; + } + + memcpy(buffer, &bbr->bbf->data[filep->f_pos], len); + filep->f_pos += len; + stm32_bbsram_semgive(bbr); + return len; +} + +/**************************************************************************** + * Name: stm32_bbsram_internal_write + ****************************************************************************/ + +static ssize_t stm32_bbsram_internal_write(FAR struct bbsramfh_s *bbf, + FAR const char *buffer, + off_t offset, size_t len) +{ + bbf->dirty = 1; + memcpy(&bbf->data[offset], buffer, len); + return len; +} + +/**************************************************************************** + * Name: stm32_bbsram_write + ****************************************************************************/ + +static ssize_t stm32_bbsram_write(FAR struct file *filep, + FAR const char *buffer, size_t len) +{ + FAR struct inode *inode = filep->f_inode; + FAR struct stm32_bbsram_s *bbr; + int ret = -EFBIG; + + DEBUGASSERT(inode && inode->i_private); + bbr = (FAR struct stm32_bbsram_s *)inode->i_private; + + /* Forbid writes past the end of the device */ + + if (filep->f_pos < bbr->bbf->len) + { + /* Clamp len to avoid crossing the end of the memory */ + + if ((filep->f_pos + len) > bbr->bbf->len) + { + len = bbr->bbf->len - filep->f_pos; + } + + ret = len; /* save number of bytes written */ + + stm32_bbsram_semtake(bbr); + BBSRAM_DUMP(bbr->bbf, "write"); + stm32_bbsram_unlock(); + stm32_bbsram_internal_write(bbr->bbf, buffer, filep->f_pos, len); + stm32_bbsram_lock(); + filep->f_pos += len; + BBSRAM_DUMP(bbr->bbf, "write done"); + stm32_bbsram_semgive(bbr); + } + + BBSRAM_DEBUG_READ(); + return ret; +} + +/**************************************************************************** + * Name: stm32_bbsram_poll + ****************************************************************************/ + +#ifndef CONFIG_DISABLE_POLL +static int stm32_bbsram_poll(FAR struct file *filep, FAR struct pollfd *fds, + bool setup) +{ + if (setup) + { + fds->revents |= (fds->events & (POLLIN | POLLOUT)); + if (fds->revents != 0) + { + sem_post(fds->sem); + } + } + + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32_bbsram_ioctl + * + * Description: Return device geometry + * + ****************************************************************************/ + +static int stm32_bbsram_ioctl(FAR struct file *filep, int cmd, + unsigned long arg) +{ + FAR struct inode *inode = filep->f_inode; + FAR struct stm32_bbsram_s *bbr; + int ret = -ENOTTY; + + DEBUGASSERT(inode && inode->i_private); + bbr = (FAR struct stm32_bbsram_s *)inode->i_private; + + if (cmd == STM32F7_BBSRAM_GETDESC_IOCTL) + { + FAR struct bbsramd_s *bbrr = (FAR struct bbsramd_s *)((uintptr_t)arg); + + stm32_bbsram_semtake(bbr); + if (!bbrr) + { + ret = -EINVAL; + } + else + { + bbrr->fileno = bbr->bbf->fileno; + bbrr->lastwrite = bbr->bbf->lastwrite; + bbrr->len = bbr->bbf->len; + bbrr->flags = ((bbr->bbf->crc == stm32_bbsram_crc(bbr->bbf)) + ? BBSRAM_CRC_VALID : 0); + bbrr->flags |= ((bbr->bbf->dirty) ? BBSRAM_DIRTY : 0); + ret = OK; + } + + stm32_bbsram_semgive(bbr); + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_bbsram_unlink + * + * Description: + * This function will remove the remove the file from the file system + * it will zero the contents and time stamp. It will leave the fileno + * and pointer to the BBSRAM intact. + * It should be called called on the the file used for the crash dump + * to remove it from visibility in the file system after it is created or + * read thus arming it. + * + ****************************************************************************/ + +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS +static int stm32_bbsram_unlink(FAR struct inode *inode) +{ + FAR struct stm32_bbsram_s *bbr; + + DEBUGASSERT(inode && inode->i_private); + bbr = (FAR struct stm32_bbsram_s *)inode->i_private; + + stm32_bbsram_semtake(bbr); + stm32_bbsram_unlock(); + memset(bbr->bbf->data, 0, bbr->bbf->len); + bbr->bbf->lastwrite.tv_nsec = 0; + bbr->bbf->lastwrite.tv_sec = 0; + bbr->bbf->crc = stm32_bbsram_crc(bbr->bbf); + stm32_bbsram_lock(); + bbr->refs = 0; + stm32_bbsram_semgive(bbr); + sem_destroy(&bbr->exclsem); + return 0; +} +#endif + +/**************************************************************************** + * Name: stm32_bbsram_probe + * + * Description: Based on the number of files defined and their sizes + * Initializes the base pointers to the file entries. + * + ****************************************************************************/ + +static int stm32_bbsram_probe(int *ent, struct stm32_bbsram_s pdev[]) +{ + int i; + int avail = STM32F7_BBSRAM_SIZE; + int alloc; + int size; + int ret = -EFBIG; + struct bbsramfh_s *pf = (struct bbsramfh_s *) STM32_BKPSRAM_BASE; + + for (i = 0; (i < CONFIG_STM32F7_BBSRAM_FILES) && ent[i] && (avail > 0); i++) + { + /* Validate the actual allocations against what is in the BBSRAM */ + + size = ent[i]; + + /* Use all that is left */ + + if (size == -1) + { + size = avail - (BBSRAM_HEADER_SIZE + BBSRAM_ALIGNMENT_MASK); + } + + /* Add in header size and keep aligned */ + + alloc = size + BBSRAM_HEADER_SIZE + BBSRAM_ALIGNMENT_MASK; + alloc &= ~(BBSRAM_ALIGNMENT_MASK); + + /* Does it fit? */ + + if (alloc <= avail) + { + ret = i + 1; + BBSRAM_DUMP(pf, "probe"); + + if (pf->len != size || + pf->fileno != i || + pf->crc != stm32_bbsram_crc(pf)) + { + + /* Not Valid so wipe the file in BBSRAM */ + + memset((uint8_t *)pf, 0, alloc); + pf->fileno = i; + pf->len = size; + pf->crc = stm32_bbsram_crc(pf); + BBSRAM_DUMP(pf, "probe reset"); + } + + pdev[i].bbf = pf; + pf = (struct bbsramfh_s *)((uint8_t *)pf + alloc); + sem_init(&g_bbsram[i].exclsem, 0, 1); + } + + avail -= alloc; + } + + BBSRAM_DEBUG_READ(); + return ret; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: stm32_bbsraminitialize + * + * Description: + * Initialize the Battery Backed up SRAM driver. + * + * Parameters: + * devpath - the path to instantiate the files. + * sizes - Pointer to a any array of file sizes to create + * the last entry should be 0 + * A size of -1 will use all the remaining spaces + * + * If the length of sizes is greater then CONFIG_STM32_BBSRAM_FILES + * CONFIG_STM32_BBSRAM_FILES will be returned. + * + * Returned Value: + * Number of files created on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +int stm32_bbsraminitialize(char *devpath, int *sizes) +{ + int i; + int fcnt; + char path[32]; + char devname[32]; + + int ret = OK; + + if (devpath == NULL) + { + return -EINVAL; + } + + i = strlen(devpath); + if (i == 0 || i > sizeof(path) + 3) + { + return -EINVAL; + } + + memset(g_bbsram, 0, sizeof(g_bbsram)); + + /* Clocking for the PWR block must be provided. However, this is done + * unconditionally in stm32f7xxxx_rcc.c on power up. This done + * unconditionally because the PWR block is also needed to set the + * internal voltage regulator for maximum performance. + */ + + /* Enable backup SRAM clock is done in rcc_enableahb1() when + * CONFIG_STM32_BKPSRAM is defined. + */ + + /* Allow Access */ + + stm32_bbsram_unlock(); + + /* Enable backup regulator so that the data is retained in Standby and + * VBAT modes + */ + + stm32_pwr_enablebreg(true); + + fcnt = stm32_bbsram_probe(sizes, g_bbsram); + + strncpy(path, devpath, sizeof(path)); + strcat(path, "%d"); + + for (i = 0; i < fcnt && ret >= OK; i++) + { + snprintf(devname, sizeof(devname), path, i); + ret = register_driver(devname, &stm32_bbsram_fops, 0666, &g_bbsram[i]); + } + + /* Disallow Access */ + + stm32_bbsram_lock(); + return ret < OK ? ret : fcnt; +} + +/**************************************************************************** + * Function: stm32_bbsram_savepanic + * + * Description: + * Saves the panic context in a previously allocated BBSRAM file + * + * Parameters: + * fileno - the value returned by the ioctl STM32_BBSRAM_GETDESC_IOCTL + * context - Pointer to a any array of bytes to save + * length - The length of the data pointed to byt context + * + * Returned Value: + * Length saved or negated errno. + * + * Assumptions: + * + ****************************************************************************/ + +#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length) +{ + FAR struct bbsramfh_s *bbf; + int fill; + int ret = -ENOSPC; + + /* On a bad day we could panic while panicking, (and we debug assert) + * this is a potential feeble attempt at only writing the first + * panic's context to the file + */ + + static bool once = false; + + if (!once) + { + once = true; + + DEBUGASSERT(fileno > 0 && fileno < CONFIG_STM32F7_BBSRAM_FILES); + + bbf = g_bbsram[fileno].bbf; + + DEBUGASSERT(bbf); + + /* If the g_bbsram has been nulled out we return ENXIO. + * + * As once ensures we will keep the first dump. Checking the time for + * 0 protects from over writing a previous crash dump that has not + * been saved to long term storage and erased. The dreaded reboot + * loop. + */ + + if (!bbf) + { + ret = -ENXIO; + } + else if ((bbf->lastwrite.tv_sec == 0 && bbf->lastwrite.tv_nsec == 0)) + { + /* Clamp length if too big */ + + if (length > bbf->len) + { + length = bbf->len; + } + + stm32_bbsram_unlock(); + + stm32_bbsram_internal_write(bbf, (char *) context, 0, length); + + /* Fill with 0 if data is less then file size */ + + fill = (int) bbf->len - length; + + if (fill > 0) + { + memset(&bbf->data[length], 0, fill); + } + + /* Seal the file */ + + stm32_bbsram_internal_close(bbf); + + stm32_bbsram_lock(); + ret = length; + } + } + + return ret; +} +#endif + +#endif /* CONFIG_BBSRAM_DRIVER */ diff --git a/arch/arm/src/stm32f7/stm32_bbsram.h b/arch/arm/src/stm32f7/stm32_bbsram.h new file mode 100644 index 0000000000000000000000000000000000000000..554a0c60df84bb78ec0d2ff569117b9033d9a62f --- /dev/null +++ b/arch/arm/src/stm32f7/stm32_bbsram.h @@ -0,0 +1,165 @@ +/**************************************************************************** + * arch/arm/src/stm32f7/stm32_bbsram.h + * + * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_STM32_BBSRAM_H +#define __ARCH_ARM_SRC_STM32F7_STM32_BBSRAM_H + +/**************************************************************************** + * The purpose of this driver is to add battery backup file to the file + * system. There can be CONFIG_STM32F7_BBRSRAM_COUNT files defined. + * These files are of fixed size up to the maximum of the backing 4K SRAM. + * + * If CONFIG_SAVE_CRASHDUMP is defined The driver also supports a feature + * to save the context of a PANIC in one of these files. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \ + defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +# define STM32F7_BBSRAM_SIZE 4096 +#else +# error "No backup SRAM on this STM32 Device" +#endif + +#if !defined(CONFIG_STM32F7_BBSRAM_FILES) +# define CONFIG_STM32F7_BBSRAM_FILES 4 +#endif + +/* REVISIT: What guarantees that STM32F7_BBSRAM_GETDESC_IOCTL has a unique + * value among all over _DIOC() values? + */ + +#define STM32F7_BBSRAM_GETDESC_IOCTL _DIOC(0x0010) /* Returns a bbsramd_s */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +enum bbsramdf_e +{ + BBSRAM_CRC_VALID = 1, /* The crc is valid */ + BBSRAM_DIRTY = 2, /* The file was closed */ +}; + +struct bbsramd_s +{ + uint8_t flags; /* The crc is valid and the file was closed */ + uint8_t fileno; /* The minor number */ + uint16_t len; /* Total Bytes in this file*/ + struct timespec lastwrite; /* Last write time */ +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +# define EXTERN extern "C" +extern "C" +{ +#else +# define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ +/**************************************************************************** + * Function: stm32_bbsraminitialize + * + * Description: + * Initialize the Battery Backed up SRAM driver. + * + * Parameters: + * devpath - the path to instantiate the files. + * sizes - Pointer to a any array of file sizes to create + * the last entry should be 0 + * A size of -1 will use all the remaining spaces + * + * If the length of sizes is greater then CONFIG_STM32F7_BBSRAM_FILES + * CONFIG_STM32F7_BBSRAM_FILES will be returned. + * + * Returned Value: + * Number of files created on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +int stm32_bbsraminitialize(char *devpath, int *sizes); + +/**************************************************************************** +* Function: stm32_bbsram_savepanic +* +* Description: +* Saves the panic context in a previously allocated BBSRAM file +* +* Parameters: +* fileno - the value returned by the ioctl STM32F7_BBSRAM_GETDESC_IOCTL +* context - Pointer to a any array of bytes to save +* length - The length of the data pointed to byt context +* +* Returned Value: +* Length saved or negated errno. +* +* Assumptions: +* +****************************************************************************/ + +#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length); +#endif + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_STM32F7_STM32_BBSRAM_H */ diff --git a/arch/arm/src/stm32f7/stm32_dbgmcu.h b/arch/arm/src/stm32f7/stm32_dbgmcu.h new file mode 100644 index 0000000000000000000000000000000000000000..0aef4d5f0a0284c023b58a8e6877f5e5db64921c --- /dev/null +++ b/arch/arm/src/stm32f7/stm32_dbgmcu.h @@ -0,0 +1,48 @@ +/**************************************************************************** + * arch/arm/src/stm32f7/stm32_dbgmcu.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_STM32_DBGMCU_H +#define __ARCH_ARM_SRC_STM32F7_STM32_DBGMCU_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "chip/stm32_dbgmcu.h" + +#endif /* __ARCH_ARM_SRC_STM32F7_STM32_DBGMCU_H */ diff --git a/arch/arm/src/stm32f7/stm32_dma.c b/arch/arm/src/stm32f7/stm32_dma.c index 7b03377bcccdfc02d705472da1848db21d385088..adfee405cc8a61e6dfed1759e3ed3827cf57f54a 100644 --- a/arch/arm/src/stm32f7/stm32_dma.c +++ b/arch/arm/src/stm32f7/stm32_dma.c @@ -521,9 +521,9 @@ void weak_function up_dmainitialize(void) * version. Feel free to do that if that is what you need. * * Input parameter: - * dmamap - Identifies the stream/channel resource. For the STM32 F4, this + * dmamap - Identifies the stream/channel resource. For the STM32 F7, this * is a bit-encoded value as provided by the DMAMAP_* definitions - * in chip/stm32f40xxx_dma.h + * in chip/stm32f7xxxxxxx_dma.h * * Returned Value: * Provided that 'dmamap' is valid, this function ALWAYS returns a non-NULL, diff --git a/arch/arm/src/stm32f7/stm32_dma.h b/arch/arm/src/stm32f7/stm32_dma.h index f78221c94993234f6e1cc18a4f383db37263b488..70b5173467f171e89f82752adc16fe95443c963e 100644 --- a/arch/arm/src/stm32f7/stm32_dma.h +++ b/arch/arm/src/stm32f7/stm32_dma.h @@ -62,8 +62,8 @@ * Public Types ************************************************************************************/ -/* DMA_HANDLE provides an opaque are reference that can be used to represent a DMA - * channel (F1) or a DMA stream (F4). +/* DMA_HANDLE Provides an opaque are reference that can be used to represent a DMA + * a DMA stream. */ typedef FAR void *DMA_HANDLE; @@ -137,10 +137,8 @@ extern "C" * * Input parameter: * chan - Identifies the stream/channel resource - * For the STM32 F1, this is simply the channel number as provided by - * the DMACHAN_* definitions in chip/stm32f10xxx_dma.h. - * For the STM32 F4, this is a bit encoded value as provided by the - * the DMAMAP_* definitions in chip/stm32f40xxx_dma.h + * For the STM32 F7, this is a bit encoded value as provided by the + * the DMAMAP_* definitions in chip/stm32f7xxxxxxx_dma.h * * Returned Value: * Provided that 'chan' is valid, this function ALWAYS returns a non-NULL, diff --git a/arch/arm/src/stm32f7/stm32_dtcm.h b/arch/arm/src/stm32f7/stm32_dtcm.h index a3e76330e917e10d0c68bf8aacdefc7ee1c0293d..0b52bcf96c2fd64fee52861915b5ac3e2e29f09c 100644 --- a/arch/arm/src/stm32f7/stm32_dtcm.h +++ b/arch/arm/src/stm32f7/stm32_dtcm.h @@ -1,8 +1,9 @@ /**************************************************************************** * arch/arm/src/stm32f7/stm32_dtcm.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -52,14 +53,14 @@ #define HAVE_DTCM_HEAP 1 -/* Only the STM32 F2, F3, and F4 have DTCM memory */ +/* The STM32 F7 have DTCM memory */ -#if defined(CONFIG_STM32_STM32F30XX) -# define DTCM_START 0x10000000 -# define DTCM_END 0x10002000 -#elif defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX) -# define DTCM_START 0x10000000 -# define DTCM_END 0x10010000 +#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) +# define DTCM_START 0x20000000 +# define DTCM_END 0x20010000 +#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX) +# define DTCM_START 0x20000000 +# define DTCM_END 0x20020000 #else # undef HAVE_DTCM_HEAP #endif @@ -68,7 +69,7 @@ * heap. */ -#ifndef CONFIG_STM32_DTCMEXCLUDE +#ifndef CONFIG_STM32F7_DTCMEXCLUDE # undef HAVE_DTCM_HEAP #endif diff --git a/arch/arm/src/stm32f7/stm32_exti_pwr.h b/arch/arm/src/stm32f7/stm32_exti_pwr.h new file mode 100644 index 0000000000000000000000000000000000000000..b72acd5cc9fcaeeec51b942753151befd7ebeedc --- /dev/null +++ b/arch/arm/src/stm32f7/stm32_exti_pwr.h @@ -0,0 +1,72 @@ +/**************************************************************************** + * arch/arm/src/stm32f7/stm32_exti_pwr.h + * + * Copyright (C) 2015 Haltian Ltd. All rights reserved. + * Authors: Dmitry Nikolaev + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_STM32_EXTI_PWR_H +#define __ARCH_ARM_SRC_STM32F7_STM32_EXTI_PWR_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_exti_pvd + * + * Description: + * Sets/clears EXTI PVD interrupt. + * + * Parameters: + * - rising/falling edge: enables interrupt on rising/falling edge + * - event: generate event when set + * - func: when non-NULL, generate interrupt + * + * Returns: + * The previous value of the interrupt handler function pointer. This + * value may, for example, be used to restore the previous handler when + * multiple handlers are used. + * + ****************************************************************************/ + +xcpt_t stm32_exti_pvd(bool risingedge, bool fallingedge, bool event, + xcpt_t func); + +#endif /* __ARCH_ARM_SRC_STM32F7_STM32_EXTI_PWR_H */ diff --git a/arch/arm/src/stm32f7/stm32_irq.c b/arch/arm/src/stm32f7/stm32_irq.c index eb7a8e1b868399ee96bd2a03216db11fbc34be50..758f32b14778b41a3317ea5c7b6c11815db4e1ad 100644 --- a/arch/arm/src/stm32f7/stm32_irq.c +++ b/arch/arm/src/stm32f7/stm32_irq.c @@ -656,7 +656,7 @@ int up_prioritize_irq(int irq, int priority) uint32_t regval; int shift; - DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < STM32_IRQ_NIRQS && + DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN); if (irq < STM32_IRQ_FIRST) diff --git a/arch/arm/src/stm32f7/stm32_lsi.c b/arch/arm/src/stm32f7/stm32_lsi.c new file mode 100644 index 0000000000000000000000000000000000000000..46e961637277fb452dfdb0c553bf298eca6b0047 --- /dev/null +++ b/arch/arm/src/stm32f7/stm32_lsi.c @@ -0,0 +1,89 @@ +/**************************************************************************** + * arch/arm/src/stm32f/stm32_lsi.c + * + * Copyright (C) 2012, 2015-2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include "up_arch.h" + +#include "stm32_rcc.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_rcc_enablelsi + * + * Description: + * Enable the Internal Low-Speed (LSI) RC Oscillator. + * + ****************************************************************************/ + +void stm32_rcc_enablelsi(void) +{ + /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION + * bit the RCC CSR register. + */ + + modifyreg32(STM32_RCC_CSR, 0, RCC_CSR_LSION); + + /* Wait for the internal RC 40 kHz oscillator to be stable. */ + + while ((getreg32(STM32_RCC_CSR) & RCC_CSR_LSIRDY) == 0); +} + +/**************************************************************************** + * Name: stm32_rcc_disablelsi + * + * Description: + * Disable the Internal Low-Speed (LSI) RC Oscillator. + * + ****************************************************************************/ + +void stm32_rcc_disablelsi(void) +{ + /* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION + * bit the RCC CSR register. + */ + + modifyreg32(STM32_RCC_CSR, RCC_CSR_LSION, 0); + + /* LSIRDY should go low after 3 LSI clock cycles */ +} diff --git a/arch/arm/src/stm32f7/stm32_otg.h b/arch/arm/src/stm32f7/stm32_otg.h new file mode 100644 index 0000000000000000000000000000000000000000..7eba65a61ba4b4b6c0a72cee6d8b50b8d3be108b --- /dev/null +++ b/arch/arm/src/stm32f7/stm32_otg.h @@ -0,0 +1,148 @@ +/************************************************************************************ + * arch/arm/src/stm32f7/stm32_otg.h + * + * Copyright (C) 2012-2013, 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_STM32_OTG_H +#define __ARCH_ARM_SRC_STM32F7_STM32_OTG_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include "chip.h" +#include "chip/stm32_otg.h" + +#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_OTGHS) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Configuration ********************************************************************/ + +#ifndef CONFIG_OTG_PRI +# define CONFIG_OTG_PRI NVIC_SYSH_PRIORITY_DEFAULT +#endif + +#if defined(CONFIG_STM32F7_OTGFS) +# define STM32_IRQ_OTG STM32_IRQ_OTGFS +# define STM32_OTG_BASE STM32_USBOTGFS_BASE +# define STM32_NENDPOINTS (6) /* ep0-5 x 2 for IN and OUT */ +# define GPIO_OTG_DM GPIO_OTGFS_DM +# define GPIO_OTG_DP GPIO_OTGFS_DP +# define GPIO_OTG_ID GPIO_OTGFS_ID +# define GPIO_OTG_SOF GPIO_OTGFS_SOF +# define STM32_OTG_FIFO_SIZE 1280 +#endif + +#if defined(CONFIG_STM32F7_OTGHS) +# define STM32_IRQ_OTG STM32_IRQ_OTGHS +# define STM32_OTG_BASE STM32_USBOTGHS_BASE +# define STM32_NENDPOINTS (7) /* ep0-8 x 2 for IN and OUT but driver internals use byte to map + one bit for direction */ +# define GPIO_OTG_DM GPIO_OTGHS_DM +# define GPIO_OTG_DP GPIO_OTGHS_DP +# define GPIO_OTG_ID GPIO_OTGHS_ID +# define GPIO_OTG_SOF GPIO_OTGHS_SOF +# define STM32_OTG_FIFO_SIZE 4096 +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Name: stm32_otghost_initialize + * + * Description: + * Initialize USB host device controller hardware. + * + * Input Parameters: + * controller -- If the device supports more than USB host controller, then + * this identifies which controller is being initializeed. Normally, this + * is just zero. + * + * Returned Value: + * And instance of the USB host interface. The controlling task should + * use this interface to (1) call the wait() method to wait for a device + * to be connected, and (2) call the enumerate() method to bind the device + * to a class driver. + * + * Assumptions: + * - This function should called in the initialization sequence in order + * to initialize the USB device functionality. + * - Class drivers should be initialized prior to calling this function. + * Otherwise, there is a race condition if the device is already connected. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST +struct usbhost_connection_s; +FAR struct usbhost_connection_s *stm32_otghost_initialize(int controller); +#endif + +/************************************************************************************ + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the OTG FS device driver + * is used. This function is called whenever the USB enters or leaves suspend + * mode. This is an opportunity for the board logic to shutdown clocks, power, + * etc. while the USB is suspended. + * + ************************************************************************************/ + +void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_STM32F7_OTGFS */ +#endif /* __ARCH_ARM_SRC_STM32F7_STM32_OTG_H */ diff --git a/arch/arm/src/stm32f7/stm32_otgdev.c b/arch/arm/src/stm32f7/stm32_otgdev.c new file mode 100644 index 0000000000000000000000000000000000000000..6a776976e2d4b489654ef58215d5e1aacec8deec --- /dev/null +++ b/arch/arm/src/stm32f7/stm32_otgdev.c @@ -0,0 +1,5765 @@ +/**************************************************************************** + * arch/arm/src/stm32f7/stm32_otgdev.c + * + * Copyright (C) 2012-2014, 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_otg.h" +#include "up_arch.h" +#include "up_internal.h" + + +#if defined(CONFIG_USBDEV) && (defined(CONFIG_STM32F7_OTGFS) || \ + defined(CONFIG_STM32F7_OTGHS)) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_USBDEV_EP0_MAXSIZE +# define CONFIG_USBDEV_EP0_MAXSIZE 64 +#endif + +#ifndef CONFIG_USBDEV_SETUP_MAXDATASIZE +# define CONFIG_USBDEV_SETUP_MAXDATASIZE CONFIG_USBDEV_EP0_MAXSIZE +#endif + +#ifndef CONFIG_USBDEV_MAXPOWER +# define CONFIG_USBDEV_MAXPOWER 100 /* mA */ +#endif + +/* There is 1.25Kb of FIFO memory. The default partitions this memory + * so that there is a TxFIFO allocated for each endpoint and with more + * memory provided for the common RxFIFO. A more knowledge-able + * configuration would not allocate any TxFIFO space to OUT endpoints. + */ + +#ifndef CONFIG_USBDEV_RXFIFO_SIZE +# define CONFIG_USBDEV_RXFIFO_SIZE (STM32_OTG_FIFO_SIZE - STM32_OTG_FIFO_SIZE/4/2/STM32_NENDPOINTS*4*STM32_NENDPOINTS) +#endif + +#if STM32_NENDPOINTS > 0 +# ifndef CONFIG_USBDEV_EP0_TXFIFO_SIZE +# define CONFIG_USBDEV_EP0_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# endif +#else +# define CONFIG_USBDEV_EP0_TXFIFO_SIZE 0 +#endif + +#if STM32_NENDPOINTS > 1 +# ifndef CONFIG_USBDEV_EP1_TXFIFO_SIZE +# define CONFIG_USBDEV_EP1_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# endif +#else +# define CONFIG_USBDEV_EP1_TXFIFO_SIZE 0 +#endif + +#if STM32_NENDPOINTS > 2 +# ifndef CONFIG_USBDEV_EP2_TXFIFO_SIZE +# define CONFIG_USBDEV_EP2_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# endif +#else +# define CONFIG_USBDEV_EP2_TXFIFO_SIZE 0 +#endif + +#if STM32_NENDPOINTS > 3 +# ifndef CONFIG_USBDEV_EP3_TXFIFO_SIZE +# define CONFIG_USBDEV_EP3_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# endif +#else +# define CONFIG_USBDEV_EP3_TXFIFO_SIZE 0 +#endif + +#if STM32_NENDPOINTS > 4 +# ifndef CONFIG_USBDEV_EP4_TXFIFO_SIZE +# define CONFIG_USBDEV_EP4_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# endif +#else +# define CONFIG_USBDEV_EP4_TXFIFO_SIZE 0 +#endif + +#if STM32_NENDPOINTS > 5 +# ifndef CONFIG_USBDEV_EP5_TXFIFO_SIZE +# define CONFIG_USBDEV_EP5_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# endif +#else +# define CONFIG_USBDEV_EP5_TXFIFO_SIZE 0 +#endif + +#if STM32_NENDPOINTS > 6 +# ifndef CONFIG_USBDEV_EP6_TXFIFO_SIZE +# define CONFIG_USBDEV_EP6_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# endif +#else +# define CONFIG_USBDEV_EP6_TXFIFO_SIZE 0 +#endif + +#if STM32_NENDPOINTS > 7 +# ifndef CONFIG_USBDEV_EP7_TXFIFO_SIZE +# define CONFIG_USBDEV_EP7_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# endif +#else +# define CONFIG_USBDEV_EP7_TXFIFO_SIZE 0 +#endif + +#if STM32_NENDPOINTS > 8 +# ifndef CONFIG_USBDEV_EP8_TXFIFO_SIZE +# define CONFIG_USBDEV_EP8_TXFIFO_SIZE ((STM32_OTG_FIFO_SIZE - CONFIG_USBDEV_RXFIFO_SIZE)/STM32_NENDPOINTS) +# endif +#else +# define CONFIG_USBDEV_EP8_TXFIFO_SIZE 0 +#endif + +/* The actual FIFO addresses that we use must be aligned to 4-byte boundaries; + * FIFO sizes must be provided in units of 32-bit words. + */ + +#define STM32_RXFIFO_BYTES ((CONFIG_USBDEV_RXFIFO_SIZE + 3) & ~3) +#define STM32_RXFIFO_WORDS ((CONFIG_USBDEV_RXFIFO_SIZE + 3) >> 2) + +#define STM32_EP0_TXFIFO_BYTES ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP0_TXFIFO_WORDS ((CONFIG_USBDEV_EP0_TXFIFO_SIZE + 3) >> 2) + +#define STM32_EP1_TXFIFO_BYTES ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP1_TXFIFO_WORDS ((CONFIG_USBDEV_EP1_TXFIFO_SIZE + 3) >> 2) + +#define STM32_EP2_TXFIFO_BYTES ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP2_TXFIFO_WORDS ((CONFIG_USBDEV_EP2_TXFIFO_SIZE + 3) >> 2) + +#define STM32_EP3_TXFIFO_BYTES ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP3_TXFIFO_WORDS ((CONFIG_USBDEV_EP3_TXFIFO_SIZE + 3) >> 2) + +#define STM32_EP4_TXFIFO_BYTES ((CONFIG_USBDEV_EP4_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP4_TXFIFO_WORDS ((CONFIG_USBDEV_EP4_TXFIFO_SIZE + 3) >> 2) + +#define STM32_EP5_TXFIFO_BYTES ((CONFIG_USBDEV_EP5_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP5_TXFIFO_WORDS ((CONFIG_USBDEV_EP5_TXFIFO_SIZE + 3) >> 2) + +#define STM32_EP6_TXFIFO_BYTES ((CONFIG_USBDEV_EP6_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP6_TXFIFO_WORDS ((CONFIG_USBDEV_EP6_TXFIFO_SIZE + 3) >> 2) + +#define STM32_EP7_TXFIFO_BYTES ((CONFIG_USBDEV_EP7_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP7_TXFIFO_WORDS ((CONFIG_USBDEV_EP7_TXFIFO_SIZE + 3) >> 2) + +#define STM32_EP8_TXFIFO_BYTES ((CONFIG_USBDEV_EP8_TXFIFO_SIZE + 3) & ~3) +#define STM32_EP8_TXFIFO_WORDS ((CONFIG_USBDEV_EP8_TXFIFO_SIZE + 3) >> 2) + + +#if (STM32_RXFIFO_BYTES + \ + STM32_EP0_TXFIFO_BYTES + STM32_EP1_TXFIFO_BYTES + STM32_EP2_TXFIFO_BYTES + STM32_EP3_TXFIFO_BYTES + \ + STM32_EP4_TXFIFO_BYTES + STM32_EP5_TXFIFO_BYTES + STM32_EP6_TXFIFO_BYTES + STM32_EP7_TXFIFO_BYTES + CONFIG_USBDEV_EP8_TXFIFO_SIZE \ + ) > STM32_OTG_FIFO_SIZE +# error "FIFO allocations exceed FIFO memory size" +#endif + +/* Debug ***********************************************************************/ +/* Trace error codes */ + +#define STM32_TRACEERR_ALLOCFAIL 0x01 +#define STM32_TRACEERR_BADCLEARFEATURE 0x02 +#define STM32_TRACEERR_BADDEVGETSTATUS 0x03 +#define STM32_TRACEERR_BADEPNO 0x04 +#define STM32_TRACEERR_BADEPGETSTATUS 0x05 +#define STM32_TRACEERR_BADGETCONFIG 0x06 +#define STM32_TRACEERR_BADGETSETDESC 0x07 +#define STM32_TRACEERR_BADGETSTATUS 0x08 +#define STM32_TRACEERR_BADSETADDRESS 0x09 +#define STM32_TRACEERR_BADSETCONFIG 0x0a +#define STM32_TRACEERR_BADSETFEATURE 0x0b +#define STM32_TRACEERR_BADTESTMODE 0x0c +#define STM32_TRACEERR_BINDFAILED 0x0d +#define STM32_TRACEERR_DISPATCHSTALL 0x0e +#define STM32_TRACEERR_DRIVER 0x0f +#define STM32_TRACEERR_DRIVERREGISTERED 0x10 +#define STM32_TRACEERR_EP0NOSETUP 0x11 +#define STM32_TRACEERR_EP0SETUPSTALLED 0x12 +#define STM32_TRACEERR_EPINNULLPACKET 0x13 +#define STM32_TRACEERR_EPINUNEXPECTED 0x14 +#define STM32_TRACEERR_EPOUTNULLPACKET 0x15 +#define STM32_TRACEERR_EPOUTUNEXPECTED 0x16 +#define STM32_TRACEERR_INVALIDCTRLREQ 0x17 +#define STM32_TRACEERR_INVALIDPARMS 0x18 +#define STM32_TRACEERR_IRQREGISTRATION 0x19 +#define STM32_TRACEERR_NOEP 0x1a +#define STM32_TRACEERR_NOTCONFIGURED 0x1b +#define STM32_TRACEERR_EPOUTQEMPTY 0x1c +#define STM32_TRACEERR_EPINREQEMPTY 0x1d +#define STM32_TRACEERR_NOOUTSETUP 0x1e +#define STM32_TRACEERR_POLLTIMEOUT 0x1f + +/* Trace interrupt codes */ + +#define STM32_TRACEINTID_USB 1 /* USB Interrupt entry/exit */ +#define STM32_TRACEINTID_INTPENDING 2 /* On each pass through the loop */ + +#define STM32_TRACEINTID_EPOUT (10 + 0) /* First level interrupt decode */ +#define STM32_TRACEINTID_EPIN (10 + 1) +#define STM32_TRACEINTID_MISMATCH (10 + 2) +#define STM32_TRACEINTID_WAKEUP (10 + 3) +#define STM32_TRACEINTID_SUSPEND (10 + 4) +#define STM32_TRACEINTID_SOF (10 + 5) +#define STM32_TRACEINTID_RXFIFO (10 + 6) +#define STM32_TRACEINTID_DEVRESET (10 + 7) +#define STM32_TRACEINTID_ENUMDNE (10 + 8) +#define STM32_TRACEINTID_IISOIXFR (10 + 9) +#define STM32_TRACEINTID_IISOOXFR (10 + 10) +#define STM32_TRACEINTID_SRQ (10 + 11) +#define STM32_TRACEINTID_OTG (10 + 12) + +#define STM32_TRACEINTID_EPOUT_XFRC (40 + 0) /* EPOUT second level decode */ +#define STM32_TRACEINTID_EPOUT_EPDISD (40 + 1) +#define STM32_TRACEINTID_EPOUT_SETUP (40 + 2) +#define STM32_TRACEINTID_DISPATCH (40 + 3) + +#define STM32_TRACEINTID_GETSTATUS (50 + 0) /* EPOUT third level decode */ +#define STM32_TRACEINTID_EPGETSTATUS (50 + 1) +#define STM32_TRACEINTID_DEVGETSTATUS (50 + 2) +#define STM32_TRACEINTID_IFGETSTATUS (50 + 3) +#define STM32_TRACEINTID_CLEARFEATURE (50 + 4) +#define STM32_TRACEINTID_SETFEATURE (50 + 5) +#define STM32_TRACEINTID_SETADDRESS (50 + 6) +#define STM32_TRACEINTID_GETSETDESC (50 + 7) +#define STM32_TRACEINTID_GETCONFIG (50 + 8) +#define STM32_TRACEINTID_SETCONFIG (50 + 9) +#define STM32_TRACEINTID_GETSETIF (50 + 10) +#define STM32_TRACEINTID_SYNCHFRAME (50 + 11) + +#define STM32_TRACEINTID_EPIN_XFRC (70 + 0) /* EPIN second level decode */ +#define STM32_TRACEINTID_EPIN_TOC (70 + 1) +#define STM32_TRACEINTID_EPIN_ITTXFE (70 + 2) +#define STM32_TRACEINTID_EPIN_EPDISD (70 + 3) +#define STM32_TRACEINTID_EPIN_TXFE (70 + 4) + +#define STM32_TRACEINTID_EPIN_EMPWAIT (80 + 0) /* EPIN second level decode */ + +#define STM32_TRACEINTID_OUTNAK (90 + 0) /* RXFLVL second level decode */ +#define STM32_TRACEINTID_OUTRECVD (90 + 1) +#define STM32_TRACEINTID_OUTDONE (90 + 2) +#define STM32_TRACEINTID_SETUPDONE (90 + 3) +#define STM32_TRACEINTID_SETUPRECVD (90 + 4) + +/* Endpoints ******************************************************************/ + +/* Odd physical endpoint numbers are IN; even are OUT */ + +#define STM32_EPPHYIN2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_IN) +#define STM32_EPPHYOUT2LOG(epphy) ((uint8_t)(epphy)|USB_DIR_OUT) + +/* Endpoint 0 */ + +#define EP0 (0) + +/* The set of all enpoints available to the class implementation (1-3) */ + +#define STM32_EP_AVAILABLE (0x0e) /* All available endpoints */ + +/* Maximum packet sizes for full speed endpoints */ + +#define STM32_MAXPACKET (64) /* Max packet size (1-64) */ + +/* Delays **********************************************************************/ + +#define STM32_READY_DELAY 200000 +#define STM32_FLUSH_DELAY 200000 + +/* Request queue operations ****************************************************/ + +#define stm32_rqempty(ep) ((ep)->head == NULL) +#define stm32_rqpeek(ep) ((ep)->head) + +/* Standard stuff **************************************************************/ + +#ifndef MIN +# define MIN(a,b) ((a) < (b) ? (a) : (b)) +#endif + +#ifndef MAX +# define MAX(a,b) ((a) > (b) ? (a) : (b)) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* Overall device state */ + +enum stm32_devstate_e +{ + DEVSTATE_DEFAULT = 0, /* Power-up, unconfigured state. This state simply + * means that the device is not yet been given an + * address. + * SET: At initialization, uninitialization, + * reset, and whenever the device address + * is set to zero + * TESTED: Never + */ + DEVSTATE_ADDRESSED, /* Device address has been assigned, not no + * configuration has yet been selected. + * SET: When either a non-zero device address + * is first assigned or when the device + * is unconfigured (with configuration == 0) + * TESTED: never + */ + DEVSTATE_CONFIGURED, /* Address assigned and configured: + * SET: When the device has been addressed and + * an non-zero configuration has been selected. + * TESTED: In many places to assure that the USB device + * has been properly configured by the host. + */ +}; + +/* Endpoint 0 states */ + +enum stm32_ep0state_e +{ + EP0STATE_IDLE = 0, /* Idle State, leave on receiving a SETUP packet or + * epsubmit: + * SET: In stm32_epin() and stm32_epout() when + * we revert from request processing to + * SETUP processing. + * TESTED: Never + */ + EP0STATE_SETUP_OUT, /* OUT SETUP packet received. Waiting for the DATA + * OUT phase of SETUP Packet to complete before + * processing a SETUP command (without a USB request): + * SET: Set in stm32_rxinterrupt() when SETUP OUT + * packet is received. + * TESTED: In stm32_ep0out_receive() + */ + EP0STATE_SETUP_READY, /* IN SETUP packet received -OR- OUT SETUP packet and + * accompanying data have been received. Processing + * of SETUP command will happen soon. + * SET: (1) stm32_ep0out_receive() when the OUT + * SETUP data phase completes, or (2) + * stm32_rxinterrupt() when an IN SETUP is + * packet received. + * TESTED: Tested in stm32_epout_interrupt() when + * SETUP phase is done to see if the SETUP + * command is ready to be processed. Also + * tested in stm32_ep0out_setup() just to + * double-check that we have a SETUP request + * and any accompanying data. + */ + EP0STATE_SETUP_PROCESS, /* SETUP Packet is being processed by stm32_ep0out_setup(): + * SET: When SETUP packet received in EP0 OUT + * TESTED: Never + */ + EP0STATE_SETUPRESPONSE, /* Short SETUP response write (without a USB request): + * SET: When SETUP response is sent by + * stm32_ep0in_setupresponse() + * TESTED: Never + */ + EP0STATE_DATA_IN, /* Waiting for data out stage (with a USB request): + * SET: In stm32_epin_request() when a write + * request is processed on EP0. + * TESTED: In stm32_epin() to see if we should + * revert to SETUP processing. + */ + EP0STATE_DATA_OUT /* Waiting for data in phase to complete ( with a + * USB request) + * SET: In stm32_epout_request() when a read + * request is processed on EP0. + * TESTED: In stm32_epout() to see if we should + * revert to SETUP processing + */ +}; + +/* Parsed control request */ + +struct stm32_ctrlreq_s +{ + uint8_t type; + uint8_t req; + uint16_t value; + uint16_t index; + uint16_t len; +}; + +/* A container for a request so that the request may be retained in a list */ + +struct stm32_req_s +{ + struct usbdev_req_s req; /* Standard USB request */ + struct stm32_req_s *flink; /* Supports a singly linked list */ +}; + +/* This is the internal representation of an endpoint */ + +struct stm32_ep_s +{ + /* Common endpoint fields. This must be the first thing defined in the + * structure so that it is possible to simply cast from struct usbdev_ep_s + * to struct stm32_ep_s. + */ + + struct usbdev_ep_s ep; /* Standard endpoint structure */ + + /* STM32-specific fields */ + + struct stm32_usbdev_s *dev; /* Reference to private driver data */ + struct stm32_req_s *head; /* Request list for this endpoint */ + struct stm32_req_s *tail; + uint8_t epphy; /* Physical EP address */ + uint8_t eptype:2; /* Endpoint type */ + uint8_t active:1; /* 1: A request is being processed */ + uint8_t stalled:1; /* 1: Endpoint is stalled */ + uint8_t isin:1; /* 1: IN Endpoint */ + uint8_t odd:1; /* 1: Odd frame */ + uint8_t zlp:1; /* 1: Transmit a zero-length-packet (IN EPs only) */ +}; + +/* This structure retains the state of the USB device controller */ + +struct stm32_usbdev_s +{ + /* Common device fields. This must be the first thing defined in the + * structure so that it is possible to simply cast from struct usbdev_s + * to struct stm32_usbdev_s. + */ + + struct usbdev_s usbdev; + + /* The bound device class driver */ + + struct usbdevclass_driver_s *driver; + + /* STM32-specific fields */ + + uint8_t stalled:1; /* 1: Protocol stalled */ + uint8_t selfpowered:1; /* 1: Device is self powered */ + uint8_t addressed:1; /* 1: Peripheral address has been set */ + uint8_t configured:1; /* 1: Class driver has been configured */ + uint8_t wakeup:1; /* 1: Device remote wake-up */ + uint8_t dotest:1; /* 1: Test mode selected */ + + uint8_t devstate:4; /* See enum stm32_devstate_e */ + uint8_t ep0state:4; /* See enum stm32_ep0state_e */ + uint8_t testmode:4; /* Selected test mode */ + uint8_t epavail[2]; /* Bitset of available OUT/IN endpoints */ + + /* E0 SETUP data buffering. + * + * ctrlreq: + * The 8-byte SETUP request is received on the EP0 OUT endpoint and is + * saved. + * + * ep0data + * For OUT SETUP requests, the SETUP data phase must also complete before + * the SETUP command can be processed. The pack receipt logic will save + * the accompanying EP0 IN data in ep0data[] before the SETUP command is + * processed. + * + * For IN SETUP requests, the DATA phase will occur AFTER the SETUP + * control request is processed. In that case, ep0data[] may be used as + * the response buffer. + * + * ep0datlen + * Length of OUT DATA received in ep0data[] (Not used with OUT data) + */ + + struct usb_ctrlreq_s ctrlreq; + uint8_t ep0data[CONFIG_USBDEV_SETUP_MAXDATASIZE]; + uint16_t ep0datlen; + + /* The endpoint lists */ + + struct stm32_ep_s epin[STM32_NENDPOINTS]; + struct stm32_ep_s epout[STM32_NENDPOINTS]; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Register operations ******************************************************/ + +#if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +static uint32_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint32_t val, uint32_t addr); +#else +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(val,addr) putreg32(val,addr) +#endif + +/* Request queue operations **************************************************/ + +static FAR struct stm32_req_s *stm32_req_remfirst(FAR struct stm32_ep_s *privep); +static bool stm32_req_addlast(FAR struct stm32_ep_s *privep, + FAR struct stm32_req_s *req); + +/* Low level data transfers and request operations ***************************/ +/* Special endpoint 0 data transfer logic */ + +static void stm32_ep0in_setupresponse(FAR struct stm32_usbdev_s *priv, + FAR uint8_t *data, uint32_t nbytes); +static inline void stm32_ep0in_transmitzlp(FAR struct stm32_usbdev_s *priv); +static void stm32_ep0in_activate(void); + +static void stm32_ep0out_ctrlsetup(FAR struct stm32_usbdev_s *priv); + +/* IN request and TxFIFO handling */ + +static void stm32_txfifo_write(FAR struct stm32_ep_s *privep, + FAR uint8_t *buf, int nbytes); +static void stm32_epin_transfer(FAR struct stm32_ep_s *privep, + FAR uint8_t *buf, int nbytes); +static void stm32_epin_request(FAR struct stm32_usbdev_s *priv, + FAR struct stm32_ep_s *privep); + +/* OUT request and RxFIFO handling */ + +static void stm32_rxfifo_read(FAR struct stm32_ep_s *privep, + FAR uint8_t *dest, uint16_t len); +static void stm32_rxfifo_discard(FAR struct stm32_ep_s *privep, int len); +static void stm32_epout_complete(FAR struct stm32_usbdev_s *priv, + FAR struct stm32_ep_s *privep); +static inline void stm32_ep0out_receive(FAR struct stm32_ep_s *privep, int bcnt); +static inline void stm32_epout_receive(FAR struct stm32_ep_s *privep, int bcnt); +static void stm32_epout_request(FAR struct stm32_usbdev_s *priv, + FAR struct stm32_ep_s *privep); + +/* General request handling */ + +static void stm32_ep_flush(FAR struct stm32_ep_s *privep); +static void stm32_req_complete(FAR struct stm32_ep_s *privep, + int16_t result); +static void stm32_req_cancel(FAR struct stm32_ep_s *privep, + int16_t status); + +/* Interrupt handling ********************************************************/ + +static struct stm32_ep_s *stm32_ep_findbyaddr(struct stm32_usbdev_s *priv, + uint16_t eplog); +static int stm32_req_dispatch(FAR struct stm32_usbdev_s *priv, + FAR const struct usb_ctrlreq_s *ctrl); +static void stm32_usbreset(FAR struct stm32_usbdev_s *priv); + +/* Second level OUT endpoint interrupt processing */ + +static inline void stm32_ep0out_testmode(FAR struct stm32_usbdev_s *priv, + uint16_t index); +static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, + FAR struct stm32_ctrlreq_s *ctrlreq); +static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv); +static inline void stm32_epout(FAR struct stm32_usbdev_s *priv, + uint8_t epno); +static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv); + +/* Second level IN endpoint interrupt processing */ + +static inline void stm32_epin_runtestmode(FAR struct stm32_usbdev_s *priv); +static inline void stm32_epin(FAR struct stm32_usbdev_s *priv, uint8_t epno); +static inline void stm32_epin_txfifoempty(FAR struct stm32_usbdev_s *priv, + int epno); +static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv); + +/* Other second level interrupt processing */ + +static inline void stm32_resumeinterrupt(FAR struct stm32_usbdev_s *priv); +static inline void stm32_suspendinterrupt(FAR struct stm32_usbdev_s *priv); +static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv); +static inline void stm32_enuminterrupt(FAR struct stm32_usbdev_s *priv); +#ifdef CONFIG_USBDEV_ISOCHRONOUS +static inline void stm32_isocininterrupt(FAR struct stm32_usbdev_s *priv); +static inline void stm32_isocoutinterrupt(FAR struct stm32_usbdev_s *priv); +#endif +#ifdef CONFIG_USBDEV_VBUSSENSING +static inline void stm32_sessioninterrupt(FAR struct stm32_usbdev_s *priv); +static inline void stm32_otginterrupt(FAR struct stm32_usbdev_s *priv); +#endif + +/* First level interrupt processing */ + +static int stm32_usbinterrupt(int irq, FAR void *context); + +/* Endpoint operations *********************************************************/ +/* Global OUT NAK controls */ + +static void stm32_enablegonak(FAR struct stm32_ep_s *privep); +static void stm32_disablegonak(FAR struct stm32_ep_s *privep); + +/* Endpoint configuration */ + +static int stm32_epout_configure(FAR struct stm32_ep_s *privep, + uint8_t eptype, uint16_t maxpacket); +static int stm32_epin_configure(FAR struct stm32_ep_s *privep, + uint8_t eptype, uint16_t maxpacket); +static int stm32_ep_configure(FAR struct usbdev_ep_s *ep, + FAR const struct usb_epdesc_s *desc, bool last); +static void stm32_ep0_configure(FAR struct stm32_usbdev_s *priv); + +/* Endpoint disable */ + +static void stm32_epout_disable(FAR struct stm32_ep_s *privep); +static void stm32_epin_disable(FAR struct stm32_ep_s *privep); +static int stm32_ep_disable(FAR struct usbdev_ep_s *ep); + +/* Endpoint request management */ + +static FAR struct usbdev_req_s *stm32_ep_allocreq(FAR struct usbdev_ep_s *ep); +static void stm32_ep_freereq(FAR struct usbdev_ep_s *ep, + FAR struct usbdev_req_s *); + +/* Endpoint buffer management */ + +#ifdef CONFIG_USBDEV_DMA +static void *stm32_ep_allocbuffer(FAR struct usbdev_ep_s *ep, + unsigned bytes); +static void stm32_ep_freebuffer(FAR struct usbdev_ep_s *ep, + FAR void *buf); +#endif + +/* Endpoint request submission */ + +static int stm32_ep_submit(FAR struct usbdev_ep_s *ep, + struct usbdev_req_s *req); + +/* Endpoint request cancellation */ + +static int stm32_ep_cancel(FAR struct usbdev_ep_s *ep, + struct usbdev_req_s *req); + +/* Stall handling */ + +static int stm32_epout_setstall(FAR struct stm32_ep_s *privep); +static int stm32_epin_setstall(FAR struct stm32_ep_s *privep); +static int stm32_ep_setstall(FAR struct stm32_ep_s *privep); +static int stm32_ep_clrstall(FAR struct stm32_ep_s *privep); +static int stm32_ep_stall(FAR struct usbdev_ep_s *ep, bool resume); +static void stm32_ep0_stall(FAR struct stm32_usbdev_s *priv); + +/* Endpoint allocation */ + +static FAR struct usbdev_ep_s *stm32_ep_alloc(FAR struct usbdev_s *dev, + uint8_t epno, bool in, uint8_t eptype); +static void stm32_ep_free(FAR struct usbdev_s *dev, + FAR struct usbdev_ep_s *ep); + +/* USB device controller operations ********************************************/ + +static int stm32_getframe(struct usbdev_s *dev); +static int stm32_wakeup(struct usbdev_s *dev); +static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered); +static int stm32_pullup(struct usbdev_s *dev, bool enable); +static void stm32_setaddress(struct stm32_usbdev_s *priv, + uint16_t address); +static int stm32_txfifo_flush(uint32_t txfnum); +static int stm32_rxfifo_flush(void); + +/* Initialization **************************************************************/ + +static void stm32_swinitialize(FAR struct stm32_usbdev_s *priv); +static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Since there is only a single USB interface, all status information can be + * be simply retained in a single global instance. + */ + +static struct stm32_usbdev_s g_otghsdev; + +static const struct usbdev_epops_s g_epops = +{ + .configure = stm32_ep_configure, + .disable = stm32_ep_disable, + .allocreq = stm32_ep_allocreq, + .freereq = stm32_ep_freereq, +#ifdef CONFIG_USBDEV_DMA + .allocbuffer = stm32_ep_allocbuffer, + .freebuffer = stm32_ep_freebuffer, +#endif + .submit = stm32_ep_submit, + .cancel = stm32_ep_cancel, + .stall = stm32_ep_stall, +}; + +static const struct usbdev_ops_s g_devops = +{ + .allocep = stm32_ep_alloc, + .freeep = stm32_ep_free, + .getframe = stm32_getframe, + .wakeup = stm32_wakeup, + .selfpowered = stm32_selfpowered, + .pullup = stm32_pullup, +}; + +/* Device error strings that may be enabled for more descriptive USB trace + * output. + */ + +#ifdef CONFIG_USBDEV_TRACE_STRINGS +const struct trace_msg_t g_usb_trace_strings_deverror[] = +{ + TRACE_STR(STM32_TRACEERR_ALLOCFAIL ), + TRACE_STR(STM32_TRACEERR_BADCLEARFEATURE ), + TRACE_STR(STM32_TRACEERR_BADDEVGETSTATUS ), + TRACE_STR(STM32_TRACEERR_BADEPNO ), + TRACE_STR(STM32_TRACEERR_BADEPGETSTATUS ), + TRACE_STR(STM32_TRACEERR_BADGETCONFIG ), + TRACE_STR(STM32_TRACEERR_BADGETSETDESC ), + TRACE_STR(STM32_TRACEERR_BADGETSTATUS ), + TRACE_STR(STM32_TRACEERR_BADSETADDRESS ), + TRACE_STR(STM32_TRACEERR_BADSETCONFIG ), + TRACE_STR(STM32_TRACEERR_BADSETFEATURE ), + TRACE_STR(STM32_TRACEERR_BADTESTMODE ), + TRACE_STR(STM32_TRACEERR_BINDFAILED ), + TRACE_STR(STM32_TRACEERR_DISPATCHSTALL ), + TRACE_STR(STM32_TRACEERR_DRIVER ), + TRACE_STR(STM32_TRACEERR_DRIVERREGISTERED), + TRACE_STR(STM32_TRACEERR_EP0NOSETUP ), + TRACE_STR(STM32_TRACEERR_EP0SETUPSTALLED ), + TRACE_STR(STM32_TRACEERR_EPINNULLPACKET ), + TRACE_STR(STM32_TRACEERR_EPINUNEXPECTED ), + TRACE_STR(STM32_TRACEERR_EPOUTNULLPACKET ), + TRACE_STR(STM32_TRACEERR_EPOUTUNEXPECTED ), + TRACE_STR(STM32_TRACEERR_INVALIDCTRLREQ ), + TRACE_STR(STM32_TRACEERR_INVALIDPARMS ), + TRACE_STR(STM32_TRACEERR_IRQREGISTRATION ), + TRACE_STR(STM32_TRACEERR_NOEP ), + TRACE_STR(STM32_TRACEERR_NOTCONFIGURED ), + TRACE_STR(STM32_TRACEERR_EPOUTQEMPTY ), + TRACE_STR(STM32_TRACEERR_EPINREQEMPTY ), + TRACE_STR(STM32_TRACEERR_NOOUTSETUP ), + TRACE_STR(STM32_TRACEERR_POLLTIMEOUT ), + TRACE_STR_END +}; +#endif + +/* Interrupt event strings that may be enabled for more descriptive USB trace + * output. + */ + +#ifdef CONFIG_USBDEV_TRACE_STRINGS +const struct trace_msg_t g_usb_trace_strings_intdecode[] = +{ + TRACE_STR(STM32_TRACEINTID_USB ), + TRACE_STR(STM32_TRACEINTID_INTPENDING ), + TRACE_STR(STM32_TRACEINTID_EPOUT ), + TRACE_STR(STM32_TRACEINTID_EPIN ), + TRACE_STR(STM32_TRACEINTID_MISMATCH ), + TRACE_STR(STM32_TRACEINTID_WAKEUP ), + TRACE_STR(STM32_TRACEINTID_SUSPEND ), + TRACE_STR(STM32_TRACEINTID_SOF ), + TRACE_STR(STM32_TRACEINTID_RXFIFO ), + TRACE_STR(STM32_TRACEINTID_DEVRESET ), + TRACE_STR(STM32_TRACEINTID_ENUMDNE ), + TRACE_STR(STM32_TRACEINTID_IISOIXFR ), + TRACE_STR(STM32_TRACEINTID_IISOOXFR ), + TRACE_STR(STM32_TRACEINTID_SRQ ), + TRACE_STR(STM32_TRACEINTID_OTG ), + TRACE_STR(STM32_TRACEINTID_EPOUT_XFRC ), + TRACE_STR(STM32_TRACEINTID_EPOUT_EPDISD), + TRACE_STR(STM32_TRACEINTID_EPOUT_SETUP ), + TRACE_STR(STM32_TRACEINTID_DISPATCH ), + TRACE_STR(STM32_TRACEINTID_GETSTATUS ), + TRACE_STR(STM32_TRACEINTID_EPGETSTATUS ), + TRACE_STR(STM32_TRACEINTID_DEVGETSTATUS), + TRACE_STR(STM32_TRACEINTID_IFGETSTATUS ), + TRACE_STR(STM32_TRACEINTID_CLEARFEATURE), + TRACE_STR(STM32_TRACEINTID_SETFEATURE ), + TRACE_STR(STM32_TRACEINTID_SETADDRESS ), + TRACE_STR(STM32_TRACEINTID_GETSETDESC ), + TRACE_STR(STM32_TRACEINTID_GETCONFIG ), + TRACE_STR(STM32_TRACEINTID_SETCONFIG ), + TRACE_STR(STM32_TRACEINTID_GETSETIF ), + TRACE_STR(STM32_TRACEINTID_SYNCHFRAME ), + TRACE_STR(STM32_TRACEINTID_EPIN_XFRC ), + TRACE_STR(STM32_TRACEINTID_EPIN_TOC ), + TRACE_STR(STM32_TRACEINTID_EPIN_ITTXFE ), + TRACE_STR(STM32_TRACEINTID_EPIN_EPDISD ), + TRACE_STR(STM32_TRACEINTID_EPIN_TXFE ), + TRACE_STR(STM32_TRACEINTID_EPIN_EMPWAIT), + TRACE_STR(STM32_TRACEINTID_OUTNAK ), + TRACE_STR(STM32_TRACEINTID_OUTRECVD ), + TRACE_STR(STM32_TRACEINTID_OUTDONE ), + TRACE_STR(STM32_TRACEINTID_SETUPDONE ), + TRACE_STR(STM32_TRACEINTID_SETUPRECVD ), + TRACE_STR_END +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_getreg + * + * Description: + * Get the contents of an STM32 register + * + ****************************************************************************/ + +#if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +static uint32_t stm32_getreg(uint32_t addr) +{ + static uint32_t prevaddr = 0; + static uint32_t preval = 0; + static uint32_t count = 0; + + /* Read the value from the register */ + + uint32_t val = getreg32(addr); + + /* Is this the same value that we read from the same register last time? Are + * we polling the register? If so, suppress some of the output. + */ + + if (addr == prevaddr && val == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + llerr("...\n"); + } + + return val; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + llerr("[repeats %d more times]\n", count-3); + } + + /* Save the new address, value, and count */ + + prevaddr = addr; + preval = val; + count = 1; + } + + /* Show the register value read */ + + llerr("%08x->%08x\n", addr, val); + return val; +} +#endif + +/**************************************************************************** + * Name: stm32_putreg + * + * Description: + * Set the contents of an STM32 register to a value + * + ****************************************************************************/ + +#if defined(CONFIG_STM32F7_USBDEV_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +static void stm32_putreg(uint32_t val, uint32_t addr) +{ + /* Show the register value being written */ + + llerr("%08x<-%08x\n", addr, val); + + /* Write the value */ + + putreg32(val, addr); +} +#endif + +/**************************************************************************** + * Name: stm32_req_remfirst + * + * Description: + * Remove a request from the head of an endpoint request queue + * + ****************************************************************************/ + +static FAR struct stm32_req_s *stm32_req_remfirst(FAR struct stm32_ep_s *privep) +{ + FAR struct stm32_req_s *ret = privep->head; + + if (ret) + { + privep->head = ret->flink; + if (!privep->head) + { + privep->tail = NULL; + } + + ret->flink = NULL; + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_req_addlast + * + * Description: + * Add a request to the end of an endpoint request queue + * + ****************************************************************************/ + +static bool stm32_req_addlast(FAR struct stm32_ep_s *privep, + FAR struct stm32_req_s *req) +{ + bool is_empty = !privep->head; + + req->flink = NULL; + if (is_empty) + { + privep->head = req; + privep->tail = req; + } + else + { + privep->tail->flink = req; + privep->tail = req; + } + + return is_empty; +} + +/**************************************************************************** + * Name: stm32_ep0in_setupresponse + * + * Description: + * Schedule a short transfer on Endpoint 0 (IN or OUT) + * + ****************************************************************************/ + +static void stm32_ep0in_setupresponse(FAR struct stm32_usbdev_s *priv, + FAR uint8_t *buf, uint32_t nbytes) +{ + stm32_epin_transfer(&priv->epin[EP0], buf, nbytes); + priv->ep0state = EP0STATE_SETUPRESPONSE; + stm32_ep0out_ctrlsetup(priv); +} + +/**************************************************************************** + * Name: stm32_ep0in_transmitzlp + * + * Description: + * Send a zero length packet (ZLP) on endpoint 0 IN + * + ****************************************************************************/ + +static inline void stm32_ep0in_transmitzlp(FAR struct stm32_usbdev_s *priv) +{ + stm32_ep0in_setupresponse(priv, NULL, 0); +} + +/**************************************************************************** + * Name: stm32_ep0in_activate + * + * Description: + * Activate the endpoint 0 IN endpoint. + * + ****************************************************************************/ + +static void stm32_ep0in_activate(void) +{ + uint32_t regval; + + /* Set the max packet size of the IN EP. */ + + regval = stm32_getreg(STM32_OTG_DIEPCTL(0)); + regval &= ~OTG_DIEPCTL0_MPSIZ_MASK; + +#if CONFIG_USBDEV_EP0_MAXSIZE == 8 + regval |= OTG_DIEPCTL0_MPSIZ_8; +#elif CONFIG_USBDEV_EP0_MAXSIZE == 16 + regval |= OTG_DIEPCTL0_MPSIZ_16; +#elif CONFIG_USBDEV_EP0_MAXSIZE == 32 + regval |= OTG_DIEPCTL0_MPSIZ_32; +#elif CONFIG_USBDEV_EP0_MAXSIZE == 64 + regval |= OTG_DIEPCTL0_MPSIZ_64; +#else +# error "Unsupported value of CONFIG_USBDEV_EP0_MAXSIZE" +#endif + + stm32_putreg(regval, STM32_OTG_DIEPCTL(0)); + + /* Clear global IN NAK */ + + regval = stm32_getreg(STM32_OTG_DCTL); + regval |= OTG_DCTL_CGINAK; + stm32_putreg(regval, STM32_OTG_DCTL); +} + +/**************************************************************************** + * Name: stm32_ep0out_ctrlsetup + * + * Description: + * Setup to receive a SETUP packet. + * + ****************************************************************************/ + +static void stm32_ep0out_ctrlsetup(FAR struct stm32_usbdev_s *priv) +{ + uint32_t regval; + + /* Setup the hardware to perform the SETUP transfer */ + + regval = (USB_SIZEOF_CTRLREQ * 3 << OTG_DOEPTSIZ0_XFRSIZ_SHIFT) | + (OTG_DOEPTSIZ0_PKTCNT) | + (3 << OTG_DOEPTSIZ0_STUPCNT_SHIFT); + stm32_putreg(regval, STM32_OTG_DOEPTSIZ(0)); + + /* Then clear NAKing and enable the transfer */ + + regval = stm32_getreg(STM32_OTG_DOEPCTL(0)); + regval |= (OTG_DOEPCTL0_CNAK | OTG_DOEPCTL0_EPENA); + stm32_putreg(regval, STM32_OTG_DOEPCTL(0)); +} + +/**************************************************************************** + * Name: stm32_txfifo_write + * + * Description: + * Send data to the endpoint's TxFIFO. + * + ****************************************************************************/ + +static void stm32_txfifo_write(FAR struct stm32_ep_s *privep, + FAR uint8_t *buf, int nbytes) +{ + uint32_t regaddr; + uint32_t regval; + int nwords; + int i; + + /* Convert the number of bytes to words */ + + nwords = (nbytes + 3) >> 2; + + /* Get the TxFIFO for this endpoint (same as the endpoint number) */ + + regaddr = STM32_OTG_DFIFO_DEP(privep->epphy); + + /* Then transfer each word to the TxFIFO */ + + for (i = 0; i < nwords; i++) + { + /* Read four bytes from the source buffer (to avoid unaligned accesses) + * and pack these into one 32-bit word (little endian). + */ + + regval = (uint32_t)*buf++; + regval |= ((uint32_t)*buf++) << 8; + regval |= ((uint32_t)*buf++) << 16; + regval |= ((uint32_t)*buf++) << 24; + + /* Then write the packet data to the TxFIFO */ + + stm32_putreg(regval, regaddr); + } +} + +/**************************************************************************** + * Name: stm32_epin_transfer + * + * Description: + * Start the Tx data transfer + * + ****************************************************************************/ + +static void stm32_epin_transfer(FAR struct stm32_ep_s *privep, + FAR uint8_t *buf, int nbytes) +{ + uint32_t pktcnt; + uint32_t regval; + + /* Read the DIEPSIZx register */ + + regval = stm32_getreg(STM32_OTG_DIEPTSIZ(privep->epphy)); + + /* Clear the XFRSIZ, PKTCNT, and MCNT field of the DIEPSIZx register */ + + regval &= ~(OTG_DIEPTSIZ_XFRSIZ_MASK | OTG_DIEPTSIZ_PKTCNT_MASK | + OTG_DIEPTSIZ_MCNT_MASK); + + /* Are we sending a zero length packet (ZLP) */ + + if (nbytes == 0) + { + /* Yes.. leave the transfer size at zero and set the packet count to 1 */ + + pktcnt = 1; + } + else + { + /* No.. Program the transfer size and packet count . First calculate: + * + * xfrsize = The total number of bytes to be sent. + * pktcnt = the number of packets (of maxpacket bytes) required to + * perform the transfer. + */ + + pktcnt = ((uint32_t)nbytes + (privep->ep.maxpacket - 1)) / privep->ep.maxpacket; + } + + /* Set the XFRSIZ and PKTCNT */ + + regval |= (pktcnt << OTG_DIEPTSIZ_PKTCNT_SHIFT); + regval |= ((uint32_t)nbytes << OTG_DIEPTSIZ_XFRSIZ_SHIFT); + + /* If this is an isochronous endpoint, then set the multi-count field to + * the PKTCNT as well. + */ + + if (privep->eptype == USB_EP_ATTR_XFER_ISOC) + { + regval |= (pktcnt << OTG_DIEPTSIZ_MCNT_SHIFT); + } + + /* Save DIEPSIZx register value */ + + stm32_putreg(regval, STM32_OTG_DIEPTSIZ(privep->epphy)); + + /* Read the DIEPCTLx register */ + + regval = stm32_getreg(STM32_OTG_DIEPCTL(privep->epphy)); + + /* If this is an isochronous endpoint, then set the even/odd frame bit + * the DIEPCTLx register. + */ + + if (privep->eptype == USB_EP_ATTR_XFER_ISOC) + { + /* Check bit 0 of the frame number of the received SOF and set the + * even/odd frame to match. + */ + + uint32_t status = stm32_getreg(STM32_OTG_DSTS); + if ((status & OTG_DSTS_SOFFN0) == OTG_DSTS_SOFFN_EVEN) + { + regval |= OTG_DIEPCTL_SEVNFRM; + } + else + { + regval |= OTG_DIEPCTL_SODDFRM; + } + } + + /* EP enable, IN data in FIFO */ + + regval &= ~OTG_DIEPCTL_EPDIS; + regval |= (OTG_DIEPCTL_CNAK | OTG_DIEPCTL_EPENA); + stm32_putreg(regval, STM32_OTG_DIEPCTL(privep->epphy)); + + /* Transfer the data to the TxFIFO. At this point, the caller has already + * assured that there is sufficient space in the TxFIFO to hold the transfer + * we can just blindly continue. + */ + + stm32_txfifo_write(privep, buf, nbytes); +} + +/**************************************************************************** + * Name: stm32_epin_request + * + * Description: + * Begin or continue write request processing. + * + ****************************************************************************/ + +static void stm32_epin_request(FAR struct stm32_usbdev_s *priv, + FAR struct stm32_ep_s *privep) +{ + struct stm32_req_s *privreq; + uint32_t regaddr; + uint32_t regval; + uint8_t *buf; + int nbytes; + int nwords; + int bytesleft; + + /* We get here in one of four possible ways. From three interrupting + * events: + * + * 1. From stm32_epin as part of the transfer complete interrupt processing + * This interrupt indicates that the last transfer has completed. + * 2. As part of the ITTXFE interrupt processing. That interrupt indicates + * that an IN token was received when the associated TxFIFO was empty. + * 3. From stm32_epin_txfifoempty as part of the TXFE interrupt processing. + * The TXFE interrupt is only enabled when the TxFIFO is full and the + * software must wait for space to become available in the TxFIFO. + * + * And this function may be called immediately when the write request is + * queue to start up the next transaction. + * + * 4. From stm32_ep_submit when a new write request is received WHILE the + * endpoint is not active (privep->active == false). + */ + + /* Check the request from the head of the endpoint request queue */ + + privreq = stm32_rqpeek(privep); + if (!privreq) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINREQEMPTY), privep->epphy); + + /* There is no TX transfer in progress and no new pending TX + * requests to send. To stop transmitting any data on a particular + * IN endpoint, the application must set the IN NAK bit. To set this + * bit, the following field must be programmed. + */ + + regaddr = STM32_OTG_DIEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + regval |= OTG_DIEPCTL_SNAK; + stm32_putreg(regval, regaddr); + + /* The endpoint is no longer active */ + + privep->active = false; + return; + } + + uinfo("EP%d req=%p: len=%d xfrd=%d zlp=%d\n", + privep->epphy, privreq, privreq->req.len, + privreq->req.xfrd, privep->zlp); + + /* Check for a special case: If we are just starting a request (xfrd==0) and + * the class driver is trying to send a zero-length packet (len==0). Then set + * the ZLP flag so that the packet will be sent. + */ + + if (privreq->req.len == 0) + { + /* The ZLP flag is set TRUE whenever we want to force the driver to + * send a zero-length-packet on the next pass through the loop (below). + * The flag is cleared whenever a packet is sent in the loop below. + */ + + privep->zlp = true; + } + + /* Add one more packet to the TxFIFO. We will wait for the transfer + * complete event before we add the next packet (or part of a packet + * to the TxFIFO). + * + * The documentation says that we can can multiple packets to the TxFIFO, + * but it seems that we need to get the transfer complete event before + * we can add the next (or maybe I have got something wrong?) + */ + +#if 0 + while (privreq->req.xfrd < privreq->req.len || privep->zlp) +#else + if (privreq->req.xfrd < privreq->req.len || privep->zlp) +#endif + { + /* Get the number of bytes left to be sent in the request */ + + bytesleft = privreq->req.len - privreq->req.xfrd; + nbytes = bytesleft; + + /* Assume no zero-length-packet on the next pass through this loop */ + + privep->zlp = false; + + /* Limit the size of the transfer to one full packet and handle + * zero-length packets (ZLPs). + */ + + if (nbytes > 0) + { + /* Either send the maxpacketsize or all of the remaining data in + * the request. + */ + + if (nbytes >= privep->ep.maxpacket) + { + nbytes = privep->ep.maxpacket; + + /* Handle the case where this packet is exactly the + * maxpacketsize. Do we need to send a zero-length packet + * in this case? + */ + + if (bytesleft == privep->ep.maxpacket && + (privreq->req.flags & USBDEV_REQFLAGS_NULLPKT) != 0) + { + /* The ZLP flag is set TRUE whenever we want to force + * the driver to send a zero-length-packet on the next + * pass through this loop. The flag is cleared (above) + * whenever we are committed to sending any packet and + * set here when we want to force one more pass through + * the loop. + */ + + privep->zlp = true; + } + } + } + + /* Get the transfer size in 32-bit words */ + + nwords = (nbytes + 3) >> 2; + + /* Get the number of 32-bit words available in the TxFIFO. The + * DXTFSTS indicates the amount of free space available in the + * endpoint TxFIFO. Values are in terms of 32-bit words: + * + * 0: Endpoint TxFIFO is full + * 1: 1 word available + * 2: 2 words available + * n: n words available + */ + + regaddr = STM32_OTG_DTXFSTS(privep->epphy); + + /* Check for space in the TxFIFO. If space in the TxFIFO is not + * available, then set up an interrupt to resume the transfer when + * the TxFIFO is empty. + */ + + regval = stm32_getreg(regaddr); + if ((int)(regval & OTG_DTXFSTS_MASK) < nwords) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EMPWAIT), (uint16_t)regval); + + /* There is insufficient space in the TxFIFO. Wait for a TxFIFO + * empty interrupt and try again. + */ + + uint32_t empmsk = stm32_getreg(STM32_OTG_DIEPEMPMSK); + empmsk |= OTG_DIEPEMPMSK(privep->epphy); + stm32_putreg(empmsk, STM32_OTG_DIEPEMPMSK); + + /* Terminate the transfer. We will try again when the TxFIFO empty + * interrupt is received. + */ + + return; + } + + /* Transfer data to the TxFIFO */ + + buf = privreq->req.buf + privreq->req.xfrd; + stm32_epin_transfer(privep, buf, nbytes); + + /* If it was not before, the OUT endpoint is now actively transferring + * data. + */ + + privep->active = true; + + /* EP0 is a special case */ + + if (privep->epphy == EP0) + { + priv->ep0state = EP0STATE_DATA_IN; + } + + /* Update for the next time through the loop */ + + privreq->req.xfrd += nbytes; + } + + /* Note that the ZLP, if any, must be sent as a separate transfer. The need + * for a ZLP is indicated by privep->zlp. If all of the bytes were sent + * (including any final null packet) then we are finished with the transfer + */ + + if (privreq->req.xfrd >= privreq->req.len && !privep->zlp) + { + usbtrace(TRACE_COMPLETE(privep->epphy), privreq->req.xfrd); + + /* We are finished with the request (although the transfer has not + * yet completed). + */ + + stm32_req_complete(privep, OK); + } +} + +/**************************************************************************** + * Name: stm32_rxfifo_read + * + * Description: + * Read packet from the RxFIFO into a read request. + * + ****************************************************************************/ + +static void stm32_rxfifo_read(FAR struct stm32_ep_s *privep, + FAR uint8_t *dest, uint16_t len) +{ + uint32_t regaddr; + int i; + + /* Get the address of the RxFIFO. Note: there is only one RxFIFO so + * we might as well use the address associated with EP0. + */ + + regaddr = STM32_OTG_DFIFO_DEP(EP0); + + /* Read 32-bits and write 4 x 8-bits at time (to avoid unaligned accesses) */ + + for (i = 0; i < len; i += 4) + { + union + { + uint32_t w; + uint8_t b[4]; + } data; + + /* Read 1 x 32-bits of EP0 packet data */ + + data.w = stm32_getreg(regaddr); + + /* Write 4 x 8-bits of EP0 packet data */ + + *dest++ = data.b[0]; + *dest++ = data.b[1]; + *dest++ = data.b[2]; + *dest++ = data.b[3]; + } +} + +/**************************************************************************** + * Name: stm32_rxfifo_discard + * + * Description: + * Discard packet data from the RxFIFO. + * + ****************************************************************************/ + +static void stm32_rxfifo_discard(FAR struct stm32_ep_s *privep, int len) +{ + if (len > 0) + { + uint32_t regaddr; + int i; + + /* Get the address of the RxFIFO Note: there is only one RxFIFO so + * we might as well use the address associated with EP0. + */ + + regaddr = STM32_OTG_DFIFO_DEP(EP0); + + /* Read 32-bits at time */ + + for (i = 0; i < len; i += 4) + { + volatile uint32_t data = stm32_getreg(regaddr); + (void)data; + } + } +} + +/**************************************************************************** + * Name: stm32_epout_complete + * + * Description: + * This function is called when an OUT transfer complete interrupt is + * received. It completes the read request at the head of the endpoint's + * request queue. + * + ****************************************************************************/ + +static void stm32_epout_complete(FAR struct stm32_usbdev_s *priv, + FAR struct stm32_ep_s *privep) +{ + struct stm32_req_s *privreq; + + /* Since a transfer just completed, there must be a read request at the head of + * the endpoint request queue. + */ + + privreq = stm32_rqpeek(privep); + DEBUGASSERT(privreq); + + if (!privreq) + { + /* An OUT transfer completed, but no packet to receive the data. This + * should not happen. + */ + + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), privep->epphy); + privep->active = false; + return; + } + + uinfo("EP%d: len=%d xfrd=%d\n", + privep->epphy, privreq->req.len, privreq->req.xfrd); + + /* Return the completed read request to the class driver and mark the state + * IDLE. + */ + + usbtrace(TRACE_COMPLETE(privep->epphy), privreq->req.xfrd); + stm32_req_complete(privep, OK); + privep->active = false; + + /* Now set up the next read request (if any) */ + + stm32_epout_request(priv, privep); +} + +/**************************************************************************** + * Name: stm32_ep0out_receive + * + * Description: + * This function is called from the RXFLVL interrupt handler when new incoming + * data is available in the endpoint's RxFIFO. This function will simply + * copy the incoming data into pending request's data buffer. + * + ****************************************************************************/ + +static inline void stm32_ep0out_receive(FAR struct stm32_ep_s *privep, int bcnt) +{ + FAR struct stm32_usbdev_s *priv; + + /* Sanity Checking */ + + DEBUGASSERT(privep && privep->ep.priv); + priv = (FAR struct stm32_usbdev_s *)privep->ep.priv; + + uinfo("EP0: bcnt=%d\n", bcnt); + usbtrace(TRACE_READ(EP0), bcnt); + + /* Verify that an OUT SETUP request as received before this data was + * received in the RxFIFO. + */ + + if (priv->ep0state == EP0STATE_SETUP_OUT) + { + /* Read the data into our special buffer for SETUP data */ + + int readlen = MIN(CONFIG_USBDEV_SETUP_MAXDATASIZE, bcnt); + stm32_rxfifo_read(privep, priv->ep0data, readlen); + + /* Do we have to discard any excess bytes? */ + + stm32_rxfifo_discard(privep, bcnt - readlen); + + /* Now we can process the setup command */ + + privep->active = false; + priv->ep0state = EP0STATE_SETUP_READY; + priv->ep0datlen = readlen; + + stm32_ep0out_setup(priv); + } + else + { + /* This is an error. We don't have any idea what to do with the EP0 + * data in this case. Just read and discard it so that the RxFIFO + * does not become constipated. + */ + + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOOUTSETUP), priv->ep0state); + stm32_rxfifo_discard(privep, bcnt); + privep->active = false; + } +} + +/**************************************************************************** + * Name: stm32_epout_receive + * + * Description: + * This function is called from the RXFLVL interrupt handler when new incoming + * data is available in the endpoint's RxFIFO. This function will simply + * copy the incoming data into pending request's data buffer. + * + ****************************************************************************/ + +static inline void stm32_epout_receive(FAR struct stm32_ep_s *privep, int bcnt) +{ + struct stm32_req_s *privreq; + uint8_t *dest; + int buflen; + int readlen; + + /* Get a reference to the request at the head of the endpoint's request + * queue. + */ + + privreq = stm32_rqpeek(privep); + if (!privreq) + { + /* Incoming data is available in the RxFIFO, but there is no read setup + * to receive the receive the data. This should not happen for data + * endpoints; those endpoints should have been NAKing any OUT data tokens. + * + * We should get here normally on OUT data phase following an OUT + * SETUP command. EP0 data will still receive data in this case and it + * should not be NAKing. + */ + + if (privep->epphy == 0) + { + stm32_ep0out_receive(privep, bcnt); + } + else + { + /* Otherwise, the data is lost. This really should not happen if + * NAKing is working as expected. + */ + + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), privep->epphy); + + /* Discard the data in the RxFIFO */ + + stm32_rxfifo_discard(privep, bcnt); + } + + privep->active = false; + return; + } + + uinfo("EP%d: len=%d xfrd=%d\n", privep->epphy, privreq->req.len, privreq->req.xfrd); + usbtrace(TRACE_READ(privep->epphy), bcnt); + + /* Get the number of bytes to transfer from the RxFIFO */ + + buflen = privreq->req.len - privreq->req.xfrd; + DEBUGASSERT(buflen > 0 && buflen >= bcnt); + readlen = MIN(buflen, bcnt); + + /* Get the destination of the data transfer */ + + dest = privreq->req.buf + privreq->req.xfrd; + + /* Transfer the data from the RxFIFO to the request's data buffer */ + + stm32_rxfifo_read(privep, dest, readlen); + + /* If there were more bytes in the RxFIFO than could be held in the read + * request, then we will have to discard those. + */ + + stm32_rxfifo_discard(privep, bcnt - readlen); + + /* Update the number of bytes transferred */ + + privreq->req.xfrd += readlen; +} + +/**************************************************************************** + * Name: stm32_epout_request + * + * Description: + * This function is called when either (1) new read request is received, or + * (2) a pending receive request completes. If there is no read in pending, + * then this function will initiate the next OUT (read) operation. + * + ****************************************************************************/ + +static void stm32_epout_request(FAR struct stm32_usbdev_s *priv, + FAR struct stm32_ep_s *privep) +{ + struct stm32_req_s *privreq; + uint32_t regaddr; + uint32_t regval; + uint32_t xfrsize; + uint32_t pktcnt; + + /* Make sure that there is not already a pending request request. If there is, + * just return, leaving the newly received request in the request queue. + */ + + if (!privep->active) + { + /* Loop until a valid request is found (or the request queue is empty). + * The loop is only need to look at the request queue again is an invalid + * read request is encountered. + */ + + for (; ; ) + { + /* Get a reference to the request at the head of the endpoint's request queue */ + + privreq = stm32_rqpeek(privep); + if (!privreq) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTQEMPTY), privep->epphy); + + /* There are no read requests to be setup. Configure the hardware to + * NAK any incoming packets. (This should already be the case. I + * think that the hardware will automatically NAK after a transfer is + * completed until SNAK is cleared). + */ + + regaddr = STM32_OTG_DOEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + regval |= OTG_DOEPCTL_SNAK; + stm32_putreg(regval, regaddr); + + /* This endpoint is no longer actively transferring */ + + privep->active = false; + return; + } + + uinfo("EP%d: len=%d\n", privep->epphy, privreq->req.len); + + /* Ignore any attempt to receive a zero length packet (this really + * should not happen. + */ + + if (privreq->req.len <= 0) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTNULLPACKET), 0); + stm32_req_complete(privep, OK); + } + + /* Otherwise, we have a usable read request... break out of the loop */ + + else + { + break; + } + } + + /* Setup the pending read into the request buffer. First calculate: + * + * pktcnt = the number of packets (of maxpacket bytes) required to + * perform the transfer. + * xfrsize = The total number of bytes required (in units of + * maxpacket bytes). + */ + + pktcnt = (privreq->req.len + (privep->ep.maxpacket - 1)) / privep->ep.maxpacket; + xfrsize = pktcnt * privep->ep.maxpacket; + + /* Then setup the hardware to perform this transfer */ + + regaddr = STM32_OTG_DOEPTSIZ(privep->epphy); + regval = stm32_getreg(regaddr); + regval &= ~(OTG_DOEPTSIZ_XFRSIZ_MASK | OTG_DOEPTSIZ_PKTCNT_MASK); + regval |= (xfrsize << OTG_DOEPTSIZ_XFRSIZ_SHIFT); + regval |= (pktcnt << OTG_DOEPTSIZ_PKTCNT_SHIFT); + stm32_putreg(regval, regaddr); + + /* Then enable the transfer */ + + regaddr = STM32_OTG_DOEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + + /* When an isochronous transfer is enabled the Even/Odd frame bit must + * also be set appropriately. + */ + +#ifdef CONFIG_USBDEV_ISOCHRONOUS + if (privep->eptype == USB_EP_ATTR_XFER_ISOC) + { + if (privep->odd) + { + regval |= OTG_DOEPCTL_SODDFRM; + } + else + { + regval |= OTG_DOEPCTL_SEVNFRM; + } + } +#endif + + /* Clearing NAKing and enable the transfer. */ + + regval |= (OTG_DOEPCTL_CNAK | OTG_DOEPCTL_EPENA); + stm32_putreg(regval, regaddr); + + /* A transfer is now active on this endpoint */ + + privep->active = true; + + /* EP0 is a special case. We need to know when to switch back to + * normal SETUP processing. + */ + + if (privep->epphy == EP0) + { + priv->ep0state = EP0STATE_DATA_OUT; + } + } +} + +/**************************************************************************** + * Name: stm32_ep_flush + * + * Description: + * Flush any primed descriptors from this ep + * + ****************************************************************************/ + +static void stm32_ep_flush(struct stm32_ep_s *privep) +{ + if (privep->isin) + { + stm32_txfifo_flush(OTG_GRSTCTL_TXFNUM_D(privep->epphy)); + } + else + { + stm32_rxfifo_flush(); + } +} + +/**************************************************************************** + * Name: stm32_req_complete + * + * Description: + * Handle termination of the request at the head of the endpoint request queue. + * + ****************************************************************************/ + +static void stm32_req_complete(struct stm32_ep_s *privep, int16_t result) +{ + FAR struct stm32_req_s *privreq; + + /* Remove the request at the head of the request list */ + + privreq = stm32_req_remfirst(privep); + DEBUGASSERT(privreq != NULL); + + /* If endpoint 0, temporarily reflect the state of protocol stalled + * in the callback. + */ + + bool stalled = privep->stalled; + if (privep->epphy == EP0) + { + privep->stalled = privep->dev->stalled; + } + + /* Save the result in the request structure */ + + privreq->req.result = result; + + /* Callback to the request completion handler */ + + privreq->req.callback(&privep->ep, &privreq->req); + + /* Restore the stalled indication */ + + privep->stalled = stalled; +} + +/**************************************************************************** + * Name: stm32_req_cancel + * + * Description: + * Cancel all pending requests for an endpoint + * + ****************************************************************************/ + +static void stm32_req_cancel(struct stm32_ep_s *privep, int16_t status) +{ + if (!stm32_rqempty(privep)) + { + stm32_ep_flush(privep); + } + + while (!stm32_rqempty(privep)) + { + usbtrace(TRACE_COMPLETE(privep->epphy), + (stm32_rqpeek(privep))->req.xfrd); + stm32_req_complete(privep, status); + } +} + +/**************************************************************************** + * Name: stm32_ep_findbyaddr + * + * Description: + * Find the physical endpoint structure corresponding to a logic endpoint + * address + * + ****************************************************************************/ + +static struct stm32_ep_s *stm32_ep_findbyaddr(struct stm32_usbdev_s *priv, + uint16_t eplog) +{ + struct stm32_ep_s *privep; + uint8_t epphy = USB_EPNO(eplog); + + if (epphy >= STM32_NENDPOINTS) + { + return NULL; + } + + /* Is this an IN or an OUT endpoint? */ + + if (USB_ISEPIN(eplog)) + { + privep = &priv->epin[epphy]; + } + else + { + privep = &priv->epout[epphy]; + } + + /* Return endpoint reference */ + + DEBUGASSERT(privep->epphy == epphy); + return privep; +} + +/**************************************************************************** + * Name: stm32_req_dispatch + * + * Description: + * Provide unhandled setup actions to the class driver. This is logically part + * of the USB interrupt handler. + * + ****************************************************************************/ + +static int stm32_req_dispatch(struct stm32_usbdev_s *priv, + const struct usb_ctrlreq_s *ctrl) +{ + int ret = -EIO; + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DISPATCH), 0); + if (priv->driver) + { + /* Forward to the control request to the class driver implementation */ + + ret = CLASS_SETUP(priv->driver, &priv->usbdev, ctrl, + priv->ep0data, priv->ep0datlen); + } + + if (ret < 0) + { + /* Stall on failure */ + + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DISPATCHSTALL), 0); + priv->stalled = true; + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_usbreset + * + * Description: + * Reset Usb engine + * + ****************************************************************************/ + +static void stm32_usbreset(struct stm32_usbdev_s *priv) +{ + FAR struct stm32_ep_s *privep; + uint32_t regval; + int i; + + /* Clear the Remote Wake-up Signaling */ + + regval = stm32_getreg(STM32_OTG_DCTL); + regval &= ~OTG_DCTL_RWUSIG; + stm32_putreg(regval, STM32_OTG_DCTL); + + /* Flush the EP0 Tx FIFO */ + + stm32_txfifo_flush(OTG_GRSTCTL_TXFNUM_D(EP0)); + + /* Tell the class driver that we are disconnected. The class + * driver should then accept any new configurations. + */ + + if (priv->driver) + { + CLASS_DISCONNECT(priv->driver, &priv->usbdev); + } + + /* Mark all endpoints as available */ + + priv->epavail[0] = STM32_EP_AVAILABLE; + priv->epavail[1] = STM32_EP_AVAILABLE; + + /* Disable all end point interrupts */ + + for (i = 0; i < STM32_NENDPOINTS ; i++) + { + /* Disable endpoint interrupts */ + + stm32_putreg(0xff, STM32_OTG_DIEPINT(i)); + stm32_putreg(0xff, STM32_OTG_DOEPINT(i)); + + /* Return write requests to the class implementation */ + + privep = &priv->epin[i]; + stm32_req_cancel(privep, -ESHUTDOWN); + + /* Reset IN endpoint status */ + + privep->stalled = false; + + /* Return read requests to the class implementation */ + + privep = &priv->epout[i]; + stm32_req_cancel(privep, -ESHUTDOWN); + + /* Reset endpoint status */ + + privep->stalled = false; + } + + stm32_putreg(0xffffffff, STM32_OTG_DAINT); + + /* Mask all device endpoint interrupts except EP0 */ + + regval = (OTG_DAINT_IEP(EP0) | OTG_DAINT_OEP(EP0)); + stm32_putreg(regval, STM32_OTG_DAINTMSK); + + /* Unmask OUT interrupts */ + + regval = (OTG_DOEPMSK_XFRCM | OTG_DOEPMSK_STUPM | OTG_DOEPMSK_EPDM); + stm32_putreg(regval, STM32_OTG_DOEPMSK); + + /* Unmask IN interrupts */ + + regval = (OTG_DIEPMSK_XFRCM | OTG_DIEPMSK_EPDM | OTG_DIEPMSK_TOM); + stm32_putreg(regval, STM32_OTG_DIEPMSK); + + /* Reset device address to 0 */ + + stm32_setaddress(priv, 0); + priv->devstate = DEVSTATE_DEFAULT; + priv->usbdev.speed = USB_SPEED_FULL; + + /* Re-configure EP0 */ + + stm32_ep0_configure(priv); + + /* Setup EP0 to receive SETUP packets */ + + stm32_ep0out_ctrlsetup(priv); +} + +/**************************************************************************** + * Name: stm32_ep0out_testmode + * + * Description: + * Select test mode + * + ****************************************************************************/ + +static inline void stm32_ep0out_testmode(FAR struct stm32_usbdev_s *priv, + uint16_t index) +{ + uint8_t testmode; + + testmode = index >> 8; + switch (testmode) + { + case 1: + priv->testmode = OTG_TESTMODE_J; + break; + + case 2: + priv->testmode = OTG_TESTMODE_K; + break; + + case 3: + priv->testmode = OTG_TESTMODE_SE0_NAK; + break; + + case 4: + priv->testmode = OTG_TESTMODE_PACKET; + break; + + case 5: + priv->testmode = OTG_TESTMODE_FORCE; + break; + + default: + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADTESTMODE), testmode); + priv->dotest = false; + priv->testmode = OTG_TESTMODE_DISABLED; + priv->stalled = true; + } + + priv->dotest = true; + stm32_ep0in_transmitzlp(priv); +} + +/**************************************************************************** + * Name: stm32_ep0out_stdrequest + * + * Description: + * Handle a stanard request on EP0. Pick off the things of interest to the + * USB device controller driver; pass what is left to the class driver. + * + ****************************************************************************/ + +static inline void stm32_ep0out_stdrequest(struct stm32_usbdev_s *priv, + FAR struct stm32_ctrlreq_s *ctrlreq) +{ + FAR struct stm32_ep_s *privep; + + /* Handle standard request */ + + switch (ctrlreq->req) + { + case USB_REQ_GETSTATUS: + { + /* type: device-to-host; recipient = device, interface, endpoint + * value: 0 + * index: zero interface endpoint + * len: 2; data = status + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSTATUS), 0); + if (!priv->addressed || + ctrlreq->len != 2 || + USB_REQ_ISOUT(ctrlreq->type) || + ctrlreq->value != 0) + { + priv->stalled = true; + } + else + { + switch (ctrlreq->type & USB_REQ_RECIPIENT_MASK) + { + case USB_REQ_RECIPIENT_ENDPOINT: + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPGETSTATUS), 0); + privep = stm32_ep_findbyaddr(priv, ctrlreq->index); + if (!privep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPGETSTATUS), 0); + priv->stalled = true; + } + else + { + if (privep->stalled) + { + priv->ep0data[0] = (1 << USB_FEATURE_ENDPOINTHALT); + } + else + { + priv->ep0data[0] = 0; /* Not stalled */ + } + + priv->ep0data[1] = 0; + stm32_ep0in_setupresponse(priv, priv->ep0data, 2); + } + } + break; + + case USB_REQ_RECIPIENT_DEVICE: + { + if (ctrlreq->index == 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DEVGETSTATUS), 0); + + /* Features: Remote Wakeup and self-powered */ + + priv->ep0data[0] = (priv->selfpowered << USB_FEATURE_SELFPOWERED); + priv->ep0data[0] |= (priv->wakeup << USB_FEATURE_REMOTEWAKEUP); + priv->ep0data[1] = 0; + + stm32_ep0in_setupresponse(priv, priv->ep0data, 2); + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADDEVGETSTATUS), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_RECIPIENT_INTERFACE: + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IFGETSTATUS), 0); + priv->ep0data[0] = 0; + priv->ep0data[1] = 0; + + stm32_ep0in_setupresponse(priv, priv->ep0data, 2); + } + break; + + default: + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSTATUS), 0); + priv->stalled = true; + } + break; + } + } + } + break; + + case USB_REQ_CLEARFEATURE: + { + /* type: host-to-device; recipient = device, interface or endpoint + * value: feature selector + * index: zero interface endpoint; + * len: zero, data = none + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_CLEARFEATURE), 0); + if (priv->addressed != 0 && ctrlreq->len == 0) + { + uint8_t recipient = ctrlreq->type & USB_REQ_RECIPIENT_MASK; + if (recipient == USB_REQ_RECIPIENT_ENDPOINT && + ctrlreq->value == USB_FEATURE_ENDPOINTHALT && + (privep = stm32_ep_findbyaddr(priv, ctrlreq->index)) != NULL) + { + stm32_ep_clrstall(privep); + stm32_ep0in_transmitzlp(priv); + } + else if (recipient == USB_REQ_RECIPIENT_DEVICE && + ctrlreq->value == USB_FEATURE_REMOTEWAKEUP) + { + priv->wakeup = 0; + stm32_ep0in_transmitzlp(priv); + } + else + { + /* Actually, I think we could just stall here. */ + + (void)stm32_req_dispatch(priv, &priv->ctrlreq); + } + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADCLEARFEATURE), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_SETFEATURE: + { + /* type: host-to-device; recipient = device, interface, endpoint + * value: feature selector + * index: zero interface endpoint; + * len: 0; data = none + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETFEATURE), 0); + if (priv->addressed != 0 && ctrlreq->len == 0) + { + uint8_t recipient = ctrlreq->type & USB_REQ_RECIPIENT_MASK; + if (recipient == USB_REQ_RECIPIENT_ENDPOINT && + ctrlreq->value == USB_FEATURE_ENDPOINTHALT && + (privep = stm32_ep_findbyaddr(priv, ctrlreq->index)) != NULL) + { + stm32_ep_setstall(privep); + stm32_ep0in_transmitzlp(priv); + } + else if (recipient == USB_REQ_RECIPIENT_DEVICE && + ctrlreq->value == USB_FEATURE_REMOTEWAKEUP) + { + priv->wakeup = 1; + stm32_ep0in_transmitzlp(priv); + } + else if (recipient == USB_REQ_RECIPIENT_DEVICE && + ctrlreq->value == USB_FEATURE_TESTMODE && + ((ctrlreq->index & 0xff) == 0)) + { + stm32_ep0out_testmode(priv, ctrlreq->index); + } + else if (priv->configured) + { + /* Actually, I think we could just stall here. */ + + (void)stm32_req_dispatch(priv, &priv->ctrlreq); + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0); + priv->stalled = true; + } + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETFEATURE), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_SETADDRESS: + { + /* type: host-to-device; recipient = device + * value: device address + * index: 0 + * len: 0; data = none + */ + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETADDRESS), ctrlreq->value); + if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && + ctrlreq->index == 0 && + ctrlreq->len == 0 && + ctrlreq->value < 128 && + priv->devstate != DEVSTATE_CONFIGURED) + { + /* Save the address. We cannot actually change to the next address until + * the completion of the status phase. + */ + + stm32_setaddress(priv, (uint16_t)priv->ctrlreq.value[0]); + stm32_ep0in_transmitzlp(priv); + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETADDRESS), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_GETDESCRIPTOR: + /* type: device-to-host; recipient = device + * value: descriptor type and index + * index: 0 or language ID; + * len: descriptor len; data = descriptor + */ + + case USB_REQ_SETDESCRIPTOR: + /* type: host-to-device; recipient = device + * value: descriptor type and index + * index: 0 or language ID; + * len: descriptor len; data = descriptor + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETDESC), 0); + if ((ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE) + { + (void)stm32_req_dispatch(priv, &priv->ctrlreq); + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETSETDESC), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_GETCONFIGURATION: + /* type: device-to-host; recipient = device + * value: 0; + * index: 0; + * len: 1; data = configuration value + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETCONFIG), 0); + if (priv->addressed && + (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && + ctrlreq->value == 0 && + ctrlreq->index == 0 && + ctrlreq->len == 1) + { + (void)stm32_req_dispatch(priv, &priv->ctrlreq); + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADGETCONFIG), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_SETCONFIGURATION: + /* type: host-to-device; recipient = device + * value: configuration value + * index: 0; + * len: 0; data = none + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETCONFIG), 0); + if (priv->addressed && + (ctrlreq->type & USB_REQ_RECIPIENT_MASK) == USB_REQ_RECIPIENT_DEVICE && + ctrlreq->index == 0 && + ctrlreq->len == 0) + { + /* Give the configuration to the class driver */ + + int ret = stm32_req_dispatch(priv, &priv->ctrlreq); + + /* If the class driver accepted the configuration, then mark the + * device state as configured (or not, depending on the + * configuration). + */ + + if (ret == OK) + { + uint8_t cfg = (uint8_t)ctrlreq->value; + if (cfg != 0) + { + priv->devstate = DEVSTATE_CONFIGURED; + priv->configured = true; + } + else + { + priv->devstate = DEVSTATE_ADDRESSED; + priv->configured = false; + } + } + } + else + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADSETCONFIG), 0); + priv->stalled = true; + } + } + break; + + case USB_REQ_GETINTERFACE: + /* type: device-to-host; recipient = interface + * value: 0 + * index: interface; + * len: 1; data = alt interface + */ + + case USB_REQ_SETINTERFACE: + /* type: host-to-device; recipient = interface + * value: alternate setting + * index: interface; + * len: 0; data = none + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_GETSETIF), 0); + (void)stm32_req_dispatch(priv, &priv->ctrlreq); + } + break; + + case USB_REQ_SYNCHFRAME: + /* type: device-to-host; recipient = endpoint + * value: 0 + * index: endpoint; + * len: 2; data = frame number + */ + + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SYNCHFRAME), 0); + } + break; + + default: + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDCTRLREQ), 0); + priv->stalled = true; + } + break; + } +} + +/**************************************************************************** + * Name: stm32_ep0out_setup + * + * Description: + * USB Ctrl EP Setup Event. This is logically part of the USB interrupt + * handler. This event occurs when a setup packet is receive on EP0 OUT. + * + ****************************************************************************/ + +static inline void stm32_ep0out_setup(struct stm32_usbdev_s *priv) +{ + struct stm32_ctrlreq_s ctrlreq; + + /* Verify that a SETUP was received */ + + if (priv->ep0state != EP0STATE_SETUP_READY) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0NOSETUP), priv->ep0state); + return; + } + + /* Terminate any pending requests */ + + stm32_req_cancel(&priv->epout[EP0], -EPROTO); + stm32_req_cancel(&priv->epin[EP0], -EPROTO); + + /* Assume NOT stalled */ + + priv->epout[EP0].stalled = false; + priv->epin[EP0].stalled = false; + priv->stalled = false; + + /* Starting to process a control request - update state */ + + priv->ep0state = EP0STATE_SETUP_PROCESS; + + /* And extract the little-endian 16-bit values to host order */ + + ctrlreq.type = priv->ctrlreq.type; + ctrlreq.req = priv->ctrlreq.req; + ctrlreq.value = GETUINT16(priv->ctrlreq.value); + ctrlreq.index = GETUINT16(priv->ctrlreq.index); + ctrlreq.len = GETUINT16(priv->ctrlreq.len); + + uinfo("type=%02x req=%02x value=%04x index=%04x len=%04x\n", + ctrlreq.type, ctrlreq.req, ctrlreq.value, ctrlreq.index, ctrlreq.len); + + /* Check for a standard request */ + + if ((ctrlreq.type & USB_REQ_TYPE_MASK) != USB_REQ_TYPE_STANDARD) + { + /* Dispatch any non-standard requests */ + + (void)stm32_req_dispatch(priv, &priv->ctrlreq); + } + else + { + /* Handle standard requests. */ + + stm32_ep0out_stdrequest(priv, &ctrlreq); + } + + /* Check if the setup processing resulted in a STALL */ + + if (priv->stalled) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EP0SETUPSTALLED), priv->ep0state); + stm32_ep0_stall(priv); + } + + /* Reset state/data associated with thie SETUP request */ + + priv->ep0datlen = 0; +} + +/**************************************************************************** + * Name: stm32_epout + * + * Description: + * This is part of the OUT endpoint interrupt processing. This function + * handles the OUT event for a single endpoint. + * + ****************************************************************************/ + +static inline void stm32_epout(FAR struct stm32_usbdev_s *priv, uint8_t epno) +{ + FAR struct stm32_ep_s *privep; + + /* Endpoint 0 is a special case. */ + + if (epno == 0) + { + privep = &priv->epout[EP0]; + + /* In the EP0STATE_DATA_OUT state, we are receiving data into the + * request buffer. In that case, we must continue the request + * processing. + */ + + if (priv->ep0state == EP0STATE_DATA_OUT) + { + /* Continue processing data from the EP0 OUT request queue */ + + stm32_epout_complete(priv, privep); + + /* If we are not actively processing an OUT request, then we + * need to setup to receive the next control request. + */ + + if (!privep->active) + { + stm32_ep0out_ctrlsetup(priv); + priv->ep0state = EP0STATE_IDLE; + } + } + } + + /* For other endpoints, the only possibility is that we are continuing + * or finishing an OUT request. + */ + + else if (priv->devstate == DEVSTATE_CONFIGURED) + { + stm32_epout_complete(priv, &priv->epout[epno]); + } +} + +/**************************************************************************** + * Name: stm32_epout_interrupt + * + * Description: + * USB OUT endpoint interrupt handler. The core generates this interrupt when + * there is an interrupt is pending on one of the OUT endpoints of the core. + * The driver must read the OTG DAINT register to determine the exact number + * of the OUT endpoint on which the interrupt occurred, and then read the + * corresponding OTG DOEPINTx register to determine the exact cause of the + * interrupt. + * + ****************************************************************************/ + +static inline void stm32_epout_interrupt(FAR struct stm32_usbdev_s *priv) +{ + uint32_t daint; + uint32_t regval; + uint32_t doepint; + int epno; + + /* Get the pending, enabled interrupts for the OUT endpoint from the endpoint + * interrupt status register. + */ + + regval = stm32_getreg(STM32_OTG_DAINT); + regval &= stm32_getreg(STM32_OTG_DAINTMSK); + daint = (regval & OTG_DAINT_OEP_MASK) >> OTG_DAINT_OEP_SHIFT; + + if (daint == 0) + { + /* We got an interrupt, but there is no unmasked endpoint that caused + * it ?! When this happens, the interrupt flag never gets cleared and + * we are stuck in infinite interrupt loop. + * + * This shouldn't happen if we are diligent about handling timing + * issues when masking endpoint interrupts. However, this workaround + * avoids infinite loop and allows operation to continue normally. It + * works by clearing each endpoint flags, masked or not. + */ + + regval = stm32_getreg(STM32_OTG_DAINT); + daint = (regval & OTG_DAINT_OEP_MASK) >> OTG_DAINT_OEP_SHIFT; + + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPOUTUNEXPECTED), + (uint16_t)regval); + + epno = 0; + while (daint) + { + if ((daint & 1) != 0) + { + regval = stm32_getreg(STM32_OTG_DOEPINT(epno)); + uerr("DOEPINT(%d) = %08x\n", epno, regval); + stm32_putreg(0xFF, STM32_OTG_DOEPINT(epno)); + } + + epno++; + daint >>= 1; + } + + return; + } + + /* Process each pending IN endpoint interrupt */ + + epno = 0; + while (daint) + { + /* Is an OUT interrupt pending for this endpoint? */ + + if ((daint & 1) != 0) + { + /* Yes.. get the OUT endpoint interrupt status */ + + doepint = stm32_getreg(STM32_OTG_DOEPINT(epno)); + doepint &= stm32_getreg(STM32_OTG_DOEPMSK); + + /* Transfer completed interrupt. This interrupt is trigged when + * stm32_rxinterrupt() removes the last packet data from the RxFIFO. + * In this case, core internally sets the NAK bit for this endpoint to + * prevent it from receiving any more packets. + */ + + if ((doepint & OTG_DOEPINT_XFRC) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_XFRC), (uint16_t)doepint); + + /* Clear the bit in DOEPINTn for this interrupt */ + + stm32_putreg(OTG_DOEPINT_XFRC, STM32_OTG_DOEPINT(epno)); + + /* Handle the RX transfer data ready event */ + + stm32_epout(priv, epno); + } + + /* Endpoint disabled interrupt (ignored because this interrupt is + * used in polled mode by the endpoint disable logic). + */ +#if 1 + /* REVISIT: */ + if ((doepint & OTG_DOEPINT_EPDISD) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_EPDISD), (uint16_t)doepint); + + /* Clear the bit in DOEPINTn for this interrupt */ + + stm32_putreg(OTG_DOEPINT_EPDISD, STM32_OTG_DOEPINT(epno)); + } +#endif + /* Setup Phase Done (control EPs) */ + + if ((doepint & OTG_DOEPINT_SETUP) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT_SETUP), priv->ep0state); + + /* Handle the receipt of the IN SETUP packets now (OUT setup + * packet processing may be delayed until the accompanying + * OUT DATA is received) + */ + + if (priv->ep0state == EP0STATE_SETUP_READY) + { + stm32_ep0out_setup(priv); + } + stm32_putreg(OTG_DOEPINT_SETUP, STM32_OTG_DOEPINT(epno)); + } + } + + epno++; + daint >>= 1; + } +} + +/**************************************************************************** + * Name: stm32_epin_runtestmode + * + * Description: + * Execute the test mode setup by the SET FEATURE request + * + ****************************************************************************/ + +static inline void stm32_epin_runtestmode(FAR struct stm32_usbdev_s *priv) +{ + uint32_t regval = stm32_getreg(STM32_OTG_DCTL); + regval &= OTG_DCTL_TCTL_MASK; + regval |= (uint32_t)priv->testmode << OTG_DCTL_TCTL_SHIFT; + stm32_putreg(regval , STM32_OTG_DCTL); + + priv->dotest = 0; + priv->testmode = OTG_TESTMODE_DISABLED; +} + +/**************************************************************************** + * Name: stm32_epin + * + * Description: + * This is part of the IN endpoint interrupt processing. This function + * handles the IN event for a single endpoint. + * + ****************************************************************************/ + +static inline void stm32_epin(FAR struct stm32_usbdev_s *priv, uint8_t epno) +{ + FAR struct stm32_ep_s *privep = &priv->epin[epno]; + + /* Endpoint 0 is a special case. */ + + if (epno == 0) + { + /* In the EP0STATE_DATA_IN state, we are sending data from request + * buffer. In that case, we must continue the request processing. + */ + + if (priv->ep0state == EP0STATE_DATA_IN) + { + /* Continue processing data from the EP0 OUT request queue */ + + stm32_epin_request(priv, privep); + + /* If we are not actively processing an OUT request, then we + * need to setup to receive the next control request. + */ + + if (!privep->active) + { + stm32_ep0out_ctrlsetup(priv); + priv->ep0state = EP0STATE_IDLE; + } + } + + /* Test mode is another special case */ + + if (priv->dotest) + { + stm32_epin_runtestmode(priv); + } + } + + /* For other endpoints, the only possibility is that we are continuing + * or finishing an IN request. + */ + + else if (priv->devstate == DEVSTATE_CONFIGURED) + { + /* Continue processing data from the endpoint write request queue */ + + stm32_epin_request(priv, privep); + } +} + +/**************************************************************************** + * Name: stm32_epin_txfifoempty + * + * Description: + * TxFIFO empty interrupt handling + * + ****************************************************************************/ + +static inline void stm32_epin_txfifoempty(FAR struct stm32_usbdev_s *priv, int epno) +{ + FAR struct stm32_ep_s *privep = &priv->epin[epno]; + + /* Continue processing the write request queue. This may mean sending + * more data from the existing request or terminating the current requests + * and (perhaps) starting the IN transfer from the next write request. + */ + + stm32_epin_request(priv, privep); +} + +/**************************************************************************** + * Name: stm32_epin_interrupt + * + * Description: + * USB IN endpoint interrupt handler. The core generates this interrupt when + * an interrupt is pending on one of the IN endpoints of the core. The driver + * must read the OTG DAINT register to determine the exact number of the IN + * endpoint on which the interrupt occurred, and then read the corresponding + * OTG DIEPINTx register to determine the exact cause of the interrupt. + * + ****************************************************************************/ + +static inline void stm32_epin_interrupt(FAR struct stm32_usbdev_s *priv) +{ + uint32_t diepint; + uint32_t daint; + uint32_t mask; + uint32_t empty; + int epno; + + /* Get the pending, enabled interrupts for the IN endpoint from the endpoint + * interrupt status register. + */ + + daint = stm32_getreg(STM32_OTG_DAINT); + daint &= stm32_getreg(STM32_OTG_DAINTMSK); + daint &= OTG_DAINT_IEP_MASK; + + if (daint == 0) + { + /* We got an interrupt, but there is no unmasked endpoint that caused + * it ?! When this happens, the interrupt flag never gets cleared and + * we are stuck in infinite interrupt loop. + * + * This shouldn't happen if we are diligent about handling timing + * issues when masking endpoint interrupts. However, this workaround + * avoids infinite loop and allows operation to continue normally. It + * works by clearing each endpoint flags, masked or not. + */ + + daint = stm32_getreg(STM32_OTG_DAINT); + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_EPINUNEXPECTED), + (uint16_t)daint); + + daint &= OTG_DAINT_IEP_MASK; + epno = 0; + + while (daint) + { + if ((daint & 1) != 0) + { + uerr("DIEPINT(%d) = %08x\n", + epno, stm32_getreg(STM32_OTG_DIEPINT(epno))); + stm32_putreg(0xFF, STM32_OTG_DIEPINT(epno)); + } + + epno++; + daint >>= 1; + } + + return; + } + + /* Process each pending IN endpoint interrupt */ + + epno = 0; + while (daint) + { + /* Is an IN interrupt pending for this endpoint? */ + + if ((daint & 1) != 0) + { + /* Get IN interrupt mask register. Bits 0-6 correspond to enabled + * interrupts as will be found in the DIEPINT interrupt status + * register. + */ + + mask = stm32_getreg(STM32_OTG_DIEPMSK); + + /* Check if the TxFIFO not empty interrupt is enabled for this + * endpoint in the DIEPMSK register. Bits n corresponds to + * endpoint n in the register. That condition corresponds to + * bit 7 of the DIEPINT interrupt status register. There is + * no TXFE bit in the mask register, so we fake one here. + */ + + empty = stm32_getreg(STM32_OTG_DIEPEMPMSK); + if ((empty & OTG_DIEPEMPMSK(epno)) != 0) + { + mask |= OTG_DIEPINT_TXFE; + } + + /* Now, read the interrupt status and mask out all disabled + * interrupts. + */ + + diepint = stm32_getreg(STM32_OTG_DIEPINT(epno)) & mask; + + /* Decode and process the enabled, pending interrupts */ + /* Transfer completed interrupt */ + + if ((diepint & OTG_DIEPINT_XFRC) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_XFRC), + (uint16_t)diepint); + + /* It is possible that logic may be waiting for a the + * TxFIFO to become empty. We disable the TxFIFO empty + * interrupt here; it will be re-enabled if there is still + * insufficient space in the TxFIFO. + */ + + empty &= ~OTG_DIEPEMPMSK(epno); + stm32_putreg(empty, STM32_OTG_DIEPEMPMSK); + stm32_putreg(OTG_DIEPINT_XFRC, STM32_OTG_DIEPINT(epno)); + + /* IN transfer complete */ + + stm32_epin(priv, epno); + } + + /* Timeout condition */ + + if ((diepint & OTG_DIEPINT_TOC) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TOC), (uint16_t)diepint); + stm32_putreg(OTG_DIEPINT_TOC, STM32_OTG_DIEPINT(epno)); + } + + /* IN token received when TxFIFO is empty. Applies to non-periodic IN + * endpoints only. This interrupt indicates that an IN token was received + * when the associated TxFIFO (periodic/non-periodic) was empty. This + * interrupt is asserted on the endpoint for which the IN token was + * received. + */ + + if ((diepint & OTG_DIEPINT_ITTXFE) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_ITTXFE), (uint16_t)diepint); + stm32_epin_request(priv, &priv->epin[epno]); + stm32_putreg(OTG_DIEPINT_ITTXFE, STM32_OTG_DIEPINT(epno)); + } + + /* IN endpoint NAK effective (ignored as this used only in polled + * mode) + */ +#if 0 + if ((diepint & OTG_DIEPINT_INEPNE) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_INEPNE), (uint16_t)diepint); + stm32_putreg(OTG_DIEPINT_INEPNE, STM32_OTG_DIEPINT(epno)); + } +#endif + /* Endpoint disabled interrupt (ignored as this used only in polled + * mode) + */ +#if 0 + if ((diepint & OTG_DIEPINT_EPDISD) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_EPDISD), (uint16_t)diepint); + stm32_putreg(OTG_DIEPINT_EPDISD, STM32_OTG_DIEPINT(epno)); + } +#endif + /* Transmit FIFO empty */ + + if ((diepint & OTG_DIEPINT_TXFE) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN_TXFE), (uint16_t)diepint); + + /* If we were waiting for TxFIFO to become empty, the we might have both + * XFRC and TXFE interrupts pending. Since we do the same thing for both + * cases, ignore the TXFE if we have already processed the XFRC. + */ + + if ((diepint & OTG_DIEPINT_XFRC) == 0) + { + /* Mask further FIFO empty interrupts. This will be re-enabled + * whenever we need to wait for a FIFO event. + */ + + empty &= ~OTG_DIEPEMPMSK(epno); + stm32_putreg(empty, STM32_OTG_DIEPEMPMSK); + + /* Handle TxFIFO empty */ + + stm32_epin_txfifoempty(priv, epno); + } + + /* Clear the pending TxFIFO empty interrupt */ + + stm32_putreg(OTG_DIEPINT_TXFE, STM32_OTG_DIEPINT(epno)); + } + } + + epno++; + daint >>= 1; + } +} + +/**************************************************************************** + * Name: stm32_resumeinterrupt + * + * Description: + * Resume/remote wakeup detected interrupt + * + ****************************************************************************/ + +static inline void stm32_resumeinterrupt(FAR struct stm32_usbdev_s *priv) +{ + uint32_t regval; + + /* Restart the PHY clock and un-gate USB core clock (HCLK) */ + +#ifdef CONFIG_USBDEV_LOWPOWER + regval = stm32_getreg(STM32_OTG_PCGCCTL); + regval &= ~(OTG_PCGCCTL_STPPCLK | OTG_PCGCCTL_GATEHCLK); + stm32_putreg(regval, STM32_OTG_PCGCCTL); +#endif + + /* Clear remote wake-up signaling */ + + regval = stm32_getreg(STM32_OTG_DCTL); + regval &= ~OTG_DCTL_RWUSIG; + stm32_putreg(regval, STM32_OTG_DCTL); + + /* Restore full power -- whatever that means for this particular board */ + + stm32_usbsuspend((struct usbdev_s *)priv, true); + + /* Notify the class driver of the resume event */ + + if (priv->driver) + { + CLASS_RESUME(priv->driver, &priv->usbdev); + } +} + +/**************************************************************************** + * Name: stm32_suspendinterrupt + * + * Description: + * USB suspend interrupt + * + ****************************************************************************/ + +static inline void stm32_suspendinterrupt(FAR struct stm32_usbdev_s *priv) +{ +#ifdef CONFIG_USBDEV_LOWPOWER + uint32_t regval; +#endif + + /* Notify the class driver of the suspend event */ + + if (priv->driver) + { + CLASS_SUSPEND(priv->driver, &priv->usbdev); + } + +#ifdef CONFIG_USBDEV_LOWPOWER + /* OTG_DSTS_SUSPSTS is set as long as the suspend condition is detected + * on USB. Check if we are still have the suspend condition, that we are + * connected to the host, and that we have been configured. + */ + + regval = stm32_getreg(STM32_OTG_DSTS); + + if ((regval & OTG_DSTS_SUSPSTS) != 0 && devstate == DEVSTATE_CONFIGURED) + { + /* Switch off OTG clocking. Setting OTG_PCGCCTL_STPPCLK stops the + * PHY clock. + */ + + regval = stm32_getreg(STM32_OTG_PCGCCTL); + regval |= OTG_PCGCCTL_STPPCLK; + stm32_putreg(regval, STM32_OTG_PCGCCTL); + + /* Setting OTG_PCGCCTL_GATEHCLK gate HCLK to modules other than + * the AHB Slave and Master and wakeup logic. + */ + + regval |= OTG_PCGCCTL_GATEHCLK; + stm32_putreg(regval, STM32_OTG_PCGCCTL); + } +#endif + + /* Let the board-specific logic know that we have entered the suspend + * state + */ + + stm32_usbsuspend((FAR struct usbdev_s *)priv, false); +} + +/**************************************************************************** + * Name: stm32_rxinterrupt + * + * Description: + * RxFIFO non-empty interrupt. This interrupt indicates that there is at + * least one packet pending to be read from the RxFIFO. + * + ****************************************************************************/ + +static inline void stm32_rxinterrupt(FAR struct stm32_usbdev_s *priv) +{ + FAR struct stm32_ep_s *privep; + uint32_t regval; + int bcnt; + int epphy; + + /* Disable the Rx status queue level interrupt */ + + regval = stm32_getreg(STM32_OTG_GINTMSK); + regval &= ~OTG_GINT_RXFLVL; + stm32_putreg(regval, STM32_OTG_GINTMSK); + + /* Get the status from the top of the FIFO */ + + regval = stm32_getreg(STM32_OTG_GRXSTSP); + + /* Decode status fields */ + + epphy = (regval & OTG_GRXSTSD_EPNUM_MASK) >> OTG_GRXSTSD_EPNUM_SHIFT; + + if (epphy < STM32_NENDPOINTS) + { + privep = &priv->epout[epphy]; + + /* Handle the RX event according to the packet status field */ + + switch (regval & OTG_GRXSTSD_PKTSTS_MASK) + { + /* Global OUT NAK. This indicate that the global OUT NAK bit has taken + * effect. + * + * PKTSTS = Global OUT NAK, BCNT = 0, EPNUM = Don't Care, DPID = Don't + * Care. + */ + + case OTG_GRXSTSD_PKTSTS_OUTNAK: + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTNAK), 0); + } + break; + + /* OUT data packet received. + * + * PKTSTS = DataOUT, BCNT = size of the received data OUT packet, + * EPNUM = EPNUM on which the packet was received, DPID = Actual Data PID. + */ + + case OTG_GRXSTSD_PKTSTS_OUTRECVD: + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTRECVD), epphy); + bcnt = (regval & OTG_GRXSTSD_BCNT_MASK) >> OTG_GRXSTSD_BCNT_SHIFT; + if (bcnt > 0) + { + stm32_epout_receive(privep, bcnt); + } + } + break; + + /* OUT transfer completed. This indicates that an OUT data transfer for + * the specified OUT endpoint has completed. After this entry is popped + * from the receive FIFO, the core asserts a Transfer Completed interrupt + * on the specified OUT endpoint. + * + * PKTSTS = Data OUT Transfer Done, BCNT = 0, EPNUM = OUT EP Num on + * which the data transfer is complete, DPID = Don't Care. + */ + + case OTG_GRXSTSD_PKTSTS_OUTDONE: + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OUTDONE), epphy); + } + break; + + /* SETUP transaction completed. This indicates that the Setup stage for + * the specified endpoint has completed and the Data stage has started. + * After this entry is popped from the receive FIFO, the core asserts a + * Setup interrupt on the specified control OUT endpoint (triggers an + * interrupt). + * + * PKTSTS = Setup Stage Done, BCNT = 0, EPNUM = Control EP Num, + * DPID = Don't Care. + */ + + case OTG_GRXSTSD_PKTSTS_SETUPDONE: + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPDONE), epphy); + } + break; + + /* SETUP data packet received. This indicates that a SETUP packet for the + * specified endpoint is now available for reading from the receive FIFO. + * + * PKTSTS = SETUP, BCNT = 8, EPNUM = Control EP Num, DPID = D0. + */ + + case OTG_GRXSTSD_PKTSTS_SETUPRECVD: + { + uint16_t datlen; + + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SETUPRECVD), epphy); + + /* Read EP0 setup data. NOTE: If multiple SETUP packets are received, + * the last one overwrites the previous setup packets and only that + * last SETUP packet will be processed. + */ + + stm32_rxfifo_read(&priv->epout[EP0], (FAR uint8_t *)&priv->ctrlreq, + USB_SIZEOF_CTRLREQ); + + /* Was this an IN or an OUT SETUP packet. If it is an OUT SETUP, + * then we need to wait for the completion of the data phase to + * process the setup command. If it is an IN SETUP packet, then + * we must processing the command BEFORE we enter the DATA phase. + * + * If the data associated with the OUT SETUP packet is zero length, + * then, of course, we don't need to wait. + */ + + datlen = GETUINT16(priv->ctrlreq.len); + if (USB_REQ_ISOUT(priv->ctrlreq.type) && datlen > 0) + { + /* Clear NAKSTS so that we can receive the data */ + + regval = stm32_getreg(STM32_OTG_DOEPCTL(0)); + regval |= OTG_DOEPCTL0_CNAK; + stm32_putreg(regval, STM32_OTG_DOEPCTL(0)); + + /* Wait for the data phase. */ + + priv->ep0state = EP0STATE_SETUP_OUT; + } + else + { + /* We can process the setup data as soon as SETUP done word is + * popped of the RxFIFO. + */ + + priv->ep0state = EP0STATE_SETUP_READY; + } + } + break; + + default: + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), + (regval & OTG_GRXSTSD_PKTSTS_MASK) >> OTG_GRXSTSD_PKTSTS_SHIFT); + } + break; + } + } + + /* Enable the Rx Status Queue Level interrupt */ + + regval = stm32_getreg(STM32_OTG_GINTMSK); + regval |= OTG_GINT_RXFLVL; + stm32_putreg(regval, STM32_OTG_GINTMSK); +} + +/**************************************************************************** + * Name: stm32_enuminterrupt + * + * Description: + * Enumeration done interrupt + * + ****************************************************************************/ + +static inline void stm32_enuminterrupt(FAR struct stm32_usbdev_s *priv) +{ + uint32_t regval; + + /* Activate EP0 */ + + stm32_ep0in_activate(); + + /* Set USB turn-around time for the full speed device with internal PHY interface. */ + + regval = stm32_getreg(STM32_OTG_GUSBCFG); + regval &= ~OTG_GUSBCFG_TRDT_MASK; + regval |= OTG_GUSBCFG_TRDT(5); + stm32_putreg(regval, STM32_OTG_GUSBCFG); +} + +/**************************************************************************** + * Name: stm32_isocininterrupt + * + * Description: + * Incomplete isochronous IN transfer interrupt. Assertion of the incomplete + * isochronous IN transfer interrupt indicates an incomplete isochronous IN + * transfer on at least one of the isochronous IN endpoints. + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV_ISOCHRONOUS +static inline void stm32_isocininterrupt(FAR struct stm32_usbdev_s *priv) +{ + int i; + + /* The application must read the endpoint control register for all isochronous + * IN endpoints to detect endpoints with incomplete IN data transfers. + */ + + for (i = 0; i < STM32_NENDPOINTS; i++) + { + /* Is this an isochronous IN endpoint? */ + + privep = &priv->epin[i]; + if (privep->eptype != USB_EP_ATTR_XFER_ISOC) + { + /* No... keep looking */ + + continue; + } + + /* Is there an active read request on the isochronous OUT endpoint? */ + + if (!privep->active) + { + /* No.. the endpoint is not actively transmitting data */ + + continue; + } + + /* Check if this is the endpoint that had the incomplete transfer */ + + regaddr = STM32_OTG_DIEPCTL(privep->epphy); + doepctl = stm32_getreg(regaddr); + dsts = stm32_getreg(STM32_OTG_DSTS); + + /* EONUM = 0:even frame, 1:odd frame + * SOFFN = Frame number of the received SOF + */ + + eonum = ((doepctl & OTG_DIEPCTL_EONUM) != 0); + soffn = ((dsts & OTG_DSTS_SOFFN0) != 0); + + if (eonum != soffn) + { + /* Not this endpoint */ + + continue; + } + + /* For isochronous IN endpoints with incomplete transfers, + * the application must discard the data in the memory and + * disable the endpoint. + */ + + stm32_req_complete(privep, -EIO); +#warning "Will clear OTG_DIEPCTL_USBAEP too" + stm32_epin_disable(privep); + break; + } +} +#endif + +/**************************************************************************** + * Name: stm32_isocoutinterrupt + * + * Description: + * Incomplete periodic transfer interrupt + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV_ISOCHRONOUS +static inline void stm32_isocoutinterrupt(FAR struct stm32_usbdev_s *priv) +{ + FAR struct stm32_ep_s *privep; + FAR struct stm32_req_s *privreq; + uint32_t regaddr; + uint32_t doepctl; + uint32_t dsts; + bool eonum; + bool soffn; + + /* When it receives an IISOOXFR interrupt, the application must read the + * control registers of all isochronous OUT endpoints to determine which + * endpoints had an incomplete transfer in the current microframe. An + * endpoint transfer is incomplete if both the following conditions are true: + * + * DOEPCTLx:EONUM = DSTS:SOFFN[0], and + * DOEPCTLx:EPENA = 1 + */ + + for (i = 0; i < STM32_NENDPOINTS; i++) + { + /* Is this an isochronous OUT endpoint? */ + + privep = &priv->epout[i]; + if (privep->eptype != USB_EP_ATTR_XFER_ISOC) + { + /* No... keep looking */ + + continue; + } + + /* Is there an active read request on the isochronous OUT endpoint? */ + + if (!privep->active) + { + /* No.. the endpoint is not actively transmitting data */ + + continue; + } + + /* Check if this is the endpoint that had the incomplete transfer */ + + regaddr = STM32_OTG_DOEPCTL(privep->epphy); + doepctl = stm32_getreg(regaddr); + dsts = stm32_getreg(STM32_OTG_DSTS); + + /* EONUM = 0:even frame, 1:odd frame + * SOFFN = Frame number of the received SOF + */ + + eonum = ((doepctl & OTG_DOEPCTL_EONUM) != 0); + soffn = ((dsts & OTG_DSTS_SOFFN0) != 0); + + if (eonum != soffn) + { + /* Not this endpoint */ + + continue; + } + + /* For isochronous OUT endpoints with incomplete transfers, + * the application must discard the data in the memory and + * disable the endpoint. + */ + + stm32_req_complete(privep, -EIO); +#warning "Will clear OTG_DOEPCTL_USBAEP too" + stm32_epout_disable(privep); + break; + } +} +#endif + +/**************************************************************************** + * Name: stm32_sessioninterrupt + * + * Description: + * Session request/new session detected interrupt + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV_VBUSSENSING +static inline void stm32_sessioninterrupt(FAR struct stm32_usbdev_s *priv) +{ +#warning "Missing logic" +} +#endif + +/**************************************************************************** + * Name: stm32_otginterrupt + * + * Description: + * OTG interrupt + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV_VBUSSENSING +static inline void stm32_otginterrupt(FAR struct stm32_usbdev_s *priv) +{ + uint32_t regval; + + /* Check for session end detected */ + + regval = stm32_getreg(STM32_OTG_GOTGINT); + if ((regval & OTG_GOTGINT_SEDET) != 0) + { +#warning "Missing logic" + } + + /* Clear OTG interrupt */ + + stm32_putreg(retval, STM32_OTG_GOTGINT); +} +#endif + +/**************************************************************************** + * Name: stm32_usbinterrupt + * + * Description: + * USB interrupt handler + * + ****************************************************************************/ + +static int stm32_usbinterrupt(int irq, FAR void *context) +{ + /* At present, there is only a single OTG device support. Hence it is + * pre-allocated as g_otghsdev. However, in most code, the private data + * structure will be referenced using the 'priv' pointer (rather than the + * global data) in order to simplify any future support for multiple devices. + */ + + FAR struct stm32_usbdev_s *priv = &g_otghsdev; + uint32_t regval; + + usbtrace(TRACE_INTENTRY(STM32_TRACEINTID_USB), 0); + + /* Assure that we are in device mode */ + + DEBUGASSERT((stm32_getreg(STM32_OTG_GINTSTS) & OTG_GINTSTS_CMOD) == OTG_GINTSTS_DEVMODE); + + /* Get the state of all enabled interrupts. We will do this repeatedly + * some interrupts (like RXFLVL) will generate additional interrupting + * events. + */ + + for (; ; ) + { + /* Get the set of pending, un-masked interrupts */ + + regval = stm32_getreg(STM32_OTG_GINTSTS); + regval &= stm32_getreg(STM32_OTG_GINTMSK); + + /* Break out of the loop when there are no further pending (and + * unmasked) interrupts to be processes. + */ + + if (regval == 0) + { + break; + } + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_INTPENDING), (uint16_t)regval); + + /* OUT endpoint interrupt. The core sets this bit to indicate that an + * interrupt is pending on one of the OUT endpoints of the core. + */ + + if ((regval & OTG_GINT_OEP) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPOUT), (uint16_t)regval); + stm32_epout_interrupt(priv); + stm32_putreg(OTG_GINT_OEP, STM32_OTG_GINTSTS); + } + + /* IN endpoint interrupt. The core sets this bit to indicate that + * an interrupt is pending on one of the IN endpoints of the core. + */ + + if ((regval & OTG_GINT_IEP) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_EPIN), (uint16_t)regval); + stm32_epin_interrupt(priv); + stm32_putreg(OTG_GINT_IEP, STM32_OTG_GINTSTS); + } + + /* Host/device mode mismatch error interrupt */ + +#ifdef CONFIG_DEBUG_USB + if ((regval & OTG_GINT_MMIS) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_MISMATCH), (uint16_t)regval); + stm32_putreg(OTG_GINT_MMIS, STM32_OTG_GINTSTS); + } +#endif + + /* Resume/remote wakeup detected interrupt */ + + if ((regval & OTG_GINT_WKUP) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_WAKEUP), (uint16_t)regval); + stm32_resumeinterrupt(priv); + stm32_putreg(OTG_GINT_WKUP, STM32_OTG_GINTSTS); + } + + /* USB suspend interrupt */ + + if ((regval & OTG_GINT_USBSUSP) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SUSPEND), (uint16_t)regval); + stm32_suspendinterrupt(priv); + stm32_putreg(OTG_GINT_USBSUSP, STM32_OTG_GINTSTS); + } + + /* Start of frame interrupt */ + +#ifdef CONFIG_USBDEV_SOFINTERRUPT + if ((regval & OTG_GINT_SOF) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SOF), (uint16_t)regval); + stm32_putreg(OTG_GINT_SOF, STM32_OTG_GINTSTS); + } +#endif + + /* RxFIFO non-empty interrupt. Indicates that there is at least one + * packet pending to be read from the RxFIFO. + */ + + if ((regval & OTG_GINT_RXFLVL) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_RXFIFO), (uint16_t)regval); + stm32_rxinterrupt(priv); + stm32_putreg(OTG_GINT_RXFLVL, STM32_OTG_GINTSTS); + } + + /* USB reset interrupt */ + + if ((regval & OTG_GINT_USBRST) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_DEVRESET), (uint16_t)regval); + + /* Perform the device reset */ + + stm32_usbreset(priv); + usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USB), 0); + stm32_putreg(OTG_GINT_USBRST, STM32_OTG_GINTSTS); + return OK; + } + + /* Enumeration done interrupt */ + + if ((regval & OTG_GINT_ENUMDNE) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_ENUMDNE), (uint16_t)regval); + stm32_enuminterrupt(priv); + stm32_putreg(OTG_GINT_ENUMDNE, STM32_OTG_GINTSTS); + } + + /* Incomplete isochronous IN transfer interrupt. When the core finds + * non-empty any of the isochronous IN endpoint FIFOs scheduled for + * the current frame non-empty, the core generates an IISOIXFR + * interrupt. + */ + +#ifdef CONFIG_USBDEV_ISOCHRONOUS + if ((regval & OTG_GINT_IISOIXFR) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOIXFR), (uint16_t)regval); + stm32_isocininterrupt(priv); + stm32_putreg(OTG_GINT_IISOIXFR, STM32_OTG_GINTSTS); + } + + /* Incomplete isochronous OUT transfer. For isochronous OUT + * endpoints, the XFRC interrupt may not always be asserted. If the + * core drops isochronous OUT data packets, the application could fail + * to detect the XFRC interrupt. The incomplete Isochronous OUT data + * interrupt indicates that an XFRC interrupt was not asserted on at + * least one of the isochronous OUT endpoints. At this point, the + * endpoint with the incomplete transfer remains enabled, but no active + * transfers remain in progress on this endpoint on the USB. + */ + + if ((regval & OTG_GINT_IISOOXFR) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_IISOOXFR), (uint16_t)regval); + stm32_isocoutinterrupt(priv); + stm32_putreg(OTG_GINT_IISOOXFR, STM32_OTG_GINTSTS); + } +#endif + + /* Session request/new session detected interrupt */ + +#ifdef CONFIG_USBDEV_VBUSSENSING + if ((regval & OTG_GINT_SRQ) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_SRQ), (uint16_t)regval); + stm32_sessioninterrupt(priv); + stm32_putreg(OTG_GINT_SRQ, STM32_OTG_GINTSTS); + } + + /* OTG interrupt */ + + if ((regval & OTG_GINT_OTG) != 0) + { + usbtrace(TRACE_INTDECODE(STM32_TRACEINTID_OTG), (uint16_t)regval); + stm32_otginterrupt(priv); + stm32_putreg(OTG_GINT_OTG, STM32_OTG_GINTSTS); + } +#endif + } + + usbtrace(TRACE_INTEXIT(STM32_TRACEINTID_USB), 0); + return OK; +} + +/**************************************************************************** + * Endpoint operations + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_enablegonak + * + * Description: + * Enable global OUT NAK mode + * + ****************************************************************************/ + +static void stm32_enablegonak(FAR struct stm32_ep_s *privep) +{ + uint32_t regval; + + /* First, make sure that there is no GNOAKEFF interrupt pending. */ + +#if 0 + stm32_putreg(OTG_GINT_GONAKEFF, STM32_OTG_GINTSTS); +#endif + + /* Enable Global OUT NAK mode in the core. */ + + regval = stm32_getreg(STM32_OTG_DCTL); + regval |= OTG_DCTL_SGONAK; + stm32_putreg(regval, STM32_OTG_DCTL); + +#if 0 + /* Wait for the GONAKEFF interrupt that indicates that the OUT NAK + * mode is in effect. When the interrupt handler pops the OUTNAK word + * from the RxFIFO, the core sets the GONAKEFF interrupt. + */ + + while ((stm32_getreg(STM32_OTG_GINTSTS) & OTG_GINT_GONAKEFF) == 0); + stm32_putreg(OTG_GINT_GONAKEFF, STM32_OTG_GINTSTS); + +#else + /* Since we are in the interrupt handler, we cannot wait inline for the + * GONAKEFF because it cannot occur until service the RXFLVL global interrupt + * and pop the OUTNAK word from the RxFIFO. + * + * Perhaps it is sufficient to wait for Global OUT NAK status to be reported + * in OTG DCTL register? + */ + + while ((stm32_getreg(STM32_OTG_DCTL) & OTG_DCTL_GONSTS) == 0); +#endif +} + +/**************************************************************************** + * Name: stm32_disablegonak + * + * Description: + * Disable global OUT NAK mode + * + ****************************************************************************/ + +static void stm32_disablegonak(FAR struct stm32_ep_s *privep) +{ + uint32_t regval; + + /* Set the "Clear the Global OUT NAK bit" to disable global OUT NAK mode */ + + regval = stm32_getreg(STM32_OTG_DCTL); + regval |= OTG_DCTL_CGONAK; + stm32_putreg(regval, STM32_OTG_DCTL); +} + +/**************************************************************************** + * Name: stm32_epout_configure + * + * Description: + * Configure an OUT endpoint, making it usable + * + * Input Parameters: + * privep - a pointer to an internal endpoint structure + * eptype - The type of the endpoint + * maxpacket - The max packet size of the endpoint + * + ****************************************************************************/ + +static int stm32_epout_configure(FAR struct stm32_ep_s *privep, + uint8_t eptype, uint16_t maxpacket) +{ + uint32_t mpsiz; + uint32_t regaddr; + uint32_t regval; + + usbtrace(TRACE_EPCONFIGURE, privep->epphy); + + /* For EP0, the packet size is encoded */ + + if (privep->epphy == EP0) + { + DEBUGASSERT(eptype == USB_EP_ATTR_XFER_CONTROL); + + /* Map the size in bytes to the encoded value in the register */ + + switch (maxpacket) + { + case 8: + mpsiz = OTG_DOEPCTL0_MPSIZ_8; + break; + + case 16: + mpsiz = OTG_DOEPCTL0_MPSIZ_16; + break; + + case 32: + mpsiz = OTG_DOEPCTL0_MPSIZ_32; + break; + + case 64: + mpsiz = OTG_DOEPCTL0_MPSIZ_64; + break; + + default: + uerr("Unsupported maxpacket: %d\n", maxpacket); + return -EINVAL; + } + } + + /* For other endpoints, the packet size is in bytes */ + + else + { + mpsiz = (maxpacket << OTG_DOEPCTL_MPSIZ_SHIFT); + } + + /* If the endpoint is already active don't change the endpoint control + * register. + */ + + regaddr = STM32_OTG_DOEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + if ((regval & OTG_DOEPCTL_USBAEP) == 0) + { + if (regval & OTG_DOEPCTL_NAKSTS) + { + regval |= OTG_DOEPCTL_CNAK; + } + + regval &= ~(OTG_DOEPCTL_MPSIZ_MASK | OTG_DOEPCTL_EPTYP_MASK); + regval |= mpsiz; + regval |= (eptype << OTG_DOEPCTL_EPTYP_SHIFT); + regval |= (OTG_DOEPCTL_SD0PID | OTG_DOEPCTL_USBAEP); + stm32_putreg(regval, regaddr); + + /* Save the endpoint configuration */ + + privep->ep.maxpacket = maxpacket; + privep->eptype = eptype; + privep->stalled = false; + } + + /* Enable the interrupt for this endpoint */ + + regval = stm32_getreg(STM32_OTG_DAINTMSK); + regval |= OTG_DAINT_OEP(privep->epphy); + stm32_putreg(regval, STM32_OTG_DAINTMSK); + return OK; +} + +/**************************************************************************** + * Name: stm32_epin_configure + * + * Description: + * Configure an IN endpoint, making it usable + * + * Input Parameters: + * privep - a pointer to an internal endpoint structure + * eptype - The type of the endpoint + * maxpacket - The max packet size of the endpoint + * + ****************************************************************************/ + +static int stm32_epin_configure(FAR struct stm32_ep_s *privep, + uint8_t eptype, uint16_t maxpacket) +{ + uint32_t mpsiz; + uint32_t regaddr; + uint32_t regval; + + usbtrace(TRACE_EPCONFIGURE, privep->epphy); + + /* For EP0, the packet size is encoded */ + + if (privep->epphy == EP0) + { + DEBUGASSERT(eptype == USB_EP_ATTR_XFER_CONTROL); + + /* Map the size in bytes to the encoded value in the register */ + + switch (maxpacket) + { + case 8: + mpsiz = OTG_DIEPCTL0_MPSIZ_8; + break; + + case 16: + mpsiz = OTG_DIEPCTL0_MPSIZ_16; + break; + + case 32: + mpsiz = OTG_DIEPCTL0_MPSIZ_32; + break; + + case 64: + mpsiz = OTG_DIEPCTL0_MPSIZ_64; + break; + + default: + uerr("Unsupported maxpacket: %d\n", maxpacket); + return -EINVAL; + } + } + + /* For other endpoints, the packet size is in bytes */ + + else + { + mpsiz = (maxpacket << OTG_DIEPCTL_MPSIZ_SHIFT); + } + + + /* If the endpoint is already active don't change the endpoint control + * register. + */ + + regaddr = STM32_OTG_DIEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + if ((regval & OTG_DIEPCTL_USBAEP) == 0) + { + if (regval & OTG_DIEPCTL_NAKSTS) + { + regval |= OTG_DIEPCTL_CNAK; + } + + regval &= ~(OTG_DIEPCTL_MPSIZ_MASK | OTG_DIEPCTL_EPTYP_MASK | + OTG_DIEPCTL_TXFNUM_MASK); + regval |= mpsiz; + regval |= (eptype << OTG_DIEPCTL_EPTYP_SHIFT); + regval |= (eptype << OTG_DIEPCTL_TXFNUM_SHIFT); + regval |= (OTG_DIEPCTL_SD0PID | OTG_DIEPCTL_USBAEP); + stm32_putreg(regval, regaddr); + + /* Save the endpoint configuration */ + + privep->ep.maxpacket = maxpacket; + privep->eptype = eptype; + privep->stalled = false; + } + + /* Enable the interrupt for this endpoint */ + + regval = stm32_getreg(STM32_OTG_DAINTMSK); + regval |= OTG_DAINT_IEP(privep->epphy); + stm32_putreg(regval, STM32_OTG_DAINTMSK); + + return OK; +} + +/**************************************************************************** + * Name: stm32_ep_configure + * + * Description: + * Configure endpoint, making it usable + * + * Input Parameters: + * ep - the struct usbdev_ep_s instance obtained from allocep() + * desc - A struct usb_epdesc_s instance describing the endpoint + * last - true if this this last endpoint to be configured. Some hardware + * needs to take special action when all of the endpoints have been + * configured. + * + ****************************************************************************/ + +static int stm32_ep_configure(FAR struct usbdev_ep_s *ep, + FAR const struct usb_epdesc_s *desc, + bool last) +{ + FAR struct stm32_ep_s *privep = (FAR struct stm32_ep_s *)ep; + uint16_t maxpacket; + uint8_t eptype; + int ret; + + usbtrace(TRACE_EPCONFIGURE, privep->epphy); + DEBUGASSERT(desc->addr == ep->eplog); + + /* Initialize EP capabilities */ + + maxpacket = GETUINT16(desc->mxpacketsize); + eptype = desc->attr & USB_EP_ATTR_XFERTYPE_MASK; + + /* Setup Endpoint Control Register */ + + if (privep->isin) + { + ret = stm32_epin_configure(privep, eptype, maxpacket); + } + else + { + ret = stm32_epout_configure(privep, eptype, maxpacket); + } + + return ret; +} + +/**************************************************************************** + * Name: stm32_ep0_configure + * + * Description: + * Reset Usb engine + * + ****************************************************************************/ + +static void stm32_ep0_configure(FAR struct stm32_usbdev_s *priv) +{ + /* Enable EP0 IN and OUT */ + + (void)stm32_epin_configure(&priv->epin[EP0], USB_EP_ATTR_XFER_CONTROL, + CONFIG_USBDEV_EP0_MAXSIZE); + (void)stm32_epout_configure(&priv->epout[EP0], USB_EP_ATTR_XFER_CONTROL, + CONFIG_USBDEV_EP0_MAXSIZE); +} + +/**************************************************************************** + * Name: stm32_epout_disable + * + * Description: + * Diable an OUT endpoint will no longer be used + * + ****************************************************************************/ + +static void stm32_epout_disable(FAR struct stm32_ep_s *privep) +{ + uint32_t regaddr; + uint32_t regval; + irqstate_t flags; + + usbtrace(TRACE_EPDISABLE, privep->epphy); + + /* Is this an IN or an OUT endpoint */ + + /* Before disabling any OUT endpoint, the application must enable + * Global OUT NAK mode in the core. + */ + + flags = enter_critical_section(); + stm32_enablegonak(privep); + + /* Disable the required OUT endpoint by setting the EPDIS and SNAK bits + * int DOECPTL register. + */ + + regaddr = STM32_OTG_DOEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + regval &= ~OTG_DOEPCTL_USBAEP; + regval |= (OTG_DOEPCTL_EPDIS | OTG_DOEPCTL_SNAK); + stm32_putreg(regval, regaddr); + + /* Wait for the EPDISD interrupt which indicates that the OUT + * endpoint is completely disabled. + */ + +#if 0 /* Doesn't happen */ + regaddr = STM32_OTG_DOEPINT(privep->epphy); + while ((stm32_getreg(regaddr) & OTG_DOEPINT_EPDISD) == 0); +#else + /* REVISIT: */ + up_udelay(10); +#endif + + /* Clear the EPDISD interrupt indication */ + + stm32_putreg(OTG_DOEPINT_EPDISD, STM32_OTG_DOEPINT(privep->epphy)); + + /* Then disable the Global OUT NAK mode to continue receiving data + * from other non-disabled OUT endpoints. + */ + + stm32_disablegonak(privep); + + /* Disable endpoint interrupts */ + + regval = stm32_getreg(STM32_OTG_DAINTMSK); + regval &= ~OTG_DAINT_OEP(privep->epphy); + stm32_putreg(regval, STM32_OTG_DAINTMSK); + + /* Cancel any queued read requests */ + + stm32_req_cancel(privep, -ESHUTDOWN); + + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: stm32_epin_disable + * + * Description: + * Disable an IN endpoint when it will no longer be used + * + ****************************************************************************/ + +static void stm32_epin_disable(FAR struct stm32_ep_s *privep) +{ + uint32_t regaddr; + uint32_t regval; + irqstate_t flags; + + usbtrace(TRACE_EPDISABLE, privep->epphy); + + /* After USB reset, the endpoint will already be deactivated by the + * hardware. Trying to disable again will just hang in the wait. + */ + + regaddr = STM32_OTG_DIEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + if ((regval & OTG_DIEPCTL_USBAEP) == 0) + { + return; + } + + /* This INEPNE wait logic is suggested by reference manual, but seems + * to get stuck to infinite loop. + */ + +#if 0 + /* Make sure that there is no pending IPEPNE interrupt (because we are + * to poll this bit below). + */ + + stm32_putreg(OTG_DIEPINT_INEPNE, STM32_OTG_DIEPINT(privep->epphy)); + + /* Set the endpoint in NAK mode */ + + regaddr = STM32_OTG_DIEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + regval &= ~OTG_DIEPCTL_USBAEP; + regval |= (OTG_DIEPCTL_EPDIS | OTG_DIEPCTL_SNAK); + stm32_putreg(regval, regaddr); + + /* Wait for the INEPNE interrupt that indicates that we are now in NAK mode */ + + regaddr = STM32_OTG_DIEPINT(privep->epphy); + while ((stm32_getreg(regaddr) & OTG_DIEPINT_INEPNE) == 0); + + /* Clear the INEPNE interrupt indication */ + + stm32_putreg(OTG_DIEPINT_INEPNE, regaddr); +#endif + + /* Deactivate and disable the endpoint by setting the EPDIS and SNAK bits + * the DIEPCTLx register. + */ + + flags = enter_critical_section(); + regaddr = STM32_OTG_DIEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + regval &= ~OTG_DIEPCTL_USBAEP; + regval |= (OTG_DIEPCTL_EPDIS | OTG_DIEPCTL_SNAK); + stm32_putreg(regval, regaddr); + + /* Wait for the EPDISD interrupt which indicates that the IN + * endpoint is completely disabled. + */ + + regaddr = STM32_OTG_DIEPINT(privep->epphy); + while ((stm32_getreg(regaddr) & OTG_DIEPINT_EPDISD) == 0); + + /* Clear the EPDISD interrupt indication */ + + stm32_putreg(OTG_DIEPINT_EPDISD, stm32_getreg(regaddr)); + + /* Flush any data remaining in the TxFIFO */ + + stm32_txfifo_flush(OTG_GRSTCTL_TXFNUM_D(privep->epphy)); + + /* Disable endpoint interrupts */ + + regval = stm32_getreg(STM32_OTG_DAINTMSK); + regval &= ~OTG_DAINT_IEP(privep->epphy); + stm32_putreg(regval, STM32_OTG_DAINTMSK); + + /* Cancel any queued write requests */ + + stm32_req_cancel(privep, -ESHUTDOWN); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: stm32_ep_disable + * + * Description: + * The endpoint will no longer be used + * + ****************************************************************************/ + +static int stm32_ep_disable(FAR struct usbdev_ep_s *ep) +{ + FAR struct stm32_ep_s *privep = (FAR struct stm32_ep_s *)ep; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + usbtrace(TRACE_EPDISABLE, privep->epphy); + + /* Is this an IN or an OUT endpoint */ + + if (privep->isin) + { + /* Disable the IN endpoint */ + + stm32_epin_disable(privep); + } + else + { + /* Disable the OUT endpoint */ + + stm32_epout_disable(privep); + } + + return OK; +} + +/**************************************************************************** + * Name: stm32_ep_allocreq + * + * Description: + * Allocate an I/O request + * + ****************************************************************************/ + +static FAR struct usbdev_req_s *stm32_ep_allocreq(FAR struct usbdev_ep_s *ep) +{ + FAR struct stm32_req_s *privreq; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return NULL; + } +#endif + + usbtrace(TRACE_EPALLOCREQ, ((FAR struct stm32_ep_s *)ep)->epphy); + + privreq = (FAR struct stm32_req_s *)kmm_malloc(sizeof(struct stm32_req_s)); + if (!privreq) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_ALLOCFAIL), 0); + return NULL; + } + + memset(privreq, 0, sizeof(struct stm32_req_s)); + return &privreq->req; +} + +/**************************************************************************** + * Name: stm32_ep_freereq + * + * Description: + * Free an I/O request + * + ****************************************************************************/ + +static void stm32_ep_freereq(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req) +{ + FAR struct stm32_req_s *privreq = (FAR struct stm32_req_s *)req; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep || !req) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return; + } +#endif + + usbtrace(TRACE_EPFREEREQ, ((FAR struct stm32_ep_s *)ep)->epphy); + kmm_free(privreq); +} + +/**************************************************************************** + * Name: stm32_ep_allocbuffer + * + * Description: + * Allocate an I/O buffer + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV_DMA +static void *stm32_ep_allocbuffer(FAR struct usbdev_ep_s *ep, unsigned bytes) +{ + usbtrace(TRACE_EPALLOCBUFFER, privep->epphy); + +#ifdef CONFIG_USBDEV_DMAMEMORY + return usbdev_dma_alloc(bytes); +#else + return kmm_malloc(bytes); +#endif +} +#endif + +/**************************************************************************** + * Name: stm32_ep_freebuffer + * + * Description: + * Free an I/O buffer + * + ****************************************************************************/ + +#ifdef CONFIG_USBDEV_DMA +static void stm32_ep_freebuffer(FAR struct usbdev_ep_s *ep, FAR void *buf) +{ + usbtrace(TRACE_EPFREEBUFFER, privep->epphy); + +#ifdef CONFIG_USBDEV_DMAMEMORY + usbdev_dma_free(buf); +#else + kmm_free(buf); +#endif +} +#endif + +/**************************************************************************** + * Name: stm32_ep_submit + * + * Description: + * Submit an I/O request to the endpoint + * + ****************************************************************************/ + +static int stm32_ep_submit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req) +{ + FAR struct stm32_req_s *privreq = (FAR struct stm32_req_s *)req; + FAR struct stm32_ep_s *privep = (FAR struct stm32_ep_s *)ep; + FAR struct stm32_usbdev_s *priv; + irqstate_t flags; + int ret = OK; + + /* Some sanity checking */ + +#ifdef CONFIG_DEBUG_FEATURES + if (!req || !req->callback || !req->buf || !ep) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + uinfo("req=%p callback=%p buf=%p ep=%p\n", req, req->callback, req->buf, ep); + return -EINVAL; + } +#endif + + usbtrace(TRACE_EPSUBMIT, privep->epphy); + priv = privep->dev; + +#ifdef CONFIG_DEBUG_FEATURES + if (!priv->driver) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOTCONFIGURED), priv->usbdev.speed); + return -ESHUTDOWN; + } +#endif + + /* Handle the request from the class driver */ + + req->result = -EINPROGRESS; + req->xfrd = 0; + + /* Disable Interrupts */ + + flags = enter_critical_section(); + + /* If we are stalled, then drop all requests on the floor */ + + if (privep->stalled) + { + ret = -EBUSY; + } + else + { + /* Add the new request to the request queue for the endpoint. */ + + if (stm32_req_addlast(privep, privreq) && !privep->active) + { + /* If a request was added to an IN endpoint, then attempt to send + * the request data buffer now. + */ + + if (privep->isin) + { + usbtrace(TRACE_INREQQUEUED(privep->epphy), privreq->req.len); + + /* If the endpoint is not busy with another write request, + * then process the newly received write request now. + */ + + if (!privep->active) + { + stm32_epin_request(priv, privep); + } + } + + /* If the request was added to an OUT endpoint, then attempt to + * setup a read into the request data buffer now (this will, of + * course, fail if there is already a read in place). + */ + + else + { + usbtrace(TRACE_OUTREQQUEUED(privep->epphy), privreq->req.len); + stm32_epout_request(priv, privep); + } + } + } + + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Name: stm32_ep_cancel + * + * Description: + * Cancel an I/O request previously sent to an endpoint + * + ****************************************************************************/ + +static int stm32_ep_cancel(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *req) +{ + FAR struct stm32_ep_s *privep = (FAR struct stm32_ep_s *)ep; + irqstate_t flags; + +#ifdef CONFIG_DEBUG_FEATURES + if (!ep || !req) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + usbtrace(TRACE_EPCANCEL, privep->epphy); + + flags = enter_critical_section(); + + /* FIXME: if the request is the first, then we need to flush the EP + * otherwise just remove it from the list + * + * but ... all other implementations cancel all requests ... + */ + + stm32_req_cancel(privep, -ESHUTDOWN); + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_epout_setstall + * + * Description: + * Stall an OUT endpoint + * + ****************************************************************************/ + +static int stm32_epout_setstall(FAR struct stm32_ep_s *privep) +{ +#if 1 + /* This implementation follows the requirements from the STM32 F4 reference + * manual. + */ + + uint32_t regaddr; + uint32_t regval; + + /* Put the core in the Global OUT NAK mode */ + + stm32_enablegonak(privep); + + /* Disable and STALL the OUT endpoint by setting the EPDIS and STALL bits + * in the DOECPTL register. + */ + + regaddr = STM32_OTG_DOEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + regval |= (OTG_DOEPCTL_EPDIS | OTG_DOEPCTL_STALL); + stm32_putreg(regval, regaddr); + + /* Wait for the EPDISD interrupt which indicates that the OUT + * endpoint is completely disabled. + */ + +#if 0 /* Doesn't happen */ + regaddr = STM32_OTG_DOEPINT(privep->epphy); + while ((stm32_getreg(regaddr) & OTG_DOEPINT_EPDISD) == 0); +#else + /* REVISIT: */ + up_udelay(10); +#endif + + /* Disable Global OUT NAK mode */ + + stm32_disablegonak(privep); + + /* The endpoint is now stalled */ + + privep->stalled = true; + return OK; +#else + /* This implementation follows the STMicro code example. */ + /* REVISIT: */ + + uint32_t regaddr; + uint32_t regval; + + /* Stall the OUT endpoint by setting the STALL bit in the DOECPTL register. */ + + regaddr = STM32_OTG_DOEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + regval |= OTG_DOEPCTL_STALL; + stm32_putreg(regval, regaddr); + + /* The endpoint is now stalled */ + + privep->stalled = true; + return OK; +#endif +} + +/**************************************************************************** + * Name: stm32_epin_setstall + * + * Description: + * Stall an IN endpoint + * + ****************************************************************************/ + +static int stm32_epin_setstall(FAR struct stm32_ep_s *privep) +{ + uint32_t regaddr; + uint32_t regval; + + /* Get the IN endpoint device control register */ + + regaddr = STM32_OTG_DIEPCTL(privep->epphy); + regval = stm32_getreg(regaddr); + + /* Then stall the endpoint */ + + regval |= OTG_DIEPCTL_STALL; + stm32_putreg(regval, regaddr); + + /* The endpoint is now stalled */ + + privep->stalled = true; + return OK; +} + +/**************************************************************************** + * Name: stm32_ep_setstall + * + * Description: + * Stall an endpoint + * + ****************************************************************************/ + +static int stm32_ep_setstall(FAR struct stm32_ep_s *privep) +{ + usbtrace(TRACE_EPSTALL, privep->epphy); + + /* Is this an IN endpoint? */ + + if (privep->isin == 1) + { + return stm32_epin_setstall(privep); + } + else + { + return stm32_epout_setstall(privep); + } +} + +/**************************************************************************** + * Name: stm32_ep_clrstall + * + * Description: + * Resume a stalled endpoint + * + ****************************************************************************/ + +static int stm32_ep_clrstall(FAR struct stm32_ep_s *privep) +{ + uint32_t regaddr; + uint32_t regval; + uint32_t stallbit; + uint32_t data0bit; + + usbtrace(TRACE_EPRESUME, privep->epphy); + + /* Is this an IN endpoint? */ + + if (privep->isin == 1) + { + /* Clear the stall bit in the IN endpoint device control register */ + + regaddr = STM32_OTG_DIEPCTL(privep->epphy); + stallbit = OTG_DIEPCTL_STALL; + data0bit = OTG_DIEPCTL_SD0PID; + } + else + { + /* Clear the stall bit in the IN endpoint device control register */ + + regaddr = STM32_OTG_DOEPCTL(privep->epphy); + stallbit = OTG_DOEPCTL_STALL; + data0bit = OTG_DOEPCTL_SD0PID; + } + + /* Clear the stall bit */ + + regval = stm32_getreg(regaddr); + regval &= ~stallbit; + + /* Set the DATA0 pid for interrupt and bulk endpoints */ + + if (privep->eptype == USB_EP_ATTR_XFER_INT || + privep->eptype == USB_EP_ATTR_XFER_BULK) + { + /* Writing this bit sets the DATA0 PID */ + + regval |= data0bit; + } + + stm32_putreg(regval, regaddr); + + /* The endpoint is no longer stalled */ + + privep->stalled = false; + return OK; +} + +/**************************************************************************** + * Name: stm32_ep_stall + * + * Description: + * Stall or resume an endpoint + * + ****************************************************************************/ + +static int stm32_ep_stall(FAR struct usbdev_ep_s *ep, bool resume) +{ + FAR struct stm32_ep_s *privep = (FAR struct stm32_ep_s *)ep; + irqstate_t flags; + int ret; + + /* Set or clear the stall condition as requested */ + + flags = enter_critical_section(); + if (resume) + { + ret = stm32_ep_clrstall(privep); + } + else + { + ret = stm32_ep_setstall(privep); + } + leave_critical_section(flags); + + return ret; +} + +/**************************************************************************** + * Name: stm32_ep0_stall + * + * Description: + * Stall endpoint 0 + * + ****************************************************************************/ + +static void stm32_ep0_stall(FAR struct stm32_usbdev_s *priv) +{ + stm32_epin_setstall(&priv->epin[EP0]); + stm32_epout_setstall(&priv->epout[EP0]); + priv->stalled = true; + stm32_ep0out_ctrlsetup(priv); +} + +/**************************************************************************** + * Device operations + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_ep_alloc + * + * Description: + * Allocate an endpoint matching the parameters. + * + * Input Parameters: + * eplog - 7-bit logical endpoint number (direction bit ignored). Zero means + * that any endpoint matching the other requirements will suffice. The + * assigned endpoint can be found in the eplog field. + * in - true: IN (device-to-host) endpoint requested + * eptype - Endpoint type. One of {USB_EP_ATTR_XFER_ISOC, USB_EP_ATTR_XFER_BULK, + * USB_EP_ATTR_XFER_INT} + * + ****************************************************************************/ + +static FAR struct usbdev_ep_s *stm32_ep_alloc(FAR struct usbdev_s *dev, + uint8_t eplog, bool in, + uint8_t eptype) +{ + FAR struct stm32_usbdev_s *priv = (FAR struct stm32_usbdev_s *)dev; + uint8_t epavail; + irqstate_t flags; + int epphy; + int epno = 0; + + usbtrace(TRACE_DEVALLOCEP, (uint16_t)eplog); + + /* Ignore any direction bits in the logical address */ + + epphy = USB_EPNO(eplog); + + /* Get the set of available endpoints depending on the direction */ + + flags = enter_critical_section(); + epavail = priv->epavail[in]; + + /* A physical address of 0 means that any endpoint will do */ + + if (epphy > 0) + { + /* Otherwise, we will return the endpoint structure only for the requested + * 'logical' endpoint. All of the other checks will still be performed. + * + * First, verify that the logical endpoint is in the range supported by + * by the hardware. + */ + + if (epphy >= STM32_NENDPOINTS) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BADEPNO), (uint16_t)epphy); + return NULL; + } + + /* Remove all of the candidate endpoints from the bitset except for the + * this physical endpoint number. + */ + + epavail &= (1 << epphy); + } + + /* Is there an available endpoint? */ + + if (epavail) + { + /* Yes.. Select the lowest numbered endpoint in the set of available + * endpoints. + */ + + for (epno = 1; epno < STM32_NENDPOINTS; epno++) + { + uint8_t bit = 1 << epno; + if ((epavail & bit) != 0) + { + /* Mark the endpoint no longer available */ + + priv->epavail[in] &= ~(1 << epno); + + /* And return the pointer to the standard endpoint structure */ + + leave_critical_section(flags); + return in ? &priv->epin[epno].ep : &priv->epout[epno].ep; + } + } + + /* We should not get here */ + } + + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_NOEP), (uint16_t)eplog); + leave_critical_section(flags); + return NULL; +} + +/**************************************************************************** + * Name: stm32_ep_free + * + * Description: + * Free the previously allocated endpoint + * + ****************************************************************************/ + +static void stm32_ep_free(FAR struct usbdev_s *dev, FAR struct usbdev_ep_s *ep) +{ + FAR struct stm32_usbdev_s *priv = (FAR struct stm32_usbdev_s *)dev; + FAR struct stm32_ep_s *privep = (FAR struct stm32_ep_s *)ep; + irqstate_t flags; + + usbtrace(TRACE_DEVFREEEP, (uint16_t)privep->epphy); + + if (priv && privep) + { + /* Mark the endpoint as available */ + + flags = enter_critical_section(); + priv->epavail[privep->isin] |= (1 << privep->epphy); + leave_critical_section(flags); + } +} + +/**************************************************************************** + * Name: stm32_getframe + * + * Description: + * Returns the current frame number + * + ****************************************************************************/ + +static int stm32_getframe(struct usbdev_s *dev) +{ + uint32_t regval; + + usbtrace(TRACE_DEVGETFRAME, 0); + + /* Return the last frame number of the last SOF detected by the hardware */ + + regval = stm32_getreg(STM32_OTG_DSTS); + return (int)((regval & OTG_DSTS_SOFFN_MASK) >> OTG_DSTS_SOFFN_SHIFT); +} + +/**************************************************************************** + * Name: stm32_wakeup + * + * Description: + * Exit suspend mode. + * + ****************************************************************************/ + +static int stm32_wakeup(struct usbdev_s *dev) +{ + FAR struct stm32_usbdev_s *priv = (FAR struct stm32_usbdev_s *)dev; + uint32_t regval; + irqstate_t flags; + + usbtrace(TRACE_DEVWAKEUP, 0); + + /* Is wakeup enabled? */ + + flags = enter_critical_section(); + if (priv->wakeup) + { + /* Yes... is the core suspended? */ + + regval = stm32_getreg(STM32_OTG_DSTS); + if ((regval & OTG_DSTS_SUSPSTS) != 0) + { + /* Re-start the PHY clock and un-gate USB core clock (HCLK) */ + +#ifdef CONFIG_USBDEV_LOWPOWER + regval = stm32_getreg(STM32_OTG_PCGCCTL); + regval &= ~(OTG_PCGCCTL_STPPCLK | OTG_PCGCCTL_GATEHCLK); + stm32_putreg(regval, STM32_OTG_PCGCCTL); +#endif + /* Activate Remote wakeup signaling */ + + regval = stm32_getreg(STM32_OTG_DCTL); + regval |= OTG_DCTL_RWUSIG; + stm32_putreg(regval, STM32_OTG_DCTL); + up_mdelay(5); + regval &= ~OTG_DCTL_RWUSIG; + stm32_putreg(regval, STM32_OTG_DCTL); + } + } + + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_selfpowered + * + * Description: + * Sets/clears the device self-powered feature + * + ****************************************************************************/ + +static int stm32_selfpowered(struct usbdev_s *dev, bool selfpowered) +{ + FAR struct stm32_usbdev_s *priv = (FAR struct stm32_usbdev_s *)dev; + + usbtrace(TRACE_DEVSELFPOWERED, (uint16_t)selfpowered); + +#ifdef CONFIG_DEBUG_FEATURES + if (!dev) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -ENODEV; + } +#endif + + priv->selfpowered = selfpowered; + return OK; +} + +/**************************************************************************** + * Name: stm32_pullup + * + * Description: + * Software-controlled connect to/disconnect from USB host + * + ****************************************************************************/ + +static int stm32_pullup(struct usbdev_s *dev, bool enable) +{ + uint32_t regval; + + usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); + + irqstate_t flags = enter_critical_section(); + regval = stm32_getreg(STM32_OTG_DCTL); + if (enable) + { + /* Connect the device by clearing the soft disconnect bit in the DCTL + * register + */ + + regval &= ~OTG_DCTL_SDIS; + } + else + { + /* Connect the device by setting the soft disconnect bit in the DCTL + * register + */ + + regval |= OTG_DCTL_SDIS; + } + + stm32_putreg(regval, STM32_OTG_DCTL); + leave_critical_section(flags); + return OK; +} + +/**************************************************************************** + * Name: stm32_setaddress + * + * Description: + * Set the devices USB address + * + ****************************************************************************/ + +static void stm32_setaddress(struct stm32_usbdev_s *priv, uint16_t address) +{ + uint32_t regval; + + /* Set the device address in the DCFG register */ + + regval = stm32_getreg(STM32_OTG_DCFG); + regval &= ~OTG_DCFG_DAD_MASK; + regval |= ((uint32_t)address << OTG_DCFG_DAD_SHIFT); + stm32_putreg(regval, STM32_OTG_DCFG); + + /* Are we now addressed? (i.e., do we have a non-NULL device + * address?) + */ + + if (address != 0) + { + priv->devstate = DEVSTATE_ADDRESSED; + priv->addressed = true; + } + else + { + priv->devstate = DEVSTATE_DEFAULT; + priv->addressed = false; + } +} + +/**************************************************************************** + * Name: stm32_txfifo_flush + * + * Description: + * Flush the specific TX fifo. + * + ****************************************************************************/ + +static int stm32_txfifo_flush(uint32_t txfnum) +{ + uint32_t regval; + uint32_t timeout; + + /* Initiate the TX FIFO flush operation */ + + regval = OTG_GRSTCTL_TXFFLSH | txfnum; + stm32_putreg(regval, STM32_OTG_GRSTCTL); + + /* Wait for the FLUSH to complete */ + + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) + { + regval = stm32_getreg(STM32_OTG_GRSTCTL); + if ((regval & OTG_GRSTCTL_TXFFLSH) == 0) + { + break; + } + } + + /* Wait for 3 PHY Clocks */ + + up_udelay(3); + return OK; +} + +/**************************************************************************** + * Name: stm32_rxfifo_flush + * + * Description: + * Flush the RX fifo. + * + ****************************************************************************/ + +static int stm32_rxfifo_flush(void) +{ + uint32_t regval; + uint32_t timeout; + + /* Initiate the RX FIFO flush operation */ + + stm32_putreg(OTG_GRSTCTL_RXFFLSH, STM32_OTG_GRSTCTL); + + /* Wait for the FLUSH to complete */ + + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) + { + regval = stm32_getreg(STM32_OTG_GRSTCTL); + if ((regval & OTG_GRSTCTL_RXFFLSH) == 0) + { + break; + } + } + + /* Wait for 3 PHY Clocks */ + + up_udelay(3); + return OK; +} + +/**************************************************************************** + * Name: stm32_swinitialize + * + * Description: + * Initialize all driver data structures. + * + ****************************************************************************/ + +static void stm32_swinitialize(FAR struct stm32_usbdev_s *priv) +{ + FAR struct stm32_ep_s *privep; + int i; + + /* Initialize the device state structure */ + + memset(priv, 0, sizeof(struct stm32_usbdev_s)); + + priv->usbdev.ops = &g_devops; + priv->usbdev.ep0 = &priv->epin[EP0].ep; + + priv->epavail[0] = STM32_EP_AVAILABLE; + priv->epavail[1] = STM32_EP_AVAILABLE; + + priv->epin[EP0].ep.priv = priv; + priv->epout[EP0].ep.priv = priv; + + /* Initialize the endpoint lists */ + + for (i = 0; i < STM32_NENDPOINTS; i++) + { + /* Set endpoint operations, reference to driver structure (not + * really necessary because there is only one controller), and + * the physical endpoint number (which is just the index to the + * endpoint). + */ + + privep = &priv->epin[i]; + privep->ep.ops = &g_epops; + privep->dev = priv; + privep->isin = 1; + + /* The index, i, is the physical endpoint address; Map this + * to a logical endpoint address usable by the class driver. + */ + + privep->epphy = i; + privep->ep.eplog = STM32_EPPHYIN2LOG(i); + + /* Control until endpoint is activated */ + + privep->eptype = USB_EP_ATTR_XFER_CONTROL; + privep->ep.maxpacket = CONFIG_USBDEV_EP0_MAXSIZE; + } + + /* Initialize the endpoint lists */ + + for (i = 0; i < STM32_NENDPOINTS; i++) + { + /* Set endpoint operations, reference to driver structure (not + * really necessary because there is only one controller), and + * the physical endpoint number (which is just the index to the + * endpoint). + */ + + privep = &priv->epout[i]; + privep->ep.ops = &g_epops; + privep->dev = priv; + + /* The index, i, is the physical endpoint address; Map this + * to a logical endpoint address usable by the class driver. + */ + + privep->epphy = i; + privep->ep.eplog = STM32_EPPHYOUT2LOG(i); + + /* Control until endpoint is activated */ + + privep->eptype = USB_EP_ATTR_XFER_CONTROL; + privep->ep.maxpacket = CONFIG_USBDEV_EP0_MAXSIZE; + } +} + +/**************************************************************************** + * Name: stm32_hwinitialize + * + * Description: + * Configure the OTG core for operation. + * + ****************************************************************************/ + +static void stm32_hwinitialize(FAR struct stm32_usbdev_s *priv) +{ + uint32_t regval; + uint32_t timeout; + uint32_t address; + int i; + + /* At start-up the core is in FS/HS mode. */ + + /* Disable global interrupts by clearing the GINTMASK bit in the GAHBCFG + * register; Set the TXFELVL bit in the GAHBCFG register so that TxFIFO + * interrupts will occur when the TxFIFO is truly empty (not just half full). + */ + + stm32_putreg(OTG_GAHBCFG_TXFELVL, STM32_OTG_GAHBCFG); + +#if defined(CONFIG_STM32F7_OTGHS) + /* Set the PHYSEL bit in the GUSBCFG register to select the OTG HS serial + * transceiver: "This bit is always 1 with write-only access" + */ + + regval = stm32_getreg(STM32_OTG_GUSBCFG); + regval |= OTG_GUSBCFG_PHYSEL; + stm32_putreg(regval, STM32_OTG_GUSBCFG); +#endif + + /* Common USB OTG core initialization */ + /* Reset after a PHY select and set Host mode. First, wait for AHB master + * IDLE state. + */ + + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) + { + up_udelay(3); + regval = stm32_getreg(STM32_OTG_GRSTCTL); + if ((regval & OTG_GRSTCTL_AHBIDL) != 0) + { + break; + } + } + + /* Then perform the core soft reset. */ + + stm32_putreg(OTG_GRSTCTL_CSRST, STM32_OTG_GRSTCTL); + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) + { + regval = stm32_getreg(STM32_OTG_GRSTCTL); + if ((regval & OTG_GRSTCTL_CSRST) == 0) + { + break; + } + } + + /* Wait for 3 PHY Clocks */ + + up_udelay(3); + + /* Deactivate the power down */ + + + /* Detection Enable when set + */ + + regval = OTG_GCCFG_PWRDWN; + +# ifdef CONFIG_USBDEV_VBUSSENSING + regval |= OTG_GCCFG_VBDEN; +# endif + + + stm32_putreg(regval, STM32_OTG_GCCFG); + up_mdelay(20); + + /* When VBUS sensing is not used we + * need to force the B session valid + */ + + +# ifndef CONFIG_USBDEV_VBUSSENSING + regval = stm32_getreg(STM32_OTG_GOTGCTL); + regval |= (OTG_GOTGCTL_BVALOEN | OTG_GOTGCTL_BVALOVAL); + stm32_putreg(regval, STM32_OTG_GOTGCTL); +# endif + + + /* Force Device Mode */ + + regval = stm32_getreg(STM32_OTG_GUSBCFG); + regval &= ~OTG_GUSBCFG_FHMOD; + regval |= OTG_GUSBCFG_FDMOD; + stm32_putreg(regval, STM32_OTG_GUSBCFG); + up_mdelay(50); + + /* Initialize device mode */ + /* Restart the PHY Clock */ + + stm32_putreg(0, STM32_OTG_PCGCCTL); + + /* Device configuration register */ + + regval = stm32_getreg(STM32_OTG_DCFG); + regval &= ~OTG_DCFG_PFIVL_MASK; + regval |= OTG_DCFG_PFIVL_80PCT; + stm32_putreg(regval, STM32_OTG_DCFG); + + /* Set full speed PHY */ + + regval = stm32_getreg(STM32_OTG_DCFG); + regval &= ~OTG_DCFG_DSPD_MASK; + regval |= OTG_DCFG_DSPD_FS; + stm32_putreg(regval, STM32_OTG_DCFG); + + /* Set Rx FIFO size */ + + stm32_putreg(STM32_RXFIFO_WORDS, STM32_OTG_GRXFSIZ); + +#if STM32_NENDPOINTS > 0 + address = STM32_RXFIFO_WORDS; + regval = (address << OTG_DIEPTXF0_TX0FD_SHIFT) | + (STM32_EP0_TXFIFO_WORDS << OTG_DIEPTXF0_TX0FSA_SHIFT); + stm32_putreg(regval, STM32_OTG_DIEPTXF0); +#endif + +#if STM32_NENDPOINTS > 1 + address += STM32_EP0_TXFIFO_WORDS; + regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | + (STM32_EP1_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); + stm32_putreg(regval, STM32_OTG_DIEPTXF(1)); +#endif + +#if STM32_NENDPOINTS > 2 + address += STM32_EP1_TXFIFO_WORDS; + regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | + (STM32_EP2_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); + stm32_putreg(regval, STM32_OTG_DIEPTXF(2)); +#endif + +#if STM32_NENDPOINTS > 3 + address += STM32_EP2_TXFIFO_WORDS; + regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | + (STM32_EP3_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); + stm32_putreg(regval, STM32_OTG_DIEPTXF(3)); +#endif + +#if STM32_NENDPOINTS > 4 + address += STM32_EP3_TXFIFO_WORDS; + regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | + (STM32_EP4_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); + stm32_putreg(regval, STM32_OTG_DIEPTXF(4)); +#endif + +#if STM32_NENDPOINTS > 5 + address += STM32_EP4_TXFIFO_WORDS; + regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | + (STM32_EP5_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); + stm32_putreg(regval, STM32_OTG_DIEPTXF(5)); +#endif + +#if STM32_NENDPOINTS > 6 + address += STM32_EP5_TXFIFO_WORDS; + regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | + (STM32_EP6_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); + stm32_putreg(regval, STM32_OTG_DIEPTXF(6)); +#endif + +#if STM32_NENDPOINTS > 7 + address += STM32_EP6_TXFIFO_WORDS; + regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | + (STM32_EP7_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); + stm32_putreg(regval, STM32_OTG_DIEPTXF(7)); +#endif + +#if STM32_NENDPOINTS > 8 + address += STM32_EP7_TXFIFO_WORDS; + regval = (address << OTG_DIEPTXF_INEPTXSA_SHIFT) | + (STM32_EP8_TXFIFO_WORDS << OTG_DIEPTXF_INEPTXFD_SHIFT); + stm32_putreg(regval, STM32_OTG_DIEPTXF(8)); +#endif + + /* Flush the FIFOs */ + + stm32_txfifo_flush(OTG_GRSTCTL_TXFNUM_DALL); + stm32_rxfifo_flush(); + + /* Clear all pending Device Interrupts */ + + stm32_putreg(0, STM32_OTG_DIEPMSK); + stm32_putreg(0, STM32_OTG_DOEPMSK); + stm32_putreg(0, STM32_OTG_DIEPEMPMSK); + stm32_putreg(0xffffffff, STM32_OTG_DAINT); + stm32_putreg(0, STM32_OTG_DAINTMSK); + + /* Configure all IN endpoints */ + + for (i = 0; i < STM32_NENDPOINTS; i++) + { + regval = stm32_getreg(STM32_OTG_DIEPCTL(i)); + if ((regval & OTG_DIEPCTL_EPENA) != 0) + { + /* The endpoint is already enabled */ + + regval = OTG_DIEPCTL_EPENA | OTG_DIEPCTL_SNAK; + } + else + { + regval = 0; + } + + stm32_putreg(regval, STM32_OTG_DIEPCTL(i)); + stm32_putreg(0, STM32_OTG_DIEPTSIZ(i)); + stm32_putreg(0xff, STM32_OTG_DIEPINT(i)); + } + + /* Configure all OUT endpoints */ + + for (i = 0; i < STM32_NENDPOINTS; i++) + { + regval = stm32_getreg(STM32_OTG_DOEPCTL(i)); + if ((regval & OTG_DOEPCTL_EPENA) != 0) + { + /* The endpoint is already enabled */ + + regval = OTG_DOEPCTL_EPENA | OTG_DOEPCTL_SNAK; + } + else + { + regval = 0; + } + + stm32_putreg(regval, STM32_OTG_DOEPCTL(i)); + stm32_putreg(0, STM32_OTG_DOEPTSIZ(i)); + stm32_putreg(0xff, STM32_OTG_DOEPINT(i)); + } + + /* Disable all interrupts. */ + + stm32_putreg(0, STM32_OTG_GINTMSK); + + /* Clear any pending USB_OTG Interrupts */ + + stm32_putreg(0xffffffff, STM32_OTG_GOTGINT); + + /* Clear any pending interrupts */ + + stm32_putreg(0xbfffffff, STM32_OTG_GINTSTS); + +#if defined(CONFIG_STM32F7_OTGHS) + /* Disable the ULPI Clock enable in RCC AHB1 Register. This must + * be done because if both the ULPI and the FS PHY clock enable bits + * are set at the same time, the ARM never awakens from WFI due to + * some bug / errata in the chip. + */ + + regval = stm32_getreg(STM32_RCC_AHB1LPENR); + regval &= ~RCC_AHB1ENR_OTGULPIEN; + stm32_putreg(regval, STM32_RCC_AHB1LPENR); +#endif + + /* Enable the interrupts in the INTMSK */ + + regval = (OTG_GINT_RXFLVL | OTG_GINT_USBSUSP | OTG_GINT_ENUMDNE | + OTG_GINT_IEP | OTG_GINT_OEP | OTG_GINT_USBRST); + +#ifdef CONFIG_USBDEV_ISOCHRONOUS + regval |= (OTG_GINT_IISOIXFR | OTG_GINT_IISOOXFR); +#endif + +#ifdef CONFIG_USBDEV_SOFINTERRUPT + regval |= OTG_GINT_SOF; +#endif + +#ifdef CONFIG_USBDEV_VBUSSENSING + regval |= (OTG_GINT_OTG | OTG_GINT_SRQ); +#endif + +#ifdef CONFIG_DEBUG_USB + regval |= OTG_GINT_MMIS; +#endif + + stm32_putreg(regval, STM32_OTG_GINTMSK); + + /* Enable the USB global interrupt by setting GINTMSK in the global OTG + * AHB configuration register; Set the TXFELVL bit in the GAHBCFG + * register so that TxFIFO interrupts will occur when the TxFIFO is truly + * empty (not just half full). + */ + + stm32_putreg(OTG_GAHBCFG_GINTMSK | OTG_GAHBCFG_TXFELVL, + STM32_OTG_GAHBCFG); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_usbinitialize + * + * Description: + * Initialize USB hardware. + * + * Assumptions: + * - This function is called very early in the initialization sequence + * - PLL and GIO pin initialization is not performed here but should been in + * the low-level boot logic: PLL1 must be configured for operation at 48MHz + * and P0.23 and PO.31 in PINSEL1 must be configured for Vbus and USB connect + * LED. + * + ****************************************************************************/ + +void up_usbinitialize(void) +{ + /* At present, there is only a single OTG device support. Hence it is + * pre-allocated as g_otghsdev. However, in most code, the private data + * structure will be referenced using the 'priv' pointer (rather than the + * global data) in order to simplify any future support for multiple + * devices. + */ + + FAR struct stm32_usbdev_s *priv = &g_otghsdev; + int ret; + + usbtrace(TRACE_DEVINIT, 0); + + /* Here we assume that: + * + * 1. GPIOA and OTG peripheral clocking has already been enabled as part + * of the boot sequence. + * 2. Board-specific logic has already enabled other board specific GPIOs + * for things like soft pull-up, VBUS sensing, power controls, and over- + * current detection. + */ + + /* Configure OTG alternate function pins + */ + + stm32_configgpio(GPIO_OTG_DM); + stm32_configgpio(GPIO_OTG_DP); + stm32_configgpio(GPIO_OTG_ID); /* Only needed for OTG */ + + /* SOF output pin configuration is configurable. */ + +#ifdef CONFIG_STM32F7_OTG_SOFOUTPUT + stm32_configgpio(GPIO_OTG_SOF); +#endif + + /* Uninitialize the hardware so that we know that we are starting from a + * known state. */ + + up_usbuninitialize(); + + /* Initialie the driver data structure */ + + stm32_swinitialize(priv); + + /* Attach the OTG interrupt handler */ + + ret = irq_attach(STM32_IRQ_OTG, stm32_usbinterrupt); + if (ret < 0) + { + uerr("irq_attach failed\n", ret); + goto errout; + } + + /* Initialize the USB OTG core */ + + stm32_hwinitialize(priv); + + /* Disconnect device */ + + stm32_pullup(&priv->usbdev, false); + + /* Reset/Re-initialize the USB hardware */ + + stm32_usbreset(priv); + + /* Enable USB controller interrupts at the NVIC */ + + up_enable_irq(STM32_IRQ_OTG); + +#ifdef CONFIG_ARCH_IRQPRIO + /* Set the interrupt priority */ + + up_prioritize_irq(STM32_IRQ_OTG, CONFIG_OTG_PRI); +#endif + return; + +errout: + up_usbuninitialize(); +} + +/**************************************************************************** + * Name: up_usbuninitialize + ****************************************************************************/ + +void up_usbuninitialize(void) +{ + /* At present, there is only a single OTG device support. Hence it is + * pre-allocated as g_otghsdev. However, in most code, the private data + * structure will be referenced using the 'priv' pointer (rather than the + * global data) in order to simplify any future support for multiple devices. + */ + + FAR struct stm32_usbdev_s *priv = &g_otghsdev; + irqstate_t flags; + int i; + + usbtrace(TRACE_DEVUNINIT, 0); + + if (priv->driver) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVERREGISTERED), 0); + usbdev_unregister(priv->driver); + } + + /* Disconnect device */ + + flags = enter_critical_section(); + stm32_pullup(&priv->usbdev, false); + priv->usbdev.speed = USB_SPEED_UNKNOWN; + + /* Disable and detach IRQs */ + + up_disable_irq(STM32_IRQ_OTG); + irq_detach(STM32_IRQ_OTG); + + /* Disable all endpoint interrupts */ + + for (i = 0; i < STM32_NENDPOINTS; i++) + { + stm32_putreg(0xff, STM32_OTG_DIEPINT(i)); + stm32_putreg(0xff, STM32_OTG_DOEPINT(i)); + } + + stm32_putreg(0, STM32_OTG_DIEPMSK); + stm32_putreg(0, STM32_OTG_DOEPMSK); + stm32_putreg(0, STM32_OTG_DIEPEMPMSK); + stm32_putreg(0, STM32_OTG_DAINTMSK); + stm32_putreg(0xffffffff, STM32_OTG_DAINT); + + /* Flush the FIFOs */ + + stm32_txfifo_flush(OTG_GRSTCTL_TXFNUM_DALL); + stm32_rxfifo_flush(); + + /* TODO: Turn off USB power and clocking */ + + priv->devstate = DEVSTATE_DEFAULT; + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: usbdev_register + * + * Description: + * Register a USB device class driver. The class driver's bind() method will be + * called to bind it to a USB device driver. + * + ****************************************************************************/ + +int usbdev_register(struct usbdevclass_driver_s *driver) +{ + /* At present, there is only a single OTG device support. Hence it is + * pre-allocated as g_otghsdev. However, in most code, the private data + * structure will be referenced using the 'priv' pointer (rather than the + * global data) in order to simplify any future support for multiple devices. + */ + + FAR struct stm32_usbdev_s *priv = &g_otghsdev; + int ret; + + usbtrace(TRACE_DEVREGISTER, 0); + +#ifdef CONFIG_DEBUG_FEATURES + if (!driver || !driver->ops->bind || !driver->ops->unbind || + !driver->ops->disconnect || !driver->ops->setup) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } + + if (priv->driver) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_DRIVER), 0); + return -EBUSY; + } +#endif + + /* First hook up the driver */ + + priv->driver = driver; + + /* Then bind the class driver */ + + ret = CLASS_BIND(driver, &priv->usbdev); + if (ret) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_BINDFAILED), (uint16_t)-ret); + priv->driver = NULL; + } + else + { + /* Enable USB controller interrupts */ + + up_enable_irq(STM32_IRQ_OTG); + + /* FIXME: nothing seems to call DEV_CONNECT(), but we need to set + * the RS bit to enable the controller. It kind of makes sense + * to do this after the class has bound to us... + * GEN: This bug is really in the class driver. It should make the + * soft connect when it is ready to be enumerated. I have added + * that logic to the class drivers but left this logic here. + */ + + stm32_pullup(&priv->usbdev, true); + priv->usbdev.speed = USB_SPEED_FULL; + } + + return ret; +} + +/**************************************************************************** + * Name: usbdev_unregister + * + * Description: + * Un-register usbdev class driver.If the USB device is connected to a USB host, + * it will first disconnect(). The driver is also requested to unbind() and clean + * up any device state, before this procedure finally returns. + * + ****************************************************************************/ + +int usbdev_unregister(struct usbdevclass_driver_s *driver) +{ + /* At present, there is only a single OTG device support. Hence it is + * pre-allocated as g_otghsdev. However, in most code, the private data + * structure will be referenced using the 'priv' pointer (rather than the + * global data) in order to simplify any future support for multiple devices. + */ + + FAR struct stm32_usbdev_s *priv = &g_otghsdev; + irqstate_t flags; + + usbtrace(TRACE_DEVUNREGISTER, 0); + +#ifdef CONFIG_DEBUG_FEATURES + if (driver != priv->driver) + { + usbtrace(TRACE_DEVERROR(STM32_TRACEERR_INVALIDPARMS), 0); + return -EINVAL; + } +#endif + + /* Reset the hardware and cancel all requests. All requests must be + * canceled while the class driver is still bound. + */ + + flags = enter_critical_section(); + stm32_usbreset(priv); + leave_critical_section(flags); + + /* Unbind the class driver */ + + CLASS_UNBIND(driver, &priv->usbdev); + + /* Disable USB controller interrupts */ + + flags = enter_critical_section(); + up_disable_irq(STM32_IRQ_OTG); + + /* Disconnect device */ + + stm32_pullup(&priv->usbdev, false); + + /* Unhook the driver */ + + priv->driver = NULL; + leave_critical_section(flags); + + return OK; +} + +#endif /* CONFIG_USBDEV && CONFIG_STM32F7_OTGDEV */ diff --git a/arch/arm/src/stm32f7/stm32_otghost.c b/arch/arm/src/stm32f7/stm32_otghost.c new file mode 100644 index 0000000000000000000000000000000000000000..69ac3fbe6875e1ad748c87f9c639d32e4bf32f98 --- /dev/null +++ b/arch/arm/src/stm32f7/stm32_otghost.c @@ -0,0 +1,5304 @@ +/**************************************************************************** + * arch/arm/src/stm32f7/stm32_otghost.c + * + * Copyright (C) 2012-2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "chip.h" /* Includes default GPIO settings */ +#include /* May redefine GPIO settings */ + +#include "up_arch.h" +#include "up_internal.h" + +#include "stm32_otg.h" + +#if defined(CONFIG_USBHOST) && defined(CONFIG_STM32F7_OTGFS) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ +/* STM32 USB OTG FS Host Driver Support + * + * Pre-requisites + * + * CONFIG_USBHOST - Enable general USB host support + * CONFIG_STM32F7_OTGFS - Enable the STM32 USB OTG FS block + * CONFIG_STM32F7_SYSCFG - Needed + * + * Options: + * + * CONFIG_STM32F7_OTG_RXFIFO_SIZE - Size of the RX FIFO in 32-bit words. + * Default 128 (512 bytes) + * CONFIG_STM32F7_OTG_NPTXFIFO_SIZE - Size of the non-periodic Tx FIFO + * in 32-bit words. Default 96 (384 bytes) + * CONFIG_STM32F7_OTG_PTXFIFO_SIZE - Size of the periodic Tx FIFO in 32-bit + * words. Default 96 (384 bytes) + * CONFIG_STM32F7_OTG_DESCSIZE - Maximum size of a descriptor. Default: 128 + * CONFIG_STM32F7_OTG_SOFINTR - Enable SOF interrupts. Why would you ever + * want to do that? + * CONFIG_STM32F7_USBHOST_REGDEBUG - Enable very low-level register access + * debug. Depends on CONFIG_DEBUG_FEATURES. + * CONFIG_STM32F7_USBHOST_PKTDUMP - Dump all incoming and outgoing USB + * packets. Depends on CONFIG_DEBUG_FEATURES. + */ + +/* Pre-requisites (partial) */ + +#ifndef CONFIG_STM32F7_SYSCFG +# error "CONFIG_STM32F7_SYSCFG is required" +#endif + +/* Default RxFIFO size */ + +#ifndef CONFIG_STM32F7_OTG_RXFIFO_SIZE +# define CONFIG_STM32F7_OTG_RXFIFO_SIZE 128 +#endif + +/* Default host non-periodic Tx FIFO size */ + +#ifndef CONFIG_STM32F7_OTG_NPTXFIFO_SIZE +# define CONFIG_STM32F7_OTG_NPTXFIFO_SIZE 96 +#endif + +/* Default host periodic Tx fifo size register */ + +#ifndef CONFIG_STM32F7_OTG_PTXFIFO_SIZE +# define CONFIG_STM32F7_OTG_PTXFIFO_SIZE 96 +#endif + +/* Maximum size of a descriptor */ + +#ifndef CONFIG_STM32F7_OTG_DESCSIZE +# define CONFIG_STM32F7_OTG_DESCSIZE 128 +#endif + +/* Register/packet debug depends on CONFIG_DEBUG_FEATURES */ + +#ifndef CONFIG_DEBUG_FEATURES +# undef CONFIG_STM32F7_USBHOST_REGDEBUG +# undef CONFIG_STM32F7_USBHOST_PKTDUMP +#endif + +/* HCD Setup ****************************************************************/ +/* Hardware capabilities */ + +#define STM32_NHOST_CHANNELS 8 /* Number of host channels */ +#define STM32_MAX_PACKET_SIZE 64 /* Full speed max packet size */ +#define STM32_EP0_DEF_PACKET_SIZE 8 /* EP0 default packet size */ +#define STM32_EP0_MAX_PACKET_SIZE 64 /* EP0 FS max packet size */ +#define STM32_MAX_TX_FIFOS 15 /* Max number of TX FIFOs */ +#define STM32_MAX_PKTCOUNT 256 /* Max packet count */ +#define STM32_RETRY_COUNT 3 /* Number of ctrl transfer retries */ + +/* Delays *******************************************************************/ + +#define STM32_READY_DELAY 200000 /* In loop counts */ +#define STM32_FLUSH_DELAY 200000 /* In loop counts */ +#define STM32_SETUP_DELAY SEC2TICK(5) /* 5 seconds in system ticks */ +#define STM32_DATANAK_DELAY SEC2TICK(5) /* 5 seconds in system ticks */ + +/* Ever-present MIN/MAX macros */ + +#ifndef MIN +# define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef MAX +# define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* The following enumeration represents the various states of the USB host + * state machine (for debug purposes only) + */ + +enum stm32_smstate_e +{ + SMSTATE_DETACHED = 0, /* Not attached to a device */ + SMSTATE_ATTACHED, /* Attached to a device */ + SMSTATE_ENUM, /* Attached, enumerating */ + SMSTATE_CLASS_BOUND, /* Enumeration complete, class bound */ +}; + +/* This enumeration provides the reason for the channel halt. */ + +enum stm32_chreason_e +{ + CHREASON_IDLE = 0, /* Inactive (initial state) */ + CHREASON_FREED, /* Channel is no longer in use */ + CHREASON_XFRC, /* Transfer complete */ + CHREASON_NAK, /* NAK received */ + CHREASON_NYET, /* NotYet received */ + CHREASON_STALL, /* Endpoint stalled */ + CHREASON_TXERR, /* Transfer error received */ + CHREASON_DTERR, /* Data toggle error received */ + CHREASON_FRMOR, /* Frame overrun */ + CHREASON_CANCELLED /* Transfer cancelled */ +}; + +/* This structure retains the state of one host channel. NOTE: Since there + * is only one channel operation active at a time, some of the fields in + * in the structure could be moved in struct stm32_ubhost_s to achieve + * some memory savings. + */ + +struct stm32_chan_s +{ + sem_t waitsem; /* Channel wait semaphore */ + volatile uint8_t result; /* The result of the transfer */ + volatile uint8_t chreason; /* Channel halt reason. See enum stm32_chreason_e */ + uint8_t chidx; /* Channel index */ + uint8_t epno; /* Device endpoint number (0-127) */ + uint8_t eptype; /* See OTG_EPTYPE_* definitions */ + uint8_t funcaddr; /* Device function address */ + uint8_t speed; /* Device speed */ + uint8_t pid; /* Data PID */ + uint8_t npackets; /* Number of packets (for data toggle) */ + bool inuse; /* True: This channel is "in use" */ + volatile bool indata1; /* IN data toggle. True: DATA01 (Bulk and INTR only) */ + volatile bool outdata1; /* OUT data toggle. True: DATA01 */ + bool in; /* True: IN endpoint */ + volatile bool waiter; /* True: Thread is waiting for a channel event */ + uint16_t maxpacket; /* Max packet size */ + uint16_t buflen; /* Buffer length (at start of transfer) */ + volatile uint16_t xfrd; /* Bytes transferred (at end of transfer) */ + volatile uint16_t inflight; /* Number of Tx bytes "in-flight" */ + FAR uint8_t *buffer; /* Transfer buffer pointer */ +#ifdef CONFIG_USBHOST_ASYNCH + usbhost_asynch_t callback; /* Transfer complete callback */ + FAR void *arg; /* Argument that accompanies the callback */ +#endif +}; + +/* A channel represents on uni-directional endpoint. So, in the case of the + * bi-directional, control endpoint, there must be two channels to represent + * the endpoint. + */ + +struct stm32_ctrlinfo_s +{ + uint8_t inndx; /* EP0 IN control channel index */ + uint8_t outndx; /* EP0 OUT control channel index */ +}; + +/* This structure retains the state of the USB host controller */ + +struct stm32_usbhost_s +{ + /* Common device fields. This must be the first thing defined in the + * structure so that it is possible to simply cast from struct usbhost_s + * to structstm32_usbhost_s. + */ + + struct usbhost_driver_s drvr; + + /* This is the hub port description understood by class drivers */ + + struct usbhost_roothubport_s rhport; + + /* Overall driver status */ + + volatile uint8_t smstate; /* The state of the USB host state machine */ + uint8_t chidx; /* ID of channel waiting for space in Tx FIFO */ + volatile bool connected; /* Connected to device */ + volatile bool change; /* Connection change */ + volatile bool pscwait; /* True: Thread is waiting for a port event */ + sem_t exclsem; /* Support mutually exclusive access */ + sem_t pscsem; /* Semaphore to wait for a port event */ + struct stm32_ctrlinfo_s ep0; /* Root hub port EP0 description */ + +#ifdef CONFIG_USBHOST_HUB + /* Used to pass external hub port events */ + + volatile struct usbhost_hubport_s *hport; +#endif + + /* The state of each host channel */ + + struct stm32_chan_s chan[STM32_MAX_TX_FIFOS]; +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Register operations ******************************************************/ + +#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG +static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite); +static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite); +static uint32_t stm32_getreg(uint32_t addr); +static void stm32_putreg(uint32_t addr, uint32_t value); +#else +# define stm32_getreg(addr) getreg32(addr) +# define stm32_putreg(addr,val) putreg32(val,addr) +#endif + +static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, + uint32_t setbits); + +#ifdef CONFIG_STM32F7_USBHOST_PKTDUMP +# define stm32_pktdump(m,b,n) lib_dumpbuffer(m,b,n) +#else +# define stm32_pktdump(m,b,n) +#endif + +/* Semaphores ***************************************************************/ + +static void stm32_takesem(sem_t *sem); +#define stm32_givesem(s) sem_post(s); + +/* Byte stream access helper functions **************************************/ + +static inline uint16_t stm32_getle16(const uint8_t *val); + +/* Channel management *******************************************************/ + +static int stm32_chan_alloc(FAR struct stm32_usbhost_s *priv); +static inline void stm32_chan_free(FAR struct stm32_usbhost_s *priv, int chidx); +static inline void stm32_chan_freeall(FAR struct stm32_usbhost_s *priv); +static void stm32_chan_configure(FAR struct stm32_usbhost_s *priv, int chidx); +static void stm32_chan_halt(FAR struct stm32_usbhost_s *priv, int chidx, + enum stm32_chreason_e chreason); +static int stm32_chan_waitsetup(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_chan_s *chan); +#ifdef CONFIG_USBHOST_ASYNCH +static int stm32_chan_asynchsetup(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_chan_s *chan, + usbhost_asynch_t callback, FAR void *arg); +#endif +static int stm32_chan_wait(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_chan_s *chan); +static void stm32_chan_wakeup(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_chan_s *chan); +static int stm32_ctrlchan_alloc(FAR struct stm32_usbhost_s *priv, + uint8_t epno, uint8_t funcaddr, uint8_t speed, + FAR struct stm32_ctrlinfo_s *ctrlep); +static int stm32_ctrlep_alloc(FAR struct stm32_usbhost_s *priv, + FAR const struct usbhost_epdesc_s *epdesc, + FAR usbhost_ep_t *ep); +static int stm32_xfrep_alloc(FAR struct stm32_usbhost_s *priv, + FAR const struct usbhost_epdesc_s *epdesc, + FAR usbhost_ep_t *ep); + +/* Control/data transfer logic **********************************************/ + +static void stm32_transfer_start(FAR struct stm32_usbhost_s *priv, int chidx); +#if 0 /* Not used */ +static inline uint16_t stm32_getframe(void); +#endif +static int stm32_ctrl_sendsetup(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_ctrlinfo_s *ep0, + FAR const struct usb_ctrlreq_s *req); +static int stm32_ctrl_senddata(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_ctrlinfo_s *ep0, + FAR uint8_t *buffer, unsigned int buflen); +static int stm32_ctrl_recvdata(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_ctrlinfo_s *ep0, + FAR uint8_t *buffer, unsigned int buflen); +static int stm32_in_setup(FAR struct stm32_usbhost_s *priv, int chidx); +static ssize_t stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx, + FAR uint8_t *buffer, size_t buflen); +#ifdef CONFIG_USBHOST_ASYNCH +static void stm32_in_next(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_chan_s *chan); +static int stm32_in_asynch(FAR struct stm32_usbhost_s *priv, int chidx, + FAR uint8_t *buffer, size_t buflen, + usbhost_asynch_t callback, FAR void *arg); +#endif +static int stm32_out_setup(FAR struct stm32_usbhost_s *priv, int chidx); +static ssize_t stm32_out_transfer(FAR struct stm32_usbhost_s *priv, int chidx, + FAR uint8_t *buffer, size_t buflen); +#ifdef CONFIG_USBHOST_ASYNCH +static void stm32_out_next(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_chan_s *chan); +static int stm32_out_asynch(FAR struct stm32_usbhost_s *priv, int chidx, + FAR uint8_t *buffer, size_t buflen, + usbhost_asynch_t callback, FAR void *arg); +#endif + +/* Interrupt handling *******************************************************/ +/* Lower level interrupt handlers */ + +static void stm32_gint_wrpacket(FAR struct stm32_usbhost_s *priv, + FAR uint8_t *buffer, int chidx, int buflen); +static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv, + int chidx); +static inline void stm32_gint_hcoutisr(FAR struct stm32_usbhost_s *priv, + int chidx); +static void stm32_gint_connected(FAR struct stm32_usbhost_s *priv); +static void stm32_gint_disconnected(FAR struct stm32_usbhost_s *priv); + +/* Second level interrupt handlers */ + +#ifdef CONFIG_STM32F7_OTG_SOFINTR +static inline void stm32_gint_sofisr(FAR struct stm32_usbhost_s *priv); +#endif +static inline void stm32_gint_rxflvlisr(FAR struct stm32_usbhost_s *priv); +static inline void stm32_gint_nptxfeisr(FAR struct stm32_usbhost_s *priv); +static inline void stm32_gint_ptxfeisr(FAR struct stm32_usbhost_s *priv); +static inline void stm32_gint_hcisr(FAR struct stm32_usbhost_s *priv); +static inline void stm32_gint_hprtisr(FAR struct stm32_usbhost_s *priv); +static inline void stm32_gint_discisr(FAR struct stm32_usbhost_s *priv); +static inline void stm32_gint_ipxfrisr(FAR struct stm32_usbhost_s *priv); + +/* First level, global interrupt handler */ + +static int stm32_gint_isr(int irq, FAR void *context); + +/* Interrupt controls */ + +static void stm32_gint_enable(void); +static void stm32_gint_disable(void); +static inline void stm32_hostinit_enable(void); +static void stm32_txfe_enable(FAR struct stm32_usbhost_s *priv, int chidx); + +/* USB host controller operations *******************************************/ + +static int stm32_wait(FAR struct usbhost_connection_s *conn, + FAR struct usbhost_hubport_s **hport); +static int stm32_rh_enumerate(FAR struct stm32_usbhost_s *priv, + FAR struct usbhost_connection_s *conn, + FAR struct usbhost_hubport_s *hport); +static int stm32_enumerate(FAR struct usbhost_connection_s *conn, + FAR struct usbhost_hubport_s *hport); + +static int stm32_ep0configure(FAR struct usbhost_driver_s *drvr, + usbhost_ep_t ep0, uint8_t funcaddr, uint8_t speed, + uint16_t maxpacketsize); +static int stm32_epalloc(FAR struct usbhost_driver_s *drvr, + FAR const FAR struct usbhost_epdesc_s *epdesc, + FAR usbhost_ep_t *ep); +static int stm32_epfree(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep); +static int stm32_alloc(FAR struct usbhost_driver_s *drvr, + FAR uint8_t **buffer, FAR size_t *maxlen); +static int stm32_free(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer); +static int stm32_ioalloc(FAR struct usbhost_driver_s *drvr, + FAR uint8_t **buffer, size_t buflen); +static int stm32_iofree(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer); +static int stm32_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0, + const struct usb_ctrlreq_s *req, + FAR uint8_t *buffer); +static int stm32_ctrlout(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0, + FAR const struct usb_ctrlreq_s *req, + FAR const uint8_t *buffer); +static ssize_t stm32_transfer(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep, + FAR uint8_t *buffer, size_t buflen); +#ifdef CONFIG_USBHOST_ASYNCH +static int stm32_asynch(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep, + FAR uint8_t *buffer, size_t buflen, + usbhost_asynch_t callback, FAR void *arg); +#endif +static int stm32_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep); +#ifdef CONFIG_USBHOST_HUB +static int stm32_connect(FAR struct usbhost_driver_s *drvr, + FAR struct usbhost_hubport_s *hport, + bool connected); +#endif +static void stm32_disconnect(FAR struct usbhost_driver_s *drvr, + FAR struct usbhost_hubport_s *hport); + +/* Initialization ***********************************************************/ + +static void stm32_portreset(FAR struct stm32_usbhost_s *priv); +static void stm32_flush_txfifos(uint32_t txfnum); +static void stm32_flush_rxfifo(void); +static void stm32_vbusdrive(FAR struct stm32_usbhost_s *priv, bool state); +static void stm32_host_initialize(FAR struct stm32_usbhost_s *priv); + +static inline void stm32_sw_initialize(FAR struct stm32_usbhost_s *priv); +static inline int stm32_hw_initialize(FAR struct stm32_usbhost_s *priv); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* In this driver implementation, support is provided for only a single a single + * USB device. All status information can be simply retained in a single global + * instance. + */ + +static struct stm32_usbhost_s g_usbhost; + +/* This is the connection/enumeration interface */ + +static struct usbhost_connection_s g_usbconn = +{ + .wait = stm32_wait, + .enumerate = stm32_enumerate, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_printreg + * + * Description: + * Print the contents of an STM32xx register operation + * + ****************************************************************************/ + +#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG +static void stm32_printreg(uint32_t addr, uint32_t val, bool iswrite) +{ + llerr("%08x%s%08x\n", addr, iswrite ? "<-" : "->", val); +} +#endif + +/**************************************************************************** + * Name: stm32_checkreg + * + * Description: + * Get the contents of an STM32 register + * + ****************************************************************************/ + +#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG +static void stm32_checkreg(uint32_t addr, uint32_t val, bool iswrite) +{ + static uint32_t prevaddr = 0; + static uint32_t preval = 0; + static uint32_t count = 0; + static bool prevwrite = false; + + /* Is this the same value that we read from/wrote to the same register last time? + * Are we polling the register? If so, suppress the output. + */ + + if (addr == prevaddr && val == preval && prevwrite == iswrite) + { + /* Yes.. Just increment the count */ + + count++; + } + else + { + /* No this is a new address or value or operation. Were there any + * duplicate accesses before this one? + */ + + if (count > 0) + { + /* Yes.. Just one? */ + + if (count == 1) + { + /* Yes.. Just one */ + + stm32_printreg(prevaddr, preval, prevwrite); + } + else + { + /* No.. More than one. */ + + llerr("[repeats %d more times]\n", count); + } + } + + /* Save the new address, value, count, and operation for next time */ + + prevaddr = addr; + preval = val; + count = 0; + prevwrite = iswrite; + + /* Show the new regisgter access */ + + stm32_printreg(addr, val, iswrite); + } +} +#endif + +/**************************************************************************** + * Name: stm32_getreg + * + * Description: + * Get the contents of an STM32 register + * + ****************************************************************************/ + +#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG +static uint32_t stm32_getreg(uint32_t addr) +{ + /* Read the value from the register */ + + uint32_t val = getreg32(addr); + + /* Check if we need to print this value */ + + stm32_checkreg(addr, val, false); + return val; +} +#endif + +/**************************************************************************** + * Name: stm32_putreg + * + * Description: + * Set the contents of an STM32 register to a value + * + ****************************************************************************/ + +#ifdef CONFIG_STM32F7_USBHOST_REGDEBUG +static void stm32_putreg(uint32_t addr, uint32_t val) +{ + /* Check if we need to print this value */ + + stm32_checkreg(addr, val, true); + + /* Write the value */ + + putreg32(val, addr); +} +#endif + +/**************************************************************************** + * Name: stm32_modifyreg + * + * Description: + * Modify selected bits of an STM32 register. + * + ****************************************************************************/ + +static inline void stm32_modifyreg(uint32_t addr, uint32_t clrbits, + uint32_t setbits) +{ + stm32_putreg(addr, (((stm32_getreg(addr)) & ~clrbits) | setbits)); +} + +/**************************************************************************** + * Name: stm32_takesem + * + * Description: + * This is just a wrapper to handle the annoying behavior of semaphore + * waits that return due to the receipt of a signal. + * + ****************************************************************************/ + +static void stm32_takesem(sem_t *sem) +{ + /* Take the semaphore (perhaps waiting) */ + + while (sem_wait(sem) != 0) + { + /* The only case that an error should occr here is if the wait was + * awakened by a signal. + */ + + ASSERT(errno == EINTR); + } +} + +/**************************************************************************** + * Name: stm32_getle16 + * + * Description: + * Get a (possibly unaligned) 16-bit little endian value. + * + ****************************************************************************/ + +static inline uint16_t stm32_getle16(const uint8_t *val) +{ + return (uint16_t)val[1] << 8 | (uint16_t)val[0]; +} + +/**************************************************************************** + * Name: stm32_chan_alloc + * + * Description: + * Allocate a channel. + * + ****************************************************************************/ + +static int stm32_chan_alloc(FAR struct stm32_usbhost_s *priv) +{ + int chidx; + + /* Search the table of channels */ + + for (chidx = 0; chidx < STM32_NHOST_CHANNELS; chidx++) + { + /* Is this channel available? */ + + if (!priv->chan[chidx].inuse) + { + /* Yes... make it "in use" and return the index */ + + priv->chan[chidx].inuse = true; + return chidx; + } + } + + /* All of the channels are "in-use" */ + + return -EBUSY; +} + +/**************************************************************************** + * Name: stm32_chan_free + * + * Description: + * Free a previoiusly allocated channel. + * + ****************************************************************************/ + +static void stm32_chan_free(FAR struct stm32_usbhost_s *priv, int chidx) +{ + DEBUGASSERT((unsigned)chidx < STM32_NHOST_CHANNELS); + + /* Halt the channel */ + + stm32_chan_halt(priv, chidx, CHREASON_FREED); + + /* Mark the channel available */ + + priv->chan[chidx].inuse = false; +} + +/**************************************************************************** + * Name: stm32_chan_freeall + * + * Description: + * Free all channels. + * + ****************************************************************************/ + +static inline void stm32_chan_freeall(FAR struct stm32_usbhost_s *priv) +{ + uint8_t chidx; + + /* Free all host channels */ + + for (chidx = 2; chidx < STM32_NHOST_CHANNELS; chidx ++) + { + stm32_chan_free(priv, chidx); + } +} + +/**************************************************************************** + * Name: stm32_chan_configure + * + * Description: + * Configure or re-configure a host channel. Host channels are configured + * when endpoint is allocated and EP0 (only) is re-configured with the + * max packet size or device address changes. + * + ****************************************************************************/ + +static void stm32_chan_configure(FAR struct stm32_usbhost_s *priv, int chidx) +{ + FAR struct stm32_chan_s *chan = &priv->chan[chidx]; + uint32_t regval; + + /* Clear any old pending interrupts for this host channel. */ + + stm32_putreg(STM32_OTG_HCINT(chidx), 0xffffffff); + + /* Enable channel interrupts required for transfers on this channel. */ + + regval = 0; + + switch (chan->eptype) + { + case OTG_EPTYPE_CTRL: + case OTG_EPTYPE_BULK: + { +#ifdef HAVE_USBHOST_TRACE_VERBOSE + uint16_t intrace; + uint16_t outtrace; + + /* Determine the definitive trace ID to use below */ + + if (chan->eptype == OTG_EPTYPE_CTRL) + { + intrace = OTG_VTRACE2_CHANCONF_CTRL_IN; + outtrace = OTG_VTRACE2_CHANCONF_CTRL_OUT; + } + else + { + intrace = OTG_VTRACE2_CHANCONF_BULK_IN; + outtrace = OTG_VTRACE2_CHANCONF_BULK_OUT; + } +#endif + + /* Interrupts required for CTRL and BULK endpoints */ + + regval |= (OTG_HCINT_XFRC | OTG_HCINT_STALL | OTG_HCINT_NAK | + OTG_HCINT_TXERR | OTG_HCINT_DTERR); + + /* Additional setting for IN/OUT endpoints */ + + if (chan->in) + { + usbhost_vtrace2(intrace, chidx, chan->epno); + regval |= OTG_HCINT_BBERR; + } + else + { + usbhost_vtrace2(outtrace, chidx, chan->epno); + regval |= OTG_HCINT_NYET; + } + } + break; + + case OTG_EPTYPE_INTR: + { + /* Interrupts required for INTR endpoints */ + + regval |= (OTG_HCINT_XFRC | OTG_HCINT_STALL | OTG_HCINT_NAK | + OTG_HCINT_TXERR | OTG_HCINT_FRMOR | OTG_HCINT_DTERR); + + /* Additional setting for IN endpoints */ + + if (chan->in) + { + usbhost_vtrace2(OTG_VTRACE2_CHANCONF_INTR_IN, chidx, + chan->epno); + regval |= OTG_HCINT_BBERR; + } +#ifdef HAVE_USBHOST_TRACE_VERBOSE + else + { + usbhost_vtrace2(OTG_VTRACE2_CHANCONF_INTR_OUT, chidx, + chan->epno); + } +#endif + } + break; + + case OTG_EPTYPE_ISOC: + { + /* Interrupts required for ISOC endpoints */ + + regval |= (OTG_HCINT_XFRC | OTG_HCINT_ACK | OTG_HCINT_FRMOR); + + /* Additional setting for IN endpoints */ + + if (chan->in) + { + usbhost_vtrace2(OTG_VTRACE2_CHANCONF_ISOC_IN, chidx, + chan->epno); + regval |= (OTG_HCINT_TXERR | OTG_HCINT_BBERR); + } +#ifdef HAVE_USBHOST_TRACE_VERBOSE + else + { + usbhost_vtrace2(OTG_VTRACE2_CHANCONF_ISOC_OUT, chidx, + chan->epno); + } +#endif + } + break; + } + + stm32_putreg(STM32_OTG_HCINTMSK(chidx), regval); + + /* Enable the top level host channel interrupt. */ + + stm32_modifyreg(STM32_OTG_HAINTMSK, 0, OTG_HAINT(chidx)); + + /* Make sure host channel interrupts are enabled. */ + + stm32_modifyreg(STM32_OTG_GINTMSK, 0, OTG_GINT_HC); + + /* Program the HCCHAR register */ + + regval = ((uint32_t)chan->maxpacket << OTG_HCCHAR_MPSIZ_SHIFT) | + ((uint32_t)chan->epno << OTG_HCCHAR_EPNUM_SHIFT) | + ((uint32_t)chan->eptype << OTG_HCCHAR_EPTYP_SHIFT) | + ((uint32_t)chan->funcaddr << OTG_HCCHAR_DAD_SHIFT); + + /* Special case settings for low speed devices */ + + if (chan->speed == USB_SPEED_LOW) + { + regval |= OTG_HCCHAR_LSDEV; + } + + /* Special case settings for IN endpoints */ + + if (chan->in) + { + regval |= OTG_HCCHAR_EPDIR_IN; + } + + /* Special case settings for INTR endpoints */ + + if (chan->eptype == OTG_EPTYPE_INTR) + { + regval |= OTG_HCCHAR_ODDFRM; + } + + /* Write the channel configuration */ + + stm32_putreg(STM32_OTG_HCCHAR(chidx), regval); +} + +/**************************************************************************** + * Name: stm32_chan_halt + * + * Description: + * Halt the channel associated with 'chidx' by setting the CHannel DISable + * (CHDIS) bit in in the HCCHAR register. + * + ****************************************************************************/ + +static void stm32_chan_halt(FAR struct stm32_usbhost_s *priv, int chidx, + enum stm32_chreason_e chreason) +{ + uint32_t hcchar; + uint32_t intmsk; + uint32_t eptype; + unsigned int avail; + + /* Save the reason for the halt. We need this in the channel halt interrupt + * handling logic to know what to do next. + */ + + usbhost_vtrace2(OTG_VTRACE2_CHANHALT, chidx, chreason); + + priv->chan[chidx].chreason = (uint8_t)chreason; + + /* "The application can disable any channel by programming the OTG_FS_HCCHARx + * register with the CHDIS and CHENA bits set to 1. This enables the OTG_FS + * host to flush the posted requests (if any) and generates a channel halted + * interrupt. The application must wait for the CHH interrupt in OTG_FS_HCINTx + * before reallocating the channel for other transactions. The OTG_FS host + * does not interrupt the transaction that has already been started on the + * USB." + */ + + hcchar = stm32_getreg(STM32_OTG_HCCHAR(chidx)); + hcchar |= (OTG_HCCHAR_CHDIS | OTG_HCCHAR_CHENA); + + /* Get the endpoint type from the HCCHAR register */ + + eptype = hcchar & OTG_HCCHAR_EPTYP_MASK; + + /* Check for space in the Tx FIFO to issue the halt. + * + * "Before disabling a channel, the application must ensure that there is at + * least one free space available in the non-periodic request queue (when + * disabling a non-periodic channel) or the periodic request queue (when + * disabling a periodic channel). The application can simply flush the + * posted requests when the Request queue is full (before disabling the + * channel), by programming the OTG_FS_HCCHARx register with the CHDIS bit + * set to 1, and the CHENA bit cleared to 0. + */ + + if (eptype == OTG_HCCHAR_EPTYP_CTRL || eptype == OTG_HCCHAR_EPTYP_BULK) + { + /* Get the number of words available in the non-periodic Tx FIFO. */ + + avail = stm32_getreg(STM32_OTG_HNPTXSTS) & OTG_HNPTXSTS_NPTXFSAV_MASK; + } + else /* if (eptype == OTG_HCCHAR_EPTYP_ISOC || eptype == OTG_HCCHAR_EPTYP_INTR) */ + { + /* Get the number of words available in the non-periodic Tx FIFO. */ + + avail = stm32_getreg(STM32_OTG_HPTXSTS) & OTG_HPTXSTS_PTXFSAVL_MASK; + } + + /* Check if there is any space available in the Tx FIFO. */ + + if (avail == 0) + { + /* The Tx FIFO is full... disable the channel to flush the requests */ + + hcchar &= ~OTG_HCCHAR_CHENA; + } + + /* Unmask the CHannel Halted (CHH) interrupt */ + + intmsk = stm32_getreg(STM32_OTG_HCINTMSK(chidx)); + intmsk |= OTG_HCINT_CHH; + stm32_putreg(STM32_OTG_HCINTMSK(chidx), intmsk); + + /* Halt the channel by setting CHDIS (and maybe CHENA) in the HCCHAR */ + + stm32_putreg(STM32_OTG_HCCHAR(chidx), hcchar); +} + +/**************************************************************************** + * Name: stm32_chan_waitsetup + * + * Description: + * Set the request for the transfer complete event well BEFORE enabling + * the transfer (as soon as we are absolutely committed to the transfer). + * We do this to minimize race conditions. This logic would have to be + * expanded if we want to have more than one packet in flight at a time! + * + * Assumptions: + * Called from a normal thread context BEFORE the transfer has been started. + * + ****************************************************************************/ + +static int stm32_chan_waitsetup(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_chan_s *chan) +{ + irqstate_t flags = enter_critical_section(); + int ret = -ENODEV; + + /* Is the device still connected? */ + + if (priv->connected) + { + /* Yes.. then set waiter to indicate that we expect to be informed when + * either (1) the device is disconnected, or (2) the transfer completed. + */ + + chan->waiter = true; +#ifdef CONFIG_USBHOST_ASYNCH + chan->callback = NULL; + chan->arg = NULL; +#endif + ret = OK; + } + + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Name: stm32_chan_asynchsetup + * + * Description: + * Set the request for the transfer complete event well BEFORE enabling the + * transfer (as soon as we are absolutely committed to the to avoid transfer). + * We do this to minimize race conditions. This logic would have to be expanded + * if we want to have more than one packet in flight at a time! + * + * Assumptions: + * Might be called from the level of an interrupt handler + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST_ASYNCH +static int stm32_chan_asynchsetup(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_chan_s *chan, + usbhost_asynch_t callback, FAR void *arg) +{ + irqstate_t flags = enter_critical_section(); + int ret = -ENODEV; + + /* Is the device still connected? */ + + if (priv->connected) + { + /* Yes.. then set waiter to indicate that we expect to be informed when + * either (1) the device is disconnected, or (2) the transfer completed. + */ + + chan->waiter = false; + chan->callback = callback; + chan->arg = arg; + ret = OK; + } + + leave_critical_section(flags); + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_chan_wait + * + * Description: + * Wait for a transfer on a channel to complete. + * + * Assumptions: + * Called from a normal thread context + * + ****************************************************************************/ + +static int stm32_chan_wait(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_chan_s *chan) +{ + irqstate_t flags; + int ret; + + /* Disable interrupts so that the following operations will be atomic. On + * the OTG FS global interrupt needs to be disabled. However, here we + * disable all interrupts to exploit that fact that interrupts will be re- + * enabled while we wait. + */ + + flags = enter_critical_section(); + + /* Loop, testing for an end of transfer condition. The channel 'result' + * was set to EBUSY and 'waiter' was set to true before the transfer; 'waiter' + * will be set to false and 'result' will be set appropriately when the + * transfer is completed. + */ + + do + { + /* Wait for the transfer to complete. NOTE the transfer may already + * completed before we get here or the transfer may complete while we + * wait here. + */ + + ret = sem_wait(&chan->waitsem); + + /* sem_wait should succeed. But it is possible that we could be + * awakened by a signal too. + */ + + DEBUGASSERT(ret == OK || get_errno() == EINTR); + } + while (chan->waiter); + + /* The transfer is complete re-enable interrupts and return the result */ + + ret = -(int)chan->result; + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Name: stm32_chan_wakeup + * + * Description: + * A channel transfer has completed... wakeup any threads waiting for the + * transfer to complete. + * + * Assumptions: + * This function is called from the transfer complete interrupt handler for + * the channel. Interrupts are disabled. + * + ****************************************************************************/ + +static void stm32_chan_wakeup(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_chan_s *chan) +{ + /* Is the transfer complete? */ + + if (chan->result != EBUSY) + { + /* Is there a thread waiting for this transfer to complete? */ + + if (chan->waiter) + { +#ifdef CONFIG_USBHOST_ASYNCH + /* Yes.. there should not also be a callback scheduled */ + + DEBUGASSERT(chan->callback == NULL); +#endif + /* Wake'em up! */ + + usbhost_vtrace2(chan->in ? OTG_VTRACE2_CHANWAKEUP_IN : + OTG_VTRACE2_CHANWAKEUP_OUT, + chan->epno, chan->result); + + stm32_givesem(&chan->waitsem); + chan->waiter = false; + } + +#ifdef CONFIG_USBHOST_ASYNCH + /* No.. is an asynchronous callback expected when the transfer + * completes? + */ + + else if (chan->callback) + { + /* Handle continuation of IN/OUT pipes */ + + if (chan->in) + { + stm32_in_next(priv, chan); + } + else + { + stm32_out_next(priv, chan); + } + } +#endif + } +} + +/**************************************************************************** + * Name: stm32_ctrlchan_alloc + * + * Description: + * Allocate and configured channels for a control pipe. + * + ****************************************************************************/ + +static int stm32_ctrlchan_alloc(FAR struct stm32_usbhost_s *priv, + uint8_t epno, uint8_t funcaddr, uint8_t speed, + FAR struct stm32_ctrlinfo_s *ctrlep) +{ + FAR struct stm32_chan_s *chan; + int inndx; + int outndx; + + outndx = stm32_chan_alloc(priv); + if (outndx < 0) + { + return -ENOMEM; + } + + ctrlep->outndx = outndx; + chan = &priv->chan[outndx]; + chan->epno = epno; + chan->in = false; + chan->eptype = OTG_EPTYPE_CTRL; + chan->funcaddr = funcaddr; + chan->speed = speed; + chan->maxpacket = STM32_EP0_DEF_PACKET_SIZE; + chan->indata1 = false; + chan->outdata1 = false; + + /* Configure control OUT channels */ + + stm32_chan_configure(priv, outndx); + + /* Allocate and initialize the control IN channel */ + + inndx = stm32_chan_alloc(priv); + if (inndx < 0) + { + stm32_chan_free(priv, outndx); + return -ENOMEM; + } + + ctrlep->inndx = inndx; + chan = &priv->chan[inndx]; + chan->epno = epno; + chan->in = true; + chan->eptype = OTG_EPTYPE_CTRL; + chan->funcaddr = funcaddr; + chan->speed = speed; + chan->maxpacket = STM32_EP0_DEF_PACKET_SIZE; + chan->indata1 = false; + chan->outdata1 = false; + + /* Configure control IN channels */ + + stm32_chan_configure(priv, inndx); + return OK; +} + +/**************************************************************************** + * Name: stm32_ctrlep_alloc + * + * Description: + * Allocate a container and channels for control pipe. + * + * Input Parameters: + * priv - The private USB host driver state. + * epdesc - Describes the endpoint to be allocated. + * ep - A memory location provided by the caller in which to receive the + * allocated endpoint descriptor. + * + * Returned Values: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_ctrlep_alloc(FAR struct stm32_usbhost_s *priv, + FAR const struct usbhost_epdesc_s *epdesc, + FAR usbhost_ep_t *ep) +{ + FAR struct usbhost_hubport_s *hport; + FAR struct stm32_ctrlinfo_s *ctrlep; + int ret; + + /* Sanity check. NOTE that this method should only be called if a device is + * connected (because we need a valid low speed indication). + */ + + DEBUGASSERT(epdesc->hport != NULL); + hport = epdesc->hport; + + /* Allocate a container for the control endpoint */ + + ctrlep = (FAR struct stm32_ctrlinfo_s *)kmm_malloc(sizeof(struct stm32_ctrlinfo_s)); + if (ctrlep == NULL) + { + uerr("ERROR: Failed to allocate control endpoint container\n"); + return -ENOMEM; + } + + /* Then allocate and configure the IN/OUT channnels */ + + ret = stm32_ctrlchan_alloc(priv, epdesc->addr & USB_EPNO_MASK, + hport->funcaddr, hport->speed, ctrlep); + if (ret < 0) + { + uerr("ERROR: stm32_ctrlchan_alloc failed: %d\n", ret); + kmm_free(ctrlep); + return ret; + } + + /* Return a pointer to the control pipe container as the pipe "handle" */ + + *ep = (usbhost_ep_t)ctrlep; + return OK; +} + +/**************************************************************************** + * Name: stm32_xfrep_alloc + * + * Description: + * Allocate and configure one unidirectional endpoint. + * + * Input Parameters: + * priv - The private USB host driver state. + * epdesc - Describes the endpoint to be allocated. + * ep - A memory location provided by the caller in which to receive the + * allocated endpoint descriptor. + * + * Returned Values: + * On success, zero (OK) is returned. On a failure, a negated errno value + * is returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_xfrep_alloc(FAR struct stm32_usbhost_s *priv, + FAR const struct usbhost_epdesc_s *epdesc, + FAR usbhost_ep_t *ep) +{ + struct usbhost_hubport_s *hport; + FAR struct stm32_chan_s *chan; + int chidx; + + /* Sanity check. NOTE that this method should only be called if a device is + * connected (because we need a valid low speed indication). + */ + + DEBUGASSERT(epdesc->hport != NULL); + hport = epdesc->hport; + + /* Allocate a host channel for the endpoint */ + + chidx = stm32_chan_alloc(priv); + if (chidx < 0) + { + uerr("ERROR: Failed to allocate a host channel\n"); + return -ENOMEM; + } + + /* Decode the endpoint descriptor to initialize the channel data structures. + * Note: Here we depend on the fact that the endpoint point type is + * encoded in the same way in the endpoint descriptor as it is in the OTG + * HS hardware. + */ + + chan = &priv->chan[chidx]; + chan->epno = epdesc->addr & USB_EPNO_MASK; + chan->in = epdesc->in; + chan->eptype = epdesc->xfrtype; + chan->funcaddr = hport->funcaddr; + chan->speed = hport->speed; + chan->maxpacket = epdesc->mxpacketsize; + chan->indata1 = false; + chan->outdata1 = false; + + /* Then configure the endpoint */ + + stm32_chan_configure(priv, chidx); + + /* Return the index to the allocated channel as the endpoint "handle" */ + + *ep = (usbhost_ep_t)chidx; + return OK; +} + +/**************************************************************************** + * Name: stm32_transfer_start + * + * Description: + * Start at transfer on the select IN or OUT channel. + * + ****************************************************************************/ + +static void stm32_transfer_start(FAR struct stm32_usbhost_s *priv, int chidx) +{ + FAR struct stm32_chan_s *chan; + uint32_t regval; + unsigned int npackets; + unsigned int maxpacket; + unsigned int avail; + unsigned int wrsize; + unsigned int minsize; + + /* Set up the initial state of the transfer */ + + chan = &priv->chan[chidx]; + + usbhost_vtrace2(OTG_VTRACE2_STARTTRANSFER, chidx, chan->buflen); + + chan->result = EBUSY; + chan->inflight = 0; + chan->xfrd = 0; + priv->chidx = chidx; + + /* Compute the expected number of packets associated to the transfer. + * If the transfer length is zero (or less than the size of one maximum + * size packet), then one packet is expected. + */ + + /* If the transfer size is greater than one packet, then calculate the + * number of packets that will be received/sent, including any partial + * final packet. + */ + + maxpacket = chan->maxpacket; + + if (chan->buflen > maxpacket) + { + npackets = (chan->buflen + maxpacket - 1) / maxpacket; + + /* Clip if the buffer length if it exceeds the maximum number of + * packets that can be transferred (this should not happen). + */ + + if (npackets > STM32_MAX_PKTCOUNT) + { + npackets = STM32_MAX_PKTCOUNT; + chan->buflen = STM32_MAX_PKTCOUNT * maxpacket; + usbhost_trace2(OTG_TRACE2_CLIP, chidx, chan->buflen); + } + } + else + { + /* One packet will be sent/received (might be a zero length packet) */ + + npackets = 1; + } + + /* If it is an IN transfer, then adjust the size of the buffer UP to + * a full number of packets. Hmmm... couldn't this cause an overrun + * into unallocated memory? + */ + +#if 0 /* Think about this */ + if (chan->in) + { + /* Force the buffer length to an even multiple of maxpacket */ + + chan->buflen = npackets * maxpacket; + } +#endif + + /* Save the number of packets in the transfer. We will need this in + * order to set the next data toggle correctly when the transfer + * completes. + */ + + chan->npackets = (uint8_t)npackets; + + /* Setup the HCTSIZn register */ + + regval = ((uint32_t)chan->buflen << OTG_HCTSIZ_XFRSIZ_SHIFT) | + ((uint32_t)npackets << OTG_HCTSIZ_PKTCNT_SHIFT) | + ((uint32_t)chan->pid << OTG_HCTSIZ_DPID_SHIFT); + stm32_putreg(STM32_OTG_HCTSIZ(chidx), regval); + + /* Setup the HCCHAR register: Frame oddness and host channel enable */ + + regval = stm32_getreg(STM32_OTG_HCCHAR(chidx)); + + /* Set/clear the Odd Frame bit. Check for an even frame; if so set Odd + * Frame. This field is applicable for only periodic (isochronous and + * interrupt) channels. + */ + + if ((stm32_getreg(STM32_OTG_HFNUM) & 1) == 0) + { + regval |= OTG_HCCHAR_ODDFRM; + } + else + { + regval &= ~OTG_HCCHAR_ODDFRM; + } + + regval &= ~OTG_HCCHAR_CHDIS; + regval |= OTG_HCCHAR_CHENA; + stm32_putreg(STM32_OTG_HCCHAR(chidx), regval); + + /* If this is an out transfer, then we need to do more.. we need to copy + * the outgoing data into the correct TxFIFO. + */ + + if (!chan->in && chan->buflen > 0) + { + /* Handle non-periodic (CTRL and BULK) OUT transfers differently than + * periodic (INTR and ISOC) OUT transfers. + */ + + minsize = MIN(chan->buflen, chan->maxpacket); + + switch (chan->eptype) + { + case OTG_EPTYPE_CTRL: /* Non periodic transfer */ + case OTG_EPTYPE_BULK: + { + /* Read the Non-periodic Tx FIFO status register */ + + regval = stm32_getreg(STM32_OTG_HNPTXSTS); + avail = ((regval & OTG_HNPTXSTS_NPTXFSAV_MASK) >> OTG_HNPTXSTS_NPTXFSAV_SHIFT) << 2; + } + break; + + /* Periodic transfer */ + + case OTG_EPTYPE_INTR: + case OTG_EPTYPE_ISOC: + { + /* Read the Non-periodic Tx FIFO status register */ + + regval = stm32_getreg(STM32_OTG_HPTXSTS); + avail = ((regval & OTG_HPTXSTS_PTXFSAVL_MASK) >> OTG_HPTXSTS_PTXFSAVL_SHIFT) << 2; + } + break; + + default: + DEBUGASSERT(false); + return; + } + + /* Is there space in the TxFIFO to hold the minimum size packet? */ + + if (minsize <= avail) + { + /* Yes.. Get the size of the biggest thing that we can put in the Tx FIFO now */ + + wrsize = chan->buflen; + if (wrsize > avail) + { + /* Clip the write size to the number of full, max sized packets + * that will fit in the Tx FIFO. + */ + + unsigned int wrpackets = avail / chan->maxpacket; + wrsize = wrpackets * chan->maxpacket; + } + + /* Write packet into the Tx FIFO. */ + + stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize); + } + + /* Did we put the entire buffer into the Tx FIFO? */ + + if (chan->buflen > avail) + { + /* No, there was insufficient space to hold the entire transfer ... + * Enable the Tx FIFO interrupt to handle the transfer when the Tx + * FIFO becomes empty. + */ + + stm32_txfe_enable(priv, chidx); + } + } +} + +/**************************************************************************** + * Name: stm32_getframe + * + * Description: + * Get the current frame number. The frame number (FRNUM) field increments + * when a new SOF is transmitted on the USB, and is cleared to 0 when it + * reaches 0x3fff. + * + ****************************************************************************/ + +#if 0 /* Not used */ +static inline uint16_t stm32_getframe(void) +{ + return (uint16_t)(stm32_getreg(STM32_OTG_HFNUM) & OTG_HFNUM_FRNUM_MASK); +} +#endif + +/**************************************************************************** + * Name: stm32_ctrl_sendsetup + * + * Description: + * Send an IN/OUT SETUP packet. + * + ****************************************************************************/ + +static int stm32_ctrl_sendsetup(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_ctrlinfo_s *ep0, + FAR const struct usb_ctrlreq_s *req) +{ + FAR struct stm32_chan_s *chan; + systime_t start; + systime_t elapsed; + int ret; + + /* Loop while the device reports NAK (and a timeout is not exceeded */ + + chan = &priv->chan[ep0->outndx]; + start = clock_systimer(); + + do + { + /* Send the SETUP packet */ + + chan->pid = OTG_PID_SETUP; + chan->buffer = (FAR uint8_t *)req; + chan->buflen = USB_SIZEOF_CTRLREQ; + chan->xfrd = 0; + + /* Set up for the wait BEFORE starting the transfer */ + + ret = stm32_chan_waitsetup(priv, chan); + if (ret < 0) + { + usbhost_trace1(OTG_TRACE1_DEVDISCONN, 0); + return ret; + } + + /* Start the transfer */ + + stm32_transfer_start(priv, ep0->outndx); + + /* Wait for the transfer to complete */ + + ret = stm32_chan_wait(priv, chan); + + /* Return on success and for all failures other than EAGAIN. EAGAIN + * means that the device NAKed the SETUP command and that we should + * try a few more times. + */ + + if (ret != -EAGAIN) + { + /* Output some debug information if the transfer failed */ + + if (ret < 0) + { + usbhost_trace1(OTG_TRACE1_TRNSFRFAILED, ret); + } + + /* Return the result in any event */ + + return ret; + } + + /* Get the elapsed time (in frames) */ + + elapsed = clock_systimer() - start; + } + while (elapsed < STM32_SETUP_DELAY); + + return -ETIMEDOUT; +} + +/**************************************************************************** + * Name: stm32_ctrl_senddata + * + * Description: + * Send data in the data phase of an OUT control transfer. Or send status + * in the status phase of an IN control transfer + * + ****************************************************************************/ + +static int stm32_ctrl_senddata(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_ctrlinfo_s *ep0, + FAR uint8_t *buffer, unsigned int buflen) +{ + FAR struct stm32_chan_s *chan = &priv->chan[ep0->outndx]; + int ret; + + /* Save buffer information */ + + chan->buffer = buffer; + chan->buflen = buflen; + chan->xfrd = 0; + + /* Set the DATA PID */ + + if (buflen == 0) + { + /* For status OUT stage with buflen == 0, set PID DATA1 */ + + chan->outdata1 = true; + } + + /* Set the Data PID as per the outdata1 boolean */ + + chan->pid = chan->outdata1 ? OTG_PID_DATA1 : OTG_PID_DATA0; + + /* Set up for the wait BEFORE starting the transfer */ + + ret = stm32_chan_waitsetup(priv, chan); + if (ret < 0) + { + usbhost_trace1(OTG_TRACE1_DEVDISCONN, 0); + return ret; + } + + /* Start the transfer */ + + stm32_transfer_start(priv, ep0->outndx); + + /* Wait for the transfer to complete and return the result */ + + return stm32_chan_wait(priv, chan); +} + +/**************************************************************************** + * Name: stm32_ctrl_recvdata + * + * Description: + * Receive data in the data phase of an IN control transfer. Or receive status + * in the status phase of an OUT control transfer + * + ****************************************************************************/ + +static int stm32_ctrl_recvdata(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_ctrlinfo_s *ep0, + FAR uint8_t *buffer, unsigned int buflen) +{ + FAR struct stm32_chan_s *chan = &priv->chan[ep0->inndx]; + int ret; + + /* Save buffer information */ + + chan->pid = OTG_PID_DATA1; + chan->buffer = buffer; + chan->buflen = buflen; + chan->xfrd = 0; + + /* Set up for the wait BEFORE starting the transfer */ + + ret = stm32_chan_waitsetup(priv, chan); + if (ret < 0) + { + usbhost_trace1(OTG_TRACE1_DEVDISCONN, 0); + return ret; + } + + /* Start the transfer */ + + stm32_transfer_start(priv, ep0->inndx); + + /* Wait for the transfer to complete and return the result */ + + return stm32_chan_wait(priv, chan); +} + +/**************************************************************************** + * Name: stm32_in_setup + * + * Description: + * Initiate an IN transfer on an bulk, interrupt, or isochronous pipe. + * + ****************************************************************************/ + +static int stm32_in_setup(FAR struct stm32_usbhost_s *priv, int chidx) +{ + FAR struct stm32_chan_s *chan; + + /* Set up for the transfer based on the direction and the endpoint type */ + + chan = &priv->chan[chidx]; + switch (chan->eptype) + { + default: + case OTG_EPTYPE_CTRL: /* Control */ + { + /* This kind of transfer on control endpoints other than EP0 are not + * currently supported + */ + + return -ENOSYS; + } + + case OTG_EPTYPE_ISOC: /* Isochronous */ + { + /* Set up the IN data PID */ + + usbhost_vtrace2(OTG_VTRACE2_ISOCIN, chidx, chan->buflen); + chan->pid = OTG_PID_DATA0; + } + break; + + case OTG_EPTYPE_BULK: /* Bulk */ + { + /* Setup the IN data PID */ + + usbhost_vtrace2(OTG_VTRACE2_BULKIN, chidx, chan->buflen); + chan->pid = chan->indata1 ? OTG_PID_DATA1 : OTG_PID_DATA0; + } + break; + + case OTG_EPTYPE_INTR: /* Interrupt */ + { + /* Setup the IN data PID */ + + usbhost_vtrace2(OTG_VTRACE2_INTRIN, chidx, chan->buflen); + chan->pid = chan->indata1 ? OTG_PID_DATA1 : OTG_PID_DATA0; + } + break; + } + + /* Start the transfer */ + + stm32_transfer_start(priv, chidx); + return OK; +} + +/**************************************************************************** + * Name: stm32_in_transfer + * + * Description: + * Transfer 'buflen' bytes into 'buffer' from an IN channel. + * + ****************************************************************************/ + +static ssize_t stm32_in_transfer(FAR struct stm32_usbhost_s *priv, int chidx, + FAR uint8_t *buffer, size_t buflen) +{ + FAR struct stm32_chan_s *chan; + systime_t start; + systime_t elapsed; + int ret; + + /* Loop until the transfer completes (i.e., buflen is decremented to zero) + * or a fatal error occurs (any error other than a simple NAK) + */ + + chan = &priv->chan[chidx]; + chan->buffer = buffer; + chan->buflen = buflen; + chan->xfrd = 0; + + start = clock_systimer(); + while (chan->xfrd < chan->buflen) + { + /* Set up for the wait BEFORE starting the transfer */ + + ret = stm32_chan_waitsetup(priv, chan); + if (ret < 0) + { + usbhost_trace1(OTG_TRACE1_DEVDISCONN, 0); + return (ssize_t)ret; + } + + /* Set up for the transfer based on the direction and the endpoint type */ + + ret = stm32_in_setup(priv, chidx); + if (ret < 0) + { + uerr("ERROR: stm32_in_setup failed: %d\n", ret); + return (ssize_t)ret; + } + + /* Wait for the transfer to complete and get the result */ + + ret = stm32_chan_wait(priv, chan); + + /* EAGAIN indicates that the device NAKed the transfer and we need + * do try again. Anything else (success or other errors) will + * cause use to return + */ + + if (ret < 0) + { + usbhost_trace1(OTG_TRACE1_TRNSFRFAILED, ret); + + /* Check for a special case: If (1) the transfer was NAKed and (2) + * no Tx FIFO empty or Rx FIFO not-empty event occurred, then we + * should be able to just flush the Rx and Tx FIFOs and try again. + * We can detect this latter case because the then the transfer + * buffer pointer and buffer size will be unaltered. + */ + + elapsed = clock_systimer() - start; + if (ret != -EAGAIN || /* Not a NAK condition OR */ + elapsed >= STM32_DATANAK_DELAY || /* Timeout has elapsed OR */ + chan->xfrd > 0) /* Data has been partially transferred */ + { + /* Break out and return the error */ + + uerr("ERROR: stm32_chan_wait failed: %d\n", ret); + return (ssize_t)ret; + } + } + } + + return (ssize_t)chan->xfrd; +} + +/**************************************************************************** + * Name: stm32_in_next + * + * Description: + * Initiate the next of a sequence of asynchronous transfers. + * + * Assumptions: + * This function is always called from an interrupt handler + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST_ASYNCH +static void stm32_in_next(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_chan_s *chan) +{ + usbhost_asynch_t callback; + FAR void *arg; + ssize_t nbytes; + int result; + int ret; + + /* Is the full transfer complete? Did the last chunk transfer complete OK? */ + + result = -(int)chan->result; + if (chan->xfrd < chan->buflen && result == OK) + { + /* Yes.. Set up for the next transfer based on the direction and the + * endpoint type + */ + + ret = stm32_in_setup(priv, chan->chidx); + if (ret >= 0) + { + return; + } + + uerr("ERROR: stm32_in_setup failed: %d\n", ret); + result = ret; + } + + /* The transfer is complete, with or without an error */ + + uinfo("Transfer complete: %d\n", result); + + /* Extract the callback information */ + + callback = chan->callback; + arg = chan->arg; + nbytes = chan->xfrd; + + chan->callback = NULL; + chan->arg = NULL; + chan->xfrd = 0; + + /* Then perform the callback */ + + if (result < 0) + { + nbytes = (ssize_t)result; + } + + callback(arg, nbytes); +} +#endif + +/**************************************************************************** + * Name: stm32_in_asynch + * + * Description: + * Initiate the first of a sequence of asynchronous transfers. + * + * Assumptions: + * This function is never called from an interrupt handler + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST_ASYNCH +static int stm32_in_asynch(FAR struct stm32_usbhost_s *priv, int chidx, + FAR uint8_t *buffer, size_t buflen, + usbhost_asynch_t callback, FAR void *arg) +{ + FAR struct stm32_chan_s *chan; + int ret; + + /* Set up for the transfer data and callback BEFORE starting the first transfer */ + + chan = &priv->chan[chidx]; + chan->buffer = buffer; + chan->buflen = buflen; + chan->xfrd = 0; + + ret = stm32_chan_asynchsetup(priv, chan, callback, arg); + if (ret < 0) + { + uerr("ERROR: stm32_chan_asynchsetup failed: %d\n", ret); + return ret; + } + + /* Set up for the transfer based on the direction and the endpoint type */ + + ret = stm32_in_setup(priv, chidx); + if (ret < 0) + { + uerr("ERROR: stm32_in_setup failed: %d\n", ret); + } + + /* And return with the transfer pending */ + + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_out_setup + * + * Description: + * Initiate an OUT transfer on an bulk, interrupt, or isochronous pipe. + * + ****************************************************************************/ + +static int stm32_out_setup(FAR struct stm32_usbhost_s *priv, int chidx) +{ + FAR struct stm32_chan_s *chan; + + /* Set up for the transfer based on the direction and the endpoint type */ + + chan = &priv->chan[chidx]; + switch (chan->eptype) + { + default: + case OTG_EPTYPE_CTRL: /* Control */ + { + /* This kind of transfer on control endpoints other than EP0 are not + * currently supported + */ + + return -ENOSYS; + } + + case OTG_EPTYPE_ISOC: /* Isochronous */ + { + /* Set up the OUT data PID */ + + usbhost_vtrace2(OTG_VTRACE2_ISOCOUT, chidx, chan->buflen); + chan->pid = OTG_PID_DATA0; + } + break; + + case OTG_EPTYPE_BULK: /* Bulk */ + { + /* Setup the OUT data PID */ + + usbhost_vtrace2(OTG_VTRACE2_BULKOUT, chidx, chan->buflen); + chan->pid = chan->outdata1 ? OTG_PID_DATA1 : OTG_PID_DATA0; + } + break; + + case OTG_EPTYPE_INTR: /* Interrupt */ + { + /* Setup the OUT data PID */ + + usbhost_vtrace2(OTG_VTRACE2_INTROUT, chidx, chan->buflen); + chan->pid = chan->outdata1 ? OTG_PID_DATA1 : OTG_PID_DATA0; + + /* Toggle the OUT data PID for the next transfer */ + + chan->outdata1 ^= true; + } + break; + } + + /* Start the transfer */ + + stm32_transfer_start(priv, chidx); + return OK; +} + +/**************************************************************************** + * Name: stm32_out_transfer + * + * Description: + * Transfer the 'buflen' bytes in 'buffer' through an OUT channel. + * + ****************************************************************************/ + +static ssize_t stm32_out_transfer(FAR struct stm32_usbhost_s *priv, int chidx, + FAR uint8_t *buffer, size_t buflen) +{ + FAR struct stm32_chan_s *chan; + systime_t start; + systime_t elapsed; + size_t xfrlen; + ssize_t xfrd; + int ret; + + /* Loop until the transfer completes (i.e., buflen is decremented to zero) + * or a fatal error occurs (any error other than a simple NAK) + */ + + chan = &priv->chan[chidx]; + start = clock_systimer(); + xfrd = 0; + + while (buflen > 0) + { + /* Transfer one packet at a time. The hardware is capable of queueing + * multiple OUT packets, but I just haven't figured out how to handle + * the case where a single OUT packet in the group is NAKed. + */ + + xfrlen = MIN(chan->maxpacket, buflen); + chan->buffer = buffer; + chan->buflen = xfrlen; + chan->xfrd = 0; + + /* Set up for the wait BEFORE starting the transfer */ + + ret = stm32_chan_waitsetup(priv, chan); + if (ret < 0) + { + usbhost_trace1(OTG_TRACE1_DEVDISCONN, 0); + return (ssize_t)ret; + } + + /* Set up for the transfer based on the direction and the endpoint type */ + + ret = stm32_out_setup(priv, chidx); + if (ret < 0) + { + uerr("ERROR: stm32_out_setup failed: %d\n", ret); + return (ssize_t)ret; + } + + /* Wait for the transfer to complete and get the result */ + + ret = stm32_chan_wait(priv, chan); + + /* Handle transfer failures */ + + if (ret < 0) + { + usbhost_trace1(OTG_TRACE1_TRNSFRFAILED, ret); + + /* Check for a special case: If (1) the transfer was NAKed and (2) + * no Tx FIFO empty or Rx FIFO not-empty event occurred, then we + * should be able to just flush the Rx and Tx FIFOs and try again. + * We can detect this latter case because the then the transfer + * buffer pointer and buffer size will be unaltered. + */ + + elapsed = clock_systimer() - start; + if (ret != -EAGAIN || /* Not a NAK condition OR */ + elapsed >= STM32_DATANAK_DELAY || /* Timeout has elapsed OR */ + chan->xfrd > 0) /* Data has been partially transferred */ + { + /* Break out and return the error */ + + uerr("ERROR: stm32_chan_wait failed: %d\n", ret); + return (ssize_t)ret; + } + + /* Is this flush really necessary? What does the hardware do with the + * data in the FIFO when the NAK occurs? Does it discard it? + */ + + stm32_flush_txfifos(OTG_GRSTCTL_TXFNUM_HALL); + + /* Get the device a little time to catch up. Then retry the transfer + * using the same buffer pointer and length. + */ + + usleep(20*1000); + } + else + { + /* Successfully transferred. Update the buffer pointer and length */ + + buffer += xfrlen; + buflen -= xfrlen; + xfrd += chan->xfrd; + } + } + + return xfrd; +} + +/**************************************************************************** + * Name: stm32_out_next + * + * Description: + * Initiate the next of a sequence of asynchronous transfers. + * + * Assumptions: + * This function is always called from an interrupt handler + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST_ASYNCH +static void stm32_out_next(FAR struct stm32_usbhost_s *priv, + FAR struct stm32_chan_s *chan) +{ + usbhost_asynch_t callback; + FAR void *arg; + ssize_t nbytes; + int result; + int ret; + + /* Is the full transfer complete? Did the last chunk transfer complete OK? */ + + result = -(int)chan->result; + if (chan->xfrd < chan->buflen && result == OK) + { + /* Yes.. Set up for the next transfer based on the direction and the + * endpoint type + */ + + ret = stm32_out_setup(priv, chan->chidx); + if (ret >= 0) + { + return; + } + + uerr("ERROR: stm32_out_setup failed: %d\n", ret); + result = ret; + } + + /* The transfer is complete, with or without an error */ + + uinfo("Transfer complete: %d\n", result); + + /* Extract the callback information */ + + callback = chan->callback; + arg = chan->arg; + nbytes = chan->xfrd; + + chan->callback = NULL; + chan->arg = NULL; + chan->xfrd = 0; + + /* Then perform the callback */ + + if (result < 0) + { + nbytes = (ssize_t)result; + } + + callback(arg, nbytes); +} +#endif + +/**************************************************************************** + * Name: stm32_out_asynch + * + * Description: + * Initiate the first of a sequence of asynchronous transfers. + * + * Assumptions: + * This function is never called from an interrupt handler + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST_ASYNCH +static int stm32_out_asynch(FAR struct stm32_usbhost_s *priv, int chidx, + FAR uint8_t *buffer, size_t buflen, + usbhost_asynch_t callback, FAR void *arg) +{ + FAR struct stm32_chan_s *chan; + int ret; + + /* Set up for the transfer data and callback BEFORE starting the first transfer */ + + chan = &priv->chan[chidx]; + chan->buffer = buffer; + chan->buflen = buflen; + chan->xfrd = 0; + + ret = stm32_chan_asynchsetup(priv, chan, callback, arg); + if (ret < 0) + { + uerr("ERROR: stm32_chan_asynchsetup failed: %d\n", ret); + return ret; + } + + /* Set up for the transfer based on the direction and the endpoint type */ + + ret = stm32_out_setup(priv, chidx); + if (ret < 0) + { + uerr("ERROR: stm32_out_setup failed: %d\n", ret); + } + + /* And return with the transfer pending */ + + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_gint_wrpacket + * + * Description: + * Transfer the 'buflen' bytes in 'buffer' to the Tx FIFO associated with + * 'chidx' (non-DMA). + * + ****************************************************************************/ + +static void stm32_gint_wrpacket(FAR struct stm32_usbhost_s *priv, + FAR uint8_t *buffer, int chidx, int buflen) +{ + FAR uint32_t *src; + uint32_t fifo; + int buflen32; + + stm32_pktdump("Sending", buffer, buflen); + + /* Get the number of 32-byte words associated with this byte size */ + + buflen32 = (buflen + 3) >> 2; + + /* Get the address of the Tx FIFO associated with this channel */ + + fifo = STM32_OTG_DFIFO_HCH(chidx); + + /* Transfer all of the data into the Tx FIFO */ + + src = (FAR uint32_t *)buffer; + for (; buflen32 > 0; buflen32--) + { + uint32_t data = *src++; + stm32_putreg(fifo, data); + } + + /* Increment the count of bytes "in-flight" in the Tx FIFO */ + + priv->chan[chidx].inflight += buflen; +} + +/**************************************************************************** + * Name: stm32_gint_hcinisr + * + * Description: + * USB OTG FS host IN channels interrupt handler + * + * One the completion of the transfer, the channel result byte may be set as + * follows: + * + * OK - Transfer completed successfully + * EAGAIN - If devices NAKs the transfer or NYET occurs + * EPERM - If the endpoint stalls + * EIO - On a TX or data toggle error + * EPIPE - Frame overrun + * + * EBUSY in the result field indicates that the transfer has not completed. + * + ****************************************************************************/ + +static inline void stm32_gint_hcinisr(FAR struct stm32_usbhost_s *priv, + int chidx) +{ + FAR struct stm32_chan_s *chan = &priv->chan[chidx]; + uint32_t regval; + uint32_t pending; + + /* Read the HCINT register to get the pending HC interrupts. Read the + * HCINTMSK register to get the set of enabled HC interrupts. + */ + + pending = stm32_getreg(STM32_OTG_HCINT(chidx)); + regval = stm32_getreg(STM32_OTG_HCINTMSK(chidx)); + + /* AND the two to get the set of enabled, pending HC interrupts */ + + pending &= regval; + uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending); + + /* Check for a pending ACK response received/transmitted (ACK) interrupt */ + + if ((pending & OTG_HCINT_ACK) != 0) + { + /* Clear the pending the ACK response received/transmitted (ACK) interrupt */ + + stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_ACK); + } + + /* Check for a pending STALL response receive (STALL) interrupt */ + + else if ((pending & OTG_HCINT_STALL) != 0) + { + /* Clear the NAK and STALL Conditions. */ + + stm32_putreg(STM32_OTG_HCINT(chidx), (OTG_HCINT_NAK | OTG_HCINT_STALL)); + + /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is + * received on the channel. + */ + + stm32_chan_halt(priv, chidx, CHREASON_STALL); + + /* When there is a STALL, clear any pending NAK so that it is not + * processed below. + */ + + pending &= ~OTG_HCINT_NAK; + } + + /* Check for a pending Data Toggle ERRor (DTERR) interrupt */ + + else if ((pending & OTG_HCINT_DTERR) != 0) + { + /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is + * received on the channel. + */ + + stm32_chan_halt(priv, chidx, CHREASON_DTERR); + + /* Clear the NAK and data toggle error conditions */ + + stm32_putreg(STM32_OTG_HCINT(chidx), (OTG_HCINT_NAK | OTG_HCINT_DTERR)); + } + + /* Check for a pending FRaMe OverRun (FRMOR) interrupt */ + + if ((pending & OTG_HCINT_FRMOR) != 0) + { + /* Halt the channel -- the CHH interrupt is expected next */ + + stm32_chan_halt(priv, chidx, CHREASON_FRMOR); + + /* Clear the FRaMe OverRun (FRMOR) condition */ + + stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_FRMOR); + } + + /* Check for a pending TransFeR Completed (XFRC) interrupt */ + + else if ((pending & OTG_HCINT_XFRC) != 0) + { + /* Clear the TransFeR Completed (XFRC) condition */ + + stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_XFRC); + + /* Then handle the transfer completion event based on the endpoint type */ + + if (chan->eptype == OTG_EPTYPE_CTRL || chan->eptype == OTG_EPTYPE_BULK) + { + /* Halt the channel -- the CHH interrupt is expected next */ + + stm32_chan_halt(priv, chidx, CHREASON_XFRC); + + /* Clear any pending NAK condition. The 'indata1' data toggle + * should have been appropriately updated by the RxFIFO + * logic as each packet was received. + */ + + stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_NAK); + } + else if (chan->eptype == OTG_EPTYPE_INTR) + { + /* Force the next transfer on an ODD frame */ + + regval = stm32_getreg(STM32_OTG_HCCHAR(chidx)); + regval |= OTG_HCCHAR_ODDFRM; + stm32_putreg(STM32_OTG_HCCHAR(chidx), regval); + + /* Set the request done state */ + + chan->result = OK; + } + } + + /* Check for a pending CHannel Halted (CHH) interrupt */ + + else if ((pending & OTG_HCINT_CHH) != 0) + { + /* Mask the CHannel Halted (CHH) interrupt */ + + regval = stm32_getreg(STM32_OTG_HCINTMSK(chidx)); + regval &= ~OTG_HCINT_CHH; + stm32_putreg(STM32_OTG_HCINTMSK(chidx), regval); + + /* Update the request state based on the host state machine state */ + + if (chan->chreason == CHREASON_XFRC) + { + /* Set the request done result */ + + chan->result = OK; + } + else if (chan->chreason == CHREASON_STALL) + { + /* Set the request stall result */ + + chan->result = EPERM; + } + else if ((chan->chreason == CHREASON_TXERR) || + (chan->chreason == CHREASON_DTERR)) + { + /* Set the request I/O error result */ + + chan->result = EIO; + } + else if (chan->chreason == CHREASON_NAK) + { + /* Halt on NAK only happens on an INTR channel. Fetch the HCCHAR + * register and check for an interrupt endpoint. + */ + + regval = stm32_getreg(STM32_OTG_HCCHAR(chidx)); + if ((regval & OTG_HCCHAR_EPTYP_MASK) == OTG_HCCHAR_EPTYP_INTR) + { + /* Toggle the IN data toggle (Used by Bulk and INTR only) */ + + chan->indata1 ^= true; + } + + /* Set the NAK error result */ + + chan->result = EAGAIN; + } + else /* if (chan->chreason == CHREASON_FRMOR) */ + { + /* Set the frame overrun error result */ + + chan->result = EPIPE; + } + + /* Clear the CHannel Halted (CHH) condition */ + + stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_CHH); + } + + /* Check for a pending Transaction ERror (TXERR) interrupt */ + + else if ((pending & OTG_HCINT_TXERR) != 0) + { + /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is + * received on the channel. + */ + + stm32_chan_halt(priv, chidx, CHREASON_TXERR); + + /* Clear the Transaction ERror (TXERR) condition */ + + stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_TXERR); + } + + /* Check for a pending NAK response received (NAK) interrupt */ + + else if ((pending & OTG_HCINT_NAK) != 0) + { + /* For a BULK transfer, the hardware is capable of retrying + * automatically on a NAK. However, this is not always + * what we need to do. So we always halt the transfer and + * return control to high level logic in the event of a NAK. + */ + +#if 1 + /* Halt the interrupt channel */ + + if (chan->eptype == OTG_EPTYPE_INTR) + { + /* Halt the channel -- the CHH interrupt is expected next */ + + stm32_chan_halt(priv, chidx, CHREASON_NAK); + } + + /* Re-activate CTRL and BULK channels. + * REVISIT: This can cause a lot of interrupts! + */ + + else if (chan->eptype == OTG_EPTYPE_CTRL || + chan->eptype == OTG_EPTYPE_BULK) + { + /* Re-activate the channel by clearing CHDIS and assuring that + * CHENA is set + */ + + regval = stm32_getreg(STM32_OTG_HCCHAR(chidx)); + regval |= OTG_HCCHAR_CHENA; + regval &= ~OTG_HCCHAR_CHDIS; + stm32_putreg(STM32_OTG_HCCHAR(chidx), regval); + } +#else + /* Halt all transfers on the NAK -- the CHH interrupt is expected next */ + + stm32_chan_halt(priv, chidx, CHREASON_NAK); +#endif + + /* Clear the NAK condition */ + + stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_NAK); + } + + /* Check for a transfer complete event */ + + stm32_chan_wakeup(priv, chan); +} + +/**************************************************************************** + * Name: stm32_gint_hcoutisr + * + * Description: + * USB OTG FS host OUT channels interrupt handler + * + * One the completion of the transfer, the channel result byte may be set as + * follows: + * + * OK - Transfer completed successfully + * EAGAIN - If devices NAKs the transfer or NYET occurs + * EPERM - If the endpoint stalls + * EIO - On a TX or data toggle error + * EPIPE - Frame overrun + * + * EBUSY in the result field indicates that the transfer has not completed. + * + ****************************************************************************/ + +static inline void stm32_gint_hcoutisr(FAR struct stm32_usbhost_s *priv, + int chidx) +{ + FAR struct stm32_chan_s *chan = &priv->chan[chidx]; + uint32_t regval; + uint32_t pending; + + /* Read the HCINT register to get the pending HC interrupts. Read the + * HCINTMSK register to get the set of enabled HC interrupts. + */ + + pending = stm32_getreg(STM32_OTG_HCINT(chidx)); + regval = stm32_getreg(STM32_OTG_HCINTMSK(chidx)); + + /* AND the two to get the set of enabled, pending HC interrupts */ + + pending &= regval; + uinfo("HCINTMSK%d: %08x pending: %08x\n", chidx, regval, pending); + + /* Check for a pending ACK response received/transmitted (ACK) interrupt */ + + if ((pending & OTG_HCINT_ACK) != 0) + { + /* Clear the pending the ACK response received/transmitted (ACK) interrupt */ + + stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_ACK); + } + + /* Check for a pending FRaMe OverRun (FRMOR) interrupt */ + + else if ((pending & OTG_HCINT_FRMOR) != 0) + { + /* Halt the channel (probably not necessary for FRMOR) */ + + stm32_chan_halt(priv, chidx, CHREASON_FRMOR); + + /* Clear the pending the FRaMe OverRun (FRMOR) interrupt */ + + stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_FRMOR); + } + + /* Check for a pending TransFeR Completed (XFRC) interrupt */ + + else if ((pending & OTG_HCINT_XFRC) != 0) + { + /* Decrement the number of bytes remaining by the number of + * bytes that were "in-flight". + */ + + priv->chan[chidx].buffer += priv->chan[chidx].inflight; + priv->chan[chidx].xfrd += priv->chan[chidx].inflight; + priv->chan[chidx].inflight = 0; + + /* Halt the channel -- the CHH interrupt is expected next */ + + stm32_chan_halt(priv, chidx, CHREASON_XFRC); + + /* Clear the pending the TransFeR Completed (XFRC) interrupt */ + + stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_XFRC); + } + + /* Check for a pending STALL response receive (STALL) interrupt */ + + else if ((pending & OTG_HCINT_STALL) != 0) + { + /* Clear the pending the STALL response receiv (STALL) interrupt */ + + stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_STALL); + + /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is + * received on the channel. + */ + + stm32_chan_halt(priv, chidx, CHREASON_STALL); + } + + /* Check for a pending NAK response received (NAK) interrupt */ + + else if ((pending & OTG_HCINT_NAK) != 0) + { + /* Halt the channel -- the CHH interrupt is expected next */ + + stm32_chan_halt(priv, chidx, CHREASON_NAK); + + /* Clear the pending the NAK response received (NAK) interrupt */ + + stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_NAK); + } + + /* Check for a pending Transaction ERror (TXERR) interrupt */ + + else if ((pending & OTG_HCINT_TXERR) != 0) + { + /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is + * received on the channel. + */ + + stm32_chan_halt(priv, chidx, CHREASON_TXERR); + + /* Clear the pending the Transaction ERror (TXERR) interrupt */ + + stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_TXERR); + } + + /* Check for a NYET interrupt */ + +#if 0 /* NYET is a reserved bit in the HCINT register */ + else if ((pending & OTG_HCINT_NYET) != 0) + { + /* Halt the channel */ + + stm32_chan_halt(priv, chidx, CHREASON_NYET); + + /* Clear the pending the NYET interrupt */ + + stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_NYET); + } +#endif + + /* Check for a pending Data Toggle ERRor (DTERR) interrupt */ + + else if (pending & OTG_HCINT_DTERR) + { + /* Halt the channel when a STALL, TXERR, BBERR or DTERR interrupt is + * received on the channel. + */ + + stm32_chan_halt(priv, chidx, CHREASON_DTERR); + + /* Clear the pending the Data Toggle ERRor (DTERR) and NAK interrupts */ + + stm32_putreg(STM32_OTG_HCINT(chidx), (OTG_HCINT_DTERR | OTG_HCINT_NAK)); + } + + /* Check for a pending CHannel Halted (CHH) interrupt */ + + else if ((pending & OTG_HCINT_CHH) != 0) + { + /* Mask the CHannel Halted (CHH) interrupt */ + + regval = stm32_getreg(STM32_OTG_HCINTMSK(chidx)); + regval &= ~OTG_HCINT_CHH; + stm32_putreg(STM32_OTG_HCINTMSK(chidx), regval); + + if (chan->chreason == CHREASON_XFRC) + { + /* Set the request done result */ + + chan->result = OK; + + /* Read the HCCHAR register to get the HCCHAR register to get + * the endpoint type. + */ + + regval = stm32_getreg(STM32_OTG_HCCHAR(chidx)); + + /* Is it a bulk endpoint? Were an odd number of packets + * transferred? + */ + + if ((regval & OTG_HCCHAR_EPTYP_MASK) == OTG_HCCHAR_EPTYP_BULK && + (chan->npackets & 1) != 0) + { + /* Yes to both... toggle the data out PID */ + + chan->outdata1 ^= true; + } + } + else if (chan->chreason == CHREASON_NAK || + chan->chreason == CHREASON_NYET) + { + /* Set the try again later result */ + + chan->result = EAGAIN; + } + else if (chan->chreason == CHREASON_STALL) + { + /* Set the request stall result */ + + chan->result = EPERM; + } + else if ((chan->chreason == CHREASON_TXERR) || + (chan->chreason == CHREASON_DTERR)) + { + /* Set the I/O failure result */ + + chan->result = EIO; + } + else /* if (chan->chreason == CHREASON_FRMOR) */ + { + /* Set the frame error result */ + + chan->result = EPIPE; + } + + /* Clear the pending the CHannel Halted (CHH) interrupt */ + + stm32_putreg(STM32_OTG_HCINT(chidx), OTG_HCINT_CHH); + } + + /* Check for a transfer complete event */ + + stm32_chan_wakeup(priv, chan); +} + +/**************************************************************************** + * Name: stm32_gint_connected + * + * Description: + * Handle a connection event. + * + ****************************************************************************/ + +static void stm32_gint_connected(FAR struct stm32_usbhost_s *priv) +{ + /* We we previously disconnected? */ + + if (!priv->connected) + { + /* Yes.. then now we are connected */ + + usbhost_vtrace1(OTG_VTRACE1_CONNECTED, 0); + priv->connected = true; + priv->change = true; + DEBUGASSERT(priv->smstate == SMSTATE_DETACHED); + + /* Notify any waiters */ + + priv->smstate = SMSTATE_ATTACHED; + if (priv->pscwait) + { + stm32_givesem(&priv->pscsem); + priv->pscwait = false; + } + } +} + +/**************************************************************************** + * Name: stm32_gint_disconnected + * + * Description: + * Handle a disconnection event. + * + ****************************************************************************/ + +static void stm32_gint_disconnected(FAR struct stm32_usbhost_s *priv) +{ + /* Were we previously connected? */ + + if (priv->connected) + { + /* Yes.. then we no longer connected */ + + usbhost_vtrace1(OTG_VTRACE1_DISCONNECTED, 0); + + /* Are we bound to a class driver? */ + + if (priv->rhport.hport.devclass) + { + /* Yes.. Disconnect the class driver */ + + CLASS_DISCONNECTED(priv->rhport.hport.devclass); + priv->rhport.hport.devclass = NULL; + } + + /* Re-Initialize Host for new Enumeration */ + + priv->smstate = SMSTATE_DETACHED; + priv->connected = false; + priv->change = true; + stm32_chan_freeall(priv); + + priv->rhport.hport.speed = USB_SPEED_FULL; + + /* Notify any waiters that there is a change in the connection state */ + + if (priv->pscwait) + { + stm32_givesem(&priv->pscsem); + priv->pscwait = false; + } + } +} + +/**************************************************************************** + * Name: stm32_gint_sofisr + * + * Description: + * USB OTG FS start-of-frame interrupt handler + * + ****************************************************************************/ + +#ifdef CONFIG_STM32F7_OTG_SOFINTR +static inline void stm32_gint_sofisr(FAR struct stm32_usbhost_s *priv) +{ + /* Handle SOF interrupt */ +#warning "Do what?" + + /* Clear pending SOF interrupt */ + + stm32_putreg(STM32_OTG_GINTSTS, OTG_GINT_SOF); +} +#endif + +/**************************************************************************** + * Name: stm32_gint_rxflvlisr + * + * Description: + * USB OTG FS RxFIFO non-empty interrupt handler + * + ****************************************************************************/ + +static inline void stm32_gint_rxflvlisr(FAR struct stm32_usbhost_s *priv) +{ + FAR uint32_t *dest; + uint32_t grxsts; + uint32_t intmsk; + uint32_t hcchar; + uint32_t hctsiz; + uint32_t fifo; + int bcnt; + int bcnt32; + int chidx; + int i; + + /* Disable the RxFIFO non-empty interrupt */ + + intmsk = stm32_getreg(STM32_OTG_GINTMSK); + intmsk &= ~OTG_GINT_RXFLVL; + stm32_putreg(STM32_OTG_GINTMSK, intmsk); + + /* Read and pop the next status from the Rx FIFO */ + + grxsts = stm32_getreg(STM32_OTG_GRXSTSP); + uinfo("GRXSTS: %08x\n", grxsts); + + /* Isolate the channel number/index in the status word */ + + chidx = (grxsts & OTG_GRXSTSH_CHNUM_MASK) >> OTG_GRXSTSH_CHNUM_SHIFT; + + /* Get the host channel characteristics register (HCCHAR) for this channel */ + + hcchar = stm32_getreg(STM32_OTG_HCCHAR(chidx)); + + /* Then process the interrupt according to the packet status */ + + switch (grxsts & OTG_GRXSTSH_PKTSTS_MASK) + { + case OTG_GRXSTSH_PKTSTS_INRECVD: /* IN data packet received */ + { + /* Read the data into the host buffer. */ + + bcnt = (grxsts & OTG_GRXSTSH_BCNT_MASK) >> OTG_GRXSTSH_BCNT_SHIFT; + if (bcnt > 0 && priv->chan[chidx].buffer != NULL) + { + /* Transfer the packet from the Rx FIFO into the user buffer */ + + dest = (FAR uint32_t *)priv->chan[chidx].buffer; + fifo = STM32_OTG_DFIFO_HCH(0); + bcnt32 = (bcnt + 3) >> 2; + + for (i = 0; i < bcnt32; i++) + { + *dest++ = stm32_getreg(fifo); + } + + stm32_pktdump("Received", priv->chan[chidx].buffer, bcnt); + + /* Toggle the IN data pid (Used by Bulk and INTR only) */ + + priv->chan[chidx].indata1 ^= true; + + /* Manage multiple packet transfers */ + + priv->chan[chidx].buffer += bcnt; + priv->chan[chidx].xfrd += bcnt; + + /* Check if more packets are expected */ + + hctsiz = stm32_getreg(STM32_OTG_HCTSIZ(chidx)); + if ((hctsiz & OTG_HCTSIZ_PKTCNT_MASK) != 0) + { + /* Re-activate the channel when more packets are expected */ + + hcchar |= OTG_HCCHAR_CHENA; + hcchar &= ~OTG_HCCHAR_CHDIS; + stm32_putreg(STM32_OTG_HCCHAR(chidx), hcchar); + } + } + } + break; + + case OTG_GRXSTSH_PKTSTS_INDONE: /* IN transfer completed */ + case OTG_GRXSTSH_PKTSTS_DTOGERR: /* Data toggle error */ + case OTG_GRXSTSH_PKTSTS_HALTED: /* Channel halted */ + default: + break; + } + + /* Re-enable the RxFIFO non-empty interrupt */ + + intmsk |= OTG_GINT_RXFLVL; + stm32_putreg(STM32_OTG_GINTMSK, intmsk); +} + +/**************************************************************************** + * Name: stm32_gint_nptxfeisr + * + * Description: + * USB OTG FS non-periodic TxFIFO empty interrupt handler + * + ****************************************************************************/ + +static inline void stm32_gint_nptxfeisr(FAR struct stm32_usbhost_s *priv) +{ + FAR struct stm32_chan_s *chan; + uint32_t regval; + unsigned int wrsize; + unsigned int avail; + unsigned int chidx; + + /* Recover the index of the channel that is waiting for space in the Tx + * FIFO. + */ + + chidx = priv->chidx; + chan = &priv->chan[chidx]; + + /* Reduce the buffer size by the number of bytes that were previously placed + * in the Tx FIFO. + */ + + chan->buffer += chan->inflight; + chan->xfrd += chan->inflight; + chan->inflight = 0; + + /* If we have now transferred the entire buffer, then this transfer is + * complete (this case really should never happen because we disable + * the NPTXFE interrupt on the final packet). + */ + + if (chan->xfrd >= chan->buflen) + { + /* Disable further Tx FIFO empty interrupts and bail. */ + + stm32_modifyreg(STM32_OTG_GINTMSK, OTG_GINT_NPTXFE, 0); + return; + } + + /* Read the status from the top of the non-periodic TxFIFO */ + + regval = stm32_getreg(STM32_OTG_HNPTXSTS); + + /* Extract the number of bytes available in the non-periodic Tx FIFO. */ + + avail = ((regval & OTG_HNPTXSTS_NPTXFSAV_MASK) >> OTG_HNPTXSTS_NPTXFSAV_SHIFT) << 2; + + /* Get the size to put in the Tx FIFO now */ + + wrsize = chan->buflen - chan->xfrd; + + /* Get minimal size packet that can be sent. Something is seriously + * configured wrong if one packet will not fit into the empty Tx FIFO. + */ + + DEBUGASSERT(wrsize > 0 && avail >= MIN(wrsize, chan->maxpacket)); + if (wrsize > avail) + { + /* Clip the write size to the number of full, max sized packets + * that will fit in the Tx FIFO. + */ + + unsigned int wrpackets = avail / chan->maxpacket; + wrsize = wrpackets * chan->maxpacket; + } + + /* Otherwise, this will be the last packet to be sent in this transaction. + * We now need to disable further NPTXFE interrupts. + */ + + else + { + stm32_modifyreg(STM32_OTG_GINTMSK, OTG_GINT_NPTXFE, 0); + } + + /* Write the next group of packets into the Tx FIFO */ + + uinfo("HNPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n", + regval, chidx, avail, chan->buflen, chan->xfrd, wrsize); + + stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize); +} + +/**************************************************************************** + * Name: stm32_gint_ptxfeisr + * + * Description: + * USB OTG FS periodic TxFIFO empty interrupt handler + * + ****************************************************************************/ + +static inline void stm32_gint_ptxfeisr(FAR struct stm32_usbhost_s *priv) +{ + FAR struct stm32_chan_s *chan; + uint32_t regval; + unsigned int wrsize; + unsigned int avail; + unsigned int chidx; + + /* Recover the index of the channel that is waiting for space in the Tx + * FIFO. + */ + + chidx = priv->chidx; + chan = &priv->chan[chidx]; + + /* Reduce the buffer size by the number of bytes that were previously placed + * in the Tx FIFO. + */ + + chan->buffer += chan->inflight; + chan->xfrd += chan->inflight; + chan->inflight = 0; + + /* If we have now transfered the entire buffer, then this transfer is + * complete (this case really should never happen because we disable + * the PTXFE interrupt on the final packet). + */ + + if (chan->xfrd >= chan->buflen) + { + /* Disable further Tx FIFO empty interrupts and bail. */ + + stm32_modifyreg(STM32_OTG_GINTMSK, OTG_GINT_PTXFE, 0); + return; + } + + /* Read the status from the top of the periodic TxFIFO */ + + regval = stm32_getreg(STM32_OTG_HPTXSTS); + + /* Extract the number of bytes available in the periodic Tx FIFO. */ + + avail = ((regval & OTG_HPTXSTS_PTXFSAVL_MASK) >> OTG_HPTXSTS_PTXFSAVL_SHIFT) << 2; + + /* Get the size to put in the Tx FIFO now */ + + wrsize = chan->buflen - chan->xfrd; + + /* Get minimal size packet that can be sent. Something is seriously + * configured wrong if one packet will not fit into the empty Tx FIFO. + */ + + DEBUGASSERT(wrsize && avail >= MIN(wrsize, chan->maxpacket)); + if (wrsize > avail) + { + /* Clip the write size to the number of full, max sized packets + * that will fit in the Tx FIFO. + */ + + unsigned int wrpackets = avail / chan->maxpacket; + wrsize = wrpackets * chan->maxpacket; + } + + /* Otherwise, this will be the last packet to be sent in this transaction. + * We now need to disable further PTXFE interrupts. + */ + + else + { + stm32_modifyreg(STM32_OTG_GINTMSK, OTG_GINT_PTXFE, 0); + } + + /* Write the next group of packets into the Tx FIFO */ + + uinfo("HPTXSTS: %08x chidx: %d avail: %d buflen: %d xfrd: %d wrsize: %d\n", + regval, chidx, avail, chan->buflen, chan->xfrd, wrsize); + + stm32_gint_wrpacket(priv, chan->buffer, chidx, wrsize); +} + +/**************************************************************************** + * Name: stm32_gint_hcisr + * + * Description: + * USB OTG FS host channels interrupt handler + * + ****************************************************************************/ + +static inline void stm32_gint_hcisr(FAR struct stm32_usbhost_s *priv) +{ + uint32_t haint; + uint32_t hcchar; + int i = 0; + + /* Read the Host all channels interrupt register and test each bit in the + * register. Each bit i, i=0...(STM32_NHOST_CHANNELS-1), corresponds to + * a pending interrupt on channel i. + */ + + haint = stm32_getreg(STM32_OTG_HAINT); + for (i = 0; i < STM32_NHOST_CHANNELS; i++) + { + /* Is an interrupt pending on this channel? */ + + if ((haint & OTG_HAINT(i)) != 0) + { + /* Yes... read the HCCHAR register to get the direction bit */ + + hcchar = stm32_getreg(STM32_OTG_HCCHAR(i)); + + /* Was this an interrupt on an IN or an OUT channel? */ + + if ((hcchar & OTG_HCCHAR_EPDIR) != 0) + { + /* Handle the HC IN channel interrupt */ + + stm32_gint_hcinisr(priv, i); + } + else + { + /* Handle the HC OUT channel interrupt */ + + stm32_gint_hcoutisr(priv, i); + } + } + } +} + +/**************************************************************************** + * Name: stm32_gint_hprtisr + * + * Description: + * USB OTG FS host port interrupt handler + * + ****************************************************************************/ + +static inline void stm32_gint_hprtisr(FAR struct stm32_usbhost_s *priv) +{ + uint32_t hprt; + uint32_t newhprt; + uint32_t hcfg; + + usbhost_vtrace1(OTG_VTRACE1_GINT_HPRT, 0); + /* Read the port status and control register (HPRT) */ + + hprt = stm32_getreg(STM32_OTG_HPRT); + + /* Setup to clear the interrupt bits in GINTSTS by setting the corresponding + * bits in the HPRT. The HCINT interrupt bit is cleared when the appropriate + * status bits in the HPRT register are cleared. + */ + + newhprt = hprt & ~(OTG_HPRT_PENA | OTG_HPRT_PCDET | + OTG_HPRT_PENCHNG | OTG_HPRT_POCCHNG); + + /* Check for Port Overcurrent CHaNGe (POCCHNG) */ + + if ((hprt & OTG_HPRT_POCCHNG) != 0) + { + /* Set up to clear the POCCHNG status in the new HPRT contents. */ + + usbhost_vtrace1(OTG_VTRACE1_GINT_HPRT_POCCHNG, 0); + newhprt |= OTG_HPRT_POCCHNG; + } + + /* Check for Port Connect DETected (PCDET). The core sets this bit when a + * device connection is detected. + */ + + if ((hprt & OTG_HPRT_PCDET) != 0) + { + /* Set up to clear the PCDET status in the new HPRT contents. Then + * process the new connection event. + */ + + usbhost_vtrace1(OTG_VTRACE1_GINT_HPRT_PCDET, 0); + newhprt |= OTG_HPRT_PCDET; + stm32_portreset(priv); + stm32_gint_connected(priv); + } + + /* Check for Port Enable CHaNGed (PENCHNG) */ + + if ((hprt & OTG_HPRT_PENCHNG) != 0) + { + /* Set up to clear the PENCHNG status in the new HPRT contents. */ + + usbhost_vtrace1(OTG_VTRACE1_GINT_HPRT_PENCHNG, 0); + newhprt |= OTG_HPRT_PENCHNG; + + /* Was the port enabled? */ + + if ((hprt & OTG_HPRT_PENA) != 0) + { + /* Yes.. handle the new connection event */ + + stm32_gint_connected(priv); + + /* Check the Host ConFiGuration register (HCFG) */ + + hcfg = stm32_getreg(STM32_OTG_HCFG); + + /* Is this a low speed or full speed connection (OTG FS does not + * support high speed) + */ + + if ((hprt & OTG_HPRT_PSPD_MASK) == OTG_HPRT_PSPD_LS) + { + /* Set the Host Frame Interval Register for the 6KHz speed */ + + usbhost_vtrace1(OTG_VTRACE1_GINT_HPRT_LSDEV, 0); + stm32_putreg(STM32_OTG_HFIR, 6000); + + /* Are we switching from FS to LS? */ + + if ((hcfg & OTG_HCFG_FSLSPCS_MASK) != OTG_HCFG_FSLSPCS_LS6MHz) + { + usbhost_vtrace1(OTG_VTRACE1_GINT_HPRT_FSLSSW, 0); + + /* Yes... configure for LS */ + + hcfg &= ~OTG_HCFG_FSLSPCS_MASK; + hcfg |= OTG_HCFG_FSLSPCS_LS6MHz; + stm32_putreg(STM32_OTG_HCFG, hcfg); + + /* And reset the port */ + + stm32_portreset(priv); + } + } + else /* if ((hprt & OTG_HPRT_PSPD_MASK) == OTG_HPRT_PSPD_FS) */ + { + + usbhost_vtrace1(OTG_VTRACE1_GINT_HPRT_FSDEV, 0); + stm32_putreg(STM32_OTG_HFIR, 48000); + + /* Are we switching from LS to FS? */ + + if ((hcfg & OTG_HCFG_FSLSPCS_MASK) != OTG_HCFG_FSLSPCS_FS48MHz) + { + + usbhost_vtrace1(OTG_VTRACE1_GINT_HPRT_LSFSSW, 0); + /* Yes... configure for FS */ + + hcfg &= ~OTG_HCFG_FSLSPCS_MASK; + hcfg |= OTG_HCFG_FSLSPCS_FS48MHz; + stm32_putreg(STM32_OTG_HCFG, hcfg); + + /* And reset the port */ + + stm32_portreset(priv); + } + } + } + } + + /* Clear port interrupts by setting bits in the HPRT */ + + stm32_putreg(STM32_OTG_HPRT, newhprt); +} + +/**************************************************************************** + * Name: stm32_gint_discisr + * + * Description: + * USB OTG FS disconnect detected interrupt handler + * + ****************************************************************************/ + +static inline void stm32_gint_discisr(FAR struct stm32_usbhost_s *priv) +{ + /* Handle the disconnection event */ + + stm32_gint_disconnected(priv); + + /* Clear the dicsonnect interrupt */ + + stm32_putreg(STM32_OTG_GINTSTS, OTG_GINT_DISC); +} + +/**************************************************************************** + * Name: stm32_gint_ipxfrisr + * + * Description: + * USB OTG FS incomplete periodic interrupt handler + * + ****************************************************************************/ + +static inline void stm32_gint_ipxfrisr(FAR struct stm32_usbhost_s *priv) +{ + uint32_t regval; + + /* CHENA : Set to enable the channel + * CHDIS : Set to stop transmitting/receiving data on a channel + */ + + regval = stm32_getreg(STM32_OTG_HCCHAR(0)); + regval |= (OTG_HCCHAR_CHDIS | OTG_HCCHAR_CHENA); + stm32_putreg(STM32_OTG_HCCHAR(0), regval); + + /* Clear the incomplete isochronous OUT interrupt */ + + stm32_putreg(STM32_OTG_GINTSTS, OTG_GINT_IPXFR); +} + +/**************************************************************************** + * Name: stm32_gint_isr + * + * Description: + * USB OTG FS global interrupt handler + * + ****************************************************************************/ + +static int stm32_gint_isr(int irq, FAR void *context) +{ + /* At present, there is only support for a single OTG FS host. Hence it is + * pre-allocated as g_usbhost. However, in most code, the private data + * structure will be referenced using the 'priv' pointer (rather than the + * global data) in order to simplify any future support for multiple devices. + */ + + FAR struct stm32_usbhost_s *priv = &g_usbhost; + uint32_t pending; + + /* If OTG were supported, we would need to check if we are in host or + * device mode when the global interrupt occurs. Here we support only + * host mode + */ + + /* Loop while there are pending interrupts to process. This loop may save a + * little interrupt handling overhead. + */ + + for (; ; ) + { + /* Get the unmasked bits in the GINT status */ + + pending = stm32_getreg(STM32_OTG_GINTSTS); + pending &= stm32_getreg(STM32_OTG_GINTMSK); + + /* Return from the interrupt when there are no further pending + * interrupts. + */ + + if (pending == 0) + { + return OK; + } + + /* Otherwise, process each pending, unmasked GINT interrupts */ + /* Handle the start of frame interrupt */ + +#ifdef CONFIG_STM32F7_OTG_SOFINTR + if ((pending & OTG_GINT_SOF) != 0) + { + usbhost_vtrace1(OTG_VTRACE1_GINT_SOF, 0); + stm32_gint_sofisr(priv); + } +#endif + + /* Handle the RxFIFO non-empty interrupt */ + + if ((pending & OTG_GINT_RXFLVL) != 0) + { + usbhost_vtrace1(OTG_VTRACE1_GINT_RXFLVL, 0); + stm32_gint_rxflvlisr(priv); + } + + /* Handle the non-periodic TxFIFO empty interrupt */ + + if ((pending & OTG_GINT_NPTXFE) != 0) + { + usbhost_vtrace1(OTG_VTRACE1_GINT_NPTXFE, 0); + stm32_gint_nptxfeisr(priv); + } + + /* Handle the periodic TxFIFO empty interrupt */ + + if ((pending & OTG_GINT_PTXFE) != 0) + { + usbhost_vtrace1(OTG_VTRACE1_GINT_PTXFE, 0); + stm32_gint_ptxfeisr(priv); + } + + /* Handle the host channels interrupt */ + + if ((pending & OTG_GINT_HC) != 0) + { + usbhost_vtrace1(OTG_VTRACE1_GINT_HC, 0); + stm32_gint_hcisr(priv); + } + + /* Handle the host port interrupt */ + + if ((pending & OTG_GINT_HPRT) != 0) + { + stm32_gint_hprtisr(priv); + } + + /* Handle the disconnect detected interrupt */ + + if ((pending & OTG_GINT_DISC) != 0) + { + usbhost_vtrace1(OTG_VTRACE1_GINT_DISC, 0); + stm32_gint_discisr(priv); + } + + /* Handle the incomplete periodic transfer */ + + if ((pending & OTG_GINT_IPXFR) != 0) + { + usbhost_vtrace1(OTG_VTRACE1_GINT_IPXFR, 0); + stm32_gint_ipxfrisr(priv); + } + } + + /* We won't get here */ + + return OK; +} + +/**************************************************************************** + * Name: stm32_gint_enable and stm32_gint_disable + * + * Description: + * Respectively enable or disable the global OTG FS interrupt. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_gint_enable(void) +{ + uint32_t regval; + + /* Set the GINTMSK bit to unmask the interrupt */ + + regval = stm32_getreg(STM32_OTG_GAHBCFG); + regval |= OTG_GAHBCFG_GINTMSK; + stm32_putreg(STM32_OTG_GAHBCFG, regval); +} + +static void stm32_gint_disable(void) +{ + uint32_t regval; + + /* Clear the GINTMSK bit to mask the interrupt */ + + regval = stm32_getreg(STM32_OTG_GAHBCFG); + regval &= ~OTG_GAHBCFG_GINTMSK; + stm32_putreg(STM32_OTG_GAHBCFG, regval); +} + +/**************************************************************************** + * Name: stm32_hostinit_enable + * + * Description: + * Enable host interrupts. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void stm32_hostinit_enable(void) +{ + uint32_t regval; + + /* Disable all interrupts. */ + + stm32_putreg(STM32_OTG_GINTMSK, 0); + + /* Clear any pending interrupts. */ + + stm32_putreg(STM32_OTG_GINTSTS, 0xffffffff); + + /* Clear any pending USB OTG Interrupts (should be done elsewhere if OTG is supported) */ + + stm32_putreg(STM32_OTG_GOTGINT, 0xffffffff); + + /* Clear any pending USB OTG interrupts */ + + stm32_putreg(STM32_OTG_GINTSTS, 0xbfffffff); + + /* Enable the host interrupts */ + /* Common interrupts: + * + * OTG_GINT_WKUP : Resume/remote wakeup detected interrupt + * OTG_GINT_USBSUSP : USB suspend + */ + + regval = (OTG_GINT_WKUP | OTG_GINT_USBSUSP); + + /* If OTG were supported, we would need to enable the following as well: + * + * OTG_GINT_OTG : OTG interrupt + * OTG_GINT_SRQ : Session request/new session detected interrupt + * OTG_GINT_CIDSCHG : Connector ID status change + */ + + /* Host-specific interrupts + * + * OTG_GINT_SOF : Start of frame + * OTG_GINT_RXFLVL : RxFIFO non-empty + * OTG_GINT_IISOOXFR : Incomplete isochronous OUT transfer + * OTG_GINT_HPRT : Host port interrupt + * OTG_GINT_HC : Host channels interrupt + * OTG_GINT_DISC : Disconnect detected interrupt + */ + +#ifdef CONFIG_STM32F7_OTG_SOFINTR + regval |= (OTG_GINT_SOF | OTG_GINT_RXFLVL | OTG_GINT_IISOOXFR | + OTG_GINT_HPRT | OTG_GINT_HC | OTG_GINT_DISC); +#else + regval |= (OTG_GINT_RXFLVL | OTG_GINT_IPXFR | OTG_GINT_HPRT | + OTG_GINT_HC | OTG_GINT_DISC); +#endif + stm32_putreg(STM32_OTG_GINTMSK, regval); +} + +/**************************************************************************** + * Name: stm32_txfe_enable + * + * Description: + * Enable Tx FIFO empty interrupts. This is necessary when the entire + * transfer will not fit into Tx FIFO. The transfer will then be completed + * when the Tx FIFO is empty. NOTE: The Tx FIFO interrupt is disabled + * the fifo empty interrupt handler when the transfer is complete. + * + * Input Parameters: + * priv - Driver state structure reference + * chidx - The channel that requires the Tx FIFO empty interrupt + * + * Returned Value: + * None + * + * Assumptions: + * Called from user task context. Interrupts must be disabled to assure + * exclusive access to the GINTMSK register. + * + ****************************************************************************/ + +static void stm32_txfe_enable(FAR struct stm32_usbhost_s *priv, int chidx) +{ + FAR struct stm32_chan_s *chan = &priv->chan[chidx]; + irqstate_t flags; + uint32_t regval; + + /* Disable all interrupts so that we have exclusive access to the GINTMSK + * (it would be sufficent just to disable the GINT interrupt). + */ + + flags = enter_critical_section(); + + /* Should we enable the periodic or non-peridic Tx FIFO empty interrupts */ + + regval = stm32_getreg(STM32_OTG_GINTMSK); + switch (chan->eptype) + { + default: + case OTG_EPTYPE_CTRL: /* Non periodic transfer */ + case OTG_EPTYPE_BULK: + regval |= OTG_GINT_NPTXFE; + break; + + case OTG_EPTYPE_INTR: /* Periodic transfer */ + case OTG_EPTYPE_ISOC: + regval |= OTG_GINT_PTXFE; + break; + } + + /* Enable interrupts */ + + stm32_putreg(STM32_OTG_GINTMSK, regval); + leave_critical_section(flags); +} + +/**************************************************************************** + * USB Host Controller Operations + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_wait + * + * Description: + * Wait for a device to be connected or disconnected to/from a hub port. + * + * Input Parameters: + * conn - The USB host connection instance obtained as a parameter from the call to + * the USB driver initialization logic. + * hport - The location to return the hub port descriptor that detected the + * connection related event. + * + * Returned Values: + * Zero (OK) is returned on success when a device in connected or + * disconnected. This function will not return until either (1) a device is + * connected or disconnect to/from any hub port or until (2) some failure + * occurs. On a failure, a negated errno value is returned indicating the + * nature of the failure + * + * Assumptions: + * - Called from a single thread so no mutual exclusion is required. + * - Never called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_wait(FAR struct usbhost_connection_s *conn, + FAR struct usbhost_hubport_s **hport) +{ + FAR struct stm32_usbhost_s *priv = &g_usbhost; + struct usbhost_hubport_s *connport; + irqstate_t flags; + + /* Loop until a change in connection state is detected */ + + flags = enter_critical_section(); + for (; ; ) + { + /* Is there a change in the connection state of the single root hub + * port? + */ + + if (priv->change) + { + connport = &priv->rhport.hport; + + /* Yes. Remember the new state */ + + connport->connected = priv->connected; + priv->change = false; + + /* And return the root hub port */ + + *hport = connport; + leave_critical_section(flags); + + uinfo("RHport Connected: %s\n", connport->connected ? "YES" : "NO"); + return OK; + } + +#ifdef CONFIG_USBHOST_HUB + /* Is a device connected to an external hub? */ + + if (priv->hport) + { + /* Yes.. return the external hub port */ + + connport = (struct usbhost_hubport_s *)priv->hport; + priv->hport = NULL; + + *hport = connport; + leave_critical_section(flags); + + uinfo("Hub port Connected: %s\n", connport->connected ? "YES" : "NO"); + return OK; + } +#endif + + /* Wait for the next connection event */ + + priv->pscwait = true; + stm32_takesem(&priv->pscsem); + } +} + +/**************************************************************************** + * Name: stm32_enumerate + * + * Description: + * Enumerate the connected device. As part of this enumeration process, + * the driver will (1) get the device's configuration descriptor, (2) + * extract the class ID info from the configuration descriptor, (3) call + * usbhost_findclass() to find the class that supports this device, (4) + * call the create() method on the struct usbhost_registry_s interface + * to get a class instance, and finally (5) call the connect() method + * of the struct usbhost_class_s interface. After that, the class is in + * charge of the sequence of operations. + * + * Input Parameters: + * conn - The USB host connection instance obtained as a parameter from + * the call to the USB driver initialization logic. + * hport - The descriptor of the hub port that has the newly connected + * device. + * + * Returned Values: + * On success, zero (OK) is returned. On a failure, a negated errno value is + * returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_rh_enumerate(FAR struct stm32_usbhost_s *priv, + FAR struct usbhost_connection_s *conn, + FAR struct usbhost_hubport_s *hport) +{ + uint32_t regval; + int ret; + + DEBUGASSERT(conn != NULL && hport != NULL && hport->port == 0); + + /* Are we connected to a device? The caller should have called the wait() + * method first to be assured that a device is connected. + */ + + while (!priv->connected) + { + /* No, return an error */ + + usbhost_trace1(OTG_TRACE1_DEVDISCONN, 0); + return -ENODEV; + } + + DEBUGASSERT(priv->smstate == SMSTATE_ATTACHED); + + /* USB 2.0 spec says at least 50ms delay before port reset. We wait 100ms. */ + + usleep(100*1000); + + /* Reset the host port */ + + stm32_portreset(priv); + + /* Get the current device speed */ + + regval = stm32_getreg(STM32_OTG_HPRT); + if ((regval & OTG_HPRT_PSPD_MASK) == OTG_HPRT_PSPD_LS) + { + priv->rhport.hport.speed = USB_SPEED_LOW; + } + else + { + priv->rhport.hport.speed = USB_SPEED_FULL; + } + + /* Allocate and initialize the root hub port EP0 channels */ + + ret = stm32_ctrlchan_alloc(priv, 0, 0, priv->rhport.hport.speed, &priv->ep0); + if (ret < 0) + { + uerr("ERROR: Failed to allocate a control endpoint: %d\n", ret); + } + + return ret; +} + +static int stm32_enumerate(FAR struct usbhost_connection_s *conn, + FAR struct usbhost_hubport_s *hport) +{ + FAR struct stm32_usbhost_s *priv = &g_usbhost; + int ret; + + DEBUGASSERT(hport); + + /* If this is a connection on the root hub, then we need to go to + * little more effort to get the device speed. If it is a connection + * on an external hub, then we already have that information. + */ + +#ifdef CONFIG_USBHOST_HUB + if (ROOTHUB(hport)) +#endif + { + ret = stm32_rh_enumerate(priv, conn, hport); + if (ret < 0) + { + return ret; + } + } + + /* Then let the common usbhost_enumerate do the real enumeration. */ + + uinfo("Enumerate the device\n"); + priv->smstate = SMSTATE_ENUM; + ret = usbhost_enumerate(hport, &hport->devclass); + + /* The enumeration may fail either because of some HCD interfaces failure + * or because the device class is not supported. In either case, we just + * need to perform the disconnection operation and make ready for a new + * enumeration. + */ + + if (ret < 0) + { + /* Return to the disconnected state */ + + uerr("ERROR: Enumeration failed: %d\n", ret); + stm32_gint_disconnected(priv); + } + + return ret; +} + +/************************************************************************************ + * Name: stm32_ep0configure + * + * Description: + * Configure endpoint 0. This method is normally used internally by the + * enumerate() method but is made available at the interface to support an + * external implementation of the enumeration logic. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the call to + * the class create() method. + * ep0 - The (opaque) EP0 endpoint instance + * funcaddr - The USB address of the function containing the endpoint that EP0 + * controls + * speed - The speed of the port USB_SPEED_LOW, _FULL, or _HIGH + * maxpacketsize - The maximum number of bytes that can be sent to or + * received from the endpoint in a single data packet + * + * Returned Values: + * On success, zero (OK) is returned. On a failure, a negated errno value is + * returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ************************************************************************************/ + +static int stm32_ep0configure(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0, + uint8_t funcaddr, uint8_t speed, + uint16_t maxpacketsize) +{ + FAR struct stm32_usbhost_s *priv = (FAR struct stm32_usbhost_s *)drvr; + FAR struct stm32_ctrlinfo_s *ep0info = (FAR struct stm32_ctrlinfo_s *)ep0; + FAR struct stm32_chan_s *chan; + + DEBUGASSERT(drvr != NULL && ep0info != NULL && funcaddr < 128 && + maxpacketsize <= 64); + + /* We must have exclusive access to the USB host hardware and state structures */ + + stm32_takesem(&priv->exclsem); + + /* Configure the EP0 OUT channel */ + + chan = &priv->chan[ep0info->outndx]; + chan->funcaddr = funcaddr; + chan->speed = speed; + chan->maxpacket = maxpacketsize; + + stm32_chan_configure(priv, ep0info->outndx); + + /* Configure the EP0 IN channel */ + + chan = &priv->chan[ep0info->inndx]; + chan->funcaddr = funcaddr; + chan->speed = speed; + chan->maxpacket = maxpacketsize; + + stm32_chan_configure(priv, ep0info->inndx); + + stm32_givesem(&priv->exclsem); + return OK; +} + +/************************************************************************************ + * Name: stm32_epalloc + * + * Description: + * Allocate and configure one endpoint. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the call to + * the class create() method. + * epdesc - Describes the endpoint to be allocated. + * ep - A memory location provided by the caller in which to receive the + * allocated endpoint descriptor. + * + * Returned Values: + * On success, zero (OK) is returned. On a failure, a negated errno value is + * returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ************************************************************************************/ + +static int stm32_epalloc(FAR struct usbhost_driver_s *drvr, + FAR const struct usbhost_epdesc_s *epdesc, + FAR usbhost_ep_t *ep) +{ + FAR struct stm32_usbhost_s *priv = (FAR struct stm32_usbhost_s *)drvr; + int ret; + + /* Sanity check. NOTE that this method should only be called if a device is + * connected (because we need a valid low speed indication). + */ + + DEBUGASSERT(drvr != 0 && epdesc != NULL && ep != NULL); + + /* We must have exclusive access to the USB host hardware and state structures */ + + stm32_takesem(&priv->exclsem); + + /* Handler control pipes differently from other endpoint types. This is + * because the normal, "transfer" endpoints are unidirectional an require + * only a single channel. Control endpoints, however, are bi-diretional + * and require two channels, one for the IN and one for the OUT direction. + */ + + if (epdesc->xfrtype == OTG_EPTYPE_CTRL) + { + ret = stm32_ctrlep_alloc(priv, epdesc, ep); + } + else + { + ret = stm32_xfrep_alloc(priv, epdesc, ep); + } + + stm32_givesem(&priv->exclsem); + return ret; +} + +/************************************************************************************ + * Name: stm32_epfree + * + * Description: + * Free and endpoint previously allocated by DRVR_EPALLOC. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the call to + * the class create() method. + * ep - The endpoint to be freed. + * + * Returned Values: + * On success, zero (OK) is returned. On a failure, a negated errno value is + * returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ************************************************************************************/ + +static int stm32_epfree(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep) +{ + FAR struct stm32_usbhost_s *priv = (FAR struct stm32_usbhost_s *)drvr; + + DEBUGASSERT(priv); + + /* We must have exclusive access to the USB host hardware and state structures */ + + stm32_takesem(&priv->exclsem); + + /* A single channel is represent by an index in the range of 0 to STM32_MAX_TX_FIFOS. + * Otherwise, the ep must be a pointer to an allocated control endpoint structure. + */ + + if ((uintptr_t)ep < STM32_MAX_TX_FIFOS) + { + /* Halt the channel and mark the channel available */ + + stm32_chan_free(priv, (int)ep); + } + else + { + /* Halt both control channel and mark the channels available */ + + FAR struct stm32_ctrlinfo_s *ctrlep = (FAR struct stm32_ctrlinfo_s *)ep; + stm32_chan_free(priv, ctrlep->inndx); + stm32_chan_free(priv, ctrlep->outndx); + + /* And free the control endpoint container */ + + kmm_free(ctrlep); + } + + stm32_givesem(&priv->exclsem); + return OK; +} + +/**************************************************************************** + * Name: stm32_alloc + * + * Description: + * Some hardware supports special memory in which request and descriptor data can + * be accessed more efficiently. This method provides a mechanism to allocate + * the request/descriptor memory. If the underlying hardware does not support + * such "special" memory, this functions may simply map to kmm_malloc. + * + * This interface was optimized under a particular assumption. It was assumed + * that the driver maintains a pool of small, pre-allocated buffers for descriptor + * traffic. NOTE that size is not an input, but an output: The size of the + * pre-allocated buffer is returned. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the call to + * the class create() method. + * buffer - The address of a memory location provided by the caller in which to + * return the allocated buffer memory address. + * maxlen - The address of a memory location provided by the caller in which to + * return the maximum size of the allocated buffer memory. + * + * Returned Values: + * On success, zero (OK) is returned. On a failure, a negated errno value is + * returned indicating the nature of the failure + * + * Assumptions: + * - Called from a single thread so no mutual exclusion is required. + * - Never called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_alloc(FAR struct usbhost_driver_s *drvr, + FAR uint8_t **buffer, FAR size_t *maxlen) +{ + FAR uint8_t *alloc; + + DEBUGASSERT(drvr && buffer && maxlen); + + /* There is no special memory requirement for the STM32. */ + + alloc = (FAR uint8_t *)kmm_malloc(CONFIG_STM32F7_OTG_DESCSIZE); + if (!alloc) + { + return -ENOMEM; + } + + /* Return the allocated address and size of the descriptor buffer */ + + *buffer = alloc; + *maxlen = CONFIG_STM32F7_OTG_DESCSIZE; + return OK; +} + +/**************************************************************************** + * Name: stm32_free + * + * Description: + * Some hardware supports special memory in which request and descriptor data can + * be accessed more efficiently. This method provides a mechanism to free that + * request/descriptor memory. If the underlying hardware does not support + * such "special" memory, this functions may simply map to kmm_free(). + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the call to + * the class create() method. + * buffer - The address of the allocated buffer memory to be freed. + * + * Returned Values: + * On success, zero (OK) is returned. On a failure, a negated errno value is + * returned indicating the nature of the failure + * + * Assumptions: + * - Never called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_free(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer) +{ + /* There is no special memory requirement */ + + DEBUGASSERT(drvr && buffer); + kmm_free(buffer); + return OK; +} + +/************************************************************************************ + * Name: stm32_ioalloc + * + * Description: + * Some hardware supports special memory in which larger IO buffers can + * be accessed more efficiently. This method provides a mechanism to allocate + * the request/descriptor memory. If the underlying hardware does not support + * such "special" memory, this functions may simply map to kmm_malloc. + * + * This interface differs from DRVR_ALLOC in that the buffers are variable-sized. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the call to + * the class create() method. + * buffer - The address of a memory location provided by the caller in which to + * return the allocated buffer memory address. + * buflen - The size of the buffer required. + * + * Returned Values: + * On success, zero (OK) is returned. On a failure, a negated errno value is + * returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ************************************************************************************/ + +static int stm32_ioalloc(FAR struct usbhost_driver_s *drvr, + FAR uint8_t **buffer, size_t buflen) +{ + FAR uint8_t *alloc; + + DEBUGASSERT(drvr && buffer && buflen > 0); + + /* There is no special memory requirement */ + + alloc = (FAR uint8_t *)kmm_malloc(buflen); + if (!alloc) + { + return -ENOMEM; + } + + /* Return the allocated buffer */ + + *buffer = alloc; + return OK; +} + +/************************************************************************************ + * Name: stm32_iofree + * + * Description: + * Some hardware supports special memory in which IO data can be accessed more + * efficiently. This method provides a mechanism to free that IO buffer + * memory. If the underlying hardware does not support such "special" memory, + * this functions may simply map to kmm_free(). + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the call to + * the class create() method. + * buffer - The address of the allocated buffer memory to be freed. + * + * Returned Values: + * On success, zero (OK) is returned. On a failure, a negated errno value is + * returned indicating the nature of the failure + * + * Assumptions: + * This function will *not* be called from an interrupt handler. + * + ************************************************************************************/ + +static int stm32_iofree(FAR struct usbhost_driver_s *drvr, FAR uint8_t *buffer) +{ + /* There is no special memory requirement */ + + DEBUGASSERT(drvr && buffer); + kmm_free(buffer); + return OK; +} + +/**************************************************************************** + * Name: stm32_ctrlin and stm32_ctrlout + * + * Description: + * Process a IN or OUT request on the control endpoint. These methods + * will enqueue the request and wait for it to complete. Only one transfer may be + * queued; Neither these methods nor the transfer() method can be called again + * until the control transfer functions returns. + * + * These are blocking methods; these functions will not return until the + * control transfer has completed. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the call to + * the class create() method. + * ep0 - The control endpoint to send/receive the control request. + * req - Describes the request to be sent. This request must lie in memory + * created by DRVR_ALLOC. + * buffer - A buffer used for sending the request and for returning any + * responses. This buffer must be large enough to hold the length value + * in the request description. buffer must have been allocated using DRVR_ALLOC. + * + * NOTE: On an IN transaction, req and buffer may refer to the same allocated + * memory. + * + * Returned Values: + * On success, zero (OK) is returned. On a failure, a negated errno value is + * returned indicating the nature of the failure + * + * Assumptions: + * - Called from a single thread so no mutual exclusion is required. + * - Never called from an interrupt handler. + * + ****************************************************************************/ + +static int stm32_ctrlin(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0, + FAR const struct usb_ctrlreq_s *req, + FAR uint8_t *buffer) +{ + FAR struct stm32_usbhost_s *priv = (FAR struct stm32_usbhost_s *)drvr; + FAR struct stm32_ctrlinfo_s *ep0info = (FAR struct stm32_ctrlinfo_s *)ep0; + uint16_t buflen; + systime_t start; + systime_t elapsed; + int retries; + int ret; + + DEBUGASSERT(priv != NULL && ep0info != NULL && req != NULL); + usbhost_vtrace2(OTG_VTRACE2_CTRLIN, req->type, req->req); + uinfo("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n", + req->type, req->req, req->value[1], req->value[0], + req->index[1], req->index[0], req->len[1], req->len[0]); + + /* Extract values from the request */ + + buflen = stm32_getle16(req->len); + + /* We must have exclusive access to the USB host hardware and state structures */ + + stm32_takesem(&priv->exclsem); + + /* Loop, retrying until the retry time expires */ + + for (retries = 0; retries < STM32_RETRY_COUNT; retries++) + { + /* Send the SETUP request */ + + ret = stm32_ctrl_sendsetup(priv, ep0info, req); + if (ret < 0) + { + usbhost_trace1(OTG_TRACE1_SENDSETUP, -ret); + continue; + } + + /* Get the start time. Loop again until the timeout expires */ + + start = clock_systimer(); + do + { + /* Handle the IN data phase (if any) */ + + if (buflen > 0) + { + ret = stm32_ctrl_recvdata(priv, ep0info, buffer, buflen); + if (ret < 0) + { + usbhost_trace1(OTG_TRACE1_RECVDATA, -ret); + } + } + + /* Handle the status OUT phase */ + + if (ret == OK) + { + priv->chan[ep0info->outndx].outdata1 ^= true; + ret = stm32_ctrl_senddata(priv, ep0info, NULL, 0); + if (ret == OK) + { + /* All success transactions exit here */ + + stm32_givesem(&priv->exclsem); + return OK; + } + + usbhost_trace1(OTG_TRACE1_SENDDATA, ret < 0 ? -ret : ret); + } + + /* Get the elapsed time (in frames) */ + + elapsed = clock_systimer() - start; + } + while (elapsed < STM32_DATANAK_DELAY); + } + + /* All failures exit here after all retries and timeouts have been exhausted */ + + stm32_givesem(&priv->exclsem); + return -ETIMEDOUT; +} + +static int stm32_ctrlout(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep0, + FAR const struct usb_ctrlreq_s *req, + FAR const uint8_t *buffer) +{ + FAR struct stm32_usbhost_s *priv = (FAR struct stm32_usbhost_s *)drvr; + FAR struct stm32_ctrlinfo_s *ep0info = (FAR struct stm32_ctrlinfo_s *)ep0; + uint16_t buflen; + systime_t start; + systime_t elapsed; + int retries; + int ret; + + DEBUGASSERT(priv != NULL && ep0info != NULL && req != NULL); + usbhost_vtrace2(OTG_VTRACE2_CTRLOUT, req->type, req->req); + uinfo("type:%02x req:%02x value:%02x%02x index:%02x%02x len:%02x%02x\n", + req->type, req->req, req->value[1], req->value[0], + req->index[1], req->index[0], req->len[1], req->len[0]); + + /* Extract values from the request */ + + buflen = stm32_getle16(req->len); + + /* We must have exclusive access to the USB host hardware and state structures */ + + stm32_takesem(&priv->exclsem); + + /* Loop, retrying until the retry time expires */ + + for (retries = 0; retries < STM32_RETRY_COUNT; retries++) + { + /* Send the SETUP request */ + + ret = stm32_ctrl_sendsetup(priv, ep0info, req); + if (ret < 0) + { + usbhost_trace1(OTG_TRACE1_SENDSETUP, -ret); + continue; + } + + /* Get the start time. Loop again until the timeout expires */ + + start = clock_systimer(); + do + { + /* Handle the data OUT phase (if any) */ + + if (buflen > 0) + { + /* Start DATA out transfer (only one DATA packet) */ + + priv->chan[ep0info->outndx].outdata1 = true; + ret = stm32_ctrl_senddata(priv, ep0info, NULL, 0); + if (ret < 0) + { + usbhost_trace1(OTG_TRACE1_SENDDATA, -ret); + } + } + + /* Handle the status IN phase */ + + if (ret == OK) + { + ret = stm32_ctrl_recvdata(priv, ep0info, NULL, 0); + if (ret == OK) + { + /* All success transactins exit here */ + + stm32_givesem(&priv->exclsem); + return OK; + } + + usbhost_trace1(OTG_TRACE1_RECVDATA, ret < 0 ? -ret : ret); + } + + /* Get the elapsed time (in frames) */ + + elapsed = clock_systimer() - start; + } + while (elapsed < STM32_DATANAK_DELAY); + } + + /* All failures exit here after all retries and timeouts have been exhausted */ + + stm32_givesem(&priv->exclsem); + return -ETIMEDOUT; +} + +/**************************************************************************** + * Name: stm32_transfer + * + * Description: + * Process a request to handle a transfer descriptor. This method will + * enqueue the transfer request, blocking until the transfer completes. Only + * one transfer may be queued; Neither this method nor the ctrlin or + * ctrlout methods can be called again until this function returns. + * + * This is a blocking method; this functions will not return until the + * transfer has completed. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the call to + * the class create() method. + * ep - The IN or OUT endpoint descriptor for the device endpoint on which to + * perform the transfer. + * buffer - A buffer containing the data to be sent (OUT endpoint) or received + * (IN endpoint). buffer must have been allocated using DRVR_ALLOC + * buflen - The length of the data to be sent or received. + * + * Returned Values: + * On success, a non-negative value is returned that indicates the number + * of bytes successfully transferred. On a failure, a negated errno value is + * returned that indicates the nature of the failure: + * + * EAGAIN - If devices NAKs the transfer (or NYET or other error where + * it may be appropriate to restart the entire transaction). + * EPERM - If the endpoint stalls + * EIO - On a TX or data toggle error + * EPIPE - Overrun errors + * + * Assumptions: + * - Called from a single thread so no mutual exclusion is required. + * - Never called from an interrupt handler. + * + ****************************************************************************/ + +static ssize_t stm32_transfer(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep, + FAR uint8_t *buffer, size_t buflen) +{ + FAR struct stm32_usbhost_s *priv = (FAR struct stm32_usbhost_s *)drvr; + unsigned int chidx = (unsigned int)ep; + ssize_t nbytes; + + uinfo("chidx: %d buflen: %d\n", (unsigned int)ep, buflen); + + DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0); + + /* We must have exclusive access to the USB host hardware and state structures */ + + stm32_takesem(&priv->exclsem); + + /* Handle IN and OUT transfer slightly differently */ + + if (priv->chan[chidx].in) + { + nbytes = stm32_in_transfer(priv, chidx, buffer, buflen); + } + else + { + nbytes = stm32_out_transfer(priv, chidx, buffer, buflen); + } + + stm32_givesem(&priv->exclsem); + return nbytes; +} + +/**************************************************************************** + * Name: stm32_asynch + * + * Description: + * Process a request to handle a transfer descriptor. This method will + * enqueue the transfer request and return immediately. When the transfer + * completes, the the callback will be invoked with the provided transfer. + * This method is useful for receiving interrupt transfers which may come + * infrequently. + * + * Only one transfer may be queued; Neither this method nor the ctrlin or + * ctrlout methods can be called again until the transfer completes. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the call to + * the class create() method. + * ep - The IN or OUT endpoint descriptor for the device endpoint on which to + * perform the transfer. + * buffer - A buffer containing the data to be sent (OUT endpoint) or received + * (IN endpoint). buffer must have been allocated using DRVR_ALLOC + * buflen - The length of the data to be sent or received. + * callback - This function will be called when the transfer completes. + * arg - The arbitrary parameter that will be passed to the callback function + * when the transfer completes. + * + * Returned Values: + * On success, zero (OK) is returned. On a failure, a negated errno value is + * returned indicating the nature of the failure + * + * Assumptions: + * - Called from a single thread so no mutual exclusion is required. + * - Never called from an interrupt handler. + * + ****************************************************************************/ + +#ifdef CONFIG_USBHOST_ASYNCH +static int stm32_asynch(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep, + FAR uint8_t *buffer, size_t buflen, + usbhost_asynch_t callback, FAR void *arg) +{ + FAR struct stm32_usbhost_s *priv = (FAR struct stm32_usbhost_s *)drvr; + unsigned int chidx = (unsigned int)ep; + int ret; + + uinfo("chidx: %d buflen: %d\n", (unsigned int)ep, buflen); + + DEBUGASSERT(priv && buffer && chidx < STM32_MAX_TX_FIFOS && buflen > 0); + + /* We must have exclusive access to the USB host hardware and state structures */ + + stm32_takesem(&priv->exclsem); + + /* Handle IN and OUT transfer slightly differently */ + + if (priv->chan[chidx].in) + { + ret = stm32_in_asynch(priv, chidx, buffer, buflen, callback, arg); + } + else + { + ret = stm32_out_asynch(priv, chidx, buffer, buflen, callback, arg); + } + + stm32_givesem(&priv->exclsem); + return ret; +} +#endif /* CONFIG_USBHOST_ASYNCH */ + +/************************************************************************************ + * Name: stm32_cancel + * + * Description: + * Cancel a pending transfer on an endpoint. Cancelled synchronous or + * asynchronous transfer will complete normally with the error -ESHUTDOWN. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the call to + * the class create() method. + * ep - The IN or OUT endpoint descriptor for the device endpoint on which an + * asynchronous transfer should be transferred. + * + * Returned Values: + * On success, zero (OK) is returned. On a failure, a negated errno value is + * returned indicating the nature of the failure. + * + ************************************************************************************/ + +static int stm32_cancel(FAR struct usbhost_driver_s *drvr, usbhost_ep_t ep) +{ + FAR struct stm32_usbhost_s *priv = (FAR struct stm32_usbhost_s *)drvr; + FAR struct stm32_chan_s *chan; + unsigned int chidx = (unsigned int)ep; + irqstate_t flags; + + uinfo("chidx: %u: %d\n", chidx); + + DEBUGASSERT(priv && chidx < STM32_MAX_TX_FIFOS); + chan = &priv->chan[chidx]; + + /* We need to disable interrupts to avoid race conditions with the asynchronous + * completion of the transfer being cancelled. + */ + + flags = enter_critical_section(); + + /* Halt the channel */ + + stm32_chan_halt(priv, chidx, CHREASON_CANCELLED); + chan->result = -ESHUTDOWN; + + /* Is there a thread waiting for this transfer to complete? */ + + if (chan->waiter) + { +#ifdef CONFIG_USBHOST_ASYNCH + /* Yes.. there should not also be a callback scheduled */ + + DEBUGASSERT(chan->callback == NULL); +#endif + + /* Wake'em up! */ + + stm32_givesem(&chan->waitsem); + chan->waiter = false; + } + +#ifdef CONFIG_USBHOST_ASYNCH + /* No.. is an asynchronous callback expected when the transfer + * completes? + */ + + else if (chan->callback) + { + usbhost_asynch_t callback; + FAR void *arg; + + /* Extract the callback information */ + + callback = chan->callback; + arg = chan->arg; + + chan->callback = NULL; + chan->arg = NULL; + chan->xfrd = 0; + + /* Then perform the callback */ + + callback(arg, -ESHUTDOWN); + } +#endif + + leave_critical_section(flags); + return OK; +} + +/************************************************************************************ + * Name: stm32_connect + * + * Description: + * New connections may be detected by an attached hub. This method is the + * mechanism that is used by the hub class to introduce a new connection + * and port description to the system. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the call to + * the class create() method. + * hport - The descriptor of the hub port that detected the connection + * related event + * connected - True: device connected; false: device disconnected + * + * Returned Values: + * On success, zero (OK) is returned. On a failure, a negated errno value is + * returned indicating the nature of the failure. + * + ************************************************************************************/ + +#ifdef CONFIG_USBHOST_HUB +static int stm32_connect(FAR struct usbhost_driver_s *drvr, + FAR struct usbhost_hubport_s *hport, + bool connected) +{ + FAR struct stm32_usbhost_s *priv = (FAR struct stm32_usbhost_s *)drvr; + irqstate_t flags; + + DEBUGASSERT(priv != NULL && hport != NULL); + + /* Set the connected/disconnected flag */ + + hport->connected = connected; + uinfo("Hub port %d connected: %s\n", hport->port, connected ? "YES" : "NO"); + + /* Report the connection event */ + + flags = enter_critical_section(); + priv->hport = hport; + if (priv->pscwait) + { + priv->pscwait = false; + stm32_givesem(&priv->pscsem); + } + + leave_critical_section(flags); + return OK; +} +#endif + +/**************************************************************************** + * Name: stm32_disconnect + * + * Description: + * Called by the class when an error occurs and driver has been disconnected. + * The USB host driver should discard the handle to the class instance (it is + * stale) and not attempt any further interaction with the class driver instance + * (until a new instance is received from the create() method). The driver + * should not called the class' disconnected() method. + * + * Input Parameters: + * drvr - The USB host driver instance obtained as a parameter from the call to + * the class create() method. + * hport - The port from which the device is being disconnected. Might be a port + * on a hub. + * + * Returned Values: + * None + * + * Assumptions: + * - Only a single class bound to a single device is supported. + * - Never called from an interrupt handler. + * + ****************************************************************************/ + +static void stm32_disconnect(FAR struct usbhost_driver_s *drvr, + FAR struct usbhost_hubport_s *hport) +{ + DEBUGASSERT(hport != NULL); + hport->devclass = NULL; +} + +/**************************************************************************** + * Initialization + ****************************************************************************/ +/**************************************************************************** + * Name: stm32_portreset + * + * Description: + * Reset the USB host port. + * + * NOTE: "Before starting to drive a USB reset, the application waits for the + * OTG interrupt triggered by the debounce done bit (DBCDNE bit in + * OTG_FS_GOTGINT), which indicates that the bus is stable again after the + * electrical debounce caused by the attachment of a pull-up resistor on DP + * (FS) or DM (LS). + * + * Input Parameters: + * priv -- USB host driver private data structure. + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void stm32_portreset(FAR struct stm32_usbhost_s *priv) +{ + uint32_t regval; + + regval = stm32_getreg(STM32_OTG_HPRT); + regval &= ~(OTG_HPRT_PENA | OTG_HPRT_PCDET | OTG_HPRT_PENCHNG | + OTG_HPRT_POCCHNG); + regval |= OTG_HPRT_PRST; + stm32_putreg(STM32_OTG_HPRT, regval); + + up_mdelay(20); + + regval &= ~OTG_HPRT_PRST; + stm32_putreg(STM32_OTG_HPRT, regval); + + up_mdelay(20); +} + +/**************************************************************************** + * Name: stm32_flush_txfifos + * + * Description: + * Flush the selected Tx FIFO. + * + * Input Parameters: + * txfnum -- USB host driver private data structure. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void stm32_flush_txfifos(uint32_t txfnum) +{ + uint32_t regval; + uint32_t timeout; + + /* Initiate the TX FIFO flush operation */ + + regval = OTG_GRSTCTL_TXFFLSH | txfnum; + stm32_putreg(STM32_OTG_GRSTCTL, regval); + + /* Wait for the FLUSH to complete */ + + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) + { + regval = stm32_getreg(STM32_OTG_GRSTCTL); + if ((regval & OTG_GRSTCTL_TXFFLSH) == 0) + { + break; + } + } + + /* Wait for 3 PHY Clocks */ + + up_udelay(3); +} + +/**************************************************************************** + * Name: stm32_flush_rxfifo + * + * Description: + * Flush the Rx FIFO. + * + * Input Parameters: + * priv -- USB host driver private data structure. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void stm32_flush_rxfifo(void) +{ + uint32_t regval; + uint32_t timeout; + + /* Initiate the RX FIFO flush operation */ + + stm32_putreg(STM32_OTG_GRSTCTL, OTG_GRSTCTL_RXFFLSH); + + /* Wait for the FLUSH to complete */ + + for (timeout = 0; timeout < STM32_FLUSH_DELAY; timeout++) + { + regval = stm32_getreg(STM32_OTG_GRSTCTL); + if ((regval & OTG_GRSTCTL_RXFFLSH) == 0) + { + break; + } + } + + /* Wait for 3 PHY Clocks */ + + up_udelay(3); +} + +/**************************************************************************** + * Name: stm32_vbusdrive + * + * Description: + * Drive the Vbus +5V. + * + * Input Parameters: + * priv - USB host driver private data structure. + * state - True: Drive, False: Don't drive + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void stm32_vbusdrive(FAR struct stm32_usbhost_s *priv, bool state) +{ + uint32_t regval; + + /* Enable/disable the external charge pump */ + + stm32_usbhost_vbusdrive(0, state); + + /* Turn on the Host port power. */ + + regval = stm32_getreg(STM32_OTG_HPRT); + regval &= ~(OTG_HPRT_PENA | OTG_HPRT_PCDET | OTG_HPRT_PENCHNG | + OTG_HPRT_POCCHNG); + + if (((regval & OTG_HPRT_PPWR) == 0) && state) + { + regval |= OTG_HPRT_PPWR; + stm32_putreg(STM32_OTG_HPRT, regval); + } + + if (((regval & OTG_HPRT_PPWR) != 0) && !state) + { + regval &= ~OTG_HPRT_PPWR; + stm32_putreg(STM32_OTG_HPRT, regval); + } + + up_mdelay(200); +} + +/**************************************************************************** + * Name: stm32_host_initialize + * + * Description: + * Initialize/re-initialize hardware for host mode operation. At present, + * this function is called only from stm32_hw_initialize(). But if OTG mode + * were supported, this function would also be called to swtich between + * host and device modes on a connector ID change interrupt. + * + * Input Parameters: + * priv -- USB host driver private data structure. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static void stm32_host_initialize(FAR struct stm32_usbhost_s *priv) +{ + uint32_t regval; + uint32_t offset; + int i; + + /* Restart the PHY Clock */ + + stm32_putreg(STM32_OTG_PCGCCTL, 0); + + /* Initialize Host Configuration (HCFG) register */ + + regval = stm32_getreg(STM32_OTG_HCFG); + regval &= ~OTG_HCFG_FSLSPCS_MASK; + regval |= OTG_HCFG_FSLSPCS_FS48MHz; + stm32_putreg(STM32_OTG_HCFG, regval); + + /* Reset the host port */ + + stm32_portreset(priv); + + /* Clear the FS-/LS-only support bit in the HCFG register */ + + regval = stm32_getreg(STM32_OTG_HCFG); + regval &= ~OTG_HCFG_FSLSS; + stm32_putreg(STM32_OTG_HCFG, regval); + + /* Carve up FIFO memory for the Rx FIFO and the periodic and non-periodic Tx FIFOs */ + /* Configure Rx FIFO size (GRXFSIZ) */ + + stm32_putreg(STM32_OTG_GRXFSIZ, CONFIG_STM32F7_OTG_RXFIFO_SIZE); + offset = CONFIG_STM32F7_OTG_RXFIFO_SIZE; + + /* Setup the host non-periodic Tx FIFO size (HNPTXFSIZ) */ + + regval = (offset | (CONFIG_STM32F7_OTG_NPTXFIFO_SIZE << OTG_HNPTXFSIZ_NPTXFD_SHIFT)); + stm32_putreg(STM32_OTG_HNPTXFSIZ, regval); + offset += CONFIG_STM32F7_OTG_NPTXFIFO_SIZE; + + /* Set up the host periodic Tx fifo size register (HPTXFSIZ) */ + + regval = (offset | (CONFIG_STM32F7_OTG_PTXFIFO_SIZE << OTG_HPTXFSIZ_PTXFD_SHIFT)); + stm32_putreg(STM32_OTG_HPTXFSIZ, regval); + + /* If OTG were supported, we sould need to clear HNP enable bit in the + * USB_OTG control register about here. + */ + + /* Flush all FIFOs */ + + stm32_flush_txfifos(OTG_GRSTCTL_TXFNUM_HALL); + stm32_flush_rxfifo(); + + /* Clear all pending HC Interrupts */ + + for (i = 0; i < STM32_NHOST_CHANNELS; i++) + { + stm32_putreg(STM32_OTG_HCINT(i), 0xffffffff); + stm32_putreg(STM32_OTG_HCINTMSK(i), 0); + } + + /* Driver Vbus +5V (the smoke test). Should be done elsewhere in OTG + * mode. + */ + + stm32_vbusdrive(priv, true); + + /* Enable host interrupts */ + + stm32_hostinit_enable(); +} + +/**************************************************************************** + * Name: stm32_sw_initialize + * + * Description: + * One-time setup of the host driver state structure. + * + * Input Parameters: + * priv -- USB host driver private data structure. + * + * Returned Value: + * None. + * + ****************************************************************************/ + +static inline void stm32_sw_initialize(FAR struct stm32_usbhost_s *priv) +{ + FAR struct usbhost_driver_s *drvr; + FAR struct usbhost_hubport_s *hport; + int i; + + /* Initialize the device operations */ + + drvr = &priv->drvr; + drvr->ep0configure = stm32_ep0configure; + drvr->epalloc = stm32_epalloc; + drvr->epfree = stm32_epfree; + drvr->alloc = stm32_alloc; + drvr->free = stm32_free; + drvr->ioalloc = stm32_ioalloc; + drvr->iofree = stm32_iofree; + drvr->ctrlin = stm32_ctrlin; + drvr->ctrlout = stm32_ctrlout; + drvr->transfer = stm32_transfer; +#ifdef CONFIG_USBHOST_ASYNCH + drvr->asynch = stm32_asynch; +#endif + drvr->cancel = stm32_cancel; +#ifdef CONFIG_USBHOST_HUB + drvr->connect = stm32_connect; +#endif + drvr->disconnect = stm32_disconnect; + + /* Initialize the public port representation */ + + hport = &priv->rhport.hport; + hport->drvr = drvr; +#ifdef CONFIG_USBHOST_HUB + hport->parent = NULL; +#endif + hport->ep0 = (usbhost_ep_t)&priv->ep0; + hport->speed = USB_SPEED_FULL; + + /* Initialize function address generation logic */ + + usbhost_devaddr_initialize(&priv->rhport); + + /* Initialize semaphores */ + + sem_init(&priv->pscsem, 0, 0); + sem_init(&priv->exclsem, 0, 1); + + /* Initialize the driver state data */ + + priv->smstate = SMSTATE_DETACHED; + priv->connected = false; + priv->change = false; + + /* Put all of the channels back in their initial, allocated state */ + + memset(priv->chan, 0, STM32_MAX_TX_FIFOS * sizeof(struct stm32_chan_s)); + + /* Initialize each channel */ + + for (i = 0; i < STM32_MAX_TX_FIFOS; i++) + { + FAR struct stm32_chan_s *chan = &priv->chan[i]; + chan->chidx = i; + sem_init(&chan->waitsem, 0, 0); + } +} + +/**************************************************************************** + * Name: stm32_hw_initialize + * + * Description: + * One-time setup of the host controller harware for normal operations. + * + * Input Parameters: + * priv -- USB host driver private data structure. + * + * Returned Value: + * Zero on success; a negated errno value on failure. + * + ****************************************************************************/ + +static inline int stm32_hw_initialize(FAR struct stm32_usbhost_s *priv) +{ + uint32_t regval; + unsigned long timeout; + + /* Set the PHYSEL bit in the GUSBCFG register to select the OTG FS serial + * transceiver: "This bit is always 1 with write-only access" + */ + + regval = stm32_getreg(STM32_OTG_GUSBCFG); + regval |= OTG_GUSBCFG_PHYSEL; + stm32_putreg(STM32_OTG_GUSBCFG, regval); + + /* Reset after a PHY select and set Host mode. First, wait for AHB master + * IDLE state. + */ + + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) + { + up_udelay(3); + regval = stm32_getreg(STM32_OTG_GRSTCTL); + if ((regval & OTG_GRSTCTL_AHBIDL) != 0) + { + break; + } + } + + /* Then perform the core soft reset. */ + + stm32_putreg(STM32_OTG_GRSTCTL, OTG_GRSTCTL_CSRST); + for (timeout = 0; timeout < STM32_READY_DELAY; timeout++) + { + regval = stm32_getreg(STM32_OTG_GRSTCTL); + if ((regval & OTG_GRSTCTL_CSRST) == 0) + { + break; + } + } + + /* Wait for 3 PHY Clocks */ + + up_udelay(3); + + /* Deactivate the power down */ + + regval = (OTG_GCCFG_PWRDWN | OTG_GCCFG_VBUSASEN | OTG_GCCFG_VBUSBSEN); +#ifndef CONFIG_USBDEV_VBUSSENSING + regval |= OTG_GCCFG_NOVBUSSENS; +#endif +#ifdef CONFIG_STM32F7_OTG_SOFOUTPUT + regval |= OTG_GCCFG_SOFOUTEN; +#endif + stm32_putreg(STM32_OTG_GCCFG, regval); + up_mdelay(20); + + /* Initialize OTG features: In order to support OTP, the HNPCAP and SRPCAP + * bits would need to be set in the GUSBCFG register about here. + */ + + /* Force Host Mode */ + + regval = stm32_getreg(STM32_OTG_GUSBCFG); + regval &= ~OTG_GUSBCFG_FDMOD; + regval |= OTG_GUSBCFG_FHMOD; + stm32_putreg(STM32_OTG_GUSBCFG, regval); + up_mdelay(50); + + /* Initialize host mode and return success */ + + stm32_host_initialize(priv); + return OK; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_otgfshost_initialize + * + * Description: + * Initialize USB host device controller hardware. + * + * Input Parameters: + * controller -- If the device supports more than USB host controller, then + * this identifies which controller is being initialized. Normally, this + * is just zero. + * + * Returned Value: + * And instance of the USB host interface. The controlling task should + * use this interface to (1) call the wait() method to wait for a device + * to be connected, and (2) call the enumerate() method to bind the device + * to a class driver. + * + * Assumptions: + * - This function should called in the initialization sequence in order + * to initialize the USB device functionality. + * - Class drivers should be initialized prior to calling this function. + * Otherwise, there is a race condition if the device is already connected. + * + ****************************************************************************/ + +FAR struct usbhost_connection_s *stm32_otgfshost_initialize(int controller) +{ + /* At present, there is only support for a single OTG FS host. Hence it is + * pre-allocated as g_usbhost. However, in most code, the private data + * structure will be referenced using the 'priv' pointer (rather than the + * global data) in order to simplify any future support for multiple devices. + */ + + FAR struct stm32_usbhost_s *priv = &g_usbhost; + + /* Sanity checks */ + + DEBUGASSERT(controller == 0); + + /* Make sure that interrupts from the OTG FS core are disabled */ + + stm32_gint_disable(); + + /* Reset the state of the host driver */ + + stm32_sw_initialize(priv); + + /* Alternate function pin configuration. Here we assume that: + * + * 1. GPIOA, SYSCFG, and OTG FS peripheral clocking have already been\ + * enabled as part of the boot sequence. + * 2. Board-specific logic has already enabled other board specific GPIOs + * for things like soft pull-up, VBUS sensing, power controls, and over- + * current detection. + */ + + /* Configure OTG FS alternate function pins for DM, DP, ID, and SOF. + * + * PIN* SIGNAL DIRECTION + * ---- ----------- ---------- + * PA8 OTG_FS_SOF SOF clock output + * PA9 OTG_FS_VBUS VBUS input for device, Driven by external regulator by + * host (not an alternate function) + * PA10 OTG_FS_ID OTG ID pin (only needed in Dual mode) + * PA11 OTG_FS_DM D- I/O + * PA12 OTG_FS_DP D+ I/O + * + * *Pins may vary from device-to-device. + */ + + stm32_configgpio(GPIO_OTG_DM); + stm32_configgpio(GPIO_OTG_DP); + stm32_configgpio(GPIO_OTG_ID); /* Only needed for OTG */ + + /* SOF output pin configuration is configurable */ + +#ifdef CONFIG_STM32F7_OTG_SOFOUTPUT + stm32_configgpio(GPIO_OTG_SOF); +#endif + + /* Initialize the USB OTG FS core */ + + stm32_hw_initialize(priv); + + /* Attach USB host controller interrupt handler */ + + if (irq_attach(STM32_IRQ_OTGFS, stm32_gint_isr) != 0) + { + usbhost_trace1(OTG_TRACE1_IRQATTACH, 0); + return NULL; + } + + /* Enable USB OTG FS global interrupts */ + + stm32_gint_enable(); + + /* Enable interrupts at the interrupt controller */ + + up_enable_irq(STM32_IRQ_OTGFS); + return &g_usbconn; +} + +#endif /* CONFIG_USBHOST && CONFIG_STM32F7_OTGFS */ diff --git a/arch/arm/src/stm32f7/stm32_pwr.c b/arch/arm/src/stm32f7/stm32_pwr.c new file mode 100644 index 0000000000000000000000000000000000000000..961eaf438097dd6bea8cb31309bca0d5ba498d00 --- /dev/null +++ b/arch/arm/src/stm32f7/stm32_pwr.c @@ -0,0 +1,260 @@ +/************************************************************************************ + * arch/arm/src/stm32f7/stm32_pwr.c + * + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved. + * Authors: Uros Platise + * Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include + +#include +#include +#include + +#include "up_arch.h" +#include "stm32_pwr.h" + +#if defined(CONFIG_STM32F7_PWR) + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +static inline uint16_t stm32_pwr_getreg(uint8_t offset) +{ + return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset); +} + +static inline void stm32_pwr_putreg(uint8_t offset, uint16_t value) +{ + putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset); +} + +static inline void stm32_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint16_t setbits) +{ + modifyreg32(STM32_PWR_BASE + (uint32_t)offset, (uint32_t)clearbits, (uint32_t)setbits); +} + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_pwr_enablebkp + * + * Description: + * Enables access to the backup domain (RTC registers, RTC backup data registers + * and backup SRAM). + * + * Input Parameters: + * writable - True: enable ability to write to backup domain registers + * + * Returned Value: + * True: The backup domain was previously writable. + * + ************************************************************************************/ + +bool stm32_pwr_enablebkp(bool writable) +{ + uint16_t regval; + bool waswritable; + + /* Get the current state of the STM32 PWR control register */ + + regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET); + waswritable = ((regval & PWR_CR1_DBP) != 0); + + /* Enable or disable the ability to write */ + + if (waswritable && !writable) + { + /* Disable backup domain access */ + + regval &= ~PWR_CR1_DBP; + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); + } + else if (!waswritable && writable) + { + /* Enable backup domain access */ + + regval |= PWR_CR1_DBP; + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); + + /* Enable does not happen right away */ + + up_udelay(4); + } + + return waswritable; +} + +/************************************************************************************ + * Name: stm32_pwr_enablebreg + * + * Description: + * Enables the Backup regulator, the Backup regulator (used to maintain backup + * SRAM content in Standby and VBAT modes) is enabled. If BRE is reset, the backup + * regulator is switched off. The backup SRAM can still be used but its content will + * be lost in the Standby and VBAT modes. Once set, the application must wait that + * the Backup Regulator Ready flag (BRR) is set to indicate that the data written + * into the RAM will be maintained in the Standby and VBAT modes. + * + * Input Parameters: + * regon - state to set it to + * + * Returned Values: + * None + * + ************************************************************************************/ + +void stm32_pwr_enablebreg(bool regon) +{ + uint16_t regval; + + regval = stm32_pwr_getreg(STM32_PWR_CSR1_OFFSET); + regval &= ~PWR_CSR1_BRE; + regval |= regon ? PWR_CSR1_BRE : 0; + stm32_pwr_putreg(STM32_PWR_CSR1_OFFSET, regval); + + if (regon) + { + while ((stm32_pwr_getreg(STM32_PWR_CSR1_OFFSET) & PWR_CSR1_BRR) == 0); + } +} + +/************************************************************************************ + * Name: stm32_pwr_setvos + * + * Description: + * Set voltage scaling. + * + * Input Parameters: + * vos - Properly aligned voltage scaling select bits for the PWR_CR register. + * + * Returned Values: + * None + * + * Assumptions: + * At present, this function is called only from initialization logic. If used + * for any other purpose that protection to assure that its operation is atomic + * will be required. + * + ************************************************************************************/ + +void stm32_pwr_setvos(uint16_t vos) +{ + uint16_t regval; + + /* The following sequence is required to program the voltage regulator ranges: + * 1. Check VDD to identify which ranges are allowed... + * 2. Configure the voltage scaling range by setting the VOS bits in the PWR_CR1 + * register. + */ + + regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET); + regval &= ~PWR_CR1_VOS_MASK; + regval |= (vos & PWR_CR1_VOS_MASK); + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); +} + +/************************************************************************************ + * Name: stm32_pwr_setpvd + * + * Description: + * Sets power voltage detector + * + * Input Parameters: + * pls - PVD level + * + * Returned Values: + * None + * + * Assumptions: + * At present, this function is called only from initialization logic. If used + * for any other purpose that protection to assure that its operation is atomic + * will be required. + * + ************************************************************************************/ + +void stm32_pwr_setpvd(uint16_t pls) +{ + uint16_t regval; + + /* Set PLS */ + + regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET); + regval &= ~PWR_CR1_PLS_MASK; + regval |= (pls & PWR_CR1_PLS_MASK); + + /* Write value to register */ + + stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval); +} + +/************************************************************************************ + * Name: stm32_pwr_enablepvd + * + * Description: + * Enable the Programmable Voltage Detector + * + ************************************************************************************/ + +void stm32_pwr_enablepvd(void) +{ + /* Enable PVD by setting the PVDE bit in PWR_CR register. */ + + stm32_pwr_modifyreg(STM32_PWR_CR1_OFFSET, 0, PWR_CR1_PVDE); +} + +/************************************************************************************ + * Name: stm32_pwr_disablepvd + * + * Description: + * Disable the Programmable Voltage Detector + * + ************************************************************************************/ + +void stm32_pwr_disablepvd(void) +{ + /* Disable PVD by clearing the PVDE bit in PWR_CR register. */ + + stm32_pwr_modifyreg(STM32_PWR_CR1_OFFSET, PWR_CR1_PVDE, 0); +} + +#endif /* CONFIG_STM32_PWR */ diff --git a/arch/arm/src/stm32f7/stm32_pwr.h b/arch/arm/src/stm32f7/stm32_pwr.h index 3c5a30f96738676775413bc07942eb930ffd28d7..772851d524d657355206a98323ee57249d3f8c6e 100644 --- a/arch/arm/src/stm32f7/stm32_pwr.h +++ b/arch/arm/src/stm32f7/stm32_pwr.h @@ -1,8 +1,9 @@ /************************************************************************************ * arch/arm/src/stm32f7/stm32_pwr.h * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions diff --git a/arch/arm/src/stm32f7/stm32_rtc.c b/arch/arm/src/stm32f7/stm32_rtc.c new file mode 100644 index 0000000000000000000000000000000000000000..bd42b8396a67779936c1ee343f43e92ec244293f --- /dev/null +++ b/arch/arm/src/stm32f7/stm32_rtc.c @@ -0,0 +1,1503 @@ +/**************************************************************************** + * arch/arm/src/stm32f7/stm32_rtc.c + * + * Copyright (C) 2011, 2015-2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "up_arch.h" + +#include "stm32_rcc.h" +#include "stm32_pwr.h" +#include "stm32_exti.h" +#include "stm32_rtc.h" + +#include + +#ifdef CONFIG_RTC + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ +/* This RTC implementation supports + * - date/time RTC hardware + * - extended functions Alarm A and B for STM32F4xx and onwards + * */ + +#ifndef CONFIG_RTC_DATETIME +# error "CONFIG_RTC_DATETIME must be set to use this driver" +#endif + +#ifdef CONFIG_RTC_HIRES +# error "CONFIG_RTC_HIRES must NOT be set with this driver" +#endif + +#ifndef CONFIG_STM32F7_PWR +# error "CONFIG_STM32F7_PWR must selected to use this driver" +#endif + +/* Constants ****************************************************************/ + +#if defined(CONFIG_STM32F7_RTC_HSECLOCK) +# define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_HSE +#elif defined(CONFIG_STM32F7_RTC_LSICLOCK) +# define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_LSI +#elif defined(CONFIG_STM32F7_RTC_LSECLOCK) +# define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_LSE +#else +# warning "RCC_BDCR_RTCSEL_NOCLK has been selected - RTC will not count" +#endif + +#define SYNCHRO_TIMEOUT (0x00020000) +#define INITMODE_TIMEOUT (0x00010000) + +/* Time conversions */ + +#define MINUTES_IN_HOUR 60 +#define HOURS_IN_DAY 24 + +#define hours_add(parm_hrs) \ + time->tm_hour += parm_hrs;\ + if ((HOURS_IN_DAY-1) < (time->tm_hour))\ + {\ + time->tm_hour = (parm_hrs - HOURS_IN_DAY);\ + } + +#define RTC_ALRMR_DIS_MASK (RTC_ALRMR_MSK4 | RTC_ALRMR_MSK3 | \ + RTC_ALRMR_MSK2 | RTC_ALRMR_MSK1) +#define RTC_ALRMR_DIS_DATE_MASK (RTC_ALRMR_MSK4) +#define RTC_ALRMR_ENABLE (0) + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +typedef unsigned int rtc_alarmreg_t; + +struct alm_cbinfo_s +{ + volatile alm_callback_t ac_cb; /* Client callback function */ + volatile FAR void *ac_arg; /* Argument to pass with the callback function */ +}; +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +/* Callback to use when an EXTI is activated */ + +static struct alm_cbinfo_s g_alarmcb[RTC_ALARM_LAST]; +#endif + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* g_rtc_enabled is set true after the RTC has successfully initialized */ + +volatile bool g_rtc_enabled = false; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int rtchw_check_alrawf(void); +static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg); +#if CONFIG_RTC_NALARMS > 1 +static int rtchw_check_alrbwf(void); +static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg); +#endif +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rtc_dumpregs + * + * Description: + * Disable RTC write protection + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_RTC_INFO +static void rtc_dumpregs(FAR const char *msg) +{ + int rtc_state; + + rtcinfo("%s:\n", msg); + rtcinfo(" TR: %08x\n", getreg32(STM32_RTC_TR)); + rtcinfo(" DR: %08x\n", getreg32(STM32_RTC_DR)); + rtcinfo(" CR: %08x\n", getreg32(STM32_RTC_CR)); + rtcinfo(" ISR: %08x\n", getreg32(STM32_RTC_ISR)); + rtcinfo(" PRER: %08x\n", getreg32(STM32_RTC_PRER)); + rtcinfo(" WUTR: %08x\n", getreg32(STM32_RTC_WUTR)); + rtcinfo(" ALRMAR: %08x\n", getreg32(STM32_RTC_ALRMAR)); + rtcinfo(" ALRMBR: %08x\n", getreg32(STM32_RTC_ALRMBR)); + rtcinfo(" SHIFTR: %08x\n", getreg32(STM32_RTC_SHIFTR)); + rtcinfo(" TSTR: %08x\n", getreg32(STM32_RTC_TSTR)); + rtcinfo(" TSDR: %08x\n", getreg32(STM32_RTC_TSDR)); + rtcinfo(" TSSSR: %08x\n", getreg32(STM32_RTC_TSSSR)); + rtcinfo(" CALR: %08x\n", getreg32(STM32_RTC_CALR)); + rtcinfo(" TAFCR: %08x\n", getreg32(STM32_RTC_TAFCR)); + rtcinfo("ALRMASSR: %08x\n", getreg32(STM32_RTC_ALRMASSR)); + rtcinfo("ALRMBSSR: %08x\n", getreg32(STM32_RTC_ALRMBSSR)); + rtcinfo("MAGICREG: %08x\n", getreg32(RTC_MAGIC_REG)); + + rtc_state = + ((getreg32(STM32_EXTI_RTSR) & EXTI_RTC_ALARM) ? 0x1000 : 0) | + ((getreg32(STM32_EXTI_FTSR) & EXTI_RTC_ALARM) ? 0x0100 : 0) | + ((getreg32(STM32_EXTI_IMR) & EXTI_RTC_ALARM) ? 0x0010 : 0) | + ((getreg32(STM32_EXTI_EMR) & EXTI_RTC_ALARM) ? 0x0001 : 0); + rtcinfo("EXTI (RTSR FTSR ISR EVT): %01x\n",rtc_state); +} +#else +# define rtc_dumpregs(msg) +#endif + +/**************************************************************************** + * Name: rtc_dumptime + * + * Description: + * Disable RTC write protection + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_DEBUG_RTC_INFO +static void rtc_dumptime(FAR const struct tm *tp, FAR const char *msg) +{ + rtcinfo("%s:\n", msg); + rtcinfo(" tm_sec: %08x\n", tp->tm_sec); + rtcinfo(" tm_min: %08x\n", tp->tm_min); + rtcinfo(" tm_hour: %08x\n", tp->tm_hour); + rtcinfo(" tm_mday: %08x\n", tp->tm_mday); + rtcinfo(" tm_mon: %08x\n", tp->tm_mon); + rtcinfo(" tm_year: %08x\n", tp->tm_year); +} +#else +# define rtc_dumptime(tp, msg) +#endif + +/**************************************************************************** + * Name: rtc_wprunlock + * + * Description: + * Disable RTC write protection + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static void rtc_wprunlock(void) +{ + /* Enable write access to the backup domain (RTC registers, RTC backup data + * registers and backup SRAM). + */ + + (void)stm32_pwr_enablebkp(true); + + /* The following steps are required to unlock the write protection on all the + * RTC registers (except for RTC_ISR[13:8], RTC_TAFCR, and RTC_BKPxR). + * + * 1. Write 0xCA into the RTC_WPR register. + * 2. Write 0x53 into the RTC_WPR register. + * + * Writing a wrong key re-activates the write protection. + */ + + putreg32(0xca, STM32_RTC_WPR); + putreg32(0x53, STM32_RTC_WPR); +} + +/**************************************************************************** + * Name: rtc_wprlock + * + * Description: + * Enable RTC write protection + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +static inline void rtc_wprlock(void) +{ + /* Writing any wrong key re-activates the write protection. */ + + putreg32(0xff, STM32_RTC_WPR); + + /* Disable write access to the backup domain (RTC registers, RTC backup + * data registers and backup SRAM). + */ + + (void)stm32_pwr_enablebkp(false); +} + +/**************************************************************************** + * Name: rtc_synchwait + * + * Description: + * Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are + * synchronized with RTC APB clock. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +static int rtc_synchwait(void) +{ + volatile uint32_t timeout; + uint32_t regval; + int ret; + + /* Disable the write protection for RTC registers */ + + rtc_wprunlock(); + + /* Clear Registers synchronization flag (RSF) */ + + regval = getreg32(STM32_RTC_ISR); + regval &= ~RTC_ISR_RSF; + putreg32(regval, STM32_RTC_ISR); + + /* Now wait the registers to become synchronised */ + + ret = -ETIMEDOUT; + for (timeout = 0; timeout < SYNCHRO_TIMEOUT; timeout++) + { + regval = getreg32(STM32_RTC_ISR); + if ((regval & RTC_ISR_RSF) != 0) + { + /* Synchronized */ + + ret = OK; + break; + } + } + + /* Re-enable the write protection for RTC registers */ + + rtc_wprlock(); + return ret; +} + +/**************************************************************************** + * Name: rtc_enterinit + * + * Description: + * Enter RTC initialization mode. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +static int rtc_enterinit(void) +{ + volatile uint32_t timeout; + uint32_t regval; + int ret; + + /* Check if the Initialization mode is already set */ + + regval = getreg32(STM32_RTC_ISR); + + ret = OK; + if ((regval & RTC_ISR_INITF) == 0) + { + /* Set the Initialization mode */ + + putreg32(RTC_ISR_INIT, STM32_RTC_ISR); + + /* Wait until the RTC is in the INIT state (or a timeout occurs) */ + + ret = -ETIMEDOUT; + for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) + { + regval = getreg32(STM32_RTC_ISR); + if ((regval & RTC_ISR_INITF) != 0) + { + ret = OK; + break; + } + } + } + + return ret; +} + +/**************************************************************************** + * Name: rtc_exitinit + * + * Description: + * Exit RTC initialization mode. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +static void rtc_exitinit(void) +{ + uint32_t regval; + + regval = getreg32(STM32_RTC_ISR); + regval &= ~(RTC_ISR_INIT); + putreg32(regval, STM32_RTC_ISR); +} + +/**************************************************************************** + * Name: rtc_bin2bcd + * + * Description: + * Converts a 2 digit binary to BCD format + * + * Input Parameters: + * value - The byte to be converted. + * + * Returned Value: + * The value in BCD representation + * + ****************************************************************************/ + +static uint32_t rtc_bin2bcd(int value) +{ + uint32_t msbcd = 0; + + while (value >= 10) + { + msbcd++; + value -= 10; + } + + return (msbcd << 4) | value; +} + +/**************************************************************************** + * Name: rtc_bin2bcd + * + * Description: + * Convert from 2 digit BCD to binary. + * + * Input Parameters: + * value - The BCD value to be converted. + * + * Returned Value: + * The value in binary representation + * + ****************************************************************************/ + +static int rtc_bcd2bin(uint32_t value) +{ + uint32_t tens = (value >> 4) * 10; + return (int)(tens + (value & 0x0f)); +} + +/**************************************************************************** + * Name: rtc_setup + * + * Description: + * Performs first time configuration of the RTC. A special value written + * into back-up register 0 will prevent this function from being called on + * sub-sequent resets or power up. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +static int rtc_setup(void) +{ + uint32_t regval; + int ret; + + /* Disable the write protection for RTC registers */ + + rtc_wprunlock(); + + /* Set Initialization mode */ + + ret = rtc_enterinit(); + if (ret == OK) + { + /* Set the 24 hour format by clearing the FMT bit in the RTC + * control register + */ + + regval = getreg32(STM32_RTC_CR); + regval &= ~RTC_CR_FMT; + putreg32(regval, STM32_RTC_CR); + + /* Configure RTC pre-scaler with the required values */ + +#ifdef CONFIG_STM32F7_RTC_HSECLOCK + /* For a 1 MHz clock this yields 0.9999360041 Hz on the second + * timer - which is pretty close. + */ + + putreg32(((uint32_t)7182 << RTC_PRER_PREDIV_S_SHIFT) | + ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), + STM32_RTC_PRER); +#else + /* Correct values for 32.768 KHz LSE clock and inaccurate LSI clock */ + + putreg32(((uint32_t)0xff << RTC_PRER_PREDIV_S_SHIFT) | + ((uint32_t)0x7f << RTC_PRER_PREDIV_A_SHIFT), + STM32_RTC_PRER); +#endif + + /* Exit RTC initialization mode */ + + rtc_exitinit(); + } + + /* Re-enable the write protection for RTC registers */ + + rtc_wprlock(); + + return ret; +} + +/**************************************************************************** + * Name: rtc_resume + * + * Description: + * Called when the RTC was already initialized on a previous power cycle. + * This just brings the RTC back into full operation. + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +static void rtc_resume(void) +{ +#ifdef CONFIG_RTC_ALARM + uint32_t regval; + + /* Clear the RTC alarm flags */ + + regval = getreg32(STM32_RTC_ISR); + regval &= ~(RTC_ISR_ALRAF | RTC_ISR_ALRBF); + putreg32(regval, STM32_RTC_ISR); + + /* Clear the RTC Alarm Pending bit */ + + putreg32(EXTI_RTC_ALARM, STM32_EXTI_PR); +#endif +} + +/**************************************************************************** + * Name: stm32_rtc_alarm_handler + * + * Description: + * RTC ALARM interrupt service routine through the EXTI line + * + * Input Parameters: + * irq - The IRQ number that generated the interrupt + * context - Architecture specific register save information. + * + * Returned Value: + * Zero (OK) on success; A negated errno value on failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int stm32_rtc_alarm_handler(int irq, void *context) +{ + FAR struct alm_cbinfo_s *cbinfo; + alm_callback_t cb; + FAR void *arg; + uint32_t isr; + uint32_t cr; + int ret = OK; + + isr = getreg32(STM32_RTC_ISR); + + /* Check for EXTI from Alarm A or B and handle according */ + + if ((isr & RTC_ISR_ALRAF) != 0) + { + cr = getreg32(STM32_RTC_CR); + if ((cr & RTC_CR_ALRAIE) != 0) + { + cbinfo = &g_alarmcb[RTC_ALARMA]; + if (cbinfo->ac_cb != NULL) + { + /* Alarm A callback */ + + cb = cbinfo->ac_cb; + arg = (FAR void *)cbinfo->ac_arg; + + cbinfo->ac_cb = NULL; + cbinfo->ac_arg = NULL; + + cb(arg, RTC_ALARMA); + } + + isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRAF; + putreg32(isr, STM32_RTC_CR); + } + } + +#if CONFIG_RTC_NALARMS > 1 + if ((isr & RTC_ISR_ALRBF) != 0) + { + cr = getreg32(STM32_RTC_CR); + if ((cr & RTC_CR_ALRBIE) != 0) + { + cbinfo = &g_alarmcb[RTC_ALARMB]; + if (cbinfo->ac_cb != NULL) + { + /* Alarm B callback */ + + cb = cbinfo->ac_cb; + arg = (FAR void *)cbinfo->ac_arg; + + cbinfo->ac_cb = NULL; + cbinfo->ac_arg = NULL; + + cb(arg, RTC_ALARMB); + } + + isr = getreg32(STM32_RTC_ISR) & ~RTC_ISR_ALRBF; + putreg32(isr, STM32_RTC_CR); + } + } +#endif + + return ret; +} +#endif + +/**************************************************************************** + * Name: rtchw_check_alrXwf X= a or B + * + * Description: + * Check registers + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int rtchw_check_alrawf(void) +{ + volatile uint32_t timeout; + uint32_t regval; + int ret = -ETIMEDOUT; + + /* Check RTC_ISR ALRAWF for access to alarm register, + * Can take 2 RTCCLK cycles or timeout + * CubeMX use GetTick. + */ + + for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) + { + regval = getreg32(STM32_RTC_ISR); + if ((regval & RTC_ISR_ALRAWF) != 0) + { + ret = OK; + break; + } + } + + return ret; +} +#endif + +#if defined(CONFIG_RTC_ALARM) && CONFIG_RTC_NALARMS > 1 +static int rtchw_check_alrbwf(void) +{ + volatile uint32_t timeout; + uint32_t regval; + int ret = -ETIMEDOUT; + + /* Check RTC_ISR ALRAWF for access to alarm register, + * can take 2 RTCCLK cycles or timeout + * CubeMX use GetTick. + */ + + for (timeout = 0; timeout < INITMODE_TIMEOUT; timeout++) + { + regval = getreg32(STM32_RTC_ISR); + if ((regval & RTC_ISR_ALRBWF) != 0) + { + ret = OK; + break; + } + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_rtchw_set_alrmXr X is a or b + * + * Description: + * Set the alarm (A or B) hardware registers, using the required hardware + * access protocol + * + * Input Parameters: + * alarmreg - the register + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int rtchw_set_alrmar(rtc_alarmreg_t alarmreg) +{ + int ret = -EBUSY; + + /* Need to follow RTC register wrote protection + * Disable the write protection for RTC registers + */ + + rtc_wprunlock(); + + /* Disable RTC alarm & Interrupt */ + + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); + + ret = rtchw_check_alrawf(); + if (ret != OK) + { + goto errout_with_wprunlock; + } + + /* Set the RTC Alarm register */ + + putreg32(alarmreg, STM32_RTC_ALRMAR); + rtcinfo(" TR: %08x ALRMAR: %08x\n", + getreg32(STM32_RTC_TR), getreg32(STM32_RTC_ALRMAR)); + + /* Enable RTC alarm */ + + modifyreg32(STM32_RTC_CR, 0, (RTC_CR_ALRAE | RTC_CR_ALRAIE)); + +errout_with_wprunlock: + rtc_wprlock(); + return ret; +} +#endif + +#if defined(CONFIG_RTC_ALARM) && CONFIG_RTC_NALARMS > 1 +static int rtchw_set_alrmbr(rtc_alarmreg_t alarmreg) +{ + int ret = -EBUSY; + + /* Need to follow RTC register wrote protection + * Disable the write protection for RTC registers + */ + + rtc_wprunlock(); + + /* Disable RTC alarm B & Interrupt B */ + + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); + + ret = rtchw_check_alrbwf(); + if (ret != OK) + { + goto rtchw_set_alrmbr_exit; + } + + /* Set the RTC Alarm register */ + + putreg32(alarmreg, STM32_RTC_ALRMBR); + rtcinfo(" TR: %08x ALRMBR: %08x\n", + getreg32(STM32_RTC_TR), getreg32(STM32_RTC_ALRMBR)); + + /* Enable RTC alarm B */ + + modifyreg32(STM32_RTC_CR, 0, (RTC_CR_ALRBE | RTC_CR_ALRBIE)); + +rtchw_set_alrmbr_exit: + rtc_wprlock(); + return ret; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_rtc_initialize + * + * Description: + * Initialize the hardware RTC per the selected configuration. This + * function is called once during the OS initialization sequence + * + * Input Parameters: + * None + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_initialize(void) +{ + uint32_t regval; + uint32_t tr_bkp; + uint32_t dr_bkp; + int ret; + int maxretry = 10; + int nretry = 0; + + /* Clocking for the PWR block must be provided. However, this is done + * unconditionally in stm32f7xxx_rcc.c on power up. This done + * unconditionally because the PWR block is also needed to set the + * internal voltage regulator for maximum performance. + */ + + /* Select the clock source */ + /* Save the token before losing it when resetting */ + + regval = getreg32(RTC_MAGIC_REG); + + (void)stm32_pwr_enablebkp(true); + + if (regval != RTC_MAGIC) + { + /* Issue the Backup domain Reset Per Section 5.3.20 DocID028270 Rev 2 + * The LSEON, LSEBYP, RTCSEL and RTCEN bits in the RCC backup domain + * control register (RCC_BDCR) are in the Backup domain. As a result, + * after Reset, these bits are write-protected and the DBP bit in the + * PWR power control register (PWR_CR1) has to be set before these can + * be modified. Refer to Section 5.1.1: System reset on page 148 for + * further information. These bits are only reset after a Backup + * domain Reset (see Section 5.1.3: Backup domain reset). + * + * This has to be done here so that PWR is already enabled + */ + + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); + +#if RCC_BDCR_RTCSEL == RCC_BDCR_RTCSEL_LSE + /* Because of the Backup domain Reset - we must re enable the LSE */ + + stm32_rcc_enablelse(); +#endif + + /* Some boards do not have the external 32khz oscillator installed, for + * those boards we must fallback to the crummy internal RC clock or the + * external high rate clock + */ + +#ifdef CONFIG_STM32F7_RTC_HSECLOCK + /* Use the HSE clock as the input to the RTC block */ + + rtc_dumpregs("On reset HSE"); + +#elif defined(CONFIG_STM32F7_RTC_LSICLOCK) + /* Use the LSI clock as the input to the RTC block */ + + rtc_dumpregs("On reset LSI"); + +#elif defined(CONFIG_STM32F7_RTC_LSECLOCK) + /* Use the LSE clock as the input to the RTC block */ + + rtc_dumpregs("On reset LSE"); + +#endif + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL); + + /* Enable the RTC Clock by setting the RTCEN bit in the RCC register */ + + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN); + } + else + { + uint32_t clksrc = getreg32(STM32_RCC_BDCR); + + rtc_dumpregs("On reset warm"); + + /* The RTC is already in use: check if the clock source has changed */ + + if ((clksrc & RCC_BDCR_RTCSEL_MASK) != RCC_BDCR_RTCSEL) + { + tr_bkp = getreg32(STM32_RTC_TR); + dr_bkp = getreg32(STM32_RTC_DR); + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST); + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0); + +# if RCC_BDCR_RTCSEL == RCC_BDCR_RTCSEL_LSE + /* Because of the Backup domain Reset - we must re enable the LSE + * if it is used + */ + + stm32_rcc_enablelse(); +#endif + /* Change to the new clock as the input to the RTC block */ + + modifyreg32(STM32_RCC_BDCR, RCC_BDCR_RTCSEL_MASK, RCC_BDCR_RTCSEL); + + putreg32(tr_bkp, STM32_RTC_TR); + putreg32(dr_bkp, STM32_RTC_DR); + + /* Keep the fact that the RTC is initialized */ + + putreg32(RTC_MAGIC, RTC_MAGIC_REG); + + /* Enable the RTC Clock by setting the RTCEN bit in the RCC + * register. + */ + + modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_RTCEN); + } + } + + (void)stm32_pwr_enablebkp(false); + + /* Loop, attempting to initialize/resume the RTC. This loop is necessary + * because it seems that occasionally it takes longer to initialize the + * RTC (the actual failure is in rtc_synchwait()). + */ + + do + { + /* Wait for the RTC Time and Date registers to be synchronized with + * RTC APB clock. + */ + + ret = rtc_synchwait(); + + /* Check that rtc_syncwait() returned successfully */ + + switch (ret) + { + case OK: + { + rtcinfo("rtc_syncwait() okay\n"); + break; + } + + default: + { + rtcerr("ERROR: rtc_syncwait() failed (%d)\n", ret); + break; + } + } + } + while (ret != OK && ++nretry < maxretry); + + /* Check if the one-time initialization of the RTC has already been + * performed. We can determine this by checking if the magic number + * has been writing to to back-up date register DR0. + */ + + if (regval != RTC_MAGIC) + { + rtcinfo("Do setup\n"); + + /* Perform the one-time setup of the LSE clocking to the RTC */ + + ret = rtc_setup(); + + /* Enable write access to the backup domain (RTC registers, RTC + * backup data registers and backup SRAM). + */ + + (void)stm32_pwr_enablebkp(true); + + /* Remember that the RTC is initialized */ + + putreg32(RTC_MAGIC, RTC_MAGIC_REG); + } + else + { + rtcinfo("Do resume\n"); + + /* RTC already set-up, just resume normal operation */ + + rtc_resume(); + rtc_dumpregs("Did resume"); + } + + /* Disable write access to the backup domain (RTC registers, RTC backup + * data registers and backup SRAM). + */ + + (void)stm32_pwr_enablebkp(false); + + if (ret != OK && nretry > 0) + { + rtcinfo("setup/resume ran %d times and failed with %d\n", + nretry, ret); + return -ETIMEDOUT; + } + +#ifdef CONFIG_RTC_ALARM + /* Configure RTC interrupt to catch alarm interrupts. All RTC interrupts + * are connected to the EXTI controller. To enable the RTC Alarm + * interrupt, the following sequence is required: + * + * 1. Configure and enable the EXTI Line 17 RTC ALARM in interrupt mode + * and select the rising edge sensitivity. + * For STM32F4xx + * EXTI line 21 RTC Tamper & Timestamp + * EXTI line 22 RTC Wakeup + * 2. Configure and enable the RTC_Alarm IRQ channel in the NVIC. + * 3. Configure the RTC to generate RTC alarms (Alarm A or Alarm B). + */ + + stm32_exti_alarm(true, false, true, stm32_rtc_alarm_handler); + rtc_dumpregs("After InitExtiAlarm"); +#else + rtc_dumpregs("After Initialization"); +#endif + + g_rtc_enabled = true; + return OK; +} + +/**************************************************************************** + * Name: stm32_rtc_getdatetime_with_subseconds + * + * Description: + * Get the current date and time from the date/time RTC. This interface + * is only supported by the date/time RTC hardware implementation. + * It is used to replace the system timer. It is only used by the RTOS + * during initialization to set up the system time when CONFIG_RTC and + * CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not). + * + * NOTE: Some date/time RTC hardware is capability of sub-second accuracy. + * That sub-second accuracy is returned through 'nsec'. + * + * Input Parameters: + * tp - The location to return the high resolution time value. + * nsec - The location to return the subsecond time value. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS +int stm32_rtc_getdatetime_with_subseconds(FAR struct tm *tp, FAR long *nsec) +#else +int up_rtc_getdatetime(FAR struct tm *tp) +#endif +{ +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS + uint32_t ssr; +#endif + uint32_t dr; + uint32_t tr; + uint32_t tmp; + + /* Sample the data time registers. There is a race condition here... If + * we sample the time just before midnight on December 31, the date could + * be wrong because the day rolled over while were sampling. + */ + + do + { + dr = getreg32(STM32_RTC_DR); + tr = getreg32(STM32_RTC_TR); +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS + ssr = getreg32(STM32_RTC_SSR); +#endif + tmp = getreg32(STM32_RTC_DR); + } + while (tmp != dr); + + rtc_dumpregs("Reading Time"); + + /* Convert the RTC time to fields in struct tm format. All of the STM32 + * All of the ranges of values correspond between struct tm and the time + * register. + */ + + tmp = (tr & (RTC_TR_SU_MASK | RTC_TR_ST_MASK)) >> RTC_TR_SU_SHIFT; + tp->tm_sec = rtc_bcd2bin(tmp); + + tmp = (tr & (RTC_TR_MNU_MASK | RTC_TR_MNT_MASK)) >> RTC_TR_MNU_SHIFT; + tp->tm_min = rtc_bcd2bin(tmp); + + tmp = (tr & (RTC_TR_HU_MASK | RTC_TR_HT_MASK)) >> RTC_TR_HU_SHIFT; + tp->tm_hour = rtc_bcd2bin(tmp); + + /* Now convert the RTC date to fields in struct tm format: + * Days: 1-31 match in both cases. + * Month: STM32 is 1-12, struct tm is 0-11. + * Years: STM32 is 00-99, struct tm is years since 1900. + * WeekDay: STM32 is 1 = Mon - 7 = Sun + * + * Issue: I am not sure what the STM32 years mean. Are these the + * years 2000-2099? I'll assume so. + */ + + tmp = (dr & (RTC_DR_DU_MASK | RTC_DR_DT_MASK)) >> RTC_DR_DU_SHIFT; + tp->tm_mday = rtc_bcd2bin(tmp); + + tmp = (dr & (RTC_DR_MU_MASK | RTC_DR_MT)) >> RTC_DR_MU_SHIFT; + tp->tm_mon = rtc_bcd2bin(tmp) - 1; + + tmp = (dr & (RTC_DR_YU_MASK | RTC_DR_YT_MASK)) >> RTC_DR_YU_SHIFT; + tp->tm_year = rtc_bcd2bin(tmp) + 100; + +#if defined(CONFIG_LIBC_LOCALTIME) || defined(CONFIG_TIME_EXTENDED) + tmp = (dr & RTC_DR_WDU_MASK) >> RTC_DR_WDU_SHIFT; + tp->tm_wday = tmp % 7; + tp->tm_yday = tp->tm_mday + + clock_daysbeforemonth(tp->tm_mon, clock_isleapyear(tp->tm_year + 1900)); + tp->tm_isdst = 0 +#endif + +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS + /* Return RTC sub-seconds if no configured and if a non-NULL value + * of nsec has been provided to receive the sub-second value. + */ + + if (nsec) + { + uint32_t prediv_s; + uint32_t usecs; + + prediv_s = getreg32(STM32_RTC_PRER) & RTC_PRER_PREDIV_S_MASK; + prediv_s >>= RTC_PRER_PREDIV_S_SHIFT; + + ssr &= RTC_SSR_MASK; + + /* Maximum prediv_s is 0x7fff, thus we can multiply by 100000 and + * still fit 32-bit unsigned integer. + */ + + usecs = (((prediv_s - ssr) * 100000) / (prediv_s + 1)) * 10; + *nsec = usecs * 1000; + } +#endif /* CONFIG_STM32_HAVE_RTC_SUBSECONDS */ + + rtc_dumptime((FAR const struct tm *)tp, "Returning"); + return OK; +} + +/**************************************************************************** + * Name: up_rtc_getdatetime + * + * Description: + * Get the current date and time from the date/time RTC. This interface + * is only supported by the date/time RTC hardware implementation. + * It is used to replace the system timer. It is only used by the RTOS + * during initialization to set up the system time when CONFIG_RTC and + * CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not). + * + * NOTE: Some date/time RTC hardware is capability of sub-second accuracy. + * That sub-second accuracy is lost in this interface. However, since the + * system time is reinitialized on each power-up/reset, there will be no + * timing inaccuracy in the long run. + * + * Input Parameters: + * tp - The location to return the high resolution time value. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_STM32_HAVE_RTC_SUBSECONDS +int up_rtc_getdatetime(FAR struct tm *tp) +{ + return stm32_rtc_getdatetime_with_subseconds(tp, NULL); +} +#endif + +/**************************************************************************** + * Name: stm32_rtc_setdatetime + * + * Description: + * Set the RTC to the provided time. RTC implementations which provide + * up_rtc_getdatetime() (CONFIG_RTC_DATETIME is selected) should provide + * this function. + * + * Input Parameters: + * tp - the time to use + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int stm32_rtc_setdatetime(FAR const struct tm *tp) +{ + uint32_t tr; + uint32_t dr; + int ret; + + rtc_dumptime(tp, "Setting time"); + + /* Then write the broken out values to the RTC */ + + /* Convert the struct tm format to RTC time register fields. All of the + * STM32 All of the ranges of values correspond between struct tm and the + * time register. + */ + + tr = (rtc_bin2bcd(tp->tm_sec) << RTC_TR_SU_SHIFT) | + (rtc_bin2bcd(tp->tm_min) << RTC_TR_MNU_SHIFT) | + (rtc_bin2bcd(tp->tm_hour) << RTC_TR_HU_SHIFT); + + /* Now convert the fields in struct tm format to the RTC date register + * fields: + * + * Days: 1-31 match in both cases. + * Month: STM32 is 1-12, struct tm is 0-11. + * Years: STM32 is 00-99, struct tm is years since 1900. + * WeekDay: STM32 is 1 = Mon - 7 = Sun + * + * Issue: I am not sure what the STM32 years mean. Are these the + * years 2000-2099? I'll assume so. + */ + + dr = (rtc_bin2bcd(tp->tm_mday) << RTC_DR_DU_SHIFT) | + ((rtc_bin2bcd(tp->tm_mon + 1)) << RTC_DR_MU_SHIFT) | +#if defined(CONFIG_LIBC_LOCALTIME) || defined(CONFIG_TIME_EXTENDED) + ((tp->tm_wday == 0 ? 7 : (tp->tm_wday & 7)) << RTC_DR_WDU_SHIFT) | +#endif + ((rtc_bin2bcd(tp->tm_year - 100)) << RTC_DR_YU_SHIFT); + + dr &= ~RTC_DR_RESERVED_BITS; + + /* Disable the write protection for RTC registers */ + + rtc_wprunlock(); + + /* Set Initialization mode */ + + ret = rtc_enterinit(); + if (ret == OK) + { + /* Set the RTC TR and DR registers */ + + putreg32(tr, STM32_RTC_TR); + putreg32(dr, STM32_RTC_DR); + + /* Exit Initialization mode and wait for the RTC Time and Date + * registers to be synchronized with RTC APB clock. + */ + + rtc_exitinit(); + ret = rtc_synchwait(); + } + + /* Re-enable the write protection for RTC registers */ + + rtc_wprlock(); + rtc_dumpregs("New time setting"); + return ret; +} + +/**************************************************************************** + * Name: up_rtc_settime + * + * Description: + * Set the RTC to the provided time. All RTC implementations must be able + * to set their time based on a standard timespec. + * + * Input Parameters: + * tp - the time to use + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +int up_rtc_settime(FAR const struct timespec *tp) +{ + FAR struct tm newtime; + + /* Break out the time values (not that the time is set only to units of + * seconds) + */ + + (void)gmtime_r(&tp->tv_sec, &newtime); + return stm32_rtc_setdatetime(&newtime); +} + +/**************************************************************************** + * Name: stm32_rtc_setalarm + * + * Description: + * Set an alarm to an asbolute time using associated hardware. + * + * Input Parameters: + * alminfo - Information about the alarm configuration. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +int stm32_rtc_setalarm(FAR struct alm_setalarm_s *alminfo) +{ + FAR struct alm_cbinfo_s *cbinfo; + rtc_alarmreg_t alarmreg; + int ret = -EINVAL; + + ASSERT(alminfo != NULL); + DEBUGASSERT(RTC_ALARM_LAST > alminfo->as_id); + + /* REVISIT: Should test that the time is in the future */ + + rtc_dumptime(&alminfo->as_time, "New alarm time"); + + /* Break out the values to the HW alarm register format. The values in + * all STM32 fields match the fields of struct tm in this case. Notice + * that the alarm is limited to one month. + */ + + alarmreg = (rtc_bin2bcd(alminfo->as_time.tm_sec) << RTC_ALRMR_SU_SHIFT) | + (rtc_bin2bcd(alminfo->as_time.tm_min) << RTC_ALRMR_MNU_SHIFT) | + (rtc_bin2bcd(alminfo->as_time.tm_hour) << RTC_ALRMR_HU_SHIFT) | + (rtc_bin2bcd(alminfo->as_time.tm_mday) << RTC_ALRMR_DU_SHIFT); + + /* Set the alarm in hardware and enable interrupts */ + + switch (alminfo->as_id) + { + case RTC_ALARMA: + { + cbinfo = &g_alarmcb[RTC_ALARMA]; + cbinfo->ac_cb = alminfo->as_cb; + cbinfo->ac_arg = alminfo->as_arg; + + ret = rtchw_set_alrmar(alarmreg | RTC_ALRMR_ENABLE); + if (ret < 0) + { + cbinfo->ac_cb = NULL; + cbinfo->ac_arg = NULL; + } + + rtc_dumpregs("Set AlarmA"); + } + break; + +#if CONFIG_RTC_NALARMS > 1 + case RTC_ALARMB: + { + cbinfo = &g_alarmcb[RTC_ALARMB]; + cbinfo->ac_cb = alminfo->as_cb; + cbinfo->ac_arg = alminfo->as_arg; + + ret = rtchw_set_alrmbr(alarmreg | RTC_ALRMR_ENABLE); + if (ret < 0) + { + cbinfo->ac_cb = NULL; + cbinfo->ac_arg = NULL; + } + + rtc_dumpregs("Set AlarmB"); + } + break; +#endif + + default: + rtcerr("ERROR: Invalid ALARM%d\n", alminfo->as_id); + break; + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_rtc_cancelalarm + * + * Description: + * Cancel an alaram. + * + * Input Parameters: + * alarmid - Identifies the alarm to be cancelled + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +int stm32_rtc_cancelalarm(enum alm_id_e alarmid) +{ + int ret = -EINVAL; + + DEBUGASSERT(RTC_ALARM_LAST > alarmid); + + /* Cancel the alarm in hardware and disable interrupts */ + + switch (alarmid) + { + case RTC_ALARMA: + { + /* Cancel the global callback function */ + + g_alarmcb[alarmid].ac_cb = NULL; + g_alarmcb[alarmid].ac_arg = NULL; + + /* Need to follow RTC register wrote protection. + * Disable the write protection for RTC registers + */ + + rtc_wprunlock(); + + /* Disable RTC alarm and interrupt */ + + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRAE | RTC_CR_ALRAIE), 0); + + ret = rtchw_check_alrawf(); + if (ret < 0) + { + goto errout_with_wprunlock; + } + + /* Unset the alarm */ + + putreg32(-1, STM32_RTC_ALRMAR); + rtc_wprlock(); + ret = OK; + } + break; + +#if CONFIG_RTC_NALARMS > 1 + case RTC_ALARMB: + { + /* Cancel the global callback function */ + + g_alarmcb[alarmid].ac_cb = NULL; + g_alarmcb[alarmid].ac_arg = NULL; + + /* Need to follow RTC register wrote protection. + * Disable the write protection for RTC registers + */ + + rtc_wprunlock(); + + /* Disable RTC alarm and interrupt */ + + modifyreg32(STM32_RTC_CR, (RTC_CR_ALRBE | RTC_CR_ALRBIE), 0); + + ret = rtchw_check_alrbwf(); + if (ret < 0) + { + goto errout_with_wprunlock; + } + + /* Unset the alarm */ + + putreg32(-1, STM32_RTC_ALRMBR); + rtc_wprlock(); + ret = OK; + } + break; +#endif + + default: + rtcerr("ERROR: Invalid ALARM%d\n", alarmid); + break; + } + + return ret; + +errout_with_wprunlock: + rtc_wprlock(); + return ret; +} +#endif + +#endif /* CONFIG_RTC */ diff --git a/arch/arm/src/stm32f7/stm32_rtc.h b/arch/arm/src/stm32f7/stm32_rtc.h new file mode 100644 index 0000000000000000000000000000000000000000..f784f8acd310b1dc0cc0dc926812d2f4024e80e9 --- /dev/null +++ b/arch/arm/src/stm32f7/stm32_rtc.h @@ -0,0 +1,178 @@ +/**************************************************************************** + * arch/arm/src/stm32f7/stm32_rtc.h + * + * Copyright (C) 2011 Uros Platise. All rights reserved. + * Copyright (C) 2011-2013, 2015-2016 Gregory Nutt. All rights reserved. + * Authors: Uros Platise (Original for the F1) + * Gregory Nutt (On-going support and development) + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32F7_STM32_RTC_H +#define __ARCH_ARM_SRC_STM32F7_STM32_RTC_H + +#include + +#include "chip.h" + +/* The STMF7 family use a more traditional Realtime Clock/Calendar (RTCC) with + * broken-out data/time in BCD format. The backup registers are integrated into + * the RTCC in these families. + */ + +#include "chip/stm32_rtcc.h" +#include "stm32_alarm.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */ +#define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */ + +#if !defined(CONFIG_RTC_MAGIC) +# define CONFIG_RTC_MAGIC (0xfacefeee) +#endif + +#if !defined(CONFIG_RTC_MAGIC_REG) +# define CONFIG_RTC_MAGIC_REG (0) +#endif + +#define RTC_MAGIC CONFIG_RTC_MAGIC +#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_RTC_MAGIC_REG) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_rtc_getdatetime_with_subseconds + * + * Description: + * Get the current date and time from the date/time RTC. This interface + * is only supported by the date/time RTC hardware implementation. + * It is used to replace the system timer. It is only used by the RTOS + * during initialization to set up the system time when CONFIG_RTC and + * CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not). + * + * NOTE: Some date/time RTC hardware is capability of sub-second accuracy. + * Thatsub-second accuracy is returned through 'nsec'. + * + * Input Parameters: + * tp - The location to return the high resolution time value. + * nsec - The location to return the subsecond time value. + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS +int stm32_rtc_getdatetime_with_subseconds(FAR struct tm *tp, FAR long *nsec); +#endif + +/**************************************************************************** + * Name: stm32_rtc_setdatetime + * + * Description: + * Set the RTC to the provided time. RTC implementations which provide + * up_rtc_getdatetime() (CONFIG_RTC_DATETIME is selected) should provide + * this function. + * + * Input Parameters: + * tp - the time to use + * + * Returned Value: + * Zero (OK) on success; a negated errno on failure + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_DATETIME +struct tm; +int stm32_rtc_setdatetime(FAR const struct tm *tp); +#endif + +/**************************************************************************** + * Name: stm32_rtc_lowerhalf + * + * Description: + * Instantiate the RTC lower half driver for the STM32. General usage: + * + * #include + * #include "stm32_rtc.h> + * + * struct rtc_lowerhalf_s *lower; + * lower = stm32_rtc_lowerhalf(); + * rtc_initialize(0, lower); + * + * Input Parameters: + * None + * + * Returned Value: + * On success, a non-NULL RTC lower interface is returned. NULL is + * returned on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_DRIVER +struct rtc_lowerhalf_s; +FAR struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_STM32F7_STM32_RTC_H */ diff --git a/arch/arm/src/stm32f7/stm32_rtc_lowerhalf.c b/arch/arm/src/stm32f7/stm32_rtc_lowerhalf.c new file mode 100644 index 0000000000000000000000000000000000000000..1b20b44edabff9a1bed544e39b712a6544e9b358 --- /dev/null +++ b/arch/arm/src/stm32f7/stm32_rtc_lowerhalf.c @@ -0,0 +1,530 @@ +/**************************************************************************** + * arch/arm/src/stm32f7/stm32_rtc_lowerhalf.c + * + * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* REVISIT: This driver is *not* thread-safe! */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "stm32_rtc.h" + +#ifdef CONFIG_RTC_DRIVER + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define STM32_NALARMS 2 + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +struct stm32_cbinfo_s +{ + volatile rtc_alarm_callback_t cb; /* Callback when the alarm expires */ + volatile FAR void *priv; /* Private argurment to accompany callback */ + uint8_t id; /* Identifies the alarm */ +}; +#endif + +/* This is the private type for the RTC state. It must be cast compatible + * with struct rtc_lowerhalf_s. + */ + +struct stm32_lowerhalf_s +{ + /* This is the contained reference to the read-only, lower-half + * operations vtable (which may lie in FLASH or ROM) + */ + + FAR const struct rtc_ops_s *ops; + + /* Data following is private to this driver and not visible outside of + * this file. + */ + +#ifdef CONFIG_RTC_ALARM + /* Alarm callback information */ + + struct stm32_cbinfo_s cbinfo[STM32_NALARMS]; +#endif +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ +/* Prototypes for static methods in struct rtc_ops_s */ + +static int stm32_rdtime(FAR struct rtc_lowerhalf_s *lower, + FAR struct rtc_time *rtctime); +static int stm32_settime(FAR struct rtc_lowerhalf_s *lower, + FAR const struct rtc_time *rtctime); + +#ifdef CONFIG_RTC_ALARM +static int stm32_setalarm(FAR struct rtc_lowerhalf_s *lower, + FAR const struct lower_setalarm_s *alarminfo); +static int stm32_setrelative(FAR struct rtc_lowerhalf_s *lower, + FAR const struct lower_setrelative_s *alarminfo); +static int stm32_cancelalarm(FAR struct rtc_lowerhalf_s *lower, + int alarmid); +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ +/* STM32 RTC driver operations */ + +static const struct rtc_ops_s g_rtc_ops = +{ + .rdtime = stm32_rdtime, + .settime = stm32_settime, +#ifdef CONFIG_RTC_ALARM + .setalarm = stm32_setalarm, + .setrelative = stm32_setrelative, + .cancelalarm = stm32_cancelalarm, +#endif +#ifdef CONFIG_RTC_IOCTL + .ioctl = NULL, +#endif +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS + .destroy = NULL, +#endif +}; + +/* STM32 RTC device state */ + +static struct stm32_lowerhalf_s g_rtc_lowerhalf = +{ + .ops = &g_rtc_ops, +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_alarm_callback + * + * Description: + * This is the function that is called from the RTC driver when the alarm + * goes off. It just invokes the upper half drivers callback. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static void stm32_alarm_callback(FAR void *arg, unsigned int alarmid) +{ + FAR struct stm32_lowerhalf_s *lower; + FAR struct stm32_cbinfo_s *cbinfo; + rtc_alarm_callback_t cb; + FAR void *priv; + + DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB); + + lower = (struct stm32_lowerhalf_s *)arg; + cbinfo = &lower->cbinfo[alarmid]; + + /* Sample and clear the callback information to minimize the window in + * time in which race conditions can occur. + */ + + cb = (rtc_alarm_callback_t)cbinfo->cb; + priv = (FAR void *)cbinfo->priv; + DEBUGASSERT(priv != NULL); + + cbinfo->cb = NULL; + cbinfo->priv = NULL; + + /* Perform the callback */ + + if (cb != NULL) + { + cb(priv, alarmid); + } +} +#endif /* CONFIG_RTC_ALARM */ + +/**************************************************************************** + * Name: stm32_rdtime + * + * Description: + * Implements the rdtime() method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * rcttime - The location in which to return the current RTC time. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +static int stm32_rdtime(FAR struct rtc_lowerhalf_s *lower, + FAR struct rtc_time *rtctime) +{ +#if defined(CONFIG_RTC_DATETIME) + /* This operation depends on the fact that struct rtc_time is cast + * compatible with struct tm. + */ + + return up_rtc_getdatetime((FAR struct tm *)rtctime); + +#elif defined(CONFIG_RTC_HIRES) + FAR struct timespec ts; + int ret; + + /* Get the higher resolution time */ + + ret = up_rtc_gettime(&ts); + if (ret < 0) + { + goto errout_with_errno; + } + + /* Convert the one second epoch time to a struct tm. This operation + * depends on the fact that struct rtc_time and struct tm are cast + * compatible. + */ + + if (!gmtime_r(&ts.tv_sec, (FAR struct tm *)rtctime)) + { + goto errout_with_errno; + } + + return OK; + +errout_with_errno: + ret = get_errno(); + DEBUGASSERT(ret > 0); + return -ret; + +#else + time_t timer; + + /* The resolution of time is only 1 second */ + + timer = up_rtc_time(); + + /* Convert the one second epoch time to a struct tm */ + + if (!gmtime_r(&timer, (FAR struct tm *)rtctime)) + { + int errcode = get_errno(); + DEBUGASSERT(errcode > 0); + return -errcode; + } + + return OK; +#endif +} + +/**************************************************************************** + * Name: stm32_settime + * + * Description: + * Implements the settime() method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * rcttime - The new time to set + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +static int stm32_settime(FAR struct rtc_lowerhalf_s *lower, + FAR const struct rtc_time *rtctime) +{ +#ifdef CONFIG_RTC_DATETIME + /* This operation depends on the fact that struct rtc_time is cast + * compatible with struct tm. + */ + + return stm32_rtc_setdatetime((FAR const struct tm *)rtctime); + +#else + struct timespec ts; + + /* Convert the struct rtc_time to a time_t. Here we assume that struct + * rtc_time is cast compatible with struct tm. + */ + + ts.tv_sec = mktime((FAR struct tm *)rtctime); + ts.tv_nsec = 0; + + /* Now set the time (to one second accuracy) */ + + return up_rtc_settime(&ts); +#endif +} + +/**************************************************************************** + * Name: stm32_setalarm + * + * Description: + * Set a new alarm. This function implements the setalarm() method of the + * RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarminfo - Provided information needed to set the alarm + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int stm32_setalarm(FAR struct rtc_lowerhalf_s *lower, + FAR const struct lower_setalarm_s *alarminfo) +{ + FAR struct stm32_lowerhalf_s *priv; + FAR struct stm32_cbinfo_s *cbinfo; + struct alm_setalarm_s lowerinfo; + int ret = -EINVAL; + + /* ID0-> Alarm A; ID1 -> Alarm B */ + + DEBUGASSERT(lower != NULL && alarminfo != NULL); + DEBUGASSERT(alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB); + priv = (FAR struct stm32_lowerhalf_s *)lower; + + if (alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB) + { + /* Remember the callback information */ + + cbinfo = &priv->cbinfo[alarminfo->id]; + cbinfo->cb = alarminfo->cb; + cbinfo->priv = alarminfo->priv; + cbinfo->id = alarminfo->id; + + /* Set the alarm */ + + lowerinfo.as_id = alarminfo->id; + lowerinfo.as_cb = stm32_alarm_callback; + lowerinfo.as_arg = priv; + memcpy(&lowerinfo.as_time, &alarminfo->time, sizeof(struct tm)); + + /* And set the alarm */ + + ret = stm32_rtc_setalarm(&lowerinfo); + if (ret < 0) + { + cbinfo->cb = NULL; + cbinfo->priv = NULL; + } + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_setrelative + * + * Description: + * Set a new alarm relative to the current time. This function implements + * the setrelative() method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarminfo - Provided information needed to set the alarm + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int stm32_setrelative(FAR struct rtc_lowerhalf_s *lower, + FAR const struct lower_setrelative_s *alarminfo) +{ + struct lower_setalarm_s setalarm; + struct tm time; + time_t seconds; + int ret = -EINVAL; + + ASSERT(lower != NULL && alarminfo != NULL); + DEBUGASSERT(alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB); + + if ((alarminfo->id == RTC_ALARMA || alarminfo->id == RTC_ALARMB) && + alarminfo->reltime > 0) + { + /* Disable pre-emption while we do this so that we don't have to worry + * about being suspended and working on an old time. + */ + + sched_lock(); + + /* Get the current time in broken out format */ + + ret = up_rtc_getdatetime(&time); + if (ret >= 0) + { + /* Convert to seconds since the epoch */ + + seconds = mktime(&time); + + /* Add the seconds offset. Add one to the number of seconds + * because we are unsure of the phase of the timer. + */ + + seconds += (alarminfo->reltime + 1); + + /* And convert the time back to broken out format */ + + (void)gmtime_r(&seconds, (FAR struct tm *)&setalarm.time); + + /* The set the alarm using this absolute time */ + + setalarm.id = alarminfo->id; + setalarm.cb = alarminfo->cb; + setalarm.priv = alarminfo->priv; + + ret = stm32_setalarm(lower, &setalarm); + } + + sched_unlock(); + } + + return ret; +} +#endif + +/**************************************************************************** + * Name: stm32_cancelalarm + * + * Description: + * Cancel the current alarm. This function implements the cancelalarm() + * method of the RTC driver interface + * + * Input Parameters: + * lower - A reference to RTC lower half driver state structure + * alarminfo - Provided information needed to set the alarm + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned + * on any failure. + * + ****************************************************************************/ + +#ifdef CONFIG_RTC_ALARM +static int stm32_cancelalarm(FAR struct rtc_lowerhalf_s *lower, int alarmid) +{ + FAR struct stm32_lowerhalf_s *priv; + FAR struct stm32_cbinfo_s *cbinfo; + int ret = -EINVAL; + + DEBUGASSERT(lower != NULL); + DEBUGASSERT(alarmid == RTC_ALARMA || alarmid == RTC_ALARMB); + priv = (FAR struct stm32_lowerhalf_s *)lower; + + /* ID0-> Alarm A; ID1 -> Alarm B */ + + if (alarmid == RTC_ALARMA || alarmid == RTC_ALARMB) + { + /* Nullify callback information to reduce window for race conditions */ + + cbinfo = &priv->cbinfo[alarmid]; + cbinfo->cb = NULL; + cbinfo->priv = NULL; + + /* Then cancel the alarm */ + + ret = stm32_rtc_cancelalarm((enum alm_id_e)alarmid); + } + + return ret; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_rtc_lowerhalf + * + * Description: + * Instantiate the RTC lower half driver for the STM32. General usage: + * + * #include + * #include "stm32_rtc.h> + * + * struct rtc_lowerhalf_s *lower; + * lower = stm32_rtc_lowerhalf(); + * rtc_initialize(0, lower); + * + * Input Parameters: + * None + * + * Returned Value: + * On success, a non-NULL RTC lower interface is returned. NULL is + * returned on any failure. + * + ****************************************************************************/ + +FAR struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void) +{ + return (FAR struct rtc_lowerhalf_s *)&g_rtc_lowerhalf; +} + +#endif /* CONFIG_RTC_DRIVER */ diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.c b/arch/arm/src/stm32f7/stm32_sdmmc.c index 16473094b5a07db43495a753430daaaf7f2ae2d6..e05523e46bc5c6e42598ef29cc8984b3066a5e88 100644 --- a/arch/arm/src/stm32f7/stm32_sdmmc.c +++ b/arch/arm/src/stm32f7/stm32_sdmmc.c @@ -2,7 +2,8 @@ * arch/arm/src/stm32f7/stm32_sdmmc.c * * Copyright (C) 2009, 2011-2016 Gregory Nutt. All rights reserved. - * Author: Gregory Nutt + * Authors: Gregory Nutt + * David Sidrane * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -37,8 +38,6 @@ * Included Files ****************************************************************************/ -#include "stm32_sdmmc.h" - #include #include @@ -65,12 +64,9 @@ #include "stm32_dma.h" #include "stm32_gpio.h" +#include "stm32_sdmmc.h" - -/* TODO STM32F7_SDMMC2 - */ - -#ifdef CONFIG_STM32F7_SDMMC1 +#if defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) /**************************************************************************** * Pre-processor Definitions @@ -80,27 +76,27 @@ /* Required system configuration options: * * CONFIG_ARCH_DMA - Enable architecture-specific DMA subsystem - * initialization. Required if CONFIG_SDIO_DMA is enabled. + * initialization. Required if CONFIG_SDMMC[1|2]_DMA is enabled. * CONFIG_STM32F7_DMA2 - Enable STM32 DMA2 support. Required if - * CONFIG_SDIO_DMA is enabled + * CONFIG_SDMMC[1|2]_DMA is enabled * CONFIG_SCHED_WORKQUEUE -- Callback support requires work queue support. * * Driver-specific configuration options: * * CONFIG_SDIO_MUXBUS - Setting this configuration enables some locking - * APIs to manage concurrent accesses on the SDIO bus. This is not + * APIs to manage concurrent accesses on the SDMMC bus. This is not * needed for the simple case of a single SD card, for example. - * CONFIG_SDIO_DMA - Enable SDIO. This is a marginally optional. For - * most usages, SDIO will cause data overruns if used without DMA. + * CONFIG_SDIO_DMA - Enable SDMMC. This is a marginally optional. For + * most usages, SDMMC will cause data overruns if used without DMA. * NOTE the above system DMA configuration options. - * CONFIG_SDIO_WIDTH_D1_ONLY - This may be selected to force the driver + * CONFIG_SDMMC_WIDTH_D1_ONLY - This may be selected to force the driver * operate with only a single data line (the default is to use all * 4 SD data lines). - * CONFIG_SDIO_PRI - SDIO interrupt priority. This setting is not very + * CONFIG_SDMMC_PRI - SDMMC interrupt priority. This setting is not very * important since interrupt nesting is not currently supported. - * CONFIG_SDM_DMAPRIO - SDIO DMA priority. This can be selecte if + * CONFIG_SDMMMC_DMAPRIO - SDMMC DMA priority. This can be selecte if * CONFIG_SDIO_DMA is enabled. - * CONFIG_SDIO_XFRDEBUG - Enables some very low-level debug output + * CONFIG_CONFIG_STM32F7_SDMMC_XFRDEBUG - Enables some very low-level debug output * This also requires CONFIG_DEBUG_FS and CONFIG_DEBUG_INFO */ @@ -116,52 +112,75 @@ # error "Callback support requires CONFIG_SCHED_WORKQUEUE" #endif -#ifndef CONFIG_SDIO_PRI -# define CONFIG_SDIO_PRI NVIC_SYSH_PRIORITY_DEFAULT +#ifdef CONFIG_STM32F7_SDMMC1 +# ifndef CONFIG_SDMMC1_PRI +# define CONFIG_SDMMC1_PRI NVIC_SYSH_PRIORITY_DEFAULT +# endif + +# ifdef CONFIG_SDIO_DMA +# ifndef CONFIG_SDMMC1_DMAPRIO +# define CONFIG_SDMMC1_DMAPRIO DMA_SCR_PRIVERYHI +# endif +# if (CONFIG_SDMMC1_DMAPRIO & ~DMA_SCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_SDMMC1_DMAPRIO" +# endif +# else +# undef CONFIG_SDMMC1_DMAPRIO +# endif #endif -#ifdef CONFIG_SDIO_DMA -# ifndef CONFIG_SDIO_DMAPRIO -# define CONFIG_SDIO_DMAPRIO DMA_SCR_PRIVERYHI +#ifdef CONFIG_STM32F7_SDMMC2 +# ifndef CONFIG_SDMMC2_PRI +# define CONFIG_SDMMC2_PRI NVIC_SYSH_PRIORITY_DEFAULT # endif -# if (CONFIG_SDIO_DMAPRIO & ~DMA_SCR_PL_MASK) != 0 -# error "Illegal value for CONFIG_SDIO_DMAPRIO" + +# ifdef CONFIG_SDIO_DMA +# ifndef CONFIG_SDMMC2_DMAPRIO +# define CONFIG_SDMMC2_DMAPRIO DMA_SCR_PRIVERYHI +# endif +# if (CONFIG_SDMMC2_DMAPRIO & ~DMA_SCR_PL_MASK) != 0 +# error "Illegal value for CONFIG_SDMMC2_DMAPRIO" +# endif +# else +# undef CONFIG_SDMMC2_DMAPRIO # endif -#else -# undef CONFIG_SDIO_DMAPRIO #endif #if !defined(CONFIG_DEBUG_FS) || !defined(CONFIG_DEBUG_FEATURES) -# undef CONFIG_SDIO_XFRDEBUG +# undef CONFIG_CONFIG_STM32F7_SDMMC_XFRDEBUG #endif /* Friendly CLKCR bit re-definitions ****************************************/ -#define SDIO_CLKCR_RISINGEDGE (0) -#define SDIO_CLKCR_FALLINGEDGE SDIO_CLKCR_NEGEDGE +#define STM32_CLKCR_RISINGEDGE (0) +#define STM32_CLKCR_FALLINGEDGE STM32_CLKCR_NEGEDGE -/* Mode dependent settings. These depend on clock devisor settings that must - * be defined in the board-specific board.h header file: SDIO_INIT_CLKDIV, - * SDIO_MMCXFR_CLKDIV, and SDIO_SDXFR_CLKDIV. +/* Mode dependent settings. These depend on clock divisor settings that must + * be defined in the board-specific board.h header file: STM32_SDMMC_INIT_CLKDIV, + * STM32_SDMMC_MMCXFR_CLKDIV, and STM32_SDMMC_SDXFR_CLKDIV. */ -#define STM32_CLCKCR_INIT (SDMMC1_INIT_CLKDIV | SDIO_CLKCR_RISINGEDGE | \ - SDIO_CLKCR_WIDBUS_D1) -#define SDIO_CLKCR_MMCXFR (SDMMC1_MMCXFR_CLKDIV | SDIO_CLKCR_RISINGEDGE | \ - SDIO_CLKCR_WIDBUS_D1) -#define SDIO_CLCKR_SDXFR (SDMMC1_SDXFR_CLKDIV | SDIO_CLKCR_RISINGEDGE | \ - SDIO_CLKCR_WIDBUS_D1) -#define SDIO_CLCKR_SDWIDEXFR (SDMMC1_SDXFR_CLKDIV | SDIO_CLKCR_RISINGEDGE | \ - SDIO_CLKCR_WIDBUS_D4) +#define STM32_CLCKCR_INIT (STM32_SDMMC_INIT_CLKDIV | \ + STM32_CLKCR_RISINGEDGE | \ + STM32_SDMMC_CLKCR_WIDBUS_D1) +#define STM32_SDMMC_CLKCR_MMCXFR (STM32_SDMMC_MMCXFR_CLKDIV | \ + STM32_CLKCR_RISINGEDGE | \ + STM32_SDMMC_CLKCR_WIDBUS_D1) +#define STM32_SDMMC_CLCKR_SDXFR (STM32_SDMMC_SDXFR_CLKDIV | \ + STM32_CLKCR_RISINGEDGE | \ + STM32_SDMMC_CLKCR_WIDBUS_D1) +#define STM32_SDMMC_CLCKR_SDWIDEXFR (STM32_SDMMC_SDXFR_CLKDIV | \ + STM32_CLKCR_RISINGEDGE | \ + STM32_SDMMC_CLKCR_WIDBUS_D4) /* Timing */ -#define SDIO_CMDTIMEOUT (100000) -#define SDIO_LONGTIMEOUT (0x7fffffff) +#define SDMMC_CMDTIMEOUT (100000) +#define SDMMC_LONGTIMEOUT (0x7fffffff) /* Big DTIMER setting */ -#define SDIO_DTIMER_DATATIMEOUT (0x000fffff) +#define SDMMC_DTIMER_DATATIMEOUT (0x000fffff) /* DMA channel/stream configuration register settings. The following * must be selected. The DMA driver will select the remaining fields. @@ -173,76 +192,120 @@ */ -/* STM32 stream configuration register (SCR) settings. */ +/* STM32 stream configuration register (SCR) settings base settings sans + * priority. + */ -#define SDIO_RXDMA32_CONFIG (DMA_SCR_PFCTRL | DMA_SCR_DIR_P2M|DMA_SCR_MINC | \ +# define SDMMC_RXDMA32_CONFIG (DMA_SCR_PFCTRL | DMA_SCR_DIR_P2M|DMA_SCR_MINC | \ DMA_SCR_PSIZE_32BITS | DMA_SCR_MSIZE_32BITS | \ - CONFIG_SDIO_DMAPRIO | DMA_SCR_PBURST_INCR4 | \ - DMA_SCR_MBURST_INCR4) -#define SDIO_TXDMA32_CONFIG (DMA_SCR_PFCTRL | DMA_SCR_DIR_M2P | DMA_SCR_MINC | \ + DMA_SCR_PBURST_INCR4 | DMA_SCR_MBURST_INCR4) +# define SDMMC_TXDMA32_CONFIG (DMA_SCR_PFCTRL | DMA_SCR_DIR_M2P | DMA_SCR_MINC | \ DMA_SCR_PSIZE_32BITS | DMA_SCR_MSIZE_32BITS | \ - CONFIG_SDIO_DMAPRIO | DMA_SCR_PBURST_INCR4 | \ - DMA_SCR_MBURST_INCR4) + DMA_SCR_PBURST_INCR4 | DMA_SCR_MBURST_INCR4) + +#ifdef DMAMAP_SDMMC1 -/* SDIO DMA Channel/Stream selection. There +/* SDMMC DMA Channel/Stream selection. There * are multiple DMA stream options that must be dis-ambiguated in the board.h * file. */ -#define SDIO_DMACHAN DMAMAP_SDMMC1 +# define SDMMC1_DMACHAN DMAMAP_SDMMC1 +#endif + + +#ifdef DMAMAP_SDMMC2 + +/* SDMMC DMA Channel/Stream selection. There + * are multiple DMA stream options that must be dis-ambiguated in the board.h + * file. + */ + +# define SDMMC2_DMACHAN DMAMAP_SDMMC2 +#endif /* FIFO sizes */ -#define SDIO_HALFFIFO_WORDS (8) -#define SDIO_HALFFIFO_BYTES (8*4) +#define SDMMC_HALFFIFO_WORDS (8) +#define SDMMC_HALFFIFO_BYTES (8*4) /* Data transfer interrupt mask bits */ -#define SDIO_RECV_MASK (SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | \ - SDIO_MASK_DATAENDIE | SDIO_MASK_RXOVERRIE | \ - SDIO_MASK_RXFIFOHFIE | SDIO_MASK_STBITERRIE) -#define SDIO_SEND_MASK (SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | \ - SDIO_MASK_DATAENDIE | SDIO_MASK_TXUNDERRIE | \ - SDIO_MASK_TXFIFOHEIE | SDIO_MASK_STBITERRIE) -#define SDIO_DMARECV_MASK (SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | \ - SDIO_MASK_DATAENDIE | SDIO_MASK_RXOVERRIE | \ - SDIO_MASK_STBITERRIE) -#define SDIO_DMASEND_MASK (SDIO_MASK_DCRCFAILIE | SDIO_MASK_DTIMEOUTIE | \ - SDIO_MASK_DATAENDIE | SDIO_MASK_TXUNDERRIE | \ - SDIO_MASK_STBITERRIE) +#define STM32_SDMMC_RECV_MASK (STM32_SDMMC_MASK_DCRCFAILIE | \ + STM32_SDMMC_MASK_DTIMEOUTIE | \ + STM32_SDMMC_MASK_DATAENDIE | \ + STM32_SDMMC_MASK_RXOVERRIE | \ + STM32_SDMMC_MASK_RXFIFOHFIE | \ + STM32_SDMMC_MASK_STBITERRIE) + +#define STM32_SDMMC_SEND_MASK (STM32_SDMMC_MASK_DCRCFAILIE | \ + STM32_SDMMC_MASK_DTIMEOUTIE | \ + STM32_SDMMC_MASK_DATAENDIE | \ + STM32_SDMMC_MASK_TXUNDERRIE | \ + STM32_SDMMC_MASK_TXFIFOHEIE | \ + STM32_SDMMC_MASK_STBITERRIE) + +#define STM32_SDMMC_DMARECV_MASK (STM32_SDMMC_MASK_DCRCFAILIE | \ + STM32_SDMMC_MASK_DTIMEOUTIE | \ + STM32_SDMMC_MASK_DATAENDIE | \ + STM32_SDMMC_MASK_RXOVERRIE | \ + STM32_SDMMC_MASK_STBITERRIE) + +#define STM32_SDMMC_DMASEND_MASK (STM32_SDMMC_MASK_DCRCFAILIE | \ + STM32_SDMMC_MASK_DTIMEOUTIE | \ + STM32_SDMMC_MASK_DATAENDIE | \ + STM32_SDMMC_MASK_TXUNDERRIE | \ + STM32_SDMMC_MASK_STBITERRIE) /* Event waiting interrupt mask bits */ -#define SDIO_CMDDONE_STA (SDIO_STA_CMDSENT) -#define SDIO_RESPDONE_STA (SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL | \ - SDIO_STA_CMDREND) -#define SDIO_XFRDONE_STA (0) +#define STM32_SDMMC_CMDDONE_STA (STM32_SDMMC_STA_CMDSENT) + +#define STM32_SDMMC_RESPDONE_STA (STM32_SDMMC_STA_CTIMEOUT | \ + STM32_SDMMC_STA_CCRCFAIL | \ + STM32_SDMMC_STA_CMDREND) + +#define STM32_SDMMC_XFRDONE_STA (0) + +#define STM32_SDMMC_CMDDONE_MASK (STM32_SDMMC_MASK_CMDSENTIE) + +#define STM32_SDMMC_RESPDONE_MASK (STM32_SDMMC_MASK_CCRCFAILIE | \ + STM32_SDMMC_MASK_CTIMEOUTIE | \ + STM32_SDMMC_MASK_CMDRENDIE) + +#define STM32_SDMMC_XFRDONE_MASK (0) + +#define STM32_SDMMC_CMDDONE_ICR (STM32_SDMMC_ICR_CMDSENTC | \ + STM32_SDMMC_ICR_DBCKENDC) -#define SDIO_CMDDONE_MASK (SDIO_MASK_CMDSENTIE) -#define SDIO_RESPDONE_MASK (SDIO_MASK_CCRCFAILIE | SDIO_MASK_CTIMEOUTIE | \ - SDIO_MASK_CMDRENDIE) -#define SDIO_XFRDONE_MASK (0) +#define STM32_SDMMC_RESPDONE_ICR (STM32_SDMMC_ICR_CTIMEOUTC | \ + STM32_SDMMC_ICR_CCRCFAILC | \ + STM32_SDMMC_ICR_CMDRENDC | \ + STM32_SDMMC_ICR_DBCKENDC) -#define SDIO_CMDDONE_ICR (SDIO_ICR_CMDSENTC | SDIO_ICR_DBCKENDC) -#define SDIO_RESPDONE_ICR (SDIO_ICR_CTIMEOUTC | SDIO_ICR_CCRCFAILC | \ - SDIO_ICR_CMDRENDC | SDIO_ICR_DBCKENDC) -#define SDIO_XFRDONE_ICR (SDIO_ICR_DATAENDC | SDIO_ICR_DCRCFAILC | \ - SDIO_ICR_DTIMEOUTC | SDIO_ICR_RXOVERRC | \ - SDIO_ICR_TXUNDERRC | SDIO_ICR_STBITERRC | \ - SDIO_ICR_DBCKENDC) +#define STM32_SDMMC_XFRDONE_ICR (STM32_SDMMC_ICR_DATAENDC | \ + STM32_SDMMC_ICR_DCRCFAILC | \ + STM32_SDMMC_ICR_DTIMEOUTC | \ + STM32_SDMMC_ICR_RXOVERRC | \ + STM32_SDMMC_ICR_TXUNDERRC | \ + STM32_SDMMC_ICR_STBITERRC | \ + STM32_SDMMC_ICR_DBCKENDC) -#define SDIO_WAITALL_ICR (SDIO_CMDDONE_ICR | SDIO_RESPDONE_ICR | \ - SDIO_XFRDONE_ICR | SDIO_ICR_DBCKENDC) +#define STM32_SDMMC_WAITALL_ICR (STM32_SDMMC_CMDDONE_ICR | \ + STM32_SDMMC_RESPDONE_ICR | \ + STM32_SDMMC_XFRDONE_ICR | \ + STM32_SDMMC_ICR_DBCKENDC) /* Let's wait until we have both SDIO transfer complete and DMA complete. */ -#define SDIO_XFRDONE_FLAG (1) -#define SDIO_DMADONE_FLAG (2) -#define SDIO_ALLDONE (3) + +#define SDMMC_XFRDONE_FLAG (1) +#define SDMMC_DMADONE_FLAG (2) +#define SDMMC_ALLDONE (3) /* Register logging support */ -#ifdef CONFIG_SDIO_XFRDEBUG +#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG # ifdef CONFIG_SDIO_DMA # define SAMPLENDX_BEFORE_SETUP 0 # define SAMPLENDX_BEFORE_ENABLE 1 @@ -262,13 +325,27 @@ * Private Types ****************************************************************************/ -/* This structure defines the state of the STM32 SDIO interface */ +/* This structure defines the state of the STM32 SDMMC interface */ struct stm32_dev_s { struct sdio_dev_s dev; /* Standard, base SDIO interface */ /* STM32-specific extensions */ + uint32_t base; + int nirq; + xcpt_t handler; +#ifdef CONFIG_ARCH_IRQPRIO + int irqprio; +#endif +#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE + uint32_t d0_gpio; + xcpt_t wrchandler; +#endif +#ifdef CONFIG_SDIO_DMA + uint32_t dmapri; +#endif + /* Event support */ sem_t waitsem; /* Implements event waiting */ @@ -295,7 +372,7 @@ struct stm32_dev_s bool widebus; /* Required for DMA support */ #ifdef CONFIG_SDIO_DMA - volatile uint8_t xfrflags; /* Used to synchronize SDIO and DMA completion events */ + volatile uint8_t xfrflags; /* Used to synchronize SDMMC and DMA completion events */ bool dmamode; /* true: DMA mode transfer */ DMA_HANDLE dma; /* Handle for DMA channel */ #endif @@ -303,7 +380,7 @@ struct stm32_dev_s /* Register logging support */ -#ifdef CONFIG_SDIO_XFRDEBUG +#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG struct stm32_sdioregs_s { uint8_t power; @@ -332,20 +409,24 @@ struct stm32_sampleregs_s /* Low-level helpers ********************************************************/ +static inline void sdmmc_putreg32(struct stm32_dev_s *priv, uint32_t value,\ + int offset); +static inline uint32_t sdmmc_getreg32(struct stm32_dev_s *priv, int offset); static void stm32_takesem(struct stm32_dev_s *priv); #define stm32_givesem(priv) (sem_post(&priv->waitsem)) -static inline void stm32_setclkcr(uint32_t clkcr); +static inline void stm32_setclkcr(struct stm32_dev_s *priv, uint32_t clkcr); static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask, sdio_eventset_t waitevents, sdio_eventset_t wkupevents); static void stm32_configxfrints(struct stm32_dev_s *priv, uint32_t xfrmask); -static void stm32_setpwrctrl(uint32_t pwrctrl); -static inline uint32_t stm32_getpwrctrl(void); +static void stm32_setpwrctrl(struct stm32_dev_s *priv, uint32_t pwrctrl); +static inline uint32_t stm32_getpwrctrl(struct stm32_dev_s *priv); /* DMA Helpers **************************************************************/ -#ifdef CONFIG_SDIO_XFRDEBUG +#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG static void stm32_sampleinit(void); -static void stm32_sdiosample(struct stm32_sdioregs_s *regs); +static void stm32_sdiosample(struct stm32_dev_s *priv, + struct stm32_sdioregs_s *regs); static void stm32_sample(struct stm32_dev_s *priv, int index); static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg); static void stm32_dumpsample(struct stm32_dev_s *priv, @@ -364,8 +445,9 @@ static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg); /* Data Transfer Helpers ****************************************************/ static uint8_t stm32_log2(uint16_t value); -static void stm32_dataconfig(uint32_t timeout, uint32_t dlen, uint32_t dctrl); -static void stm32_datadisable(void); +static void stm32_dataconfig(struct stm32_dev_s *priv, uint32_t timeout, + uint32_t dlen, uint32_t dctrl); +static void stm32_datadisable(struct stm32_dev_s *priv); static void stm32_sendfifo(struct stm32_dev_s *priv); static void stm32_recvfifo(struct stm32_dev_s *priv); static void stm32_eventtimeout(int argc, uint32_t arg); @@ -374,9 +456,22 @@ static void stm32_endtransfer(struct stm32_dev_s *priv, sdio_eventset_t wkupeven /* Interrupt Handling *******************************************************/ -static int stm32_interrupt(int irq, void *context); +static int stm32_sdmmc_interrupt(struct stm32_dev_s *sdmmc_dev); + +#ifdef CONFIG_STM32F7_SDMMC1 +static int stm32_sdmmc1_interrupt(int irq, void *context); +#endif +#ifdef CONFIG_STM32F7_SDMMC2 +static int stm32_sdmmc2_interrupt(int irq, void *context); +#endif + #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE -static int stm32_rdyinterrupt(int irq, void *context); +#ifdef CONFIG_STM32F7_SDMMC1 +static int stm32_sdmmc1_rdyinterrupt(int irq, void *context); +#endif +#ifdef CONFIG_STM32F7_SDMMC2 +static int stm32_sdmmc2_rdyinterrupt(int irq, void *context); +#endif #endif /* SDIO interface methods ***************************************************/ @@ -444,13 +539,69 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev, /* Initialization/uninitialization/reset ************************************/ static void stm32_callback(void *arg); -static void stm32_default(void); +static void stm32_default(struct stm32_dev_s *priv); /**************************************************************************** * Private Data ****************************************************************************/ - -struct stm32_dev_s g_sdiodev = +#ifdef CONFIG_STM32F7_SDMMC1 +struct stm32_dev_s g_sdmmcdev1 = +{ + .dev = + { +#ifdef CONFIG_SDIO_MUXBUS + .lock = stm32_lock, +#endif + .reset = stm32_reset, + .status = stm32_status, + .widebus = stm32_widebus, + .clock = stm32_clock, + .attach = stm32_attach, + .sendcmd = stm32_sendcmd, +#ifdef CONFIG_SDIO_BLOCKSETUP + .blocksetup = stm32_blocksetup, /* Not implemented yet */ +#endif + .recvsetup = stm32_recvsetup, + .sendsetup = stm32_sendsetup, + .cancel = stm32_cancel, + .waitresponse = stm32_waitresponse, + .recvR1 = stm32_recvshortcrc, + .recvR2 = stm32_recvlong, + .recvR3 = stm32_recvshort, + .recvR4 = stm32_recvnotimpl, + .recvR5 = stm32_recvnotimpl, + .recvR6 = stm32_recvshortcrc, + .recvR7 = stm32_recvshort, + .waitenable = stm32_waitenable, + .eventwait = stm32_eventwait, + .callbackenable = stm32_callbackenable, + .registercallback = stm32_registercallback, +#ifdef CONFIG_SDIO_DMA + .dmasupported = stm32_dmasupported, +#ifdef CONFIG_SDIO_PREFLIGHT + .dmapreflight = stm32_dmapreflight, +#endif + .dmarecvsetup = stm32_dmarecvsetup, + .dmasendsetup = stm32_dmasendsetup, +#endif + }, + .base = STM32_SDMMC1_BASE, + .nirq = STM32_IRQ_SDMMC1, + .handler = stm32_sdmmc1_interrupt, +#ifdef CONFIG_SDMMC1_PRI + .irqprio = CONFIG_SDMMC1_PRI, +#endif +#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE + .d0_gpio = GPIO_SDMMC1_D0, + .wrchandler = stm32_sdmmc1_rdyinterrupt, +#endif +#ifdef CONFIG_SDMMC1_DMAPRIO + .dmapri = CONFIG_SDMMC1_DMAPRIO, +#endif +}; +#endif +#ifdef CONFIG_STM32F7_SDMMC2 +struct stm32_dev_s g_sdmmcdev2 = { .dev = { @@ -490,11 +641,24 @@ struct stm32_dev_s g_sdiodev = .dmasendsetup = stm32_dmasendsetup, #endif }, + .base = STM32_SDMMC2_BASE, + .nirq = STM32_IRQ_SDMMC2, + .handler = stm32_sdmmc2_interrupt, +#ifdef CONFIG_SDMMC2_PRI + .irqprio = CONFIG_SDMMC2_PRI, +#endif +#ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE + .d0_gpio = GPIO_SDMMC2_D0, + .wrchandler = stm32_sdmmc2_rdyinterrupt, +#endif +#ifdef CONFIG_SDMMC2_DMAPRIO + .dmapri = CONFIG_SDMMC2_DMAPRIO, +#endif }; - +#endif /* Register logging support */ -#ifdef CONFIG_SDIO_XFRDEBUG +#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG static struct stm32_sampleregs_s g_sampleregs[DEBUG_NSAMPLES]; #endif @@ -505,6 +669,44 @@ static struct stm32_sampleregs_s g_sampleregs[DEBUG_NSAMPLES]; /**************************************************************************** * Low-level Helpers ****************************************************************************/ + +/**************************************************************************** + * Name: sdmmc_putreg32 + ****************************************************************************/ + +static inline void sdmmc_putreg32(struct stm32_dev_s *priv, uint32_t value,\ + int offset) +{ + putreg32(value, priv->base + offset); +} + +/**************************************************************************** + * Name: sdmmc_gettreg32 + ****************************************************************************/ + +static inline uint32_t sdmmc_getreg32(struct stm32_dev_s *priv, int offset) +{ + return getreg32(priv->base + offset); +} + +/**************************************************************************** + * Name: sdmmc_modifyreg32 + ****************************************************************************/ + +static inline void sdmmc_modifyreg32(struct stm32_dev_s *priv, int offset, + uint32_t clearbits, uint32_t setbits) +{ + irqstate_t flags; + int32_t regval; + + flags = enter_critical_section(); + regval = getreg32(priv->base + offset); + regval &= ~clearbits; + regval |= setbits; + putreg32(regval, priv->base + offset); + leave_critical_section(flags); +} + /**************************************************************************** * Name: stm32_takesem * @@ -513,7 +715,7 @@ static struct stm32_sampleregs_s g_sampleregs[DEBUG_NSAMPLES]; * of signals). * * Input Parameters: - * dev - Instance of the SDIO device driver state structure. + * priv - Instance of the SDMMC private state structure. * * Returned Value: * None @@ -544,6 +746,7 @@ static void stm32_takesem(struct stm32_dev_s *priv) * CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, and HWFC_EN * * Input Parameters: + * priv - Instance of the SDMMC private state structure. * clkcr - A new CLKCR setting for the above mentions bits (other bits * are ignored. * @@ -552,27 +755,30 @@ static void stm32_takesem(struct stm32_dev_s *priv) * ****************************************************************************/ -static inline void stm32_setclkcr(uint32_t clkcr) +static inline void stm32_setclkcr(struct stm32_dev_s *priv, uint32_t clkcr) { - uint32_t regval = getreg32(STM32_SDMMC1_CLKCR); + uint32_t regval = sdmmc_getreg32(priv, STM32_SDMMC_CLKCR_OFFSET); /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */ - regval &= ~(SDIO_CLKCR_CLKDIV_MASK | SDIO_CLKCR_PWRSAV | SDIO_CLKCR_BYPASS | - SDIO_CLKCR_WIDBUS_MASK | SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN | - SDIO_CLKCR_CLKEN); + regval &= ~(STM32_SDMMC_CLKCR_CLKDIV_MASK | STM32_SDMMC_CLKCR_PWRSAV | + STM32_SDMMC_CLKCR_BYPASS | STM32_SDMMC_CLKCR_WIDBUS_MASK | + STM32_SDMMC_CLKCR_NEGEDGE | STM32_SDMMC_CLKCR_HWFC_EN | + STM32_SDMMC_CLKCR_CLKEN); /* Replace with user provided settings */ - clkcr &= (SDIO_CLKCR_CLKDIV_MASK | SDIO_CLKCR_PWRSAV | SDIO_CLKCR_BYPASS | - SDIO_CLKCR_WIDBUS_MASK | SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN | - SDIO_CLKCR_CLKEN); + clkcr &= (STM32_SDMMC_CLKCR_CLKDIV_MASK | STM32_SDMMC_CLKCR_PWRSAV | + STM32_SDMMC_CLKCR_BYPASS | STM32_SDMMC_CLKCR_WIDBUS_MASK | + STM32_SDMMC_CLKCR_NEGEDGE | STM32_SDMMC_CLKCR_HWFC_EN | + STM32_SDMMC_CLKCR_CLKEN); regval |= clkcr; - putreg32(regval, STM32_SDMMC1_CLKCR); + sdmmc_putreg32(priv, regval, STM32_SDMMC_CLKCR_OFFSET); - finfo("CLKCR: %08x PWR: %08x\n", - getreg32(STM32_SDMMC1_CLKCR), getreg32(STM32_SDMMC1_POWER)); + mcinfo("CLKCR: %08x PWR: %08x\n", + sdmmc_getreg32(priv, STM32_SDMMC_CLKCR_OFFSET), + sdmmc_getreg32(priv, STM32_SDMMC_POWER_OFFSET)); } /**************************************************************************** @@ -582,7 +788,7 @@ static inline void stm32_setclkcr(uint32_t clkcr) * Enable/disable SDIO interrupts needed to suport the wait function * * Input Parameters: - * priv - A reference to the SDIO device state structure + * priv - Instance of the SDMMC private state structure. * waitmask - The set of bits in the SDIO MASK register to set * waitevents - Waited for events * wkupevent - Wake-up events @@ -609,24 +815,24 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask, #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE if ((waitmask & SDIOWAIT_WRCOMPLETE) != 0) { - /* Do not use this in STM32_SDMMC1_MASK register */ + /* Do not use this in STM32_SDMMC_MASK register */ waitmask &= !SDIOWAIT_WRCOMPLETE; - pinset = GPIO_SDMMC1_D0 & (GPIO_PORT_MASK | GPIO_PIN_MASK); + pinset = priv->d0_gpio & (GPIO_PORT_MASK | GPIO_PIN_MASK); pinset |= (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI); - /* Arm the SDIO_D Ready and install Isr */ + /* Arm the SDMMC_D Ready and install Isr */ - stm32_gpiosetevent(pinset, true, false, false, stm32_rdyinterrupt); + stm32_gpiosetevent(pinset, true, false, false, priv->wrchandler); } - /* Disarm SDIO_D ready */ + /* Disarm SDMMC_D ready */ if ((wkupevent & SDIOWAIT_WRCOMPLETE) != 0) { - stm32_gpiosetevent(GPIO_SDMMC1_D0, false, false, false , NULL); - stm32_configgpio(GPIO_SDMMC1_D0); + stm32_gpiosetevent(priv->d0_gpio, false, false, false , NULL); + stm32_configgpio(priv->d0_gpio); } #endif @@ -636,7 +842,7 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask, #ifdef CONFIG_SDIO_DMA priv->xfrflags = 0; #endif - putreg32(priv->xfrmask | priv->waitmask, STM32_SDMMC1_MASK); + sdmmc_putreg32(priv, priv->xfrmask | priv->waitmask, STM32_SDMMC_MASK_OFFSET); leave_critical_section(flags); } @@ -647,7 +853,7 @@ static void stm32_configwaitints(struct stm32_dev_s *priv, uint32_t waitmask, * Enable SDIO interrupts needed to support the data transfer event * * Input Parameters: - * priv - A reference to the SDIO device state structure + * priv - Instance of the SDMMC private state structure. * xfrmask - The set of bits in the SDIO MASK register to set * * Returned Value: @@ -660,7 +866,7 @@ static void stm32_configxfrints(struct stm32_dev_s *priv, uint32_t xfrmask) irqstate_t flags; flags = enter_critical_section(); priv->xfrmask = xfrmask; - putreg32(priv->xfrmask | priv->waitmask, STM32_SDMMC1_MASK); + sdmmc_putreg32(priv, priv->xfrmask | priv->waitmask, STM32_SDMMC_MASK_OFFSET); leave_critical_section(flags); } @@ -672,6 +878,7 @@ static void stm32_configxfrints(struct stm32_dev_s *priv, uint32_t xfrmask) * ON or OFF * * Input Parameters: + * priv - Instance of the SDMMC private state structure. * clkcr - A new PWRCTRL setting * * Returned Value: @@ -679,14 +886,14 @@ static void stm32_configxfrints(struct stm32_dev_s *priv, uint32_t xfrmask) * ****************************************************************************/ -static void stm32_setpwrctrl(uint32_t pwrctrl) +static void stm32_setpwrctrl(struct stm32_dev_s *priv, uint32_t pwrctrl) { uint32_t regval; - regval = getreg32(STM32_SDMMC1_POWER); - regval &= ~SDIO_POWER_PWRCTRL_MASK; + regval = sdmmc_getreg32(priv, STM32_SDMMC_POWER_OFFSET); + regval &= ~STM32_SDMMC_POWER_PWRCTRL_MASK; regval |= pwrctrl; - putreg32(regval, STM32_SDMMC1_POWER); + sdmmc_putreg32(priv, regval, STM32_SDMMC_POWER_OFFSET); } /**************************************************************************** @@ -698,16 +905,17 @@ static void stm32_setpwrctrl(uint32_t pwrctrl) * or OFF * * Input Parameters: - * None + * priv - Instance of the SDMMC private state structure. * * Returned Value: * The current value of the the PWRCTRL field of the SDIO POWER register. * ****************************************************************************/ -static inline uint32_t stm32_getpwrctrl(void) +static inline uint32_t stm32_getpwrctrl(struct stm32_dev_s *priv) { - return getreg32(STM32_SDMMC1_POWER) & SDIO_POWER_PWRCTRL_MASK; + return sdmmc_getreg32(priv, STM32_SDMMC_POWER_OFFSET) & + STM32_SDMMC_POWER_PWRCTRL_MASK; } /**************************************************************************** @@ -722,7 +930,7 @@ static inline uint32_t stm32_getpwrctrl(void) * ****************************************************************************/ -#ifdef CONFIG_SDIO_XFRDEBUG +#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG static void stm32_sampleinit(void) { memset(g_sampleregs, 0xff, DEBUG_NSAMPLES * sizeof(struct stm32_sampleregs_s)); @@ -737,18 +945,19 @@ static void stm32_sampleinit(void) * ****************************************************************************/ -#ifdef CONFIG_SDIO_XFRDEBUG -static void stm32_sdiosample(struct stm32_sdioregs_s *regs) +#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG +static void stm32_sdiosample(struct stm32_dev_s *priv, + struct stm32_sdioregs_s *regs) { - regs->power = (uint8_t)getreg32(STM32_SDMMC1_POWER); - regs->clkcr = (uint16_t)getreg32(STM32_SDMMC1_CLKCR); - regs->dctrl = (uint16_t)getreg32(STM32_SDMMC1_DCTRL); - regs->dtimer = getreg32(STM32_SDMMC1_DTIMER); - regs->dlen = getreg32(STM32_SDMMC1_DLEN); - regs->dcount = getreg32(STM32_SDMMC1_DCOUNT); - regs->sta = getreg32(STM32_SDMMC1_STA); - regs->mask = getreg32(STM32_SDMMC1_MASK); - regs->fifocnt = getreg32(STM32_SDMMC1_FIFOCNT); + regs->power = (uint8_t)sdmmc_getreg32(priv, STM32_SDMMC_POWER_OFFSET); + regs->clkcr = (uint16_t)sdmmc_getreg32(priv, STM32_SDMMC_CLKCR_OFFSET); + regs->dctrl = (uint16_t)sdmmc_getreg32(priv, STM32_SDMMC_DCTRL_OFFSET); + regs->dtimer = sdmmc_getreg32(priv, STM32_SDMMC_DTIMER_OFFSET); + regs->dlen = sdmmc_getreg32(priv, STM32_SDMMC_DLEN_OFFSET); + regs->dcount = sdmmc_getreg32(priv, STM32_SDMMC_DCOUNT_OFFSET); + regs->sta = sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET); + regs->mask = sdmmc_getreg32(priv, STM32_SDMMC_MASK_OFFSET); + regs->fifocnt = sdmmc_getreg32(priv, STM32_SDMMC_FIFOCNT_OFFSET); } #endif @@ -760,7 +969,7 @@ static void stm32_sdiosample(struct stm32_sdioregs_s *regs) * ****************************************************************************/ -#ifdef CONFIG_SDIO_XFRDEBUG +#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG static void stm32_sample(struct stm32_dev_s *priv, int index) { struct stm32_sampleregs_s *regs = &g_sampleregs[index]; @@ -772,7 +981,7 @@ static void stm32_sample(struct stm32_dev_s *priv, int index) } #endif - stm32_sdiosample(®s->sdio); + stm32_sdiosample(priv, ®s->sdio); } #endif @@ -784,19 +993,19 @@ static void stm32_sample(struct stm32_dev_s *priv, int index) * ****************************************************************************/ -#ifdef CONFIG_SDIO_XFRDEBUG +#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg) { - ferr("SDIO Registers: %s\n", msg); - ferr(" POWER[%08x]: %08x\n", STM32_SDMMC1_POWER, regs->power); - ferr(" CLKCR[%08x]: %08x\n", STM32_SDMMC1_CLKCR, regs->clkcr); - ferr(" DCTRL[%08x]: %08x\n", STM32_SDMMC1_DCTRL, regs->dctrl); - ferr(" DTIMER[%08x]: %08x\n", STM32_SDMMC1_DTIMER, regs->dtimer); - ferr(" DLEN[%08x]: %08x\n", STM32_SDMMC1_DLEN, regs->dlen); - ferr(" DCOUNT[%08x]: %08x\n", STM32_SDMMC1_DCOUNT, regs->dcount); - ferr(" STA[%08x]: %08x\n", STM32_SDMMC1_STA, regs->sta); - ferr(" MASK[%08x]: %08x\n", STM32_SDMMC1_MASK, regs->mask); - ferr("FIFOCNT[%08x]: %08x\n", STM32_SDMMC1_FIFOCNT, regs->fifocnt); + mcinfo("SDIO Registers: %s\n", msg); + mcinfo(" POWER[%08x]: %08x\n", STM32_SDMMC_POWER_OFFSET, regs->power); + mcinfo(" CLKCR[%08x]: %08x\n", STM32_SDMMC_CLKCR_OFFSET, regs->clkcr); + mcinfo(" DCTRL[%08x]: %08x\n", STM32_SDMMC_DCTRL_OFFSET, regs->dctrl); + mcinfo(" DTIMER[%08x]: %08x\n", STM32_SDMMC_DTIMER_OFFSET, regs->dtimer); + mcinfo(" DLEN[%08x]: %08x\n", STM32_SDMMC_DLEN_OFFSET, regs->dlen); + mcinfo(" DCOUNT[%08x]: %08x\n", STM32_SDMMC_DCOUNT_OFFSET, regs->dcount); + mcinfo(" STA[%08x]: %08x\n", STM32_SDMMC_STA_OFFSET, regs->sta); + mcinfo(" MASK[%08x]: %08x\n", STM32_SDMMC_MASK_OFFSET, regs->mask); + mcinfo("FIFOCNT[%08x]: %08x\n", STM32_SDMMC_FIFOCNT_OFFSET, regs->fifocnt); } #endif @@ -808,7 +1017,7 @@ static void stm32_sdiodump(struct stm32_sdioregs_s *regs, const char *msg) * ****************************************************************************/ -#ifdef CONFIG_SDIO_XFRDEBUG +#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG static void stm32_dumpsample(struct stm32_dev_s *priv, struct stm32_sampleregs_s *regs, const char *msg) { @@ -831,7 +1040,7 @@ static void stm32_dumpsample(struct stm32_dev_s *priv, * ****************************************************************************/ -#ifdef CONFIG_SDIO_XFRDEBUG +#ifdef CONFIG_STM32F7_SDMMC_XFRDEBUG static void stm32_dumpsamples(struct stm32_dev_s *priv) { stm32_dumpsample(priv, &g_sampleregs[SAMPLENDX_BEFORE_SETUP], "Before setup"); @@ -882,7 +1091,7 @@ static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg) if ((status & DMA_STATUS_ERROR) != 0) { - fllerr("DMA error %02x, remaining: %d\n", status, priv->remaining); + mcerr("DMA error %02x, remaining: %d\n", status, priv->remaining); result = SDIOWAIT_ERROR; } else @@ -896,8 +1105,8 @@ static void stm32_dmacallback(DMA_HANDLE handle, uint8_t status, void *arg) * will appropriately time out. */ - priv->xfrflags |= SDIO_DMADONE_FLAG; - if (priv->xfrflags == SDIO_ALLDONE || result == SDIOWAIT_ERROR) + priv->xfrflags |= SDMMC_DMADONE_FLAG; + if (priv->xfrflags == SDMMC_ALLDONE || result == SDIOWAIT_ERROR) { stm32_endtransfer(priv, result); } @@ -947,29 +1156,27 @@ static uint8_t stm32_log2(uint16_t value) * ****************************************************************************/ -static void stm32_dataconfig(uint32_t timeout, uint32_t dlen, uint32_t dctrl) +static void stm32_dataconfig(struct stm32_dev_s *priv, uint32_t timeout, + uint32_t dlen, uint32_t dctrl) { uint32_t regval = 0; /* Enable data path */ - putreg32(timeout, STM32_SDMMC1_DTIMER); /* Set DTIMER */ - putreg32(dlen, STM32_SDMMC1_DLEN); /* Set DLEN */ + sdmmc_putreg32(priv, timeout, STM32_SDMMC_DTIMER_OFFSET); /* Set DTIMER */ + sdmmc_putreg32(priv, dlen, STM32_SDMMC_DLEN_OFFSET); /* Set DLEN */ /* Configure DCTRL DTDIR, DTMODE, and DBLOCKSIZE fields and set the DTEN * field */ - regval = getreg32(STM32_SDMMC1_DCTRL); - regval &= ~(SDIO_DCTRL_DTDIR | SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE_MASK); - dctrl &= (SDIO_DCTRL_DTDIR | SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE_MASK); - regval |= (dctrl | SDIO_DCTRL_DTEN); - -#ifdef CONFIG_SDIO_DMA - regval |= SDIO_DCTRL_DMAEN; -#endif - - putreg32(regval, STM32_SDMMC1_DCTRL); + regval = sdmmc_getreg32(priv, STM32_SDMMC_DCTRL_OFFSET); + regval &= ~(STM32_SDMMC_DCTRL_DTDIR | STM32_SDMMC_DCTRL_DTMODE | + STM32_SDMMC_DCTRL_DBLOCKSIZE_MASK); + dctrl &= (STM32_SDMMC_DCTRL_DTDIR | STM32_SDMMC_DCTRL_DTMODE | + STM32_SDMMC_DCTRL_DBLOCKSIZE_MASK); + regval |= (dctrl | STM32_SDMMC_DCTRL_DTEN); + sdmmc_putreg32(priv, regval, STM32_SDMMC_DCTRL_OFFSET); } /**************************************************************************** @@ -981,21 +1188,23 @@ static void stm32_dataconfig(uint32_t timeout, uint32_t dlen, uint32_t dctrl) * ****************************************************************************/ -static void stm32_datadisable(void) +static void stm32_datadisable(struct stm32_dev_s *priv) { uint32_t regval; /* Disable the data path */ - putreg32(SDIO_DTIMER_DATATIMEOUT, STM32_SDMMC1_DTIMER); /* Reset DTIMER */ - putreg32(0, STM32_SDMMC1_DLEN); /* Reset DLEN */ + /* Reset DTIMER */ + sdmmc_putreg32(priv, SDMMC_DTIMER_DATATIMEOUT, STM32_SDMMC_DTIMER_OFFSET); + sdmmc_putreg32(priv, 0, STM32_SDMMC_DLEN_OFFSET); /* Reset DLEN */ /* Reset DCTRL DTEN, DTDIR, DTMODE, DMAEN, and DBLOCKSIZE fields */ - regval = getreg32(STM32_SDMMC1_DCTRL); - regval &= ~(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR | SDIO_DCTRL_DTMODE | - SDIO_DCTRL_DMAEN | SDIO_DCTRL_DBLOCKSIZE_MASK); - putreg32(regval, STM32_SDMMC1_DCTRL); + regval = sdmmc_getreg32(priv, STM32_SDMMC_DCTRL_OFFSET); + regval &= ~(STM32_SDMMC_DCTRL_DTEN | STM32_SDMMC_DCTRL_DTDIR | + STM32_SDMMC_DCTRL_DTMODE | STM32_SDMMC_DCTRL_DMAEN | + STM32_SDMMC_DCTRL_DBLOCKSIZE_MASK); + sdmmc_putreg32(priv, regval, STM32_SDMMC_DCTRL_OFFSET); } /**************************************************************************** @@ -1005,7 +1214,7 @@ static void stm32_datadisable(void) * Send SDIO data in interrupt mode * * Input Parameters: - * priv - An instance of the SDIO device interface + * priv - Instance of the SDMMC private state structure. * * Returned Value: * None @@ -1023,7 +1232,7 @@ static void stm32_sendfifo(struct stm32_dev_s *priv) /* Loop while there is more data to be sent and the RX FIFO is not full */ while (priv->remaining > 0 && - (getreg32(STM32_SDMMC1_STA) & SDIO_STA_TXFIFOF) == 0) + (sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET) & STM32_SDMMC_STA_TXFIFOF) == 0) { /* Is there a full word remaining in the user buffer? */ @@ -1056,7 +1265,7 @@ static void stm32_sendfifo(struct stm32_dev_s *priv) /* Put the word in the FIFO */ - putreg32(data.w, STM32_SDMMC1_FIFO); + sdmmc_putreg32(priv, data.w, STM32_SDMMC_FIFO_OFFSET); } } @@ -1067,7 +1276,7 @@ static void stm32_sendfifo(struct stm32_dev_s *priv) * Receive SDIO data in interrupt mode * * Input Parameters: - * priv - An instance of the SDIO device interface + * priv - Instance of the SDMMC private state structure. * * Returned Value: * None @@ -1087,11 +1296,11 @@ static void stm32_recvfifo(struct stm32_dev_s *priv) */ while (priv->remaining > 0 && - (getreg32(STM32_SDMMC1_STA) & SDIO_STA_RXDAVL) != 0) + (sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET) & STM32_SDMMC_STA_RXDAVL) != 0) { /* Read the next word from the RX FIFO */ - data.w = getreg32(STM32_SDMMC1_FIFO); + data.w = sdmmc_getreg32(priv, STM32_SDMMC_FIFO_OFFSET); if (priv->remaining >= sizeof(uint32_t)) { /* Transfer the whole word to the user buffer */ @@ -1127,7 +1336,8 @@ static void stm32_recvfifo(struct stm32_dev_s *priv) * * Input Parameters: * argc - The number of arguments (should be 1) - * arg - The argument (state structure reference cast to uint32_t) + * arg - The argument (the SDMMC private state structure reference cast + * to uint32_t) * * Returned Value: * None @@ -1143,7 +1353,8 @@ static void stm32_eventtimeout(int argc, uint32_t arg) /* There is always race conditions with timer expirations. */ - DEBUGASSERT((priv->waitevents & SDIOWAIT_TIMEOUT) != 0 || priv->wkupevent != 0); + DEBUGASSERT((priv->waitevents & SDIOWAIT_TIMEOUT) != 0 || + priv->wkupevent != 0); /* Is a data transfer complete event expected? */ @@ -1152,7 +1363,7 @@ static void stm32_eventtimeout(int argc, uint32_t arg) /* Yes.. wake up any waiting threads */ stm32_endwait(priv, SDIOWAIT_TIMEOUT); - fllerr("Timeout: remaining: %d\n", priv->remaining); + mcerr("Timeout: remaining: %d\n", priv->remaining); } } @@ -1163,7 +1374,7 @@ static void stm32_eventtimeout(int argc, uint32_t arg) * Wake up a waiting thread if the waited-for event has occurred. * * Input Parameters: - * priv - An instance of the SDIO device interface + * priv - Instance of the SDMMC private state structure. * wkupevent - The event that caused the wait to end * * Returned Value: @@ -1198,7 +1409,7 @@ static void stm32_endwait(struct stm32_dev_s *priv, sdio_eventset_t wkupevent) * are detected. * * Input Parameters: - * priv - An instance of the SDIO device interface + * priv - Instance of the SDMMC private state structure. * wkupevent - The event that caused the transfer to end * * Returned Value: @@ -1209,7 +1420,8 @@ static void stm32_endwait(struct stm32_dev_s *priv, sdio_eventset_t wkupevent) * ****************************************************************************/ -static void stm32_endtransfer(struct stm32_dev_s *priv, sdio_eventset_t wkupevent) +static void stm32_endtransfer(struct stm32_dev_s *priv, + sdio_eventset_t wkupevent) { /* Disable all transfer related interrupts */ @@ -1217,7 +1429,7 @@ static void stm32_endtransfer(struct stm32_dev_s *priv, sdio_eventset_t wkupeven /* Clearing pending interrupt status on all transfer related interrupts */ - putreg32(SDIO_XFRDONE_ICR, STM32_SDMMC1_ICR); + sdmmc_putreg32(priv, STM32_SDMMC_XFRDONE_ICR, STM32_SDMMC_ICR_OFFSET); /* If this was a DMA transfer, make sure that DMA is stopped */ @@ -1256,13 +1468,14 @@ static void stm32_endtransfer(struct stm32_dev_s *priv, sdio_eventset_t wkupeven ****************************************************************************/ /**************************************************************************** - * Name: stm32_rdyinterrupt + * Name: stm32_sdmmc[1|2]_rdyinterrupt * * Description: - * SDIO ready interrupt handler + * SDMMC ready interrupt handler * * Input Parameters: - * dev - An instance of the SDIO device interface + * irq - not used + * context - not used * * Returned Value: * None @@ -1270,31 +1483,41 @@ static void stm32_endtransfer(struct stm32_dev_s *priv, sdio_eventset_t wkupeven ****************************************************************************/ #ifdef CONFIG_MMCSD_SDIOWAIT_WRCOMPLETE -static int stm32_rdyinterrupt(int irq, void *context) +# if defined(CONFIG_STM32F7_SDMMC1) +static int stm32_sdmmc1_rdyinterrupt(int irq, void *context) +{ + struct stm32_dev_s *priv = &g_sdmmcdev1; + stm32_endwait(priv, SDIOWAIT_WRCOMPLETE); + return OK; +} +# endif + +# if defined(CONFIG_STM32F7_SDMMC2) +static int stm32_sdmmc2_rdyinterrupt(int irq, void *context) { - struct stm32_dev_s *priv = &g_sdiodev; + struct stm32_dev_s *priv = &g_sdmmcdev2; stm32_endwait(priv, SDIOWAIT_WRCOMPLETE); return OK; } +# endif #endif /**************************************************************************** - * Name: stm32_interrupt + * Name: stm32_sdmmc_interrupt * * Description: - * SDIO interrupt handler + * SDMMC common interrupt handler * * Input Parameters: - * dev - An instance of the SDIO device interface + * priv - Instance of the SDMMC private state structure. * * Returned Value: * None * ****************************************************************************/ -static int stm32_interrupt(int irq, void *context) +static int stm32_sdmmc_interrupt(struct stm32_dev_s *priv) { - struct stm32_dev_s *priv = &g_sdiodev; uint32_t enabled; uint32_t pending; @@ -1305,7 +1528,8 @@ static int stm32_interrupt(int irq, void *context) * bits remaining, then we have work to do here. */ - while ((enabled = getreg32(STM32_SDMMC1_STA) & getreg32(STM32_SDMMC1_MASK)) != 0) + while ((enabled = sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET) & + sdmmc_getreg32(priv, STM32_SDMMC_MASK_OFFSET)) != 0) { /* Handle in progress, interrupt driven data transfers ****************/ @@ -1320,7 +1544,7 @@ static int stm32_interrupt(int irq, void *context) * processing a receive transaction. */ - if ((pending & SDIO_STA_RXFIFOHF) != 0) + if ((pending & STM32_SDMMC_STA_RXFIFOHF) != 0) { /* Receive data from the RX FIFO */ @@ -1332,7 +1556,7 @@ static int stm32_interrupt(int irq, void *context) * both! */ - else if ((pending & SDIO_STA_TXFIFOHE) != 0) + else if ((pending & STM32_SDMMC_STA_TXFIFOHE) != 0) { /* Send data via the TX FIFO */ @@ -1342,7 +1566,7 @@ static int stm32_interrupt(int irq, void *context) /* Handle data end events */ - if ((pending & SDIO_STA_DATAEND) != 0) + if ((pending & STM32_SDMMC_STA_DATAEND) != 0) { /* Handle any data remaining the RX FIFO. If the RX FIFO is * less than half full at the end of the transfer, then no @@ -1358,8 +1582,8 @@ static int stm32_interrupt(int irq, void *context) * finished. */ - priv->xfrflags |= SDIO_XFRDONE_FLAG; - if (priv->xfrflags == SDIO_ALLDONE) + priv->xfrflags |= SDMMC_XFRDONE_FLAG; + if (priv->xfrflags == SDMMC_ALLDONE) { stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE); } @@ -1388,51 +1612,52 @@ static int stm32_interrupt(int irq, void *context) /* Handle data block send/receive CRC failure */ - else if ((pending & SDIO_STA_DCRCFAIL) != 0) + else if ((pending & STM32_SDMMC_STA_DCRCFAIL) != 0) { /* Terminate the transfer with an error */ - fllerr("ERROR: Data block CRC failure, remaining: %d\n", priv->remaining); + mcerr("ERROR: Data block CRC failure, remaining: %d\n", + priv->remaining); stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); } /* Handle data timeout error */ - else if ((pending & SDIO_STA_DTIMEOUT) != 0) + else if ((pending & STM32_SDMMC_STA_DTIMEOUT) != 0) { /* Terminate the transfer with an error */ - fllerr("ERROR: Data timeout, remaining: %d\n", priv->remaining); + mcerr("ERROR: Data timeout, remaining: %d\n", priv->remaining); stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT); } /* Handle RX FIFO overrun error */ - else if ((pending & SDIO_STA_RXOVERR) != 0) + else if ((pending & STM32_SDMMC_STA_RXOVERR) != 0) { /* Terminate the transfer with an error */ - fllerr("ERROR: RX FIFO overrun, remaining: %d\n", priv->remaining); + mcerr("ERROR: RX FIFO overrun, remaining: %d\n", priv->remaining); stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); } /* Handle TX FIFO underrun error */ - else if ((pending & SDIO_STA_TXUNDERR) != 0) + else if ((pending & STM32_SDMMC_STA_TXUNDERR) != 0) { /* Terminate the transfer with an error */ - fllerr("ERROR: TX FIFO underrun, remaining: %d\n", priv->remaining); + mcerr("ERROR: TX FIFO underrun, remaining: %d\n", priv->remaining); stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); } /* Handle start bit error */ - else if ((pending & SDIO_STA_STBITERR) != 0) + else if ((pending & STM32_SDMMC_STA_STBITERR) != 0) { /* Terminate the transfer with an error */ - fllerr("ERROR: Start bit, remaining: %d\n", priv->remaining); + mcerr("ERROR: Start bit, remaining: %d\n", priv->remaining); stm32_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR); } } @@ -1444,7 +1669,7 @@ static int stm32_interrupt(int irq, void *context) { /* Is this a response completion event? */ - if ((pending & SDIO_RESPDONE_STA) != 0) + if ((pending & STM32_SDMMC_RESPDONE_STA) != 0) { /* Yes.. Is their a thread waiting for response done? */ @@ -1452,14 +1677,15 @@ static int stm32_interrupt(int irq, void *context) { /* Yes.. wake the thread up */ - putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, STM32_SDMMC1_ICR); + sdmmc_putreg32(priv, STM32_SDMMC_RESPDONE_ICR | + STM32_SDMMC_CMDDONE_ICR, STM32_SDMMC_ICR_OFFSET); stm32_endwait(priv, SDIOWAIT_RESPONSEDONE); } } /* Is this a command completion event? */ - if ((pending & SDIO_CMDDONE_STA) != 0) + if ((pending & STM32_SDMMC_CMDDONE_STA) != 0) { /* Yes.. Is their a thread waiting for command done? */ @@ -1467,7 +1693,8 @@ static int stm32_interrupt(int irq, void *context) { /* Yes.. wake the thread up */ - putreg32(SDIO_CMDDONE_ICR, STM32_SDMMC1_ICR); + sdmmc_putreg32(priv, STM32_SDMMC_CMDDONE_ICR, + STM32_SDMMC_ICR_OFFSET); stm32_endwait(priv, SDIOWAIT_CMDDONE); } } @@ -1477,6 +1704,49 @@ static int stm32_interrupt(int irq, void *context) return OK; } +/**************************************************************************** + * Name: stm32_sdmmc1_interrupt + * + * Description: + * SDMMC 1 interrupt handler wrapper + * + * Input Parameters: + * irq - not used + * context - not used + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_STM32F7_SDMMC1 +static int stm32_sdmmc1_interrupt(int irq, void *context) +{ + return stm32_sdmmc_interrupt(&g_sdmmcdev1); +} +#endif + +/**************************************************************************** + * Name: stm32_sdmmc2_interrupt + * + * Description: + * SDMMC 2 interrupt handler wrapper + * + * Input Parameters: + * irq - not used + * context - not used + * + * + * Returned Value: + * None + * + ****************************************************************************/ +#ifdef CONFIG_STM32F7_SDMMC2 +static int stm32_sdmmc2_interrupt(int irq, void *context) +{ + return stm32_sdmmc_interrupt(&g_sdmmcdev2); +} +#endif /**************************************************************************** * SDIO Interface Methods ****************************************************************************/ @@ -1500,11 +1770,9 @@ static int stm32_interrupt(int irq, void *context) #ifdef CONFIG_SDIO_MUXBUS static int stm32_lock(FAR struct sdio_dev_s *dev, bool lock) { - /* Single SDIO instance so there is only one possibility. The multiplex - * bus is part of board support package. + /* The multiplex bus is part of board support package. */ - - stm32_muxbus_sdio_lock(lock); + stm32_muxbus_sdio_lock(dev, lock); return OK; } #endif @@ -1531,11 +1799,12 @@ static void stm32_reset(FAR struct sdio_dev_s *dev) /* Disable clocking */ flags = enter_critical_section(); - stm32_setpwrctrl(SDIO_POWER_PWRCTRL_OFF); + sdmmc_modifyreg32(priv, STM32_SDMMC_CLKCR_OFFSET, STM32_SDMMC_CLKCR_CLKEN, 0); + stm32_setpwrctrl(priv, STM32_SDMMC_POWER_PWRCTRL_OFF); /* Put SDIO registers in their default, reset state */ - stm32_default(); + stm32_default(priv); /* Reset data */ @@ -1543,7 +1812,8 @@ static void stm32_reset(FAR struct sdio_dev_s *dev) priv->waitmask = 0; /* Interrupt enables for event waiting */ priv->wkupevent = 0; /* The event that caused the wakeup */ #ifdef CONFIG_SDIO_DMA - priv->xfrflags = 0; /* Used to synchronize SDIO and DMA completion events */ + priv->xfrflags = 0; /* Used to synchronize SDIO and DMA + * completion events */ #endif wd_cancel(priv->waitwdog); /* Cancel any timeouts */ @@ -1563,12 +1833,13 @@ static void stm32_reset(FAR struct sdio_dev_s *dev) /* Configure the SDIO peripheral */ - stm32_setclkcr(STM32_CLCKCR_INIT | SDIO_CLKCR_CLKEN); - stm32_setpwrctrl(SDIO_POWER_PWRCTRL_ON); + stm32_setclkcr(priv, STM32_CLCKCR_INIT | STM32_SDMMC_CLKCR_CLKEN); + stm32_setpwrctrl(priv, STM32_SDMMC_POWER_PWRCTRL_ON); leave_critical_section(flags); - finfo("CLCKR: %08x POWER: %08x\n", - getreg32(STM32_SDMMC1_CLKCR), getreg32(STM32_SDMMC1_POWER)); + mcinfo("CLCKR: %08x POWER: %08x\n", + sdmmc_getreg32(priv, STM32_SDMMC_CLKCR_OFFSET), + sdmmc_getreg32(priv, STM32_SDMMC_POWER_OFFSET)); } /**************************************************************************** @@ -1631,6 +1902,7 @@ static void stm32_widebus(FAR struct sdio_dev_s *dev, bool wide) static void stm32_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate) { + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; uint32_t clckr; switch (rate) @@ -1645,33 +1917,33 @@ static void stm32_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate) /* Enable in initial ID mode clocking (<400KHz) */ case CLOCK_IDMODE: - clckr = (STM32_CLCKCR_INIT | SDIO_CLKCR_CLKEN); + clckr = (STM32_CLCKCR_INIT | STM32_SDMMC_CLKCR_CLKEN); break; /* Enable in MMC normal operation clocking */ case CLOCK_MMC_TRANSFER: - clckr = (SDIO_CLKCR_MMCXFR | SDIO_CLKCR_CLKEN); + clckr = (STM32_SDMMC_CLKCR_MMCXFR | STM32_SDMMC_CLKCR_CLKEN); break; /* SD normal operation clocking (wide 4-bit mode) */ case CLOCK_SD_TRANSFER_4BIT: -#ifndef CONFIG_SDIO_WIDTH_D1_ONLY - clckr = (SDIO_CLCKR_SDWIDEXFR | SDIO_CLKCR_CLKEN); +#ifndef CONFIG_SDMMC_WIDTH_D1_ONLY + clckr = (STM32_SDMMC_CLCKR_SDWIDEXFR | STM32_SDMMC_CLKCR_CLKEN); break; #endif /* SD normal operation clocking (narrow 1-bit mode) */ case CLOCK_SD_TRANSFER_1BIT: - clckr = (SDIO_CLCKR_SDXFR | SDIO_CLKCR_CLKEN); + clckr = (STM32_SDMMC_CLCKR_SDXFR | STM32_SDMMC_CLKCR_CLKEN); break; } /* Set the new clock frequency along with the clock enable/disable bit */ - stm32_setclkcr(clckr); + stm32_setclkcr(priv, clckr); } /**************************************************************************** @@ -1690,11 +1962,13 @@ static void stm32_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate) static int stm32_attach(FAR struct sdio_dev_s *dev) { + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; int ret; /* Attach the SDIO interrupt handler */ - ret = irq_attach(STM32_IRQ_SDMMC1, stm32_interrupt); + ret = irq_attach(priv->nirq, priv->handler); + if (ret == OK) { @@ -1702,19 +1976,20 @@ static int stm32_attach(FAR struct sdio_dev_s *dev) * interrupt flags */ - putreg32(SDIO_MASK_RESET, STM32_SDMMC1_MASK); - putreg32(SDIO_ICR_STATICFLAGS, STM32_SDMMC1_ICR); + sdmmc_putreg32(priv, STM32_SDMMC_MASK_RESET, STM32_SDMMC_MASK_OFFSET); + sdmmc_putreg32(priv, STM32_SDMMC_ICR_STATICFLAGS, STM32_SDMMC_ICR_OFFSET); /* Enable SDIO interrupts at the NVIC. They can now be enabled at * the SDIO controller as needed. */ - up_enable_irq(STM32_IRQ_SDMMC1); + up_enable_irq(priv->nirq); -#ifdef CONFIG_ARCH_IRQPRIO +#if defined(CONFIG_ARCH_IRQPRIO) && (defined(CONFIG_SDMMC1_DMAPRIO) || \ + defined(CONFIG_SDMMC2_DMAPRIO)) /* Set the interrupt priority */ - up_prioritize_irq(STM32_IRQ_SDIO, CONFIG_SDIO_PRI); + up_prioritize_irq(priv->nirq, priv->irqprio); #endif } @@ -1739,25 +2014,27 @@ static int stm32_attach(FAR struct sdio_dev_s *dev) static int stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg) { + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; uint32_t regval; uint32_t cmdidx; /* Set the SDIO Argument value */ - putreg32(arg, STM32_SDMMC1_ARG); + sdmmc_putreg32(priv, arg, STM32_SDMMC_ARG_OFFSET); /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, and CPSMEN bits */ - regval = getreg32(STM32_SDMMC1_CMD); - regval &= ~(SDIO_CMD_CMDINDEX_MASK | SDIO_CMD_WAITRESP_MASK | - SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND | SDIO_CMD_CPSMEN); + regval = sdmmc_getreg32(priv, STM32_SDMMC_CMD_OFFSET); + regval &= ~(STM32_SDMMC_CMD_CMDINDEX_MASK | STM32_SDMMC_CMD_WAITRESP_MASK | + STM32_SDMMC_CMD_WAITINT | STM32_SDMMC_CMD_WAITPEND | + STM32_SDMMC_CMD_CPSMEN); /* Set WAITRESP bits */ switch (cmd & MMCSD_RESPONSE_MASK) { case MMCSD_NO_RESPONSE: - regval |= SDIO_CMD_NORESPONSE; + regval |= STM32_SDMMC_CMD_NORESPONSE; break; case MMCSD_R1_RESPONSE: @@ -1767,25 +2044,26 @@ static int stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg) case MMCSD_R5_RESPONSE: case MMCSD_R6_RESPONSE: case MMCSD_R7_RESPONSE: - regval |= SDIO_CMD_SHORTRESPONSE; + regval |= STM32_SDMMC_CMD_SHORTRESPONSE; break; case MMCSD_R2_RESPONSE: - regval |= SDIO_CMD_LONGRESPONSE; + regval |= STM32_SDMMC_CMD_LONGRESPONSE; break; } /* Set CPSMEN and the command index */ cmdidx = (cmd & MMCSD_CMDIDX_MASK) >> MMCSD_CMDIDX_SHIFT; - regval |= cmdidx | SDIO_CMD_CPSMEN; + regval |= cmdidx | STM32_SDMMC_CMD_CPSMEN; - finfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval); + mcinfo("cmd: %08x arg: %08x regval: %08x\n", cmd, arg, regval); /* Write the SDIO CMD */ - putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, STM32_SDMMC1_ICR); - putreg32(regval, STM32_SDMMC1_CMD); + sdmmc_putreg32(priv, STM32_SDMMC_RESPDONE_ICR | STM32_SDMMC_CMDDONE_ICR, + STM32_SDMMC_ICR_OFFSET); + sdmmc_putreg32(priv, regval, STM32_SDMMC_CMD_OFFSET); return OK; } @@ -1797,7 +2075,7 @@ static int stm32_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg) * (interrupt driven mode). This method will do whatever controller setup * is necessary. This would be called for SD memory just BEFORE sending * CMD13 (SEND_STATUS), CMD17 (READ_SINGLE_BLOCK), CMD18 - * (READ_MULTIPLE_BLOCKS), ACMD51 (SEND_SCR), etc. Normally, SDIO_WAITEVENT + * (READ_MULTIPLE_BLOCKS), ACMD51 (SEND_SCR), etc. Normally, SDMMC_WAITEVENT * will be called to receive the indication that the transfer is complete. * * Input Parameters: @@ -1821,7 +2099,7 @@ static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, /* Reset the DPSM configuration */ - stm32_datadisable(); + stm32_datadisable(priv); stm32_sampleinit(); stm32_sample(priv, SAMPLENDX_BEFORE_SETUP); @@ -1835,12 +2113,13 @@ static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, /* Then set up the SDIO data path */ - dblocksize = stm32_log2(nbytes) << SDIO_DCTRL_DBLOCKSIZE_SHIFT; - stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT, nbytes, dblocksize | SDIO_DCTRL_DTDIR); + dblocksize = stm32_log2(nbytes) << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT; + stm32_dataconfig(priv, SDMMC_DTIMER_DATATIMEOUT, nbytes, dblocksize | + STM32_SDMMC_DCTRL_DTDIR); /* And enable interrupts */ - stm32_configxfrints(priv, SDIO_RECV_MASK); + stm32_configxfrints(priv, STM32_SDMMC_RECV_MASK); stm32_sample(priv, SAMPLENDX_AFTER_SETUP); return OK; } @@ -1852,7 +2131,7 @@ static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, * Setup hardware in preparation for data transfer from the card. This method * will do whatever controller setup is necessary. This would be called * for SD memory just AFTER sending CMD24 (WRITE_BLOCK), CMD25 - * (WRITE_MULTIPLE_BLOCK), ... and before SDIO_SENDDATA is called. + * (WRITE_MULTIPLE_BLOCK), ... and before SDMMC_SENDDATA is called. * * Input Parameters: * dev - An instance of the SDIO device interface @@ -1864,8 +2143,8 @@ static int stm32_recvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, * ****************************************************************************/ -static int stm32_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer, - size_t nbytes) +static int stm32_sendsetup(FAR struct sdio_dev_s *dev, FAR const + uint8_t *buffer, size_t nbytes) { struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; uint32_t dblocksize; @@ -1875,7 +2154,7 @@ static int stm32_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer /* Reset the DPSM configuration */ - stm32_datadisable(); + stm32_datadisable(priv); stm32_sampleinit(); stm32_sample(priv, SAMPLENDX_BEFORE_SETUP); @@ -1889,12 +2168,12 @@ static int stm32_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer /* Then set up the SDIO data path */ - dblocksize = stm32_log2(nbytes) << SDIO_DCTRL_DBLOCKSIZE_SHIFT; - stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT, nbytes, dblocksize); + dblocksize = stm32_log2(nbytes) << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT; + stm32_dataconfig(priv, SDMMC_DTIMER_DATATIMEOUT, nbytes, dblocksize); /* Enable TX interrupts */ - stm32_configxfrints(priv, SDIO_SEND_MASK); + stm32_configxfrints(priv, STM32_SDMMC_SEND_MASK); stm32_sample(priv, SAMPLENDX_AFTER_SETUP); return OK; } @@ -1903,8 +2182,8 @@ static int stm32_sendsetup(FAR struct sdio_dev_s *dev, FAR const uint8_t *buffer * Name: stm32_cancel * * Description: - * Cancel the data transfer setup of SDIO_RECVSETUP, SDIO_SENDSETUP, - * SDIO_DMARECVSETUP or SDIO_DMASENDSETUP. This must be called to cancel + * Cancel the data transfer setup of SDMMC_RECVSETUP, SDMMC_SENDSETUP, + * SDMMC_DMARECVSETUP or SDMMC_DMASENDSETUP. This must be called to cancel * the data transfer setup if, for some reason, you cannot perform the * transfer. * @@ -1929,7 +2208,7 @@ static int stm32_cancel(FAR struct sdio_dev_s *dev) * interrupts */ - putreg32(SDIO_WAITALL_ICR, STM32_SDMMC1_ICR); + sdmmc_putreg32(priv, STM32_SDMMC_WAITALL_ICR, STM32_SDMMC_ICR_OFFSET); /* Cancel any watchdog timeout */ @@ -1972,22 +2251,23 @@ static int stm32_cancel(FAR struct sdio_dev_s *dev) static int stm32_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) { + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; int32_t timeout; uint32_t events; switch (cmd & MMCSD_RESPONSE_MASK) { case MMCSD_NO_RESPONSE: - events = SDIO_CMDDONE_STA; - timeout = SDIO_CMDTIMEOUT; + events = STM32_SDMMC_CMDDONE_STA; + timeout = SDMMC_CMDTIMEOUT; break; case MMCSD_R1_RESPONSE: case MMCSD_R1B_RESPONSE: case MMCSD_R2_RESPONSE: case MMCSD_R6_RESPONSE: - events = SDIO_RESPDONE_STA; - timeout = SDIO_LONGTIMEOUT; + events = STM32_SDMMC_RESPDONE_STA; + timeout = SDMMC_LONGTIMEOUT; break; case MMCSD_R4_RESPONSE: @@ -1996,8 +2276,8 @@ static int stm32_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) case MMCSD_R3_RESPONSE: case MMCSD_R7_RESPONSE: - events = SDIO_RESPDONE_STA; - timeout = SDIO_CMDTIMEOUT; + events = STM32_SDMMC_RESPDONE_STA; + timeout = SDMMC_CMDTIMEOUT; break; default: @@ -2006,18 +2286,18 @@ static int stm32_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) /* Then wait for the response (or timeout) */ - while ((getreg32(STM32_SDMMC1_STA) & events) == 0) + while ((sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET) & events) == 0) { if (--timeout <= 0) { - ferr("ERROR: Timeout cmd: %08x events: %08x STA: %08x\n", - cmd, events, getreg32(STM32_SDMMC1_STA)); + mcerr("ERROR: Timeout cmd: %08x events: %08x STA: %08x\n", + cmd, events, sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET)); return -ETIMEDOUT; } } - putreg32(SDIO_CMDDONE_ICR, STM32_SDMMC1_ICR); + sdmmc_putreg32(priv, STM32_SDMMC_CMDDONE_ICR, STM32_SDMMC_ICR_OFFSET); return OK; } @@ -2036,15 +2316,17 @@ static int stm32_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd) * * Returned Value: * Number of bytes sent on success; a negated errno on failure. Here a - * failure means only a faiure to obtain the requested reponse (due to + * failure means only a faiure to obtain the requested response (due to * transport problem -- timeout, CRC, etc.). The implementation only - * assures that the response is returned intacta and does not check errors + * assures that the response is returned intact and does not check errors * within the response itself. * ****************************************************************************/ -static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rshort) +static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t *rshort) { + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; #ifdef CONFIG_DEBUG_FEATURES uint32_t respcmd; #endif @@ -2077,7 +2359,7 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t #ifdef CONFIG_DEBUG_FEATURES if (!rshort) { - ferr("ERROR: rshort=NULL\n"); + mcerr("ERROR: rshort=NULL\n"); ret = -EINVAL; } @@ -2087,7 +2369,7 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R1B_RESPONSE && (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R6_RESPONSE) { - ferr("ERROR: Wrong response CMD=%08x\n", cmd); + mcerr("ERROR: Wrong response CMD=%08x\n", cmd); ret = -EINVAL; } else @@ -2095,15 +2377,15 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t { /* Check if a timeout or CRC error occurred */ - regval = getreg32(STM32_SDMMC1_STA); - if ((regval & SDIO_STA_CTIMEOUT) != 0) + regval = sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET); + if ((regval & STM32_SDMMC_STA_CTIMEOUT) != 0) { - ferr("ERROR: Command timeout: %08x\n", regval); + mcerr("ERROR: Command timeout: %08x\n", regval); ret = -ETIMEDOUT; } - else if ((regval & SDIO_STA_CCRCFAIL) != 0) + else if ((regval & STM32_SDMMC_STA_CCRCFAIL) != 0) { - ferr("ERROR: CRC failure: %08x\n", regval); + mcerr("ERROR: CRC failure: %08x\n", regval); ret = -EIO; } #ifdef CONFIG_DEBUG_FEATURES @@ -2111,10 +2393,11 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t { /* Check response received is of desired command */ - respcmd = getreg32(STM32_SDMMC1_RESPCMD); - if ((uint8_t)(respcmd & SDIO_RESPCMD_MASK) != (cmd & MMCSD_CMDIDX_MASK)) + respcmd = sdmmc_getreg32(priv, STM32_SDMMC_RESPCMD_OFFSET); + if ((uint8_t)(respcmd & STM32_SDMMC_RESPCMD_MASK) != + (cmd & MMCSD_CMDIDX_MASK)) { - ferr("ERROR: RESCMD=%02x CMD=%08x\n", respcmd, cmd); + mcerr("ERROR: RESCMD=%02x CMD=%08x\n", respcmd, cmd); ret = -EINVAL; } } @@ -2123,13 +2406,16 @@ static int stm32_recvshortcrc(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t /* Clear all pending message completion events and return the R1/R6 response */ - putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, STM32_SDMMC1_ICR); - *rshort = getreg32(STM32_SDMMC1_RESP1); + sdmmc_putreg32(priv, STM32_SDMMC_RESPDONE_ICR | STM32_SDMMC_CMDDONE_ICR, + STM32_SDMMC_ICR_OFFSET); + *rshort = sdmmc_getreg32(priv, STM32_SDMMC_RESP1_OFFSET); return ret; } -static int stm32_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlong[4]) +static int stm32_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t rlong[4]) { + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; uint32_t regval; int ret = OK; @@ -2147,7 +2433,7 @@ static int stm32_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlo if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R2_RESPONSE) { - ferr("ERROR: Wrong response CMD=%08x\n", cmd); + mcerr("ERROR: Wrong response CMD=%08x\n", cmd); ret = -EINVAL; } else @@ -2155,34 +2441,36 @@ static int stm32_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlo { /* Check if a timeout or CRC error occurred */ - regval = getreg32(STM32_SDMMC1_STA); - if (regval & SDIO_STA_CTIMEOUT) + regval = sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET); + if (regval & STM32_SDMMC_STA_CTIMEOUT) { - ferr("ERROR: Timeout STA: %08x\n", regval); + mcerr("ERROR: Timeout STA: %08x\n", regval); ret = -ETIMEDOUT; } - else if (regval & SDIO_STA_CCRCFAIL) + else if (regval & STM32_SDMMC_STA_CCRCFAIL) { - ferr("ERROR: CRC fail STA: %08x\n", regval); + mcerr("ERROR: CRC fail STA: %08x\n", regval); ret = -EIO; } } /* Return the long response */ - putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, STM32_SDMMC1_ICR); + sdmmc_putreg32(priv, STM32_SDMMC_RESPDONE_ICR | STM32_SDMMC_CMDDONE_ICR, + STM32_SDMMC_ICR_OFFSET); if (rlong) { - rlong[0] = getreg32(STM32_SDMMC1_RESP1); - rlong[1] = getreg32(STM32_SDMMC1_RESP2); - rlong[2] = getreg32(STM32_SDMMC1_RESP3); - rlong[3] = getreg32(STM32_SDMMC1_RESP4); + rlong[0] = sdmmc_getreg32(priv, STM32_SDMMC_RESP1_OFFSET); + rlong[1] = sdmmc_getreg32(priv, STM32_SDMMC_RESP2_OFFSET); + rlong[2] = sdmmc_getreg32(priv, STM32_SDMMC_RESP3_OFFSET); + rlong[3] = sdmmc_getreg32(priv, STM32_SDMMC_RESP4_OFFSET); } return ret; } static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rshort) { + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; uint32_t regval; int ret = OK; @@ -2201,7 +2489,7 @@ static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *r if ((cmd & MMCSD_RESPONSE_MASK) != MMCSD_R3_RESPONSE && (cmd & MMCSD_RESPONSE_MASK) != MMCSD_R7_RESPONSE) { - ferr("ERROR: Wrong response CMD=%08x\n", cmd); + mcerr("ERROR: Wrong response CMD=%08x\n", cmd); ret = -EINVAL; } else @@ -2211,27 +2499,31 @@ static int stm32_recvshort(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *r * a good response) */ - regval = getreg32(STM32_SDMMC1_STA); - if (regval & SDIO_STA_CTIMEOUT) + regval = sdmmc_getreg32(priv, STM32_SDMMC_STA_OFFSET); + if (regval & STM32_SDMMC_STA_CTIMEOUT) { - ferr("ERROR: Timeout STA: %08x\n", regval); + mcerr("ERROR: Timeout STA: %08x\n", regval); ret = -ETIMEDOUT; } } - putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, STM32_SDMMC1_ICR); + sdmmc_putreg32(priv, STM32_SDMMC_RESPDONE_ICR | STM32_SDMMC_CMDDONE_ICR, + STM32_SDMMC_ICR_OFFSET); if (rshort) { - *rshort = getreg32(STM32_SDMMC1_RESP1); + *rshort = sdmmc_getreg32(priv, STM32_SDMMC_RESP1_OFFSET); } return ret; } /* MMC responses not supported */ -static int stm32_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t *rnotimpl) +static int stm32_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd, + uint32_t *rnotimpl) { - putreg32(SDIO_RESPDONE_ICR | SDIO_CMDDONE_ICR, STM32_SDMMC1_ICR); + struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; + sdmmc_putreg32(priv, STM32_SDMMC_RESPDONE_ICR | STM32_SDMMC_CMDDONE_ICR, + STM32_SDMMC_ICR_OFFSET); return -ENOSYS; } @@ -2240,13 +2532,13 @@ static int stm32_recvnotimpl(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t * * Description: * Enable/disable of a set of SDIO wait events. This is part of the - * the SDIO_WAITEVENT sequence. The set of to-be-waited-for events is + * the SDMMC_WAITEVENT sequence. The set of to-be-waited-for events is * configured before calling stm32_eventwait. This is done in this way * to help the driver to eliminate race conditions between the command * setup and the subsequent events. * - * The enabled events persist until either (1) SDIO_WAITENABLE is called - * again specifying a different set of wait events, or (2) SDIO_EVENTWAIT + * The enabled events persist until either (1) SDMMC_WAITENABLE is called + * again specifying a different set of wait events, or (2) SDMMC_EVENTWAIT * returns. * * Input Parameters: @@ -2286,22 +2578,22 @@ static void stm32_waitenable(FAR struct sdio_dev_s *dev, waitmask = 0; if ((eventset & SDIOWAIT_CMDDONE) != 0) { - waitmask |= SDIO_CMDDONE_MASK; + waitmask |= STM32_SDMMC_CMDDONE_MASK; } if ((eventset & SDIOWAIT_RESPONSEDONE) != 0) { - waitmask |= SDIO_RESPDONE_MASK; + waitmask |= STM32_SDMMC_RESPDONE_MASK; } if ((eventset & SDIOWAIT_TRANSFERDONE) != 0) { - waitmask |= SDIO_XFRDONE_MASK; + waitmask |= STM32_SDMMC_XFRDONE_MASK; } /* Enable event-related interrupts */ - putreg32(SDIO_WAITALL_ICR, STM32_SDMMC1_ICR); + sdmmc_putreg32(priv, STM32_SDMMC_WAITALL_ICR, STM32_SDMMC_ICR_OFFSET); } stm32_configwaitints(priv, waitmask, eventset, 0); @@ -2312,8 +2604,8 @@ static void stm32_waitenable(FAR struct sdio_dev_s *dev, * * Description: * Wait for one of the enabled events to occur (or a timeout). Note that - * all events enabled by SDIO_WAITEVENTS are disabled when stm32_eventwait - * returns. SDIO_WAITEVENTS must be called again before stm32_eventwait + * all events enabled by SDMMC_WAITEVENTS are disabled when stm32_eventwait + * returns. SDMMC_WAITEVENTS must be called again before stm32_eventwait * can be used again. * * Input Parameters: @@ -2369,7 +2661,7 @@ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev, 1, (uint32_t)priv); if (ret != OK) { - ferr("ERROR: wd_start failed: %d\n", ret); + mcerr("ERROR: wd_start failed: %d\n", ret); } } @@ -2380,7 +2672,7 @@ static sdio_eventset_t stm32_eventwait(FAR struct sdio_dev_s *dev, * If Pin is ready and if ISR did NOT fire end the wait here */ - if (stm32_gpioread(GPIO_SDMMC1_D0) && + if (stm32_gpioread(priv->d0_gpio) && (priv->wkupevent & SDIOWAIT_WRCOMPLETE) == 0) { stm32_endwait(priv, SDIOWAIT_WRCOMPLETE); @@ -2456,7 +2748,7 @@ static void stm32_callbackenable(FAR struct sdio_dev_s *dev, { struct stm32_dev_s *priv = (struct stm32_dev_s *)dev; - finfo("eventset: %02x\n", eventset); + mcinfo("eventset: %02x\n", eventset); DEBUGASSERT(priv != NULL); priv->cbevents = eventset; @@ -2473,7 +2765,7 @@ static void stm32_callbackenable(FAR struct sdio_dev_s *dev, * thread. * * When this method is called, all callbacks should be disabled until they - * are enabled via a call to SDIO_CALLBACKENABLE + * are enabled via a call to SDMMC_CALLBACKENABLE * * Input Parameters: * dev - Device-specific state data @@ -2492,7 +2784,7 @@ static int stm32_registercallback(FAR struct sdio_dev_s *dev, /* Disable callbacks and register this callback and is argument */ - finfo("Register %p(%p)\n", callback, arg); + mcinfo("Register %p(%p)\n", callback, arg); DEBUGASSERT(priv != NULL); priv->cbevents = 0; @@ -2555,7 +2847,8 @@ static int stm32_dmapreflight(FAR struct sdio_dev_s *dev, /* DMA must be possible to the buffer */ - if (!stm32_dmacapable((uintptr_t)buffer, (buflen + 3) >> 2, SDIO_RXDMA32_CONFIG)) + if (!stm32_dmacapable((uintptr_t)buffer, (buflen + 3) >> 2, + STM32_SDMMC_RXDMA32_CONFIG | priv->dmapri)) { return -EFAULT; } @@ -2598,7 +2891,8 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, #ifdef CONFIG_ARMV7M_DCACHE /* buffer alignment is required for DMA transfers with dcache */ - if (((uintptr_t)buffer & (ARMV7M_DCACHE_LINESIZE-1)) != 0 || (buflen & (ARMV7M_DCACHE_LINESIZE-1)) != 0) + if (((uintptr_t)buffer & (ARMV7M_DCACHE_LINESIZE-1)) != 0 || + (buflen & (ARMV7M_DCACHE_LINESIZE-1)) != 0) { return -EFAULT; } @@ -2606,7 +2900,7 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, /* Reset the DPSM configuration */ - stm32_datadisable(); + stm32_datadisable(priv); /* Initialize register sampling */ @@ -2621,15 +2915,18 @@ static int stm32_dmarecvsetup(FAR struct sdio_dev_s *dev, FAR uint8_t *buffer, /* Then set up the SDIO data path */ - dblocksize = stm32_log2(buflen) << SDIO_DCTRL_DBLOCKSIZE_SHIFT; - stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT, buflen, dblocksize | SDIO_DCTRL_DTDIR); + dblocksize = stm32_log2(buflen) << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT; + stm32_dataconfig(priv, SDMMC_DTIMER_DATATIMEOUT, buflen, dblocksize | + STM32_SDMMC_DCTRL_DTDIR); /* Configure the RX DMA */ - stm32_configxfrints(priv, SDIO_DMARECV_MASK); - - stm32_dmasetup(priv->dma, STM32_SDMMC1_FIFO, (uint32_t)buffer, - (buflen + 3) >> 2, SDIO_RXDMA32_CONFIG); + stm32_configxfrints(priv, STM32_SDMMC_DMARECV_MASK); + + sdmmc_modifyreg32(priv, STM32_SDMMC_DCTRL_OFFSET, 0, STM32_SDMMC_DCTRL_DMAEN); + stm32_dmasetup(priv->dma, priv->base + STM32_SDMMC_FIFO_OFFSET, + (uint32_t)buffer, (buflen + 3) >> 2, + SDMMC_RXDMA32_CONFIG | priv->dmapri); /* Force RAM reread */ @@ -2679,7 +2976,8 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev, #ifdef CONFIG_ARMV7M_DCACHE /* buffer alignment is required for DMA transfers with dcache */ - if (((uintptr_t)buffer & (ARMV7M_DCACHE_LINESIZE-1)) != 0 || (buflen & (ARMV7M_DCACHE_LINESIZE-1)) != 0) + if (((uintptr_t)buffer & (ARMV7M_DCACHE_LINESIZE-1)) != 0 || + (buflen & (ARMV7M_DCACHE_LINESIZE-1)) != 0) { return -EFAULT; } @@ -2687,7 +2985,7 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev, /* Reset the DPSM configuration */ - stm32_datadisable(); + stm32_datadisable(priv); /* Initialize register sampling */ @@ -2706,13 +3004,13 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev, /* Then set up the SDIO data path */ - dblocksize = stm32_log2(buflen) << SDIO_DCTRL_DBLOCKSIZE_SHIFT; - stm32_dataconfig(SDIO_DTIMER_DATATIMEOUT, buflen, dblocksize); + dblocksize = stm32_log2(buflen) << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT; + stm32_dataconfig(priv, SDMMC_DTIMER_DATATIMEOUT, buflen, dblocksize); /* Configure the TX DMA */ - stm32_dmasetup(priv->dma, STM32_SDMMC1_FIFO, (uint32_t)buffer, - (buflen + 3) >> 2, SDIO_TXDMA32_CONFIG); + stm32_dmasetup(priv->dma, priv->base + STM32_SDMMC_FIFO_OFFSET, (uint32_t)buffer, + (buflen + 3) >> 2, SDMMC_TXDMA32_CONFIG | priv->dmapri); stm32_sample(priv, SAMPLENDX_BEFORE_ENABLE); @@ -2723,7 +3021,7 @@ static int stm32_dmasendsetup(FAR struct sdio_dev_s *dev, /* Enable TX interrupts */ - stm32_configxfrints(priv, SDIO_DMASEND_MASK); + stm32_configxfrints(priv, STM32_SDMMC_DMASEND_MASK); return OK; } @@ -2752,7 +3050,7 @@ static void stm32_callback(void *arg) /* Is a callback registered? */ DEBUGASSERT(priv != NULL); - finfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n", + mcinfo("Callback %p(%p) cbevents: %02x cdstatus: %02x\n", priv->callback, priv->cbarg, priv->cbevents, priv->cdstatus); if (priv->callback) @@ -2797,14 +3095,14 @@ static void stm32_callback(void *arg) { /* Yes.. queue it */ - finfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg); + mcinfo("Queuing callback to %p(%p)\n", priv->callback, priv->cbarg); (void)work_queue(HPWORK, &priv->cbwork, (worker_t)priv->callback, priv->cbarg, 0); } else { /* No.. then just call the callback here */ - finfo("Callback to %p(%p)\n", priv->callback, priv->cbarg); + mcinfo("Callback to %p(%p)\n", priv->callback, priv->cbarg); priv->callback(priv->cbarg); } } @@ -2818,17 +3116,17 @@ static void stm32_callback(void *arg) * ****************************************************************************/ -static void stm32_default(void) +static void stm32_default(struct stm32_dev_s *priv) { - putreg32(SDIO_POWER_RESET, STM32_SDMMC1_POWER); - putreg32(SDIO_CLKCR_RESET, STM32_SDMMC1_CLKCR); - putreg32(SDIO_ARG_RESET, STM32_SDMMC1_ARG); - putreg32(SDIO_CMD_RESET, STM32_SDMMC1_CMD); - putreg32(SDIO_DTIMER_RESET, STM32_SDMMC1_DTIMER); - putreg32(SDIO_DLEN_RESET, STM32_SDMMC1_DLEN); - putreg32(SDIO_DCTRL_RESET, STM32_SDMMC1_DCTRL); - putreg32(SDIO_ICR_RESET, STM32_SDMMC1_ICR); - putreg32(SDIO_MASK_RESET, STM32_SDMMC1_MASK); + sdmmc_putreg32(priv, STM32_SDMMC_POWER_RESET, STM32_SDMMC_POWER_OFFSET); + sdmmc_putreg32(priv, STM32_SDMMC_CLKCR_RESET, STM32_SDMMC_CLKCR_OFFSET); + sdmmc_putreg32(priv, STM32_SDMMC_ARG_RESET, STM32_SDMMC_ARG_OFFSET); + sdmmc_putreg32(priv, STM32_SDMMC_CMD_RESET, STM32_SDMMC_CMD_OFFSET); + sdmmc_putreg32(priv, STM32_SDMMC_DTIMER_RESET, STM32_SDMMC_DTIMER_OFFSET); + sdmmc_putreg32(priv, STM32_SDMMC_DLEN_RESET, STM32_SDMMC_DLEN_OFFSET); + sdmmc_putreg32(priv, STM32_SDMMC_DCTRL_RESET, STM32_SDMMC_DCTRL_OFFSET); + sdmmc_putreg32(priv, STM32_SDMMC_ICR_RESET, STM32_SDMMC_ICR_OFFSET); + sdmmc_putreg32(priv, STM32_SDMMC_MASK_RESET, STM32_SDMMC_MASK_OFFSET); } /**************************************************************************** @@ -2851,9 +3149,68 @@ static void stm32_default(void) FAR struct sdio_dev_s *sdio_initialize(int slotno) { - /* There is only one slot */ + struct stm32_dev_s *priv = NULL; +#ifdef CONFIG_SDIO_DMA + unsigned int dmachan; +#endif + +#ifdef CONFIG_STM32F7_SDMMC1 + if (slotno == 0) + { + /* Select SDMMC 1 */ + + priv = &g_sdmmcdev1; +#ifdef CONFIG_SDIO_DMA + dmachan = SDMMC1_DMACHAN; +#endif + + /* Configure GPIOs for 4-bit, wide-bus operation (the chip is capable of + * 8-bit wide bus operation but D4-D7 are not configured). + * + * If bus is multiplexed then there is a custom bus configuration utility + * in the scope of the board support package. + */ +#ifndef CONFIG_SDIO_MUXBUS + stm32_configgpio(GPIO_SDMMC1_D0); +#ifndef CONFIG_SDMMC1_WIDTH_D1_ONLY + stm32_configgpio(GPIO_SDMMC1_D1); + stm32_configgpio(GPIO_SDMMC1_D2); + stm32_configgpio(GPIO_SDMMC1_D3); +#endif + stm32_configgpio(GPIO_SDMMC1_CK); + stm32_configgpio(GPIO_SDMMC1_CMD); +#endif + + } + else +#endif +#ifdef CONFIG_STM32F7_SDMMC2 + if (slotno == 1) + { + /* Select SDMMC 2 */ - struct stm32_dev_s *priv = &g_sdiodev; + priv = &g_sdmmcdev2; +#ifdef CONFIG_SDIO_DMA + dmachan = SDMMC2_DMACHAN; +#endif + +#ifndef CONFIG_SDIO_MUXBUS + stm32_configgpio(GPIO_SDMMC2_D0); +#ifndef CONFIG_SDMMC2_WIDTH_D1_ONLY + stm32_configgpio(GPIO_SDMMC2_D1); + stm32_configgpio(GPIO_SDMMC2_D2); + stm32_configgpio(GPIO_SDMMC2_D3); +#endif + stm32_configgpio(GPIO_SDMMC2_CK); + stm32_configgpio(GPIO_SDMMC2_CMD); +#endif +} + else +#endif + { + mcerr("ERROR: Unsupported SDMMC slot: %d\n", slotno); + return NULL; + } /* Initialize the SDIO slot structure */ @@ -2864,41 +3221,23 @@ FAR struct sdio_dev_s *sdio_initialize(int slotno) /* Allocate a DMA channel */ #ifdef CONFIG_SDIO_DMA - priv->dma = stm32_dmachannel(SDIO_DMACHAN); + priv->dma = stm32_dmachannel(dmachan); DEBUGASSERT(priv->dma); #endif - /* Configure GPIOs for 4-bit, wide-bus operation (the chip is capable of - * 8-bit wide bus operation but D4-D7 are not configured). - * - * If bus is multiplexed then there is a custom bus configuration utility - * in the scope of the board support package. - */ - -#ifndef CONFIG_SDIO_MUXBUS - stm32_configgpio(GPIO_SDMMC1_D0); -#ifndef CONFIG_SDIO_WIDTH_D1_ONLY - stm32_configgpio(GPIO_SDMMC1_D1); - stm32_configgpio(GPIO_SDMMC1_D2); - stm32_configgpio(GPIO_SDMMC1_D3); -#endif - stm32_configgpio(GPIO_SDMMC1_CK); - stm32_configgpio(GPIO_SDMMC1_CMD); -#endif - /* Reset the card and assure that it is in the initial, unconfigured * state. */ stm32_reset(&priv->dev); - return &g_sdiodev.dev; + return &priv->dev; } /**************************************************************************** * Name: sdio_mediachange * * Description: - * Called by board-specific logic -- posssible from an interrupt handler -- + * Called by board-specific logic -- possible from an interrupt handler -- * in order to signal to the driver that a card has been inserted or * removed from the slot * @@ -2934,7 +3273,7 @@ void sdio_mediachange(FAR struct sdio_dev_s *dev, bool cardinslot) leave_critical_section(flags); - finfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus); + mcinfo("cdstatus OLD: %02x NEW: %02x\n", cdstatus, priv->cdstatus); /* Perform any requested callback if the status has changed */ @@ -2976,7 +3315,8 @@ void sdio_wrprotect(FAR struct sdio_dev_s *dev, bool wrprotect) { priv->cdstatus &= ~SDIO_STATUS_WRPROTECTED; } - finfo("cdstatus: %02x\n", priv->cdstatus); + + mcinfo("cdstatus: %02x\n", priv->cdstatus); leave_critical_section(flags); } -#endif /* CONFIG_STM32F7_SDMMC1 */ +#endif /* CONFIG_STM32F7_SDMMC1 || CONFIG_STM32F7_SDMMC2 */ diff --git a/arch/arm/src/stm32f7/stm32_sdmmc.h b/arch/arm/src/stm32f7/stm32_sdmmc.h index 12b6348559f7c2992eba0415677f489347cbc7c7..8e722497c5f296141a7fd40b87f4c581c0806c5a 100644 --- a/arch/arm/src/stm32f7/stm32_sdmmc.h +++ b/arch/arm/src/stm32f7/stm32_sdmmc.h @@ -40,13 +40,13 @@ * Included Files ************************************************************************************/ -#include "chip/stm32_sdmmc.h" - #include #include #include #include "chip.h" +#include "chip/stm32_sdmmc.h" + /************************************************************************************ * Public Functions diff --git a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c index 7ae301548a091df5de9e6023d8d2820eea93c601..aac857b9c3977c9efad80822ca28b18fc5dede4b 100644 --- a/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f74xx75xx_rcc.c @@ -746,7 +746,7 @@ static void stm32_stdclockconfig(void) regval |= STM32_RCC_CFGR_PPRE1; putreg32(regval, STM32_RCC_CFGR); -#ifdef CONFIG_RTC_HSECLOCK +#ifdef CONFIG_STM32F7_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32_RCC_CFGR); @@ -936,13 +936,13 @@ static void stm32_stdclockconfig(void) } #endif -#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_RTC_LSICLOCK) +#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_STM32F7_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); #endif -#if defined(CONFIG_RTC_LSECLOCK) +#if defined(CONFIG_STM32F7_RTC_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to diff --git a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c index d24705d5fd6ebe045e3a9198fb34a0856f888ba6..b390d422b4dc0782a6ec4db16f0899491b766968 100644 --- a/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c +++ b/arch/arm/src/stm32f7/stm32f76xx77xx_rcc.c @@ -742,7 +742,7 @@ static void stm32_stdclockconfig(void) regval |= STM32_RCC_CFGR_PPRE1; putreg32(regval, STM32_RCC_CFGR); -#ifdef CONFIG_RTC_HSECLOCK +#ifdef CONFIG_STM32F7_RTC_HSECLOCK /* Set the RTC clock divisor */ regval = getreg32(STM32_RCC_CFGR); @@ -939,13 +939,13 @@ static void stm32_stdclockconfig(void) } #endif -#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_RTC_LSICLOCK) +#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_STM32F7_RTC_LSICLOCK) /* Low speed internal clock source LSI */ stm32_rcc_enablelsi(); #endif -#if defined(CONFIG_RTC_LSECLOCK) +#if defined(CONFIG_STM32F7_RTC_LSECLOCK) /* Low speed external clock source LSE * * TODO: There is another case where the LSE needs to diff --git a/arch/arm/src/stm32l4/chip/stm32l4_can.h b/arch/arm/src/stm32l4/chip/stm32l4_can.h index 75c48cfeb8a816f2847ab4431e08b2e28569e2d9..6319282e48e722b005182e1bb73cf98378c745f8 100644 --- a/arch/arm/src/stm32l4/chip/stm32l4_can.h +++ b/arch/arm/src/stm32l4/chip/stm32l4_can.h @@ -74,6 +74,7 @@ #define STM32L4_CAN_MCR_OFFSET 0x0000 /* CAN master control register */ #define STM32L4_CAN_MSR_OFFSET 0x0004 /* CAN master status register */ #define STM32L4_CAN_TSR_OFFSET 0x0008 /* CAN transmit status register */ +#define STM32L4_CAN_RFR_OFFSET(m) (0x000c + ((m) << 2)) #define STM32L4_CAN_RF0R_OFFSET 0x000c /* CAN receive FIFO 0 register */ #define STM32L4_CAN_RF1R_OFFSET 0x0010 /* CAN receive FIFO 1 register */ #define STM32L4_CAN_IER_OFFSET 0x0014 /* CAN interrupt enable register */ @@ -82,39 +83,39 @@ /* CAN mailbox registers (3 TX and 2 RX) */ -#define STM32L4_CAN_TIR_OFFSET(m) (0x0180+((m)<<4)) +#define STM32L4_CAN_TIR_OFFSET(m) (0x0180 + ((m) << 4)) #define STM32L4_CAN_TI0R_OFFSET 0x0180 /* TX mailbox identifier register 0 */ #define STM32L4_CAN_TI1R_OFFSET 0x0190 /* TX mailbox identifier register 1 */ #define STM32L4_CAN_TI2R_OFFSET 0x01a0 /* TX mailbox identifier register 2 */ -#define STM32L4_CAN_TDTR_OFFSET(m) (0x0184+((m)<<4)) +#define STM32L4_CAN_TDTR_OFFSET(m) (0x0184 + ((m) << 4)) #define STM32L4_CAN_TDT0R_OFFSET 0x0184 /* Mailbox data length control and time stamp register 0 */ #define STM32L4_CAN_TDT1R_OFFSET 0x0194 /* Mailbox data length control and time stamp register 1 */ #define STM32L4_CAN_TDT2R_OFFSET 0x01a4 /* Mailbox data length control and time stamp register 2 */ -#define STM32L4_CAN_TDLR_OFFSET(m) (0x0188+((m)<<4)) +#define STM32L4_CAN_TDLR_OFFSET(m) (0x0188 + ((m) << 4)) #define STM32L4_CAN_TDL0R_OFFSET 0x0188 /* Mailbox data low register 0 */ #define STM32L4_CAN_TDL1R_OFFSET 0x0198 /* Mailbox data low register 1 */ #define STM32L4_CAN_TDL2R_OFFSET 0x01a8 /* Mailbox data low register 2 */ -#define STM32L4_CAN_TDHR_OFFSET(m) (0x018c+((m)<<4)) +#define STM32L4_CAN_TDHR_OFFSET(m) (0x018c + ((m) << 4)) #define STM32L4_CAN_TDH0R_OFFSET 0x018c /* Mailbox data high register 0 */ #define STM32L4_CAN_TDH1R_OFFSET 0x019c /* Mailbox data high register 1 */ #define STM32L4_CAN_TDH2R_OFFSET 0x01ac /* Mailbox data high register 2 */ -#define STM32L4_CAN_RIR_OFFSET(m) (0x01b0+((m)<<4)) +#define STM32L4_CAN_RIR_OFFSET(m) (0x01b0 + ((m) << 4)) #define STM32L4_CAN_RI0R_OFFSET 0x01b0 /* Rx FIFO mailbox identifier register 0 */ #define STM32L4_CAN_RI1R_OFFSET 0x01c0 /* Rx FIFO mailbox identifier register 1 */ -#define STM32L4_CAN_RDTR_OFFSET(m) (0x01b4+((m)<<4)) +#define STM32L4_CAN_RDTR_OFFSET(m) (0x01b4 + ((m) << 4)) #define STM32L4_CAN_RDT0R_OFFSET 0x01b4 /* Rx FIFO mailbox data length control and time stamp register 0 */ #define STM32L4_CAN_RDT1R_OFFSET 0x01c4 /* Rx FIFO mailbox data length control and time stamp register 1 */ -#define STM32L4_CAN_RDLR_OFFSET(m) (0x01b8+((m)<<4)) +#define STM32L4_CAN_RDLR_OFFSET(m) (0x01b8 + ((m) << 4)) #define STM32L4_CAN_RDL0R_OFFSET 0x01b8 /* Receive FIFO mailbox data low register 0 */ #define STM32L4_CAN_RDL1R_OFFSET 0x01c8 /* Receive FIFO mailbox data low register 1 */ -#define STM32L4_CAN_RDHR_OFFSET(m) (0x01bc+((m)<<4)) +#define STM32L4_CAN_RDHR_OFFSET(m) (0x01bc + ((m) << 4)) #define STM32L4_CAN_RDH0R_OFFSET 0x01bc /* Receive FIFO mailbox data high register 0 */ #define STM32L4_CAN_RDH1R_OFFSET 0x01cc /* Receive FIFO mailbox data high register 1 */ @@ -126,7 +127,7 @@ #define STM32L4_CAN_FFA1R_OFFSET 0x0214 /* CAN filter FIFO assignment register */ #define STM32L4_CAN_FA1R_OFFSET 0x021c /* CAN filter activation register */ -/* There are 14 or 28 filter banks (depending) on the device. Each filter bank is +/* There are 14 filter banks on the device. Each filter bank is * composed of two 32-bit registers, CAN_FiR: * F0R1 Offset 0x240 * F0R2 Offset 0x244 @@ -143,6 +144,7 @@ # define STM32L4_CAN1_MCR (STM32L4_CAN1_BASE+STM32L4_CAN_MCR_OFFSET) # define STM32L4_CAN1_MSR (STM32L4_CAN1_BASE+STM32L4_CAN_MSR_OFFSET) # define STM32L4_CAN1_TSR (STM32L4_CAN1_BASE+STM32L4_CAN_TSR_OFFSET) +# define STM32L4_CAN1_RFR(m) (STM32L4_CAN1_BASE+STM32L4_CAN_RFR_OFFSET(m)) # define STM32L4_CAN1_RF0R (STM32L4_CAN1_BASE+STM32L4_CAN_RF0R_OFFSET) # define STM32L4_CAN1_RF1R (STM32L4_CAN1_BASE+STM32L4_CAN_RF1R_OFFSET) # define STM32L4_CAN1_IER (STM32L4_CAN1_BASE+STM32L4_CAN_IER_OFFSET) @@ -302,7 +304,7 @@ #define CAN_BTR_SJW_SHIFT (24) /* Bits 25-24: Resynchronization Jump Width */ #define CAN_BTR_SJW_MASK (3 << CAN_BTR_SJW_SHIFT) #define CAN_BTR_LBKM (1 << 30) /* Bit 30: Loop Back Mode (Debug) */ -#define CAN_BTR_SILM (1 << 31) /* Bit 31: Silent Mode (Debug) */ +#define CAN_BTR_SILM (1ul << 31) /* Bit 31: Silent Mode (Debug) */ #define CAN_BTR_BRP_MAX (1024) /* Maximum BTR value (without decrement) */ #define CAN_BTR_TSEG1_MAX (16) /* Maximum TSEG1 value (without decrement) */ @@ -394,43 +396,23 @@ /* CAN filter mode register */ -#if defined(CONFIG_STM32L4_CONNECTIVITYLINE) || defined(CONFIG_STM32L4_STM32F20XX) || defined(CONFIG_STM32L4_STM32F40XX) -# define CAN_FM1R_FBM_SHIFT (0) /* Bits 13:0: Filter Mode */ -# define CAN_FM1R_FBM_MASK (0x3fff << CAN_FM1R_FBM_SHIFT) -#else -# define CAN_FM1R_FBM_SHIFT (0) /* Bits 27:0: Filter Mode */ -# define CAN_FM1R_FBM_MASK (0x0fffffff << CAN_FM1R_FBM_SHIFT) -#endif +#define CAN_FM1R_FBM_SHIFT (0) /* Bits 13:0: Filter Mode */ +#define CAN_FM1R_FBM_MASK (0x3fff << CAN_FM1R_FBM_SHIFT) /* CAN filter scale register */ -#if defined(CONFIG_STM32L4_CONNECTIVITYLINE) || defined(CONFIG_STM32L4_STM32F20XX) || defined(CONFIG_STM32L4_STM32F40XX) -# define CAN_FS1R_FSC_SHIFT (0) /* Bits 13:0: Filter Scale Configuration */ -# define CAN_FS1R_FSC_MASK (0x3fff << CAN_FS1R_FSC_SHIFT) -#else -# define CAN_FS1R_FSC_SHIFT (0) /* Bits 27:0: Filter Scale Configuration */ -# define CAN_FS1R_FSC_MASK (0x0fffffff << CAN_FS1R_FSC_SHIFT) -#endif +#define CAN_FS1R_FSC_SHIFT (0) /* Bits 13:0: Filter Scale Configuration */ +#define CAN_FS1R_FSC_MASK (0x3fff << CAN_FS1R_FSC_SHIFT) /* CAN filter FIFO assignment register */ -#if defined(CONFIG_STM32L4_CONNECTIVITYLINE) || defined(CONFIG_STM32L4_STM32F20XX) || defined(CONFIG_STM32L4_STM32F40XX) -# define CAN_FFA1R_FFA_SHIFT (0) /* Bits 13:0: Filter FIFO Assignment */ -# define CAN_FFA1R_FFA_MASK (0x3fff << CAN_FFA1R_FFA_SHIFT) -#else -# define CAN_FFA1R_FFA_SHIFT (0) /* Bits 27:0: Filter FIFO Assignment */ -# define CAN_FFA1R_FFA_MASK (0x0fffffff << CAN_FFA1R_FFA_SHIFT) -#endif +#define CAN_FFA1R_FFA_SHIFT (0) /* Bits 13:0: Filter FIFO Assignment */ +#define CAN_FFA1R_FFA_MASK (0x3fff << CAN_FFA1R_FFA_SHIFT) /* CAN filter activation register */ -#if defined(CONFIG_STM32L4_CONNECTIVITYLINE) || defined(CONFIG_STM32L4_STM32F20XX) || defined(CONFIG_STM32L4_STM32F40XX) -# define CAN_FA1R_FACT_SHIFT (0) /* Bits 13:0: Filter Active */ -# define CAN_FA1R_FACT_MASK (0x3fff << CAN_FA1R_FACT_SHIFT) -#else -# define CAN_FA1R_FACT_SHIFT (0) /* Bits 27:0: Filter Active */ -# define CAN_FA1R_FACT_MASK (0x0fffffff << CAN_FA1R_FACT_SHIFT) -#endif +#define CAN_FA1R_FACT_SHIFT (0) /* Bits 13:0: Filter Active */ +#define CAN_FA1R_FACT_MASK (0x3fff << CAN_FA1R_FACT_SHIFT) /************************************************************************************ * Public Types diff --git a/arch/arm/src/stm32l4/stm32l4_can.c b/arch/arm/src/stm32l4/stm32l4_can.c index 2d65032c3309681e2bce4e5a969f1efdcea56688..7891319e8f10927efae95e52ea50bf6542217268 100644 --- a/arch/arm/src/stm32l4/stm32l4_can.c +++ b/arch/arm/src/stm32l4/stm32l4_can.c @@ -4,6 +4,9 @@ * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * + * Copyright (C) 2016 Omni Hoverboards Inc. All rights reserved. + * Author: Paul Alexander Patience + * * Adaptations for stm32l4: * Copyright (C) 2016 Sebastien Lorquet. All rights reserved. * Author: Sebastien Lorquet @@ -92,13 +95,13 @@ struct stm32l4_can_s { - uint8_t port; /* CAN port number (1 or 2) */ - uint8_t canrx0; /* CAN RX FIFO 0 IRQ number */ - uint8_t cantx; /* CAN TX IRQ number */ - uint8_t filter; /* Filter number */ - uint32_t base; /* Base address of the CAN control registers */ - uint32_t fbase; /* Base address of the CAN filter registers */ - uint32_t baud; /* Configured baud */ + uint8_t port; /* CAN port number (1 or 2) */ + uint8_t canrx[2]; /* CAN RX FIFO 0/1 IRQ number */ + uint8_t cantx; /* CAN TX IRQ number */ + uint8_t filter; /* Filter number */ + uint32_t base; /* Base address of the CAN control registers */ + uint32_t fbase; /* Base address of the CAN filter registers */ + uint32_t baud; /* Configured baud */ }; /**************************************************************************** @@ -108,20 +111,20 @@ struct stm32l4_can_s /* CAN Register access */ static uint32_t stm32l4can_getreg(FAR struct stm32l4_can_s *priv, - int offset); + int offset); static uint32_t stm32l4can_getfreg(FAR struct stm32l4_can_s *priv, - int offset); + int offset); static void stm32l4can_putreg(FAR struct stm32l4_can_s *priv, int offset, - uint32_t value); + uint32_t value); static void stm32l4can_putfreg(FAR struct stm32l4_can_s *priv, int offset, - uint32_t value); + uint32_t value); #ifdef CONFIG_STM32L4_CAN_REGDEBUG static void stm32l4can_dumpctrlregs(FAR struct stm32l4_can_s *priv, - FAR const char *msg); + FAR const char *msg); static void stm32l4can_dumpmbregs(FAR struct stm32l4_can_s *priv, - FAR const char *msg); + FAR const char *msg); static void stm32l4can_dumpfiltregs(FAR struct stm32l4_can_s *priv, - FAR const char *msg); + FAR const char *msg); #else # define stm32l4can_dumpctrlregs(priv,msg) # define stm32l4can_dumpmbregs(priv,msg) @@ -130,14 +133,16 @@ static void stm32l4can_dumpfiltregs(FAR struct stm32l4_can_s *priv, /* Filtering (todo) */ +#ifdef CONFIG_CAN_EXTID static int stm32l4can_addextfilter(FAR struct stm32l4_can_s *priv, - FAR struct canioc_extfilter_s *arg); + FAR struct canioc_extfilter_s *arg); static int stm32l4can_delextfilter(FAR struct stm32l4_can_s *priv, - int arg); + int arg); +#endif static int stm32l4can_addstdfilter(FAR struct stm32l4_can_s *priv, - FAR struct canioc_stdfilter_s *arg); + FAR struct canioc_stdfilter_s *arg); static int stm32l4can_delstdfilter(FAR struct stm32l4_can_s *priv, - int arg); + int arg); /* CAN driver methods */ @@ -147,17 +152,19 @@ static void stm32l4can_shutdown(FAR struct can_dev_s *dev); static void stm32l4can_rxint(FAR struct can_dev_s *dev, bool enable); static void stm32l4can_txint(FAR struct can_dev_s *dev, bool enable); static int stm32l4can_ioctl(FAR struct can_dev_s *dev, int cmd, - unsigned long arg); + unsigned long arg); static int stm32l4can_remoterequest(FAR struct can_dev_s *dev, - uint16_t id); + uint16_t id); static int stm32l4can_send(FAR struct can_dev_s *dev, - FAR struct can_msg_s *msg); + FAR struct can_msg_s *msg); static bool stm32l4can_txready(FAR struct can_dev_s *dev); static bool stm32l4can_txempty(FAR struct can_dev_s *dev); /* CAN interrupt handling */ +static int stm32l4can_rxinterrupt(int irq, FAR void *context, int rxmb); static int stm32l4can_rx0interrupt(int irq, FAR void *context); +static int stm32l4can_rx1interrupt(int irq, FAR void *context); static int stm32l4can_txinterrupt(int irq, FAR void *context); /* Initialization */ @@ -190,7 +197,11 @@ static const struct can_ops_s g_canops = static struct stm32l4_can_s g_can1priv = { .port = 1, - .canrx0 = STM32L4_IRQ_CAN1RX0, + .canrx = + { + STM32L4_IRQ_CAN1RX0, + STM32L4_IRQ_CAN1RX1, + }, .cantx = STM32L4_IRQ_CAN1TX, .filter = 0, .base = STM32L4_CAN1_BASE, @@ -545,7 +556,7 @@ static void stm32l4can_reset(FAR struct can_dev_s *dev) return; } - /* Disable interrupts momentary to stop any ongoing CAN event processing + /* Disable interrupts momentarily to stop any ongoing CAN event processing * and to prevent any concurrent access to the AHB1RSTR1 register. */ @@ -584,8 +595,8 @@ static int stm32l4can_setup(FAR struct can_dev_s *dev) FAR struct stm32l4_can_s *priv = dev->cd_priv; int ret; - caninfo("CAN%d RX0 irq: %d TX irq: %d\n", - priv->port, priv->canrx0, priv->cantx); + caninfo("CAN%d RX0 irq: %d RX1 irq: %d TX irq: %d\n", + priv->port, priv->canrx[0], priv->canrx[1], priv->cantx); /* CAN cell initialization */ @@ -612,15 +623,23 @@ static int stm32l4can_setup(FAR struct can_dev_s *dev) stm32l4can_dumpfiltregs(priv, "After filter initialization"); - /* Attach the CAN RX FIFO 0 interrupt and TX interrupts. The others are - * not used. + /* Attach the CAN RX FIFO 0/1 interrupts and TX interrupts. + * The others are not used. */ - ret = irq_attach(priv->canrx0, stm32l4can_rx0interrupt); + ret = irq_attach(priv->canrx[0], stm32l4can_rx0interrupt); if (ret < 0) { canerr("ERROR: Failed to attach CAN%d RX0 IRQ (%d)", - priv->port, priv->canrx0); + priv->port, priv->canrx[0]); + return ret; + } + + ret = irq_attach(priv->canrx[1], stm32l4can_rx1interrupt); + if (ret < 0) + { + canerr("ERROR: Failed to attach CAN%d RX1 IRQ (%d)", + priv->port, priv->canrx[1]); return ret; } @@ -632,12 +651,13 @@ static int stm32l4can_setup(FAR struct can_dev_s *dev) return ret; } - /* Enable the interrupts at the NVIC. Interrupts arestill disabled in + /* Enable the interrupts at the NVIC. Interrupts are still disabled in * the CAN module. Since we coming out of reset here, there should be * no pending interrupts. */ - up_enable_irq(priv->canrx0); + up_enable_irq(priv->canrx[0]); + up_enable_irq(priv->canrx[1]); up_enable_irq(priv->cantx); return OK; } @@ -663,14 +683,16 @@ static void stm32l4can_shutdown(FAR struct can_dev_s *dev) caninfo("CAN%d\n", priv->port); - /* Disable the RX FIFO 0 and TX interrupts */ + /* Disable the RX FIFO 0/1 and TX interrupts */ - up_disable_irq(priv->canrx0); + up_disable_irq(priv->canrx[0]); + up_disable_irq(priv->canrx[1]); up_disable_irq(priv->cantx); - /* Detach the RX FIFO 0 and TX interrupts */ + /* Detach the RX FIFO 0/1 and TX interrupts */ - irq_detach(priv->canrx0); + irq_detach(priv->canrx[0]); + irq_detach(priv->canrx[1]); irq_detach(priv->cantx); /* And reset the hardware */ @@ -699,16 +721,16 @@ static void stm32l4can_rxint(FAR struct can_dev_s *dev, bool enable) caninfo("CAN%d enable: %d\n", priv->port, enable); - /* Enable/disable the FIFO 0 message pending interrupt */ + /* Enable/disable the FIFO 0/1 message pending interrupt */ regval = stm32l4can_getreg(priv, STM32L4_CAN_IER_OFFSET); if (enable) { - regval |= CAN_IER_FMPIE0; + regval |= CAN_IER_FMPIE0 | CAN_IER_FMPIE1; } else { - regval &= ~CAN_IER_FMPIE0; + regval &= ~(CAN_IER_FMPIE0 | CAN_IER_FMPIE1); } stm32l4can_putreg(priv, STM32L4_CAN_IER_OFFSET, regval); @@ -853,6 +875,7 @@ static int stm32l4can_ioctl(FAR struct can_dev_s *dev, int cmd, /* This timing is not possible */ ret = -EINVAL; + break; } /* Otherwise, nquanta is can_bit_quanta, ts1 and ts2 are @@ -866,20 +889,22 @@ static int stm32l4can_ioctl(FAR struct can_dev_s *dev, int cmd, DEBUGASSERT(brp >= 1 && brp <= CAN_BTR_BRP_MAX); } - caninfo("TS1: %d TS2: %d BRP: %d\n", bt->bt_tseg1, bt->bt_tseg2, brp); + caninfo("TS1: %d TS2: %d BRP: %d\n", + bt->bt_tseg1, bt->bt_tseg2, brp); /* Configure bit timing. */ - regval &= ~(CAN_BTR_BRP_MASK | CAN_BTR_TS1_MASK | CAN_BTR_TS2_MASK | CAN_BTR_SJW_MASK); + regval &= ~(CAN_BTR_BRP_MASK | CAN_BTR_TS1_MASK | + CAN_BTR_TS2_MASK | CAN_BTR_SJW_MASK); regval |= ((brp - 1) << CAN_BTR_BRP_SHIFT) | ((bt->bt_tseg1 - 1) << CAN_BTR_TS1_SHIFT) | ((bt->bt_tseg2 - 1) << CAN_BTR_TS2_SHIFT) | ((bt->bt_sjw - 1) << CAN_BTR_SJW_SHIFT); - + /* Bit timing can only be configured in init mode. */ ret = stm32l4can_enterinitmode(priv); - if (ret != 0) + if (ret < 0) { break; } @@ -887,10 +912,10 @@ static int stm32l4can_ioctl(FAR struct can_dev_s *dev, int cmd, stm32l4can_putreg(priv, STM32L4_CAN_BTR_OFFSET, regval); ret = stm32l4can_exitinitmode(priv); - - if (ret == 0) + if (ret >= 0) { - priv->baud = STM32L4_PCLK1_FREQUENCY / (brp * (bt->bt_tseg1 + bt->bt_tseg2 + 1)); + priv->baud = STM32L4_PCLK1_FREQUENCY / + (brp * (bt->bt_tseg1 + bt->bt_tseg2 + 1)); } } break; @@ -931,7 +956,7 @@ static int stm32l4can_ioctl(FAR struct can_dev_s *dev, int cmd, * (ERROR) is returned with the errno variable set * to indicate the nature of the error. * Dependencies: None - */ + */ case CANIOC_SET_CONNMODES: { @@ -945,26 +970,26 @@ static int stm32l4can_ioctl(FAR struct can_dev_s *dev, int cmd, if (bm->bm_loopback) { - regval |= CAN_BTR_LBKM; + regval |= CAN_BTR_LBKM; } else { - regval &= ~CAN_BTR_LBKM; + regval &= ~CAN_BTR_LBKM; } if (bm->bm_silent) { - regval |= CAN_BTR_SILM; + regval |= CAN_BTR_SILM; } else { - regval &= ~CAN_BTR_SILM; + regval &= ~CAN_BTR_SILM; } /* This register can only be configured in init mode. */ ret = stm32l4can_enterinitmode(priv); - if (ret != 0) + if (ret < 0) { break; } @@ -988,7 +1013,8 @@ static int stm32l4can_ioctl(FAR struct can_dev_s *dev, int cmd, case CANIOC_ADD_EXTFILTER: { DEBUGASSERT(arg != 0); - ret = stm32l4can_addextfilter(priv, (FAR struct canioc_extfilter_s *)arg); + ret = stm32l4can_addextfilter(priv, + (FAR struct canioc_extfilter_s *)arg); } break; @@ -1004,7 +1030,9 @@ static int stm32l4can_ioctl(FAR struct can_dev_s *dev, int cmd, case CANIOC_DEL_EXTFILTER: { +#if 0 /* Unimplemented */ DEBUGASSERT(arg <= priv->config->nextfilters); +#endif ret = stm32l4can_delextfilter(priv, (int)arg); } break; @@ -1022,7 +1050,8 @@ static int stm32l4can_ioctl(FAR struct can_dev_s *dev, int cmd, case CANIOC_ADD_STDFILTER: { DEBUGASSERT(arg != 0); - ret = stm32l4can_addstdfilter(priv, (FAR struct canioc_stdfilter_s *)arg); + ret = stm32l4can_addstdfilter(priv, + (FAR struct canioc_stdfilter_s *)arg); } break; @@ -1038,7 +1067,9 @@ static int stm32l4can_ioctl(FAR struct can_dev_s *dev, int cmd, case CANIOC_DEL_STDFILTER: { +#if 0 /* Unimplemented */ DEBUGASSERT(arg <= priv->config->nstdfilters); +#endif ret = stm32l4can_delstdfilter(priv, (int)arg); } break; @@ -1133,8 +1164,8 @@ static int stm32l4can_send(FAR struct can_dev_s *dev, /* Clear TXRQ, RTR, IDE, EXID, and STID fields */ regval = stm32l4can_getreg(priv, STM32L4_CAN_TIR_OFFSET(txmb)); - regval &= ~(CAN_TIR_TXRQ | CAN_TIR_RTR | CAN_TIR_IDE | CAN_TIR_EXID_MASK | - CAN_TIR_STID_MASK); + regval &= ~(CAN_TIR_TXRQ | CAN_TIR_RTR | CAN_TIR_IDE | + CAN_TIR_EXID_MASK | CAN_TIR_STID_MASK); stm32l4can_putreg(priv, STM32L4_CAN_TIR_OFFSET(txmb), regval); /* Set up the ID, standard 11-bit or extended 29-bit. */ @@ -1177,17 +1208,17 @@ static int stm32l4can_send(FAR struct can_dev_s *dev, if (dlc > 1) { - tmp = (uint32_t)*ptr++; + tmp = (uint32_t)*ptr++; regval |= tmp << CAN_TDLR_DATA1_SHIFT; if (dlc > 2) { - tmp = (uint32_t)*ptr++; + tmp = (uint32_t)*ptr++; regval |= tmp << CAN_TDLR_DATA2_SHIFT; if (dlc > 3) { - tmp = (uint32_t)*ptr++; + tmp = (uint32_t)*ptr++; regval |= tmp << CAN_TDLR_DATA3_SHIFT; } } @@ -1204,17 +1235,17 @@ static int stm32l4can_send(FAR struct can_dev_s *dev, if (dlc > 5) { - tmp = (uint32_t)*ptr++; + tmp = (uint32_t)*ptr++; regval |= tmp << CAN_TDHR_DATA5_SHIFT; if (dlc > 6) { - tmp = (uint32_t)*ptr++; + tmp = (uint32_t)*ptr++; regval |= tmp << CAN_TDHR_DATA6_SHIFT; if (dlc > 7) { - tmp = (uint32_t)*ptr++; + tmp = (uint32_t)*ptr++; regval |= tmp << CAN_TDHR_DATA7_SHIFT; } } @@ -1263,12 +1294,7 @@ static bool stm32l4can_txready(FAR struct can_dev_s *dev) regval = stm32l4can_getreg(priv, STM32L4_CAN_TSR_OFFSET); caninfo("CAN%d TSR: %08x\n", priv->port, regval); - if ((regval & CAN_ALL_MAILBOXES) != 0) - { - return true; - } - - return false; + return (regval & CAN_ALL_MAILBOXES) != 0; } /**************************************************************************** @@ -1299,30 +1325,26 @@ static bool stm32l4can_txempty(FAR struct can_dev_s *dev) regval = stm32l4can_getreg(priv, STM32L4_CAN_TSR_OFFSET); caninfo("CAN%d TSR: %08x\n", priv->port, regval); - if ((regval & CAN_ALL_MAILBOXES) == CAN_ALL_MAILBOXES) - { - return true; - } - - return false; + return (regval & CAN_ALL_MAILBOXES) == CAN_ALL_MAILBOXES; } /**************************************************************************** - * Name: stm32l4can_rx0interrupt + * Name: stm32l4can_rxinterrupt * * Description: - * CAN RX FIFO 0 interrupt handler + * CAN RX FIFO 0/1 interrupt handler * * Input Parameters: * irq - The IRQ number of the interrupt. * context - The register state save array at the time of the interrupt. + * rxmb - The RX mailbox number. * * Returned Value: * Zero on success; a negated errno on failure * ****************************************************************************/ -static int stm32l4can_rx0interrupt(int irq, FAR void *context) +static int stm32l4can_rxinterrupt(int irq, FAR void *context, int rxmb) { FAR struct can_dev_s *dev = NULL; FAR struct stm32l4_can_s *priv; @@ -1335,9 +1357,9 @@ static int stm32l4can_rx0interrupt(int irq, FAR void *context) dev = &g_can1dev; priv = dev->cd_priv; - /* Verify that a message is pending in FIFO 0 */ + /* Verify that a message is pending in the FIFO */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_RF0R_OFFSET); + regval = stm32l4can_getreg(priv, STM32L4_CAN_RFR_OFFSET(rxmb)); npending = (regval & CAN_RFR_FMP_MASK) >> CAN_RFR_FMP_SHIFT; if (npending < 1) { @@ -1345,11 +1367,18 @@ static int stm32l4can_rx0interrupt(int irq, FAR void *context) return OK; } - stm32l4can_dumpmbregs(priv, "RX0 interrupt"); + if (rxmb == 0) + { + stm32l4can_dumpmbregs(priv, "RX0 interrupt"); + } + else + { + stm32l4can_dumpmbregs(priv, "RX1 interrupt"); + } /* Get the CAN identifier. */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_RI0R_OFFSET); + regval = stm32l4can_getreg(priv, STM32L4_CAN_RIR_OFFSET(rxmb)); #ifdef CONFIG_CAN_EXTID if ((regval & CAN_RIR_IDE) != 0) @@ -1382,22 +1411,22 @@ static int stm32l4can_rx0interrupt(int irq, FAR void *context) /* Extract the RTR bit */ - hdr.ch_rtr = (regval & CAN_RIR_RTR) != 0 ? true : false; + hdr.ch_rtr = (regval & CAN_RIR_RTR) != 0; /* Get the DLC */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_RDT0R_OFFSET); + regval = stm32l4can_getreg(priv, STM32L4_CAN_RDTR_OFFSET(rxmb)); hdr.ch_dlc = (regval & CAN_RDTR_DLC_MASK) >> CAN_RDTR_DLC_SHIFT; /* Save the message data */ - regval = stm32l4can_getreg(priv, STM32L4_CAN_RDL0R_OFFSET); + regval = stm32l4can_getreg(priv, STM32L4_CAN_RDLR_OFFSET(rxmb)); data[0] = (regval & CAN_RDLR_DATA0_MASK) >> CAN_RDLR_DATA0_SHIFT; data[1] = (regval & CAN_RDLR_DATA1_MASK) >> CAN_RDLR_DATA1_SHIFT; data[2] = (regval & CAN_RDLR_DATA2_MASK) >> CAN_RDLR_DATA2_SHIFT; data[3] = (regval & CAN_RDLR_DATA3_MASK) >> CAN_RDLR_DATA3_SHIFT; - regval = stm32l4can_getreg(priv, STM32L4_CAN_RDH0R_OFFSET); + regval = stm32l4can_getreg(priv, STM32L4_CAN_RDHR_OFFSET(rxmb)); data[4] = (regval & CAN_RDHR_DATA4_MASK) >> CAN_RDHR_DATA4_SHIFT; data[5] = (regval & CAN_RDHR_DATA5_MASK) >> CAN_RDHR_DATA5_SHIFT; data[6] = (regval & CAN_RDHR_DATA6_MASK) >> CAN_RDHR_DATA6_SHIFT; @@ -1407,17 +1436,57 @@ static int stm32l4can_rx0interrupt(int irq, FAR void *context) ret = can_receive(dev, &hdr, data); - /* Release the FIFO0 */ + /* Release the FIFO */ #ifndef CONFIG_CAN_EXTID errout: #endif - regval = stm32l4can_getreg(priv, STM32L4_CAN_RF0R_OFFSET); + regval = stm32l4can_getreg(priv, STM32L4_CAN_RFR_OFFSET(rxmb)); regval |= CAN_RFR_RFOM; - stm32l4can_putreg(priv, STM32L4_CAN_RF0R_OFFSET, regval); + stm32l4can_putreg(priv, STM32L4_CAN_RFR_OFFSET(rxmb), regval); return ret; } +/**************************************************************************** + * Name: stm32l4can_rx0interrupt + * + * Description: + * CAN RX FIFO 0 interrupt handler + * + * Input Parameters: + * irq - The IRQ number of the interrupt. + * context - The register state save array at the time of the interrupt. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int stm32l4can_rx0interrupt(int irq, FAR void *context) +{ + return stm32l4can_rxinterrupt(irq, context, 0); +} + +/**************************************************************************** + * Name: stm32l4can_rx1interrupt + * + * Description: + * CAN RX FIFO 1 interrupt handler + * + * Input Parameters: + * irq - The IRQ number of the interrupt. + * context - The register state save array at the time of the interrupt. + * + * Returned Value: + * Zero on success; a negated errno on failure + * + ****************************************************************************/ + +static int stm32l4can_rx1interrupt(int irq, FAR void *context) +{ + return stm32l4can_rxinterrupt(irq, context, 1); +} + /**************************************************************************** * Name: stm32l4can_txinterrupt * @@ -1553,7 +1622,7 @@ static int stm32l4can_txinterrupt(int irq, FAR void *context) * Tbs1 = Tq * ts1 * Tbs2 = Tq * ts2 * Tq = brp * Tpclk1 - * baud = Fpclk1 / (brp * (1 + ts1 + ts2))) + * baud = Fpclk1 / (brp * (1 + ts1 + ts2)) * * Where: * Tpclk1 is the period of the APB1 clock (PCLK1). @@ -1606,7 +1675,6 @@ static int stm32l4can_bittiming(FAR struct stm32l4_can_s *priv) ts1 = (tmp - 1) >> 1; ts2 = tmp - ts1 - 1; - if (ts1 == ts2 && ts1 > 1 && ts2 < CAN_BTR_TSEG2_MAX) { ts1--; @@ -1700,7 +1768,7 @@ static int stm32l4can_enterinitmode(FAR struct stm32l4_can_s *priv) return -ETIMEDOUT; } - return 0; + return OK; } /**************************************************************************** @@ -1745,11 +1813,12 @@ static int stm32l4can_exitinitmode(FAR struct stm32l4_can_s *priv) if (timeout < 1) { - canerr("ERROR: Timed out waiting to exit initialization mode: %08x\n", regval); + canerr("ERROR: Timed out waiting to exit initialization mode: %08x\n", + regval); return -ETIMEDOUT; } - return 0; + return OK; } /**************************************************************************** @@ -1779,11 +1848,6 @@ static int stm32l4can_cellinit(FAR struct stm32l4_can_s *priv) regval &= ~CAN_MCR_SLEEP; stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval); - /* Configure CAN behavior. Priority driven request order, not message ID. */ - - regval |= CAN_MCR_TXFP; - stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval); - ret = stm32l4can_enterinitmode(priv); if(ret != 0) { @@ -1801,8 +1865,8 @@ static int stm32l4can_cellinit(FAR struct stm32l4_can_s *priv) */ regval = stm32l4can_getreg(priv, STM32L4_CAN_MCR_OFFSET); - regval &= ~(CAN_MCR_TXFP | CAN_MCR_RFLM | CAN_MCR_NART | CAN_MCR_AWUM | - CAN_MCR_ABOM | CAN_MCR_TTCM); + regval &= ~(CAN_MCR_TXFP | CAN_MCR_RFLM | CAN_MCR_NART | + CAN_MCR_AWUM | CAN_MCR_ABOM | CAN_MCR_TTCM); stm32l4can_putreg(priv, STM32L4_CAN_MCR_OFFSET, regval); /* Configure bit timing. */ @@ -1858,7 +1922,7 @@ static int stm32l4can_filterinit(FAR struct stm32l4_can_s *priv) /* Get the bitmask associated with the filter used by this CAN block */ - bitmask = ((uint32_t)1) << priv->filter; + bitmask = (uint32_t)1 << priv->filter; /* Enter filter initialization mode */ @@ -1878,12 +1942,12 @@ static int stm32l4can_filterinit(FAR struct stm32l4_can_s *priv) regval |= bitmask; stm32l4can_putfreg(priv, STM32L4_CAN_FS1R_OFFSET, regval); - /* There are 14 or 28 filter banks (depending) on the device. Each filter bank is - * composed of two 32-bit registers, CAN_FiR: + /* There are 14 or 28 filter banks (depending) on the device. + * Each filter bank is composed of two 32-bit registers, CAN_FiR: */ - stm32l4can_putfreg(priv, STM32L4_CAN_FIR_OFFSET(priv->filter, 1), 0); - stm32l4can_putfreg(priv, STM32L4_CAN_FIR_OFFSET(priv->filter, 2), 0); + stm32l4can_putfreg(priv, STM32L4_CAN_FIR_OFFSET(priv->filter, 1), 0); + stm32l4can_putfreg(priv, STM32L4_CAN_FIR_OFFSET(priv->filter, 2), 0); /* Set Id/Mask mode for the filter */ @@ -1928,11 +1992,13 @@ static int stm32l4can_filterinit(FAR struct stm32l4_can_s *priv) * ****************************************************************************/ -static int stm32l4can_addextfilter(FAR struct stm32l4_can_s *priv, - FAR struct canioc_extfilter_s *arg) +#ifdef CONFIG_CAN_EXTID +static int stm32l4can_addextfilter(FAR struct stm32l4_can_s *priv, + FAR struct canioc_extfilter_s *arg) { return -ENOTTY; } +#endif /**************************************************************************** * Name: stm32l4can_delextfilter @@ -1952,13 +2018,15 @@ static int stm32l4can_addextfilter(FAR struct stm32l4_can_s *priv, * ****************************************************************************/ -static int stm32l4can_delextfilter(FAR struct stm32l4_can_s *priv, int arg) +#ifdef CONFIG_CAN_EXTID +static int stm32l4can_delextfilter(FAR struct stm32l4_can_s *priv, int arg) { return -ENOTTY; } +#endif /**************************************************************************** - * Name: stm32l4can_addextfilter + * Name: stm32l4can_addstdfilter * * Description: * Add a filter for standard CAN IDs @@ -1974,8 +2042,8 @@ static int stm32l4can_delextfilter(FAR struct stm32l4_can_s *priv, int arg) * ****************************************************************************/ -static int stm32l4can_addstdfilter(FAR struct stm32l4_can_s *priv, - FAR struct canioc_stdfilter_s *arg) +static int stm32l4can_addstdfilter(FAR struct stm32l4_can_s *priv, + FAR struct canioc_stdfilter_s *arg) { return -ENOTTY; } @@ -1998,7 +2066,7 @@ static int stm32l4can_addstdfilter(FAR struct stm32l4_can_s *priv, * ****************************************************************************/ -static int stm32l4can_delstdfilter(FAR struct stm32l4_can_s *priv, int arg) +static int stm32l4can_delstdfilter(FAR struct stm32l4_can_s *priv, int arg) { return -ENOTTY; } diff --git a/arch/arm/src/stm32l4/stm32l4_can.h b/arch/arm/src/stm32l4/stm32l4_can.h index 91b96c7c9b3ff64200a0bce99f30c752384978d6..453b031bda2755bfe61701c6498075d9c7c6d1a6 100644 --- a/arch/arm/src/stm32l4/stm32l4_can.h +++ b/arch/arm/src/stm32l4/stm32l4_can.h @@ -117,7 +117,7 @@ extern "C" ************************************************************************************/ /**************************************************************************** - * Name: stm32l4_caninitialize + * Name: stm32l4can_initialize * * Description: * Initialize the selected CAN port diff --git a/arch/arm/src/stm32l4/stm32l4_irq.c b/arch/arm/src/stm32l4/stm32l4_irq.c index 4742d5c95b59eb1ab60a048d9e90d12f43d702bf..8e90bf0fa8a007b393f357c0289008d5f125bdb8 100644 --- a/arch/arm/src/stm32l4/stm32l4_irq.c +++ b/arch/arm/src/stm32l4/stm32l4_irq.c @@ -244,31 +244,23 @@ static inline void stm32l4_prioritize_syscall(int priority) static int stm32l4_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit, uintptr_t offset) { + int n; + DEBUGASSERT(irq >= STM32L4_IRQ_NMI && irq < NR_IRQS); /* Check for external interrupt */ if (irq >= STM32L4_IRQ_FIRST) { - if (irq < STM32L4_IRQ_FIRST + 32) - { - *regaddr = (NVIC_IRQ0_31_ENABLE + offset); - *bit = 1 << (irq - STM32L4_IRQ_FIRST); - } - else if (irq < STM32L4_IRQ_FIRST + 64) - { - *regaddr = (NVIC_IRQ32_63_ENABLE + offset); - *bit = 1 << (irq - STM32L4_IRQ_FIRST - 32); - } - else if (irq < NR_IRQS) - { - *regaddr = (NVIC_IRQ64_95_ENABLE + offset); - *bit = 1 << (irq - STM32L4_IRQ_FIRST - 64); - } - else + n = irq - STM32L4_IRQ_FIRST; + *regaddr = NVIC_IRQ_ENABLE(n) + offset; + + while (n >= 32) { - return ERROR; /* Invalid interrupt */ + n -= 32; } + + *bit = 1 << n; } /* Handle processor exceptions. Only a few can be disabled */ @@ -314,11 +306,14 @@ void up_irqinitialize(void) { uint32_t regaddr; int num_priority_registers; + int i; /* Disable all interrupts */ - putreg32(0, NVIC_IRQ0_31_ENABLE); - putreg32(0, NVIC_IRQ32_63_ENABLE); + for (i = 0; i < NR_IRQS - STM32L4_IRQ_FIRST; i += 32) + { + putreg32(0xffffffff, NVIC_IRQ_CLEAR(i)); + } /* Colorize the interrupt stack for debug purposes */ diff --git a/arch/arm/src/tiva/tiva_serial.c b/arch/arm/src/tiva/tiva_serial.c index e131fbd5d6bce55e723cd1cc17a45ed1c6d18913..fb80e9f3263070e6e6f87e11d1784a2591276d3b 100644 --- a/arch/arm/src/tiva/tiva_serial.c +++ b/arch/arm/src/tiva/tiva_serial.c @@ -305,13 +305,13 @@ struct up_dev_s { - uint32_t uartbase; /* Base address of UART registers */ - uint32_t baud; /* Configured baud */ - uint32_t im; /* Saved IM value */ - uint8_t irq; /* IRQ associated with this UART */ - uint8_t parity; /* 0=none, 1=odd, 2=even */ - uint8_t bits; /* Number of bits (7 or 8) */ - bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ + uint32_t uartbase; /* Base address of UART registers */ + uint32_t baud; /* Configured baud */ + uint32_t im; /* Saved IM value */ + uint8_t irq; /* IRQ associated with this UART */ + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (7 or 8) */ + bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ }; /**************************************************************************** diff --git a/arch/sim/include/.gitignore b/arch/sim/include/.gitignore index 12c22f4f28ae35faec71b131922f800ca8813bea..e6460c4a67846d5801c3600ce961277e3644f647 100644 --- a/arch/sim/include/.gitignore +++ b/arch/sim/include/.gitignore @@ -1,2 +1,3 @@ /board +/chip diff --git a/binfmt/Kconfig b/binfmt/Kconfig index fc2b457f89116608fb2886c927e7037b2ce6aca4..bd563bc0c89242b7943a695d5c88c72b321f6cc7 100644 --- a/binfmt/Kconfig +++ b/binfmt/Kconfig @@ -69,10 +69,10 @@ if BUILTIN source binfmt/libbuiltin/Kconfig endif -config PCODE +config BINFMT_PCODE bool "Support P-Code Applications" default n - depends on INTERPRETERS_PCODE && SYSTEM_PRUN && ((!BUILD_PROTECTED && !BUILD_KERNEL) || EXPERIMENTAL) + depends on INTERPRETERS_PCODE && ((!BUILD_PROTECTED && !BUILD_KERNEL) || EXPERIMENTAL) ---help--- Enable support for interpreted P-Code binaries. P-Code binaries are generated by the NuttX Pascal compiler. @@ -84,12 +84,12 @@ config PCODE Pascal package directory for more details. The correct installation directory is: apps/interpreters. - ISSUES: This feature is highly coupled with logic in the apps/subdirectory - and, as a consequence, cannot be used in environments that do not - include the standard NuttX apps/ nor in build configurations using - UILD_PROTECTED or BUILD_KERNEL.. + ISSUES: This feature is highly coupled with logic in the apps/ + directory and, as a consequence, cannot be used in environments that + do not include the standard NuttX apps/ directory nor in build + configurations using BUILD_PROTECTED or BUILD_KERNEL. -if PCODE +if BINFMT_PCODE source binfmt/libpcode/Kconfig endif diff --git a/binfmt/libpcode/Kconfig b/binfmt/libpcode/Kconfig index 046dc71c55bdc0d1c4e9527ebfda99eafb65a8e6..12bc6665c05070a992924795948b557dce3e6428 100644 --- a/binfmt/libpcode/Kconfig +++ b/binfmt/libpcode/Kconfig @@ -3,65 +3,68 @@ # see the file kconfig-language.txt in the NuttX tools repository. # -config PCODE_STACKSIZE +config BINFMT_PCODE_STACKSIZE int "P-code interpreter stack size" default 2048 ---help--- This is the stack size that will be used when starting P-code interpreter. -config PCODE_PRIORITY +config BINFMT_PCODE_PRIORITY int "P-code interpreter priority" default 100 ---help--- This is the task_priority that will be used when starting P-code interpreter. -config PCODE_VARSTACKSIZE +config BINFMT_PCODE_VARSTACKSIZE int "P-code variable stack size" default 1024 ---help--- This size of the P-Code variable storage area to be allocated by the P-Code runtime. -config PCODE_STRSTACKSIZE +config BINFMT_PCODE_STRSTACKSIZE int "P-code string stack size" default 128 ---help--- This size of the P-Code string stack area to be allocated by the P-Code runtime. -config PCODE_TEST_FS +config BINFMT_PCODE_TEST_FS bool "Mount a test file system" depends on FS_ROMFS && !DISABLE_MOUNTPOINT ---help--- - Mount a test file system. This test file system was used to verify the P-Code binary format. + Mount a test file system. This test file system was used to verify + the P-Code binary format. -if PCODE_TEST_FS +if BINFMT_PCODE_TEST_FS -config PCODE_TEST_DEVMINOR +config BINFMT_PCODE_TEST_DEVMINOR int "Test file system minor device number" default 0 ---help--- - The minor device number of the ROMFS block. For example, the N in /dev/ramN. - Used for registering the RAM block driver that will hold the ROMFS file system - containing the P-code files to be tested. Default: 0 + The minor device number of the ROMFS block. For example, the N in + /dev/ramN. Used for registering the RAM block driver that will hold + the ROMFS file system containing the P-code files to be tested. + Default: 0 -config PCODE_TEST_DEVPATH +config BINFMT_PCODE_TEST_DEVPATH string "Test file system device Path" default "/dev/ram0" ---help--- - The path to the ROMFS block driver device. This must match PCODE_TEST_DEVMINOR. - Used for registering the RAM block driver that will hold the ROMFS file system - containing the P-code files to be tested. Default: "/dev/ram0" + The path to the ROMFS block driver device. This must match + BINFMT_PCODE_TEST_DEVMINOR. Used for registering the RAM block + driver that will hold the ROMFS file system containing the P-code + files to be tested. Default: "/dev/ram0" -config PCODE_TEST_MOUNTPOINT +config BINFMT_PCODE_TEST_MOUNTPOINT string "Test file system mount point" default "/bin" ---help--- Location where the test file system will be mounted -endif # PCODE_TEST_FS +endif # BINFMT_PCODE_TEST_FS -config PCODE_DUMPBUFFER +config BINFMT_PCODE_DUMPBUFFER bool "Dump P-code buffers" default n depends on DEBUG_INFO diff --git a/binfmt/libpcode/Make.defs b/binfmt/libpcode/Make.defs index e84d0d325704125f6c6fca5c54fa269372b2e207..5b0107c39a2f507904c743a590218c97e1d0d961 100644 --- a/binfmt/libpcode/Make.defs +++ b/binfmt/libpcode/Make.defs @@ -1,7 +1,7 @@ ############################################################################ # binfmt/libpcode/Make.defs # -# Copyright (C) 2014 Gregory Nutt. All rights reserved. +# Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -33,7 +33,7 @@ # ############################################################################ -ifeq ($(CONFIG_PCODE),y) +ifeq ($(CONFIG_BINFMT_PCODE),y) # P-code application interfaces @@ -46,7 +46,15 @@ BINFMT_CSRCS += pcode.c # Add an include path so that P-Code related header files may reside in # the libpcode sub-directory -CFLAGS += ${shell $(INCDIR) $(INCDIROPT) "$(CC)" "$(TOPDIR)$(DELIM)binfmt$(DELIM)libpcode"} +CFLAGS += ${shell $(INCDIR) $(INCDIROPT) "$(CC)" \ + "$(TOPDIR)$(DELIM)binfmt$(DELIM)libpcode"} + +# FIXME: This also depends upon header files installed at +# apps/interpreters/pcode + +PCODE_DIR = $(TOPDIR)$(DELIM)$(CONFIG_APPS_DIR)$(DELIM)interpreters$(DELIM)pcode +CFLAGS += ${shell $(INCDIR) $(INCDIROPT) "$(CC)" \ + "$(PCODE_DIR)$(DELIM)include" "$(PCODE_DIR)$(DELIM)insn$(DELIM)include"} # Hook the libpcode subdirectory into the build diff --git a/binfmt/libpcode/README.txt b/binfmt/libpcode/README.txt index d6cb606af7777b5e31bb8c81ba91dcb06c891155..4e0724ee07c9f7c2d617441a90fc5860358fe0f8 100644 --- a/binfmt/libpcode/README.txt +++ b/binfmt/libpcode/README.txt @@ -14,7 +14,7 @@ Other required configuration settings: CONFIG_NFILE_DESCRIPTORS > 3 CONFIG_BINFMT_DISABLE=n - CONFIG_PCODE=y + CONFIG_BINFMT_PCODE=y Directory Contents ------------------ @@ -83,16 +83,16 @@ Here is a simple test configuration using the NuttX simulator: This enables building the PCODE binary format - CONFIG_PCODE=y - CONFIG_PCODE_PRIORITY=100 - CONFIG_PCODE_STACKSIZE=2048 + CONFIG_BINFMT_PCODE=y + CONFIG_BINFMT_PCODE_PRIORITY=100 + CONFIG_BINFMT_PCODE_STACKSIZE=2048 This enables building and mount a test filesystem: - CONFIG_PCODE_TEST_FS=y - CONFIG_PCODE_TEST_DEVMINOR=3 - CONFIG_PCODE_TEST_DEVPATH="/dev/ram3" - CONFIG_PCODE_TEST_MOUNTPOINT="/bin" + CONFIG_BINFMT_PCODE_TEST_FS=y + CONFIG_BINFMT_PCODE_TEST_DEVMINOR=3 + CONFIG_BINFMT_PCODE_TEST_DEVPATH="/dev/ram3" + CONFIG_BINFMT_PCODE_TEST_MOUNTPOINT="/bin" Debug options can also be enabled with: @@ -127,23 +127,24 @@ Here is a simple test configuration using the NuttX simulator: Issues ------ -1. As implemented now, there is a tight coupling between the nuttx/directory - and the apps/ directory. That should not be the case; the nuttx/ logic - should be completely independent of apps/ logic (but not vice versa). +1. As implemented now, there is a tight coupling between the nuttx/binfmt + directory and the apps/interpreters/pcode directory. That should not + be the case; the nuttx/ logic should be completely independent of apps/ + logic (but not vice versa). 2. The current implementation will not work in the CONFIG_BUILD_PROTECTED or CONFIG_BUILD_KERNEL configurations. That is because of the little proxy - logic (function pcode_proxy() in the file pcode.c). (a) That logic would - attempt to link with P-code logic that resides in user space. That will - not work. And (2) that proxy would be started in user mode but in the - kernel address space which will certainly crash immediately. + logic (function pcode_proxy() and prun() in the file pcode.c). (a) That + logic would attempt to link with P-code logic that resides in user space. + That will not work. And (2) that proxy would be started in user mode but + in the kernel address space which will certainly crash immediately. The general idea to fix both of these problems is as follows: 1. Eliminate the pcode_proxy. Instead start a P-Code execution program that resides in the file system. That P-Code execution program already - exists. It is in apps/system/prun. This program should be built as, - say, an ELF binary and installed in a file system. + exists. This program should be built as, say, an ELF binary and + installed in a file system. 2. Add a configuration setting that gives the full path to where the pexec program is stored in the filesystem. diff --git a/binfmt/pcode.c b/binfmt/pcode.c index 8e52b75aab37d1f75a858116232a6a0cbb6b6db2..f295e1291c2a4ed5832abb5c317eeade0a505f3c 100644 --- a/binfmt/pcode.c +++ b/binfmt/pcode.c @@ -1,7 +1,7 @@ /**************************************************************************** * binfmt/pcode.c * - * Copyright (C) 2014-2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2014-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -47,15 +47,16 @@ #include #include -#include - #include #include #include #include #include -#ifdef CONFIG_PCODE +#include "pexec.h" +#include "pedefs.h" + +#ifdef CONFIG_BINFMT_PCODE /**************************************************************************** * Pre-processor Definitions @@ -72,23 +73,19 @@ # error The binary loader is disabled (CONFIG_BINFMT_DISABLE)! #endif -#ifndef CONFIG_PCODE -# error You must select CONFIG_PCODE in your configuration file -#endif - #ifndef CONFIG_SCHED_ONEXIT # error CONFIG_SCHED_ONEXIT is required #endif -#ifndef CONFIG_PCODE_VARSTACKSIZE -# define CONFIG_PCODE_VARSTACKSIZE 1024 +#ifndef CONFIG_BINFMT_PCODE_VARSTACKSIZE +# define CONFIG_BINFMT_PCODE_VARSTACKSIZE 1024 #endif -#ifndef CONFIG_PCODE_STRSTACKSIZE -# define CONFIG_PCODE_STRSTACKSIZE 128 +#ifndef CONFIG_BINFMT_PCODE_STRSTACKSIZE +# define CONFIG_BINFMT_PCODE_STRSTACKSIZE 128 #endif -#ifdef CONFIG_PCODE_TEST_FS +#ifdef CONFIG_BINFMT_PCODE_TEST_FS # ifndef CONFIG_FS_ROMFS # error You must select CONFIG_FS_ROMFS in your configuration file # endif @@ -97,16 +94,16 @@ # error You must not disable mountpoints via CONFIG_DISABLE_MOUNTPOINT in your configuration file # endif -# ifndef CONFIG_PCODE_TEST_DEVMINOR -# define CONFIG_PCODE_TEST_DEVMINOR 0 +# ifndef CONFIG_BINFMT_PCODE_TEST_DEVMINOR +# define CONFIG_BINFMT_PCODE_TEST_DEVMINOR 0 # endif -# ifndef CONFIG_PCODE_TEST_DEVPATH -# define CONFIG_PCODE_TEST_DEVPATH "/dev/ram0" +# ifndef CONFIG_BINFMT_PCODE_TEST_DEVPATH +# define CONFIG_BINFMT_PCODE_TEST_DEVPATH "/dev/ram0" # endif -# ifndef CONFIG_PCODE_TEST_MOUNTPOINT -# define CONFIG_PCODE_TEST_MOUNTPOINT "/bin" +# ifndef CONFIG_BINFMT_PCODE_TEST_MOUNTPOINT +# define CONFIG_BINFMT_PCODE_TEST_MOUNTPOINT "/bin" # endif #endif @@ -130,6 +127,16 @@ struct binfmt_handoff_s * Private Function Prototypes ****************************************************************************/ +static int pcode_run(FAR char *exepath, size_t varsize, size_t strsize); +#ifdef CONFIG_BINFMT_PCODE_TEST_FS +static int pcode_mount_testfs(void); +#endif +#if !defined(CONFIG_BUILD_PROTECTED) && !defined(CONFIG_BUILD_KERNEL) +static void pcode_onexit(int exitcode, FAR void *arg); +#endif +#if !defined(CONFIG_BUILD_PROTECTED) && !defined(CONFIG_BUILD_KERNEL) +static int pcode_proxy(int argc, char **argv); +#endif static int pcode_load(FAR struct binary_s *binp); static int pcode_unload(FAR struct binary_s *binp); @@ -146,7 +153,7 @@ static struct binfmt_s g_pcode_binfmt = struct binfmt_handoff_s g_pcode_handoff; -#ifdef CONFIG_PCODE_TEST_FS +#ifdef CONFIG_BINFMT_PCODE_TEST_FS # include "romfs.h" #endif @@ -154,6 +161,69 @@ struct binfmt_handoff_s g_pcode_handoff; * Private Functions ****************************************************************************/ +/**************************************************************************** + * Name: pcode_run + * + * Description: + * Execute/interpret a P-Code file. This function does not return until + * the P-code program terminates or until a fatal error occurs. + * + * Input Parameters: + * exepath - The full path to the P-Code binary. + * varsize - Size of the P-Code variable stack + * strsize - the size of the P-Code string stack. + * + * Returned Value: + * OK if the P-Code program successfully terminated; A negated errno value + * is returned on the event of any failure. + * + ****************************************************************************/ + +static int pcode_run(FAR char *exepath, size_t varsize, size_t strsize) +{ + FAR struct pexec_s *st; + int errcode; + int ret = OK; + + /* Load the POFF file into memory */ + + st = pload(exepath, varsize, varsize); + if (!st) + { + berr("ERROR: Could not load %s\n", exepath); + return -ENOEXEC; + } + + binfo("Loaded %s\n", exepath); + + /* Execute the P-Code program until a stopping condition occurs */ + + for (;;) + { + /* Execute the instruction; Check for exceptional conditions */ + + errcode = pexec(st); + if (errcode != eNOERROR) + { + break; + } + } + + if (errcode != eEXIT) + { + /* REVISIT: Select a more appropriated return errocode */ + + berr("ERROR: Runtime error 0x%02x -- Execution Stopped\n", errcode); + ret = -ENOEXEC; + } + + /* Clean up resources used by the interpreter */ + + binfo("Execution terminated\n"); + pexec_release(st); + return ret; +} + /**************************************************************************** * Name: pcode_mount_testfs * @@ -162,15 +232,15 @@ struct binfmt_handoff_s g_pcode_handoff; * ****************************************************************************/ -#ifdef CONFIG_PCODE_TEST_FS +#ifdef CONFIG_BINFMT_PCODE_TEST_FS static int pcode_mount_testfs(void) { int ret; /* Create a ROM disk for the ROMFS filesystem */ - binfo("Registering romdisk at /dev/ram%d\n", CONFIG_PCODE_TEST_DEVMINOR); - ret = romdisk_register(CONFIG_PCODE_TEST_DEVMINOR, (FAR uint8_t *)romfs_img, + binfo("Registering romdisk at /dev/ram%d\n", CONFIG_BINFMT_PCODE_TEST_DEVMINOR); + ret = romdisk_register(CONFIG_BINFMT_PCODE_TEST_DEVMINOR, (FAR uint8_t *)romfs_img, NSECTORS(ROMFS_IMG_LEN), SECTORSIZE); if (ret < 0) { @@ -181,9 +251,11 @@ static int pcode_mount_testfs(void) /* Mount the test file system */ binfo("Mounting ROMFS filesystem at target=%s with source=%s\n", - CONFIG_PCODE_TEST_MOUNTPOINT, CONFIG_PCODE_TEST_DEVPATH); + CONFIG_BINFMT_PCODE_TEST_MOUNTPOINT, + CONFIG_BINFMT_PCODE_TEST_DEVPATH); - ret = mount(CONFIG_PCODE_TEST_DEVPATH, CONFIG_PCODE_TEST_MOUNTPOINT, + ret = mount(CONFIG_BINFMT_PCODE_TEST_DEVPATH, + CONFIG_BINFMT_PCODE_TEST_MOUNTPOINT, "romfs", MS_RDONLY, NULL); if (ret < 0) { @@ -191,7 +263,9 @@ static int pcode_mount_testfs(void) DEBUGASSERT(errval > 0); berr("ERROR: mount(%s,%s,romfs) failed: %d\n", - CONFIG_PCODE_TEST_DEVPATH, CONFIG_PCODE_TEST_MOUNTPOINT, errval); + CONFIG_BINFMT_PCODE_TEST_DEVPATH, + CONFIG_BINFMT_PCODE_TEST_MOUNTPOINT, errval); + return -errval; } @@ -201,7 +275,7 @@ static int pcode_mount_testfs(void) */ #if defined(CONFIG_BINFMT_EXEPATH) && !defined(CONFIG_PATH_INITIAL) - (void)setenv("PATH", CONFIG_PCODE_TEST_MOUNTPOINT, 1); + (void)setenv("PATH", CONFIG_BINFMT_PCODE_TEST_MOUNTPOINT, 1); #endif return OK; @@ -273,7 +347,8 @@ static int pcode_proxy(int argc, char **argv) /* Load the P-code file and execute it */ - ret = prun(fullpath, CONFIG_PCODE_VARSTACKSIZE, CONFIG_PCODE_STRSTACKSIZE); + ret = pcode_run(fullpath, CONFIG_BINFMT_PCODE_VARSTACKSIZE, + CONFIG_BINFMT_PCODE_STRSTACKSIZE); /* We no longer need the fullpath */ @@ -324,8 +399,8 @@ static int pcode_load(struct binary_s *binp) /* Read the POFF file header */ - for (remaining = sizeof(struct poff_fileheader_s), ptr = (FAR uint8_t *)&hdr; - remaining > 0; ) + for (remaining = sizeof(struct poff_fileheader_s), + ptr = (FAR uint8_t *)&hdr; remaining > 0; ) { /* Read the next GULP */ @@ -358,7 +433,7 @@ static int pcode_load(struct binary_s *binp) } } -#ifdef CONFIG_PCODE_DUMPBUFFER +#ifdef CONFIG_BINFMT_PCODE_DUMPBUFFER lib_dumpbuffer("POFF File Header", &hdr, sizeof(poff_fileheader_s)); #endif @@ -377,8 +452,8 @@ static int pcode_load(struct binary_s *binp) */ binp->entrypt = pcode_proxy; - binp->stacksize = CONFIG_PCODE_STACKSIZE; - binp->priority = CONFIG_PCODE_PRIORITY; + binp->stacksize = CONFIG_BINFMT_PCODE_STACKSIZE; + binp->priority = CONFIG_BINFMT_PCODE_PRIORITY; /* Get exclusive access to the p-code handoff structure */ @@ -517,14 +592,15 @@ void pcode_uninitialize(void) UNUSED(errval); } -#ifdef CONFIG_PCODE_TEST_FS - ret = umount(CONFIG_PCODE_TEST_MOUNTPOINT); +#ifdef CONFIG_BINFMT_PCODE_TEST_FS + ret = umount(CONFIG_BINFMT_PCODE_TEST_MOUNTPOINT); if (ret < 0) { int errval = get_errno(); DEBUGASSERT(errval > 0); - berr("ERROR: umount(%s) failed: %d\n", CONFIG_PCODE_TEST_MOUNTPOINT, errval); + berr("ERROR: umount(%s) failed: %d\n", + CONFIG_BINFMT_PCODE_TEST_MOUNTPOINT, errval); UNUSED(errval); } #endif @@ -534,4 +610,4 @@ void pcode_uninitialize(void) sem_destroy(&g_pcode_handoff.exclsem); } -#endif /* CONFIG_PCODE */ +#endif /* CONFIG_BINFMT_PCODE */ diff --git a/configs/Kconfig b/configs/Kconfig index c2efce0812812c382283d74946f54bbfd3353bcf..a46efb462a9c15f370bc52940f47b3c5b2da667c 100644 --- a/configs/Kconfig +++ b/configs/Kconfig @@ -201,6 +201,17 @@ config ARCH_BOARD_FIRE_STM32 and 3 of the boards are supported but only version 2 has been tested. +config ARCH_BOARD_FREEDOM_K64F + bool "NXP Freedom-k64f development board" + depends on ARCH_CHIP_MK64FN1M0VLL12 + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + development board. + This port uses the FreeScale FREEDOM-K64F development board. This + board uses the Kinetis K64 MK64FN1M0VLL12 Cortex-M4 MCU. + config ARCH_BOARD_FREEDOM_KL25Z bool "Freescale Freedom KL25Z" depends on ARCH_CHIP_MKL25Z128 @@ -518,6 +529,15 @@ config ARCH_BOARD_OLIMEX_STM32H407 toolchain* under Linux or Cygwin. See the http://www.olimex.com for further information. This board features the STMicro STM32F407ZGT6 (144pins). +config ARCH_BOARD_OLIMEX_STM32E407 + bool "Olimex STM32 E407 board" + depends on ARCH_CHIP_STM32F407ZG + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + select ARCH_HAVE_IRQBUTTONS + ---help--- + Olimex STM32 E407 board based on the STMicro STM32F407ZGT6 (144pins). + config ARCH_BOARD_OLIMEX_STM32P107 bool "Olimex STM32 P107 board" depends on ARCH_CHIP_STM32F107VC @@ -1265,25 +1285,19 @@ config ARCH_BOARD_CUSTOM endchoice -if !ARCH_BOARD_CUSTOM - -config ARCH_BOARD_CUSTOM_DIR - string - default "configs/dummy" - -config ARCH_BOARD_CUSTOM_DIR_RELPATH - bool - default y - -endif # !ARCH_BOARD_CUSTOM - if ARCH_BOARD_CUSTOM - menu "Custom Board Configuration" +config ARCH_BOARD_CUSTOM_NAME + string "Custom board name" + default "" + ---help--- + This is a name for the board. It is not used except to return the + information via the NSH uname command. + config ARCH_BOARD_CUSTOM_DIR string "Custom board directory" - default "configs/dummy" + default "" ---help--- If the custom board configuration is selected, then it is necessary to also tell the build system where it can find the board directory @@ -1300,12 +1314,6 @@ config ARCH_BOARD_CUSTOM_DIR_RELPATH ---help--- Specifies that the board directory is relative to the NuttX directory. -config ARCH_BOARD_CUSTOM_NAME - string "Custom board name" - ---help--- - This is a name for the board. It is not used except to return the - information via the NSH uname command. - config BOARD_CUSTOM_LEDS bool "Custom board LEDs" default n @@ -1355,6 +1363,7 @@ config ARCH_BOARD default "ez80f910200kitg" if ARCH_BOARD_EZ80F910200KITG default "ez80f910200zco" if ARCH_BOARD_EZ80F910200ZCO default "fire-stm32v2" if ARCH_BOARD_FIRE_STM32 + default "freedom-k64f" if ARCH_BOARD_FREEDOM_K64F default "freedom-kl25z" if ARCH_BOARD_FREEDOM_KL25Z default "freedom-kl26z" if ARCH_BOARD_FREEDOM_KL26Z default "hymini-stm32v" if ARCH_BOARD_HYMINI_STM32V @@ -1387,6 +1396,7 @@ config ARCH_BOARD default "olimex-lpc-h3131" if ARCH_BOARD_OLIMEX_LPC_H3131 default "olimex-stm32-h405" if ARCH_BOARD_OLIMEX_STM32H405 default "olimex-stm32-h407" if ARCH_BOARD_OLIMEX_STM32H407 + default "olimex-stm32-e407" if ARCH_BOARD_OLIMEX_STM32E407 default "olimex-stm32-p107" if ARCH_BOARD_OLIMEX_STM32P107 default "olimex-stm32-p207" if ARCH_BOARD_OLIMEX_STM32P207 default "olimex-strp711" if ARCH_BOARD_OLIMEX_STRP711 @@ -1555,6 +1565,9 @@ endif if ARCH_BOARD_FIRE_STM32 source "configs/fire-stm32v2/Kconfig" endif +if ARCH_BOARD_FREEDOM_K64F +source "configs/freedom-k64f/Kconfig" +endif if ARCH_BOARD_FREEDOM_KL25Z source "configs/freedom-kl25z/Kconfig" endif @@ -1654,6 +1667,9 @@ endif if ARCH_BOARD_OLIMEX_STM32H407 source "configs/olimex-stm32-h407/Kconfig" endif +if ARCH_BOARD_OLIMEX_STM32E407 +source "configs/olimex-stm32-e407/Kconfig" +endif if ARCH_BOARD_OLIMEX_STM32P107 source "configs/olimex-stm32-p107/Kconfig" endif @@ -1859,7 +1875,7 @@ if ARCH_BOARD_SIM source "configs/sim/Kconfig" endif if ARCH_BOARD_CUSTOM -source "$ARCH_BOARD_CUSTOM_DIR/Kconfig" +source "configs/dummy/Kconfig" endif config BOARD_CRASHDUMP diff --git a/configs/Makefile b/configs/Makefile index 496601da0b05f2040c0cb20213e98f1e8f6b8805..4ae15b8777ad341cb06c503321aa6b71d76e8a3f 100644 --- a/configs/Makefile +++ b/configs/Makefile @@ -35,6 +35,28 @@ -include $(TOPDIR)/Make.defs +# Determine if there is a Kconfig file for any custom board configuration + +ifeq ($(CONFIG_ARCH_BOARD_CUSTOM),y) + CUSTOM_DIR = $(patsubst "%",%,$(CONFIG_ARCH_BOARD_CUSTOM_DIR)) + ifeq ($(CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH),y) + CUSTOM_KPATH = $(TOPDIR)$(DELIM)$(CUSTOM_DIR)$(DELIM)Kconfig + else + CUSTOM_KPATH = $(CUSTOM_DIR)$(DELIM)Kconfig + endif + CUSTOM_KCONFIG = $(if $(wildcard $(CUSTOM_KPATH)),y,) +else + CUSTOM_KCONFIG = +endif + +ifeq ($(CUSTOM_KCONFIG),y) + BOARD_KCONFIG = $(CUSTOM_KPATH) +else + BOARD_KCONFIG = $(TOPDIR)$(DELIM)configs$(DELIM)dummy$(DELIM)dummy_kconfig +endif + +DUMMY_KCONFIG = $(TOPDIR)$(DELIM)configs$(DELIM)dummy$(DELIM)Kconfig + # Basic CONFIG_ASRCS = @@ -58,7 +80,7 @@ OBJS = $(AOBJS) $(COBJS) BIN = libconfigs$(LIBEXT) all: $(BIN) -.PHONY: depend clean distclean +.PHONY: depend ccontext clean_context clean distclean $(AOBJS): %$(OBJEXT): %.S $(call ASSEMBLE, $<, $@) @@ -77,7 +99,16 @@ endif depend: .depend -clean: +$(DUMMY_KCONFIG): $(BOARD_KCONFIG) + $(call DELFILE, $(DUMMY_KCONFIG)) + $(Q) cp -f $(BOARD_KCONFIG) $(DUMMY_KCONFIG) + +context: $(DUMMY_KCONFIG) + +clean_context: + $(call DELFILE, $(DUMMY_KCONFIG)) + +clean: clean_context $(call DELFILE, $(BIN)) $(call CLEAN) diff --git a/configs/README.txt b/configs/README.txt index 2e4c4aad9582d43d7eb9ec19c6383e5e67c15e81..6f30c63104c74bcb21bd242920736bd6007eaad6 100644 --- a/configs/README.txt +++ b/configs/README.txt @@ -261,6 +261,10 @@ configs/fire-stm32v2 STM32F103VET6 chip. See http://firestm32.taobao.com . Version 2 and 3 of the boards are supported but only version 2 has been tested. +configs/freedom-k64f + This port uses the FreeScale FREEDOM-K64F development board. This board + uses the Kinetis K64 MK64FN1M0VLL12 Cortex-M4 MCU. + configs/freedom-kl25z configs/freedom-kl26z These configurations are for the Freescale Freedom KL25Z and very similar @@ -438,6 +442,10 @@ configs/olimex-stm32-h407 further information. This board features the STMicro STM32F407ZGT6 (144 pins). Contributed by Neil Hancock. +configs/olimex-stm32-e407 + Olimex STM32 E407 board based on the STMicro STM32F407ZGT6 (144pins). + Contributed by Mateusz Szafoni. + configs/olimex-stm32-p107 This port uses the Olimex STM32-P107 board (STM32F107VC) and a GNU arm-nuttx-elf toolchain* under Linux or Cygwin. See the https://www.olimex.com/dev/stm32-p107.html diff --git a/configs/arduino-due/nsh/defconfig b/configs/arduino-due/nsh/defconfig index eb780c055653f1500bdfd0a9989af08638066973..f3ee262739aebd011984a52b1bee5881915c2f35 100644 --- a/configs/arduino-due/nsh/defconfig +++ b/configs/arduino-due/nsh/defconfig @@ -900,7 +900,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/arduino-mega2560/hello/defconfig b/configs/arduino-mega2560/hello/defconfig index fe1eb43cfc05fa15825eb9bd3b67d025ef5a2b72..129b81c4806373cfbd0d506365b3ebae62a56a49 100644 --- a/configs/arduino-mega2560/hello/defconfig +++ b/configs/arduino-mega2560/hello/defconfig @@ -577,7 +577,7 @@ CONFIG_EXAMPLES_HELLO=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_FSUTILS_INIFILE is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/arduino-mega2560/nsh/defconfig b/configs/arduino-mega2560/nsh/defconfig index 5c561848996a8a1fa14c649dcfbaf6cab8e9daf8..fb6c5ddeae60cabaf483df6c6b9e3a88a68ff036 100644 --- a/configs/arduino-mega2560/nsh/defconfig +++ b/configs/arduino-mega2560/nsh/defconfig @@ -668,7 +668,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_FSUTILS_INIFILE is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/c5471evm/httpd/defconfig b/configs/c5471evm/httpd/defconfig index 8407b01b8a661870b1cdfe352d3508b92fe8f8bb..e7a99b43015b66e8fe5acf6b117d5b905f2e6553 100644 --- a/configs/c5471evm/httpd/defconfig +++ b/configs/c5471evm/httpd/defconfig @@ -796,7 +796,7 @@ CONFIG_NETUTILS_HTTPD_KEEPALIVE_DISABLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/c5471evm/nettest/defconfig b/configs/c5471evm/nettest/defconfig index 386d69a57db8447488d1ad113d2c21b736673ef5..4c63b6f380916b4ae8ea25281807d0ddb71a2e1a 100644 --- a/configs/c5471evm/nettest/defconfig +++ b/configs/c5471evm/nettest/defconfig @@ -787,7 +787,7 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/c5471evm/nsh/defconfig b/configs/c5471evm/nsh/defconfig index ea349bf244811954efe7b316eeb6d8f6637f58ca..204c435266efc556bdbb3eceed454d5dea5a1f0c 100644 --- a/configs/c5471evm/nsh/defconfig +++ b/configs/c5471evm/nsh/defconfig @@ -931,7 +931,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/cc3200-launchpad/nsh/defconfig b/configs/cc3200-launchpad/nsh/defconfig index 8fbff6d4eb47d75b2017cc5fc73ff5d696340e62..ef25a4302f468ef86b7edc829dc263011fb234e4 100644 --- a/configs/cc3200-launchpad/nsh/defconfig +++ b/configs/cc3200-launchpad/nsh/defconfig @@ -875,7 +875,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/cloudctrl/nsh/defconfig b/configs/cloudctrl/nsh/defconfig index ec0165b7f392b250ea933484fe7d3ac91f7db1eb..c881714fe94cd0c2e445db8f376b4123506e9508 100644 --- a/configs/cloudctrl/nsh/defconfig +++ b/configs/cloudctrl/nsh/defconfig @@ -1411,7 +1411,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/compal_e86/nsh_highram/defconfig b/configs/compal_e86/nsh_highram/defconfig index 4e47505113045b97a0044e5ea0d4169d9d926560..f3366ba3c1e4f7b0657dda0a2d93b65a5071b7bb 100644 --- a/configs/compal_e86/nsh_highram/defconfig +++ b/configs/compal_e86/nsh_highram/defconfig @@ -797,7 +797,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/compal_e88/nsh_highram/defconfig b/configs/compal_e88/nsh_highram/defconfig index 41fd85249b1ecb10550f7391bf323d03777cb2a9..90d01e30457eb5badc915b95c4718aaa44064721 100644 --- a/configs/compal_e88/nsh_highram/defconfig +++ b/configs/compal_e88/nsh_highram/defconfig @@ -797,7 +797,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/compal_e99/nsh_compalram/defconfig b/configs/compal_e99/nsh_compalram/defconfig index d2a8f010e5d25671a71d66506675952de6174ff8..0d5d9a0ac8dba2d99cb5583c667defbdbd6a5355 100644 --- a/configs/compal_e99/nsh_compalram/defconfig +++ b/configs/compal_e99/nsh_compalram/defconfig @@ -830,7 +830,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/compal_e99/nsh_highram/defconfig b/configs/compal_e99/nsh_highram/defconfig index 778ad9d60e35b8f31489adb88911f4fa1d08a84b..c126366add2e597c4b911fb903a923c621c406d4 100644 --- a/configs/compal_e99/nsh_highram/defconfig +++ b/configs/compal_e99/nsh_highram/defconfig @@ -971,7 +971,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/dk-tm4c129x/ipv6/defconfig b/configs/dk-tm4c129x/ipv6/defconfig index b67e6e377d25ca9c860d0fe29b64c64dd152ad95..817e669b1dafb9ddb96f1b16608b76422043888e 100644 --- a/configs/dk-tm4c129x/ipv6/defconfig +++ b/configs/dk-tm4c129x/ipv6/defconfig @@ -1156,7 +1156,7 @@ CONFIG_NSH_MAX_ROUNDTRIP=20 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set CONFIG_SYSTEM_I2CTOOL=y CONFIG_I2CTOOL_MINBUS=6 diff --git a/configs/dk-tm4c129x/nsh/defconfig b/configs/dk-tm4c129x/nsh/defconfig index aa70c473d95baf9f0251f088e813f914a74f8291..0fb44482270f7a5b35b285877b2dcfbb737c64ee 100644 --- a/configs/dk-tm4c129x/nsh/defconfig +++ b/configs/dk-tm4c129x/nsh/defconfig @@ -1156,7 +1156,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set CONFIG_SYSTEM_I2CTOOL=y CONFIG_I2CTOOL_MINBUS=6 diff --git a/configs/dummy/.gitignore b/configs/dummy/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..99f41601fd87e96adf2eda287f558d1bffdf8df2 --- /dev/null +++ b/configs/dummy/.gitignore @@ -0,0 +1,2 @@ +/Kconfig + diff --git a/configs/dummy/Kconfig b/configs/dummy/dummy_kconfig similarity index 99% rename from configs/dummy/Kconfig rename to configs/dummy/dummy_kconfig index f72f3c094ce4c8f031445c514c343376e4e79e75..18c7905aed7cf0d3f1dba59f4bbeaba3c8c4af0e 100644 --- a/configs/dummy/Kconfig +++ b/configs/dummy/dummy_kconfig @@ -2,3 +2,4 @@ # For a description of the syntax of this configuration file, # see the file kconfig-language.txt in the NuttX tools repository. # + diff --git a/configs/ea3131/nsh/defconfig b/configs/ea3131/nsh/defconfig index b4536492556ae66bed6b5788868af7d05793ef7b..d53178fc423b554a718f46643824a7bc17d8e5c9 100644 --- a/configs/ea3131/nsh/defconfig +++ b/configs/ea3131/nsh/defconfig @@ -828,7 +828,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/ea3131/pgnsh/defconfig b/configs/ea3131/pgnsh/defconfig index 0be35cb7ecda25c8d3df9b1cf1e24636d7bdf601..a49bd3421f4ca7e3abfdeee1d8f19d6dc5c1aeb1 100644 --- a/configs/ea3131/pgnsh/defconfig +++ b/configs/ea3131/pgnsh/defconfig @@ -905,7 +905,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/ea3131/usbserial/defconfig b/configs/ea3131/usbserial/defconfig index 4af07a8c243e25b9f51677ac06f1e613b9d8902d..3c15c8bb079c8b60ffd8c650a48bbb3e932e7089 100644 --- a/configs/ea3131/usbserial/defconfig +++ b/configs/ea3131/usbserial/defconfig @@ -777,7 +777,7 @@ CONFIG_EXAMPLES_USBSERIAL_BUFSIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set @@ -785,6 +785,6 @@ CONFIG_EXAMPLES_USBSERIAL_BUFSIZE=512 # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set # CONFIG_SYSTEM_UBLOXMODEM is not set -# CONFIG_SYSTEM_USBMONITOR is not set +# CONFIG_USBMONITOR is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/ea3152/ostest/defconfig b/configs/ea3152/ostest/defconfig index 7c590ebf44cd98fd2777741f364cfa33ace83830..542bde2f8a96296383d1a32d88518c05eeb53766 100644 --- a/configs/ea3152/ostest/defconfig +++ b/configs/ea3152/ostest/defconfig @@ -712,7 +712,7 @@ CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/eagle100/httpd/defconfig b/configs/eagle100/httpd/defconfig index 19ed517f66dc9e2e83d0c24a85c1b453d8432aa3..9db394eac5ab555bd34f3686dcf0e84da6284a73 100644 --- a/configs/eagle100/httpd/defconfig +++ b/configs/eagle100/httpd/defconfig @@ -930,7 +930,7 @@ CONFIG_NETUTILS_HTTPD_KEEPALIVE_DISABLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/eagle100/nettest/defconfig b/configs/eagle100/nettest/defconfig index deb0cd9e48adf94061f9395410d4b36691c87b26..b19e984e0497f7351f2bf406e0440e04a584ea13 100644 --- a/configs/eagle100/nettest/defconfig +++ b/configs/eagle100/nettest/defconfig @@ -920,7 +920,7 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/eagle100/nsh/defconfig b/configs/eagle100/nsh/defconfig index f39a61f2ae8431ca398b544019366ca98cd95369..452f24ecde7bde945b08ceb9a2c6e3865169c572 100644 --- a/configs/eagle100/nsh/defconfig +++ b/configs/eagle100/nsh/defconfig @@ -1126,7 +1126,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/eagle100/nxflat/defconfig b/configs/eagle100/nxflat/defconfig index 00b4c87cf21a78ddccd8a336af74f6edaebfde6b..f328bb6c89fddc5286ea45adeb4db82f9a19ffc2 100644 --- a/configs/eagle100/nxflat/defconfig +++ b/configs/eagle100/nxflat/defconfig @@ -789,7 +789,7 @@ CONFIG_EXAMPLES_NXFLAT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/eagle100/thttpd/defconfig b/configs/eagle100/thttpd/defconfig index 191ad3376566348c55571c43caa86369fe88aab0..da9c32d88caf5ab74c8c58b1b78b16df1294bd1e 100644 --- a/configs/eagle100/thttpd/defconfig +++ b/configs/eagle100/thttpd/defconfig @@ -954,7 +954,7 @@ CONFIG_THTTPD_TILDE_MAP_NONE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/efm32-g8xx-stk/nsh/defconfig b/configs/efm32-g8xx-stk/nsh/defconfig index b641b4264ea57bd4bae149524a2cdd21b7469734..082ffa6848a15ecb2bcaed4b2c617b58745638d8 100644 --- a/configs/efm32-g8xx-stk/nsh/defconfig +++ b/configs/efm32-g8xx-stk/nsh/defconfig @@ -819,7 +819,7 @@ CONFIG_SYSTEM_CLE=y CONFIG_SYSTEM_CLE_DEBUGLEVEL=0 # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/efm32gg-stk3700/nsh/defconfig b/configs/efm32gg-stk3700/nsh/defconfig index 74c43841d3d97ea5d0c24b5820e4d9e29546d97b..79397ebf07d2852a7cdc703f4bb4f78838b2b74a 100644 --- a/configs/efm32gg-stk3700/nsh/defconfig +++ b/configs/efm32gg-stk3700/nsh/defconfig @@ -819,7 +819,7 @@ CONFIG_SYSTEM_CLE=y CONFIG_SYSTEM_CLE_DEBUGLEVEL=0 # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/ekk-lm3s9b96/nsh/defconfig b/configs/ekk-lm3s9b96/nsh/defconfig index ee98426b9e0dd131da79bf9363d1ae4ab536a5dd..4141e117c214a89db371ff717156aaeb644a6228 100644 --- a/configs/ekk-lm3s9b96/nsh/defconfig +++ b/configs/ekk-lm3s9b96/nsh/defconfig @@ -1118,7 +1118,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/ez80f910200kitg/ostest/defconfig b/configs/ez80f910200kitg/ostest/defconfig index cdd48e8e119f2736c03a38683742d2234c93d50c..555cbad837642324b948d55b7b3036457fdca7e7 100644 --- a/configs/ez80f910200kitg/ostest/defconfig +++ b/configs/ez80f910200kitg/ostest/defconfig @@ -666,7 +666,7 @@ CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_RAMTEST is not set # CONFIG_READLINE_HAVE_EXTMATCH is not set diff --git a/configs/ez80f910200zco/dhcpd/defconfig b/configs/ez80f910200zco/dhcpd/defconfig index a46d8181611f064087b4d44e67c78c85a7c83ed3..fd28494460b78d8e17c5c7958d5d1dbc7c14bb51 100644 --- a/configs/ez80f910200zco/dhcpd/defconfig +++ b/configs/ez80f910200zco/dhcpd/defconfig @@ -834,7 +834,7 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_RAMTEST is not set # CONFIG_READLINE_HAVE_EXTMATCH is not set diff --git a/configs/ez80f910200zco/httpd/defconfig b/configs/ez80f910200zco/httpd/defconfig index 1d8f5613c8836443970d6497fce4047fd5303c8d..9f7bb651456fcccf13815210a617a155f3b099dd 100644 --- a/configs/ez80f910200zco/httpd/defconfig +++ b/configs/ez80f910200zco/httpd/defconfig @@ -843,7 +843,7 @@ CONFIG_NETUTILS_HTTPD_KEEPALIVE_DISABLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_RAMTEST is not set # CONFIG_READLINE_HAVE_EXTMATCH is not set diff --git a/configs/ez80f910200zco/nettest/defconfig b/configs/ez80f910200zco/nettest/defconfig index 0975adabd05c7c4bac8076ceec021e2c323b96b3..a1f8e711fcd30363553d616c78efaf51e2148d89 100644 --- a/configs/ez80f910200zco/nettest/defconfig +++ b/configs/ez80f910200zco/nettest/defconfig @@ -833,7 +833,7 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_RAMTEST is not set # CONFIG_READLINE_HAVE_EXTMATCH is not set diff --git a/configs/ez80f910200zco/nsh/defconfig b/configs/ez80f910200zco/nsh/defconfig index 241877ecd1bc85565876d3f6fb48092204d4f1ec..92bc839c27e2a86c2be9b0291ca7559967b255b6 100644 --- a/configs/ez80f910200zco/nsh/defconfig +++ b/configs/ez80f910200zco/nsh/defconfig @@ -1007,7 +1007,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/ez80f910200zco/poll/defconfig b/configs/ez80f910200zco/poll/defconfig index f24325f5771ad97de34d67c7362db98567b8a041..f3bc5693e0fd52447d92a6975b19d8e86260291a 100644 --- a/configs/ez80f910200zco/poll/defconfig +++ b/configs/ez80f910200zco/poll/defconfig @@ -834,7 +834,7 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_RAMTEST is not set # CONFIG_READLINE_HAVE_EXTMATCH is not set diff --git a/configs/fire-stm32v2/nsh/defconfig b/configs/fire-stm32v2/nsh/defconfig index 425af3af490fe6cf99f6ac83fc17cea333f4deea..0190388cd3de5ac911d726cdb00e3f22cf829a80 100644 --- a/configs/fire-stm32v2/nsh/defconfig +++ b/configs/fire-stm32v2/nsh/defconfig @@ -1456,7 +1456,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set CONFIG_SYSTEM_I2CTOOL=y CONFIG_I2CTOOL_MINBUS=1 diff --git a/configs/freedom-k64f/Kconfig b/configs/freedom-k64f/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..7c0f1fe281dd645391910534a3fd8b942be90683 --- /dev/null +++ b/configs/freedom-k64f/Kconfig @@ -0,0 +1,7 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_FREEDOM_K64F +endif diff --git a/configs/freedom-k64f/README.txt b/configs/freedom-k64f/README.txt new file mode 100644 index 0000000000000000000000000000000000000000..9ef9660763c198e2335ab26be0670f54b848014a --- /dev/null +++ b/configs/freedom-k64f/README.txt @@ -0,0 +1,393 @@ +README.txt +========== + +This is the README file for the port of NuttX to the Freescale Freedom-K64F +develoment board. + +Contents +======== + + o Freedom K64F Features + o Serial Console + o LEDs and Buttons + o Development Environment + o GNU Toolchain Options + +Kinetis Freedom K64F Features: +============================= + + The features of the FRDM-K64F hardware are as follows: + + - MK64FN1M0VLL12 MCU (120 MHz, 1 MB flash memory, 256 KB RAM, low-power, + crystal-less USB, and 100 LQFP) + - Dual role USB interface with micro-B USB connector + - RGB LED + - FXOS8700CQ - accelerometer and magnetometer + - Two user push buttons + - Flexible power supply option - OpenSDAv2 USB, K64 USB, and external + source + - Easy access to MCU input/output through Arduino R3TM compatible I/O + connectors + - Programmable OpenSDAv2 debug circuit supporting the CMSIS-DAP Interface + software that provides: + o Mass storage device (MSD) flash programming interface + o CMSIS-DAP debug interface over a driver-less USB HID connection + providing run-control debugging and compatibility with IDE tools + o Virtual serial port interface + o Open-source CMSIS-DAP software project: github.com/mbedmicro/CMSIS-DAP. + - Ethernet + - SDHC + - Add-on RF module: nRF24L01+ Nordic 2.4GHz Radio + - Add-on Bluetooth module: JY-MCU BT board V1.05 BT + +OpenSDAv2 +========= + + The FRDM-K64F platform features OpenSDAv2, the Freescale open-source + hardware embedded serial and debug adapter running an open-source + bootloader. This circuit offers several options for serial communication, + flash programming, and run-control debugging. OpenSDAv2 is an mbed + HDK-compatible debug interface preloaded with the open-source CMSIS-DAP + Interface firmware (mbed interface) for rapid prototyping and product + development. + +Serial Console +============== + + USB VCOM Console + ---------------- + The primary serial port interface signals are PTB16 UART0_RX and PTB17 + UART0_TX. These signals are connected to the OpenSDAv2 VCOM circuit. + + Serial Shield Console + --------------------- + An alternative serial port might use a standard serial shield mounted + on the Freedom Board. In this case, Arduino pin D1 provides UART TX and + pin D0 privides UART RX. + + The I/O headers on the FRDM-K64F board are arranged to enable + compatibility with Arduino shield. The outer rows of pins (even numbered + pins) on the headers, share the same mechanical spacing and placement with + the I/O headers on the Arduino Revision 3 (R3) standard. + + The Arduino D0 and D1 pins then correspond to pins 2 and 4 on the J1 I/O + connector: + + Arduino Pin FRDM-K64F J1 Connector + ------------------------ ----------------------- + UART TX, Arduino D1 pin Pin 4, PTC17, UART3_TX + UART RX, Arduino D0 pin Pin 2, PTC16, UART3_RX + + Default Serial Console + ---------------------- + By default, these configuration are setup to use the Serial Console on + UART3. That, however, is easily reconfigured. + +LEDs and Buttons +================ + + RGB LED + ------- + An RGB LED is connected through GPIO as shown below: + + LED K64 + ------ ------------------------------------------------------- + RED PTB22/SPI2_SOUT/FB_AD29/CMP2_OUT + BLUE PTB21/SPI2_SCK/FB_AD30/CMP1_OUT + GREEN PTE26/ENET_1588_CLKIN/UART4_CTS_b/RTC_CLKOUT/USB0_CLKIN + + If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board the + Freedom KL25Z. Usage of these LEDs is defined in include/board.h and + src/k64_leds.c. The following definitions describe how NuttX controls the LEDs: + + SYMBOL Meaning LED state + RED GREEN BLUE + ------------------- ----------------------- ----------------- + LED_STARTED NuttX has been started OFF OFF OFF + LED_HEAPALLOCATE Heap has been allocated OFF OFF ON + LED_IRQSENABLED Interrupts enabled OFF OFF ON + LED_STACKCREATED Idle stack created OFF ON OFF + LED_INIRQ In an interrupt (no change) + LED_SIGNAL In a signal handler (no change) + LED_ASSERTION An assertion failed (no change) + LED_PANIC The system has crashed FLASH OFF OFF + LED_IDLE K64 is in sleep mode (Optional, not used) + + Buttons + ------- + Two push buttons, SW2 and SW3, are available on FRDM-K64F board, where + SW2 is connected to PTC6 and SW3 is connected to PTA4. Besides the + general purpose input/output functions, SW2 and SW3 can be low-power + wake up signal. Also, only SW3 can be a non-maskable interrupt. + + Switch GPIO Function + --------- --------------------------------------------------------------- + SW2 PTC6/SPI0_SOUT/PD0_EXTRG/I2S0_RX_BCLK/FB_AD9/I2S0_MCLK/LLWU_P10 + SW3 PTA4/FTM0_CH1/NMI_b/LLWU_P3 + +Development Environment +======================= + + Either Linux or Cygwin on Windows can be used for the development environment. + The source has been built only using the GNU toolchain (see below). Other + toolchains will likely cause problems. Testing was performed using the Cygwin + environment. + +GNU Toolchain Options +===================== + + The NuttX make system supports several GNU-based toolchains under Linux, + Cygwin under Windows, and Windoes native. To select a toolchain: + + 1. Use 'make menuconfig' and select the toolchain that you are using + under the System Type menu. + 2. The default toolchain is the NuttX buildroot under Linux or Cygwin: + + CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y + + If you are not using CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT, then you may + also have to modify the PATH in the setenv.h file if your make cannot + find the tools. + + NOTE: Using native Windows toolchains under Cygwin has some limitations. + This incuudes the CodeSourcery (for Windows) and devkitARM toolchains are + Windows native toolchains. The biggest limitations are: + + 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are + performed automatically in the Cygwin makefiles using the 'cygpath' utility + but you might easily find some new path problems. If so, check out 'cygpath -w' + + 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links + are used in Nuttx (e.g., include/arch). The make system works around these + problems for the Windows tools by copying directories instead of linking them. + But this can also cause some confusion for you: For example, you may edit + a file in a "linked" directory and find that your changes had no effect. + That is because you are building the copy of the file in the "fake" symbolic + directory. If you use a Windows toolchain, you should get in the habit of + making like this: + + make clean_context all + + An alias in your .bashrc file might make that less painful. + +Freedom K64F Configuration Options +================================== + + CONFIG_ARCH - Identifies the arch/ subdirectory. This sould + be set to: + + CONFIG_ARCH=arm + + CONFIG_ARCH_family - For use in C code: + + CONFIG_ARCH_ARM=y + + CONFIG_ARCH_architecture - For use in C code: + + CONFIG_ARCH_CORTEXM4=y + + CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory + + CONFIG_ARCH_CHIP=kinetis + + CONFIG_ARCH_CHIP_name - For use in C code to identify the exact + chip: + + CONFIG_ARCH_CHIP_MK64FN1M0VLL12 + + CONFIG_ARCH_BOARD - Identifies the configs subdirectory and + hence, the board that supports the particular chip or SoC. + + CONFIG_ARCH_BOARD="freedom-k64f" (for the Freedom K64F development board) + + CONFIG_ARCH_BOARD_name - For use in C code + + CONFIG_ARCH_BOARD_FREEDOM_K64F=y + + CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation + of delay loops + + CONFIG_ENDIAN_BIG - define if big endian (default is little + endian) + + CONFIG_RAM_SIZE - Describes the installed DRAM (SRAM in this case): + + CONFIG_RAM_SIZE=0x00010000 (64Kb) + + CONFIG_RAM_START - The start address of installed DRAM + + CONFIG_RAM_START=0x20000000 + + CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that + have LEDs + + CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt + stack. If defined, this symbol is the size of the interrupt + stack in bytes. If not defined, the user task stacks will be + used during interrupt handling. + + CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions + + CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture. + + CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that + cause a 100 second delay during boot-up. This 100 second delay + serves no purpose other than it allows you to calibratre + CONFIG_ARCH_LOOPSPERMSEC. You simply use a stop watch to measure + the 100 second delay then adjust CONFIG_ARCH_LOOPSPERMSEC until + the delay actually is 100 seconds. + + Individual subsystems can be enabled: + + CONFIG_KINETIS_TRACE -- Enable trace clocking on power up. + CONFIG_KINETIS_FLEXBUS -- Enable flexbus clocking on power up. + CONFIG_KINETIS_UART0 -- Support UART0 + CONFIG_KINETIS_UART1 -- Support UART1 + CONFIG_KINETIS_UART2 -- Support UART2 + CONFIG_KINETIS_UART3 -- Support UART3 + CONFIG_KINETIS_UART4 -- Support UART4 + CONFIG_KINETIS_UART5 -- Support UART5 + CONFIG_KINETIS_ENET -- Support Ethernet (K5x, K6x, and K7x only) + CONFIG_KINETIS_RNGB -- Support the random number generator(K6x only) + CONFIG_KINETIS_FLEXCAN0 -- Support FlexCAN0 + CONFIG_KINETIS_FLEXCAN1 -- Support FlexCAN1 + CONFIG_KINETIS_SPI0 -- Support SPI0 + CONFIG_KINETIS_SPI1 -- Support SPI1 + CONFIG_KINETIS_SPI2 -- Support SPI2 + CONFIG_KINETIS_I2C0 -- Support I2C0 + CONFIG_KINETIS_I2C1 -- Support I2C1 + CONFIG_KINETIS_I2S -- Support I2S + CONFIG_KINETIS_DAC0 -- Support DAC0 + CONFIG_KINETIS_DAC1 -- Support DAC1 + CONFIG_KINETIS_ADC0 -- Support ADC0 + CONFIG_KINETIS_ADC1 -- Support ADC1 + CONFIG_KINETIS_CMP -- Support CMP + CONFIG_KINETIS_VREF -- Support VREF + CONFIG_KINETIS_SDHC -- Support SD host controller + CONFIG_KINETIS_FTM0 -- Support FlexTimer 0 + CONFIG_KINETIS_FTM1 -- Support FlexTimer 1 + CONFIG_KINETIS_FTM2 -- Support FlexTimer 2 + CONFIG_KINETIS_LPTIMER -- Support the low power timer + CONFIG_KINETIS_RTC -- Support RTC + CONFIG_KINETIS_SLCD -- Support the segment LCD (K3x, K4x, and K5x only) + CONFIG_KINETIS_EWM -- Support the external watchdog + CONFIG_KINETIS_CMT -- Support Carrier Modulator Transmitter + CONFIG_KINETIS_USBOTG -- Support USB OTG (see also CONFIG_USBHOST and CONFIG_USBDEV) + CONFIG_KINETIS_USBDCD -- Support the USB Device Charger Detection module + CONFIG_KINETIS_LLWU -- Support the Low Leakage Wake-Up Unit + CONFIG_KINETIS_TSI -- Support the touch screeen interface + CONFIG_KINETIS_FTFL -- Support FLASH + CONFIG_KINETIS_DMA -- Support DMA + CONFIG_KINETIS_CRC -- Support CRC + CONFIG_KINETIS_PDB -- Support the Programmable Delay Block + CONFIG_KINETIS_PIT -- Support Programmable Interval Timers + CONFIG_ARM_MPU -- Support the MPU + + Kinetis interrupt priorities (Default is the mid priority). These should + not be set because they can cause unhandled, nested interrupts. All + interrupts need to be at the default priority in the current design. + + CONFIG_KINETIS_UART0PRIO + CONFIG_KINETIS_UART1PRIO + CONFIG_KINETIS_UART2PRIO + CONFIG_KINETIS_UART3PRIO + CONFIG_KINETIS_UART4PRIO + CONFIG_KINETIS_UART5PRIO + + CONFIG_KINETIS_EMACTMR_PRIO + CONFIG_KINETIS_EMACTX_PRIO + CONFIG_KINETIS_EMACRX_PRIO + CONFIG_KINETIS_EMACMISC_PRIO + + CONFIG_KINETIS_SDHC_PRIO + + PIN Interrupt Support + + CONFIG_GPIO_IRQ -- Enable pin interrupt support. Also needs + one or more of the following: + CONFIG_KINETIS_PORTAINTS -- Support 32 Port A interrupts + CONFIG_KINETIS_PORTBINTS -- Support 32 Port B interrupts + CONFIG_KINETIS_PORTCINTS -- Support 32 Port C interrupts + CONFIG_KINETIS_PORTDINTS -- Support 32 Port D interrupts + CONFIG_KINETIS_PORTEINTS -- Support 32 Port E interrupts + + Kinetis K64 specific device driver settings + + CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn (n=0..5) for the + console and ttys0 (default is the UART0). + CONFIG_UARTn_RXBUFSIZE - Characters are buffered as received. + This specific the size of the receive buffer + CONFIG_UARTn_TXBUFSIZE - Characters are buffered before + being sent. This specific the size of the transmit buffer + CONFIG_UARTn_BAUD - The configure BAUD of the UART. + CONFIG_UARTn_BITS - The number of bits. Must be either 8 or 8. + CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity + + Kenetis ethernet controller settings + + CONFIG_ENET_NRXBUFFERS - Number of RX buffers. The size of one + buffer is determined by CONFIG_NET_ETH_MTU. Default: 6 + CONFIG_ENET_NTXBUFFERS - Number of TX buffers. The size of one + buffer is determined by CONFIG_NET_ETH_MTU. Default: 2 + CONFIG_ENET_USEMII - Use MII mode. Default: RMII mode. + CONFIG_ENET_PHYADDR - PHY address + +Configurations +============== + +Each Freedom K64F configuration is maintained in a sub-directory and +can be selected as follow: + + cd tools + ./configure.sh freedom-k64f/ + cd - + . ./setenv.sh + +Where is one of the following: + + nsh: + --- + Configures the NuttShell (nsh) located at apps/examples/nsh using a + serial console on UART3. + + NOTES: + + 1. This configuration uses the mconf-based configuration tool. To + change this configuration using that tool, you should: + + a. Build and install the kconfig-mconf tool. See nuttx/README.txt + see additional README.txt files in the NuttX tools repository. + + b. Execute 'make menuconfig' in nuttx/ in order to start the + reconfiguration process. + + 2. Default platform/toolchain: + + CONFIG_HOST_LINUX=y : Linux (Cygwin under Windows okay too). + CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y : Buildroot (arm-nuttx-elf-gcc) + CONFIG_ARMV7M_OABI_TOOLCHAIN=y : The older OABI version + CONFIG_RAW_BINARY=y : Output formats: ELF and raw binary + + 3. The Serial Console is provided on UART3 with the correct pin + configuration for use with an Arduino Serial Shield. + + 4. An SDHC driver is has not yet been tested but can be enabled in the NSH + configuration by setting the following configuration values as follows: + + CONFIG_KINETIS_SDHC=y : Enable the SDHC driver + + CONFIG_MMCSD=y : Enable MMC/SD support + CONFIG_MMCSD_SDIO=y : Use the SDIO-based MMC/SD driver + CONFIG_MMCSD_NSLOTS=1 : One MMC/SD slot + + CONFIG_FAT=y : Eable FAT file system + CONFIG_FAT_LCNAMES=y : FAT lower case name support + CONFIG_FAT_LFN=y : FAT long file name support + CONFIG_FAT_MAXFNAME=32 : Maximum lenght of a long file name + + CONFIG_GPIO_IRQ=y : Enable GPIO interrupts + CONFIG_KINETIS_PORTEINTS=y : Enable PortE GPIO interrupts + + CONFIG_SCHED_WORKQUEUE=y : Enable the NuttX workqueue + + CONFIG_NSH_ARCHINIT=y : Provide NSH initializeation logic diff --git a/configs/freedom-k64f/include/board.h b/configs/freedom-k64f/include/board.h new file mode 100644 index 0000000000000000000000000000000000000000..92247416c36d840a558d24cea4c58ffe5819f51d --- /dev/null +++ b/configs/freedom-k64f/include/board.h @@ -0,0 +1,269 @@ +/************************************************************************************ + * configs/freedom-k64f/include/board.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIG_FREEDOM_K64F_INCLUDE_BOARD_H +#define __CONFIG_FREEDOM_K64F_INCLUDE_BOARD_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#ifndef __ASSEMBLY__ +# include +#endif + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Clocking *************************************************************************/ +/* The Freedom K64F uses a 50MHz external clock from the Micrel Ethernet PHY. The + * Kinetis MCU startup from an internal digitally-controlled oscillator (DCO). Nuttx + * will enable the main external oscillator (EXTAL0/XTAL0). The external + * oscillator/resonator can range from 32.768 KHz up to 50 MHz. The default external + * source for the MCG oscillator inputs (EXTAL) is 50 MHz clock source from Micrel + * Ethernet PHY. + */ + +#define BOARD_EXTCLOCK 1 /* External clock */ +#define BOARD_EXTAL_FREQ 50000000 /* 50MHz Oscillator from Micrel PHY */ +#define BOARD_XTAL32_FREQ 32768 /* 32KHz RTC Oscillator */ + +/* PLL Configuration. Either the external clock or crystal frequency is used to + * select the PRDIV value. Only reference clock frequencies are supported that will + * produce a 2MHz reference clock to the PLL. + * + * PLL Input frequency: PLLIN = REFCLK / PRDIV = 50 Mhz / 20 = 2.5 MHz + * PLL Output frequency: PLLOUT = PLLIN * VDIV = 2.5 Mhz * 48 = 120 MHz + * MCG Frequency: PLLOUT = 96MHz + * + * PRDIV register value is the divider minus one. So 20 -> 19 + * VDIV regiser value is offset by 24. So 28 -> 24 + */ + +#define BOARD_PRDIV 20 /* PLL External Reference Divider */ +#define BOARD_VDIV 48 /* PLL VCO Divider (frequency multiplier) */ + +#define BOARD_PLLIN_FREQ (BOARD_EXTAL_FREQ / BOARD_PRDIV) +#define BOARD_PLLOUT_FREQ (BOARD_PLLIN_FREQ * BOARD_VDIV) +#define BOARD_MCG_FREQ BOARD_PLLOUT_FREQ + +/* SIM CLKDIV1 dividers */ + +#define BOARD_OUTDIV1 1 /* Core = MCG, 120 MHz */ +#define BOARD_OUTDIV2 2 /* Bus = MCG / 2, 60 MHz */ +#define BOARD_OUTDIV3 2 /* FlexBus = MCG / 2, 60 MHz */ +#define BOARD_OUTDIV4 5 /* Flash clock = MCG / 5, 24 MHz */ + +#define BOARD_CORECLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV1) +#define BOARD_BUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV2) +#define BOARD_FLEXBUS_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV3) +#define BOARD_FLASHCLK_FREQ (BOARD_MCG_FREQ / BOARD_OUTDIV4) + +/* SDHC clocking ********************************************************************/ + +/* SDCLK configurations corresponding to various modes of operation. Formula is: + * + * SDCLK frequency = (base clock) / (prescaler * divisor) + * + * The SDHC module is always configure configured so that the core clock is the base + * clock. + */ + +/* Identification mode: 400KHz = 96MHz / ( 16 * 15) */ + +#define BOARD_SDHC_IDMODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV16 +#define BOARD_SDHC_IDMODE_DIVISOR SDHC_SYSCTL_DVS_DIV(15) + +/* MMC normal mode: 16MHz = 96MHz / (2 * 3) */ + +#define BOARD_SDHC_MMCMODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2 +#define BOARD_SDHC_MMCMODE_DIVISOR SDHC_SYSCTL_DVS_DIV(3) + +/* SD normal mode (1-bit): 16MHz = 96MHz / (2 * 3) */ + +#define BOARD_SDHC_SD1MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2 +#define BOARD_SDHC_SD1MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(3) + +/* SD normal mode (4-bit): 24MHz = 96MHz / (2 * 2) (with DMA) + * SD normal mode (4-bit): 16MHz = 96MHz / (2 * 3) (no DMA) + */ + +#ifdef CONFIG_SDIO_DMA +# define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2 +# define BOARD_SDHC_SD4MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(2) +#else +//# define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV2 +//# define BOARD_SDHC_SD4MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(3) +# define BOARD_SDHC_SD4MODE_PRESCALER SDHC_SYSCTL_SDCLKFS_DIV16 +# define BOARD_SDHC_SD4MODE_DIVISOR SDHC_SYSCTL_DVS_DIV(15) +#endif + +/* LED definitions ******************************************************************/ +/* The Freedom K64F has a single RGB LED driven by the K64F as follows: + * + * LED K64 + * ------ ------------------------------------------------------- + * RED PTB22/SPI2_SOUT/FB_AD29/CMP2_OUT + * BLUE PTB21/SPI2_SCK/FB_AD30/CMP1_OUT + * GREEN PTE26/ENET_1588_CLKIN/UART4_CTS_b/RTC_CLKOUT/USB0_CLKIN + * + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any + * way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED_R 0 +#define BOARD_LED_G 1 +#define BOARD_LED_B 2 +#define BOARD_NLEDS 3 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED_R_BIT (1 << BOARD_LED_R) +#define BOARD_LED_G_BIT (1 << BOARD_LED_G) +#define BOARD_LED_B_BIT (1 << BOARD_LED_B) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the Freedom K64F. The following definitions describe how NuttX controls + * the LEDs: + * + * SYMBOL Meaning LED state + * RED GREEN BLUE + * ------------------- ----------------------- ----------------- */ +#define LED_STARTED 1 /* NuttX has been started OFF OFF OFF */ +#define LED_HEAPALLOCATE 2 /* Heap has been allocated OFF OFF ON */ +#define LED_IRQSENABLED 0 /* Interrupts enabled OFF OFF ON */ +#define LED_STACKCREATED 3 /* Idle stack created OFF ON OFF */ +#define LED_INIRQ 0 /* In an interrupt (no change) */ +#define LED_SIGNAL 0 /* In a signal handler (no change) */ +#define LED_ASSERTION 0 /* An assertion failed (no change) */ +#define LED_PANIC 4 /* The system has crashed FLASH OFF OFF */ +#undef LED_IDLE /* K64 is in sleep mode (Not used) */ + +/* Button definitions ***************************************************************/ +/* Two push buttons, SW2 and SW3, are available on FRDM-K64F board, where SW2 is + * connected to PTC6 and SW3 is connected to PTA4. Besides the general purpose + * input/output functions, SW2 and SW3 can be low-power wake up signal. Also, only + * SW3 can be a non-maskable interrupt. + * + * Switch GPIO Function + * --------- --------------------------------------------------------------- + * SW2 PTC6/SPI0_SOUT/PD0_EXTRG/I2S0_RX_BCLK/FB_AD9/I2S0_MCLK/LLWU_P10 + * SW3 PTA4/FTM0_CH1/NMI_b/LLWU_P3 + */ + +#define BUTTON_SW2 0 +#define BUTTON_SW3 1 + +#define BUTTON_SW2_BIT (1 << BUTTON_SW2) +#define BUTTON_SW3_BIT (1 << BUTTON_SW3) + +/* Alternative pin resolution *******************************************************/ +/* If there are alternative configurations for various pins in the + * kinetis_k64pinmux.h header file, those alternative pins will be labeled with a + * suffix like _1, _2, etc. The logic in this file must select the correct pin + * configuration for the board by defining a pin configuration (with no suffix) that + * maps to the correct alternative. + */ + +/* The primary serial port interface signals are PTB16 UART0_RX and PTB17 UART0_TX. + * These signals are connected to the OpenSDAv2 circuit. + */ + +#define PIN_UART0_RX PIN_UART0_RX_3 +#define PIN_UART0_TX PIN_UART0_TX_3 + +/* An alternative serial port might use a standard serial shield mounted + * on the Freedom Board. In this case, Arduino pin D1 provides UART TX and + * pin D0 privides UART RX. + * + * The I/O headers on the FRDM-K64F board are arranged to enable + * compatibility with Arduino shield. The outer rows of pins (even numbered + * pins) on the headers, share the same mechanical spacing and placement with + * the I/O headers on the Arduino Revision 3 (R3) standard. + * + * The Arduino D0 and D1 pins then correspond to pins 2 and 4 on the J1 I/O + * connector: + * + * Arduino Pin FRDM-K64F J1 Connector + * ------------------------ ----------------------- + * UART TX, Arduino D1 pin Pin 4, PTC17, UART3_TX + * UART RX, Arduino D0 pin Pin 2, PTC16, UART3_RX + */ + +#define PIN_UART3_RX PIN_UART3_RX_2 +#define PIN_UART3_TX PIN_UART3_TX_2 + +/************************************************************************************ + * Public Data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Function Prototypes + ************************************************************************************/ + +/************************************************************************************ + * Name: kinetis_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void kinetis_boardinitialize(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIG_FREEDOM_K64F_INCLUDE_BOARD_H */ diff --git a/configs/freedom-k64f/nsh/Make.defs b/configs/freedom-k64f/nsh/Make.defs new file mode 100644 index 0000000000000000000000000000000000000000..c0f3c57b41e8bf320c58df0da0d0d4895f3cf116 --- /dev/null +++ b/configs/freedom-k64f/nsh/Make.defs @@ -0,0 +1,111 @@ +############################################################################ +# configs/freedom-k64f/nsh/Make.defs +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/flash.ld}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/flash.ld +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(CROSSDEV)ar rcs +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/configs/freedom-k64f/nsh/defconfig b/configs/freedom-k64f/nsh/defconfig new file mode 100644 index 0000000000000000000000000000000000000000..085afbde0980b38a06f0727bb3d951249f4953d2 --- /dev/null +++ b/configs/freedom-k64f/nsh/defconfig @@ -0,0 +1,901 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_DEFAULT_SMALL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +CONFIG_INTELHEX_BINARY=y +CONFIG_MOTOROLA_SREC=y +# CONFIG_RAW_BINARY is not set +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG_ALERT=y +# CONFIG_DEBUG_FEATURES is not set +CONFIG_ARCH_HAVE_STACKCHECK=y +# CONFIG_STACK_COLORATION is not set +# CONFIG_ARCH_HAVE_HEAPCHECK is not set +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ARCH_HAVE_CUSTOMOPT=y +# CONFIG_DEBUG_NOOPT is not set +# CONFIG_DEBUG_CUSTOMOPT is not set +CONFIG_DEBUG_FULLOPT=y + +# +# System Type +# +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_A1X is not set +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_EFM32 is not set +# CONFIG_ARCH_CHIP_IMX1 is not set +# CONFIG_ARCH_CHIP_IMX6 is not set +CONFIG_ARCH_CHIP_KINETIS=y +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_TIVA is not set +# CONFIG_ARCH_CHIP_LPC11XX is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +# CONFIG_ARCH_CHIP_SAMA5 is not set +# CONFIG_ARCH_CHIP_SAMD is not set +# CONFIG_ARCH_CHIP_SAML is not set +# CONFIG_ARCH_CHIP_SAM34 is not set +# CONFIG_ARCH_CHIP_SAMV7 is not set +# CONFIG_ARCH_CHIP_STM32 is not set +# CONFIG_ARCH_CHIP_STM32F7 is not set +# CONFIG_ARCH_CHIP_STM32L4 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +# CONFIG_ARCH_CHIP_TMS570 is not set +# CONFIG_ARCH_CHIP_MOXART is not set +# CONFIG_ARCH_ARM7TDMI is not set +# CONFIG_ARCH_ARM926EJS is not set +# CONFIG_ARCH_ARM920T is not set +# CONFIG_ARCH_CORTEXM0 is not set +# CONFIG_ARCH_CORTEXM3 is not set +CONFIG_ARCH_CORTEXM4=y +# CONFIG_ARCH_CORTEXM7 is not set +# CONFIG_ARCH_CORTEXA5 is not set +# CONFIG_ARCH_CORTEXA8 is not set +# CONFIG_ARCH_CORTEXA9 is not set +# CONFIG_ARCH_CORTEXR4 is not set +# CONFIG_ARCH_CORTEXR4F is not set +# CONFIG_ARCH_CORTEXR5 is not set +# CONFIG_ARCH_CORTEX5F is not set +# CONFIG_ARCH_CORTEXR7 is not set +# CONFIG_ARCH_CORTEXR7F is not set +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="kinetis" +# CONFIG_ARM_TOOLCHAIN_IAR is not set +CONFIG_ARM_TOOLCHAIN_GNU=y +# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_FPU=y +# CONFIG_ARCH_HAVE_DPFPU is not set +# CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_HAVE_TRUSTZONE is not set +CONFIG_ARM_HAVE_MPU_UNIFIED=y +# CONFIG_ARM_MPU is not set + +# +# ARMV7M Configuration Options +# +# CONFIG_ARMV7M_HAVE_ICACHE is not set +# CONFIG_ARMV7M_HAVE_DCACHE is not set +# CONFIG_ARMV7M_HAVE_ITCM is not set +# CONFIG_ARMV7M_HAVE_DTCM is not set +# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set +CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL is not set +CONFIG_ARMV7M_OABI_TOOLCHAIN=y +# CONFIG_ARMV7M_HAVE_STACKCHECK is not set +# CONFIG_ARMV7M_ITMSYSLOG is not set + +# +# Kinetis Configuration Options +# +# CONFIG_ARCH_CHIP_MK20DN32VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DX32VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DN64VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DX64VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DN128VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DX128VLH5 is not set +# CONFIG_ARCH_CHIP_MK20DX64VLH7 is not set +# CONFIG_ARCH_CHIP_MK20DX128VLH7 is not set +# CONFIG_ARCH_CHIP_MK20DX256VLH7 is not set +# CONFIG_ARCH_CHIP_MK40N512VLQ100 is not set +# CONFIG_ARCH_CHIP_MK40N512VMD100 is not set +# CONFIG_ARCH_CHIP_MK40X128VLQ100 is not set +# CONFIG_ARCH_CHIP_MK40X128VMD100 is not set +# CONFIG_ARCH_CHIP_MK40X256VLQ100 is not set +# CONFIG_ARCH_CHIP_MK40X256VMD100 is not set +# CONFIG_ARCH_CHIP_MK60N256VLQ100 is not set +# CONFIG_ARCH_CHIP_MK60N256VMD100 is not set +# CONFIG_ARCH_CHIP_MK60N512VLL100 is not set +# CONFIG_ARCH_CHIP_MK60N512VLQ100 is not set +# CONFIG_ARCH_CHIP_MK60N512VMD100 is not set +# CONFIG_ARCH_CHIP_MK60X256VLQ100 is not set +# CONFIG_ARCH_CHIP_MK60X256VMD100 is not set +CONFIG_ARCH_CHIP_MK64FN1M0VLL12=y +# CONFIG_ARCH_CHIP_MK64FX512VLL12 is not set +# CONFIG_ARCH_CHIP_MK64FX512VDC12 is not set +# CONFIG_ARCH_CHIP_MK64FN1M0VDC12 is not set +# CONFIG_ARCH_CHIP_MK64FX512VLQ12 is not set +# CONFIG_ARCH_CHIP_MK64FX512VMD12 is not set +# CONFIG_ARCH_CHIP_MK64FN1M0VMD12 is not set +# CONFIG_ARCH_FAMILY_K20 is not set +# CONFIG_ARCH_FAMILY_K40 is not set +# CONFIG_ARCH_FAMILY_K60 is not set +CONFIG_ARCH_FAMILY_K64=y + +# +# Kinetis Peripheral Support +# +# CONFIG_KINETIS_TRACE is not set +# CONFIG_KINETIS_FLEXBUS is not set +# CONFIG_KINETIS_UART0 is not set +# CONFIG_KINETIS_UART1 is not set +# CONFIG_KINETIS_UART2 is not set +CONFIG_KINETIS_UART3=y +# CONFIG_KINETIS_UART4 is not set +# CONFIG_KINETIS_UART5 is not set +# CONFIG_KINETIS_FLEXCAN0 is not set +# CONFIG_KINETIS_FLEXCAN1 is not set +# CONFIG_KINETIS_SPI0 is not set +# CONFIG_KINETIS_SPI1 is not set +# CONFIG_KINETIS_SPI2 is not set +# CONFIG_KINETIS_I2C0 is not set +# CONFIG_KINETIS_I2C1 is not set +# CONFIG_KINETIS_I2S is not set +# CONFIG_KINETIS_DAC0 is not set +# CONFIG_KINETIS_DAC1 is not set +# CONFIG_KINETIS_ADC0 is not set +# CONFIG_KINETIS_ADC1 is not set +# CONFIG_KINETIS_CMP is not set +# CONFIG_KINETIS_VREF is not set +# CONFIG_KINETIS_SDHC is not set +# CONFIG_KINETIS_FTM0 is not set +# CONFIG_KINETIS_FTM1 is not set +# CONFIG_KINETIS_FTM2 is not set +# CONFIG_KINETIS_LPTIMER is not set +# CONFIG_KINETIS_RTC is not set +# CONFIG_KINETIS_EWM is not set +# CONFIG_KINETIS_CMT is not set +# CONFIG_KINETIS_USBOTG is not set +# CONFIG_KINETIS_USBDCD is not set +# CONFIG_KINETIS_LLWU is not set +# CONFIG_KINETIS_TSI is not set +# CONFIG_KINETIS_FTFL is not set +# CONFIG_KINETIS_DMA is not set +# CONFIG_KINETIS_CRC is not set +# CONFIG_KINETIS_PDB is not set +# CONFIG_KINETIS_PIT is not set + +# +# Kinetis GPIO Interrupt Configuration +# +# CONFIG_GPIO_IRQ is not set + +# +# Kinetis UART Configuration +# + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_HAVE_IRQPRIO=y +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +CONFIG_ARCH_HAVE_VFORK=y +# CONFIG_ARCH_HAVE_MMU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +CONFIG_ARCH_HAVE_RESET=y +# CONFIG_ARCH_USE_MPU is not set +# CONFIG_ARCH_IRQPRIO is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +CONFIG_ARCH_HAVE_RAMFUNCS=y +CONFIG_ARCH_RAMFUNCS=y +CONFIG_ARCH_HAVE_RAMVECTORS=y +# CONFIG_ARCH_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=9535 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 +CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y +# CONFIG_ARCH_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x1fff0000 +CONFIG_RAM_SIZE=131072 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +CONFIG_ARCH_BOARD_FREEDOM_K64F=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="freedom-k64f" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +# CONFIG_ARCH_BUTTONS is not set +CONFIG_ARCH_HAVE_IRQBUTTONS=y + +# +# Board-Specific Options +# +# CONFIG_BOARD_CRASHDUMP is not set +# CONFIG_LIB_BOARDCTL is not set + +# +# RTOS Features +# +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_ENVIRON is not set + +# +# Clocks and Timers +# +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2013 +CONFIG_START_MONTH=3 +CONFIG_START_DAY=25 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=4 +CONFIG_WDOG_INTRESERVE=0 +CONFIG_PREALLOC_TIMERS=4 + +# +# Tasks and Scheduling +# +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=0 +CONFIG_MAX_TASKS=16 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y + +# +# Pthread Options +# +# CONFIG_MUTEX_TYPES is not set +CONFIG_NPTHREAD_KEYS=4 + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +CONFIG_DEV_CONSOLE=y +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 + +# +# POSIX Message Queue Options +# +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +# CONFIG_MODULE is not set + +# +# Work queue support +# +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_HPWORK is not set +# CONFIG_SCHED_LPWORK is not set + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +CONFIG_DISABLE_POLL=y +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +# CONFIG_ARCH_HAVE_I2CRESET is not set +# CONFIG_I2C is not set +# CONFIG_SPI is not set +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +# CONFIG_USERLED is not set +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set +# CONFIG_MMCSD is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +# CONFIG_DEV_LOWCONSOLE is not set +# CONFIG_SERIAL_REMOVABLE is not set +CONFIG_SERIAL_CONSOLE=y +# CONFIG_16550_UART is not set +# CONFIG_UART_SERIALDRIVER is not set +# CONFIG_UART0_SERIALDRIVER is not set +# CONFIG_UART1_SERIALDRIVER is not set +# CONFIG_UART2_SERIALDRIVER is not set +CONFIG_UART3_SERIALDRIVER=y +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +# CONFIG_USART1_SERIALDRIVER is not set +# CONFIG_USART2_SERIALDRIVER is not set +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +# CONFIG_ARCH_HAVE_SERIAL_TERMIOS is not set +CONFIG_UART3_SERIAL_CONSOLE=y +# CONFIG_OTHER_SERIAL_CONSOLE is not set +# CONFIG_NO_SERIAL_CONSOLE is not set + +# +# UART3 Configuration +# +CONFIG_UART3_RXBUFSIZE=256 +CONFIG_UART3_TXBUFSIZE=256 +CONFIG_UART3_BAUD=115200 +CONFIG_UART3_BITS=8 +CONFIG_UART3_PARITY=0 +CONFIG_UART3_2STOP=0 +# CONFIG_UART3_IFLOWCONTROL is not set +# CONFIG_UART3_OFLOWCONTROL is not set +# CONFIG_UART3_DMA is not set +# CONFIG_USBDEV is not set +# CONFIG_USBHOST is not set +# CONFIG_HAVE_USBTRACE is not set +# CONFIG_DRIVERS_WIRELESS is not set + +# +# System Logging +# +# CONFIG_ARCH_SYSLOG is not set +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +CONFIG_SYSLOG_SERIAL_CONSOLE=y +# CONFIG_SYSLOG_CHAR is not set +CONFIG_SYSLOG_CONSOLE=y +# CONFIG_SYSLOG_NONE is not set +# CONFIG_SYSLOG_FILE is not set + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_AUTOMOUNTER is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +CONFIG_FS_READABLE=y +CONFIG_FS_WRITABLE=y +# CONFIG_FS_NAMED_SEMAPHORES is not set +CONFIG_FS_MQUEUE_MPATH="/var/mqueue" +# CONFIG_FS_RAMMAP is not set +CONFIG_FS_FAT=y +# CONFIG_FAT_LCNAMES is not set +# CONFIG_FAT_LFN is not set +# CONFIG_FS_FATTIME is not set +# CONFIG_FAT_FORCE_INDIRECT is not set +# CONFIG_FAT_DMAMEMORY is not set +# CONFIG_FAT_DIRECT_RETRY is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_PROCFS is not set +# CONFIG_FS_UNIONFS is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=1 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +# CONFIG_BUILTIN is not set +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +CONFIG_LIBC_LONG_LONG=y +# CONFIG_LIBC_IOCTL_VARIADIC is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_LIBC_TMPDIR="/tmp" +CONFIG_LIBC_MAX_TMPFILE=32 +CONFIG_ARCH_LOWPUTC=y +# CONFIG_LIBC_LOCALTIME is not set +# CONFIG_TIME_EXTENDED is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +CONFIG_ARCH_HAVE_TLS=y +# CONFIG_TLS is not set +# CONFIG_LIBC_NETDB is not set +# CONFIG_NETDB_HOSTFILE is not set + +# +# Non-standard Library Support +# +# CONFIG_LIB_CRC64_FAST is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +# CONFIG_HAVE_CXX is not set + +# +# Application Configuration +# + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_CPUHOG is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FSTEST is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +# CONFIG_EXAMPLES_HELLO is not set +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +CONFIG_EXAMPLES_NSH=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_POLL is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set +# CONFIG_FSUTILS_PASSWD is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_BAS is not set +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_SMTP is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set + +# +# Command Line Configuration +# +CONFIG_NSH_READLINE=y +# CONFIG_NSH_CLE is not set +CONFIG_NSH_LINELEN=64 +# CONFIG_NSH_DISABLE_SEMICOLON is not set +CONFIG_NSH_CMDPARMS=y +CONFIG_NSH_MAXARGUMENTS=6 +CONFIG_NSH_ARGCAT=y +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLEBG is not set + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_ADDROUTE is not set +# CONFIG_NSH_DISABLE_BASENAME is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_CMP is not set +CONFIG_NSH_DISABLE_DATE=y +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_DELROUTE is not set +# CONFIG_NSH_DISABLE_DIRNAME is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +CONFIG_NSH_DISABLE_IFUPDOWN=y +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +CONFIG_NSH_DISABLE_LOSMART=y +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKFATFS is not set +# CONFIG_NSH_DISABLE_MKFIFO is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MV is not set +# CONFIG_NSH_DISABLE_MW is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PSSTACKUSAGE is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TIME is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 + +# +# Configure Command Options +# +CONFIG_NSH_CMDOPT_DF_H=y +CONFIG_NSH_CODECS_BUFSIZE=128 +CONFIG_NSH_CMDOPT_HEXDUMP=y +CONFIG_NSH_FILEIOSIZE=512 + +# +# Scripting Support +# +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_ALTCONDEV is not set +# CONFIG_NSH_ARCHINIT is not set +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_RAMTEST is not set +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +# CONFIG_READLINE_TABCOMPLETION is not set +# CONFIG_READLINE_CMD_HISTORY is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm32f746g-disco/netnsh/setenv.sh b/configs/freedom-k64f/nsh/setenv.sh old mode 100755 new mode 100644 similarity index 92% rename from configs/stm32f746g-disco/netnsh/setenv.sh rename to configs/freedom-k64f/nsh/setenv.sh index 427dcdd32c0f8dc93392bc4aabadbfeb964cca8e..45d7f9dd1182528ab4c9f50a1d0a4e7efc3ce20c --- a/configs/stm32f746g-disco/netnsh/setenv.sh +++ b/configs/freedom-k64f/nsh/setenv.sh @@ -1,7 +1,7 @@ #!/bin/bash -# configs/stm32f746g-disco/netnsh/setenv.sh +# configs/freedom-k64f/nsh/setenv.sh # -# Copyright (C) 2015 Gregory Nutt. All rights reserved. +# Copyright (C) 2016 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -61,7 +61,7 @@ fi # This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors" # You can this free toolchain here https://launchpad.net/gcc-arm-embedded -export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin" +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin" # This is the path to the location where I installed the devkitARM toolchain # You can get this free toolchain from http://devkitpro.org/ or http://sourceforge.net/projects/devkitpro/ @@ -69,7 +69,7 @@ export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 # This is the Cygwin path to the location where I build the buildroot # toolchain. -# export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" +export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" # Add the path to the toolchain to the PATH varialble export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" diff --git a/configs/freedom-k64f/scripts/flash.ld b/configs/freedom-k64f/scripts/flash.ld new file mode 100644 index 0000000000000000000000000000000000000000..f60e7d330e01fdcb98d2dea09a02fd72e3164bd4 --- /dev/null +++ b/configs/freedom-k64f/scripts/flash.ld @@ -0,0 +1,142 @@ +/**************************************************************************** + * configs/freedom-k64f/scripts/flash.ld + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The MK64FN1M0VLL12 has 1M of FLASH beginning at address 0x0000:0000 and + * 128Kb of SRAM beginning at address 0x1800:0000 (SRAM_L) and 0x2000:000 + * (SRAM_U). + * + * NOTE: that the first part of the K64 FLASH region is reserved for + * interrupt vectflash and, following that, is a region from 0x0000:0400 + * to 0x0000:040f that is reserved for the FLASH control fields (FCF). + * + * NOTE: The on-chip RAM is split evenly among SRAM_L and SRAM_U. The RAM is + * also implemented such that the SRAM_L and SRAM_U ranges form a + * contiguous block in the memory map. + */ + +MEMORY +{ + vectflash (rx) : ORIGIN = 0x00000000, LENGTH = 1K + cfmprotect (rx) : ORIGIN = 0x00000400, LENGTH = 16 + progflash (rx) : ORIGIN = 0x00000800, LENGTH = 1M + datasram (rwx) : ORIGIN = 0x1fff0000, LENGTH = 128K +} + +OUTPUT_ARCH(arm) +ENTRY(_stext) +EXTERN(__flashconfigbytes) +SECTIONS +{ + .vectors : { + _svectors = ABSOLUTE(.); + *(.vectors) + _evectors = ABSOLUTE(.); + } > vectflash + + .cfmprotect : { + KEEP(*(.cfmconfig)) + } > cfmprotect + + .text : { + _stext = ABSOLUTE(.); + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > progflash + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > progflash + + .ARM.extab : { + *(.ARM.extab*) + } > progflash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > progflash + __exidx_end = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > datasram AT > progflash + + _eronly = LOADADDR(.data); + + .ramfunc ALIGN(4): { + _sramfuncs = ABSOLUTE(.); + *(.ramfunc .ramfunc.*) + _eramfuncs = ABSOLUTE(.); + } > datasram AT > progflash + + _framfuncs = LOADADDR(.ramfunc); + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > datasram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/freedom-k64f/src/Makefile b/configs/freedom-k64f/src/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..65cba8c536cd5222fe1b0712eecbc32311695fd1 --- /dev/null +++ b/configs/freedom-k64f/src/Makefile @@ -0,0 +1,65 @@ +############################################################################ +# configs/freedom-k64f/src/Makefile +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = k64_boot.c k64_spi.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += k64_autoleds.c +else +CSRCS += k64_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += k64_buttons.c +endif + +ifeq ($(CONFIG_LIB_BOARDCTL),y) +CSRCS += k64_appinit.c k64_bringup.c +else ifeq ($(CONFIG_BOARD_INITIALIZE),y) +CSRCS += k64_bringup.c +endif + +ifeq ($(CONFIG_USBDEV),y) +CSRCS += k64_usbdev.c +endif + +ifeq ($(CONFIG_USBMSC),y) +CSRCS += k64_usbmsc.c +endif + +include $(TOPDIR)/configs/Board.mk diff --git a/configs/freedom-k64f/src/freedom-k64f.h b/configs/freedom-k64f/src/freedom-k64f.h new file mode 100644 index 0000000000000000000000000000000000000000..53a6e000e9efa50385e82ae6103604e5668ef6bf --- /dev/null +++ b/configs/freedom-k64f/src/freedom-k64f.h @@ -0,0 +1,145 @@ +/************************************************************************************ + * configs/freedom-k64f/src/freedom-k64f.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIGS_FREEDOM_K64F_SRC_FREEDOM_K64F_H +#define __CONFIGS_FREEDOM_K64F_SRC_FREEDOM_K64F_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include +#include +#include + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* How many SPI modules does this chip support? The LM3S6918 supports 2 SPI + * modules (others may support more -- in such case, the following must be + * expanded). + */ + +#if KINETIS_NSPI < 1 +# undef CONFIG_KINETIS_SPI1 +# undef CONFIG_KINETIS_SPI2 +#elif KINETIS_NSPI < 2 +# undef CONFIG_KINETIS_SPI2 +#endif + +/* FREEDOM-K64F GPIOs ****************************************************************/ +/* A micro Secure Digital (SD) card slot is available on the FRDM-K64F connected to + * the SD Host Controller (SDHC) signals of the MCU. This slot will accept micro + * format SD memory cards. The SD card detect pin (PTE6) is an open switch that + * shorts with VDD when card is inserted. + * + * There is no Write Protect pin available to the K64F. + */ + +#define GPIO_SD_CARDDETECT (GPIO_PULLUP | PIN_INT_BOTH | PIN_PORTE | PIN6) + +/* Two push buttons, SW2 and SW3, are available on FRDM-K64F board, where SW2 is + * connected to PTC6 and SW3 is connected to PTA4. Besides the general purpose + * input/output functions, SW2 and SW3 can be low-power wake up signal. Also, only + * SW3 can be a non-maskable interrupt. + * + * Switch GPIO Function + * --------- --------------------------------------------------------------- + * SW2 PTC6/SPI0_SOUT/PD0_EXTRG/I2S0_RX_BCLK/FB_AD9/I2S0_MCLK/LLWU_P10 + * SW3 PTA4/FTM0_CH1/NMI_b/LLWU_P3 + */ + +#define GPIO_SW2 (GPIO_PULLUP | PIN_INT_BOTH | PIN_PORTC | PIN6) +#define GPIO_SW3 (GPIO_PULLUP | PIN_INT_BOTH | PIN_PORTA | PIN4) + +/* An RGB LED is connected through GPIO as shown below: + * + * LED K64 + * ------ ------------------------------------------------------- + * RED PTB22/SPI2_SOUT/FB_AD29/CMP2_OUT + * BLUE PTB21/SPI2_SCK/FB_AD30/CMP1_OUT + * GREEN PTE26/ENET_1588_CLKIN/UART4_CTS_b/RTC_CLKOUT/USB0_CLKIN + */ + +#define GPIO_LED_R (GPIO_LOWDRIVE | GPIO_OUTPUT_ONE | PIN_PORTB | PIN22) +#define GPIO_LED_G (GPIO_LOWDRIVE | GPIO_OUTPUT_ONE | PIN_PORTB | PIN21) +#define GPIO_LED_B (GPIO_LOWDRIVE | GPIO_OUTPUT_ONE | PIN_PORTE | PIN26) + +/************************************************************************************ + * Public data + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: k64_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the FREEDOM-K64F board. + * + ************************************************************************************/ + +void weak_function k64_spidev_initialize(void); + +/************************************************************************************ + * Name: k64_usbinitialize + * + * Description: + * Called to setup USB-related GPIO pins for the FREEDOM-K64F board. + * + ************************************************************************************/ + +void weak_function k64_usbinitialize(void); + +/************************************************************************************ + * Name: k64_bringup + * + * Description: + * Bring up board features + * + ************************************************************************************/ + +#if defined(CONFIG_LIB_BOARDCTL) || defined(CONFIG_BOARD_INITIALIZE) +int k64_bringup(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_FREEDOM_K64F_SRC_FREEDOM_K64F_H */ diff --git a/configs/freedom-k64f/src/k64_appinit.c b/configs/freedom-k64f/src/k64_appinit.c new file mode 100644 index 0000000000000000000000000000000000000000..ba19f5b851d33543824283f7b328315f627c8a52 --- /dev/null +++ b/configs/freedom-k64f/src/k64_appinit.c @@ -0,0 +1,90 @@ +/**************************************************************************** + * config/freedom-k64f/src/k64_appinit.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include + +#include "freedom-k64f.h" + +#ifdef CONFIG_LIB_BOARDCTL + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform application specific initialization. This function is never + * called directly from application code, but only indirectly via the + * (non-standard) boardctl() interface using the command BOARDIOC_INIT. + * + * Input Parameters: + * arg - The boardctl() argument is passed to the board_app_initialize() + * implementation without modification. The argument has no + * meaning to NuttX; the meaning of the argument is a contract + * between the board-specific initalization logic and the the + * matching application logic. The value cold be such things as a + * mode enumeration value, a set of DIP switch switch settings, a + * pointer to configuration data read from a file or serial FLASH, + * or whatever you would like to do with it. Every implementation + * should accept zero/NULL as a default configuration. + * + * Returned Value: + * Zero (OK) is returned on success; a negated errno value is returned on + * any failure to indicate the nature of the failure. + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#ifndef CONFIG_BOARD_INITIALIZE + /* Perform board initialization */ + + return k64_bringup(); +#else + return OK; +#endif +} + +#endif /* CONFIG_LIB_BOARDCTL */ diff --git a/configs/freedom-k64f/src/k64_autoleds.c b/configs/freedom-k64f/src/k64_autoleds.c new file mode 100644 index 0000000000000000000000000000000000000000..5fb416f208f4c5517ecad7c03d13ef622ff0ebe2 --- /dev/null +++ b/configs/freedom-k64f/src/k64_autoleds.c @@ -0,0 +1,162 @@ +/**************************************************************************** + * configs/freedom-k64f/src/k64_autoleds.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ +/* The Freedom K64F has a single RGB LED driven by the K64F as follows: + * + * LED K64 + * ------ ------------------------------------------------------- + * RED PTB22/SPI2_SOUT/FB_AD29/CMP2_OUT + * BLUE PTB21/SPI2_SCK/FB_AD30/CMP1_OUT + * GREEN PTE26/ENET_1588_CLKIN/UART4_CTS_b/RTC_CLKOUT/USB0_CLKIN + * + * If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on board + * the Freedom K64F. The following definitions describe how NuttX controls + * the LEDs: + * + * SYMBOL Meaning LED state + * RED GREEN BLUE + * ------------------- ----------------------- ----------------- + * LED_STARTED NuttX has been started OFF OFF OFF + * LED_HEAPALLOCATE Heap has been allocated OFF OFF ON + * LED_IRQSENABLED Interrupts enabled OFF OFF ON + * LED_STACKCREATED Idle stack created OFF ON OFF + * LED_INIRQ In an interrupt (no change) + * LED_SIGNAL In a signal handler (no change) + * LED_ASSERTION An assertion failed (no change) + * LED_PANIC The system has crashed FLASH OFF OFF + * LED_IDLE K64 is in sleep mode (Optional, not used) + */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "kinetis.h" +#include "freedom-k64f.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Summary of all possible settings */ + +#define LED_NOCHANGE 0 /* LED_IRQSENABLED, LED_INIRQ, LED_SIGNAL, LED_ASSERTION */ +#define LED_OFF_OFF_OFF 1 /* LED_STARTED */ +#define LED_OFF_OFF_ON 2 /* LED_HEAPALLOCATE */ +#define LED_OFF_ON_OFF 3 /* LED_STACKCREATED */ +#define LED_ON_OFF_OFF 4 /* LED_PANIC */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + * + * Description: + * Initialize the on-board LED + * + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + kinetis_pinconfig(GPIO_LED_R); + kinetis_pinconfig(GPIO_LED_G); + kinetis_pinconfig(GPIO_LED_B); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led != LED_NOCHANGE) + { + bool redoff = true; + bool greenoff = true; + bool blueoff = true; + + switch (led) + { + default: + case LED_OFF_OFF_OFF: + break; + + case LED_OFF_OFF_ON: + blueoff = false; + break; + + case LED_OFF_ON_OFF: + greenoff = false; + break; + + case LED_ON_OFF_OFF: + redoff = false; + break; + } + + kinetis_gpiowrite(GPIO_LED_R, redoff); + kinetis_gpiowrite(GPIO_LED_G, greenoff); + kinetis_gpiowrite(GPIO_LED_B, blueoff); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == LED_ON_OFF_OFF) + { + kinetis_gpiowrite(GPIO_LED_R, true); + kinetis_gpiowrite(GPIO_LED_G, true); + kinetis_gpiowrite(GPIO_LED_B, true); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/configs/freedom-k64f/src/k64_boot.c b/configs/freedom-k64f/src/k64_boot.c new file mode 100644 index 0000000000000000000000000000000000000000..4ca687d96fed09ad8db7985dd41e2e5b9290754c --- /dev/null +++ b/configs/freedom-k64f/src/k64_boot.c @@ -0,0 +1,117 @@ +/************************************************************************************ + * configs/freedom-k64f/src/k64_boot.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include +#include + +#include "up_arch.h" +#include "freedom-k64f.h" + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: kinetis_boardinitialize + * + * Description: + * All Kinetis architectures must provide the following entry point. This entry + * point is called early in the initialization -- after all memory has been + * configured and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void kinetis_boardinitialize(void) +{ +#if defined(CONFIG_KINETIS_SPI1) || defined(CONFIG_KINETIS_SPI2) + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function + * k64_spidev_initialize() has been brought into the link. + */ + + if (k64_spidev_initialize) + { + k64_spidev_initialize(); + } +#endif + +#if defined(CONFIG_USBDEV) && defined(CONFIG_KINETIS_USB) + /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not + * disabled, and 3) the weak function k64_usbinitialize() has been brought + * into the build. + */ + + if (k64_usbinitialize) + { + k64_usbinitialize(); + } +#endif + +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_initialize + * + * Description: + * If CONFIG_BOARD_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_initialize(). board_initialize() will be + * called immediately after up_intitialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_INITIALIZE +void board_initialize(void) +{ + /* Perform board initialization */ + + (void)k64_bringup(); +} +#endif /* CONFIG_BOARD_INITIALIZE */ + diff --git a/configs/freedom-k64f/src/k64_bringup.c b/configs/freedom-k64f/src/k64_bringup.c new file mode 100644 index 0000000000000000000000000000000000000000..0739f95d00c8a1dd7689f54f5207877369d7bd58 --- /dev/null +++ b/configs/freedom-k64f/src/k64_bringup.c @@ -0,0 +1,255 @@ +/**************************************************************************** + * config/freedom-k64f/src/k64_bringup.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#ifdef CONFIG_KINETIS_SDHC +# include +# include +#endif + +#include "kinetis.h" +#include "freedom-k64f.h" + +#if defined(CONFIG_LIB_BOARDCTL) || defined(CONFIG_BOARD_INITIALIZE) + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ +/* Configuration ************************************************************/ + +/* PORT and SLOT number probably depend on the board configuration */ + +#ifdef CONFIG_ARCH_BOARD_FREEDOM_K64F +# define NSH_HAVEUSBDEV 1 +# define NSH_HAVEMMCSD 1 +# if defined(CONFIG_NSH_MMCSDSLOTNO) && CONFIG_NSH_MMCSDSLOTNO != 0 +# error "Only one MMC/SD slot, slot 0" +# undef CONFIG_NSH_MMCSDSLOTNO +# endif +# ifndef CONFIG_NSH_MMCSDSLOTNO +# define CONFIG_NSH_MMCSDSLOTNO 0 +# endif +#else + /* Add configuration for new Kinetis boards here */ +# error "Unrecognized Kinetis board" +# undef NSH_HAVEUSBDEV +# undef NSH_HAVEMMCSD +#endif + +/* Can't support USB features if USB is not enabled */ + +#ifndef CONFIG_USBDEV +# undef NSH_HAVEUSBDEV +#endif + +/* Can't support MMC/SD features if mountpoints are disabled or if SDHC support + * is not enabled. + */ + +#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_KINETIS_SDHC) +# undef NSH_HAVEMMCSD +#endif + +#ifndef CONFIG_NSH_MMCSDMINOR +# define CONFIG_NSH_MMCSDMINOR 0 +#endif + +/* We expect to receive GPIO interrupts for card insertion events */ + +#ifndef CONFIG_GPIO_IRQ +# error "CONFIG_GPIO_IRQ required for card detect interrupt" +#endif + +#ifndef CONFIG_KINETIS_PORTEINTS +# error "CONFIG_KINETIS_PORTEINTS required for card detect interrupt" +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* This structure encapsulates the global variable used in this file and + * reduces the probability of name collistions. + */ + +#ifdef NSH_HAVEMMCSD +struct k64_nsh_s +{ + FAR struct sdio_dev_s *sdhc; /* SDIO driver handle */ + bool inserted; /* True: card is inserted */ +}; +#endif + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +#ifdef NSH_HAVEMMCSD +static struct k64_nsh_s g_nsh; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: k64_mediachange + ****************************************************************************/ + +#ifdef NSH_HAVEMMCSD +static void k64_mediachange(void) +{ + bool inserted; + + /* Get the current value of the card detect pin. This pin is pulled up on + * board. So low means that a card is present. + */ + + inserted = !kinetis_gpioread(GPIO_SD_CARDDETECT); + + /* Has the pin changed state? */ + + if (inserted != g_nsh.inserted) + { + /* Yes.. perform the appropriate action (this might need some debounce). */ + + g_nsh.inserted = inserted; + sdhc_mediachange(g_nsh.sdhc, inserted); + + /* If the card has been inserted, then check if it is write protected + * as well. The pin is pulled up, but apparently logic high means + * write protected. + */ + + if (inserted) + { + sdhc_wrprotect(g_nsh.sdhc, kinetis_gpioread(GPIO_SD_WRPROTECT)); + } + } +} +#endif + +/**************************************************************************** + * Name: k64_cdinterrupt + ****************************************************************************/ + +#ifdef NSH_HAVEMMCSD +static int k64_cdinterrupt(int irq, FAR void *context) +{ + /* All of the work is done by k64_mediachange() */ + + k64_mediachange(); + return OK; +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/************************************************************************************ + * Name: k64_bringup + * + * Description: + * Bring up board features + * + ************************************************************************************/ + +int k64_bringup(void) +{ +#ifdef NSH_HAVEMMCSD + int ret; + + /* Configure GPIO pins */ + + /* Attached the card detect interrupt (but don't enable it yet) */ + + kinetis_pinconfig(GPIO_SD_CARDDETECT); + kinetis_pinirqattach(GPIO_SD_CARDDETECT, k64_cdinterrupt); + + /* Configure the write protect GPIO */ + + kinetis_pinconfig(GPIO_SD_WRPROTECT); + + /* Mount the SDHC-based MMC/SD block driver */ + /* First, get an instance of the SDHC interface */ + + syslog(LOG_INFO, "Initializing SDHC slot %d\n", + CONFIG_NSH_MMCSDSLOTNO); + + g_nsh.sdhc = sdhc_initialize(CONFIG_NSH_MMCSDSLOTNO); + if (!g_nsh.sdhc) + { + syslog(LOG_ERR, "ERROR: Failed to initialize SDHC slot %d\n", + CONFIG_NSH_MMCSDSLOTNO); + return -ENODEV; + } + + /* Now bind the SDHC interface to the MMC/SD driver */ + + syslog(LOG_INFO, "Bind SDHC to the MMC/SD driver, minor=%d\n", + CONFIG_NSH_MMCSDMINOR); + + ret = mmcsd_slotinitialize(CONFIG_NSH_MMCSDMINOR, g_nsh.sdhc); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to bind SDHC to the MMC/SD driver: %d\n", ret); + return ret; + } + + syslog(LOG_INFO, "Successfully bound SDHC to the MMC/SD driver\n"); + + /* Handle the initial card state */ + + k64_mediachange(); + + /* Enable CD interrupts to handle subsequent media changes */ + + kinetis_pinirqenable(GPIO_SD_CARDDETECT); +#endif + return OK; +} + +#endif /* CONFIG_LIB_BOARDCTL CONFIG_BOARD_INITIALIZE */ diff --git a/configs/freedom-k64f/src/k64_buttons.c b/configs/freedom-k64f/src/k64_buttons.c new file mode 100644 index 0000000000000000000000000000000000000000..f1f4ba88477a0c32e7217ac6499a75a5678b8f2d --- /dev/null +++ b/configs/freedom-k64f/src/k64_buttons.c @@ -0,0 +1,170 @@ +/**************************************************************************** + * configs/freedom-k64f/src/k64_buttons.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include "freedom-k64f.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Two push buttons, SW2 and SW3, are available on FRDM-K64F board, where SW2 is + * connected to PTC6 and SW3 is connected to PTA4. Besides the general purpose + * input/output functions, SW2 and SW3 can be low-power wake up signal. Also, only + * SW3 can be a non-maskable interrupt. + * + * Switch GPIO Function + * --------- --------------------------------------------------------------- + * SW2 PTC6/SPI0_SOUT/PD0_EXTRG/I2S0_RX_BCLK/FB_AD9/I2S0_MCLK/LLWU_P10 + * SW3 PTA4/FTM0_CH1/NMI_b/LLWU_P3 + */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +void board_button_initialize(void) +{ + /* Configure the two buttons as inputs */ + + kinetis_pinconfig(GPIO_SW2); + kinetis_pinconfig(GPIO_SW3); +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint8_t board_buttons(void) +{ + uint8_t ret = 0; + + if (kinetis_gpioread(GPIO_SW2)) + { + ret |= BUTTON_SW2_BIT; + } + + if (kinetis_gpioread(GPIO_SW3)) + { + ret |= BUTTON_SW3_BIT; + } + + return ret +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button + * resources. After that, board_buttons() may be called to collect the + * current state of all buttons or board_button_irq() may be called to + * register button interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may + * be called to collect the state of all buttons. board_buttons() returns + * an 8-bit bit set with each bit associated with a button. See the + * BUTTON_*_BIT and JOYSTICK_*_BIT definitions in board.h for the meaning + * of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* and JOYSTICK_* definitions in board.h for the meaning + * of enumeration value. The previous interrupt handler address is + * returned (so that it may restored, if so desired). + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +xcpt_t board_button_irq(int id, xcpt_t irqhandler) +{ + xcpt_t oldhandler; + uint32_t pinset; + + /* Map the button id to the GPIO bit set. */ + + if (id == BUTTON_SW2) + { + pinset = GPIO_SW2; + } + else if (id == BUTTON_SW3) + { + pinset = GPIO_SW3; + } + else + { + return NULL; + } + + /* The button has already been configured as an interrupting input (by + * board_button_initialize() above). + * + * Attach the new button handler. + */ + + oldhandler = knetis_pinirqattach(pinset, irqhandler); + + /* Then make sure that interrupts are enabled on the pin */ + + kinetis_pindmaenable(pinset); + return oldhandler; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/configs/freedom-k64f/src/k64_spi.c b/configs/freedom-k64f/src/k64_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..847d5af7e479607d4740a8f4f61408ad58581030 --- /dev/null +++ b/configs/freedom-k64f/src/k64_spi.c @@ -0,0 +1,143 @@ +/************************************************************************************ + * configs/freedom-k64f/src/k64_spi.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "chip.h" +#include "kinetis.h" +#include "freedom-k64f.h" + +#if defined(CONFIG_KINETIS_SPI1) || defined(CONFIG_KINETIS_SPI2) + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: k64_spidev_initialize + * + * Description: + * Called to configure SPI chip select GPIO pins for the FREEDOM-K64F board. + * + ************************************************************************************/ + +void weak_function k64_spidev_initialize(void) +{ +# warning "Missing logic" +} + +/************************************************************************************ + * Name: kinetis_spi[n]select, kinetis_spi[n]status, and kinetis_spi[n]cmddata + * + * Description: + * These external functions must be provided by board-specific logic. They are + * implementations of the select, status, and cmddata methods of the SPI interface + * defined by struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods + * including kinetis_spibus_initialize()) are provided by common Kinetis logic. + * To use this common SPI logic on your board: + * + * 1. Provide logic in kinetis_boardinitialize() to configure SPI chip select + * pins. + * 2. Provide kinetis_spi[n]select() and kinetis_spi[n]status() functions + * in your board-specific logic. These functions will perform chip selection + * and status operations using GPIOs in the way your board is configured. + * 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide + * kinetis_spi[n]cmddata() functions in your board-specific logic. These + * functions will perform cmd/data selection operations using GPIOs in the way + * your board is configured. + * 3. Add a call to kinetis_spibus_initialize() in your low level application + * initialization logic + * 4. The handle returned by kinetis_spibus_initialize() may then be used to bind the + * SPI driver to higher level logic (e.g., calling + * mmcsd_spislotinitialize(), for example, will bind the SPI driver to + * the SPI MMC/SD driver). + * + ************************************************************************************/ + +#ifdef CONFIG_KINETIS_SPI1 +void kinetis_spi1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); +# warning "Missing logic" +} + +uint8_t kinetis_spi1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) +{ +# warning "Missing logic" + return SPI_STATUS_PRESENT; +} +#endif + +#ifdef CONFIG_KINETIS_SPI2 +void kinetis_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); +# warning "Missing logic" +} + +uint8_t kinetis_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) +{ +# warning "Missing logic" + return SPI_STATUS_PRESENT; +} +#endif + +#ifdef CONFIG_KINETIS_SPI3 +void kinetis_spi3select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected) +{ + spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); +# warning "Missing logic" +} + +uint8_t kinetis_spi3status(FAR struct spi_dev_s *dev, enum spi_dev_e devid) +{ +# warning "Missing logic" + return SPI_STATUS_PRESENT; +} +#endif + +#endif /* CONFIG_KINETIS_SPI1 || CONFIG_KINETIS_SPI2 */ diff --git a/configs/freedom-k64f/src/k64_usbdev.c b/configs/freedom-k64f/src/k64_usbdev.c new file mode 100644 index 0000000000000000000000000000000000000000..379f0e2cc193b0ee70988506113e17da88860281 --- /dev/null +++ b/configs/freedom-k64f/src/k64_usbdev.c @@ -0,0 +1,105 @@ +/************************************************************************************ + * configs/freedom-k64f/src/k64_usbdev.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +#include "up_arch.h" +#include "kinetis.h" +#include "freedom-k64f.h" + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: k64_usbinitialize + * + * Description: + * Called to setup USB-related GPIO pins for the FREEDOM-K64F board. + * + ************************************************************************************/ + +void k64_usbinitialize(void) +{ +# warning "Missing logic" +} + +/************************************************************************************ + * Name: kinetis_usbpullup + * + * Description: + * If USB is supported and the board supports a pullup via GPIO (for USB software + * connect and disconnect), then the board software must provide kinetis_usbpullup. + * See include/nuttx/usb/usbdev.h for additional description of this method. + * Alternatively, if no pull-up GPIO the following EXTERN can be redefined to be + * NULL. + * + ************************************************************************************/ + +int kinetis_usbpullup(FAR struct usbdev_s *dev, bool enable) +{ + usbtrace(TRACE_DEVPULLUP, (uint16_t)enable); +# warning "Missing logic" + return OK; +} + +/************************************************************************************ + * Name: kinetis_usbsuspend + * + * Description: + * Board logic must provide the kinetis_usbsuspend logic if the USBDEV driver is + * used. This function is called whenever the USB enters or leaves suspend mode. + * This is an opportunity for the board logic to shutdown clocks, power, etc. + * while the USB is suspended. + * + ************************************************************************************/ + +void kinetis_usbsuspend(FAR struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +#warning "Missing logic" +} diff --git a/configs/freedom-k64f/src/k64_usbmsc.c b/configs/freedom-k64f/src/k64_usbmsc.c new file mode 100644 index 0000000000000000000000000000000000000000..0c5ff493c0a8306d99e53e7e1cca56b1a56e7b23 --- /dev/null +++ b/configs/freedom-k64f/src/k64_usbmsc.c @@ -0,0 +1,99 @@ +/**************************************************************************** + * configs/freedom-k64f/src/k64_usbmsc.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Configure and register the Kinetis MMC/SD block driver. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "kinetis.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 +# define CONFIG_SYSTEM_USBMSC_DEVMINOR1 0 +#endif + +/* SLOT number(s) could depend on the board configuration */ + +#ifdef CONFIG_ARCH_BOARD_FREEDOM_K64F +# undef K64_MMCSDSLOTNO +# define K64_MMCSDSLOTNO 0 +#else + /* Add configuration for new Kinetis boards here */ +# error "Unrecognized Kinetis board" +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_usbmsc_initialize + * + * Description: + * Perform architecture specific initialization as needed to establish + * the mass storage device that will be exported by the USB MSC device. + * + ****************************************************************************/ + +int board_usbmsc_initialize(int port) +{ + /* If system/usbmsc is built as an NSH command, then SD slot should + * already have been initialized in board_app_initialize() (see k64_appinit.c). + * In this case, there is nothing further to be done here. + */ + +#ifndef CONFIG_NSH_BUILTIN_APPS +# warning "Missing logic" +#endif /* CONFIG_NSH_BUILTIN_APPS */ + + return OK; +} diff --git a/configs/freedom-k64f/src/k64_userleds.c b/configs/freedom-k64f/src/k64_userleds.c new file mode 100644 index 0000000000000000000000000000000000000000..48a396a3ce4103083cc7d7838731d69e88390b94 --- /dev/null +++ b/configs/freedom-k64f/src/k64_userleds.c @@ -0,0 +1,109 @@ +/**************************************************************************** + * configs/freedom-k64f/src/k64_userleds.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "kinetis.h" +#include "freedom-k64f.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +void board_userled_initialize(void) +{ + kinetis_pinconfig(GPIO_LED_R); + kinetis_pinconfig(GPIO_LED_G); + kinetis_pinconfig(GPIO_LED_B); +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + uint32_t ledcfg; + + if (led == BOARD_LED_R) + { + ledcfg = GPIO_LED_R; + } + else if (led == BOARD_LED_G) + { + ledcfg = GPIO_LED_G; + } + else if (led == BOARD_LED_B) + { + ledcfg = GPIO_LED_B; + } + else + { + return; + } + + kinetis_gpiowrite(ledcfg, !ledon); /* Low illuminates */ +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint8_t ledset) +{ + /* Low illuminates */ + + kinetis_gpiowrite(GPIO_LED_R, (ledset & BOARD_LED_R_BIT) == 0); + kinetis_gpiowrite(GPIO_LED_G, (ledset & BOARD_LED_G_BIT) == 0); + kinetis_gpiowrite(GPIO_LED_B, (ledset & BOARD_LED_B_BIT) == 0); +} diff --git a/configs/freedom-kl25z/minnsh/defconfig b/configs/freedom-kl25z/minnsh/defconfig index 0b7545d9c15ab4fd4a647c3916c637bf57bfac52..8a7b3f90623a85468d571fa7befe4c2899b61aff 100644 --- a/configs/freedom-kl25z/minnsh/defconfig +++ b/configs/freedom-kl25z/minnsh/defconfig @@ -786,7 +786,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/freedom-kl25z/nsh/defconfig b/configs/freedom-kl25z/nsh/defconfig index 932777e5023e970d75fa8c535a9270bf223f9d82..639cc13063e5d7a288cc9c14c4782a2021b77603 100644 --- a/configs/freedom-kl25z/nsh/defconfig +++ b/configs/freedom-kl25z/nsh/defconfig @@ -816,7 +816,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/freedom-kl26z/minnsh/defconfig b/configs/freedom-kl26z/minnsh/defconfig index d68ba77924b4776eefc966cc26065d92b06b46ae..3356a639659aa93d268a6240e36fb337fd45b187 100644 --- a/configs/freedom-kl26z/minnsh/defconfig +++ b/configs/freedom-kl26z/minnsh/defconfig @@ -786,7 +786,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/freedom-kl26z/nsh/defconfig b/configs/freedom-kl26z/nsh/defconfig index c6c7dc985fb610761bb6cd943f924a9f06cd1c45..4e8d2b0f702cdc14f5070fb3e30da333d4dc6287 100644 --- a/configs/freedom-kl26z/nsh/defconfig +++ b/configs/freedom-kl26z/nsh/defconfig @@ -816,7 +816,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/hymini-stm32v/README.txt b/configs/hymini-stm32v/README.txt index 2ec1c04353582abaa70484ce04ee345395e84c67..e6643aaed34b1b214d9513f0e4452f2df7e3eb26 100644 --- a/configs/hymini-stm32v/README.txt +++ b/configs/hymini-stm32v/README.txt @@ -667,16 +667,16 @@ Where is one of the following: CONFIG_USBDEV_TRACE_NRECORDS=128 : Buffer 128 records in memory CONFIG_NSH_USBDEV_TRACE=n : No builtin tracing from NSH CONFIG_NSH_ARCHINIT=y : Automatically start the USB monitor - CONFIG_SYSTEM_USBMONITOR=y : Enable the USB monitor daemon - CONFIG_SYSTEM_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size - CONFIG_SYSTEM_USBMONITOR_PRIORITY=50 : USB monitor daemon priority - CONFIG_SYSTEM_USBMONITOR_INTERVAL=2 : Dump trace data every 2 seconds - - CONFIG_SYSTEM_USBMONITOR_TRACEINIT=y : Enable TRACE output - CONFIG_SYSTEM_USBMONITOR_TRACECLASS=y - CONFIG_SYSTEM_USBMONITOR_TRACETRANSFERS=y - CONFIG_SYSTEM_USBMONITOR_TRACECONTROLLER=y - CONFIG_SYSTEM_USBMONITOR_TRACEINTERRUPTS=y + CONFIG_USBMONITOR=y : Enable the USB monitor daemon + CONFIG_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size + CONFIG_USBMONITOR_PRIORITY=50 : USB monitor daemon priority + CONFIG_USBMONITOR_INTERVAL=2 : Dump trace data every 2 seconds + + CONFIG_USBMONITOR_TRACEINIT=y : Enable TRACE output + CONFIG_USBMONITOR_TRACECLASS=y + CONFIG_USBMONITOR_TRACETRANSFERS=y + CONFIG_USBMONITOR_TRACECONTROLLER=y + CONFIG_USBMONITOR_TRACEINTERRUPTS=y Using the Prolifics PL2303 Emulation diff --git a/configs/hymini-stm32v/buttons/defconfig b/configs/hymini-stm32v/buttons/defconfig index bed31efc27f13305ce95d73de60d45f8c187b2ce..a1d993bdc0cd4a43ef4e104edd566cbc73a0927c 100644 --- a/configs/hymini-stm32v/buttons/defconfig +++ b/configs/hymini-stm32v/buttons/defconfig @@ -1013,7 +1013,7 @@ CONFIG_EXAMPLES_BUTTONS_NAME7="Button 7" # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/hymini-stm32v/nsh/defconfig b/configs/hymini-stm32v/nsh/defconfig index 44bc062c76d2c033a08406ad2ec7d0906877fa89..0411715e505688e3eaf8f99d2d298881ca7cb816 100644 --- a/configs/hymini-stm32v/nsh/defconfig +++ b/configs/hymini-stm32v/nsh/defconfig @@ -1134,7 +1134,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/hymini-stm32v/nsh2/defconfig b/configs/hymini-stm32v/nsh2/defconfig index 6613d88a845b236f2ca40a52c30aafe657df1b83..826bd059a2106b47b1f9dac3115ce3b79bb56c35 100644 --- a/configs/hymini-stm32v/nsh2/defconfig +++ b/configs/hymini-stm32v/nsh2/defconfig @@ -1415,7 +1415,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set @@ -1426,7 +1426,7 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set # CONFIG_SYSTEM_UBLOXMODEM is not set -# CONFIG_SYSTEM_USBMONITOR is not set +# CONFIG_USBMONITOR is not set CONFIG_SYSTEM_USBMSC=y CONFIG_SYSTEM_USBMSC_NLUNS=1 CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 diff --git a/configs/hymini-stm32v/usbmsc/defconfig b/configs/hymini-stm32v/usbmsc/defconfig index 75652b23a63ce049109f9ba051f62b65438ab0d5..50290a135f2fef8c696caa7d13d7b73c9f452602 100644 --- a/configs/hymini-stm32v/usbmsc/defconfig +++ b/configs/hymini-stm32v/usbmsc/defconfig @@ -1094,7 +1094,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/hymini-stm32v/usbnsh/defconfig b/configs/hymini-stm32v/usbnsh/defconfig index 5ac1d3cc08fa34de27101413237d33b24bcf27cc..c794400467b55fc8723b9f04b385ebac9c1def32 100644 --- a/configs/hymini-stm32v/usbnsh/defconfig +++ b/configs/hymini-stm32v/usbnsh/defconfig @@ -1158,7 +1158,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/hymini-stm32v/usbserial/defconfig b/configs/hymini-stm32v/usbserial/defconfig index 8f3d549fe20e8c0c7cc1499fe06f1e9c9e7605aa..0771b22ef0c9c9afd24fa7d9441e5cc054739771 100644 --- a/configs/hymini-stm32v/usbserial/defconfig +++ b/configs/hymini-stm32v/usbserial/defconfig @@ -1056,7 +1056,7 @@ CONFIG_EXAMPLES_USBSERIAL_BUFSIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/kwikstik-k40/ostest/defconfig b/configs/kwikstik-k40/ostest/defconfig index dcf0bda3c3074b89c61753a5a61c94fbfb39bbbe..befa76725dd1c3bd1e439f6039261d5554ff7c4b 100644 --- a/configs/kwikstik-k40/ostest/defconfig +++ b/configs/kwikstik-k40/ostest/defconfig @@ -761,7 +761,7 @@ CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/launchxl-tms57004/nsh/defconfig b/configs/launchxl-tms57004/nsh/defconfig index ce89fc88bf351b55b2afddc244d4cdc596dcfa98..5dac2700b4e7a7bde34841fc41846ed4457e930e 100644 --- a/configs/launchxl-tms57004/nsh/defconfig +++ b/configs/launchxl-tms57004/nsh/defconfig @@ -857,7 +857,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_I2CTOOL is not set # CONFIG_SYSTEM_INSTALL is not set diff --git a/configs/lincoln60/netnsh/defconfig b/configs/lincoln60/netnsh/defconfig index 265907de16ff8bfbc9425be36382d7e46e973633..eb4939104ca497d85a65f0bc445cb8a9faac6ec0 100644 --- a/configs/lincoln60/netnsh/defconfig +++ b/configs/lincoln60/netnsh/defconfig @@ -1113,7 +1113,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/lincoln60/nsh/defconfig b/configs/lincoln60/nsh/defconfig index 223015351e30a27f7514e9d7823b540c941e25ce..2b99c9a39e83e720a9b7315a6e0a8d6898a1ac1a 100644 --- a/configs/lincoln60/nsh/defconfig +++ b/configs/lincoln60/nsh/defconfig @@ -871,7 +871,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/lincoln60/thttpd-binfs/defconfig b/configs/lincoln60/thttpd-binfs/defconfig index a59c0d2ee566dc28347ac4bcb9984b0646f8d069..41f2b81909602eaac2eca7d33b84d52806f8d587 100644 --- a/configs/lincoln60/thttpd-binfs/defconfig +++ b/configs/lincoln60/thttpd-binfs/defconfig @@ -971,7 +971,7 @@ CONFIG_THTTPD_TILDE_MAP_NONE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/lm3s6432-s2e/nsh/defconfig b/configs/lm3s6432-s2e/nsh/defconfig index 36f502dc4d26bbe4c45c04c8b5e1ab164660a7f7..cbf540affc3abcdb0f4307326a22217289c0c1a6 100644 --- a/configs/lm3s6432-s2e/nsh/defconfig +++ b/configs/lm3s6432-s2e/nsh/defconfig @@ -1089,7 +1089,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/lm3s6965-ek/discover/defconfig b/configs/lm3s6965-ek/discover/defconfig index a7c640c03d30f5fed4dbd655a4ef5e3aa394516b..abe5b4dce60c9d3a3165475fd2e707a20de53e49 100644 --- a/configs/lm3s6965-ek/discover/defconfig +++ b/configs/lm3s6965-ek/discover/defconfig @@ -1123,7 +1123,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/lm3s6965-ek/nsh/defconfig b/configs/lm3s6965-ek/nsh/defconfig index a7c640c03d30f5fed4dbd655a4ef5e3aa394516b..abe5b4dce60c9d3a3165475fd2e707a20de53e49 100644 --- a/configs/lm3s6965-ek/nsh/defconfig +++ b/configs/lm3s6965-ek/nsh/defconfig @@ -1123,7 +1123,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/lm3s6965-ek/nx/defconfig b/configs/lm3s6965-ek/nx/defconfig index 25f91bb2a394ba16df7be47bccb927525f84df11..b9c138e539b5cf843a68ae479a18d7bd3062e3e3 100644 --- a/configs/lm3s6965-ek/nx/defconfig +++ b/configs/lm3s6965-ek/nx/defconfig @@ -926,7 +926,7 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/lm3s6965-ek/tcpecho/defconfig b/configs/lm3s6965-ek/tcpecho/defconfig index a0b8bd8847f2379ce39ee50142b85c69c6a4f6d9..eef4cfa398b9c3306dbc154e9509e80e78a2753f 100644 --- a/configs/lm3s6965-ek/tcpecho/defconfig +++ b/configs/lm3s6965-ek/tcpecho/defconfig @@ -971,7 +971,7 @@ CONFIG_WEBCLIENT_TIMEOUT=10 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/lm3s8962-ek/nsh/defconfig b/configs/lm3s8962-ek/nsh/defconfig index 6cf80ae026e7071f4332b0c312d34119f07d8b6f..fbfabcd052995eae31de50337a3ff5e6745738a2 100644 --- a/configs/lm3s8962-ek/nsh/defconfig +++ b/configs/lm3s8962-ek/nsh/defconfig @@ -1132,7 +1132,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/lm3s8962-ek/nx/defconfig b/configs/lm3s8962-ek/nx/defconfig index 30bf76afc80ce85302b71ab7e293316c045c4e59..5f8a28db200b8e6d0222dbc1747ab57e2a79c97c 100644 --- a/configs/lm3s8962-ek/nx/defconfig +++ b/configs/lm3s8962-ek/nx/defconfig @@ -936,7 +936,7 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/lm4f120-launchpad/nsh/defconfig b/configs/lm4f120-launchpad/nsh/defconfig index 6d41ced7f3e9216717a74a914628a369ae33569b..f69c7c30895a02672fd705036824d89622f41d77 100644 --- a/configs/lm4f120-launchpad/nsh/defconfig +++ b/configs/lm4f120-launchpad/nsh/defconfig @@ -892,7 +892,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/lpc4330-xplorer/nsh/defconfig b/configs/lpc4330-xplorer/nsh/defconfig index 045cd709d0b8b4fa7f8c0cf841b879c214a411bd..96cee0346b9ff6cfdd3c29ed1a40705101d125c1 100644 --- a/configs/lpc4330-xplorer/nsh/defconfig +++ b/configs/lpc4330-xplorer/nsh/defconfig @@ -892,7 +892,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/lpc4337-ws/nsh/defconfig b/configs/lpc4337-ws/nsh/defconfig index ebe47a6fc981e9f2b60aef10da3e7414d0c05eaa..128ae9ca59008cdef1683ffa7b499dabab50ce6a 100644 --- a/configs/lpc4337-ws/nsh/defconfig +++ b/configs/lpc4337-ws/nsh/defconfig @@ -962,7 +962,7 @@ CONFIG_SYSTEM_CDCACM_DEVMINOR=0 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set CONFIG_SYSTEM_I2CTOOL=y CONFIG_I2CTOOL_MINBUS=0 diff --git a/configs/lpc4357-evb/nsh/defconfig b/configs/lpc4357-evb/nsh/defconfig index a94de720c8a21f5549e5c2bfdc6c9ff22737c963..58f05c236e05502811d92102d414c59f788f1e28 100644 --- a/configs/lpc4357-evb/nsh/defconfig +++ b/configs/lpc4357-evb/nsh/defconfig @@ -884,7 +884,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/lpc4370-link2/nsh/defconfig b/configs/lpc4370-link2/nsh/defconfig index 96822e9ab23d8b829d7bff1f53989e955b0d88af..f740cfd7bf7a0b946f96d304e93f02801cbf1bcd 100644 --- a/configs/lpc4370-link2/nsh/defconfig +++ b/configs/lpc4370-link2/nsh/defconfig @@ -958,7 +958,7 @@ CONFIG_SYSTEM_CDCACM_DEVMINOR=0 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set CONFIG_SYSTEM_I2CTOOL=y CONFIG_I2CTOOL_MINBUS=0 diff --git a/configs/lpcxpresso-lpc1115/minnsh/defconfig b/configs/lpcxpresso-lpc1115/minnsh/defconfig index 6a1ef9c5e39b8f159b38552e3eefb47237281be2..ea60c5f721ec4ba87c20aeac55d1b9819fb8bb6e 100644 --- a/configs/lpcxpresso-lpc1115/minnsh/defconfig +++ b/configs/lpcxpresso-lpc1115/minnsh/defconfig @@ -754,7 +754,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/lpcxpresso-lpc1115/nsh/defconfig b/configs/lpcxpresso-lpc1115/nsh/defconfig index 26382b3c070790781f4b00648e831af145124971..22a4a0c7dc924885c590323023e30d8a58125c13 100644 --- a/configs/lpcxpresso-lpc1115/nsh/defconfig +++ b/configs/lpcxpresso-lpc1115/nsh/defconfig @@ -781,7 +781,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/lpcxpresso-lpc1768/dhcpd/defconfig b/configs/lpcxpresso-lpc1768/dhcpd/defconfig index 1ab45ab5e9d582a77a6c308b832eca25d4fa296e..5cb3db6d551f520e890de3ad03ca46ad8a068a8d 100644 --- a/configs/lpcxpresso-lpc1768/dhcpd/defconfig +++ b/configs/lpcxpresso-lpc1768/dhcpd/defconfig @@ -916,7 +916,7 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/lpcxpresso-lpc1768/nsh/defconfig b/configs/lpcxpresso-lpc1768/nsh/defconfig index d50765a4286d1a5d947f585495287b0163a3d0f8..873e93ae0774bf698a8894bb59184dc9e3a6c61f 100644 --- a/configs/lpcxpresso-lpc1768/nsh/defconfig +++ b/configs/lpcxpresso-lpc1768/nsh/defconfig @@ -1153,7 +1153,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/lpcxpresso-lpc1768/nx/defconfig b/configs/lpcxpresso-lpc1768/nx/defconfig index 62553fce52317f05f99e82766312947be3daa3d1..b1e82a5645b6f9610f6ea8351e268220c8fc6beb 100644 --- a/configs/lpcxpresso-lpc1768/nx/defconfig +++ b/configs/lpcxpresso-lpc1768/nx/defconfig @@ -905,7 +905,7 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/lpcxpresso-lpc1768/thttpd/defconfig b/configs/lpcxpresso-lpc1768/thttpd/defconfig index be0fb5fbaf4bd0c65f6d902411cd7b146beacc51..dc17b59f8ba200af13a8e489dec27e2c5827c259 100644 --- a/configs/lpcxpresso-lpc1768/thttpd/defconfig +++ b/configs/lpcxpresso-lpc1768/thttpd/defconfig @@ -955,7 +955,7 @@ CONFIG_THTTPD_TILDE_MAP_NONE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/lpcxpresso-lpc1768/usbmsc/defconfig b/configs/lpcxpresso-lpc1768/usbmsc/defconfig index 405c185791568e8a694be0f6b5fa6cd2d4619ba8..ed1b761bcb6c68aa3416f1c3f2e8a74609a28504 100644 --- a/configs/lpcxpresso-lpc1768/usbmsc/defconfig +++ b/configs/lpcxpresso-lpc1768/usbmsc/defconfig @@ -839,7 +839,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/maple/nsh/defconfig b/configs/maple/nsh/defconfig index 47b1e70d77d938a3131abd21f86d941f7d861946..643f6bd63896b2e57c21c114eeafbfe46f920e38 100644 --- a/configs/maple/nsh/defconfig +++ b/configs/maple/nsh/defconfig @@ -1118,7 +1118,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set @@ -1129,6 +1129,6 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set # CONFIG_SYSTEM_UBLOXMODEM is not set -# CONFIG_SYSTEM_USBMONITOR is not set +# CONFIG_USBMONITOR is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/maple/nx/defconfig b/configs/maple/nx/defconfig index 8b166644149285507bcd13fd858436d9d18f56d7..1ba42c9fc0a5e768ad93ba9e870f50b44e3eb2f1 100644 --- a/configs/maple/nx/defconfig +++ b/configs/maple/nx/defconfig @@ -1333,7 +1333,7 @@ CONFIG_USBDEV_MINOR=0 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_I2CTOOL is not set # CONFIG_SYSTEM_INSTALL is not set @@ -1345,6 +1345,6 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set # CONFIG_SYSTEM_UBLOXMODEM is not set -# CONFIG_SYSTEM_USBMONITOR is not set +# CONFIG_USBMONITOR is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/maple/usbnsh/defconfig b/configs/maple/usbnsh/defconfig index 4976608c7f47b111ac293177855864668db585eb..17283af76e25554a7caac0f09eb87c7a4d78c4af 100644 --- a/configs/maple/usbnsh/defconfig +++ b/configs/maple/usbnsh/defconfig @@ -1154,7 +1154,7 @@ CONFIG_USBDEV_MINOR=0 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_I2CTOOL is not set # CONFIG_SYSTEM_INSTALL is not set @@ -1166,6 +1166,6 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set # CONFIG_SYSTEM_UBLOXMODEM is not set -# CONFIG_SYSTEM_USBMONITOR is not set +# CONFIG_USBMONITOR is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/mbed/hidkbd/defconfig b/configs/mbed/hidkbd/defconfig index 58136eab01dd099faae003abc48e20feb58029bc..78b35bd634bae2b4f092e880a935e0bc0d6895e8 100644 --- a/configs/mbed/hidkbd/defconfig +++ b/configs/mbed/hidkbd/defconfig @@ -800,7 +800,7 @@ CONFIG_EXAMPLES_HIDKBD_DEVNAME="/dev/kbda" # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/mbed/nsh/defconfig b/configs/mbed/nsh/defconfig index 95999a5e5618d7cc8d815e43fdbe4fd6848d4638..617dbe793bdeb8b27a8c025c553dbbf50f2ef2de 100644 --- a/configs/mbed/nsh/defconfig +++ b/configs/mbed/nsh/defconfig @@ -924,7 +924,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/mcu123-lpc214x/composite/defconfig b/configs/mcu123-lpc214x/composite/defconfig index f98119041d0ce80c0438fa20c4596f9457d82902..1a279cc8bfd8b7c3d0d911620a14f2912f8cbba2 100644 --- a/configs/mcu123-lpc214x/composite/defconfig +++ b/configs/mcu123-lpc214x/composite/defconfig @@ -845,7 +845,7 @@ CONFIG_SYSTEM_COMPOSITE_BUFSIZE=256 # CONFIG_SYSTEM_COMPOSITE_DEBUGMM is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set @@ -853,7 +853,7 @@ CONFIG_SYSTEM_COMPOSITE_BUFSIZE=256 # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set # CONFIG_SYSTEM_UBLOXMODEM is not set -# CONFIG_SYSTEM_USBMONITOR is not set +# CONFIG_USBMONITOR is not set # CONFIG_SYSTEM_USBMSC is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/mcu123-lpc214x/nsh/defconfig b/configs/mcu123-lpc214x/nsh/defconfig index 9b7c8536eae403ce427d6c3109abd0e49bd1802c..73c0d6685f699951b5679ff2100407eadb7bb965 100644 --- a/configs/mcu123-lpc214x/nsh/defconfig +++ b/configs/mcu123-lpc214x/nsh/defconfig @@ -846,7 +846,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/mcu123-lpc214x/usbmsc/defconfig b/configs/mcu123-lpc214x/usbmsc/defconfig index 250bab2762c413574f7c4ef20877ca83d9a08691..1b5e5bd05d7c44589ba0d51ebf56223196b13c36 100644 --- a/configs/mcu123-lpc214x/usbmsc/defconfig +++ b/configs/mcu123-lpc214x/usbmsc/defconfig @@ -792,7 +792,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set @@ -800,7 +800,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set # CONFIG_SYSTEM_UBLOXMODEM is not set -# CONFIG_SYSTEM_USBMONITOR is not set +# CONFIG_USBMONITOR is not set CONFIG_SYSTEM_USBMSC=y CONFIG_SYSTEM_USBMSC_NLUNS=1 CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 diff --git a/configs/mcu123-lpc214x/usbserial/defconfig b/configs/mcu123-lpc214x/usbserial/defconfig index f682875dd6a8d0bf196d8291c02e11308daac120..0fd83ba665ab207ce9369f1074bc1978d6da4a55 100644 --- a/configs/mcu123-lpc214x/usbserial/defconfig +++ b/configs/mcu123-lpc214x/usbserial/defconfig @@ -758,7 +758,7 @@ CONFIG_EXAMPLES_USBSERIAL_BUFSIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/mikroe-stm32f4/README.txt b/configs/mikroe-stm32f4/README.txt index ace80f20fbda9d9b5304157b46c3ee1c08df5fc3..ad0da7986f86e4db88d23624d56848b9649d9824 100644 --- a/configs/mikroe-stm32f4/README.txt +++ b/configs/mikroe-stm32f4/README.txt @@ -925,16 +925,16 @@ Where is one of the following: CONFIG_USBDEV_TRACE_NRECORDS=128 : Buffer 128 records in memory CONFIG_NSH_USBDEV_TRACE=n : No builtin tracing from NSH CONFIG_NSH_ARCHINIT=y : Automatically start the USB monitor - CONFIG_SYSTEM_USBMONITOR=y : Enable the USB monitor daemon - CONFIG_SYSTEM_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size - CONFIG_SYSTEM_USBMONITOR_PRIORITY=50 : USB monitor daemon priority - CONFIG_SYSTEM_USBMONITOR_INTERVAL=2 : Dump trace data every 2 seconds - - CONFIG_SYSTEM_USBMONITOR_TRACEINIT=y : Enable TRACE output - CONFIG_SYSTEM_USBMONITOR_TRACECLASS=y - CONFIG_SYSTEM_USBMONITOR_TRACETRANSFERS=y - CONFIG_SYSTEM_USBMONITOR_TRACECONTROLLER=y - CONFIG_SYSTEM_USBMONITOR_TRACEINTERRUPTS=y + CONFIG_USBMONITOR=y : Enable the USB monitor daemon + CONFIG_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size + CONFIG_USBMONITOR_PRIORITY=50 : USB monitor daemon priority + CONFIG_USBMONITOR_INTERVAL=2 : Dump trace data every 2 seconds + + CONFIG_USBMONITOR_TRACEINIT=y : Enable TRACE output + CONFIG_USBMONITOR_TRACECLASS=y + CONFIG_USBMONITOR_TRACETRANSFERS=y + CONFIG_USBMONITOR_TRACECONTROLLER=y + CONFIG_USBMONITOR_TRACEINTERRUPTS=y 5. By default, this project assumes that you are *NOT* using the DFU bootloader. diff --git a/configs/mikroe-stm32f4/fulldemo/defconfig b/configs/mikroe-stm32f4/fulldemo/defconfig index 828f56c1aafdae7711e99e315c75cb162b4f6cb4..1091be92d6388a93acc1588d564149d56b9fad3d 100644 --- a/configs/mikroe-stm32f4/fulldemo/defconfig +++ b/configs/mikroe-stm32f4/fulldemo/defconfig @@ -1739,7 +1739,7 @@ CONFIG_PLATFORM_CONFIGDATA=y # CONFIG_SYSTEM_CUTERM is not set CONFIG_SYSTEM_FLASH_ERASEALL=y # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set CONFIG_SYSTEM_NXPLAYER=y diff --git a/configs/mikroe-stm32f4/kostest/defconfig b/configs/mikroe-stm32f4/kostest/defconfig index a190dc6c565c5e7721acb6ff5a90c8645c9e48e6..5a711c2010c27f56f5fac43649a44789b9ec24ac 100644 --- a/configs/mikroe-stm32f4/kostest/defconfig +++ b/configs/mikroe-stm32f4/kostest/defconfig @@ -1312,7 +1312,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/mikroe-stm32f4/nsh/defconfig b/configs/mikroe-stm32f4/nsh/defconfig index 75d7044beae993c871b7c09216558c6e05fa408d..6a58a8add3d7847335e85d2de5b73d38d172e5d6 100644 --- a/configs/mikroe-stm32f4/nsh/defconfig +++ b/configs/mikroe-stm32f4/nsh/defconfig @@ -1243,7 +1243,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CUTERM is not set CONFIG_SYSTEM_FLASH_ERASEALL=y # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/mikroe-stm32f4/nx/defconfig b/configs/mikroe-stm32f4/nx/defconfig index 461a9672d03db17d0c1276659576f400c2356162..0a73409cf40b22d58f4b7d1b6ad6865a2fbb0c0d 100644 --- a/configs/mikroe-stm32f4/nx/defconfig +++ b/configs/mikroe-stm32f4/nx/defconfig @@ -1199,7 +1199,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/mikroe-stm32f4/nxlines/defconfig b/configs/mikroe-stm32f4/nxlines/defconfig index e290831de838658e2d34d11ae9d3f67aa3536a7f..a83f543825f5f1aa22f9b3959ce2b78153fb9ce5 100644 --- a/configs/mikroe-stm32f4/nxlines/defconfig +++ b/configs/mikroe-stm32f4/nxlines/defconfig @@ -1200,7 +1200,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/mikroe-stm32f4/nxtext/defconfig b/configs/mikroe-stm32f4/nxtext/defconfig index d2cd5abd8b78b9a54e712c4c62e6d3d364fd6a21..73fdaa7411d024bddc223f6c968441c56e1081b3 100644 --- a/configs/mikroe-stm32f4/nxtext/defconfig +++ b/configs/mikroe-stm32f4/nxtext/defconfig @@ -1209,7 +1209,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/mikroe-stm32f4/src/stm32_appinit.c b/configs/mikroe-stm32f4/src/stm32_appinit.c index 9970d6927be1f29486e4ede401cafd6565500a3e..7d43cf72ed2baa17e0b725242f53ef1a23fb9eee 100644 --- a/configs/mikroe-stm32f4/src/stm32_appinit.c +++ b/configs/mikroe-stm32f4/src/stm32_appinit.c @@ -55,8 +55,8 @@ # include #endif -#ifdef CONFIG_SYSTEM_USBMONITOR -# include +#ifdef CONFIG_USBMONITOR +# include #endif #ifdef CONFIG_MIKROE_FLASH_CONFIG_PART @@ -110,7 +110,7 @@ /* Check if we should enable the USB monitor before starting NSH */ -#if !defined(CONFIG_USBDEV_TRACE) || !defined(CONFIG_SYSTEM_USBMONITOR) +#if !defined(CONFIG_USBDEV_TRACE) || !defined(CONFIG_USBMONITOR) # undef HAVE_USBMONITOR #endif @@ -347,7 +347,7 @@ int board_app_initialize(uintptr_t arg) #ifdef HAVE_USBMONITOR /* Start the USB Monitor */ - ret = usbmonitor_start(0, NULL); + ret = usbmonitor_start(); if (ret != OK) { syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); diff --git a/configs/mikroe-stm32f4/usbnsh/defconfig b/configs/mikroe-stm32f4/usbnsh/defconfig index 8f1a3901061353cf696a2c7900a347e880b36275..666bf64382c9d01429556123ccbed73fb007304f 100644 --- a/configs/mikroe-stm32f4/usbnsh/defconfig +++ b/configs/mikroe-stm32f4/usbnsh/defconfig @@ -1293,7 +1293,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CUTERM is not set CONFIG_SYSTEM_FLASH_ERASEALL=y # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/mirtoo/nsh/defconfig b/configs/mirtoo/nsh/defconfig index 924327ea7bad7eb3e5db1aef68ef841b05e6be5a..81c76714ba74b75f4c9ee86112fe01d31d637521 100644 --- a/configs/mirtoo/nsh/defconfig +++ b/configs/mirtoo/nsh/defconfig @@ -319,6 +319,8 @@ CONFIG_RAM_SIZE=32768 # CONFIG_ARCH_BOARD_MIRTOO=y # CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD_CUSTOM_DIR="configs/dummy" +CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y CONFIG_ARCH_BOARD="mirtoo" # @@ -326,12 +328,12 @@ CONFIG_ARCH_BOARD="mirtoo" # CONFIG_ARCH_HAVE_LEDS=y CONFIG_ARCH_LEDS=y -CONFIG_NSH_MMCSDMINOR=0 # # Board-Specific Options # CONFIG_MIRTOO_RELEASE=2 +# CONFIG_BOARD_CRASHDUMP is not set # CONFIG_LIB_BOARDCTL is not set # @@ -470,7 +472,12 @@ CONFIG_DEV_NULL=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -833,6 +840,7 @@ CONFIG_NSH_DISABLE_UNAME=y # CONFIG_NSH_DISABLE_USLEEP is not set CONFIG_NSH_DISABLE_WGET=y CONFIG_NSH_DISABLE_XD=y +CONFIG_NSH_MMCSDMINOR=0 # # Configure Command Options @@ -871,7 +879,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/mirtoo/nxffs/defconfig b/configs/mirtoo/nxffs/defconfig index 2f82da56da6387d904f404c43178ae69d69fe5f7..229dcf2e0ff36846bcf857d02f23ec51d33af131 100644 --- a/configs/mirtoo/nxffs/defconfig +++ b/configs/mirtoo/nxffs/defconfig @@ -324,6 +324,8 @@ CONFIG_RAM_SIZE=32768 # CONFIG_ARCH_BOARD_MIRTOO=y # CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD_CUSTOM_DIR="configs/dummy" +CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y CONFIG_ARCH_BOARD="mirtoo" # @@ -331,12 +333,12 @@ CONFIG_ARCH_BOARD="mirtoo" # CONFIG_ARCH_HAVE_LEDS=y CONFIG_ARCH_LEDS=y -CONFIG_NSH_MMCSDMINOR=0 # # Board-Specific Options # CONFIG_MIRTOO_RELEASE=2 +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set @@ -477,7 +479,12 @@ CONFIG_SPI=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -899,6 +906,7 @@ CONFIG_NSH_DISABLE_UNAME=y # CONFIG_NSH_DISABLE_USLEEP is not set CONFIG_NSH_DISABLE_WGET=y # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 # # Configure Command Options @@ -935,7 +943,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/moteino-mega/hello/defconfig b/configs/moteino-mega/hello/defconfig index ddc57e49e37e615fc931f03e04dedec76594d3e1..50794734d6598df0aa3dd552aaa5854a6d8c05e8 100644 --- a/configs/moteino-mega/hello/defconfig +++ b/configs/moteino-mega/hello/defconfig @@ -578,7 +578,7 @@ CONFIG_EXAMPLES_HELLO=y # # Intel HEX to binary conversion # -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # # I2C tool diff --git a/configs/moteino-mega/nsh/defconfig b/configs/moteino-mega/nsh/defconfig index f2590d782dda8dadca39601e30cc1a960c825b7e..f01eb772eae668aea5651fa558caea2ed5c55041 100644 --- a/configs/moteino-mega/nsh/defconfig +++ b/configs/moteino-mega/nsh/defconfig @@ -663,7 +663,7 @@ CONFIG_NSH_CONSOLE=y # # Intel HEX to binary conversion # -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # # I2C tool diff --git a/configs/moxa/nsh/defconfig b/configs/moxa/nsh/defconfig index 2408d18fdb7f84842ca01d547783ce4db2df9a0f..29d3c506170d8e7ef760d76ef91a3507c07f3927 100644 --- a/configs/moxa/nsh/defconfig +++ b/configs/moxa/nsh/defconfig @@ -999,7 +999,7 @@ CONFIG_NSH_LOGIN_FAILCOUNT=3 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/mt-db-x3/README.txt b/configs/mt-db-x3/README.txt deleted file mode 100644 index 5ea012e1fff9b19f8d4bc85134563cc3b8c35e91..0000000000000000000000000000000000000000 --- a/configs/mt-db-x3/README.txt +++ /dev/null @@ -1,88 +0,0 @@ -README -====== - - This README file discusses the port of NuttX to the MT-DB-X3 development - board from MattairTech. This board may host a variety of 64-pin AVR XMega - part. This port was specifically performed using the ATXmega384c3. - - See the MattairTech website for further information about the MT-DB-X3: - http://www.mattairtech.com/. - - NOTE: There is no port for the XMEGA in place as of this writing. At this - point in time, this README file is only a repository for pre-porting - information. It is not clear as of this writing whether there ever will - be a port to the MT-DB-X3 development board or not. - -Contents -======== - - - PIO Usage - - LEDs and Buttons - - Serial Console - - Configurations - -PIO Usage -========= - - PA0 CONN_P_10 pin 1, Aref via J34 - PA1 CONN_P_10 pin 2 - PA2 CONN_P_10 pin 3 - PA3 CONN_P_10 pin 4 - PA4 CONN_P_10 pin 5 - PA5 CONN_P_10 pin 6 - PA6 CONN_P_10 pin 7 - PA7 CONN_P_10 pin 8 - - PB0 CONN_P_10 pin 9, Aref via J25 - PB1 CONN_P_10 pin 10 - PB2 C4_LS CONN_P14 pin 5 - PB3 C4_LS CONN_P14 pin 5 - PB4 C4_LS CONN_P14 pin 5, Alt JTAG TMS - PB5 C4_LS CONN_P14 pin 5, Alt JTAG TDI - PB6 C4_LS CONN_P14 pin 5, Alt JTAG TCK - PB7 C4_LS CONN_P14 pin 5, Alt JTAG TDO, Voltage measurement via J15 - - PC0 C0_LS CONN_P14 pin 7 - PC1 C1_LS CONN_P14 pin 8 - PC2 C2_LS CONN_P14 pin 9 - PC3 C3_LS CONN_P14 pin 10 - PC4 C4_LS CONN_P14 pin 5, PDI/SPI Header pin 5 via J8 - PC5 C5_LS CONN_P14 pin 6, PDI/SPI Header pin 4 via J8 - PC6 C6_LS CONN_P14 pin 7, PDI/SPI Header pin 1 via J13 - PC7 C7_LS CONN_P14 pin 8, PDI/SPI Header pin 3 via J12 - - PD0 CONN_P14 pin 9 - PD1 CONN_P14 pin 10 - PD2 CONN_P14 pin 11 - PD3 CONN_P14 pin 12 - PD4 CONN_P14 pin 13 - PD5 CONN_P14 pin 14, TXB0103 Output Enable - PD6 CONN_P14 pin 12, USB D- - PD7 CONN_P14 pin 13, USB D+ - - PE0 CONN_P10 pin 1 - PE1 CONN_P10 pin 2 - PE2 CONN_P10 pin 3 - PE3 CONN_P10 pin 4 - PE4 CONN_P10 pin 5 - PE5 CONN_P10 pin 6 - PE6 CONN_P10 pin 7, TOSC1 via J28 - PE7 CONN_P10 pin 8, TOSC1 via J29 - - PF0 PORT F pin 1 - PF1 PORT F pin 2 - PF2 PORT F pin 3 - PF3 PORT F pin 4 - PF4 PORT F pin 5, Bootloader jumper - PF5 PORT F pin 6 - PF6 PORT F pin 7, Green LED via J31 - PF7 PORT F pin 8, User button via J33 (otherwise reset) - -LEDs and Buttons -================ - -Serial Console -============== - -Configurations -============== diff --git a/configs/mx1ads/ostest/defconfig b/configs/mx1ads/ostest/defconfig index 6c09f16ac809df55da16ecf38b114cd3154cec68..1ed8296f8d60f76e999305e910bc5dead262d544 100644 --- a/configs/mx1ads/ostest/defconfig +++ b/configs/mx1ads/ostest/defconfig @@ -692,7 +692,7 @@ CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/ntosd-dm320/nettest/defconfig b/configs/ntosd-dm320/nettest/defconfig index 560e82a279ee0899e450ea5d2347eaea9713e361..6cefdd76bbb13936c43fadc1432d5243f571cb39 100644 --- a/configs/ntosd-dm320/nettest/defconfig +++ b/configs/ntosd-dm320/nettest/defconfig @@ -829,7 +829,7 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/ntosd-dm320/nsh/defconfig b/configs/ntosd-dm320/nsh/defconfig index 7ec57fecca3cceeeafbc2e6d4ab1a4e5a0145437..91b26d4055a5892317b726f8f7ab870796f29704 100644 --- a/configs/ntosd-dm320/nsh/defconfig +++ b/configs/ntosd-dm320/nsh/defconfig @@ -1022,7 +1022,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/ntosd-dm320/poll/defconfig b/configs/ntosd-dm320/poll/defconfig index 4bf627a38a71440a48584c81bc2450e3a2df98bb..45e393b8e1f15e9c5f64829d13a94ea3eab6f13f 100644 --- a/configs/ntosd-dm320/poll/defconfig +++ b/configs/ntosd-dm320/poll/defconfig @@ -832,7 +832,7 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/ntosd-dm320/thttpd/defconfig b/configs/ntosd-dm320/thttpd/defconfig index 04dcca72bd4153bfca69447a8e8e58049adf38a3..e17efe6802f8f9160d644668d9b22fc3da37961a 100644 --- a/configs/ntosd-dm320/thttpd/defconfig +++ b/configs/ntosd-dm320/thttpd/defconfig @@ -872,7 +872,7 @@ CONFIG_THTTPD_TILDE_MAP_NONE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/ntosd-dm320/udp/defconfig b/configs/ntosd-dm320/udp/defconfig index 6b37219e6865fa3328e40e4d6409c15c9eef6f48..e6e82675dcb4e30190576a27ec6ba386b653e5e7 100644 --- a/configs/ntosd-dm320/udp/defconfig +++ b/configs/ntosd-dm320/udp/defconfig @@ -825,7 +825,7 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/ntosd-dm320/webserver/defconfig b/configs/ntosd-dm320/webserver/defconfig index dd23e42cf97ab0e57ac6126f62d2db423616144c..d3d1aecf5cdf18956fc0937482796628b16ae86f 100644 --- a/configs/ntosd-dm320/webserver/defconfig +++ b/configs/ntosd-dm320/webserver/defconfig @@ -839,7 +839,7 @@ CONFIG_NETUTILS_HTTPD_KEEPALIVE_DISABLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/nucleo-144/f746-evalos/defconfig b/configs/nucleo-144/f746-evalos/defconfig index e95085b7c84d3c95716185a2c3bf95c48c99ff71..7ca43debd2d1ce6b545913930b4717e4a4bde9a0 100644 --- a/configs/nucleo-144/f746-evalos/defconfig +++ b/configs/nucleo-144/f746-evalos/defconfig @@ -1035,7 +1035,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/nucleo-144/f746-nsh/defconfig b/configs/nucleo-144/f746-nsh/defconfig index d20123a2f0eb48814e5059d05106e012eda5f7ee..697bedb51adb327f04873e52c1755da09af557e6 100644 --- a/configs/nucleo-144/f746-nsh/defconfig +++ b/configs/nucleo-144/f746-nsh/defconfig @@ -1013,7 +1013,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/nucleo-144/f767-evalos/defconfig b/configs/nucleo-144/f767-evalos/defconfig index 6393ea7d181880d7ccbca6f4b129e9a0f2618032..767cdf7da9da47b6622ed759f59491da07210db5 100644 --- a/configs/nucleo-144/f767-evalos/defconfig +++ b/configs/nucleo-144/f767-evalos/defconfig @@ -1039,7 +1039,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/nucleo-144/f767-nsh/defconfig b/configs/nucleo-144/f767-nsh/defconfig index c7eb54a599951d19ebe92e62995dcb18aac7e499..b97dfe2d9af0498bd587b0da79fbf4640df793bf 100644 --- a/configs/nucleo-144/f767-nsh/defconfig +++ b/configs/nucleo-144/f767-nsh/defconfig @@ -1017,7 +1017,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/nucleo-144/include/board.h b/configs/nucleo-144/include/board.h index 1561ad8cc684fd01dedf968840914689fbdd28ad..18d2727502b5e859af1ba386e1250e23fe8c4199 100644 --- a/configs/nucleo-144/include/board.h +++ b/configs/nucleo-144/include/board.h @@ -127,8 +127,8 @@ #define CONFIG_STM32F7_PLLSAI 1 #define STM32_RCC_PLLSAICFGR_PLLSAIN RCC_PLLSAICFGR_PLLSAIN(192) -#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(2) -#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(2) +#define STM32_RCC_PLLSAICFGR_PLLSAIP RCC_PLLSAICFGR_PLLSAIP(8) +#define STM32_RCC_PLLSAICFGR_PLLSAIQ RCC_PLLSAICFGR_PLLSAIQ(4) #define STM32_RCC_PLLSAICFGR_PLLSAIR RCC_PLLSAICFGR_PLLSAIR(2) /* Configure Dedicated Clock Configuration Register */ @@ -167,7 +167,7 @@ #define STM32_RCC_DCKCFGR2_I2C4SRC RCC_DCKCFGR2_I2C4SEL_HSI #define STM32_RCC_DCKCFGR2_LPTIM1SRC RCC_DCKCFGR2_LPTIM1SEL_APB #define STM32_RCC_DCKCFGR2_CECSRC RCC_DCKCFGR2_CECSEL_HSI -#define STM32_RCC_DCKCFGR2_CK48MSRC RCC_DCKCFGR2_CK48MSEL_PLLSAI +#define STM32_RCC_DCKCFGR2_CK48MSRC RCC_DCKCFGR2_CK48MSEL_PLL #define STM32_RCC_DCKCFGR2_SDMMCSRC RCC_DCKCFGR2_SDMMCSEL_48MHZ #define STM32_RCC_DCKCFGR2_SDMMC2SRC RCC_DCKCFGR2_SDMMC2SEL_48MHZ #define STM32_RCC_DCKCFGR2_DSISRC RCC_DCKCFGR2_DSISEL_48MHZ @@ -216,6 +216,61 @@ #define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) #define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) +/* SDMMC dividers. Note that slower clocking is required when DMA is disabled + * in order to avoid RX overrun/TX underrun errors due to delayed responses + * to service FIFOs in interrupt driven mode. These values have not been + * tuned!!! + * + * SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(118+2)=400 KHz + */ + +#define STM32_SDMMC_INIT_CLKDIV (118 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) + +/* DMA ON: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(1+2)=16 MHz + * DMA OFF: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define STM32_SDMMC_MMCXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#else +# define STM32_SDMMC_MMCXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#endif + +/* DMA ON: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(1+2)=16 MHz + * DMA OFF: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(2+2)=12 MHz + */ + +#ifdef CONFIG_SDIO_DMA +# define STM32_SDMMC_SDXFR_CLKDIV (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#else +# define STM32_SDMMC_SDXFR_CLKDIV (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) +#endif + +#if defined(CONFIG_STM32F7_SDMMC2) +# define GPIO_SDMMC2_D0 GPIO_SDMMC2_D0_1 +# define GPIO_SDMMC2_D1 GPIO_SDMMC2_D1_1 +# define GPIO_SDMMC2_D2 GPIO_SDMMC2_D2_1 +# define GPIO_SDMMC2_D3 GPIO_SDMMC2_D3_1 +#endif +/* DMA Channl/Stream Selections *****************************************************/ +/* Stream selections are arbitrary for now but might become important in the future + * if we set aside more DMA channels/streams. + * + * SDMMC DMA is on DMA2 + * + * SDMMC1 DMA + * DMAMAP_SDMMC1_1 = Channel 4, Stream 3 + * DMAMAP_SDMMC1_2 = Channel 4, Stream 6 + * + * SDMMC2 DMA + * DMAMAP_SDMMC2_1 = Channel 11, Stream 0 + * DMAMAP_SDMMC3_2 = Channel 11, Stream 5 + */ + +#define DMAMAP_SDMMC1 DMAMAP_SDMMC1_1 +#define DMAMAP_SDMMC2 DMAMAP_SDMMC2_1 + + /* FLASH wait states * * --------- ---------- ----------- diff --git a/configs/nucleo-144/src/Makefile b/configs/nucleo-144/src/Makefile index e4e02750bd4f7fee4dd8b5dc9cb33f0d3ba3d6a9..846122801bb07ebee028cf57839ae6d9e6200b2d 100644 --- a/configs/nucleo-144/src/Makefile +++ b/configs/nucleo-144/src/Makefile @@ -60,8 +60,16 @@ ifeq ($(CONFIG_ADC),y) CSRCS += stm32_adc.c endif -ifeq ($(HAVE_SDIO),y) +ifeq ($(CONFIG_MMCSD),y) CSRCS += stm32_sdio.c endif +ifeq ($(CONFIG_STM32F7_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_STM32F7_BBSRAM),y) +CSRCS += stm32_bbsram.c +endif + include $(TOPDIR)/configs/Board.mk diff --git a/configs/nucleo-144/src/nucleo-144.h b/configs/nucleo-144/src/nucleo-144.h index 48a6f9f11a38c3ca19635b841a0f64a188517ec7..9b0e25cb4cd89d247542f82eae93e007f23694ba 100644 --- a/configs/nucleo-144/src/nucleo-144.h +++ b/configs/nucleo-144/src/nucleo-144.h @@ -128,8 +128,68 @@ #define NUCLEO_SPI_BUS3_CS2 10 #define NUCLEO_SPI_BUS3_CS3 11 -#if defined(CONFIG_STM32_SDIO) -#define GPIO_SDIO_NCD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI | GPIO_PORTB | GPIO_PIN15) +#if defined(CONFIG_STM32F7_SDMMC1) || defined(CONFIG_STM32F7_SDMMC2) +# define HAVE_SDIO +#endif + +#if defined(CONFIG_DISABLE_MOUNTPOINT) || !defined(CONFIG_MMCSD_SDIO) +# undef HAVE_SDIO +#endif + +#define SDIO_SLOTNO 0 /* Only one slot */ + +#ifdef HAVE_SDIO + +# if defined(CONFIG_STM32F7_SDMMC1) +# define GPIO_SDMMC1_NCD (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI | GPIO_PORTC | GPIO_PIN6) +# endif + +# if defined(CONFIG_NSH_MMCSDSLOTNO) && (CONFIG_NSH_MMCSDSLOTNO != 0) +# warning "Only one MMC/SD slot, slot 0" +# define CONFIG_NSH_MMCSDSLOTNO SDIO_SLOTNO +# endif + +# if defined(CONFIG_NSH_MMCSDMINOR) +# define SDIO_MINOR CONFIG_NSH_MMCSDMINOR +# else +# define SDIO_MINOR 0 +# endif + + /* SD card bringup does not work if performed on the IDLE thread because it + * will cause waiting. Use either: + * + * CONFIG_LIB_BOARDCTL=y, OR + * CONFIG_BOARD_INITIALIZE=y && CONFIG_BOARD_INITTHREAD=y + */ + +# if defined(CONFIG_BOARD_INITIALIZE) && !defined(CONFIG_LIB_BOARDCTL) && \ + !defined(CONFIG_BOARD_INITTHREAD) +# warning SDIO initialization cannot be perfomed on the IDLE thread +# undef HAVE_SDIO +# endif +#endif + +/* USB OTG FS + * + * PA9 OTG_FS_VBUS VBUS sensing (also connected to the green LED) + * PC0 OTG_FS_PowerSwitchOn + * PD5 OTG_FS_Overcurrent + */ + +#define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|\ + GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9) + +#define GPIO_OTGFS_PWRON (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|\ + GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN6) + +#ifdef CONFIG_USBHOST +# define GPIO_OTGFS_OVER (GPIO_INPUT|GPIO_EXTI|GPIO_FLOAT|\ + GPIO_SPEED_100MHz|GPIO_PUSHPULL|\ + GPIO_PORTG|GPIO_PIN7) + +#else +# define GPIO_OTGFS_OVER (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|\ + GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN7) #endif /************************************************************************************ @@ -196,5 +256,38 @@ int stm32_dma_alloc_init(void); int board_adc_initialize(void); #endif +/**************************************************************************** + * Name: stm32_sdio_initialize + * + * Description: + * Called at application startup time to initialize the SCMMC functionality. + * + ****************************************************************************/ + +#ifdef CONFIG_MMCSD +int stm32_sdio_initialize(void); +#endif + +/************************************************************************************ + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in inialization to setup USB-related + * GPIO pins for the nucleo-144 board. + * + ************************************************************************************/ + +#ifdef CONFIG_STM32F7_OTGFS +void stm32_usbinitialize(void); +#endif + +/************************************************************************************ + * Name: stm32_bbsram_int + ************************************************************************************/ + +#ifdef CONFIG_STM32F7_BBSRAM +int stm32_bbsram_int(void); +#endif + #endif /* __ASSEMBLY__ */ #endif /* __CONFIGS_NUCLEO_144_SRC_NUCLEO_144_H */ diff --git a/configs/nucleo-144/src/stm32_appinitialize.c b/configs/nucleo-144/src/stm32_appinitialize.c index 9daf02a3ff050f54abe88ade5290afeff7a6aa36..837048b5a1a8ab431c8bdc91656ddf343bc51d59 100644 --- a/configs/nucleo-144/src/stm32_appinitialize.c +++ b/configs/nucleo-144/src/stm32_appinitialize.c @@ -42,6 +42,7 @@ #include #include +#include #include #include "nucleo-144.h" @@ -101,6 +102,12 @@ int board_app_initialize(uintptr_t arg) } #endif +#ifdef CONFIG_STM32F7_BBSRAM + /* Initialize battery-backed RAM */ + + (void)stm32_bbsram_int(); +#endif + #if defined(CONFIG_FAT_DMAMEMORY) if (stm32_dma_alloc_init() < 0) { diff --git a/configs/nucleo-144/src/stm32_autoleds.c b/configs/nucleo-144/src/stm32_autoleds.c index 64c3cccb8c0de7eb7045be38f6c4882d899db78d..cf44384630939778a8d08c401862966efc75b43a 100644 --- a/configs/nucleo-144/src/stm32_autoleds.c +++ b/configs/nucleo-144/src/stm32_autoleds.c @@ -54,7 +54,7 @@ * Pre-processor Definitions ****************************************************************************/ -#define ArraySize(x) (sizeof((x)) / sizeof((x)[0])) +#define ARRAYSIZE(x) (sizeof((x)) / sizeof((x)[0])) /**************************************************************************** * Private Data @@ -96,7 +96,7 @@ void board_autoled_initialize(void) /* Configure the LD1 GPIO for output. Initial state is OFF */ - for (i = 0; i < ArraySize(g_ledmap); i++) + for (i = 0; i < ARRAYSIZE(g_ledmap); i++) { stm32_configgpio(g_ledmap[i]); } diff --git a/configs/nucleo-144/src/stm32_bbsram.c b/configs/nucleo-144/src/stm32_bbsram.c new file mode 100644 index 0000000000000000000000000000000000000000..085ee1824922fa08472c8974ac67762de4c51616 --- /dev/null +++ b/configs/nucleo-144/src/stm32_bbsram.c @@ -0,0 +1,556 @@ +/**************************************************************************** + * configs/nucleo-144/src/stm32_bbsram.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include "nucleo-144.h" + +#ifdef CONFIG_STM32F7_BBSRAM + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define FREEZE_STR(s) #s +#define STRINGIFY(s) FREEZE_STR(s) +#define HARDFAULT_FILENO 3 +#define HARDFAULT_PATH BBSRAM_PATH""STRINGIFY(HARDFAULT_FILENO) +#define HARDFAULT_REBOOT_ FILENO 0 +#define HARDFAULT_REBOOT_PATH BBSRAM_PATH""STRINGIFY(HARDFAULT_REBOOT_FILENO) + +#define BBSRAM_SIZE_FN0 (sizeof(int)) +#define BBSRAM_SIZE_FN1 384 +#define BBSRAM_SIZE_FN2 384 +#define BBSRAM_SIZE_FN3 - 1 + +/* The following guides in the amount of the user and interrupt stack + * data we can save. The amount of storage left will dictate the actual + * number of entries of the user stack data saved. If it is too big + * It will be truncated by the call to stm32_bbsram_savepanic + */ +#define BBSRAM_HEADER_SIZE 20 /* This is an assumption */ +#define BBSRAM_USED ((4*BBSRAM_HEADER_SIZE)+ \ + (BBSRAM_SIZE_FN0+BBSRAM_SIZE_FN1+ \ + BBSRAM_SIZE_FN2)) +#define BBSRAM_REAMINING (STM32F7_BBSRAM_SIZE-BBSRAM_USED) +#if CONFIG_ARCH_INTERRUPTSTACK <= 3 +# define BBSRAM_NUMBER_STACKS 1 +#else +# define BBSRAM_NUMBER_STACKS 2 +#endif +#define BBSRAM_FIXED_ELEMENTS_SIZE (sizeof(info_t)) +#define BBSRAM_LEFTOVER (BBSRAM_REAMINING-\ + BBSRAM_FIXED_ELEMENTS_SIZE) + +#define CONFIG_ISTACK_SIZE (BBSRAM_LEFTOVER/BBSRAM_NUMBER_STACKS/ \ + sizeof(stack_word_t)) +#define CONFIG_USTACK_SIZE (BBSRAM_LEFTOVER/BBSRAM_NUMBER_STACKS/ \ + sizeof(stack_word_t)) + +/* The path to the Battery Backed up SRAM */ + +#define BBSRAM_PATH "/fs/bbr" + +/* The sizes of the files to create (-1) use rest of BBSRAM memory */ + +#define BSRAM_FILE_SIZES \ +{ \ + BBSRAM_SIZE_FN0, \ + BBSRAM_SIZE_FN1, \ + BBSRAM_SIZE_FN2, \ + BBSRAM_SIZE_FN3, \ + 0 \ +} + +#define ARRAYSIZE(a) (sizeof((a))/sizeof(a[0])) + +/* For Assert keep this much of the file name*/ + +#define MAX_FILE_PATH_LENGTH 40 + +#define HEADER_TIME_FMT "%Y-%m-%d-%H:%M:%S" +#define HEADER_TIME_FMT_NUM (2+ 0+ 0+ 0+ 0+ 0) +#define HEADER_TIME_FMT_LEN (((ARRAYSIZE(HEADER_TIME_FMT)-1) + \ + HEADER_TIME_FMT_NUM)) + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* Used for stack frame storage */ + +typedef uint32_t stack_word_t; + +/* Stack related data */ + +typedef struct +{ + uint32_t sp; + uint32_t top; + uint32_t size; + +} _stack_t; + +typedef struct +{ + _stack_t user; +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + _stack_t interrupt; +#endif +} stack_t; + +/* Not Used for reference only */ + +typedef struct +{ + uint32_t r0; + uint32_t r1; + uint32_t r2; + uint32_t r3; + uint32_t r4; + uint32_t r5; + uint32_t r6; + uint32_t r7; + uint32_t r8; + uint32_t r9; + uint32_t r10; + uint32_t r11; + uint32_t r12; + uint32_t sp; + uint32_t lr; + uint32_t pc; + uint32_t xpsr; + uint32_t d0; + uint32_t d1; + uint32_t d2; + uint32_t d3; + uint32_t d4; + uint32_t d5; + uint32_t d6; + uint32_t d7; + uint32_t d8; + uint32_t d9; + uint32_t d10; + uint32_t d11; + uint32_t d12; + uint32_t d13; + uint32_t d14; + uint32_t d15; + uint32_t fpscr; + uint32_t sp_main; + uint32_t sp_process; + uint32_t apsr; + uint32_t ipsr; + uint32_t epsr; + uint32_t primask; + uint32_t basepri; + uint32_t faultmask; + uint32_t control; + uint32_t s0; + uint32_t s1; + uint32_t s2; + uint32_t s3; + uint32_t s4; + uint32_t s5; + uint32_t s6; + uint32_t s7; + uint32_t s8; + uint32_t s9; + uint32_t s10; + uint32_t s11; + uint32_t s12; + uint32_t s13; + uint32_t s14; + uint32_t s15; + uint32_t s16; + uint32_t s17; + uint32_t s18; + uint32_t s19; + uint32_t s20; + uint32_t s21; + uint32_t s22; + uint32_t s23; + uint32_t s24; + uint32_t s25; + uint32_t s26; + uint32_t s27; + uint32_t s28; + uint32_t s29; + uint32_t s30; + uint32_t s31; +} proc_regs_t; + +/* Flags to identify what is in the dump */ + +typedef enum +{ + REGS_PRESENT = 0x01, + USERSTACK_PRESENT = 0x02, + INTSTACK_PRESENT = 0x04, + INVALID_USERSTACK_PTR = 0x20, + INVALID_INTSTACK_PTR = 0x40, +} fault_flags_t; + +typedef struct +{ + fault_flags_t flags; /* What is in the dump */ + uintptr_t current_regs; /* Used to validate the dump */ + int lineno; /* __LINE__ to up_assert */ + int pid; /* Process ID */ + uint32_t regs[XCPTCONTEXT_REGS]; /* Interrupt register save area */ + stack_t stacks; /* Stack info */ +#if CONFIG_TASK_NAME_SIZE > 0 + char name[CONFIG_TASK_NAME_SIZE + 1]; /* Task name (with NULL + * terminator) */ +#endif + char filename[MAX_FILE_PATH_LENGTH]; /* the Last of chars in + * __FILE__ to up_assert */ +} info_t; + +typedef struct +{ + info_t info; /* The info */ +#if CONFIG_ARCH_INTERRUPTSTACK > 3 /* The amount of stack data is compile time + * sized backed on what is left after the + * other BBSRAM files are defined + * The order is such that only the + * ustack should be truncated + */ + stack_word_t istack[CONFIG_USTACK_SIZE]; +#endif + stack_word_t ustack[CONFIG_ISTACK_SIZE]; +} fullcontext_t; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static uint8_t g_sdata[STM32F7_BBSRAM_SIZE]; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: hardfault_get_desc + ****************************************************************************/ + +static int hardfault_get_desc(struct bbsramd_s *desc) +{ + int ret = -ENOENT; + int fd = open(HARDFAULT_PATH, O_RDONLY); + int rv; + + if (fd < 0) + { + syslog(LOG_INFO, "stm32 bbsram: Failed to open Fault Log file [%s] " + "(%d)\n", HARDFAULT_PATH, fd); + } + else + { + ret = -EIO; + rv = ioctl(fd, STM32F7_BBSRAM_GETDESC_IOCTL, + (unsigned long)((uintptr_t)desc)); + + if (rv >= 0) + { + ret = fd; + } + else + { + syslog(LOG_INFO, "stm32 bbsram: Failed to get Fault Log descriptor " + "(%d)\n", rv); + } + } + + return ret; +} + +/**************************************************************************** + * Name: copy_reverse + ****************************************************************************/ + +#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size) +{ + while (size--) + { + *dest++ = *src--; + } +} +#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_bbsram_int + ****************************************************************************/ + +int stm32_bbsram_int(void) +{ + int filesizes[CONFIG_STM32F7_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES; + char buf[HEADER_TIME_FMT_LEN + 1]; + struct bbsramd_s desc; + int rv; + int state; + struct tm tt; + time_t time_sec; + + + /* Using Battery Backed Up SRAM */ + + stm32_bbsraminitialize(BBSRAM_PATH, filesizes); + +#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) + /* Panic Logging in Battery Backed Up Files */ + /* Do we have an hard fault in BBSRAM? */ + + rv = hardfault_get_desc(&desc); + if (rv >= OK) + { + printf("There is a hard fault logged.\n"); + state = (desc.lastwrite.tv_sec || desc.lastwrite.tv_nsec) ? OK : 1; + + syslog(LOG_INFO, "Fault Log info File No %d Length %d flags:0x%02x " + "state:%d\n",(unsigned int)desc.fileno, (unsigned int) desc.len, + (unsigned int)desc.flags, state); + + if (state == OK) + { + time_sec = desc.lastwrite.tv_sec + (desc.lastwrite.tv_nsec / 1e9); + gmtime_r(&time_sec, &tt); + strftime(buf, HEADER_TIME_FMT_LEN , HEADER_TIME_FMT , &tt); + + syslog(LOG_INFO, "Fault Logged on %s - Valid\n", buf); + } + + close(rv); + rv = unlink(HARDFAULT_PATH); + if (rv < 0) + { + syslog(LOG_INFO, "stm32 bbsram: Failed to unlink Fault Log file [%s" + "] (%d)\n", HARDFAULT_PATH, rv); + } + } +#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ + + return rv; +} + +/**************************************************************************** + * Name: board_crashdump + ****************************************************************************/ + +#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP) +void board_crashdump(uintptr_t currentsp, FAR void *tcb, + FAR const uint8_t *filename, int lineno) +{ + fullcontext_t *pdump = (fullcontext_t *)&g_sdata; + FAR struct tcb_s *rtcb; + int rv; + + (void)enter_critical_section(); + + rtcb = (FAR struct tcb_s *)tcb; + + /* Zero out everything */ + + memset(pdump, 0, sizeof(fullcontext_t)); + + /* Save Info */ + + pdump->info.lineno = lineno; + + if (filename) + { + int offset = 0; + unsigned int len = strlen((char *)filename) + 1; + + if (len > sizeof(pdump->info.filename)) + { + offset = len - sizeof(pdump->info.filename); + } + + strncpy(pdump->info.filename, (char *)&filename[offset], + sizeof(pdump->info.filename)); + } + + /* Save the value of the pointer for current_regs as debugging info. + * It should be NULL in case of an ASSERT and will aid in cross + * checking the validity of system memory at the time of the + * fault. + */ + + pdump->info.current_regs = (uintptr_t) CURRENT_REGS; + + /* Save Context */ + +#if CONFIG_TASK_NAME_SIZE > 0 + strncpy(pdump->info.name, rtcb->name, CONFIG_TASK_NAME_SIZE); +#endif + + pdump->info.pid = rtcb->pid; + + /* If current_regs is not NULL then we are in an interrupt context + * and the user context is in current_regs else we are running in + * the users context + */ + + if (CURRENT_REGS) + { + pdump->info.stacks.interrupt.sp = currentsp; + pdump->info.flags |= (REGS_PRESENT | USERSTACK_PRESENT | \ + INTSTACK_PRESENT); + memcpy(pdump->info.regs, (void *)CURRENT_REGS, + sizeof(pdump->info.regs)); + pdump->info.stacks.user.sp = pdump->info.regs[REG_R13]; + } + else + { + /* users context */ + + pdump->info.flags |= USERSTACK_PRESENT; + pdump->info.stacks.user.sp = currentsp; + } + + if (pdump->info.pid == 0) + { + pdump->info.stacks.user.top = g_idle_topstack - 4; + pdump->info.stacks.user.size = CONFIG_IDLETHREAD_STACKSIZE; + } + else + { + pdump->info.stacks.user.top = (uint32_t) rtcb->adj_stack_ptr; + pdump->info.stacks.user.size = (uint32_t) rtcb->adj_stack_size; + } + +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + /* Get the limits on the interrupt stack memory */ + + pdump->info.stacks.interrupt.top = (uint32_t)&g_intstackbase; + pdump->info.stacks.interrupt.size = (CONFIG_ARCH_INTERRUPTSTACK & ~3); + + /* If In interrupt Context save the interrupt stack data centered + * about the interrupt stack pointer + */ + + if ((pdump->info.flags & INTSTACK_PRESENT) != 0) + { + stack_word_t *ps = (stack_word_t *) pdump->info.stacks.interrupt.sp; + copy_reverse(pdump->istack, &ps[ARRAYSIZE(pdump->istack) / 2], + ARRAYSIZE(pdump->istack)); + } + + /* Is it Invalid? */ + + if (!(pdump->info.stacks.interrupt.sp <= pdump->info.stacks.interrupt.top && + pdump->info.stacks.interrupt.sp > pdump->info.stacks.interrupt.top - + pdump->info.stacks.interrupt.size)) + { + pdump->info.flags |= INVALID_INTSTACK_PTR; + } + +#endif + /* If In interrupt context or User save the user stack data centered + * about the user stack pointer + */ + + if ((pdump->info.flags & USERSTACK_PRESENT) != 0) + { + stack_word_t *ps = (stack_word_t *) pdump->info.stacks.user.sp; + copy_reverse(pdump->ustack, &ps[ARRAYSIZE(pdump->ustack) / 2], + ARRAYSIZE(pdump->ustack)); + } + + /* Is it Invalid? */ + + if (!(pdump->info.stacks.user.sp <= pdump->info.stacks.user.top && + pdump->info.stacks.user.sp > pdump->info.stacks.user.top - + pdump->info.stacks.user.size)) + { + pdump->info.flags |= INVALID_USERSTACK_PTR; + } + + rv = stm32_bbsram_savepanic(HARDFAULT_FILENO, (uint8_t *)pdump, + sizeof(fullcontext_t)); + + /* Test if memory got wiped because of using _sdata */ + + if (rv == -ENXIO) + { + char *dead = "Memory wiped - dump not saved!"; + + while (*dead) + { + up_lowputc(*dead++); + } + } + else if (rv == -ENOSPC) + { + /* hard fault again */ + + up_lowputc('!'); + } + +#if defined(CONFIG_BOARD_RESET_ON_CRASH) + up_systemreset(); +#endif +} +#endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */ + +#endif /* CONFIG_STM32_BBSRAM */ diff --git a/configs/nucleo-144/src/stm32_boot.c b/configs/nucleo-144/src/stm32_boot.c index 6e767a2975f212840b71efc9ce0b7ea0f3566cae..684ade81767bc44fb1a36e80fc8ddcb1cbee9ae3 100644 --- a/configs/nucleo-144/src/stm32_boot.c +++ b/configs/nucleo-144/src/stm32_boot.c @@ -70,6 +70,10 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif +#if defined(CONFIG_STM32F7_OTGFS) || defined(CONFIG_STM32F7_HOST) + stm32_usbinitialize(); +#endif + #if defined(CONFIG_SPI) /* Configure SPI chip selects */ diff --git a/configs/nucleo-144/src/stm32_buttons.c b/configs/nucleo-144/src/stm32_buttons.c index c2d16e50b1b628b9e15cc99a214b19ae8b86dc12..ff0e64d76425e8b7d2f9b9b8d1610d4b1e81abd7 100644 --- a/configs/nucleo-144/src/stm32_buttons.c +++ b/configs/nucleo-144/src/stm32_buttons.c @@ -40,9 +40,13 @@ #include +#include + #include #include +#include + #include "stm32_gpio.h" #include "nucleo-144.h" diff --git a/configs/nucleo-144/src/stm32_sdio.c b/configs/nucleo-144/src/stm32_sdio.c index 87b316be2e062fc8a318e53a7901d057dd67376b..7904f8c2ebafe2fd6e40c491abec01f519a8eccb 100644 --- a/configs/nucleo-144/src/stm32_sdio.c +++ b/configs/nucleo-144/src/stm32_sdio.c @@ -47,10 +47,13 @@ #include #include -#include "stm32.h" +#include "chip.h" #include "nucleo-144.h" +#include "stm32_gpio.h" +#include "stm32_sdmmc.h" + +#ifdef CONFIG_MMCSD -#ifdef HAVE_SDIO /**************************************************************************** * Pre-processor Definitions @@ -61,7 +64,7 @@ /* Card detections requires card support and a card detection GPIO */ #define HAVE_NCD 1 -#if !defined(CONFIG_STM32_SDIO) || !defined(GPIO_SDIO_NCD) +#if !defined(GPIO_SDMMC1_NCD) # undef HAVE_NCD #endif @@ -91,8 +94,8 @@ static int stm32_ncd_interrupt(int irq, FAR void *context) { bool present; - present = !stm32_gpioread(GPIO_SDIO_NCD); - if (present != g_sd_inserted) + present = !stm32_gpioread(GPIO_SDMMC1_NCD); + if (g_sdio_dev && present != g_sd_inserted) { sdio_mediachange(g_sdio_dev, present); g_sd_inserted = present; @@ -125,11 +128,11 @@ int stm32_sdio_initialize(void) /* Configure the card detect GPIO */ - stm32_configgpio(GPIO_SDIO_NCD); + stm32_configgpio(GPIO_SDMMC1_NCD); /* Register an interrupt handler for the card detect pin */ - stm32_gpiosetevent(GPIO_SDIO_NCD, true, true, true, stm32_ncd_interrupt); + stm32_gpiosetevent(GPIO_SDMMC1_NCD, true, true, true, stm32_ncd_interrupt); #endif /* Mount the SDIO-based MMC/SD block driver */ @@ -160,7 +163,7 @@ int stm32_sdio_initialize(void) #ifdef HAVE_NCD /* Use SD card detect pin to check if a card is g_sd_inserted */ - cd_status = !stm32_gpioread(GPIO_SDIO_NCD); + cd_status = !stm32_gpioread(GPIO_SDMMC1_NCD); finfo("Card detect : %d\n", cd_status); sdio_mediachange(g_sdio_dev, cd_status); diff --git a/configs/nucleo-144/src/stm32_spi.c b/configs/nucleo-144/src/stm32_spi.c index 9a1f28a94e2493c562ffd06712f912620dbefe68..61dab7a51ee3dbdbe4370eb30abcad8fe2e1b469 100644 --- a/configs/nucleo-144/src/stm32_spi.c +++ b/configs/nucleo-144/src/stm32_spi.c @@ -61,7 +61,7 @@ * Pre-processor Definitions ************************************************************************************/ -#define ArraySize(x) (sizeof((x)) / sizeof((x)[0])) +#define ARRAYSIZE(x) (sizeof((x)) / sizeof((x)[0])) #if defined(CONFIG_NUCLEO_SPI1_TEST) # if defined(CONFIG_NUCLEO_SPI1_TEST_MODE0) @@ -181,7 +181,7 @@ void weak_function stm32_spidev_initialize(void) /* Configure SPI CS GPIO for output */ - for (i = 0; i < ArraySize(g_spigpio); i++) + for (i = 0; i < ARRAYSIZE(g_spigpio); i++) { stm32_configgpio(g_spigpio[i]); } @@ -390,7 +390,7 @@ int stm32_spidev_bus_test(void) SPI_SETFREQUENCY(spi1, CONFIG_NUCLEO_SPI1_TEST_FREQ); SPI_SETBITS(spi1, CONFIG_NUCLEO_SPI1_TEST_BITS); SPI_SETMODE(spi1, CONFIG_NUCLEO_SPI1_TEST_MODE); - SPI_EXCHANGE(spi1, tx, NULL, ArraySize(CONFIG_NUCLEO_SPI_TEST_MESSAGE)); + SPI_EXCHANGE(spi1, tx, NULL, ARRAYSIZE(CONFIG_NUCLEO_SPI_TEST_MESSAGE)); #endif #if defined(CONFIG_NUCLEO_SPI2_TEST) @@ -407,7 +407,7 @@ int stm32_spidev_bus_test(void) SPI_SETFREQUENCY(spi2, CONFIG_NUCLEO_SPI2_TEST_FREQ); SPI_SETBITS(spi2, CONFIG_NUCLEO_SPI2_TEST_BITS); SPI_SETMODE(spi2, CONFIG_NUCLEO_SPI2_TEST_MODE); - SPI_EXCHANGE(spi2, tx, NULL, ArraySize(CONFIG_NUCLEO_SPI_TEST_MESSAGE)); + SPI_EXCHANGE(spi2, tx, NULL, ARRAYSIZE(CONFIG_NUCLEO_SPI_TEST_MESSAGE)); #endif #if defined(CONFIG_NUCLEO_SPI3_TEST) @@ -424,7 +424,7 @@ int stm32_spidev_bus_test(void) SPI_SETFREQUENCY(spi3, CONFIG_NUCLEO_SPI3_TEST_FREQ); SPI_SETBITS(spi3, CONFIG_NUCLEO_SPI3_TEST_BITS); SPI_SETMODE(spi3, CONFIG_NUCLEO_SPI3_TEST_MODE); - SPI_EXCHANGE(spi3, tx, NULL, ArraySize(CONFIG_NUCLEO_SPI_TEST_MESSAGE)); + SPI_EXCHANGE(spi3, tx, NULL, ARRAYSIZE(CONFIG_NUCLEO_SPI_TEST_MESSAGE)); #endif return OK; diff --git a/configs/nucleo-144/src/stm32_usb.c b/configs/nucleo-144/src/stm32_usb.c new file mode 100644 index 0000000000000000000000000000000000000000..1cb422a78c4bc9d43c60d12ae4347079bd23b310 --- /dev/null +++ b/configs/nucleo-144/src/stm32_usb.c @@ -0,0 +1,329 @@ +/************************************************************************************ + * configs//nucleo-144/src/stm32_usb.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * David Sidrane + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "up_arch.h" +#include "chip.h" +#include "stm32_gpio.h" +#include "stm32_otg.h" +#include "nucleo-144.h" + +#ifdef CONFIG_STM32F7_OTGFS + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_NUCLEO144_USBHOST_PRIO +# define CONFIG_NUCLEO144_USBHOST_PRIO 100 +#endif + +#ifndef CONFIG_NUCLEO_USBHOST_STACKSIZE +# define CONFIG_NUCLEO_USBHOST_STACKSIZE 1024 +#endif + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ************************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (;;) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + (void)CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in inialization to setup USB-related + * GPIO pins for the nucleo-144 board. + * + ************************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. No GPIO configuration is required */ + + /* Configure the OTG FS VBUS sensing GPIO, Power On, and Overcurrent GPIOs */ + +#ifdef CONFIG_STM32F7_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/*********************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host functionality. + * This function will start a thread that will monitor for device + * connection/disconnection events. + * + ***********************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int pid; +#if defined(CONFIG_USBHOST_HUB) || defined(CONFIG_USBHOST_MSC) || \ + defined(CONFIG_USBHOST_HIDKBD) || defined(CONFIG_USBHOST_HIDMOUSE) + int ret; +#endif + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uinfo("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_HIDKBD + /* Initialize the HID keyboard class */ + + ret = usbhost_kbdinit(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID keyboard class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_HIDMOUSE + /* Initialize the HID mouse class */ + + ret = usbhost_mouse_init(); + if (ret != OK) + { + uerr("ERROR: Failed to register the HID mouse class\n"); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + pid = task_create("usbhost", CONFIG_STM32F4DISCO_USBHOST_PRIO, + CONFIG_STM32F4DISCO_USBHOST_STACKSIZE, + (main_t)usbhost_waiter, (FAR char * const *)NULL); + return pid < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/*********************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be provided be + * each platform that implements the STM32 OTG FS host interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a charge pump + * or, if 5 V are available on the application board, a basic power switch, must + * be added externally to drive the 5 V VBUS line. The external charge pump can + * be driven by any GPIO output. When the application decides to power on VBUS + * using the chosen GPIO, it must also set the port power bit in the host port + * control and status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, and the core + * clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ***********************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + /* Set the Power Switch by driving the active low enable pin */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, !enable); +} +#endif + +/************************************************************************************ + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent condition is + * detected. + * + * Input Parameter: + * handler - New overcurrent interrupt handler + * + * Returned value: + * Old overcurrent interrupt handler + * + ************************************************************************************/ + +#ifdef CONFIG_USBHOST +xcpt_t stm32_setup_overcurrent(xcpt_t handler) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler); +} +#endif + +/************************************************************************************ + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver is + * used. This function is called whenever the USB enters or leaves suspend mode. + * This is an opportunity for the board logic to shutdown clocks, power, etc. + * while the USB is suspended. + * + ************************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/configs/nucleo-144/src/stm32_userleds.c b/configs/nucleo-144/src/stm32_userleds.c index a5dfaea3e7b8285f3196f051c459722d3dc10acb..53e8f809dba25e232ce11cc861a7893ba8b29b16 100644 --- a/configs/nucleo-144/src/stm32_userleds.c +++ b/configs/nucleo-144/src/stm32_userleds.c @@ -56,7 +56,7 @@ * Pre-processor Definitions ****************************************************************************/ -#define ArraySize(x) (sizeof((x)) / sizeof((x)[0])) +#define ARRAYSIZE(x) (sizeof((x)) / sizeof((x)[0])) /**************************************************************************** * Private Data @@ -94,7 +94,7 @@ void board_userled_initialize(void) /* Configure LED1-3 GPIOs for output */ - for (i = 0; i < ArraySize(g_ledcfg); i++) + for (i = 0; i < ARRAYSIZE(g_ledcfg); i++) { stm32_configgpio(g_ledcfg[i]); } @@ -112,7 +112,7 @@ void board_userled_initialize(void) void board_userled(int led, bool ledon) { - if ((unsigned)led < ArraySize(g_ledcfg)) + if ((unsigned)led < ARRAYSIZE(g_ledcfg)) { stm32_gpiowrite(g_ledcfg[led], ledon); } @@ -135,7 +135,7 @@ void board_userled_all(uint8_t ledset) /* Configure LED1-3 GPIOs for output */ - for (i = 0; i < ArraySize(g_ledcfg); i++) + for (i = 0; i < ARRAYSIZE(g_ledcfg); i++) { stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)) != 0); } diff --git a/configs/nucleo-f303re/adc/defconfig b/configs/nucleo-f303re/adc/defconfig index d8aeb57c2879ae8c4068c21489cd00a1a5bffc19..e66c60de332d22f7bc8b695ab7b9be41c9be0b6e 100644 --- a/configs/nucleo-f303re/adc/defconfig +++ b/configs/nucleo-f303re/adc/defconfig @@ -962,7 +962,7 @@ CONFIG_EXAMPLES_ADC_SWTRIG=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/nucleo-f303re/can/defconfig b/configs/nucleo-f303re/can/defconfig index d25a894c12e261d5965a0665b31c20cadf34d5c2..c19a6a4487f5c3b0c7fcaa886fba3a8c26f1d5e2 100644 --- a/configs/nucleo-f303re/can/defconfig +++ b/configs/nucleo-f303re/can/defconfig @@ -964,7 +964,7 @@ CONFIG_EXAMPLES_CAN_READWRITE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/nucleo-f303re/nxlines/defconfig b/configs/nucleo-f303re/nxlines/defconfig index aa42977bb4d476be9b51540c9fdcb61e77edd075..ef5f106ef25603564124ed99d3a9741cfda00962 100644 --- a/configs/nucleo-f303re/nxlines/defconfig +++ b/configs/nucleo-f303re/nxlines/defconfig @@ -1121,7 +1121,7 @@ CONFIG_EXAMPLES_NXLINES_EXTERNINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/nucleo-f303re/pwm/defconfig b/configs/nucleo-f303re/pwm/defconfig index bb9fdd51789360732f5cc70596c866bcdf674eec..677e6672687d9927eb65cec80344a7ee2db6aa36 100644 --- a/configs/nucleo-f303re/pwm/defconfig +++ b/configs/nucleo-f303re/pwm/defconfig @@ -1068,7 +1068,7 @@ CONFIG_SYSTEM_CLE=y CONFIG_SYSTEM_CLE_DEBUGLEVEL=0 # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/nucleo-f303re/serialrx/defconfig b/configs/nucleo-f303re/serialrx/defconfig index e758d84d1fc50c08c09edbaddab778516e413a8d..117e0db9985c41017cb102c7cb7cdad799489e2e 100644 --- a/configs/nucleo-f303re/serialrx/defconfig +++ b/configs/nucleo-f303re/serialrx/defconfig @@ -1028,7 +1028,7 @@ CONFIG_EXAMPLES_SERIALRX_PRINTSTR=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/nucleo-f303re/uavcan/defconfig b/configs/nucleo-f303re/uavcan/defconfig index 9dd992e89d9d59133371c8c4da8a8cc2437f100c..f85d04410b91bddc97bff1cafe4e1c23b273b409 100644 --- a/configs/nucleo-f303re/uavcan/defconfig +++ b/configs/nucleo-f303re/uavcan/defconfig @@ -979,7 +979,7 @@ CONFIG_EXAMPLES_UAVCAN_NODE_NAME="org.nuttx.apps.examples.uavcan" # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/nucleo-f4x1re/f401-nsh/defconfig b/configs/nucleo-f4x1re/f401-nsh/defconfig index e52ef7184c6f5d31f78e1477e3ed701676a3973b..75cc5e9964565f721e23c0e95e46e751e9f4012d 100644 --- a/configs/nucleo-f4x1re/f401-nsh/defconfig +++ b/configs/nucleo-f4x1re/f401-nsh/defconfig @@ -1120,7 +1120,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/nucleo-f4x1re/f411-nsh/defconfig b/configs/nucleo-f4x1re/f411-nsh/defconfig index fa44765d45e30d9613797a5e116daa60d34897d9..3a0fd7511a4e3be4f14e77c55e5e5113b50b4839 100644 --- a/configs/nucleo-f4x1re/f411-nsh/defconfig +++ b/configs/nucleo-f4x1re/f411-nsh/defconfig @@ -1122,7 +1122,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/nucleo-f4x1re/src/stm32_ajoystick.c b/configs/nucleo-f4x1re/src/stm32_ajoystick.c index 432d91667b4a42286a14847af56f9085a23aab37..a40f08f4b0340ad52c6a1c943d816c6c2ab9560f 100644 --- a/configs/nucleo-f4x1re/src/stm32_ajoystick.c +++ b/configs/nucleo-f4x1re/src/stm32_ajoystick.c @@ -206,7 +206,8 @@ static int ajoy_sample(FAR const struct ajoy_lowerhalf_s *lower, * channels are enabled). */ - nread = file_read(&g_adcfile, adcmsg, MAX_ADC_CHANNELS * sizeof(struct adc_msg_s)); + nread = file_read(&g_adcfile, adcmsg, + MAX_ADC_CHANNELS * sizeof(struct adc_msg_s)); if (nread < 0) { int errcode = get_errno(); diff --git a/configs/nucleo-l476rg/nsh/defconfig b/configs/nucleo-l476rg/nsh/defconfig index 4556a51c97e79ff2d37a1a1d0512b1246df582eb..968758596e55e687b0e5e0cb6d2e7cbe777ccfc6 100644 --- a/configs/nucleo-l476rg/nsh/defconfig +++ b/configs/nucleo-l476rg/nsh/defconfig @@ -992,7 +992,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/nucleo-l476rg/src/stm32_ajoystick.c b/configs/nucleo-l476rg/src/stm32_ajoystick.c index 6f49fd9823d2f3940b508cfcf2ef550a8a8ff690..71a61ef417ab970c5847ca5b57ef3def44555cb0 100644 --- a/configs/nucleo-l476rg/src/stm32_ajoystick.c +++ b/configs/nucleo-l476rg/src/stm32_ajoystick.c @@ -205,7 +205,8 @@ static int ajoy_sample(FAR const struct ajoy_lowerhalf_s *lower, * channels are enabled). */ - nread = file_read(&g_adcfile, adcmsg, MAX_ADC_CHANNELS * sizeof(struct adc_msg_s)); + nread = file_read(&g_adcfile, adcmsg, + MAX_ADC_CHANNELS * sizeof(struct adc_msg_s)); if (nread < 0) { int errcode = get_errno(); diff --git a/configs/nutiny-nuc120/nsh/defconfig b/configs/nutiny-nuc120/nsh/defconfig index f86db749b4eef609100565d303056edefa6ce9c1..60b35489d07e03f9ffe599f6d026a651fa39123e 100644 --- a/configs/nutiny-nuc120/nsh/defconfig +++ b/configs/nutiny-nuc120/nsh/defconfig @@ -819,7 +819,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/olimex-efm32g880f128-stk/nsh/defconfig b/configs/olimex-efm32g880f128-stk/nsh/defconfig index 0949f6717cd95343d87a4bbd8486e3ead27e5de0..067455ef3e040ebf1365613209af0ce94c368312 100644 --- a/configs/olimex-efm32g880f128-stk/nsh/defconfig +++ b/configs/olimex-efm32g880f128-stk/nsh/defconfig @@ -812,7 +812,7 @@ CONFIG_SYSTEM_CLE=y CONFIG_SYSTEM_CLE_DEBUGLEVEL=0 # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/olimex-lpc-h3131/README.txt b/configs/olimex-lpc-h3131/README.txt index 61d5b0416b1747e3aad053b92fe87e27b710f137..f262ff93c7901084e6e8df793bc50a1b453cf6f3 100644 --- a/configs/olimex-lpc-h3131/README.txt +++ b/configs/olimex-lpc-h3131/README.txt @@ -827,8 +827,8 @@ Configurations CONFIG_USBHOST_TRACE_VERBOSE=y Application Configuration -> System Add-Ons - CONFIG_SYSTEM_USBMONITOR=y - CONFIG_SYSTEM_USBMONITOR_INTERVAL=1 + CONFIG_USBMONITOR=y + CONFIG_USBMONITOR_INTERVAL=1 NOTE: I have found that if you enable USB DEBUG and/or USB tracing, the resulting image requires to much memory to execute out of diff --git a/configs/olimex-lpc-h3131/nsh/defconfig b/configs/olimex-lpc-h3131/nsh/defconfig index fa56b2ff44df8475fd6234ed63c47977b13fc63e..a76cfde83d818c13a1ffc0b10b278b9d09cec490 100644 --- a/configs/olimex-lpc-h3131/nsh/defconfig +++ b/configs/olimex-lpc-h3131/nsh/defconfig @@ -827,7 +827,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/olimex-lpc-h3131/src/lpc31_appinit.c b/configs/olimex-lpc-h3131/src/lpc31_appinit.c index 551a2d9bb6ce44e357711d90d5e5cc8dcc5eb056..0a40bb902c82f1733d3635809034cb3c4faf0ddd 100644 --- a/configs/olimex-lpc-h3131/src/lpc31_appinit.c +++ b/configs/olimex-lpc-h3131/src/lpc31_appinit.c @@ -46,8 +46,8 @@ #include -#ifdef CONFIG_SYSTEM_USBMONITOR -# include +#ifdef CONFIG_USBMONITOR +# include #endif #include "lpc31.h" @@ -137,7 +137,7 @@ int board_app_initialize(uintptr_t arg) /* Start the USB Monitor */ syslog(LOG_ERR, "ERROR: Failed to start the USB monitor\n"); - ret = usbmonitor_start(0, NULL); + ret = usbmonitor_start(); if (ret != OK) { syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); diff --git a/configs/olimex-lpc-h3131/src/lpc_h3131.h b/configs/olimex-lpc-h3131/src/lpc_h3131.h index 895b5ca596f91b954899abd44ff6446496b8b402..8285b7e05162f0ec27844fb2025f04f72698e064 100644 --- a/configs/olimex-lpc-h3131/src/lpc_h3131.h +++ b/configs/olimex-lpc-h3131/src/lpc_h3131.h @@ -82,7 +82,7 @@ # undef CONFIG_USBHOST_TRACE #endif -#if !defined(CONFIG_SYSTEM_USBMONITOR) || !defined(CONFIG_USBHOST_TRACE) +#if !defined(CONFIG_USBMONITOR) || !defined(CONFIG_USBHOST_TRACE) # undef HAVE_USBMONITOR #endif diff --git a/configs/olimex-lpc1766stk/ftpc/defconfig b/configs/olimex-lpc1766stk/ftpc/defconfig index 441fb62dbf0caa4dd6e1d810abe2015631ceca06..8fc1fe60108253190541a58b31abd071fa0704da 100644 --- a/configs/olimex-lpc1766stk/ftpc/defconfig +++ b/configs/olimex-lpc1766stk/ftpc/defconfig @@ -1120,7 +1120,7 @@ CONFIG_NSH_MAX_ROUNDTRIP=20 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/olimex-lpc1766stk/hidkbd/defconfig b/configs/olimex-lpc1766stk/hidkbd/defconfig index 5d8034a214ba09513ad80a042425089cc5d3983c..f4dd6913b9437c4ecc5e68f4db1af018a05b4a97 100644 --- a/configs/olimex-lpc1766stk/hidkbd/defconfig +++ b/configs/olimex-lpc1766stk/hidkbd/defconfig @@ -827,7 +827,7 @@ CONFIG_EXAMPLES_HIDKBD_ENCODED=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/olimex-lpc1766stk/hidmouse/defconfig b/configs/olimex-lpc1766stk/hidmouse/defconfig index 1f504dd9d885cdc915db556bc06daeb21ca4aee0..77d8930168ff463d92afd590ecf1e0a489d35062 100644 --- a/configs/olimex-lpc1766stk/hidmouse/defconfig +++ b/configs/olimex-lpc1766stk/hidmouse/defconfig @@ -1119,7 +1119,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/olimex-lpc1766stk/nettest/defconfig b/configs/olimex-lpc1766stk/nettest/defconfig index 90de87d3f043293f15d9be84494a1ac9bd48c26e..f53218ac1cac99204bea19b1cf0437d6870b4e98 100644 --- a/configs/olimex-lpc1766stk/nettest/defconfig +++ b/configs/olimex-lpc1766stk/nettest/defconfig @@ -915,7 +915,7 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/olimex-lpc1766stk/nsh/defconfig b/configs/olimex-lpc1766stk/nsh/defconfig index 0a6e134afc6c18fae06697aeb5645e87215df375..7b565ed90cca746927e0e72930018366242719f6 100644 --- a/configs/olimex-lpc1766stk/nsh/defconfig +++ b/configs/olimex-lpc1766stk/nsh/defconfig @@ -1132,7 +1132,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/olimex-lpc1766stk/nx/defconfig b/configs/olimex-lpc1766stk/nx/defconfig index ccad8743ea028b37b38f05ba635798407f6a9c86..f774a4d7cabf5b2b4756c4e25405b52604a3dc59 100644 --- a/configs/olimex-lpc1766stk/nx/defconfig +++ b/configs/olimex-lpc1766stk/nx/defconfig @@ -913,7 +913,7 @@ CONFIG_EXAMPLES_NX_EXTERNINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/olimex-lpc1766stk/slip-httpd/defconfig b/configs/olimex-lpc1766stk/slip-httpd/defconfig index a19664a5ed180f9c24d4842632edd78643bb26a4..6033db7243b0b46c9130cec89189bcc6c8ab5a66 100644 --- a/configs/olimex-lpc1766stk/slip-httpd/defconfig +++ b/configs/olimex-lpc1766stk/slip-httpd/defconfig @@ -917,7 +917,7 @@ CONFIG_THTTPD_TILDE_MAP_NONE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/olimex-lpc1766stk/thttpd-binfs/defconfig b/configs/olimex-lpc1766stk/thttpd-binfs/defconfig index ed2da29d9e2d48453ef40e1cbdb9357f9fa31a22..bf7ea997727ce611f818d544a179c0c995b98379 100644 --- a/configs/olimex-lpc1766stk/thttpd-binfs/defconfig +++ b/configs/olimex-lpc1766stk/thttpd-binfs/defconfig @@ -968,7 +968,7 @@ CONFIG_THTTPD_TILDE_MAP_NONE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig b/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig index 2db964db3254abc8664b64c6d0f95cbc08bf05ce..f53e7d5f4a8cae614d576a2043c9dee211150518 100644 --- a/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig +++ b/configs/olimex-lpc1766stk/thttpd-nxflat/defconfig @@ -956,7 +956,7 @@ CONFIG_THTTPD_TILDE_MAP_NONE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/olimex-lpc1766stk/usbmsc/defconfig b/configs/olimex-lpc1766stk/usbmsc/defconfig index 35799df9109728dcb8b8ccb9e721f3f3fd0efd0e..2ddcb5ccbdfe36c44aa5fbc21559663cf4478ab4 100644 --- a/configs/olimex-lpc1766stk/usbmsc/defconfig +++ b/configs/olimex-lpc1766stk/usbmsc/defconfig @@ -840,7 +840,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/olimex-lpc1766stk/usbserial/defconfig b/configs/olimex-lpc1766stk/usbserial/defconfig index 2daf97a61ccef9a08e0cb1065c9bdf3d5c99398f..7010288b6255b6c50552d204509e8e700ad762c0 100644 --- a/configs/olimex-lpc1766stk/usbserial/defconfig +++ b/configs/olimex-lpc1766stk/usbserial/defconfig @@ -809,7 +809,7 @@ CONFIG_EXAMPLES_USBSERIAL_BUFSIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/olimex-lpc1766stk/zmodem/defconfig b/configs/olimex-lpc1766stk/zmodem/defconfig index fbcfccd1444c6a72a26547073a618432b0005f3b..3ea8b1c6471d08e3b874f7927032b0957afcaa79 100644 --- a/configs/olimex-lpc1766stk/zmodem/defconfig +++ b/configs/olimex-lpc1766stk/zmodem/defconfig @@ -1145,7 +1145,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/olimex-lpc2378/nsh/defconfig b/configs/olimex-lpc2378/nsh/defconfig index 226f178aaef5e57db59ed9909281cb58f1367e9f..e6cba4b36faf53cb9a404f479ff435ce59ee4aec 100644 --- a/configs/olimex-lpc2378/nsh/defconfig +++ b/configs/olimex-lpc2378/nsh/defconfig @@ -795,7 +795,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/olimex-stm32-e407/Kconfig b/configs/olimex-stm32-e407/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..7e553c54365d6674a3545bf3441008295322d23e --- /dev/null +++ b/configs/olimex-stm32-e407/Kconfig @@ -0,0 +1,8 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_OLIMEX_STM32E407 + +endif diff --git a/configs/olimex-stm32-e407/README.txt b/configs/olimex-stm32-e407/README.txt new file mode 100644 index 0000000000000000000000000000000000000000..0b6e02eee735a1d93c721a27724a9a512dc13123 --- /dev/null +++ b/configs/olimex-stm32-e407/README.txt @@ -0,0 +1,6 @@ +README +====== +The Olimex STM32-E407 configuration is based on the configuration olimex-stm32-h407 and stm32f4discovery. + +nsh - Basic shell run on USART2. +usbnsh - Basic shell run on the virtual serial port. diff --git a/configs/olimex-stm32-e407/include/board.h b/configs/olimex-stm32-e407/include/board.h new file mode 100644 index 0000000000000000000000000000000000000000..d74fd06f765bbe3a7560148378d0c3f7e6214768 --- /dev/null +++ b/configs/olimex-stm32-e407/include/board.h @@ -0,0 +1,289 @@ +/************************************************************************************ + * configs/olimex-stm32-e407/include/board.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * Modified for H407 Neil Hancock + * Modified for E407 Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __CONFIGS_OLIMEX_STM32_E407_INCLUDE_BOARD_H +#define __CONFIGS_OLIMEX_STM32_E407_INCLUDE_BOARD_H 1 + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#ifndef __ASSEMBLY__ +# include +# include +#endif + +#ifdef __KERNEL__ +# include "stm32_rcc.h" +# include "stm32_sdio.h" +# include "stm32.h" +#endif + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Clocking *************************************************************************/ +/* The Olimex-STM32-E407 board features a 12MHz crystal and + * a 32kHz RTC backup crystal. + * + * This is the canonical configuration: + * System Clock source : PLL (HSE) + * SYSCLK(Hz) : 168000000 Determined by PLL configuration + * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) + * PLLM : 8 (STM32_PLLCFG_PLLM) + * PLLN : 336 (STM32_PLLCFG_PLLN) + * PLLP : 2 (STM32_PLLCFG_PLLP) + * PLLQ : 7 (STM32_PLLCFG_PLLQ) + * Main regulator output voltage : Scale1 mode Needed for high speed SYSCLK + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for USB OTG FS, : Enabled + * SDIO and RNG clock + */ + +/* HSI - 16 MHz RC factory-trimmed + * LSI - 32 KHz RC (30-60KHz, uncalibrated) + * HSE - On-board crystal frequency is 12MHz + * LSE - 32.768 kHz + * STM32F407ZGT6 - too 168Mhz + */ + +#define STM32_BOARD_XTAL 12000000ul + +#define STM32_HSI_FREQUENCY 16000000ul +#define STM32_LSI_FREQUENCY 32000 +#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL +#define STM32_LSE_FREQUENCY 32768 + +/* Main PLL Configuration. + * + * PLL source is HSE + * PLL_VCO = (STM32_HSE_FREQUENCY / PLLM) * PLLN + * = (25,000,000 / 12) * 360 + * = 240,000,000 + * SYSCLK = PLL_VCO / PLLP + * = 240,000,000 / 2 = 120,000,000 + * USB OTG FS, SDIO and RNG Clock + * = PLL_VCO / PLLQ + * = 240,000,000 / 5 = 48,000,000 + * = 48,000,000 + * + * Xtal /M *n /P SysClk AHB HCLK APB1 PCLK1 + * 12Mhz HSE /12 336 /2 PLLCLK 168Mhz /1 168 /4 42Mhz + * 12Mhz HSE /6 168 /2 PLLCLK 168Mhz /1 168 /4 42Mhz + */ + +#define STM32_PLLCFG_PLLM RCC_PLLCFG_PLLM(3) +#define STM32_PLLCFG_PLLN RCC_PLLCFG_PLLN(84) +#define STM32_PLLCFG_PLLP RCC_PLLCFG_PLLP_2 +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(5) +#define STM32_PLLCFG_PLLQ RCC_PLLCFG_PLLQ(7) + +#define STM32_SYSCLK_FREQUENCY 168000000ul + +/* AHB clock (HCLK) is SYSCLK (168MHz) */ + +#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */ +#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY +#define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */ + +/* APB1 clock (PCLK1) is HCLK/4 (42MHz) */ + +#define STM32_RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* Timers driven from APB1 will be twice PCLK1 */ + +#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY) +#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY) + +/* APB2 clock (PCLK2) is HCLK/2 */ + +#define STM32_RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_HCLKd2 /* PCLK2 = HCLK / 2 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/2) + +/* Timers driven from APB2 will be twice PCLK2 */ + +#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM9_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM10_CLKIN (2*STM32_PCLK2_FREQUENCY) +#define STM32_APB2_TIM11_CLKIN (2*STM32_PCLK2_FREQUENCY) + +/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx + * otherwise frequency is 2xAPBx. + * Note: TIM1,8 are on APB2, others on APB1 + */ + +#define STM32_TIM18_FREQUENCY STM32_HCLK_FREQUENCY +#define STM32_TIM27_FREQUENCY STM32_HCLK_FREQUENCY + +/* LED definitions ******************************************************************/ +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the status LED in any + * way. The following definitions are used to access individual LEDs. + */ + +/* LED index values for use with board_userled() */ + +#define BOARD_LED_STATUS 0 +#define BOARD_NLEDS 1 + +/* LED bits for use with board_userled_all() */ + +#define BOARD_LED_STATUS_BIT (1 << BOARD_LED1) + +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the status LED of the + * Olimex STM32-E405. The following definitions describe how NuttX controls the LEDs: + */ + +#define LED_STARTED 0 /* LED_STATUS on */ +#define LED_HEAPALLOCATE 1 /* no change */ +#define LED_IRQSENABLED 2 /* no change */ +#define LED_STACKCREATED 3 /* no change */ +#define LED_INIRQ 4 /* no change */ +#define LED_SIGNAL 5 /* no change */ +#define LED_ASSERTION 6 /* LED_STATUS off */ +#define LED_PANIC 7 /* LED_STATUS blinking */ + +/* Button definitions ***************************************************************/ +/* The Olimex STM32-E405 supports one buttons: */ + +#define BUTTON_BUT 0 +#define NUM_BUTTONS 1 + +#define BUTTON_BUT_BIT (1 << BUTTON_BUT) + +/* Alternate function pin selections ************************************************/ + +/* USART1 */ +#define GPIO_USART1_RX GPIO_USART1_RX_2 /* PB7 */ +#define GPIO_USART1_TX GPIO_USART1_TX_2 /* PB6 */ + +/* USART2 */ +#define GPIO_USART2_RX GPIO_USART2_RX_2 /* PD6 */ +#define GPIO_USART2_TX GPIO_USART2_TX_2 /* PD5 */ + +/* USART3 */ +#define GPIO_USART3_RX GPIO_USART3_RX_1 /* PB11 */ +#define GPIO_USART3_TX GPIO_USART3_TX_1 /* PB10 */ + +/* CAN */ +#define GPIO_CAN1_RX GPIO_CAN1_RX_2 /* PB8 */ +#define GPIO_CAN1_TX GPIO_CAN1_TX_2 /* PB9 */ + +/* I2C */ +#define GPIO_I2C1_SCL GPIO_I2C1_SCL_1 /* PB6 */ +#define GPIO_I2C1_SDA GPIO_I2C1_SDA_1 /* PB7 */ + +/* Ethernet *************************************************************************/ + +#if defined(CONFIG_STM32_ETHMAC) +/* RMII interface to the LAN8720 PHY */ + +# ifndef CONFIG_STM32_RMII +# error CONFIG_STM32_RMII must be defined +# endif + +/* Clocking is provided by an external 50Mhz XTAL */ + +# ifndef CONFIG_STM32_RMII_EXTCLK +# error CONFIG_STM32_RMII_EXTCLK must be defined +# endif + +/* Pin disambiguation */ + +# define GPIO_ETH_MII_COL GPIO_ETH_MII_COL_1 /* PA3 */ +# define GPIO_ETH_RMII_TXD0 GPIO_ETH_RMII_TXD0_2 /* PG13 */ +# define GPIO_ETH_RMII_TXD1 GPIO_ETH_RMII_TXD1_2 /* PG14 */ +# define GPIO_ETH_RMII_TX_EN GPIO_ETH_RMII_TX_EN_2 /* PG11 */ + +#endif + +/******************************************************************************* + * Public Data + ******************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/****************************************************************************** + * Public Function Prototypes + *****************************************************************************/ + +/****************************************************************************** + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This entry point + * is called early in the initialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + *****************************************************************************/ + +void stm32_boardinitialize(void); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_OLIMEX_STM32_E407_INCLUDE_BOARD_H */ diff --git a/configs/olimex-stm32-e407/nsh/Make.defs b/configs/olimex-stm32-e407/nsh/Make.defs new file mode 100644 index 0000000000000000000000000000000000000000..5b53bc4e2ada3f66a0b796f1b3c848463ca0e623 --- /dev/null +++ b/configs/olimex-stm32-e407/nsh/Make.defs @@ -0,0 +1,112 @@ +############################################################################ +# configs/olimex-stm32-e407/nsh/Make.defs +# +# Copyright (C) 2011-2012, 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk +include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs + +LDSCRIPT = ld.script + +ifeq ($(WINTOOL),y) + # Windows-native toolchains + DIRLINK = $(TOPDIR)/tools/copydir.sh + DIRUNLINK = $(TOPDIR)/tools/unlink.sh + MKDEP = $(TOPDIR)/tools/mkwindeps.sh + ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" + ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" + ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}" +else + # Linux/Cygwin-native toolchain + MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + ARCHINCLUDES = -I. -isystem $(TOPDIR)/include + ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx + ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT) +endif + +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +AR = $(ARCROSSDEV)ar rcs +NM = $(ARCROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'} +ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1} + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ARCHCFLAGS = -fno-builtin +ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fno-rtti +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +ARCHDEFINES = +ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10 + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS) +CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS) +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ + +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +ASMEXT = .S +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +ifneq ($(CROSSDEV),arm-nuttx-elf-) + LDFLAGS += -nostartfiles -nodefaultlibs +endif +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = diff --git a/configs/stm32f746g-disco/netnsh/defconfig b/configs/olimex-stm32-e407/nsh/defconfig similarity index 53% rename from configs/stm32f746g-disco/netnsh/defconfig rename to configs/olimex-stm32-e407/nsh/defconfig index 7774a4b116ef655aa60b8d7fa7f8ee7bb0cf6796..dab00f77d1b6fb86bd056f333d039b16db21adf7 100644 --- a/configs/stm32f746g-disco/netnsh/defconfig +++ b/configs/olimex-stm32-e407/nsh/defconfig @@ -8,14 +8,10 @@ # # CONFIG_EXPERIMENTAL is not set # CONFIG_DEFAULT_SMALL is not set -# CONFIG_HOST_LINUX is not set +CONFIG_HOST_LINUX=y # CONFIG_HOST_OSX is not set -CONFIG_HOST_WINDOWS=y +# CONFIG_HOST_WINDOWS is not set # CONFIG_HOST_OTHER is not set -# CONFIG_WINDOWS_NATIVE is not set -CONFIG_WINDOWS_CYGWIN=y -# CONFIG_WINDOWS_MSYS is not set -# CONFIG_WINDOWS_OTHER is not set # # Build Configuration @@ -54,9 +50,9 @@ CONFIG_ARCH_HAVE_HEAPCHECK=y # CONFIG_HEAP_COLORATION is not set # CONFIG_DEBUG_SYMBOLS is not set CONFIG_ARCH_HAVE_CUSTOMOPT=y -CONFIG_DEBUG_NOOPT=y +# CONFIG_DEBUG_NOOPT is not set # CONFIG_DEBUG_CUSTOMOPT is not set -# CONFIG_DEBUG_FULLOPT is not set +CONFIG_DEBUG_FULLOPT=y # # System Type @@ -99,8 +95,8 @@ CONFIG_ARCH="arm" # CONFIG_ARCH_CHIP_SAML is not set # CONFIG_ARCH_CHIP_SAM34 is not set # CONFIG_ARCH_CHIP_SAMV7 is not set -# CONFIG_ARCH_CHIP_STM32 is not set -CONFIG_ARCH_CHIP_STM32F7=y +CONFIG_ARCH_CHIP_STM32=y +# CONFIG_ARCH_CHIP_STM32F7 is not set # CONFIG_ARCH_CHIP_STM32L4 is not set # CONFIG_ARCH_CHIP_STR71X is not set # CONFIG_ARCH_CHIP_TMS570 is not set @@ -110,8 +106,8 @@ CONFIG_ARCH_CHIP_STM32F7=y # CONFIG_ARCH_ARM920T is not set # CONFIG_ARCH_CORTEXM0 is not set # CONFIG_ARCH_CORTEXM3 is not set -# CONFIG_ARCH_CORTEXM4 is not set -CONFIG_ARCH_CORTEXM7=y +CONFIG_ARCH_CORTEXM4=y +# CONFIG_ARCH_CORTEXM7 is not set # CONFIG_ARCH_CORTEXA5 is not set # CONFIG_ARCH_CORTEXA8 is not set # CONFIG_ARCH_CORTEXA9 is not set @@ -122,12 +118,12 @@ CONFIG_ARCH_CORTEXM7=y # CONFIG_ARCH_CORTEXR7 is not set # CONFIG_ARCH_CORTEXR7F is not set CONFIG_ARCH_FAMILY="armv7-m" -CONFIG_ARCH_CHIP="stm32f7" +CONFIG_ARCH_CHIP="stm32" # CONFIG_ARM_TOOLCHAIN_IAR is not set CONFIG_ARM_TOOLCHAIN_GNU=y # CONFIG_ARMV7M_USEBASEPRI is not set CONFIG_ARCH_HAVE_CMNVECTOR=y -CONFIG_ARMV7M_CMNVECTOR=y +# CONFIG_ARMV7M_CMNVECTOR is not set # CONFIG_ARMV7M_LAZYFPU is not set CONFIG_ARCH_HAVE_FPU=y # CONFIG_ARCH_HAVE_DPFPU is not set @@ -139,240 +135,356 @@ CONFIG_ARM_HAVE_MPU_UNIFIED=y # # ARMV7M Configuration Options # -CONFIG_ARMV7M_HAVE_ICACHE=y -CONFIG_ARMV7M_HAVE_DCACHE=y -CONFIG_ARMV7M_ICACHE=y -CONFIG_ARMV7M_DCACHE=y -CONFIG_ARMV7M_DCACHE_WRITETHROUGH=y -CONFIG_ARMV7M_HAVE_ITCM=y -CONFIG_ARMV7M_HAVE_DTCM=y -# CONFIG_ARMV7M_ITCM is not set -CONFIG_ARMV7M_DTCM=y -# CONFIG_ARMV7M_TOOLCHAIN_IARW is not set -# CONFIG_ARMV7M_TOOLCHAIN_ATOLLIC is not set +# CONFIG_ARMV7M_HAVE_ICACHE is not set +# CONFIG_ARMV7M_HAVE_DCACHE is not set +# CONFIG_ARMV7M_HAVE_ITCM is not set +# CONFIG_ARMV7M_HAVE_DTCM is not set +# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set # CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set -# CONFIG_ARMV7M_TOOLCHAIN_CODEREDW is not set -# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYW is not set -# CONFIG_ARMV7M_TOOLCHAIN_DEVKITARM is not set -# CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL is not set -CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIW=y -# CONFIG_ARMV7M_TOOLCHAIN_RAISONANCE is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y CONFIG_ARMV7M_HAVE_STACKCHECK=y # CONFIG_ARMV7M_STACKCHECK is not set # CONFIG_ARMV7M_ITMSYSLOG is not set # CONFIG_SERIAL_TERMIOS is not set -# CONFIG_USART6_RS485 is not set -# CONFIG_SERIAL_DISABLE_REORDERING is not set # -# STM32 F7 Configuration Options -# -CONFIG_ARCH_CHIP_STM32F745VG=y -# CONFIG_ARCH_CHIP_STM32F745VE is not set -# CONFIG_ARCH_CHIP_STM32F745IG is not set -# CONFIG_ARCH_CHIP_STM32F745IE is not set -# CONFIG_ARCH_CHIP_STM32F745ZE is not set -# CONFIG_ARCH_CHIP_STM32F745ZG is not set -# CONFIG_ARCH_CHIP_STM32F746BG is not set -# CONFIG_ARCH_CHIP_STM32F746VG is not set -# CONFIG_ARCH_CHIP_STM32F746VE is not set -# CONFIG_ARCH_CHIP_STM32F746BE is not set -# CONFIG_ARCH_CHIP_STM32F746ZG is not set -# CONFIG_ARCH_CHIP_STM32F746IE is not set -# CONFIG_ARCH_CHIP_STM32F746NG is not set -# CONFIG_ARCH_CHIP_STM32F746NE is not set -# CONFIG_ARCH_CHIP_STM32F746ZE is not set -# CONFIG_ARCH_CHIP_STM32F746IG is not set -# CONFIG_ARCH_CHIP_STM32F756NG is not set -# CONFIG_ARCH_CHIP_STM32F756BG is not set -# CONFIG_ARCH_CHIP_STM32F756IG is not set -# CONFIG_ARCH_CHIP_STM32F756VG is not set -# CONFIG_ARCH_CHIP_STM32F756ZG is not set -# CONFIG_ARCH_CHIP_STM32F765NI is not set -# CONFIG_ARCH_CHIP_STM32F765VI is not set -# CONFIG_ARCH_CHIP_STM32F765VG is not set -# CONFIG_ARCH_CHIP_STM32F765BI is not set -# CONFIG_ARCH_CHIP_STM32F765NG is not set -# CONFIG_ARCH_CHIP_STM32F765ZG is not set -# CONFIG_ARCH_CHIP_STM32F765ZI is not set -# CONFIG_ARCH_CHIP_STM32F765IG is not set -# CONFIG_ARCH_CHIP_STM32F765BG is not set -# CONFIG_ARCH_CHIP_STM32F765II is not set -# CONFIG_ARCH_CHIP_STM32F767NG is not set -# CONFIG_ARCH_CHIP_STM32F767IG is not set -# CONFIG_ARCH_CHIP_STM32F767VG is not set -# CONFIG_ARCH_CHIP_STM32F767ZG is not set -# CONFIG_ARCH_CHIP_STM32F767NI is not set -# CONFIG_ARCH_CHIP_STM32F767VI is not set -# CONFIG_ARCH_CHIP_STM32F767BG is not set -# CONFIG_ARCH_CHIP_STM32F767ZI is not set -# CONFIG_ARCH_CHIP_STM32F767II is not set -# CONFIG_ARCH_CHIP_STM32F769BI is not set -# CONFIG_ARCH_CHIP_STM32F769II is not set -# CONFIG_ARCH_CHIP_STM32F769BG is not set -# CONFIG_ARCH_CHIP_STM32F769NI is not set -# CONFIG_ARCH_CHIP_STM32F769AI is not set -# CONFIG_ARCH_CHIP_STM32F769NG is not set -# CONFIG_ARCH_CHIP_STM32F769IG is not set -# CONFIG_ARCH_CHIP_STM32F777ZI is not set -# CONFIG_ARCH_CHIP_STM32F777VI is not set -# CONFIG_ARCH_CHIP_STM32F777NI is not set -# CONFIG_ARCH_CHIP_STM32F777BI is not set -# CONFIG_ARCH_CHIP_STM32F777II is not set -# CONFIG_ARCH_CHIP_STM32F778AI is not set -# CONFIG_ARCH_CHIP_STM32F779II is not set -# CONFIG_ARCH_CHIP_STM32F779NI is not set -# CONFIG_ARCH_CHIP_STM32F779BI is not set -# CONFIG_ARCH_CHIP_STM32F779AI is not set -CONFIG_STM32F7_STM32F74XX=y -# CONFIG_STM32F7_STM32F75XX is not set -# CONFIG_STM32F7_STM32F76XX is not set -# CONFIG_STM32F7_STM32F77XX is not set -CONFIG_STM32F7_IO_CONFIG_V=y -# CONFIG_STM32F7_IO_CONFIG_I is not set -# CONFIG_STM32F7_IO_CONFIG_Z is not set -# CONFIG_STM32F7_IO_CONFIG_N is not set -# CONFIG_STM32F7_IO_CONFIG_B is not set -# CONFIG_STM32F7_IO_CONFIG_A is not set -CONFIG_STM32F7_STM32F745XX=y -# CONFIG_STM32F7_STM32F746XX is not set -# CONFIG_STM32F7_STM32F756XX is not set -# CONFIG_STM32F7_STM32F765XX is not set -# CONFIG_STM32F7_STM32F767XX is not set -# CONFIG_STM32F7_STM32F768XX is not set -# CONFIG_STM32F7_STM32F768AX is not set -# CONFIG_STM32F7_STM32F769XX is not set -# CONFIG_STM32F7_STM32F769AX is not set -# CONFIG_STM32F7_STM32F777XX is not set -# CONFIG_STM32F7_STM32F778XX is not set -# CONFIG_STM32F7_STM32F778AX is not set -# CONFIG_STM32F7_STM32F779XX is not set -# CONFIG_STM32F7_STM32F779AX is not set -# CONFIG_STM32F7_FLASH_CONFIG_E is not set -# CONFIG_STM32F7_FLASH_CONFIG_I is not set -CONFIG_STM32F7_FLASH_OVERRIDE_DEFAULT=y -# CONFIG_STM32F7_FLASH_OVERRIDE_E is not set -# CONFIG_STM32F7_FLASH_OVERRIDE_G is not set -# CONFIG_STM32F7_FLASH_OVERRIDE_I is not set +# STM32 Configuration Options +# +# CONFIG_ARCH_CHIP_STM32L151C6 is not set +# CONFIG_ARCH_CHIP_STM32L151C8 is not set +# CONFIG_ARCH_CHIP_STM32L151CB is not set +# CONFIG_ARCH_CHIP_STM32L151R6 is not set +# CONFIG_ARCH_CHIP_STM32L151R8 is not set +# CONFIG_ARCH_CHIP_STM32L151RB is not set +# CONFIG_ARCH_CHIP_STM32L151V6 is not set +# CONFIG_ARCH_CHIP_STM32L151V8 is not set +# CONFIG_ARCH_CHIP_STM32L151VB is not set +# CONFIG_ARCH_CHIP_STM32L152C6 is not set +# CONFIG_ARCH_CHIP_STM32L152C8 is not set +# CONFIG_ARCH_CHIP_STM32L152CB is not set +# CONFIG_ARCH_CHIP_STM32L152R6 is not set +# CONFIG_ARCH_CHIP_STM32L152R8 is not set +# CONFIG_ARCH_CHIP_STM32L152RB is not set +# CONFIG_ARCH_CHIP_STM32L152V6 is not set +# CONFIG_ARCH_CHIP_STM32L152V8 is not set +# CONFIG_ARCH_CHIP_STM32L152VB is not set +# CONFIG_ARCH_CHIP_STM32L162ZD is not set +# CONFIG_ARCH_CHIP_STM32L162VE is not set +# CONFIG_ARCH_CHIP_STM32F100C8 is not set +# CONFIG_ARCH_CHIP_STM32F100CB is not set +# CONFIG_ARCH_CHIP_STM32F100R8 is not set +# CONFIG_ARCH_CHIP_STM32F100RB is not set +# CONFIG_ARCH_CHIP_STM32F100RC is not set +# CONFIG_ARCH_CHIP_STM32F100RD is not set +# CONFIG_ARCH_CHIP_STM32F100RE is not set +# CONFIG_ARCH_CHIP_STM32F100V8 is not set +# CONFIG_ARCH_CHIP_STM32F100VB is not set +# CONFIG_ARCH_CHIP_STM32F100VC is not set +# CONFIG_ARCH_CHIP_STM32F100VD is not set +# CONFIG_ARCH_CHIP_STM32F100VE is not set +# CONFIG_ARCH_CHIP_STM32F102CB is not set +# CONFIG_ARCH_CHIP_STM32F103T8 is not set +# CONFIG_ARCH_CHIP_STM32F103TB is not set +# CONFIG_ARCH_CHIP_STM32F103C4 is not set +# CONFIG_ARCH_CHIP_STM32F103C8 is not set +# CONFIG_ARCH_CHIP_STM32F103CB is not set +# CONFIG_ARCH_CHIP_STM32F103R8 is not set +# CONFIG_ARCH_CHIP_STM32F103RB is not set +# CONFIG_ARCH_CHIP_STM32F103RC is not set +# CONFIG_ARCH_CHIP_STM32F103RD is not set +# CONFIG_ARCH_CHIP_STM32F103RE is not set +# CONFIG_ARCH_CHIP_STM32F103RG is not set +# CONFIG_ARCH_CHIP_STM32F103V8 is not set +# CONFIG_ARCH_CHIP_STM32F103VB is not set +# CONFIG_ARCH_CHIP_STM32F103VC is not set +# CONFIG_ARCH_CHIP_STM32F103VE is not set +# CONFIG_ARCH_CHIP_STM32F103ZE is not set +# CONFIG_ARCH_CHIP_STM32F105VB is not set +# CONFIG_ARCH_CHIP_STM32F105RB is not set +# CONFIG_ARCH_CHIP_STM32F107VC is not set +# CONFIG_ARCH_CHIP_STM32F205RG is not set +# CONFIG_ARCH_CHIP_STM32F207IG is not set +# CONFIG_ARCH_CHIP_STM32F207ZE is not set +# CONFIG_ARCH_CHIP_STM32F302K6 is not set +# CONFIG_ARCH_CHIP_STM32F302K8 is not set +# CONFIG_ARCH_CHIP_STM32F302CB is not set +# CONFIG_ARCH_CHIP_STM32F302CC is not set +# CONFIG_ARCH_CHIP_STM32F302RB is not set +# CONFIG_ARCH_CHIP_STM32F302RC is not set +# CONFIG_ARCH_CHIP_STM32F302VB is not set +# CONFIG_ARCH_CHIP_STM32F302VC is not set +# CONFIG_ARCH_CHIP_STM32F303K6 is not set +# CONFIG_ARCH_CHIP_STM32F303K8 is not set +# CONFIG_ARCH_CHIP_STM32F303C6 is not set +# CONFIG_ARCH_CHIP_STM32F303C8 is not set +# CONFIG_ARCH_CHIP_STM32F303CB is not set +# CONFIG_ARCH_CHIP_STM32F303CC is not set +# CONFIG_ARCH_CHIP_STM32F303RB is not set +# CONFIG_ARCH_CHIP_STM32F303RC is not set +# CONFIG_ARCH_CHIP_STM32F303RD is not set +# CONFIG_ARCH_CHIP_STM32F303RE is not set +# CONFIG_ARCH_CHIP_STM32F303VB is not set +# CONFIG_ARCH_CHIP_STM32F303VC is not set +# CONFIG_ARCH_CHIP_STM32F372C8 is not set +# CONFIG_ARCH_CHIP_STM32F372R8 is not set +# CONFIG_ARCH_CHIP_STM32F372V8 is not set +# CONFIG_ARCH_CHIP_STM32F372CB is not set +# CONFIG_ARCH_CHIP_STM32F372RB is not set +# CONFIG_ARCH_CHIP_STM32F372VB is not set +# CONFIG_ARCH_CHIP_STM32F372CC is not set +# CONFIG_ARCH_CHIP_STM32F372RC is not set +# CONFIG_ARCH_CHIP_STM32F372VC is not set +# CONFIG_ARCH_CHIP_STM32F373C8 is not set +# CONFIG_ARCH_CHIP_STM32F373R8 is not set +# CONFIG_ARCH_CHIP_STM32F373V8 is not set +# CONFIG_ARCH_CHIP_STM32F373CB is not set +# CONFIG_ARCH_CHIP_STM32F373RB is not set +# CONFIG_ARCH_CHIP_STM32F373VB is not set +# CONFIG_ARCH_CHIP_STM32F373CC is not set +# CONFIG_ARCH_CHIP_STM32F373RC is not set +# CONFIG_ARCH_CHIP_STM32F373VC is not set +# CONFIG_ARCH_CHIP_STM32F401RE is not set +# CONFIG_ARCH_CHIP_STM32F411RE is not set +# CONFIG_ARCH_CHIP_STM32F411VE is not set +# CONFIG_ARCH_CHIP_STM32F405RG is not set +# CONFIG_ARCH_CHIP_STM32F405VG is not set +# CONFIG_ARCH_CHIP_STM32F405ZG is not set +# CONFIG_ARCH_CHIP_STM32F407VE is not set +# CONFIG_ARCH_CHIP_STM32F407VG is not set +# CONFIG_ARCH_CHIP_STM32F407ZE is not set +CONFIG_ARCH_CHIP_STM32F407ZG=y +# CONFIG_ARCH_CHIP_STM32F407IE is not set +# CONFIG_ARCH_CHIP_STM32F407IG is not set +# CONFIG_ARCH_CHIP_STM32F427V is not set +# CONFIG_ARCH_CHIP_STM32F427Z is not set +# CONFIG_ARCH_CHIP_STM32F427I is not set +# CONFIG_ARCH_CHIP_STM32F429V is not set +# CONFIG_ARCH_CHIP_STM32F429Z is not set +# CONFIG_ARCH_CHIP_STM32F429I is not set +# CONFIG_ARCH_CHIP_STM32F429B is not set +# CONFIG_ARCH_CHIP_STM32F429N is not set +# CONFIG_ARCH_CHIP_STM32F446M is not set +# CONFIG_ARCH_CHIP_STM32F446R is not set +# CONFIG_ARCH_CHIP_STM32F446V is not set +# CONFIG_ARCH_CHIP_STM32F446Z is not set +# CONFIG_ARCH_CHIP_STM32F469A is not set +# CONFIG_ARCH_CHIP_STM32F469I is not set +# CONFIG_ARCH_CHIP_STM32F469B is not set +# CONFIG_ARCH_CHIP_STM32F469N is not set +CONFIG_STM32_FLASH_CONFIG_DEFAULT=y +# CONFIG_STM32_FLASH_CONFIG_4 is not set +# CONFIG_STM32_FLASH_CONFIG_6 is not set +# CONFIG_STM32_FLASH_CONFIG_8 is not set +# CONFIG_STM32_FLASH_CONFIG_B is not set +# CONFIG_STM32_FLASH_CONFIG_C is not set +# CONFIG_STM32_FLASH_CONFIG_D is not set +# CONFIG_STM32_FLASH_CONFIG_E is not set +# CONFIG_STM32_FLASH_CONFIG_F is not set +# CONFIG_STM32_FLASH_CONFIG_G is not set +# CONFIG_STM32_FLASH_CONFIG_I is not set +# CONFIG_STM32_STM32L15XX is not set +# CONFIG_STM32_ENERGYLITE is not set +# CONFIG_STM32_STM32F10XX is not set +# CONFIG_STM32_VALUELINE is not set +# CONFIG_STM32_CONNECTIVITYLINE is not set +# CONFIG_STM32_PERFORMANCELINE is not set +# CONFIG_STM32_USBACCESSLINE is not set +# CONFIG_STM32_HIGHDENSITY is not set +# CONFIG_STM32_MEDIUMDENSITY is not set +# CONFIG_STM32_LOWDENSITY is not set +# CONFIG_STM32_STM32F20XX is not set +# CONFIG_STM32_STM32F205 is not set +# CONFIG_STM32_STM32F207 is not set +# CONFIG_STM32_STM32F30XX is not set +# CONFIG_STM32_STM32F302 is not set +# CONFIG_STM32_STM32F303 is not set +# CONFIG_STM32_STM32F37XX is not set +CONFIG_STM32_STM32F40XX=y +# CONFIG_STM32_STM32F401 is not set +# CONFIG_STM32_STM32F411 is not set +# CONFIG_STM32_STM32F405 is not set +CONFIG_STM32_STM32F407=y +# CONFIG_STM32_STM32F427 is not set +# CONFIG_STM32_STM32F429 is not set +# CONFIG_STM32_STM32F446 is not set +# CONFIG_STM32_STM32F469 is not set +# CONFIG_STM32_DFU is not set # # STM32 Peripheral Support # -# CONFIG_STM32F7_HAVE_LTDC is not set -CONFIG_STM32F7_HAVE_FSMC=y -CONFIG_STM32F7_HAVE_ETHRNET=y -CONFIG_STM32F7_HAVE_RNG=y -# CONFIG_STM32F7_HAVE_SPI5 is not set -# CONFIG_STM32F7_HAVE_SPI6 is not set -# CONFIG_STM32F7_HAVE_SDMMC2 is not set -# CONFIG_STM32F7_HAVE_ADC1_DMA is not set -# CONFIG_STM32F7_HAVE_ADC2_DMA is not set -# CONFIG_STM32F7_HAVE_ADC3_DMA is not set -# CONFIG_STM32F7_HAVE_CAN3 is not set -CONFIG_STM32F7_HAVE_DCMI=y -# CONFIG_STM32F7_HAVE_DSIHOST is not set -CONFIG_STM32F7_HAVE_DMA2D=y -# CONFIG_STM32F7_HAVE_JPEG is not set -# CONFIG_STM32F7_HAVE_CRYP is not set -# CONFIG_STM32F7_HAVE_HASH is not set -# CONFIG_STM32F7_HAVE_DFSDM1 is not set -# CONFIG_STM32F7_ADC is not set -# CONFIG_STM32F7_CAN is not set -# CONFIG_STM32F7_DAC is not set -# CONFIG_STM32F7_DMA is not set -# CONFIG_STM32F7_I2C is not set -# CONFIG_STM32F7_SAI is not set -# CONFIG_STM32F7_SPI is not set -# CONFIG_STM32F7_TIM is not set -CONFIG_STM32F7_USART=y -# CONFIG_STM32F7_ADC1 is not set -# CONFIG_STM32F7_ADC2 is not set -# CONFIG_STM32F7_ADC3 is not set -# CONFIG_STM32F7_BKPSRAM is not set -# CONFIG_STM32F7_CAN1 is not set -# CONFIG_STM32F7_CAN2 is not set -# CONFIG_STM32F7_CEC is not set -# CONFIG_STM32F7_CRC is not set -# CONFIG_STM32F7_DMA1 is not set -# CONFIG_STM32F7_DMA2 is not set -# CONFIG_STM32F7_DAC1 is not set -# CONFIG_STM32F7_DAC2 is not set -# CONFIG_STM32F7_DCMI is not set -# CONFIG_STM32F7_DMA2D is not set -CONFIG_STM32F7_ETHMAC=y -# CONFIG_STM32F7_FSMC is not set -# CONFIG_STM32F7_I2C1 is not set -# CONFIG_STM32F7_I2C2 is not set -# CONFIG_STM32F7_I2C3 is not set -# CONFIG_STM32F7_I2C4 is not set -# CONFIG_STM32F7_LPTIM1 is not set -# CONFIG_STM32F7_OTGFS is not set -# CONFIG_STM32F7_OTGHS is not set -# CONFIG_STM32F7_QUADSPI is not set -# CONFIG_STM32F7_RNG is not set -# CONFIG_STM32F7_SAI1 is not set -# CONFIG_STM32F7_SAI2 is not set -# CONFIG_STM32F7_SDMMC1 is not set -# CONFIG_STM32F7_SPDIFRX is not set -# CONFIG_STM32F7_SPI1 is not set -# CONFIG_STM32F7_SPI2 is not set -# CONFIG_STM32F7_SPI3 is not set -# CONFIG_STM32F7_SPI4 is not set -# CONFIG_STM32F7_TIM1 is not set -# CONFIG_STM32F7_TIM2 is not set -# CONFIG_STM32F7_TIM3 is not set -# CONFIG_STM32F7_TIM4 is not set -# CONFIG_STM32F7_TIM5 is not set -# CONFIG_STM32F7_TIM6 is not set -# CONFIG_STM32F7_TIM7 is not set -# CONFIG_STM32F7_TIM8 is not set -# CONFIG_STM32F7_TIM9 is not set -# CONFIG_STM32F7_TIM10 is not set -# CONFIG_STM32F7_TIM11 is not set -# CONFIG_STM32F7_TIM12 is not set -# CONFIG_STM32F7_TIM13 is not set -# CONFIG_STM32F7_TIM14 is not set -# CONFIG_STM32F7_USART1 is not set -# CONFIG_STM32F7_USART2 is not set -# CONFIG_STM32F7_USART3 is not set -# CONFIG_STM32F7_UART4 is not set -# CONFIG_STM32F7_UART5 is not set -CONFIG_STM32F7_USART6=y -# CONFIG_STM32F7_UART7 is not set -# CONFIG_STM32F7_UART8 is not set -# CONFIG_STM32F7_IWDG is not set -# CONFIG_STM32F7_WWDG is not set +CONFIG_STM32_HAVE_CCM=y +# CONFIG_STM32_HAVE_USBDEV is not set +CONFIG_STM32_HAVE_OTGFS=y +CONFIG_STM32_HAVE_FSMC=y +# CONFIG_STM32_HAVE_LTDC is not set +CONFIG_STM32_HAVE_USART3=y +CONFIG_STM32_HAVE_UART4=y +CONFIG_STM32_HAVE_UART5=y +CONFIG_STM32_HAVE_USART6=y +# CONFIG_STM32_HAVE_UART7 is not set +# CONFIG_STM32_HAVE_UART8 is not set +CONFIG_STM32_HAVE_TIM1=y +CONFIG_STM32_HAVE_TIM2=y +CONFIG_STM32_HAVE_TIM3=y +CONFIG_STM32_HAVE_TIM4=y +CONFIG_STM32_HAVE_TIM5=y +CONFIG_STM32_HAVE_TIM6=y +CONFIG_STM32_HAVE_TIM7=y +CONFIG_STM32_HAVE_TIM8=y +CONFIG_STM32_HAVE_TIM9=y +CONFIG_STM32_HAVE_TIM10=y +CONFIG_STM32_HAVE_TIM11=y +CONFIG_STM32_HAVE_TIM12=y +CONFIG_STM32_HAVE_TIM13=y +CONFIG_STM32_HAVE_TIM14=y +# CONFIG_STM32_HAVE_TIM15 is not set +# CONFIG_STM32_HAVE_TIM16 is not set +# CONFIG_STM32_HAVE_TIM17 is not set +CONFIG_STM32_HAVE_ADC2=y +CONFIG_STM32_HAVE_ADC3=y +# CONFIG_STM32_HAVE_ADC4 is not set +# CONFIG_STM32_HAVE_ADC1_DMA is not set +# CONFIG_STM32_HAVE_ADC2_DMA is not set +# CONFIG_STM32_HAVE_ADC3_DMA is not set +# CONFIG_STM32_HAVE_ADC4_DMA is not set +CONFIG_STM32_HAVE_CAN1=y +CONFIG_STM32_HAVE_CAN2=y +CONFIG_STM32_HAVE_DAC1=y +CONFIG_STM32_HAVE_DAC2=y +CONFIG_STM32_HAVE_RNG=y +CONFIG_STM32_HAVE_ETHMAC=y +CONFIG_STM32_HAVE_I2C2=y +CONFIG_STM32_HAVE_I2C3=y +CONFIG_STM32_HAVE_SPI2=y +CONFIG_STM32_HAVE_SPI3=y +# CONFIG_STM32_HAVE_SPI4 is not set +# CONFIG_STM32_HAVE_SPI5 is not set +# CONFIG_STM32_HAVE_SPI6 is not set +# CONFIG_STM32_HAVE_SAIPLL is not set +# CONFIG_STM32_HAVE_I2SPLL is not set +# CONFIG_STM32_ADC1 is not set +# CONFIG_STM32_ADC2 is not set +# CONFIG_STM32_ADC3 is not set +# CONFIG_STM32_BKPSRAM is not set +# CONFIG_STM32_CAN1 is not set +# CONFIG_STM32_CAN2 is not set +# CONFIG_STM32_CCMDATARAM is not set +# CONFIG_STM32_CRC is not set +# CONFIG_STM32_CRYP is not set +# CONFIG_STM32_DMA1 is not set +# CONFIG_STM32_DMA2 is not set +# CONFIG_STM32_DAC1 is not set +# CONFIG_STM32_DAC2 is not set +# CONFIG_STM32_DCMI is not set +# CONFIG_STM32_ETHMAC is not set +# CONFIG_STM32_FSMC is not set +# CONFIG_STM32_HASH is not set +# CONFIG_STM32_I2C1 is not set +# CONFIG_STM32_I2C2 is not set +# CONFIG_STM32_I2C3 is not set +# CONFIG_STM32_OTGFS is not set +# CONFIG_STM32_OTGHS is not set +CONFIG_STM32_PWR=y +# CONFIG_STM32_RNG is not set +# CONFIG_STM32_SDIO is not set +# CONFIG_STM32_SPI1 is not set +# CONFIG_STM32_SPI2 is not set +# CONFIG_STM32_SPI3 is not set +CONFIG_STM32_SYSCFG=y +# CONFIG_STM32_TIM1 is not set +# CONFIG_STM32_TIM2 is not set +# CONFIG_STM32_TIM3 is not set +# CONFIG_STM32_TIM4 is not set +# CONFIG_STM32_TIM5 is not set +# CONFIG_STM32_TIM6 is not set +# CONFIG_STM32_TIM7 is not set +# CONFIG_STM32_TIM8 is not set +# CONFIG_STM32_TIM9 is not set +# CONFIG_STM32_TIM10 is not set +# CONFIG_STM32_TIM11 is not set +# CONFIG_STM32_TIM12 is not set +# CONFIG_STM32_TIM13 is not set +# CONFIG_STM32_TIM14 is not set +# CONFIG_STM32_USART1 is not set +CONFIG_STM32_USART2=y +# CONFIG_STM32_USART3 is not set +# CONFIG_STM32_UART4 is not set +# CONFIG_STM32_UART5 is not set +# CONFIG_STM32_USART6 is not set +# CONFIG_STM32_IWDG is not set +# CONFIG_STM32_WWDG is not set +# CONFIG_STM32_NOEXT_VECTORS is not set + +# +# Alternate Pin Mapping +# +# CONFIG_STM32_FLASH_PREFETCH is not set +# CONFIG_STM32_JTAG_DISABLE is not set +# CONFIG_STM32_JTAG_FULL_ENABLE is not set +# CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set +CONFIG_STM32_JTAG_SW_ENABLE=y +# CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG is not set +# CONFIG_STM32_FORCEPOWER is not set +# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set +# CONFIG_STM32_CCMEXCLUDE is not set + +# +# Timer Configuration +# +# CONFIG_STM32_TIM1_CAP is not set +# CONFIG_STM32_TIM2_CAP is not set +# CONFIG_STM32_TIM3_CAP is not set +# CONFIG_STM32_TIM4_CAP is not set +# CONFIG_STM32_TIM5_CAP is not set +# CONFIG_STM32_TIM8_CAP is not set +# CONFIG_STM32_TIM9_CAP is not set +# CONFIG_STM32_TIM10_CAP is not set +# CONFIG_STM32_TIM11_CAP is not set +# CONFIG_STM32_TIM12_CAP is not set +# CONFIG_STM32_TIM13_CAP is not set +# CONFIG_STM32_TIM14_CAP is not set +CONFIG_STM32_USART=y +CONFIG_STM32_SERIALDRIVER=y # # U[S]ART Configuration # -# CONFIG_STM32F7_FLOWCONTROL_BROKEN is not set -# CONFIG_STM32F7_USART_BREAKS is not set -# CONFIG_STM32F7_CUSTOM_CLOCKCONFIG is not set # -# Timer Configuration +# U[S]ART Device Configuration +# +CONFIG_STM32_USART2_SERIALDRIVER=y +# CONFIG_STM32_USART2_1WIREDRIVER is not set +# CONFIG_USART2_RS485 is not set + +# +# Serial Driver Configuration +# +# CONFIG_SERIAL_DISABLE_REORDERING is not set +# CONFIG_STM32_FLOWCONTROL_BROKEN is not set +# CONFIG_STM32_USART_BREAKS is not set +# CONFIG_STM32_USART_SINGLEWIRE is not set +# CONFIG_STM32_HAVE_RTC_COUNTER is not set +# CONFIG_STM32_HAVE_RTC_SUBSECONDS is not set + +# +# USB FS Host Configuration # # -# Ethernet MAC configuration +# USB HS Host Configuration +# + +# +# USB Host Debug Configuration +# + +# +# USB Device Configuration # -CONFIG_STM32F7_PHYADDR=0 -# CONFIG_STM32F7_PHYINIT is not set -# CONFIG_STM32F7_MII is not set -CONFIG_STM32F7_AUTONEG=y -CONFIG_STM32F7_PHYSR=31 -CONFIG_STM32F7_PHYSR_ALTCONFIG=y -CONFIG_STM32F7_PHYSR_ALTMODE=0x001c -CONFIG_STM32F7_PHYSR_10HD=0x0004 -CONFIG_STM32F7_PHYSR_100HD=0x0008 -CONFIG_STM32F7_PHYSR_10FD=0x0014 -CONFIG_STM32F7_PHYSR_100FD=0x0018 -# CONFIG_STM32F7_ETH_PTP is not set -CONFIG_STM32F7_RMII=y -# CONFIG_STM32F7_RMII_MCO1 is not set -# CONFIG_STM32F7_RMII_MCO2 is not set -CONFIG_STM32F7_RMII_EXTCLK=y # # Architecture Options @@ -392,7 +504,7 @@ CONFIG_ARCH_HAVE_MPU=y # CONFIG_ARCH_NAND_HWECC is not set # CONFIG_ARCH_HAVE_EXTCLK is not set # CONFIG_ARCH_HAVE_POWEROFF is not set -# CONFIG_ARCH_HAVE_RESET is not set +CONFIG_ARCH_HAVE_RESET=y # CONFIG_ARCH_USE_MPU is not set # CONFIG_ARCH_IRQPRIO is not set CONFIG_ARCH_STACKDUMP=y @@ -405,7 +517,7 @@ CONFIG_ARCH_HAVE_RAMVECTORS=y # # Board Settings # -CONFIG_BOARD_LOOPSPERMSEC=43103 +CONFIG_BOARD_LOOPSPERMSEC=16717 # CONFIG_ARCH_CALIBRATION is not set # @@ -428,34 +540,32 @@ CONFIG_BOOT_RUNFROMFLASH=y # # Boot Memory Configuration # -CONFIG_RAM_START=0x20010000 -CONFIG_RAM_SIZE=245760 +CONFIG_RAM_START=0x20000000 +CONFIG_RAM_SIZE=114688 # CONFIG_ARCH_HAVE_SDRAM is not set # # Board Selection # -CONFIG_ARCH_BOARD_CUSTOM=y - -# -# Custom Board Configuration -# -CONFIG_ARCH_BOARD_CUSTOM_NAME="" -CONFIG_ARCH_BOARD_CUSTOM_DIR="" -# CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH is not set -# CONFIG_BOARD_CRASHDUMP is not set -# CONFIG_BOARD_CUSTOM_LEDS is not set -# CONFIG_BOARD_CUSTOM_BUTTONS is not set -# CONFIG_BOARD_CUSTOM_INTERRUPT is not set +# CONFIG_ARCH_BOARD_OLIMEX_STM32H407 is not set +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="olimex-stm32-e407" # # Common Board Options # -CONFIG_NSH_MMCSDMINOR=0 +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_HAVE_IRQBUTTONS=y +# CONFIG_ARCH_IRQBUTTONS is not set # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set # CONFIG_LIB_BOARDCTL is not set # @@ -479,8 +589,8 @@ CONFIG_START_YEAR=2011 CONFIG_START_MONTH=12 CONFIG_START_DAY=6 CONFIG_MAX_WDOGPARMS=2 -CONFIG_PREALLOC_WDOGS=4 -CONFIG_WDOG_INTRESERVE=0 +CONFIG_PREALLOC_WDOGS=16 +CONFIG_WDOG_INTRESERVE=4 CONFIG_PREALLOC_TIMERS=4 # @@ -492,7 +602,7 @@ CONFIG_INIT_ENTRYPOINT=y CONFIG_USER_ENTRYPOINT="nsh_main" CONFIG_RR_INTERVAL=200 # CONFIG_SCHED_SPORADIC is not set -CONFIG_TASK_NAME_SIZE=0 +CONFIG_TASK_NAME_SIZE=31 CONFIG_MAX_TASKS=16 # CONFIG_SCHED_HAVE_PARENT is not set CONFIG_SCHED_WAITPID=y @@ -528,7 +638,6 @@ CONFIG_NAME_MAX=32 # CONFIG_SCHED_STARTHOOK is not set # CONFIG_SCHED_ATEXIT is not set # CONFIG_SCHED_ONEXIT is not set -# CONFIG_SIG_EVTHREAD is not set # # Signal Numbers @@ -537,7 +646,6 @@ CONFIG_SIG_SIGUSR1=1 CONFIG_SIG_SIGUSR2=2 CONFIG_SIG_SIGALARM=3 CONFIG_SIG_SIGCONDTIMEDOUT=16 -CONFIG_SIG_SIGWORK=17 # # POSIX Message Queue Options @@ -549,11 +657,8 @@ CONFIG_MQ_MAXMSGSIZE=32 # # Work queue support # -CONFIG_SCHED_WORKQUEUE=y -CONFIG_SCHED_HPWORK=y -CONFIG_SCHED_HPWORKPRIORITY=224 -CONFIG_SCHED_HPWORKPERIOD=50000 -CONFIG_SCHED_HPWORKSTACKSIZE=2048 +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_HPWORK is not set # CONFIG_SCHED_LPWORK is not set # @@ -585,16 +690,7 @@ CONFIG_DEV_NULL=y # CONFIG_PWM is not set CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set -CONFIG_SPI=y -# CONFIG_SPI_SLAVE is not set -CONFIG_SPI_EXCHANGE=y -# CONFIG_SPI_CMDDATA is not set -# CONFIG_SPI_CALLBACK is not set -# CONFIG_SPI_BITBANG is not set -# CONFIG_SPI_HWFEATURES is not set -# CONFIG_SPI_CRCGENERATION is not set -# CONFIG_SPI_CS_CONTROL is not set -# CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_SPI is not set # CONFIG_I2S is not set # @@ -608,7 +704,12 @@ CONFIG_SPI_EXCHANGE=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -619,6 +720,7 @@ CONFIG_SPI_EXCHANGE=y # # LED Support # +# CONFIG_USERLED is not set # CONFIG_RGBLED is not set # CONFIG_PCA9635PW is not set # CONFIG_NCP5623C is not set @@ -626,48 +728,6 @@ CONFIG_SPI_EXCHANGE=y # CONFIG_MODEM is not set # CONFIG_MTD is not set # CONFIG_EEPROM is not set -CONFIG_NETDEVICES=y - -# -# General Ethernet MAC Driver Options -# -# CONFIG_NETDEV_LOOPBACK is not set -CONFIG_NETDEV_TELNET=y -CONFIG_TELNET_RXBUFFER_SIZE=256 -CONFIG_TELNET_TXBUFFER_SIZE=256 -# CONFIG_NETDEV_MULTINIC is not set -# CONFIG_ARCH_HAVE_NETDEV_STATISTICS is not set -# CONFIG_NETDEV_LATEINIT is not set - -# -# External Ethernet MAC Device Support -# -# CONFIG_NET_DM90x0 is not set -# CONFIG_ENC28J60 is not set -# CONFIG_ENCX24J600 is not set -# CONFIG_NET_E1000 is not set -# CONFIG_NET_SLIP is not set -# CONFIG_NET_FTMAC100 is not set -# CONFIG_NET_VNET is not set - -# -# External Ethernet PHY Device Support -# -# CONFIG_ARCH_PHY_INTERRUPT is not set -# CONFIG_ETH0_PHY_NONE is not set -# CONFIG_ETH0_PHY_AM79C874 is not set -# CONFIG_ETH0_PHY_KS8721 is not set -# CONFIG_ETH0_PHY_KSZ8041 is not set -# CONFIG_ETH0_PHY_KSZ8051 is not set -# CONFIG_ETH0_PHY_KSZ8061 is not set -# CONFIG_ETH0_PHY_KSZ8081 is not set -# CONFIG_ETH0_PHY_KSZ90x1 is not set -# CONFIG_ETH0_PHY_DP83848C is not set -# CONFIG_ETH0_PHY_LAN8720 is not set -# CONFIG_ETH0_PHY_LAN8740 is not set -# CONFIG_ETH0_PHY_LAN8740A is not set -CONFIG_ETH0_PHY_LAN8742A=y -# CONFIG_ETH0_PHY_DM9161 is not set # CONFIG_PIPES is not set # CONFIG_PM is not set # CONFIG_POWER is not set @@ -692,11 +752,11 @@ CONFIG_SERIAL_CONSOLE=y # CONFIG_SCI1_SERIALDRIVER is not set # CONFIG_USART0_SERIALDRIVER is not set # CONFIG_USART1_SERIALDRIVER is not set -# CONFIG_USART2_SERIALDRIVER is not set +CONFIG_USART2_SERIALDRIVER=y # CONFIG_USART3_SERIALDRIVER is not set # CONFIG_USART4_SERIALDRIVER is not set # CONFIG_USART5_SERIALDRIVER is not set -CONFIG_USART6_SERIALDRIVER=y +# CONFIG_USART6_SERIALDRIVER is not set # CONFIG_USART7_SERIALDRIVER is not set # CONFIG_USART8_SERIALDRIVER is not set # CONFIG_OTHER_UART_SERIALDRIVER is not set @@ -706,22 +766,22 @@ CONFIG_STANDARD_SERIAL=y # CONFIG_SERIAL_OFLOWCONTROL is not set # CONFIG_SERIAL_DMA is not set CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y -CONFIG_USART6_SERIAL_CONSOLE=y +CONFIG_USART2_SERIAL_CONSOLE=y # CONFIG_OTHER_SERIAL_CONSOLE is not set # CONFIG_NO_SERIAL_CONSOLE is not set # -# USART6 Configuration +# USART2 Configuration # -CONFIG_USART6_RXBUFSIZE=256 -CONFIG_USART6_TXBUFSIZE=256 -CONFIG_USART6_BAUD=115200 -CONFIG_USART6_BITS=8 -CONFIG_USART6_PARITY=0 -CONFIG_USART6_2STOP=0 -# CONFIG_USART6_IFLOWCONTROL is not set -# CONFIG_USART6_OFLOWCONTROL is not set -# CONFIG_USART6_DMA is not set +CONFIG_USART2_RXBUFSIZE=128 +CONFIG_USART2_TXBUFSIZE=128 +CONFIG_USART2_BAUD=115200 +CONFIG_USART2_BITS=8 +CONFIG_USART2_PARITY=0 +CONFIG_USART2_2STOP=0 +# CONFIG_USART2_IFLOWCONTROL is not set +# CONFIG_USART2_OFLOWCONTROL is not set +# CONFIG_USART2_DMA is not set # CONFIG_USBDEV is not set # CONFIG_USBHOST is not set # CONFIG_DRIVERS_WIRELESS is not set @@ -742,131 +802,9 @@ CONFIG_SYSLOG_CONSOLE=y # # Networking Support # -CONFIG_ARCH_HAVE_NET=y -CONFIG_ARCH_HAVE_PHY=y -CONFIG_NET=y -CONFIG_NET_NOINTS=y -# CONFIG_NET_PROMISCUOUS is not set - -# -# Driver buffer configuration -# -CONFIG_NET_MULTIBUFFER=y -CONFIG_NET_ETH_MTU=1294 -CONFIG_NET_ETH_TCP_RECVWNDO=1220 -CONFIG_NET_GUARDSIZE=2 - -# -# Data link support -# -# CONFIG_NET_MULTILINK is not set -CONFIG_NET_ETHERNET=y -# CONFIG_NET_LOOPBACK is not set -# CONFIG_NET_TUN is not set - -# -# Network Device Operations -# -# CONFIG_NETDEV_PHY_IOCTL is not set - -# -# Internet Protocol Selection -# -CONFIG_NET_IPv4=y -CONFIG_NET_IPv6=y -CONFIG_NET_IPv6_NCONF_ENTRIES=8 - -# -# Socket Support -# -CONFIG_NSOCKET_DESCRIPTORS=8 -CONFIG_NET_NACTIVESOCKETS=16 -CONFIG_NET_SOCKOPTS=y -# CONFIG_NET_SOLINGER is not set - -# -# Raw Socket Support -# -# CONFIG_NET_PKT is not set - -# -# Unix Domain Socket Support -# -# CONFIG_NET_LOCAL is not set - -# -# TCP/IP Networking -# -CONFIG_NET_TCP=y -# CONFIG_NET_TCPURGDATA is not set -CONFIG_NET_TCP_CONNS=8 -CONFIG_NET_MAX_LISTENPORTS=20 -# CONFIG_NET_TCP_READAHEAD is not set -CONFIG_NET_TCP_WRITE_BUFFERS=y -CONFIG_NET_TCP_NWRBCHAINS=8 -CONFIG_NET_TCP_RECVDELAY=0 -CONFIG_NET_TCPBACKLOG=y -# CONFIG_NET_SENDFILE is not set - -# -# UDP Networking -# -CONFIG_NET_UDP=y -CONFIG_NET_UDP_CHECKSUMS=y -CONFIG_NET_UDP_CONNS=8 -CONFIG_NET_BROADCAST=y -# CONFIG_NET_RXAVAIL is not set -CONFIG_NET_UDP_READAHEAD=y - -# -# ICMP Networking Support -# -CONFIG_NET_ICMP=y -CONFIG_NET_ICMP_PING=y - -# -# ICMPv6 Networking Support -# -CONFIG_NET_ICMPv6=y -CONFIG_NET_ICMPv6_PING=y -CONFIG_NET_ICMPv6_NEIGHBOR=y -CONFIG_ICMPv6_NEIGHBOR_MAXTRIES=5 -CONFIG_ICMPv6_NEIGHBOR_DELAYMSEC=20 -# CONFIG_NET_ICMPv6_AUTOCONF is not set -# CONFIG_NET_ICMPv6_ROUTER is not set - -# -# IGMPv2 Client Support -# -# CONFIG_NET_IGMP is not set - -# -# ARP Configuration -# -CONFIG_NET_ARP=y -CONFIG_NET_ARPTAB_SIZE=16 -CONFIG_NET_ARP_MAXAGE=120 -CONFIG_NET_ARP_IPIN=y -CONFIG_NET_ARP_SEND=y -CONFIG_ARP_SEND_MAXTRIES=5 -CONFIG_ARP_SEND_DELAYMSEC=20 - -# -# Network I/O Buffer Support -# -CONFIG_NET_IOB=y -CONFIG_IOB_NBUFFERS=24 -CONFIG_IOB_BUFSIZE=196 -CONFIG_IOB_NCHAINS=8 -# CONFIG_NET_ARCH_INCR32 is not set -# CONFIG_NET_ARCH_CHKSUM is not set -# CONFIG_NET_STATISTICS is not set - -# -# Routing Table Configuration -# -# CONFIG_NET_ROUTE is not set -CONFIG_NET_HOSTNAME="STM32F746G-DISCO" +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set # # Crypto API @@ -883,19 +821,26 @@ CONFIG_NET_HOSTNAME="STM32F746G-DISCO" # CONFIG_DISABLE_MOUNTPOINT is not set # CONFIG_FS_AUTOMOUNTER is not set # CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set -# CONFIG_FS_READABLE is not set +CONFIG_FS_READABLE=y # CONFIG_FS_WRITABLE is not set # CONFIG_FS_NAMED_SEMAPHORES is not set CONFIG_FS_MQUEUE_MPATH="/var/mqueue" # CONFIG_FS_RAMMAP is not set # CONFIG_FS_FAT is not set -# CONFIG_NFS is not set # CONFIG_FS_NXFFS is not set # CONFIG_FS_ROMFS is not set # CONFIG_FS_TMPFS is not set # CONFIG_FS_SMARTFS is not set # CONFIG_FS_BINFS is not set -# CONFIG_FS_PROCFS is not set +CONFIG_FS_PROCFS=y +# CONFIG_FS_PROCFS_REGISTER is not set + +# +# Exclude individual procfs entries +# +# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set +# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set +# CONFIG_FS_PROCFS_EXCLUDE_MOUNTS is not set # CONFIG_FS_UNIONFS is not set # @@ -965,8 +910,8 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set CONFIG_ARCH_HAVE_TLS=y # CONFIG_TLS is not set -CONFIG_LIBC_NETDB=y -# CONFIG_NETDB_DNSCLIENT is not set +# CONFIG_LIBC_NETDB is not set +# CONFIG_NETDB_HOSTFILE is not set # # Non-standard Library Support @@ -1004,17 +949,20 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # # Examples # +# CONFIG_EXAMPLES_BUTTONS is not set # CONFIG_EXAMPLES_CHAT is not set # CONFIG_EXAMPLES_CONFIGDATA is not set # CONFIG_EXAMPLES_CPUHOG is not set # CONFIG_EXAMPLES_CXXTEST is not set # CONFIG_EXAMPLES_DHCPD is not set -# CONFIG_EXAMPLES_DISCOVER is not set # CONFIG_EXAMPLES_ELF is not set # CONFIG_EXAMPLES_FTPC is not set # CONFIG_EXAMPLES_FTPD is not set -# CONFIG_EXAMPLES_HELLO is not set -# CONFIG_EXAMPLES_HELLOXX is not set +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_HELLO_PRIORITY=100 +CONFIG_EXAMPLES_HELLO_STACKSIZE=2048 +CONFIG_EXAMPLES_HELLOXX=y +CONFIG_EXAMPLES_HELLOXX_CXXINITIALIZE=y # CONFIG_EXAMPLES_HIDKBD is not set # CONFIG_EXAMPLES_IGMP is not set # CONFIG_EXAMPLES_JSON is not set @@ -1023,7 +971,6 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_EXAMPLES_MM is not set # CONFIG_EXAMPLES_MODBUS is not set # CONFIG_EXAMPLES_MOUNT is not set -# CONFIG_EXAMPLES_NETTEST is not set # CONFIG_EXAMPLES_NRF24L01TERM is not set CONFIG_EXAMPLES_NSH=y CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y @@ -1054,8 +1001,6 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # CONFIG_EXAMPLES_TELNETD is not set # CONFIG_EXAMPLES_TIFF is not set # CONFIG_EXAMPLES_TOUCHSCREEN is not set -# CONFIG_EXAMPLES_UDP is not set -# CONFIG_EXAMPLES_UDPBLASTER is not set # CONFIG_EXAMPLES_USBTERM is not set # CONFIG_EXAMPLES_WATCHDOG is not set # CONFIG_EXAMPLES_WEBSERVER is not set @@ -1064,6 +1009,7 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # File System Utilities # # CONFIG_FSUTILS_INIFILE is not set +# CONFIG_FSUTILS_PASSWD is not set # # GPS Utilities @@ -1079,6 +1025,7 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # # Interpreters # +# CONFIG_INTERPRETERS_BAS is not set # CONFIG_INTERPRETERS_FICL is not set # CONFIG_INTERPRETERS_MICROPYTHON is not set # CONFIG_INTERPRETERS_PCODE is not set @@ -1092,21 +1039,10 @@ CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y # Network Utilities # # CONFIG_NETUTILS_CODECS is not set -# CONFIG_NETUTILS_DHCPC is not set -# CONFIG_NETUTILS_DHCPD is not set -# CONFIG_NETUTILS_DISCOVER is not set # CONFIG_NETUTILS_ESP8266 is not set # CONFIG_NETUTILS_FTPC is not set # CONFIG_NETUTILS_JSON is not set -CONFIG_NETUTILS_NETLIB=y -# CONFIG_NETUTILS_NTPCLIENT is not set -# CONFIG_NETUTILS_PPPD is not set # CONFIG_NETUTILS_SMTP is not set -CONFIG_NETUTILS_TELNETD=y -# CONFIG_NETUTILS_TFTPC is not set -# CONFIG_NETUTILS_WEBCLIENT is not set -# CONFIG_NETUTILS_WEBSERVER is not set -# CONFIG_NETUTILS_XMLRPC is not set # # NSH Library @@ -1121,9 +1057,9 @@ CONFIG_NSH_READLINE=y # CONFIG_NSH_CLE is not set CONFIG_NSH_LINELEN=64 # CONFIG_NSH_DISABLE_SEMICOLON is not set -CONFIG_NSH_CMDPARMS=y +# CONFIG_NSH_CMDPARMS is not set CONFIG_NSH_MAXARGUMENTS=6 -CONFIG_NSH_ARGCAT=y +# CONFIG_NSH_ARGCAT is not set CONFIG_NSH_NESTDEPTH=3 # CONFIG_NSH_DISABLEBG is not set CONFIG_NSH_BUILTIN_APPS=y @@ -1132,7 +1068,6 @@ CONFIG_NSH_BUILTIN_APPS=y # Disable Individual commands # # CONFIG_NSH_DISABLE_ADDROUTE is not set -# CONFIG_NSH_DISABLE_ARP is not set # CONFIG_NSH_DISABLE_BASENAME is not set # CONFIG_NSH_DISABLE_CAT is not set # CONFIG_NSH_DISABLE_CD is not set @@ -1151,7 +1086,7 @@ CONFIG_NSH_DISABLE_DATE=y # CONFIG_NSH_DISABLE_HELP is not set # CONFIG_NSH_DISABLE_HEXDUMP is not set # CONFIG_NSH_DISABLE_IFCONFIG is not set -CONFIG_NSH_DISABLE_IFUPDOWN=y +# CONFIG_NSH_DISABLE_IFUPDOWN is not set # CONFIG_NSH_DISABLE_KILL is not set # CONFIG_NSH_DISABLE_LOSETUP is not set CONFIG_NSH_DISABLE_LOSMART=y @@ -1165,7 +1100,6 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_MV is not set # CONFIG_NSH_DISABLE_MW is not set # CONFIG_NSH_DISABLE_PS is not set -# CONFIG_NSH_DISABLE_PING is not set # CONFIG_NSH_DISABLE_PUT is not set # CONFIG_NSH_DISABLE_PWD is not set # CONFIG_NSH_DISABLE_RM is not set @@ -1181,13 +1115,15 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 # # Configure Command Options # -CONFIG_NSH_CMDOPT_DF_H=y +# CONFIG_NSH_CMDOPT_DF_H is not set CONFIG_NSH_CODECS_BUFSIZE=128 -CONFIG_NSH_CMDOPT_HEXDUMP=y +# CONFIG_NSH_CMDOPT_HEXDUMP is not set +CONFIG_NSH_PROC_MOUNTPOINT="/proc" CONFIG_NSH_FILEIOSIZE=512 # @@ -1201,78 +1137,10 @@ CONFIG_NSH_FILEIOSIZE=512 # Console Configuration # CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_ALTCONDEV is not set # CONFIG_NSH_ARCHINIT is not set - -# -# Networking Configuration -# -CONFIG_NSH_NETINIT=y -# CONFIG_NSH_NETINIT_THREAD is not set - -# -# IP Address Configuration -# - -# -# IPv4 Addresses -# -CONFIG_NSH_IPADDR=0x0a000002 -CONFIG_NSH_DRIPADDR=0x0a000001 -CONFIG_NSH_NETMASK=0xffffff00 - -# -# Target IPv6 address -# -CONFIG_NSH_IPv6ADDR_1=0xfc00 -CONFIG_NSH_IPv6ADDR_2=0x0000 -CONFIG_NSH_IPv6ADDR_3=0x0000 -CONFIG_NSH_IPv6ADDR_4=0x0000 -CONFIG_NSH_IPv6ADDR_5=0x0000 -CONFIG_NSH_IPv6ADDR_6=0x0000 -CONFIG_NSH_IPv6ADDR_7=0x0000 -CONFIG_NSH_IPv6ADDR_8=0x0002 - -# -# Router IPv6 address -# -CONFIG_NSH_DRIPv6ADDR_1=0xfc00 -CONFIG_NSH_DRIPv6ADDR_2=0x0000 -CONFIG_NSH_DRIPv6ADDR_3=0x0000 -CONFIG_NSH_DRIPv6ADDR_4=0x0000 -CONFIG_NSH_DRIPv6ADDR_5=0x0000 -CONFIG_NSH_DRIPv6ADDR_6=0x0000 -CONFIG_NSH_DRIPv6ADDR_7=0x0000 -CONFIG_NSH_DRIPv6ADDR_8=0x0001 - -# -# IPv6 Network mask -# -CONFIG_NSH_IPv6NETMASK_1=0xffff -CONFIG_NSH_IPv6NETMASK_2=0xffff -CONFIG_NSH_IPv6NETMASK_3=0xffff -CONFIG_NSH_IPv6NETMASK_4=0xffff -CONFIG_NSH_IPv6NETMASK_5=0xffff -CONFIG_NSH_IPv6NETMASK_6=0xffff -CONFIG_NSH_IPv6NETMASK_7=0xffff -CONFIG_NSH_IPv6NETMASK_8=0x0000 -CONFIG_NSH_NOMAC=y -CONFIG_NSH_SWMAC=y -CONFIG_NSH_MACADDR=0x00e0deadbeef -CONFIG_NSH_MAX_ROUNDTRIP=20 - -# -# Telnet Configuration -# -CONFIG_NSH_TELNET=y -CONFIG_NSH_TELNETD_PORT=23 -CONFIG_NSH_TELNETD_DAEMONPRIO=100 -CONFIG_NSH_TELNETD_DAEMONSTACKSIZE=2048 -CONFIG_NSH_TELNETD_CLIENTPRIO=100 -CONFIG_NSH_TELNETD_CLIENTSTACKSIZE=2048 -CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_NSH_LOGIN is not set # CONFIG_NSH_CONSOLE_LOGIN is not set -# CONFIG_NSH_TELNET_LOGIN is not set # # NxWidgets/NxWM @@ -1289,10 +1157,9 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_NETDB is not set # CONFIG_SYSTEM_RAMTEST is not set CONFIG_READLINE_HAVE_EXTMATCH=y CONFIG_SYSTEM_READLINE=y diff --git a/configs/olimex-stm32-e407/nsh/setenv.sh b/configs/olimex-stm32-e407/nsh/setenv.sh new file mode 100755 index 0000000000000000000000000000000000000000..ded7c15537f64b686d934eb7550a1917dbb8f2f5 --- /dev/null +++ b/configs/olimex-stm32-e407/nsh/setenv.sh @@ -0,0 +1,80 @@ +#!/bin/bash +# configs/olimex-stm32-e407/nsh/setenv.sh +# +# Copyright (C) 2011-2012 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the RIDE +# toolchain under windows. You will also have to edit this if you install +# the RIDE toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Raisonance/Ride/arm-gcc/bin" + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" +#export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" + +# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors" +# You can this free toolchain here https://launchpad.net/gcc-arm-embedded +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin" + +# These are the Cygwin paths to the locations where I installed the Atollic +# toolchain under windows. You will also have to edit this if you install +# the Atollic toolchain in any other location. /usr/bin is added before +# the Atollic bin path because there is are binaries named gcc.exe and g++.exe +# at those locations as well. +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin" +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +#export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH variable +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/configs/olimex-stm32-e407/scripts/ld.script b/configs/olimex-stm32-e407/scripts/ld.script new file mode 100644 index 0000000000000000000000000000000000000000..d24be46787cc32750046d80898d089f92b6349fe --- /dev/null +++ b/configs/olimex-stm32-e407/scripts/ld.script @@ -0,0 +1,122 @@ +/**************************************************************************** + * configs/olimex-stm32-e407/scripts/ld.script + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/* The STM32F407ZGT6 has 1024Kb of FLASH beginning at address 0x0800:0000 and + * 192Kb of SRAM. SRAM is split up into two blocks: + * + * 1) 112Kb of SRAM beginning at address 0x2000:0000 + * 2) 16Kb of SRAM beginning at address 0x2001:c000 + * 3) 64Kb of SRAM beginning at address 0x2002:0000 + * + * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000 + * where the code expects to begin execution by jumping to the entry point in + * the 0x0800:0000 address + * range. + */ + +MEMORY +{ + flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K + sram (rwx) : ORIGIN = 0x20000000, LENGTH = 112K +} + +OUTPUT_ARCH(arm) +ENTRY(_stext) +SECTIONS +{ + .text : { + _stext = ABSOLUTE(.); + *(.vectors) + *(.text .text.*) + *(.fixup) + *(.gnu.warning) + *(.rodata .rodata.*) + *(.gnu.linkonce.t.*) + *(.glue_7) + *(.glue_7t) + *(.got) + *(.gcc_except_table) + *(.gnu.linkonce.r.*) + _etext = ABSOLUTE(.); + } > flash + + .init_section : { + _sinit = ABSOLUTE(.); + *(.init_array .init_array.*) + _einit = ABSOLUTE(.); + } > flash + + .ARM.extab : { + *(.ARM.extab*) + } > flash + + __exidx_start = ABSOLUTE(.); + .ARM.exidx : { + *(.ARM.exidx*) + } > flash + __exidx_end = ABSOLUTE(.); + + _eronly = ABSOLUTE(.); + + .data : { + _sdata = ABSOLUTE(.); + *(.data .data.*) + *(.gnu.linkonce.d.*) + CONSTRUCTORS + _edata = ABSOLUTE(.); + } > sram AT > flash + + .bss : { + _sbss = ABSOLUTE(.); + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + _ebss = ABSOLUTE(.); + } > sram + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_info 0 : { *(.debug_info) } + .debug_line 0 : { *(.debug_line) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_aranges 0 : { *(.debug_aranges) } +} diff --git a/configs/olimex-stm32-e407/src/Makefile b/configs/olimex-stm32-e407/src/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..652e7a5577d66571b8f450b2f8667e1fc55ac634 --- /dev/null +++ b/configs/olimex-stm32-e407/src/Makefile @@ -0,0 +1,83 @@ +############################################################################ +# configs/olimex-stm32-e407/src/Makefile +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ASRCS = +CSRCS = stm32_boot.c + +ifeq ($(CONFIG_ARCH_LEDS),y) +CSRCS += stm32_autoleds.c +else +CSRCS += stm32_userleds.c +endif + +ifeq ($(CONFIG_ARCH_BUTTONS),y) +CSRCS += stm32_buttons.c +endif + +ifeq ($(CONFIG_NSH_LIBRARY),y) +CSRCS += stm32_appinit.c +endif + +ifeq ($(CONFIG_ARCH_IDLE_CUSTOM),y) +CSRCS += stm32_idle.c +endif + +ifeq ($(CONFIG_STM32_FSMC),y) +CSRCS += stm32_extmem.c +endif + +ifeq ($(CONFIG_STM32_OTGFS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_STM32_OTGHS),y) +CSRCS += stm32_usb.c +endif + +ifeq ($(CONFIG_ADC),y) +CSRCS += stm32_adc.c +endif + +ifeq ($(CONFIG_CAN),y) +CSRCS += stm32_can.c +endif + +ifeq ($(CONFIG_ARCH_FPU),y) +CSRCS += stm32_ostest.c +endif + +include $(TOPDIR)/configs/Board.mk diff --git a/configs/olimex-stm32-e407/src/olimex-stm32-e407.h b/configs/olimex-stm32-e407/src/olimex-stm32-e407.h new file mode 100644 index 0000000000000000000000000000000000000000..3294e189e4bf687d0a8c395f884e7c4245bfbd5f --- /dev/null +++ b/configs/olimex-stm32-e407/src/olimex-stm32-e407.h @@ -0,0 +1,246 @@ +/**************************************************************************** + * configs/olimex-stm32-e407/src/olimex-stm32-e407.h + * + * Copyright (C) 2014 Max Holtzberg. All rights reserved. + * Author: Max Holtzberg + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __CONFIGS_OLIMEX_STM32_E407_SRC_H +#define __CONFIGS_OLIMEX_STM32_E407_SRC_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration from stm32f4discovert*/ + +/* Assume that we have everything */ + +#define HAVE_USBDEV 1 +#define HAVE_USBHOST 1 +#define HAVE_USBMONITOR 1 +#define HAVE_SDIO 1 +#define HAVE_RTC_DRIVER 1 +#define HAVE_ELF 1 +#define HAVE_NETMONITOR 1 + +/* Can't support USB host or device features if USB OTG FS is not enabled */ + +#ifndef CONFIG_STM32_OTGFS +# undef HAVE_USBDEV +# undef HAVE_USBHOST +# undef HAVE_USBMONITOR +#endif + +/* Can't support USB device monitor if USB device is not enabled */ + +#ifndef CONFIG_USBDEV +# undef HAVE_USBDEV +# undef HAVE_USBMONITOR +#endif + +/* Can't support USB host is USB host is not enabled */ + +#ifndef CONFIG_USBHOST +# undef HAVE_USBHOST +#endif + +/* Check if we should enable the USB monitor before starting NSH */ + +#if !defined(CONFIG_USBDEV_TRACE) || !defined(CONFIG_USBMONITOR) +# undef HAVE_USBMONITOR +#endif + +/* ELF */ + +#if defined(CONFIG_BINFMT_DISABLE) || !defined(CONFIG_ELF) +# undef HAVE_ELF +#endif + +/* NSH Network monitor */ + +#if !defined(CONFIG_NET) || !defined(CONFIG_STM32_EMACMAC) +# undef HAVE_NETMONITOR +#endif + +#if !defined(CONFIG_NSH_NETINIT_THREAD) || !defined(CONFIG_ARCH_PHY_INTERRUPT) || \ + !defined(CONFIG_NETDEV_PHY_IOCTL) || !defined(CONFIG_NET_UDP) || \ + defined(CONFIG_DISABLE_SIGNALS) +# undef HAVE_NETMONITOR +#endif + +/* The NSH Network Monitor cannot be used with the STM32F4DIS-BB base board. + * That is because the LAN8720 is configured in REF_CLK OUT mode. In that + * mode, the PHY interrupt is not supported. The NINT pin serves instead as + * REFLCK0. + */ + +#ifdef CONFIG_STM32F4DISBB +# undef HAVE_NETMONITOR +#endif + +/* procfs File System */ + +#ifdef CONFIG_FS_PROCFS +# ifdef CONFIG_NSH_PROC_MOUNTPOINT +# define STM32_PROCFS_MOUNTPOINT CONFIG_NSH_PROC_MOUNTPOINT +# else +# define STM32_PROCFS_MOUNTPOINT "/proc" +# endif +#endif + +/* Olimex-STM32-E407 GPIOs ****************************************************/ +/* LEDs */ + +#define GPIO_LED_STATUS (GPIO_OUTPUT|GPIO_PUSHPULL|GPIO_SPEED_50MHz|\ + GPIO_OUTPUT_CLEAR|GPIO_PORTC|GPIO_PIN13) + +/* BUTTONS -- NOTE that all have EXTI interrupts configured */ + +#define MIN_IRQBUTTON BUTTON_BUT +#define MAX_IRQBUTTON BUTTON_BUT +#define NUM_IRQBUTTONS 1 + +#define GPIO_BTN_BUT (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTA|GPIO_PIN0) + +/* USB OTG FS - USB-A connector + * + * PC4 OTG_FS_VBUS VBUS sensing + * PB0 OTG_FS_PowerSwitchOn + * PB1 OTG_FS_Overcurrent + */ + +#define GPIO_OTGFS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|\ + GPIO_OPENDRAIN|GPIO_PORTA|GPIO_PIN9) +#define GPIO_OTGFS_PWRON (GPIO_OUTPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|\ + GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN0) + +#ifdef CONFIG_USBHOST +# define GPIO_OTGFS_OVER (GPIO_INPUT|GPIO_EXTI|GPIO_FLOAT|\ + GPIO_SPEED_100MHz|GPIO_PUSHPULL|\ + GPIO_PORTB|GPIO_PIN1) + +#else +# define GPIO_OTGFS_OVER (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|\ + GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN1) +#endif + +/* USB OTG HS - miniUSB connector + * + * PB13 OTG_HS_VBUS VBUS sensing (also connected to the green LED) + * PA8 OTG_HS_PowerSwitchOn + * PF11 OTG_HS_Overcurrent + */ + +#define GPIO_OTGHS_VBUS (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|GPIO_OPENDRAIN|GPIO_PORTB|GPIO_PIN13) +#define GPIO_OTGHS_PWRON (GPIO_OUTPUT|GPIO_OUTPUT_SET|GPIO_FLOAT|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTA|GPIO_PIN8) + +#ifdef CONFIG_USBHOST +# define GPIO_OTGHS_OVER (GPIO_INPUT|GPIO_EXTI|GPIO_FLOAT|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN11) + +#else +# define GPIO_OTGHS_OVER (GPIO_INPUT|GPIO_FLOAT|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTF|GPIO_PIN11) +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/**************************************************************************** + * Public data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in initialization to setup + * USB-related GPIO pins for the Olimex-STM32-H405 board. + * + ****************************************************************************/ + +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGHS) +void weak_function stm32_usbinitialize(void); +#endif + +/**************************************************************************** + * Name: stm32_sdio_initialize + * + * Description: + * Initialize SDIO-based MMC/SD card support + * + ****************************************************************************/ + +#if !defined(CONFIG_DISABLE_MOUNTPOINT) && defined(CONFIG_STM32_SDIO) +int stm32_sdio_initialize(void); +#endif + +/**************************************************************************** + * Name: stm32_adc_initialize + * + * Description: + * Called at application startup time to initialize the ADC functionality. + * + ****************************************************************************/ + +#ifdef CONFIG_ADC +int stm32_adc_initialize(void); +#endif + +/**************************************************************************** + * Name: stm32_can_initialize + * + * Description: + * Called at application startup time to initialize the CAN functionality. + * + ****************************************************************************/ + +#if defined(CONFIG_CAN) && (defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2)) +int stm32_can_initialize(void); +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __CONFIGS_OLIMEX_STM32_E407_SRC_INTERNAL_H */ diff --git a/configs/olimex-stm32-e407/src/stm32_adc.c b/configs/olimex-stm32-e407/src/stm32_adc.c new file mode 100644 index 0000000000000000000000000000000000000000..98ff8b85f3c33e3ece8b350aa8c23bdcfbf9a30e --- /dev/null +++ b/configs/olimex-stm32-e407/src/stm32_adc.c @@ -0,0 +1,187 @@ +/************************************************************************************ + * configs/olimex-stm32-e407/src/stm32_adc.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include + +#include +#include +#include + +#include "chip.h" +#include "stm32_adc.h" +#include "olimex-stm32-e407.h" + +#ifdef CONFIG_ADC + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Configuration ********************************************************************/ +/* Up to 3 ADC interfaces are supported */ + +#if STM32_NADC < 3 +# undef CONFIG_STM32_ADC3 +#endif + +#if STM32_NADC < 2 +# undef CONFIG_STM32_ADC2 +#endif + +#if STM32_NADC < 1 +# undef CONFIG_STM32_ADC1 +#endif + +#if defined(CONFIG_STM32_ADC1) || defined(CONFIG_STM32_ADC2) || defined(CONFIG_STM32_ADC3) +#ifndef CONFIG_STM32_ADC1 +# warning "Channel information only available for ADC1" +#endif + +/* The number of ADC channels in the conversion list */ + +#define ADC1_NCHANNELS 1//14 + +/************************************************************************************ + * Private Data + ************************************************************************************/ +/* The Olimex STM32-P405 has a 10 Kohm potentiometer AN_TR connected to PC0 + * ADC123_IN10 + */ + +/* Identifying number of each ADC channel: Variable Resistor. + * + * {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15}; + */ + +#ifdef CONFIG_STM32_ADC1 +static const uint8_t g_chanlist[ADC1_NCHANNELS] = {1}; + +/* Configurations of pins used byte each ADC channels + * + * {GPIO_ADC1_IN1, GPIO_ADC1_IN2, GPIO_ADC1_IN3, GPIO_ADC1_IN4, GPIO_ADC1_IN5, + * GPIO_ADC1_IN6, GPIO_ADC1_IN7, GPIO_ADC1_IN8, GPIO_ADC1_IN9, GPIO_ADC1_IN10, + * GPIO_ADC1_IN11, GPIO_ADC1_IN12, GPIO_ADC1_IN13, GPIO_ADC1_IN15}; + */ + +static const uint32_t g_pinlist[ADC1_NCHANNELS] = {GPIO_ADC1_IN1}; +#endif + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: board_adc_setup + * + * Description: + * All STM32 architectures must provide the following interface to work with + * examples/adc. + * + ************************************************************************************/ + +int board_adc_setup(void) +{ + return stm32_adc_initialize(); +} + +/************************************************************************************ + * Name: stm32_adc_initialize + * + * Description: + * Called at application startup time to initialize the ADC functionality. + * + ************************************************************************************/ + +int stm32_adc_initialize(void) +{ +#ifdef CONFIG_STM32_ADC1 + static bool initialized = false; + struct adc_dev_s *adc; + int ret; + int i; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Configure the pins as analog inputs for the selected channels */ + + for (i = 0; i < ADC1_NCHANNELS; i++) + { + stm32_configgpio(g_pinlist[i]); + } + + /* Call stm32_adcinitialize() to get an instance of the ADC interface */ + + adc = stm32_adcinitialize(1, g_chanlist, ADC1_NCHANNELS); + if (adc == NULL) + { + adbg("ERROR: Failed to get ADC interface\n"); + return -ENODEV; + } + + /* Register the ADC driver at "/dev/adc0" */ + + ret = adc_register("/dev/adc0", adc); + if (ret < 0) + { + adbg("adc_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +#else + return -ENOSYS; +#endif +} + +#endif /* CONFIG_STM32_ADC1 || CONFIG_STM32_ADC2 || CONFIG_STM32_ADC3 */ +#endif /* CONFIG_ADC */ diff --git a/configs/olimex-stm32-e407/src/stm32_appinit.c b/configs/olimex-stm32-e407/src/stm32_appinit.c new file mode 100644 index 0000000000000000000000000000000000000000..c7715a95b2af5e0c506701bb23e5a71ed1492887 --- /dev/null +++ b/configs/olimex-stm32-e407/src/stm32_appinit.c @@ -0,0 +1,236 @@ +/**************************************************************************** + * config/olimex-stm32-e407/src/stm32_appinit.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include + +#ifdef CONFIG_USBMONITOR +# include +#endif + +#ifdef CONFIG_STM32_OTGFS +# include "stm32_usbhost.h" +#endif + +#include "stm32.h" +#include "olimex-stm32-e407.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#define HAVE_USBDEV 1 +#define HAVE_USBHOST 1 +#define HAVE_USBMONITOR 1 +/* #define HAVE_I2CTOOL 1 */ + +/* Can't support USB host or device features if USB OTG HS is not enabled */ + +#ifndef CONFIG_STM32_OTGHS +# undef HAVE_USBDEV +# undef HAVE_USBHOST +# undef HAVE_USBMONITOR +#endif + +/* Can't support USB device monitor if USB device is not enabled */ + +#ifndef CONFIG_USBDEV +# undef HAVE_USBDEV +# undef HAVE_USBMONITOR +#endif + +/* Can't support USB host is USB host is not enabled */ + +#ifndef CONFIG_USBHOST +# undef HAVE_USBHOST +#endif + +/* Check if we should enable the USB monitor before starting NSH */ + +#if !defined(CONFIG_USBDEV_TRACE) || !defined(CONFIG_USBMONITOR) +# undef HAVE_USBMONITOR +#endif + +#if !defined(CONFIG_STM32_CAN1) && !defined(CONFIG_STM32_CAN2) +# undef CONFIG_CAN +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: stm32_i2c_register + * + * Description: + * Register one I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#ifdef HAVE_I2CTOOL +static void stm32_i2c_register(int bus) +{ + FAR struct i2c_master_s *i2c; + int ret; + + i2c = stm32_i2cbus_initialize(bus); + if (i2c == NULL) + { + _err("ERROR: Failed to get I2C%d interface\n", bus); + } + else + { + ret = i2c_register(i2c, bus); + if (ret < 0) + { + _err("ERROR: Failed to register I2C%d driver: %d\n", bus, ret); + stm32_i2cbus_uninitialize(i2c); + } + } +} +#endif + +/**************************************************************************** + * Name: stm32_i2ctool + * + * Description: + * Register I2C drivers for the I2C tool. + * + ****************************************************************************/ + +#ifdef HAVE_I2CTOOL +static void stm32_i2ctool(void) +{ +#ifdef CONFIG_STM32_I2C1 + stm32_i2c_register(1); +#endif +#ifdef CONFIG_STM32_I2C2 + stm32_i2c_register(2); +#endif +#ifdef CONFIG_STM32_I2C3 + stm32_i2c_register(3); +#endif +} +#else +# define stm32_i2ctool() +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_app_initialize + * + * Description: + * Perform architecture specific initialization + * + * CONFIG_LIB_BOARDCTL=y : + * Called from the NSH library + * + * CONFIG_BOARD_INITIALIZE=y, CONFIG_NSH_LIBRARY=y, && + * CONFIG_LIB_BOARDCTL=n : + * Called from board_initialize(). + * + ****************************************************************************/ + +int board_app_initialize(uintptr_t arg) +{ +#if defined(CONFIG_CAN) || defined(CONFIG_ADC) + int ret; +#endif + + /* Register I2C drivers on behalf of the I2C tool */ + + stm32_i2ctool(); + + +#ifdef CONFIG_CAN + /* Configure on-board CAN if CAN support has been selected. */ + + ret = stm32_can_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to initialize CAN: %d\n", ret); + } +#endif + +#ifdef CONFIG_ADC + /* Configure on-board ADCs if ADC support has been selected. */ + + ret = stm32_adc_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to initialize ADC: %d\n", ret); + } +#endif + +#ifdef HAVE_USBHOST + /* Initialize USB host operation. stm32_usbhost_initialize() starts a thread + * will monitor for USB connection and disconnection events. + */ + + ret = stm32_usbhost_initialize(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to initialize USB host: %d\n", ret); + return ret; + } +#endif + +#ifdef HAVE_USBMONITOR + /* Start the USB Monitor */ + + ret = usbmonitor_start(); + if (ret != OK) + { + syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); + } +#endif + + return OK; +} diff --git a/configs/olimex-stm32-e407/src/stm32_autoleds.c b/configs/olimex-stm32-e407/src/stm32_autoleds.c new file mode 100644 index 0000000000000000000000000000000000000000..0b46a0e677ced2555ddbadcbb202b290d20c3ccd --- /dev/null +++ b/configs/olimex-stm32-e407/src/stm32_autoleds.c @@ -0,0 +1,106 @@ +/**************************************************************************** + * configs/olimex-stm32-e407/src/stm32_autoleds.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" +#include "stm32.h" +#include "olimex-stm32-e407.h" + +#ifdef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled_initialize + ****************************************************************************/ + +void board_autoled_initialize(void) +{ + /* Configure LED_STATUS GPIO for output */ + + stm32_configgpio(GPIO_LED_STATUS); +} + +/**************************************************************************** + * Name: board_autoled_on + ****************************************************************************/ + +void board_autoled_on(int led) +{ + if (led == LED_STARTED) + { + stm32_gpiowrite(GPIO_LED_STATUS, true); + } + + if (led == LED_ASSERTION || led == LED_PANIC) + { + stm32_gpiowrite(GPIO_LED_STATUS, false); + } +} + +/**************************************************************************** + * Name: board_autoled_off + ****************************************************************************/ + +void board_autoled_off(int led) +{ + if (led == LED_STARTED) + { + stm32_gpiowrite(GPIO_LED_STATUS, false); + } + + if (led == LED_ASSERTION || led == LED_PANIC) + { + stm32_gpiowrite(GPIO_LED_STATUS, true); + } +} + +#endif /* CONFIG_ARCH_LEDS */ diff --git a/configs/olimex-stm32-e407/src/stm32_boot.c b/configs/olimex-stm32-e407/src/stm32_boot.c new file mode 100644 index 0000000000000000000000000000000000000000..cad3479aa1af53b905f720dd346530c962e364bf --- /dev/null +++ b/configs/olimex-stm32-e407/src/stm32_boot.c @@ -0,0 +1,121 @@ +/************************************************************************************ + * configs/olimex-stm32-e407/src/stm32_boot.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include "up_arch.h" +#include "olimex-stm32-e407.h" +#include "stm32_ccm.h" + +#include "stm32.h" +#include "stm32_i2c.h" + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_boardinitialize + * + * Description: + * All STM32 architectures must provide the following entry point. This entry point + * is called early in the intitialization -- after all memory has been configured + * and mapped but before any devices have been initialized. + * + ************************************************************************************/ + +void stm32_boardinitialize(void) +{ +#if defined(CONFIG_STM32_OTGFS) || defined(CONFIG_STM32_OTGHS) + /* Initialize USB if the 1) OTG FS controller is in the configuration and 2) + * disabled, and 3) the weak function stm32_usbinitialize() has been brought + * into the build. Presumeably either CONFIG_USBDEV is also selected. + */ + + if (stm32_usbinitialize) + { + stm32_usbinitialize(); + } +#endif + +#ifdef CONFIG_ARCH_LEDS + /* Configure on-board LEDs if LED support has been selected. */ + + board_autoled_initialize(); +#endif + +#ifdef CONFIG_ARCH_BUTTONS + /* Configure on-board BUTTONs if BUTTON support has been selected. */ + + board_button_initialize(); +#endif +} + +/**************************************************************************** + * Name: board_initialize + * + * Description: + * If CONFIG_BOARD_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_initialize(). board_initialize() will be + * called immediately after up_intitialize() is called and just before the + * initial application is started. This additional initialization phase + * may be used, for example, to initialize board-specific device drivers. + * + ****************************************************************************/ + +#ifdef CONFIG_BOARD_INITIALIZE +void board_initialize(void) +{ +#if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_LIB_BOARDCTL) + /* Perform NSH initialization here instead of from the NSH. This + * alternative NSH initialization is necessary when NSH is ran in user-space + * but the initialization function must run in kernel space. + */ + + board_app_initialize(); +#endif +} +#endif diff --git a/configs/olimex-stm32-e407/src/stm32_buttons.c b/configs/olimex-stm32-e407/src/stm32_buttons.c new file mode 100644 index 0000000000000000000000000000000000000000..951df8ef1c4da53f5aab1aa1471431c5ff3fe5f0 --- /dev/null +++ b/configs/olimex-stm32-e407/src/stm32_buttons.c @@ -0,0 +1,151 @@ +/**************************************************************************** + * configs/olimex-stm32-e407/src/stm32_buttons.c + * + * Copyright (C) 2014-2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#include +#include +#include + +#include "olimex-stm32-e407.h" + +#ifdef CONFIG_ARCH_BUTTONS + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/* Pin configuration for each Olimex-STM32-H405 button. This array is + * indexed by the BUTTON_* definitions in board.h + */ + +static const uint32_t g_buttons[NUM_BUTTONS] = +{ + GPIO_BTN_BUT +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_button_initialize + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + ****************************************************************************/ + +void board_button_initialize(void) +{ + int i; + + /* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are + * configured for all pins. + */ + + for (i = 0; i < NUM_BUTTONS; i++) + { + stm32_configgpio(g_buttons[i]); + } +} + +/**************************************************************************** + * Name: board_buttons + ****************************************************************************/ + +uint8_t board_buttons(void) +{ + uint8_t ret = 0; + + /* Check that state of each key */ + + if (!stm32_gpioread(g_buttons[BUTTON_BUT])) + { + ret |= BUTTON_BUT_BIT; + } + + return ret; +} + +/**************************************************************************** + * Button support. + * + * Description: + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. + * + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 8-bit bit set with each bit associated with a button. See the BUTTON_*_BIT + * definitions in board.h for the meaning of each bit. + * + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. The previous interrupt handler address is returned (so that it + * may restored, if so desired). + * + ****************************************************************************/ + +#ifdef CONFIG_ARCH_IRQBUTTONS +xcpt_t board_button_irq(int id, xcpt_t irqhandler) +{ + xcpt_t oldhandler = NULL; + + /* The following should be atomic */ + + if (id >= MIN_IRQBUTTON && id <= MAX_IRQBUTTON) + { + oldhandler = + stm32_gpiosetevent(g_buttons[id], true, true, true, irqhandler); + } + + return oldhandler; +} +#endif +#endif /* CONFIG_ARCH_BUTTONS */ diff --git a/configs/olimex-stm32-e407/src/stm32_can.c b/configs/olimex-stm32-e407/src/stm32_can.c new file mode 100644 index 0000000000000000000000000000000000000000..d4fa00aa4c91dcc54a2fcb2b90fe0a39f169eefc --- /dev/null +++ b/configs/olimex-stm32-e407/src/stm32_can.c @@ -0,0 +1,130 @@ +/************************************************************************************ + * configs/olimex-stm32-405/src/stm32_can.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include +#include +#include "stm32.h" +#include "stm32_can.h" +#include "olimex-stm32-e407.h" + +#if defined(CONFIG_CAN) && (defined(CONFIG_STM32_CAN1) || defined(CONFIG_STM32_CAN2)) + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Configuration ********************************************************************/ + +#if defined(CONFIG_STM32_CAN1) && defined(CONFIG_STM32_CAN2) +# warning "Both CAN1 and CAN2 are enabled. Only CAN1 is used." +# undef CONFIG_STM32_CAN2 +#endif + +#ifdef CONFIG_STM32_CAN1 +# define CAN_PORT 1 +#else +# define CAN_PORT 2 +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: board_can_initialize + * + * Description: + * All STM32 architectures must provide the following interface to work with + * examples/can. + * + ************************************************************************************/ + +int board_can_initialize(void) +{ + return stm32_can_initialize(); +} + +/************************************************************************************ + * Name: stm32_can_initialize + * + * Description: + * Called at application startup time to initialize the CAN functionality. + * + ************************************************************************************/ + +int stm32_can_initialize(void) +{ + static bool initialized = false; + struct can_dev_s *can; + int ret; + + /* Check if we have already initialized */ + + if (!initialized) + { + /* Call stm32_caninitialize() to get an instance of the CAN interface */ + + can = stm32_caninitialize(CAN_PORT); + if (can == NULL) + { + candbg("ERROR: Failed to get CAN interface\n"); + return -ENODEV; + } + + /* Register the CAN driver at "/dev/can0" */ + + ret = can_register("/dev/can0", can); + if (ret < 0) + { + candbg("ERROR: can_register failed: %d\n", ret); + return ret; + } + + /* Now we are initialized */ + + initialized = true; + } + + return OK; +} + +#endif /* CONFIG_CAN && (CONFIG_STM32_CAN1 || CONFIG_STM32_CAN2) */ diff --git a/configs/olimex-stm32-e407/src/stm32_usb.c b/configs/olimex-stm32-e407/src/stm32_usb.c new file mode 100644 index 0000000000000000000000000000000000000000..db93fcbf178d1bfc8a2a33e1767e75c3c7a54309 --- /dev/null +++ b/configs/olimex-stm32-e407/src/stm32_usb.c @@ -0,0 +1,336 @@ +/************************************************************************************ + * configs/stm32f4discovery/src/stm32_usb.c + * + * Copyright (C) 2012-2013, 2015-2916 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include "up_arch.h" +#include "stm32.h" +#include "stm32_otgfs.h" +#include "olimex-stm32-e407.h" + +#ifdef CONFIG_STM32_OTGFS + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#if defined(CONFIG_USBDEV) || defined(CONFIG_USBHOST) +# define HAVE_USB 1 +#else +# warning "CONFIG_STM32_OTGFS is enabled but neither CONFIG_USBDEV nor CONFIG_USBHOST" +# undef HAVE_USB +#endif + +#ifndef CONFIG_STM32F4DISCO_USBHOST_PRIO +# define CONFIG_STM32F4DISCO_USBHOST_PRIO 100 +#endif + +#ifndef CONFIG_STM32F4DISCO_USBHOST_STACKSIZE +# define CONFIG_STM32F4DISCO_USBHOST_STACKSIZE 1024 +#endif + +/************************************************************************************ + * Private Data + ************************************************************************************/ + +#ifdef CONFIG_USBHOST +static struct usbhost_connection_s *g_usbconn; +#endif + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: usbhost_waiter + * + * Description: + * Wait for USB devices to be connected. + * + ************************************************************************************/ + +#ifdef CONFIG_USBHOST +static int usbhost_waiter(int argc, char *argv[]) +{ + struct usbhost_hubport_s *hport; + + uinfo("Running\n"); + for (;;) + { + /* Wait for the device to change state */ + + DEBUGVERIFY(CONN_WAIT(g_usbconn, &hport)); + uinfo("%s\n", hport->connected ? "connected" : "disconnected"); + + /* Did we just become connected? */ + + if (hport->connected) + { + /* Yes.. enumerate the newly connected device */ + + (void)CONN_ENUMERATE(g_usbconn, hport); + } + } + + /* Keep the compiler from complaining */ + + return 0; +} +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_usbinitialize + * + * Description: + * Called from stm32_usbinitialize very early in inialization to setup USB-related + * GPIO pins for the STM32F4Discovery board. + * + ************************************************************************************/ + +void stm32_usbinitialize(void) +{ + /* The OTG FS has an internal soft pull-up. No GPIO configuration is required */ + + /* Configure the OTG FS VBUS sensing GPIO, Power On, and Overcurrent GPIOs */ + +#ifdef CONFIG_STM32_OTGFS + stm32_configgpio(GPIO_OTGFS_VBUS); + stm32_configgpio(GPIO_OTGFS_PWRON); + stm32_configgpio(GPIO_OTGFS_OVER); +#endif +} + +/*********************************************************************************** + * Name: stm32_usbhost_initialize + * + * Description: + * Called at application startup time to initialize the USB host functionality. + * This function will start a thread that will monitor for device + *nnnn connection/disconnection events. + * + ***********************************************************************************/ + +#ifdef CONFIG_USBHOST +int stm32_usbhost_initialize(void) +{ + int pid; +#if defined(CONFIG_USBHOST_HUB) || defined(CONFIG_USBHOST_MSC) || \ + defined(CONFIG_USBHOST_HIDKBD) || defined(CONFIG_USBHOST_HIDMOUSE) + int ret; +#endif + + /* First, register all of the class drivers needed to support the drivers + * that we care about: + */ + + uvdbg("Register class drivers\n"); + +#ifdef CONFIG_USBHOST_HUB + /* Initialize USB hub class support */ + + ret = usbhost_hub_initialize(); + if (ret < 0) + { + uerr("ERROR: usbhost_hub_initialize failed: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_MSC + /* Register the USB mass storage class class */ + + ret = usbhost_msc_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the mass storage class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_CDCACM + /* Register the CDC/ACM serial class */ + + ret = usbhost_cdcacm_initialize(); + if (ret != OK) + { + uerr("ERROR: Failed to register the CDC/ACM serial class: %d\n", ret); + } +#endif + +#ifdef CONFIG_USBHOST_HIDKBD + /* Initialize the HID keyboard class */ + + ret = usbhost_kbdinit(); + if (ret != OK) + { + uerr("Failed to register the HID keyboard class\n"); + } +#endif + +#ifdef CONFIG_USBHOST_HIDMOUSE + /* Initialize the HID mouse class */ + + ret = usbhost_mouse_init(); + if (ret != OK) + { + uerr("Failed to register the HID mouse class\n"); + } +#endif + + /* Then get an instance of the USB host interface */ + + uinfo("Initialize USB host\n"); + g_usbconn = stm32_otgfshost_initialize(0); + if (g_usbconn) + { + /* Start a thread to handle device connection. */ + + uinfo("Start usbhost_waiter\n"); + + pid = task_create("usbhost", CONFIG_STM32F4DISCO_USBHOST_PRIO, + CONFIG_STM32F4DISCO_USBHOST_STACKSIZE, + (main_t)usbhost_waiter, (FAR char * const *)NULL); + return pid < 0 ? -ENOEXEC : OK; + } + + return -ENODEV; +} +#endif + +/*********************************************************************************** + * Name: stm32_usbhost_vbusdrive + * + * Description: + * Enable/disable driving of VBUS 5V output. This function must be provided be + * each platform that implements the STM32 OTG FS host interface + * + * "On-chip 5 V VBUS generation is not supported. For this reason, a charge pump + * or, if 5 V are available on the application board, a basic power switch, must + * be added externally to drive the 5 V VBUS line. The external charge pump can + * be driven by any GPIO output. When the application decides to power on VBUS + * using the chosen GPIO, it must also set the port power bit in the host port + * control and status register (PPWR bit in OTG_FS_HPRT). + * + * "The application uses this field to control power to this port, and the core + * clears this bit on an overcurrent condition." + * + * Input Parameters: + * iface - For future growth to handle multiple USB host interface. Should be zero. + * enable - true: enable VBUS power; false: disable VBUS power + * + * Returned Value: + * None + * + ***********************************************************************************/ + +#ifdef CONFIG_USBHOST +void stm32_usbhost_vbusdrive(int iface, bool enable) +{ + DEBUGASSERT(iface == 0); + + if (enable) + { + /* Enable the Power Switch by driving the enable pin low */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, false); + } + else + { + /* Disable the Power Switch by driving the enable pin high */ + + stm32_gpiowrite(GPIO_OTGFS_PWRON, true); + } +} +#endif + +/************************************************************************************ + * Name: stm32_setup_overcurrent + * + * Description: + * Setup to receive an interrupt-level callback if an overcurrent condition is + * detected. + * + * Input Parameter: + * handler - New overcurrent interrupt handler + * + * Returned value: + * Old overcurrent interrupt handler + * + ************************************************************************************/ + +#ifdef CONFIG_USBHOST +xcpt_t stm32_setup_overcurrent(xcpt_t handler) +{ + return stm32_gpiosetevent(GPIO_OTGFS_OVER, true, true, true, handler); +} +#endif + +/************************************************************************************ + * Name: stm32_usbsuspend + * + * Description: + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver is + * used. This function is called whenever the USB enters or leaves suspend mode. + * This is an opportunity for the board logic to shutdown clocks, power, etc. + * while the USB is suspended. + * + ************************************************************************************/ + +#ifdef CONFIG_USBDEV +void stm32_usbsuspend(FAR struct usbdev_s *dev, bool resume) +{ + uinfo("resume: %d\n", resume); +} +#endif + +#endif /* CONFIG_STM32_OTGFS */ diff --git a/configs/olimex-stm32-e407/src/stm32_userleds.c b/configs/olimex-stm32-e407/src/stm32_userleds.c new file mode 100644 index 0000000000000000000000000000000000000000..f927f73862eba6991888d4ad61544b402ab43de5 --- /dev/null +++ b/configs/olimex-stm32-e407/src/stm32_userleds.c @@ -0,0 +1,106 @@ +/**************************************************************************** + * configs/olimex-stm32-e407/src/stm32_leds.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" +#include "stm32.h" +#include "olimex-stm32-e407.h" + +#ifndef CONFIG_ARCH_LEDS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Private Data + ****************************************************************************/ +/* This array maps an LED number to GPIO pin configuration */ + +static uint32_t g_ledcfg[BOARD_NLEDS] = +{ + GPIO_LED_STATUS +}; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_userled_initialize + ****************************************************************************/ + +void board_userled_initialize(void) +{ + /* Configure LED1-4 GPIOs for output */ + + stm32_configgpio(GPIO_LED_STATUS); +} + +/**************************************************************************** + * Name: board_userled + ****************************************************************************/ + +void board_userled(int led, bool ledon) +{ + if ((unsigned)led < BOARD_NLEDS) + { + stm32_gpiowrite(g_ledcfg[led], ledon); + } +} + +/**************************************************************************** + * Name: board_userled_all + ****************************************************************************/ + +void board_userled_all(uint8_t ledset) +{ + stm32_gpiowrite(GPIO_LED_STATUS, (ledset & BOARD_LED1_BIT) != 0); +} + +#endif /* !CONFIG_ARCH_LEDS */ diff --git a/configs/stm32f746g-disco/netnsh/Make.defs b/configs/olimex-stm32-e407/usbnsh/Make.defs similarity index 97% rename from configs/stm32f746g-disco/netnsh/Make.defs rename to configs/olimex-stm32-e407/usbnsh/Make.defs index 7a2cc395ab70087de0e1633ca17a0f39f3a822b4..a9a8ab3992988854c24b78fc5d093c020c502c9b 100644 --- a/configs/stm32f746g-disco/netnsh/Make.defs +++ b/configs/olimex-stm32-e407/usbnsh/Make.defs @@ -1,7 +1,7 @@ ############################################################################ -# configs/stm32f746g-disco/netnsh/Make.defs +# configs/olimex-stm32-e407/usbnsh/Make.defs # -# Copyright (C) 2015 Gregory Nutt. All rights reserved. +# Copyright (C) 2013 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -37,7 +37,7 @@ include ${TOPDIR}/.config include ${TOPDIR}/tools/Config.mk include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs -LDSCRIPT = flash.ld +LDSCRIPT = ld.script ifeq ($(WINTOOL),y) # Windows-native toolchains diff --git a/configs/olimex-stm32-e407/usbnsh/defconfig b/configs/olimex-stm32-e407/usbnsh/defconfig new file mode 100644 index 0000000000000000000000000000000000000000..9e1752b9a81bd80b7e7d44d3793bfbeb71b975a7 --- /dev/null +++ b/configs/olimex-stm32-e407/usbnsh/defconfig @@ -0,0 +1,1232 @@ +# +# Automatically generated file; DO NOT EDIT. +# Nuttx/ Configuration +# + +# +# Build Setup +# +# CONFIG_EXPERIMENTAL is not set +# CONFIG_DEFAULT_SMALL is not set +CONFIG_HOST_LINUX=y +# CONFIG_HOST_OSX is not set +# CONFIG_HOST_WINDOWS is not set +# CONFIG_HOST_OTHER is not set + +# +# Build Configuration +# +# CONFIG_APPS_DIR="../apps" +CONFIG_BUILD_FLAT=y +# CONFIG_BUILD_2PASS is not set + +# +# Binary Output Formats +# +# CONFIG_RRLOAD_BINARY is not set +CONFIG_INTELHEX_BINARY=y +# CONFIG_MOTOROLA_SREC is not set +CONFIG_RAW_BINARY=y +# CONFIG_UBOOT_UIMAGE is not set + +# +# Customize Header Files +# +# CONFIG_ARCH_STDINT_H is not set +# CONFIG_ARCH_STDBOOL_H is not set +# CONFIG_ARCH_MATH_H is not set +# CONFIG_ARCH_FLOAT_H is not set +# CONFIG_ARCH_STDARG_H is not set +# CONFIG_ARCH_DEBUG_H is not set + +# +# Debug Options +# +CONFIG_DEBUG_ALERT=y +# CONFIG_DEBUG_FEATURES is not set +CONFIG_ARCH_HAVE_STACKCHECK=y +# CONFIG_STACK_COLORATION is not set +CONFIG_ARCH_HAVE_HEAPCHECK=y +# CONFIG_HEAP_COLORATION is not set +# CONFIG_DEBUG_SYMBOLS is not set +CONFIG_ARCH_HAVE_CUSTOMOPT=y +# CONFIG_DEBUG_NOOPT is not set +# CONFIG_DEBUG_CUSTOMOPT is not set +CONFIG_DEBUG_FULLOPT=y + +# +# System Type +# +CONFIG_ARCH_ARM=y +# CONFIG_ARCH_AVR is not set +# CONFIG_ARCH_HC is not set +# CONFIG_ARCH_MIPS is not set +# CONFIG_ARCH_RGMP is not set +# CONFIG_ARCH_SH is not set +# CONFIG_ARCH_SIM is not set +# CONFIG_ARCH_X86 is not set +# CONFIG_ARCH_Z16 is not set +# CONFIG_ARCH_Z80 is not set +CONFIG_ARCH="arm" + +# +# ARM Options +# +# CONFIG_ARCH_CHIP_A1X is not set +# CONFIG_ARCH_CHIP_C5471 is not set +# CONFIG_ARCH_CHIP_CALYPSO is not set +# CONFIG_ARCH_CHIP_DM320 is not set +# CONFIG_ARCH_CHIP_EFM32 is not set +# CONFIG_ARCH_CHIP_IMX1 is not set +# CONFIG_ARCH_CHIP_IMX6 is not set +# CONFIG_ARCH_CHIP_KINETIS is not set +# CONFIG_ARCH_CHIP_KL is not set +# CONFIG_ARCH_CHIP_LM is not set +# CONFIG_ARCH_CHIP_TIVA is not set +# CONFIG_ARCH_CHIP_LPC11XX is not set +# CONFIG_ARCH_CHIP_LPC17XX is not set +# CONFIG_ARCH_CHIP_LPC214X is not set +# CONFIG_ARCH_CHIP_LPC2378 is not set +# CONFIG_ARCH_CHIP_LPC31XX is not set +# CONFIG_ARCH_CHIP_LPC43XX is not set +# CONFIG_ARCH_CHIP_NUC1XX is not set +# CONFIG_ARCH_CHIP_SAMA5 is not set +# CONFIG_ARCH_CHIP_SAMD is not set +# CONFIG_ARCH_CHIP_SAML is not set +# CONFIG_ARCH_CHIP_SAM34 is not set +# CONFIG_ARCH_CHIP_SAMV7 is not set +CONFIG_ARCH_CHIP_STM32=y +# CONFIG_ARCH_CHIP_STM32F7 is not set +# CONFIG_ARCH_CHIP_STM32L4 is not set +# CONFIG_ARCH_CHIP_STR71X is not set +# CONFIG_ARCH_CHIP_TMS570 is not set +# CONFIG_ARCH_CHIP_MOXART is not set +# CONFIG_ARCH_ARM7TDMI is not set +# CONFIG_ARCH_ARM926EJS is not set +# CONFIG_ARCH_ARM920T is not set +# CONFIG_ARCH_CORTEXM0 is not set +# CONFIG_ARCH_CORTEXM3 is not set +CONFIG_ARCH_CORTEXM4=y +# CONFIG_ARCH_CORTEXM7 is not set +# CONFIG_ARCH_CORTEXA5 is not set +# CONFIG_ARCH_CORTEXA8 is not set +# CONFIG_ARCH_CORTEXA9 is not set +# CONFIG_ARCH_CORTEXR4 is not set +# CONFIG_ARCH_CORTEXR4F is not set +# CONFIG_ARCH_CORTEXR5 is not set +# CONFIG_ARCH_CORTEX5F is not set +# CONFIG_ARCH_CORTEXR7 is not set +# CONFIG_ARCH_CORTEXR7F is not set +CONFIG_ARCH_FAMILY="armv7-m" +CONFIG_ARCH_CHIP="stm32" +# CONFIG_ARM_TOOLCHAIN_IAR is not set +CONFIG_ARM_TOOLCHAIN_GNU=y +# CONFIG_ARMV7M_USEBASEPRI is not set +CONFIG_ARCH_HAVE_CMNVECTOR=y +# CONFIG_ARMV7M_CMNVECTOR is not set +# CONFIG_ARMV7M_LAZYFPU is not set +CONFIG_ARCH_HAVE_FPU=y +# CONFIG_ARCH_HAVE_DPFPU is not set +# CONFIG_ARCH_FPU is not set +# CONFIG_ARCH_HAVE_TRUSTZONE is not set +CONFIG_ARM_HAVE_MPU_UNIFIED=y +# CONFIG_ARM_MPU is not set + +# +# ARMV7M Configuration Options +# +# CONFIG_ARMV7M_HAVE_ICACHE is not set +# CONFIG_ARMV7M_HAVE_DCACHE is not set +# CONFIG_ARMV7M_HAVE_ITCM is not set +# CONFIG_ARMV7M_HAVE_DTCM is not set +# CONFIG_ARMV7M_TOOLCHAIN_IARL is not set +# CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODEREDL is not set +# CONFIG_ARMV7M_TOOLCHAIN_CODESOURCERYL is not set +CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y +CONFIG_ARMV7M_HAVE_STACKCHECK=y +# CONFIG_ARMV7M_STACKCHECK is not set +# CONFIG_ARMV7M_ITMSYSLOG is not set +# CONFIG_SERIAL_TERMIOS is not set + +# +# STM32 Configuration Options +# +# CONFIG_ARCH_CHIP_STM32L151C6 is not set +# CONFIG_ARCH_CHIP_STM32L151C8 is not set +# CONFIG_ARCH_CHIP_STM32L151CB is not set +# CONFIG_ARCH_CHIP_STM32L151R6 is not set +# CONFIG_ARCH_CHIP_STM32L151R8 is not set +# CONFIG_ARCH_CHIP_STM32L151RB is not set +# CONFIG_ARCH_CHIP_STM32L151V6 is not set +# CONFIG_ARCH_CHIP_STM32L151V8 is not set +# CONFIG_ARCH_CHIP_STM32L151VB is not set +# CONFIG_ARCH_CHIP_STM32L152C6 is not set +# CONFIG_ARCH_CHIP_STM32L152C8 is not set +# CONFIG_ARCH_CHIP_STM32L152CB is not set +# CONFIG_ARCH_CHIP_STM32L152R6 is not set +# CONFIG_ARCH_CHIP_STM32L152R8 is not set +# CONFIG_ARCH_CHIP_STM32L152RB is not set +# CONFIG_ARCH_CHIP_STM32L152V6 is not set +# CONFIG_ARCH_CHIP_STM32L152V8 is not set +# CONFIG_ARCH_CHIP_STM32L152VB is not set +# CONFIG_ARCH_CHIP_STM32L162ZD is not set +# CONFIG_ARCH_CHIP_STM32L162VE is not set +# CONFIG_ARCH_CHIP_STM32F100C8 is not set +# CONFIG_ARCH_CHIP_STM32F100CB is not set +# CONFIG_ARCH_CHIP_STM32F100R8 is not set +# CONFIG_ARCH_CHIP_STM32F100RB is not set +# CONFIG_ARCH_CHIP_STM32F100RC is not set +# CONFIG_ARCH_CHIP_STM32F100RD is not set +# CONFIG_ARCH_CHIP_STM32F100RE is not set +# CONFIG_ARCH_CHIP_STM32F100V8 is not set +# CONFIG_ARCH_CHIP_STM32F100VB is not set +# CONFIG_ARCH_CHIP_STM32F100VC is not set +# CONFIG_ARCH_CHIP_STM32F100VD is not set +# CONFIG_ARCH_CHIP_STM32F100VE is not set +# CONFIG_ARCH_CHIP_STM32F102CB is not set +# CONFIG_ARCH_CHIP_STM32F103T8 is not set +# CONFIG_ARCH_CHIP_STM32F103TB is not set +# CONFIG_ARCH_CHIP_STM32F103C4 is not set +# CONFIG_ARCH_CHIP_STM32F103C8 is not set +# CONFIG_ARCH_CHIP_STM32F103CB is not set +# CONFIG_ARCH_CHIP_STM32F103R8 is not set +# CONFIG_ARCH_CHIP_STM32F103RB is not set +# CONFIG_ARCH_CHIP_STM32F103RC is not set +# CONFIG_ARCH_CHIP_STM32F103RD is not set +# CONFIG_ARCH_CHIP_STM32F103RE is not set +# CONFIG_ARCH_CHIP_STM32F103RG is not set +# CONFIG_ARCH_CHIP_STM32F103V8 is not set +# CONFIG_ARCH_CHIP_STM32F103VB is not set +# CONFIG_ARCH_CHIP_STM32F103VC is not set +# CONFIG_ARCH_CHIP_STM32F103VE is not set +# CONFIG_ARCH_CHIP_STM32F103ZE is not set +# CONFIG_ARCH_CHIP_STM32F105VB is not set +# CONFIG_ARCH_CHIP_STM32F105RB is not set +# CONFIG_ARCH_CHIP_STM32F107VC is not set +# CONFIG_ARCH_CHIP_STM32F205RG is not set +# CONFIG_ARCH_CHIP_STM32F207IG is not set +# CONFIG_ARCH_CHIP_STM32F207ZE is not set +# CONFIG_ARCH_CHIP_STM32F302K6 is not set +# CONFIG_ARCH_CHIP_STM32F302K8 is not set +# CONFIG_ARCH_CHIP_STM32F302CB is not set +# CONFIG_ARCH_CHIP_STM32F302CC is not set +# CONFIG_ARCH_CHIP_STM32F302RB is not set +# CONFIG_ARCH_CHIP_STM32F302RC is not set +# CONFIG_ARCH_CHIP_STM32F302VB is not set +# CONFIG_ARCH_CHIP_STM32F302VC is not set +# CONFIG_ARCH_CHIP_STM32F303K6 is not set +# CONFIG_ARCH_CHIP_STM32F303K8 is not set +# CONFIG_ARCH_CHIP_STM32F303C6 is not set +# CONFIG_ARCH_CHIP_STM32F303C8 is not set +# CONFIG_ARCH_CHIP_STM32F303CB is not set +# CONFIG_ARCH_CHIP_STM32F303CC is not set +# CONFIG_ARCH_CHIP_STM32F303RB is not set +# CONFIG_ARCH_CHIP_STM32F303RC is not set +# CONFIG_ARCH_CHIP_STM32F303RD is not set +# CONFIG_ARCH_CHIP_STM32F303RE is not set +# CONFIG_ARCH_CHIP_STM32F303VB is not set +# CONFIG_ARCH_CHIP_STM32F303VC is not set +# CONFIG_ARCH_CHIP_STM32F372C8 is not set +# CONFIG_ARCH_CHIP_STM32F372R8 is not set +# CONFIG_ARCH_CHIP_STM32F372V8 is not set +# CONFIG_ARCH_CHIP_STM32F372CB is not set +# CONFIG_ARCH_CHIP_STM32F372RB is not set +# CONFIG_ARCH_CHIP_STM32F372VB is not set +# CONFIG_ARCH_CHIP_STM32F372CC is not set +# CONFIG_ARCH_CHIP_STM32F372RC is not set +# CONFIG_ARCH_CHIP_STM32F372VC is not set +# CONFIG_ARCH_CHIP_STM32F373C8 is not set +# CONFIG_ARCH_CHIP_STM32F373R8 is not set +# CONFIG_ARCH_CHIP_STM32F373V8 is not set +# CONFIG_ARCH_CHIP_STM32F373CB is not set +# CONFIG_ARCH_CHIP_STM32F373RB is not set +# CONFIG_ARCH_CHIP_STM32F373VB is not set +# CONFIG_ARCH_CHIP_STM32F373CC is not set +# CONFIG_ARCH_CHIP_STM32F373RC is not set +# CONFIG_ARCH_CHIP_STM32F373VC is not set +# CONFIG_ARCH_CHIP_STM32F401RE is not set +# CONFIG_ARCH_CHIP_STM32F411RE is not set +# CONFIG_ARCH_CHIP_STM32F411VE is not set +# CONFIG_ARCH_CHIP_STM32F405RG is not set +# CONFIG_ARCH_CHIP_STM32F405VG is not set +# CONFIG_ARCH_CHIP_STM32F405ZG is not set +# CONFIG_ARCH_CHIP_STM32F407VE is not set +# CONFIG_ARCH_CHIP_STM32F407VG is not set +# CONFIG_ARCH_CHIP_STM32F407ZE is not set +CONFIG_ARCH_CHIP_STM32F407ZG=y +# CONFIG_ARCH_CHIP_STM32F407IE is not set +# CONFIG_ARCH_CHIP_STM32F407IG is not set +# CONFIG_ARCH_CHIP_STM32F427V is not set +# CONFIG_ARCH_CHIP_STM32F427Z is not set +# CONFIG_ARCH_CHIP_STM32F427I is not set +# CONFIG_ARCH_CHIP_STM32F429V is not set +# CONFIG_ARCH_CHIP_STM32F429Z is not set +# CONFIG_ARCH_CHIP_STM32F429I is not set +# CONFIG_ARCH_CHIP_STM32F429B is not set +# CONFIG_ARCH_CHIP_STM32F429N is not set +# CONFIG_ARCH_CHIP_STM32F446M is not set +# CONFIG_ARCH_CHIP_STM32F446R is not set +# CONFIG_ARCH_CHIP_STM32F446V is not set +# CONFIG_ARCH_CHIP_STM32F446Z is not set +# CONFIG_ARCH_CHIP_STM32F469A is not set +# CONFIG_ARCH_CHIP_STM32F469I is not set +# CONFIG_ARCH_CHIP_STM32F469B is not set +# CONFIG_ARCH_CHIP_STM32F469N is not set +CONFIG_STM32_FLASH_CONFIG_DEFAULT=y +# CONFIG_STM32_FLASH_CONFIG_4 is not set +# CONFIG_STM32_FLASH_CONFIG_6 is not set +# CONFIG_STM32_FLASH_CONFIG_8 is not set +# CONFIG_STM32_FLASH_CONFIG_B is not set +# CONFIG_STM32_FLASH_CONFIG_C is not set +# CONFIG_STM32_FLASH_CONFIG_D is not set +# CONFIG_STM32_FLASH_CONFIG_E is not set +# CONFIG_STM32_FLASH_CONFIG_F is not set +# CONFIG_STM32_FLASH_CONFIG_G is not set +# CONFIG_STM32_FLASH_CONFIG_I is not set +# CONFIG_STM32_STM32L15XX is not set +# CONFIG_STM32_ENERGYLITE is not set +# CONFIG_STM32_STM32F10XX is not set +# CONFIG_STM32_VALUELINE is not set +# CONFIG_STM32_CONNECTIVITYLINE is not set +# CONFIG_STM32_PERFORMANCELINE is not set +# CONFIG_STM32_USBACCESSLINE is not set +# CONFIG_STM32_HIGHDENSITY is not set +# CONFIG_STM32_MEDIUMDENSITY is not set +# CONFIG_STM32_LOWDENSITY is not set +# CONFIG_STM32_STM32F20XX is not set +# CONFIG_STM32_STM32F205 is not set +# CONFIG_STM32_STM32F207 is not set +# CONFIG_STM32_STM32F30XX is not set +# CONFIG_STM32_STM32F302 is not set +# CONFIG_STM32_STM32F303 is not set +# CONFIG_STM32_STM32F37XX is not set +CONFIG_STM32_STM32F40XX=y +# CONFIG_STM32_STM32F401 is not set +# CONFIG_STM32_STM32F411 is not set +# CONFIG_STM32_STM32F405 is not set +CONFIG_STM32_STM32F407=y +# CONFIG_STM32_STM32F427 is not set +# CONFIG_STM32_STM32F429 is not set +# CONFIG_STM32_STM32F446 is not set +# CONFIG_STM32_STM32F469 is not set +# CONFIG_STM32_DFU is not set + +# +# STM32 Peripheral Support +# +CONFIG_STM32_HAVE_CCM=y +# CONFIG_STM32_HAVE_USBDEV is not set +CONFIG_STM32_HAVE_OTGFS=y +CONFIG_STM32_HAVE_FSMC=y +# CONFIG_STM32_HAVE_LTDC is not set +CONFIG_STM32_HAVE_USART3=y +CONFIG_STM32_HAVE_UART4=y +CONFIG_STM32_HAVE_UART5=y +CONFIG_STM32_HAVE_USART6=y +# CONFIG_STM32_HAVE_UART7 is not set +# CONFIG_STM32_HAVE_UART8 is not set +CONFIG_STM32_HAVE_TIM1=y +CONFIG_STM32_HAVE_TIM2=y +CONFIG_STM32_HAVE_TIM3=y +CONFIG_STM32_HAVE_TIM4=y +CONFIG_STM32_HAVE_TIM5=y +CONFIG_STM32_HAVE_TIM6=y +CONFIG_STM32_HAVE_TIM7=y +CONFIG_STM32_HAVE_TIM8=y +CONFIG_STM32_HAVE_TIM9=y +CONFIG_STM32_HAVE_TIM10=y +CONFIG_STM32_HAVE_TIM11=y +CONFIG_STM32_HAVE_TIM12=y +CONFIG_STM32_HAVE_TIM13=y +CONFIG_STM32_HAVE_TIM14=y +# CONFIG_STM32_HAVE_TIM15 is not set +# CONFIG_STM32_HAVE_TIM16 is not set +# CONFIG_STM32_HAVE_TIM17 is not set +CONFIG_STM32_HAVE_ADC2=y +CONFIG_STM32_HAVE_ADC3=y +# CONFIG_STM32_HAVE_ADC4 is not set +# CONFIG_STM32_HAVE_ADC1_DMA is not set +# CONFIG_STM32_HAVE_ADC2_DMA is not set +# CONFIG_STM32_HAVE_ADC3_DMA is not set +# CONFIG_STM32_HAVE_ADC4_DMA is not set +CONFIG_STM32_HAVE_CAN1=y +CONFIG_STM32_HAVE_CAN2=y +CONFIG_STM32_HAVE_DAC1=y +CONFIG_STM32_HAVE_DAC2=y +CONFIG_STM32_HAVE_RNG=y +CONFIG_STM32_HAVE_ETHMAC=y +CONFIG_STM32_HAVE_I2C2=y +CONFIG_STM32_HAVE_I2C3=y +CONFIG_STM32_HAVE_SPI2=y +CONFIG_STM32_HAVE_SPI3=y +# CONFIG_STM32_HAVE_SPI4 is not set +# CONFIG_STM32_HAVE_SPI5 is not set +# CONFIG_STM32_HAVE_SPI6 is not set +# CONFIG_STM32_HAVE_SAIPLL is not set +# CONFIG_STM32_HAVE_I2SPLL is not set +# CONFIG_STM32_ADC1 is not set +# CONFIG_STM32_ADC2 is not set +# CONFIG_STM32_ADC3 is not set +# CONFIG_STM32_BKPSRAM is not set +# CONFIG_STM32_CAN1 is not set +# CONFIG_STM32_CAN2 is not set +# CONFIG_STM32_CCMDATARAM is not set +# CONFIG_STM32_CRC is not set +# CONFIG_STM32_CRYP is not set +# CONFIG_STM32_DMA1 is not set +# CONFIG_STM32_DMA2 is not set +# CONFIG_STM32_DAC1 is not set +# CONFIG_STM32_DAC2 is not set +# CONFIG_STM32_DCMI is not set +# CONFIG_STM32_ETHMAC is not set +# CONFIG_STM32_FSMC is not set +# CONFIG_STM32_HASH is not set +# CONFIG_STM32_I2C1 is not set +# CONFIG_STM32_I2C2 is not set +# CONFIG_STM32_I2C3 is not set +CONFIG_STM32_OTGFS=y +# CONFIG_STM32_OTGHS is not set +CONFIG_STM32_PWR=y +# CONFIG_STM32_RNG is not set +# CONFIG_STM32_SDIO is not set +# CONFIG_STM32_SPI1 is not set +# CONFIG_STM32_SPI2 is not set +# CONFIG_STM32_SPI3 is not set +CONFIG_STM32_SYSCFG=y +# CONFIG_STM32_TIM1 is not set +# CONFIG_STM32_TIM2 is not set +# CONFIG_STM32_TIM3 is not set +# CONFIG_STM32_TIM4 is not set +# CONFIG_STM32_TIM5 is not set +# CONFIG_STM32_TIM6 is not set +# CONFIG_STM32_TIM7 is not set +# CONFIG_STM32_TIM8 is not set +# CONFIG_STM32_TIM9 is not set +# CONFIG_STM32_TIM10 is not set +# CONFIG_STM32_TIM11 is not set +# CONFIG_STM32_TIM12 is not set +# CONFIG_STM32_TIM13 is not set +# CONFIG_STM32_TIM14 is not set +# CONFIG_STM32_USART1 is not set +CONFIG_STM32_USART2=y +# CONFIG_STM32_USART3 is not set +# CONFIG_STM32_UART4 is not set +# CONFIG_STM32_UART5 is not set +# CONFIG_STM32_USART6 is not set +# CONFIG_STM32_IWDG is not set +# CONFIG_STM32_WWDG is not set +# CONFIG_STM32_NOEXT_VECTORS is not set + +# +# Alternate Pin Mapping +# +# CONFIG_STM32_FLASH_PREFETCH is not set +# CONFIG_STM32_JTAG_DISABLE is not set +# CONFIG_STM32_JTAG_FULL_ENABLE is not set +# CONFIG_STM32_JTAG_NOJNTRST_ENABLE is not set +CONFIG_STM32_JTAG_SW_ENABLE=y +# CONFIG_STM32_DISABLE_IDLE_SLEEP_DURING_DEBUG is not set +# CONFIG_STM32_FORCEPOWER is not set +# CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG is not set +# CONFIG_STM32_CCMEXCLUDE is not set + +# +# Timer Configuration +# +# CONFIG_STM32_TIM1_CAP is not set +# CONFIG_STM32_TIM2_CAP is not set +# CONFIG_STM32_TIM3_CAP is not set +# CONFIG_STM32_TIM4_CAP is not set +# CONFIG_STM32_TIM5_CAP is not set +# CONFIG_STM32_TIM8_CAP is not set +# CONFIG_STM32_TIM9_CAP is not set +# CONFIG_STM32_TIM10_CAP is not set +# CONFIG_STM32_TIM11_CAP is not set +# CONFIG_STM32_TIM12_CAP is not set +# CONFIG_STM32_TIM13_CAP is not set +# CONFIG_STM32_TIM14_CAP is not set +CONFIG_STM32_USART=y +CONFIG_STM32_SERIALDRIVER=y + +# +# U[S]ART Configuration +# + +# +# U[S]ART Device Configuration +# +CONFIG_STM32_USART2_SERIALDRIVER=y +# CONFIG_STM32_USART2_1WIREDRIVER is not set +# CONFIG_USART2_RS485 is not set + +# +# Serial Driver Configuration +# +# CONFIG_SERIAL_DISABLE_REORDERING is not set +# CONFIG_STM32_FLOWCONTROL_BROKEN is not set +# CONFIG_STM32_USART_BREAKS is not set +# CONFIG_STM32_USART_SINGLEWIRE is not set +# CONFIG_STM32_HAVE_RTC_COUNTER is not set +# CONFIG_STM32_HAVE_RTC_SUBSECONDS is not set + +# +# USB FS Host Configuration +# + +# +# USB HS Host Configuration +# + +# +# USB Host Debug Configuration +# + +# +# USB Device Configuration +# + +# +# Architecture Options +# +# CONFIG_ARCH_NOINTC is not set +# CONFIG_ARCH_VECNOTIRQ is not set +# CONFIG_ARCH_DMA is not set +CONFIG_ARCH_HAVE_IRQPRIO=y +# CONFIG_ARCH_L2CACHE is not set +# CONFIG_ARCH_HAVE_COHERENT_DCACHE is not set +# CONFIG_ARCH_HAVE_ADDRENV is not set +# CONFIG_ARCH_NEED_ADDRENV_MAPPING is not set +# CONFIG_ARCH_HAVE_MULTICPU is not set +CONFIG_ARCH_HAVE_VFORK=y +# CONFIG_ARCH_HAVE_MMU is not set +CONFIG_ARCH_HAVE_MPU=y +# CONFIG_ARCH_NAND_HWECC is not set +# CONFIG_ARCH_HAVE_EXTCLK is not set +# CONFIG_ARCH_HAVE_POWEROFF is not set +CONFIG_ARCH_HAVE_RESET=y +# CONFIG_ARCH_USE_MPU is not set +# CONFIG_ARCH_IRQPRIO is not set +CONFIG_ARCH_STACKDUMP=y +# CONFIG_ENDIAN_BIG is not set +# CONFIG_ARCH_IDLE_CUSTOM is not set +# CONFIG_ARCH_HAVE_RAMFUNCS is not set +CONFIG_ARCH_HAVE_RAMVECTORS=y +# CONFIG_ARCH_RAMVECTORS is not set + +# +# Board Settings +# +CONFIG_BOARD_LOOPSPERMSEC=16717 +# CONFIG_ARCH_CALIBRATION is not set + +# +# Interrupt options +# +CONFIG_ARCH_HAVE_INTERRUPTSTACK=y +CONFIG_ARCH_INTERRUPTSTACK=0 +CONFIG_ARCH_HAVE_HIPRI_INTERRUPT=y +# CONFIG_ARCH_HIPRI_INTERRUPT is not set + +# +# Boot options +# +# CONFIG_BOOT_RUNFROMEXTSRAM is not set +CONFIG_BOOT_RUNFROMFLASH=y +# CONFIG_BOOT_RUNFROMISRAM is not set +# CONFIG_BOOT_RUNFROMSDRAM is not set +# CONFIG_BOOT_COPYTORAM is not set + +# +# Boot Memory Configuration +# +CONFIG_RAM_START=0x20000000 +CONFIG_RAM_SIZE=114688 +# CONFIG_ARCH_HAVE_SDRAM is not set + +# +# Board Selection +# +# CONFIG_ARCH_BOARD_OLIMEX_STM32H407 is not set +CONFIG_ARCH_BOARD_OLIMEX_STM32E407=y +# CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD="olimex-stm32-e407" + +# +# Common Board Options +# +CONFIG_ARCH_HAVE_LEDS=y +CONFIG_ARCH_LEDS=y +CONFIG_ARCH_HAVE_BUTTONS=y +CONFIG_ARCH_BUTTONS=y +CONFIG_ARCH_HAVE_IRQBUTTONS=y +# CONFIG_ARCH_IRQBUTTONS is not set + +# +# Board-Specific Options +# +# CONFIG_BOARD_CRASHDUMP is not set +CONFIG_LIB_BOARDCTL=y +# CONFIG_BOARDCTL_RESET is not set +# CONFIG_BOARDCTL_UNIQUEID is not set +CONFIG_BOARDCTL_USBDEVCTRL=y +# CONFIG_BOARDCTL_TSCTEST is not set +# CONFIG_BOARDCTL_ADCTEST is not set +# CONFIG_BOARDCTL_PWMTEST is not set +# CONFIG_BOARDCTL_GRAPHICS is not set +# CONFIG_BOARDCTL_IOCTL is not set + +# +# RTOS Features +# +CONFIG_DISABLE_OS_API=y +# CONFIG_DISABLE_POSIX_TIMERS is not set +# CONFIG_DISABLE_PTHREAD is not set +# CONFIG_DISABLE_SIGNALS is not set +# CONFIG_DISABLE_MQUEUE is not set +# CONFIG_DISABLE_ENVIRON is not set + +# +# Clocks and Timers +# +CONFIG_USEC_PER_TICK=10000 +# CONFIG_SYSTEM_TIME64 is not set +# CONFIG_CLOCK_MONOTONIC is not set +# CONFIG_JULIAN_TIME is not set +CONFIG_START_YEAR=2013 +CONFIG_START_MONTH=1 +CONFIG_START_DAY=27 +CONFIG_MAX_WDOGPARMS=2 +CONFIG_PREALLOC_WDOGS=8 +CONFIG_WDOG_INTRESERVE=1 +CONFIG_PREALLOC_TIMERS=4 + +# +# Tasks and Scheduling +# +# CONFIG_INIT_NONE is not set +CONFIG_INIT_ENTRYPOINT=y +# CONFIG_INIT_FILEPATH is not set +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_RR_INTERVAL=200 +# CONFIG_SCHED_SPORADIC is not set +CONFIG_TASK_NAME_SIZE=31 +CONFIG_MAX_TASKS=16 +# CONFIG_SCHED_HAVE_PARENT is not set +CONFIG_SCHED_WAITPID=y + +# +# Pthread Options +# +# CONFIG_MUTEX_TYPES is not set +CONFIG_NPTHREAD_KEYS=4 + +# +# Performance Monitoring +# +# CONFIG_SCHED_CPULOAD is not set +# CONFIG_SCHED_INSTRUMENTATION is not set + +# +# Files and I/O +# +# CONFIG_DEV_CONSOLE is not set +# CONFIG_FDCLONE_DISABLE is not set +# CONFIG_FDCLONE_STDIO is not set +CONFIG_SDCLONE_DISABLE=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NAME_MAX=32 +# CONFIG_PRIORITY_INHERITANCE is not set + +# +# RTOS hooks +# +# CONFIG_BOARD_INITIALIZE is not set +# CONFIG_SCHED_STARTHOOK is not set +# CONFIG_SCHED_ATEXIT is not set +# CONFIG_SCHED_ONEXIT is not set + +# +# Signal Numbers +# +CONFIG_SIG_SIGUSR1=1 +CONFIG_SIG_SIGUSR2=2 +CONFIG_SIG_SIGALARM=3 +CONFIG_SIG_SIGCONDTIMEDOUT=16 + +# +# POSIX Message Queue Options +# +CONFIG_PREALLOC_MQ_MSGS=4 +CONFIG_MQ_MAXMSGSIZE=32 +# CONFIG_MODULE is not set + +# +# Work queue support +# +# CONFIG_SCHED_WORKQUEUE is not set +# CONFIG_SCHED_HPWORK is not set +# CONFIG_SCHED_LPWORK is not set + +# +# Stack and heap information +# +CONFIG_IDLETHREAD_STACKSIZE=2048 +CONFIG_USERMAIN_STACKSIZE=2048 +CONFIG_PTHREAD_STACK_MIN=256 +CONFIG_PTHREAD_STACK_DEFAULT=2048 +# CONFIG_LIB_SYSCALL is not set + +# +# Device Drivers +# +CONFIG_DISABLE_POLL=y +CONFIG_DEV_NULL=y +# CONFIG_DEV_ZERO is not set +# CONFIG_DEV_LOOP is not set + +# +# Buffering +# +# CONFIG_DRVR_WRITEBUFFER is not set +# CONFIG_DRVR_READAHEAD is not set +# CONFIG_RAMDISK is not set +# CONFIG_CAN is not set +# CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set +# CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set +# CONFIG_PWM is not set +CONFIG_ARCH_HAVE_I2CRESET=y +# CONFIG_I2C is not set +CONFIG_SPI=y +# CONFIG_SPI_SLAVE is not set +CONFIG_SPI_EXCHANGE=y +# CONFIG_SPI_CMDDATA is not set +# CONFIG_SPI_CALLBACK is not set +# CONFIG_SPI_BITBANG is not set +# CONFIG_SPI_HWFEATURES is not set +# CONFIG_SPI_CRCGENERATION is not set +# CONFIG_SPI_CS_CONTROL is not set +# CONFIG_SPI_CS_DELAY_CONTROL is not set +# CONFIG_I2S is not set + +# +# Timer Driver Support +# +# CONFIG_TIMER is not set +# CONFIG_RTC is not set +# CONFIG_WATCHDOG is not set +# CONFIG_ANALOG is not set +# CONFIG_AUDIO_DEVICES is not set +# CONFIG_VIDEO_DEVICES is not set +# CONFIG_BCH is not set +# CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# +# CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set + +# +# LCD Driver Support +# +# CONFIG_LCD is not set +# CONFIG_SLCD is not set + +# +# LED Support +# +# CONFIG_USERLED is not set +# CONFIG_RGBLED is not set +# CONFIG_PCA9635PW is not set +# CONFIG_NCP5623C is not set +# CONFIG_MMCSD is not set +# CONFIG_MODEM is not set +# CONFIG_MTD is not set +# CONFIG_EEPROM is not set +# CONFIG_PIPES is not set +# CONFIG_PM is not set +# CONFIG_POWER is not set +# CONFIG_SENSORS is not set +# CONFIG_SERCOMM_CONSOLE is not set +CONFIG_SERIAL=y +CONFIG_SERIAL_REMOVABLE=y +# CONFIG_SERIAL_CONSOLE is not set +# CONFIG_16550_UART is not set +# CONFIG_UART_SERIALDRIVER is not set +# CONFIG_UART0_SERIALDRIVER is not set +# CONFIG_UART1_SERIALDRIVER is not set +# CONFIG_UART2_SERIALDRIVER is not set +# CONFIG_UART3_SERIALDRIVER is not set +# CONFIG_UART4_SERIALDRIVER is not set +# CONFIG_UART5_SERIALDRIVER is not set +# CONFIG_UART6_SERIALDRIVER is not set +# CONFIG_UART7_SERIALDRIVER is not set +# CONFIG_UART8_SERIALDRIVER is not set +# CONFIG_SCI0_SERIALDRIVER is not set +# CONFIG_SCI1_SERIALDRIVER is not set +# CONFIG_USART0_SERIALDRIVER is not set +# CONFIG_USART1_SERIALDRIVER is not set +CONFIG_USART2_SERIALDRIVER=y +# CONFIG_USART3_SERIALDRIVER is not set +# CONFIG_USART4_SERIALDRIVER is not set +# CONFIG_USART5_SERIALDRIVER is not set +# CONFIG_USART6_SERIALDRIVER is not set +# CONFIG_USART7_SERIALDRIVER is not set +# CONFIG_USART8_SERIALDRIVER is not set +# CONFIG_OTHER_UART_SERIALDRIVER is not set +CONFIG_MCU_SERIAL=y +CONFIG_STANDARD_SERIAL=y +# CONFIG_SERIAL_IFLOWCONTROL is not set +# CONFIG_SERIAL_OFLOWCONTROL is not set +# CONFIG_SERIAL_DMA is not set +CONFIG_ARCH_HAVE_SERIAL_TERMIOS=y +# CONFIG_USART2_SERIAL_CONSOLE is not set +# CONFIG_OTHER_SERIAL_CONSOLE is not set +CONFIG_NO_SERIAL_CONSOLE=y + +# +# USART2 Configuration +# +CONFIG_USART2_RXBUFSIZE=256 +CONFIG_USART2_TXBUFSIZE=256 +CONFIG_USART2_BAUD=115200 +CONFIG_USART2_BITS=8 +CONFIG_USART2_PARITY=0 +CONFIG_USART2_2STOP=0 +# CONFIG_USART2_IFLOWCONTROL is not set +# CONFIG_USART2_OFLOWCONTROL is not set +# CONFIG_USART2_DMA is not set +CONFIG_USBDEV=y + +# +# USB Device Controller Driver Options +# +# CONFIG_USBDEV_ISOCHRONOUS is not set +# CONFIG_USBDEV_DUALSPEED is not set +CONFIG_USBDEV_SELFPOWERED=y +# CONFIG_USBDEV_BUSPOWERED is not set +CONFIG_USBDEV_MAXPOWER=100 +# CONFIG_USBDEV_DMA is not set +# CONFIG_ARCH_USBDEV_STALLQUEUE is not set +# CONFIG_USBDEV_TRACE is not set + +# +# USB Device Class Driver Options +# +# CONFIG_USBDEV_COMPOSITE is not set +# CONFIG_PL2303 is not set +CONFIG_CDCACM=y +CONFIG_CDCACM_CONSOLE=y +CONFIG_CDCACM_EP0MAXPACKET=64 +CONFIG_CDCACM_EPINTIN=1 +CONFIG_CDCACM_EPINTIN_FSSIZE=64 +CONFIG_CDCACM_EPINTIN_HSSIZE=64 +CONFIG_CDCACM_EPBULKOUT=3 +CONFIG_CDCACM_EPBULKOUT_FSSIZE=64 +CONFIG_CDCACM_EPBULKOUT_HSSIZE=512 +CONFIG_CDCACM_EPBULKIN=2 +CONFIG_CDCACM_EPBULKIN_FSSIZE=64 +CONFIG_CDCACM_EPBULKIN_HSSIZE=512 +CONFIG_CDCACM_NRDREQS=4 +CONFIG_CDCACM_NWRREQS=4 +CONFIG_CDCACM_BULKIN_REQLEN=96 +CONFIG_CDCACM_RXBUFSIZE=256 +CONFIG_CDCACM_TXBUFSIZE=256 +CONFIG_CDCACM_VENDORID=0x0525 +CONFIG_CDCACM_PRODUCTID=0xa4a7 +CONFIG_CDCACM_VENDORSTR="NuttX" +CONFIG_CDCACM_PRODUCTSTR="CDC/ACM Serial" +# CONFIG_USBMSC is not set +# CONFIG_USBHOST is not set +# CONFIG_DRIVERS_WIRELESS is not set + +# +# System Logging +# +# CONFIG_ARCH_SYSLOG is not set +# CONFIG_RAMLOG is not set +# CONFIG_SYSLOG_INTBUFFER is not set +# CONFIG_SYSLOG_TIMESTAMP is not set +# CONFIG_SYSLOG_SERIAL_CONSOLE is not set +CONFIG_SYSLOG_CHAR=y +# CONFIG_SYSLOG_NONE is not set +# CONFIG_SYSLOG_FILE is not set +CONFIG_SYSLOG_CHAR_CRLF=y +CONFIG_SYSLOG_DEVPATH="/dev/ttyS0" + +# +# Networking Support +# +# CONFIG_ARCH_HAVE_NET is not set +# CONFIG_ARCH_HAVE_PHY is not set +# CONFIG_NET is not set + +# +# Crypto API +# +# CONFIG_CRYPTO is not set + +# +# File Systems +# + +# +# File system configuration +# +# CONFIG_DISABLE_MOUNTPOINT is not set +# CONFIG_FS_AUTOMOUNTER is not set +# CONFIG_DISABLE_PSEUDOFS_OPERATIONS is not set +CONFIG_FS_READABLE=y +# CONFIG_FS_WRITABLE is not set +# CONFIG_FS_NAMED_SEMAPHORES is not set +CONFIG_FS_MQUEUE_MPATH="/var/mqueue" +# CONFIG_FS_RAMMAP is not set +# CONFIG_FS_FAT is not set +# CONFIG_FS_NXFFS is not set +# CONFIG_FS_ROMFS is not set +# CONFIG_FS_TMPFS is not set +# CONFIG_FS_SMARTFS is not set +# CONFIG_FS_BINFS is not set +CONFIG_FS_PROCFS=y +# CONFIG_FS_PROCFS_REGISTER is not set + +# +# Exclude individual procfs entries +# +# CONFIG_FS_PROCFS_EXCLUDE_PROCESS is not set +# CONFIG_FS_PROCFS_EXCLUDE_UPTIME is not set +# CONFIG_FS_PROCFS_EXCLUDE_MOUNTS is not set +# CONFIG_FS_UNIONFS is not set + +# +# Graphics Support +# +# CONFIG_NX is not set + +# +# Memory Management +# +# CONFIG_MM_SMALL is not set +CONFIG_MM_REGIONS=2 +# CONFIG_ARCH_HAVE_HEAP2 is not set +# CONFIG_GRAN is not set + +# +# Audio Support +# +# CONFIG_AUDIO is not set + +# +# Wireless Support +# + +# +# Binary Loader +# +# CONFIG_BINFMT_DISABLE is not set +# CONFIG_BINFMT_EXEPATH is not set +# CONFIG_NXFLAT is not set +# CONFIG_ELF is not set +CONFIG_BUILTIN=y +# CONFIG_PIC is not set +# CONFIG_SYMTAB_ORDEREDBYNAME is not set + +# +# Library Routines +# + +# +# Standard C Library Options +# +CONFIG_STDIO_BUFFER_SIZE=64 +CONFIG_STDIO_LINEBUFFER=y +CONFIG_NUNGET_CHARS=2 +CONFIG_LIB_HOMEDIR="/" +# CONFIG_LIBM is not set +# CONFIG_NOPRINTF_FIELDWIDTH is not set +# CONFIG_LIBC_FLOATINGPOINT is not set +CONFIG_LIBC_LONG_LONG=y +# CONFIG_LIBC_IOCTL_VARIADIC is not set +CONFIG_LIB_RAND_ORDER=1 +# CONFIG_EOL_IS_CR is not set +# CONFIG_EOL_IS_LF is not set +# CONFIG_EOL_IS_BOTH_CRLF is not set +CONFIG_EOL_IS_EITHER_CRLF=y +# CONFIG_LIBC_EXECFUNCS is not set +CONFIG_POSIX_SPAWN_PROXY_STACKSIZE=1024 +CONFIG_TASK_SPAWN_DEFAULT_STACKSIZE=2048 +# CONFIG_LIBC_STRERROR is not set +# CONFIG_LIBC_PERROR_STDOUT is not set +CONFIG_ARCH_LOWPUTC=y +# CONFIG_LIBC_LOCALTIME is not set +# CONFIG_TIME_EXTENDED is not set +CONFIG_LIB_SENDFILE_BUFSIZE=512 +# CONFIG_ARCH_ROMGETC is not set +# CONFIG_ARCH_OPTIMIZED_FUNCTIONS is not set +CONFIG_ARCH_HAVE_TLS=y +# CONFIG_TLS is not set +# CONFIG_LIBC_NETDB is not set +# CONFIG_NETDB_HOSTFILE is not set + +# +# Non-standard Library Support +# +# CONFIG_LIB_CRC64_FAST is not set +# CONFIG_LIB_KBDCODEC is not set +# CONFIG_LIB_SLCDCODEC is not set + +# +# Basic CXX Support +# +# CONFIG_C99_BOOL8 is not set +CONFIG_HAVE_CXX=y +CONFIG_HAVE_CXXINITIALIZE=y +# CONFIG_CXX_NEWLONG is not set + +# +# uClibc++ Standard C++ Library +# +# CONFIG_UCLIBCXX is not set + +# +# Application Configuration +# + +# +# Built-In Applications +# +CONFIG_BUILTIN_PROXY_STACKSIZE=1024 + +# +# CAN Utilities +# + +# +# Examples +# +# CONFIG_EXAMPLES_BUTTONS is not set +# CONFIG_EXAMPLES_CHAT is not set +# CONFIG_EXAMPLES_CONFIGDATA is not set +# CONFIG_EXAMPLES_CPUHOG is not set +# CONFIG_EXAMPLES_CXXTEST is not set +# CONFIG_EXAMPLES_DHCPD is not set +# CONFIG_EXAMPLES_ELF is not set +# CONFIG_EXAMPLES_FTPC is not set +# CONFIG_EXAMPLES_FTPD is not set +CONFIG_EXAMPLES_HELLO=y +CONFIG_EXAMPLES_HELLO_PRIORITY=100 +CONFIG_EXAMPLES_HELLO_STACKSIZE=2048 +CONFIG_EXAMPLES_HELLOXX=y +CONFIG_EXAMPLES_HELLOXX_CXXINITIALIZE=y +# CONFIG_EXAMPLES_HIDKBD is not set +# CONFIG_EXAMPLES_IGMP is not set +# CONFIG_EXAMPLES_JSON is not set +# CONFIG_EXAMPLES_KEYPADTEST is not set +# CONFIG_EXAMPLES_MEDIA is not set +# CONFIG_EXAMPLES_MM is not set +# CONFIG_EXAMPLES_MODBUS is not set +# CONFIG_EXAMPLES_MOUNT is not set +# CONFIG_EXAMPLES_NRF24L01TERM is not set +CONFIG_EXAMPLES_NSH=y +CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y +# CONFIG_EXAMPLES_NULL is not set +# CONFIG_EXAMPLES_NX is not set +# CONFIG_EXAMPLES_NXFFS is not set +# CONFIG_EXAMPLES_NXHELLO is not set +# CONFIG_EXAMPLES_NXIMAGE is not set +# CONFIG_EXAMPLES_NXLINES is not set +# CONFIG_EXAMPLES_NXTERM is not set +# CONFIG_EXAMPLES_NXTEXT is not set +# CONFIG_EXAMPLES_OSTEST is not set +# CONFIG_EXAMPLES_PCA9635 is not set +# CONFIG_EXAMPLES_PIPE is not set +# CONFIG_EXAMPLES_POSIXSPAWN is not set +# CONFIG_EXAMPLES_PPPD is not set +# CONFIG_EXAMPLES_RGBLED is not set +# CONFIG_EXAMPLES_RGMP is not set +# CONFIG_EXAMPLES_SENDMAIL is not set +# CONFIG_EXAMPLES_SERIALBLASTER is not set +# CONFIG_EXAMPLES_SERIALRX is not set +# CONFIG_EXAMPLES_SERLOOP is not set +# CONFIG_EXAMPLES_SLCD is not set +# CONFIG_EXAMPLES_SMART is not set +# CONFIG_EXAMPLES_SMART_TEST is not set +# CONFIG_EXAMPLES_SMP is not set +# CONFIG_EXAMPLES_TCPECHO is not set +# CONFIG_EXAMPLES_TELNETD is not set +# CONFIG_EXAMPLES_TIFF is not set +# CONFIG_EXAMPLES_TOUCHSCREEN is not set +# CONFIG_EXAMPLES_USBSERIAL is not set +# CONFIG_EXAMPLES_USBTERM is not set +# CONFIG_EXAMPLES_WATCHDOG is not set +# CONFIG_EXAMPLES_WEBSERVER is not set + +# +# File System Utilities +# +# CONFIG_FSUTILS_INIFILE is not set +# CONFIG_FSUTILS_PASSWD is not set + +# +# GPS Utilities +# +# CONFIG_GPSUTILS_MINMEA_LIB is not set + +# +# Graphics Support +# +# CONFIG_TIFF is not set +# CONFIG_GRAPHICS_TRAVELER is not set + +# +# Interpreters +# +# CONFIG_INTERPRETERS_BAS is not set +# CONFIG_INTERPRETERS_FICL is not set +# CONFIG_INTERPRETERS_MICROPYTHON is not set +# CONFIG_INTERPRETERS_PCODE is not set + +# +# FreeModBus +# +# CONFIG_MODBUS is not set + +# +# Network Utilities +# +# CONFIG_NETUTILS_CODECS is not set +# CONFIG_NETUTILS_ESP8266 is not set +# CONFIG_NETUTILS_FTPC is not set +# CONFIG_NETUTILS_JSON is not set +# CONFIG_NETUTILS_SMTP is not set + +# +# NSH Library +# +CONFIG_NSH_LIBRARY=y +# CONFIG_NSH_MOTD is not set + +# +# Command Line Configuration +# +CONFIG_NSH_READLINE=y +# CONFIG_NSH_CLE is not set +CONFIG_NSH_LINELEN=64 +# CONFIG_NSH_DISABLE_SEMICOLON is not set +CONFIG_NSH_CMDPARMS=y +CONFIG_NSH_MAXARGUMENTS=6 +CONFIG_NSH_ARGCAT=y +CONFIG_NSH_NESTDEPTH=3 +# CONFIG_NSH_DISABLEBG is not set +CONFIG_NSH_BUILTIN_APPS=y + +# +# Disable Individual commands +# +# CONFIG_NSH_DISABLE_ADDROUTE is not set +# CONFIG_NSH_DISABLE_BASENAME is not set +# CONFIG_NSH_DISABLE_CAT is not set +# CONFIG_NSH_DISABLE_CD is not set +# CONFIG_NSH_DISABLE_CP is not set +# CONFIG_NSH_DISABLE_CMP is not set +CONFIG_NSH_DISABLE_DATE=y +# CONFIG_NSH_DISABLE_DD is not set +# CONFIG_NSH_DISABLE_DF is not set +# CONFIG_NSH_DISABLE_DELROUTE is not set +# CONFIG_NSH_DISABLE_DIRNAME is not set +# CONFIG_NSH_DISABLE_ECHO is not set +# CONFIG_NSH_DISABLE_EXEC is not set +# CONFIG_NSH_DISABLE_EXIT is not set +# CONFIG_NSH_DISABLE_FREE is not set +# CONFIG_NSH_DISABLE_GET is not set +# CONFIG_NSH_DISABLE_HELP is not set +# CONFIG_NSH_DISABLE_HEXDUMP is not set +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_IFUPDOWN is not set +# CONFIG_NSH_DISABLE_KILL is not set +# CONFIG_NSH_DISABLE_LOSETUP is not set +CONFIG_NSH_DISABLE_LOSMART=y +# CONFIG_NSH_DISABLE_LS is not set +# CONFIG_NSH_DISABLE_MB is not set +# CONFIG_NSH_DISABLE_MKDIR is not set +# CONFIG_NSH_DISABLE_MKFIFO is not set +# CONFIG_NSH_DISABLE_MKRD is not set +# CONFIG_NSH_DISABLE_MH is not set +# CONFIG_NSH_DISABLE_MOUNT is not set +# CONFIG_NSH_DISABLE_MV is not set +# CONFIG_NSH_DISABLE_MW is not set +# CONFIG_NSH_DISABLE_PS is not set +# CONFIG_NSH_DISABLE_PUT is not set +# CONFIG_NSH_DISABLE_PWD is not set +# CONFIG_NSH_DISABLE_RM is not set +# CONFIG_NSH_DISABLE_RMDIR is not set +# CONFIG_NSH_DISABLE_SET is not set +# CONFIG_NSH_DISABLE_SH is not set +# CONFIG_NSH_DISABLE_SLEEP is not set +# CONFIG_NSH_DISABLE_TIME is not set +# CONFIG_NSH_DISABLE_TEST is not set +# CONFIG_NSH_DISABLE_UMOUNT is not set +# CONFIG_NSH_DISABLE_UNAME is not set +# CONFIG_NSH_DISABLE_UNSET is not set +# CONFIG_NSH_DISABLE_USLEEP is not set +# CONFIG_NSH_DISABLE_WGET is not set +# CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 + +# +# Configure Command Options +# +CONFIG_NSH_CMDOPT_DF_H=y +CONFIG_NSH_CODECS_BUFSIZE=128 +CONFIG_NSH_CMDOPT_HEXDUMP=y +CONFIG_NSH_PROC_MOUNTPOINT="/proc" +CONFIG_NSH_FILEIOSIZE=512 + +# +# Scripting Support +# +# CONFIG_NSH_DISABLESCRIPT is not set +# CONFIG_NSH_DISABLE_ITEF is not set +# CONFIG_NSH_DISABLE_LOOPS is not set + +# +# Console Configuration +# +CONFIG_NSH_CONSOLE=y +# CONFIG_NSH_USBCONSOLE is not set +# CONFIG_NSH_ALTCONDEV is not set +CONFIG_NSH_ARCHINIT=y +# CONFIG_NSH_LOGIN is not set +# CONFIG_NSH_CONSOLE_LOGIN is not set + +# +# NxWidgets/NxWM +# + +# +# Platform-specific Support +# +# CONFIG_PLATFORM_CONFIGDATA is not set + +# +# System Libraries and NSH Add-Ons +# +# CONFIG_SYSTEM_CDCACM is not set +# CONFIG_SYSTEM_CLE is not set +# CONFIG_SYSTEM_CUTERM is not set +# CONFIG_SYSTEM_FREE is not set +# CONFIG_LIB_HEX2BIN is not set +# CONFIG_SYSTEM_HEXED is not set +# CONFIG_SYSTEM_INSTALL is not set +# CONFIG_SYSTEM_RAMTEST is not set +CONFIG_READLINE_HAVE_EXTMATCH=y +CONFIG_SYSTEM_READLINE=y +CONFIG_READLINE_ECHO=y +# CONFIG_READLINE_TABCOMPLETION is not set +# CONFIG_READLINE_CMD_HISTORY is not set +# CONFIG_SYSTEM_SUDOKU is not set +# CONFIG_SYSTEM_UBLOXMODEM is not set +# CONFIG_SYSTEM_VI is not set +# CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/olimex-stm32-e407/usbnsh/setenv.sh b/configs/olimex-stm32-e407/usbnsh/setenv.sh new file mode 100755 index 0000000000000000000000000000000000000000..e5b5af7104d2f93cccb17a26048b0761bc97cc57 --- /dev/null +++ b/configs/olimex-stm32-e407/usbnsh/setenv.sh @@ -0,0 +1,80 @@ +#!/bin/bash +# configs/olimex-stm32-e407/usbnsh/setenv.sh +# +# Copyright (C) 2013 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +if [ "$_" = "$0" ] ; then + echo "You must source this script, not run it!" 1>&2 + exit 1 +fi + +WD=`pwd` +if [ ! -x "setenv.sh" ]; then + echo "This script must be executed from the top-level NuttX build directory" + exit 1 +fi + +if [ -z "${PATH_ORIG}" ]; then + export PATH_ORIG="${PATH}" +fi + +# This is the Cygwin path to the location where I installed the RIDE +# toolchain under windows. You will also have to edit this if you install +# the RIDE toolchain in any other location +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/Raisonance/Ride/arm-gcc/bin" + +# This is the Cygwin path to the location where I installed the CodeSourcery +# toolchain under windows. You will also have to edit this if you install +# the CodeSourcery toolchain in any other location +export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/CodeSourcery/Sourcery G++ Lite/bin" +#export TOOLCHAIN_BIN="/cygdrive/c/Users/MyName/MentorGraphics/Sourcery_CodeBench_Lite_for_ARM_EABI/bin" + +# This is the location where I installed the ARM "GNU Tools for ARM Embedded Processors" +# You can this free toolchain here https://launchpad.net/gcc-arm-embedded +#export TOOLCHAIN_BIN="/cygdrive/c/Program Files (x86)/GNU Tools ARM Embedded/4.9 2015q2/bin" + +# These are the Cygwin paths to the locations where I installed the Atollic +# toolchain under windows. You will also have to edit this if you install +# the Atollic toolchain in any other location. /usr/bin is added before +# the Atollic bin path because there is are binaries named gcc.exe and g++.exe +# at those locations as well. +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for ARM Pro 2.3.0/ARMTools/bin" +#export TOOLCHAIN_BIN="/usr/bin:/cygdrive/c/Program Files (x86)/Atollic/TrueSTUDIO for STMicroelectronics STM32 Lite 2.3.0/ARMTools/bin" + +# This is the Cygwin path to the location where I build the buildroot +# toolchain. +#export TOOLCHAIN_BIN="${WD}/../buildroot/build_arm_nofpu/staging_dir/bin" + +# Add the path to the toolchain to the PATH varialble +export PATH="${TOOLCHAIN_BIN}:/sbin:/usr/sbin:${PATH_ORIG}" + +echo "PATH : ${PATH}" diff --git a/configs/olimex-stm32-h405/src/stm32_appinit.c b/configs/olimex-stm32-h405/src/stm32_appinit.c index 776b5ffa5c352cc16d4c72d31ee7761131469af7..ed8b8fe846b34fa6509b222082b137415b1e7c12 100644 --- a/configs/olimex-stm32-h405/src/stm32_appinit.c +++ b/configs/olimex-stm32-h405/src/stm32_appinit.c @@ -46,8 +46,8 @@ #include -#ifdef CONFIG_SYSTEM_USBMONITOR -# include +#ifdef CONFIG_USBMONITOR +# include #endif #ifdef CONFIG_STM32_OTGFS diff --git a/configs/olimex-stm32-h405/usbnsh/defconfig b/configs/olimex-stm32-h405/usbnsh/defconfig index ef7d128fb99ca33d67ca889cee9786ee71780fbb..807518f8731d1fd821f4959f0a813ac7c369b394 100644 --- a/configs/olimex-stm32-h405/usbnsh/defconfig +++ b/configs/olimex-stm32-h405/usbnsh/defconfig @@ -1245,7 +1245,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/olimex-stm32-h407/nsh/defconfig b/configs/olimex-stm32-h407/nsh/defconfig index 4acf5a553f66b1dbfa17d14b71293680b4038bc4..9c4da0d2fe41bbcbed044740dad88ecd28a1e5f2 100644 --- a/configs/olimex-stm32-h407/nsh/defconfig +++ b/configs/olimex-stm32-h407/nsh/defconfig @@ -1156,7 +1156,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/olimex-stm32-h407/scripts/ld.script b/configs/olimex-stm32-h407/scripts/ld.script index 8cb28bca0723233abe88257e020dcc7c3da5a207..a476753cf2974baf258f42eab59d1fea517aec36 100644 --- a/configs/olimex-stm32-h407/scripts/ld.script +++ b/configs/olimex-stm32-h407/scripts/ld.script @@ -1,5 +1,5 @@ /**************************************************************************** - * configs/olimex-stm32-h405/scripts/ld.script + * configs/olimex-stm32-h407/scripts/ld.script * * Copyright (C) 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt diff --git a/configs/olimex-stm32-h407/src/olimex-stm32-h407.h b/configs/olimex-stm32-h407/src/olimex-stm32-h407.h index 766ddb9c7b536a764380209890f207b16123fa67..6687ef897a7e0b1dd8f3aa9be9f1479fe4e74ffd 100644 --- a/configs/olimex-stm32-h407/src/olimex-stm32-h407.h +++ b/configs/olimex-stm32-h407/src/olimex-stm32-h407.h @@ -78,7 +78,7 @@ /* Check if we should enable the USB monitor before starting NSH */ -#if !defined(CONFIG_USBDEV_TRACE) || !defined(CONFIG_SYSTEM_USBMONITOR) +#if !defined(CONFIG_USBDEV_TRACE) || !defined(CONFIG_USBMONITOR) # undef HAVE_USBMONITOR #endif diff --git a/configs/olimex-stm32-h407/src/stm32_appinit.c b/configs/olimex-stm32-h407/src/stm32_appinit.c index 6f0cd2dd64af7478ccd3174802b1ec192a3aa875..d87ae0670ab9cc8c353432ed78ed254b1cc0e130 100644 --- a/configs/olimex-stm32-h407/src/stm32_appinit.c +++ b/configs/olimex-stm32-h407/src/stm32_appinit.c @@ -46,8 +46,8 @@ #include -#ifdef CONFIG_SYSTEM_USBMONITOR -# include +#ifdef CONFIG_USBMONITOR +# include #endif #ifdef CONFIG_STM32_OTGFS diff --git a/configs/olimex-stm32-h407/src/stm32_bringup.c b/configs/olimex-stm32-h407/src/stm32_bringup.c index 9c683a1158cd137bc480744ff72e88ee4c84d572..73e29d5037f02d750b67e381f88b0e7ec4167b88 100644 --- a/configs/olimex-stm32-h407/src/stm32_bringup.c +++ b/configs/olimex-stm32-h407/src/stm32_bringup.c @@ -46,8 +46,8 @@ #include -#ifdef CONFIG_SYSTEM_USBMONITOR -# include +#ifdef CONFIG_USBMONITOR +# include #endif #ifdef CONFIG_STM32_OTGFS @@ -152,7 +152,7 @@ int stm32_bringup(void) #ifdef HAVE_USBMONITOR /* Start the USB Monitor */ - ret = usbmonitor_start(0, NULL); + ret = usbmonitor_start(); if (ret != OK) { syslog(LOG_ERR, diff --git a/configs/olimex-stm32-h407/src/stm32_buttons.c b/configs/olimex-stm32-h407/src/stm32_buttons.c index 24bcc1ee34ca04e956d77efde3afa669988a7999..47873bf39b5dc4f9505155163855269e0ebb1d1b 100644 --- a/configs/olimex-stm32-h407/src/stm32_buttons.c +++ b/configs/olimex-stm32-h407/src/stm32_buttons.c @@ -70,10 +70,10 @@ static const uint32_t g_buttons[NUM_BUTTONS] = * Name: board_button_initialize * * Description: - * board_button_initialize() must be called to initialize button resources. After - * that, board_buttons() may be called to collect the current state of all - * buttons or board_button_irq() may be called to register button interrupt - * handlers. + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. * ****************************************************************************/ @@ -109,28 +109,28 @@ uint8_t board_buttons(void) return ret; } -/************************************************************************************ +/**************************************************************************** * Button support. * * Description: - * board_button_initialize() must be called to initialize button resources. After - * that, board_buttons() may be called to collect the current state of all - * buttons or board_button_irq() may be called to register button interrupt - * handlers. + * board_button_initialize() must be called to initialize button resources. + * After that, board_buttons() may be called to collect the current state + * of all buttons or board_button_irq() may be called to register button + * interrupt handlers. * - * After board_button_initialize() has been called, board_buttons() may be called to - * collect the state of all buttons. board_buttons() returns an 8-bit bit set - * with each bit associated with a button. See the BUTTON_*_BIT + * After board_button_initialize() has been called, board_buttons() may be + * called to collect the state of all buttons. board_buttons() returns an + * 8-bit bit set with each bit associated with a button. See the BUTTON_*_BIT * definitions in board.h for the meaning of each bit. * - * board_button_irq() may be called to register an interrupt handler that will - * be called when a button is depressed or released. The ID value is a - * button enumeration value that uniquely identifies a button resource. See the - * BUTTON_* definitions in board.h for the meaning of enumeration - * value. The previous interrupt handler address is returned (so that it may - * restored, if so desired). + * board_button_irq() may be called to register an interrupt handler that + * will be called when a button is depressed or released. The ID value is + * a button enumeration value that uniquely identifies a button resource. + * See the BUTTON_* definitions in board.h for the meaning of enumeration + * value. The previous interrupt handler address is returned (so that it + * may restored, if so desired). * - ************************************************************************************/ + ****************************************************************************/ #ifdef CONFIG_ARCH_IRQBUTTONS xcpt_t board_button_irq(int id, xcpt_t irqhandler) diff --git a/configs/olimex-stm32-h407/src/stm32_can.c b/configs/olimex-stm32-h407/src/stm32_can.c index d293ee960c0e7652a385154bae15f4af762dbeae..c401e0c4111e08c12d28418a3bad52673348c776 100644 --- a/configs/olimex-stm32-h407/src/stm32_can.c +++ b/configs/olimex-stm32-h407/src/stm32_can.c @@ -83,13 +83,13 @@ int board_can_initialize(void) return stm32_can_initialize(); } -/**************************************************************************************************** +/************************************************************************************ * Name: stm32_can_initialize * * Description: * Called at application startup time to initialize the CAN functionality. * - ****************************************************************************************************/ + ************************************************************************************/ int stm32_can_initialize(void) { diff --git a/configs/olimex-stm32-p107/nsh/defconfig b/configs/olimex-stm32-p107/nsh/defconfig index 1065df7ce9a9d135318d4d8d8b13d2ba64d24873..49aeb5af0321b9270c47b0801ce57dd919587717 100644 --- a/configs/olimex-stm32-p107/nsh/defconfig +++ b/configs/olimex-stm32-p107/nsh/defconfig @@ -1366,7 +1366,7 @@ CONFIG_NSH_MAX_ROUNDTRIP=20 # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FLASH_ERASEALL is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/olimex-stm32-p207/nsh/defconfig b/configs/olimex-stm32-p207/nsh/defconfig index ec99e3837a89bc3268421fd3410348a811af591c..bcd74d2971e7c60e22b37e6e51f98699e63a474f 100644 --- a/configs/olimex-stm32-p207/nsh/defconfig +++ b/configs/olimex-stm32-p207/nsh/defconfig @@ -1431,7 +1431,7 @@ CONFIG_NSH_MAX_ROUNDTRIP=20 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/olimex-stm32-p207/src/stm32_appinit.c b/configs/olimex-stm32-p207/src/stm32_appinit.c index 695cc0607b4038609a3b9bf5db26eba1bcc558cb..fa3fce23f291384c345639fb32f22b4daf421734 100644 --- a/configs/olimex-stm32-p207/src/stm32_appinit.c +++ b/configs/olimex-stm32-p207/src/stm32_appinit.c @@ -46,8 +46,8 @@ #include -#ifdef CONFIG_SYSTEM_USBMONITOR -# include +#ifdef CONFIG_USBMONITOR +# include #endif #ifdef CONFIG_STM32_OTGFS @@ -90,7 +90,7 @@ /* Check if we should enable the USB monitor before starting NSH */ -#if !defined(CONFIG_USBDEV_TRACE) || !defined(CONFIG_SYSTEM_USBMONITOR) +#if !defined(CONFIG_USBDEV_TRACE) || !defined(CONFIG_USBMONITOR) # undef HAVE_USBMONITOR #endif @@ -172,7 +172,7 @@ int board_app_initialize(uintptr_t arg) #ifdef HAVE_USBMONITOR /* Start the USB Monitor */ - ret = usbmonitor_start(0, NULL); + ret = usbmonitor_start(); if (ret != OK) { syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); diff --git a/configs/olimex-strp711/nettest/defconfig b/configs/olimex-strp711/nettest/defconfig index 1dc02704630a6626a8f15ca849d7c72c73ffa140..0d4a5ee0fbe204fc2474275eaf7d873eb89b68ad 100644 --- a/configs/olimex-strp711/nettest/defconfig +++ b/configs/olimex-strp711/nettest/defconfig @@ -878,7 +878,7 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/olimex-strp711/nsh/defconfig b/configs/olimex-strp711/nsh/defconfig index ed9e622b0df417b3b16da66b6aac2a5a7cd94834..929705039252cd07a259d576e5621d86df78cd7f 100644 --- a/configs/olimex-strp711/nsh/defconfig +++ b/configs/olimex-strp711/nsh/defconfig @@ -856,7 +856,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/olimexino-stm32/can/defconfig b/configs/olimexino-stm32/can/defconfig index 9366accf055adca387545542830eb1e964898a15..dbb0994a9dd9d4b32adbefb431848d604ddcac73 100644 --- a/configs/olimexino-stm32/can/defconfig +++ b/configs/olimexino-stm32/can/defconfig @@ -1206,7 +1206,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_I2CTOOL is not set # CONFIG_SYSTEM_INSTALL is not set diff --git a/configs/olimexino-stm32/composite/defconfig b/configs/olimexino-stm32/composite/defconfig index a58f83346f97f5bbfae4682a63c4c9dcf75c376c..9a409e64604a4da165c03e924a036dceac0d4299 100644 --- a/configs/olimexino-stm32/composite/defconfig +++ b/configs/olimexino-stm32/composite/defconfig @@ -1314,7 +1314,7 @@ CONFIG_SYSTEM_COMPOSITE_BUFSIZE=256 # CONFIG_SYSTEM_COMPOSITE_DEBUGMM is not set # CONFIG_SYSTEM_CUTERM is not set CONFIG_SYSTEM_FREE=y -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/olimexino-stm32/nsh/defconfig b/configs/olimexino-stm32/nsh/defconfig index e963472cb3c4cac9b6158587d5e14f8a3aef0bbe..57700957550872addaed463c34d27a9ac62eaaf2 100644 --- a/configs/olimexino-stm32/nsh/defconfig +++ b/configs/olimexino-stm32/nsh/defconfig @@ -1229,7 +1229,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set CONFIG_SYSTEM_FREE=y -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/olimexino-stm32/smallnsh/defconfig b/configs/olimexino-stm32/smallnsh/defconfig index 6a870a7f6e982bb3c62ffa837a5c9f4d200f917b..a8ff93b3ffd3b84d589be345965fd21443c35b97 100644 --- a/configs/olimexino-stm32/smallnsh/defconfig +++ b/configs/olimexino-stm32/smallnsh/defconfig @@ -1166,7 +1166,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/olimexino-stm32/src/stm32_appinit.c b/configs/olimexino-stm32/src/stm32_appinit.c index e9cd7fe0b4d71a64adcfc4e68169476d0df8207f..c0e50597f7ffceac60145edd0b99b9f02610c910 100644 --- a/configs/olimexino-stm32/src/stm32_appinit.c +++ b/configs/olimexino-stm32/src/stm32_appinit.c @@ -49,8 +49,8 @@ #include #include -#ifdef CONFIG_SYSTEM_USBMONITOR -# include +#ifdef CONFIG_USBMONITOR +# include #endif #ifdef CONFIG_USBDEV diff --git a/configs/olimexino-stm32/tiny/defconfig b/configs/olimexino-stm32/tiny/defconfig index 0e5679272c88b72cd20cc7d0574e2bd7c0926d60..9bf4ddeff9aaf1f891ff782471b0ec788853dd7d 100644 --- a/configs/olimexino-stm32/tiny/defconfig +++ b/configs/olimexino-stm32/tiny/defconfig @@ -1074,7 +1074,7 @@ CONFIG_EXAMPLES_CAN_READWRITE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/open1788/knsh/defconfig b/configs/open1788/knsh/defconfig index aa2c88fd4a933d6e5d6c631134f53974e9ecd74d..73ef473d5467b350bf660d91e3b0227b2aad2d82 100644 --- a/configs/open1788/knsh/defconfig +++ b/configs/open1788/knsh/defconfig @@ -903,7 +903,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/open1788/nsh/defconfig b/configs/open1788/nsh/defconfig index 53981b180c8909d9ae55844047c77cb924585241..c7da461f8b2acea300535f24f403515b946fad48 100644 --- a/configs/open1788/nsh/defconfig +++ b/configs/open1788/nsh/defconfig @@ -913,7 +913,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/open1788/nxlines/defconfig b/configs/open1788/nxlines/defconfig index 38f0eb053d316590665fea4a3fcb239689c034ff..3ba4b262f95f3d379d920d4c0c38719b27ba11ad 100644 --- a/configs/open1788/nxlines/defconfig +++ b/configs/open1788/nxlines/defconfig @@ -941,7 +941,7 @@ CONFIG_EXAMPLES_NXLINES_BPP=32 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/pcblogic-pic32mx/nsh/defconfig b/configs/pcblogic-pic32mx/nsh/defconfig index 0d6bffa7a9c54f03c1d692d1873aa0b05f1306d4..d5cb127e3f5f7754ebaea3419e49d84c9f08e717 100644 --- a/configs/pcblogic-pic32mx/nsh/defconfig +++ b/configs/pcblogic-pic32mx/nsh/defconfig @@ -319,16 +319,18 @@ CONFIG_RAM_SIZE=32768 CONFIG_ARCH_BOARD_PCBLOGICPIC32MX=y # CONFIG_ARCH_BOARD_UBW32 is not set # CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD_CUSTOM_DIR="configs/dummy" +CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y CONFIG_ARCH_BOARD="pcblogic-pic32mx" # # Common Board Options # -CONFIG_NSH_MMCSDMINOR=0 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set # CONFIG_LIB_BOARDCTL is not set # @@ -467,7 +469,12 @@ CONFIG_DEV_NULL=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -846,6 +853,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 # # Configure Command Options @@ -886,7 +894,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/pcduino-a10/nsh/defconfig b/configs/pcduino-a10/nsh/defconfig index 3fbc6318cf001dd97007ae78ba645ebdf6221e1b..8de6365d1a06a01373a5dde47766db3bc0b47946 100644 --- a/configs/pcduino-a10/nsh/defconfig +++ b/configs/pcduino-a10/nsh/defconfig @@ -896,7 +896,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/pic32mx-starterkit/nsh/defconfig b/configs/pic32mx-starterkit/nsh/defconfig index 1586dd3bd39a770f91d49e37e405b14883a5bae2..4e62e0aaa9c051a64cffcc21bbc767f3a49330f4 100644 --- a/configs/pic32mx-starterkit/nsh/defconfig +++ b/configs/pic32mx-starterkit/nsh/defconfig @@ -319,6 +319,8 @@ CONFIG_RAM_SIZE=131072 CONFIG_ARCH_BOARD_PIC32MX_STARTERKIT=y # CONFIG_ARCH_BOARD_PIC32MX7MMB is not set # CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD_CUSTOM_DIR="configs/dummy" +CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y CONFIG_ARCH_BOARD="pic32mx-starterkit" # @@ -326,12 +328,11 @@ CONFIG_ARCH_BOARD="pic32mx-starterkit" # CONFIG_ARCH_HAVE_LEDS=y CONFIG_ARCH_LEDS=y -CONFIG_NSH_MMCSDMINOR=0 -CONFIG_NSH_MMCSDSLOTNO=0 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set @@ -476,7 +477,12 @@ CONFIG_DEV_NULL=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -909,6 +915,8 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 # # Configure Command Options @@ -950,7 +958,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FLASH_ERASEALL is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/pic32mx-starterkit/nsh2/defconfig b/configs/pic32mx-starterkit/nsh2/defconfig index d10280cc5c0f6878610a21fca039ff5648fd1cea..e348af2a4c50b5df5517017cc0957112644e0aae 100644 --- a/configs/pic32mx-starterkit/nsh2/defconfig +++ b/configs/pic32mx-starterkit/nsh2/defconfig @@ -329,6 +329,8 @@ CONFIG_RAM_SIZE=131072 CONFIG_ARCH_BOARD_PIC32MX_STARTERKIT=y # CONFIG_ARCH_BOARD_PIC32MX7MMB is not set # CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD_CUSTOM_DIR="configs/dummy" +CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y CONFIG_ARCH_BOARD="pic32mx-starterkit" # @@ -336,12 +338,11 @@ CONFIG_ARCH_BOARD="pic32mx-starterkit" # CONFIG_ARCH_HAVE_LEDS=y CONFIG_ARCH_LEDS=y -CONFIG_NSH_MMCSDMINOR=0 -CONFIG_NSH_MMCSDSLOTNO=0 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set @@ -486,7 +487,12 @@ CONFIG_DEV_NULL=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -1092,6 +1098,8 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 # # Configure Command Options @@ -1164,7 +1172,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FLASH_ERASEALL is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/pic32mx7mmb/nsh/defconfig b/configs/pic32mx7mmb/nsh/defconfig index 6812086deaa7ee647dfc04bf18b39f1c4404bba2..bd048635e39f498ff7d33ac0eab41aed14c32c7e 100644 --- a/configs/pic32mx7mmb/nsh/defconfig +++ b/configs/pic32mx7mmb/nsh/defconfig @@ -337,6 +337,8 @@ CONFIG_RAM_SIZE=131072 # CONFIG_ARCH_BOARD_PIC32MX_STARTERKIT is not set CONFIG_ARCH_BOARD_PIC32MX7MMB=y # CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD_CUSTOM_DIR="configs/dummy" +CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y CONFIG_ARCH_BOARD="pic32mx7mmb" # @@ -344,13 +346,11 @@ CONFIG_ARCH_BOARD="pic32mx7mmb" # CONFIG_ARCH_HAVE_LEDS=y CONFIG_ARCH_LEDS=y -CONFIG_NSH_MMCSDMINOR=0 -CONFIG_NSH_MMCSDSLOTNO=0 -CONFIG_NSH_MMCSDSPIPORTNO=1 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y @@ -505,7 +505,12 @@ CONFIG_SPI=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -1155,6 +1160,9 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 +CONFIG_NSH_MMCSDSPIPORTNO=1 # # Configure Command Options @@ -1227,7 +1235,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FLASH_ERASEALL is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/pic32mz-starterkit/nsh/defconfig b/configs/pic32mz-starterkit/nsh/defconfig index 4c31a821ae9e53ad64d06facea4cafb952be6c53..2e34b71f23427082e3ab58d5568940f12e277568 100644 --- a/configs/pic32mz-starterkit/nsh/defconfig +++ b/configs/pic32mz-starterkit/nsh/defconfig @@ -244,6 +244,8 @@ CONFIG_RAM_SIZE=131072 # CONFIG_ARCH_BOARD_PIC32MZ_STARTERKIT=y # CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD_CUSTOM_DIR="configs/dummy" +CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y CONFIG_ARCH_BOARD="pic32mz-starterkit" # @@ -253,12 +255,11 @@ CONFIG_ARCH_HAVE_LEDS=y CONFIG_ARCH_LEDS=y CONFIG_ARCH_HAVE_BUTTONS=y # CONFIG_ARCH_BUTTONS is not set -CONFIG_NSH_MMCSDMINOR=0 -CONFIG_NSH_MMCSDSLOTNO=0 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set @@ -403,7 +404,12 @@ CONFIG_DEV_NULL=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -836,6 +842,8 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 # # Configure Command Options @@ -877,7 +885,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FLASH_ERASEALL is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/pirelli_dpl10/nsh_highram/defconfig b/configs/pirelli_dpl10/nsh_highram/defconfig index a0008f818be9fe538e1b41784f988060454f85dc..0928bf0425ee4296c300c0fcfa1f9628a8942821 100644 --- a/configs/pirelli_dpl10/nsh_highram/defconfig +++ b/configs/pirelli_dpl10/nsh_highram/defconfig @@ -798,7 +798,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sabre-6quad/nsh/defconfig b/configs/sabre-6quad/nsh/defconfig index fe2e625a2ddefdd04d8e8dddd292c71a3fcc666f..1ab7f2c4c5475fe4f45c86bb40ae9907c0534432 100644 --- a/configs/sabre-6quad/nsh/defconfig +++ b/configs/sabre-6quad/nsh/defconfig @@ -869,7 +869,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sabre-6quad/smp/defconfig b/configs/sabre-6quad/smp/defconfig index 6028bfb91cae0cb77ebc9269ddd88e8a86ed49f6..5ca09504dcaa70f18e5039c3cf5300e73b1c11dc 100644 --- a/configs/sabre-6quad/smp/defconfig +++ b/configs/sabre-6quad/smp/defconfig @@ -877,7 +877,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sabre-6quad/src/imx_appinit.c b/configs/sabre-6quad/src/imx_appinit.c index 7b7f66ead6139342aa6ecd9adb61b37d2dbc8f6b..2e32a6771f3d0830069bd80ed11873eb0efd892a 100644 --- a/configs/sabre-6quad/src/imx_appinit.c +++ b/configs/sabre-6quad/src/imx_appinit.c @@ -45,7 +45,7 @@ #include "sabre-6quad.h" -#if defined(CONFIG_LIB_BOARDCTL) && !defined(CONFIG_BUILD_KERNEL) +#ifdef CONFIG_LIB_BOARDCTL /**************************************************************************** * Public Functions @@ -87,4 +87,4 @@ int board_app_initialize(uintptr_t arg) #endif } -#endif /* CONFIG_LIB_BOARDCTL && !CONFIG_BUILD_KERNEL */ +#endif /* CONFIG_LIB_BOARDCTL */ diff --git a/configs/sam3u-ek/knsh/defconfig b/configs/sam3u-ek/knsh/defconfig index a14dcebcabafda8aed42c23adca34e79ff6fb9d4..fdd4d7852b6de7449b22a89ada5099953c5291b8 100644 --- a/configs/sam3u-ek/knsh/defconfig +++ b/configs/sam3u-ek/knsh/defconfig @@ -918,7 +918,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sam3u-ek/nsh/defconfig b/configs/sam3u-ek/nsh/defconfig index ceb2c36d2c62a0ca161fbfd674a1e2fe3f597985..e2a4ed5993ee630d5f4c79eacd9d154d3b742abd 100644 --- a/configs/sam3u-ek/nsh/defconfig +++ b/configs/sam3u-ek/nsh/defconfig @@ -913,7 +913,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sam3u-ek/nx/defconfig b/configs/sam3u-ek/nx/defconfig index 86a492c3752eb2a431f5e339c01d21ebb5e30805..499368e1533b86238e5f316844f122ab7968b649 100644 --- a/configs/sam3u-ek/nx/defconfig +++ b/configs/sam3u-ek/nx/defconfig @@ -914,7 +914,7 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sam3u-ek/nxwm/defconfig b/configs/sam3u-ek/nxwm/defconfig index 3966522e3e213e9281897d116ea19fddab727443..713b5e2f36e0a85007e29a85d0432fa19f411487 100644 --- a/configs/sam3u-ek/nxwm/defconfig +++ b/configs/sam3u-ek/nxwm/defconfig @@ -1253,7 +1253,7 @@ CONFIG_NXWM_HEXCALCULATOR_FONTID=5 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sam4e-ek/README.txt b/configs/sam4e-ek/README.txt index 6de1817b0155403bd22b67ca412cb02fa5711d73..5f04cb5db410b170920da99c42fce28f7635b420 100644 --- a/configs/sam4e-ek/README.txt +++ b/configs/sam4e-ek/README.txt @@ -837,15 +837,15 @@ USB Full-Speed Device CONFIG_NSH_ARCHINIT=y : Automatically start the USB monitor Application Configuration -> System NSH Add-Ons: - CONFIG_SYSTEM_USBMONITOR=y : Enable the USB monitor daemon - CONFIG_SYSTEM_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size - CONFIG_SYSTEM_USBMONITOR_PRIORITY=50 : USB monitor daemon priority - CONFIG_SYSTEM_USBMONITOR_INTERVAL=1 : Dump trace data every second - CONFIG_SYSTEM_USBMONITOR_TRACEINIT=y : Enable TRACE output - CONFIG_SYSTEM_USBMONITOR_TRACECLASS=y - CONFIG_SYSTEM_USBMONITOR_TRACETRANSFERS=y - CONFIG_SYSTEM_USBMONITOR_TRACECONTROLLER=y - CONFIG_SYSTEM_USBMONITOR_TRACEINTERRUPTS=y + CONFIG_USBMONITOR=y : Enable the USB monitor daemon + CONFIG_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size + CONFIG_USBMONITOR_PRIORITY=50 : USB monitor daemon priority + CONFIG_USBMONITOR_INTERVAL=1 : Dump trace data every second + CONFIG_USBMONITOR_TRACEINIT=y : Enable TRACE output + CONFIG_USBMONITOR_TRACECLASS=y + CONFIG_USBMONITOR_TRACETRANSFERS=y + CONFIG_USBMONITOR_TRACECONTROLLER=y + CONFIG_USBMONITOR_TRACEINTERRUPTS=y NOTE: If USB debug output is also enabled, both outputs will appear on the serial console. However, the debug output will be asynchronous with the diff --git a/configs/sam4e-ek/nsh/defconfig b/configs/sam4e-ek/nsh/defconfig index 8664c7d7a007b7136c0a780786044338c87d2574..1104c510bfa7cb264c7c2566d1532d1da74739a1 100644 --- a/configs/sam4e-ek/nsh/defconfig +++ b/configs/sam4e-ek/nsh/defconfig @@ -1235,7 +1235,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FLASH_ERASEALL is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/sam4e-ek/nxwm/defconfig b/configs/sam4e-ek/nxwm/defconfig index 5948ce08b8dd1a16abae7028f311748f8b255c21..378d28ba1126809a67fa6d69bac7c4f735dd1cad 100644 --- a/configs/sam4e-ek/nxwm/defconfig +++ b/configs/sam4e-ek/nxwm/defconfig @@ -1588,7 +1588,7 @@ CONFIG_NXWM_HEXCALCULATOR_FONTID=5 # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FLASH_ERASEALL is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/sam4e-ek/src/sam4e-ek.h b/configs/sam4e-ek/src/sam4e-ek.h index 1b11b47c6f16ec05e91eb279d3c37cb4c3c4d983..591b90be1f6b4b7d4e8cf11637dcad34466c6935 100644 --- a/configs/sam4e-ek/src/sam4e-ek.h +++ b/configs/sam4e-ek/src/sam4e-ek.h @@ -130,7 +130,7 @@ # undef CONFIG_USBDEV_TRACE #endif -#if !defined(CONFIG_SYSTEM_USBMONITOR) || !defined(CONFIG_USBDEV_TRACE) +#if !defined(CONFIG_USBMONITOR) || !defined(CONFIG_USBDEV_TRACE) # undef HAVE_USBMONITOR #endif diff --git a/configs/sam4e-ek/src/sam_appinit.c b/configs/sam4e-ek/src/sam_appinit.c index 6eef61218745eab83baac8ab72a90dd387aa095b..aed2a31361d0b87414deccc3f7a675e4c83cc249 100644 --- a/configs/sam4e-ek/src/sam_appinit.c +++ b/configs/sam4e-ek/src/sam_appinit.c @@ -48,8 +48,8 @@ #include -#ifdef CONFIG_SYSTEM_USBMONITOR -# include +#ifdef CONFIG_USBMONITOR +# include #endif #include "sam4e-ek.h" @@ -118,7 +118,7 @@ int board_app_initialize(uintptr_t arg) #ifdef HAVE_USBMONITOR /* Start the USB Monitor */ - ret = usbmonitor_start(0, NULL); + ret = usbmonitor_start(); if (ret != OK) { syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); diff --git a/configs/sam4e-ek/usbnsh/defconfig b/configs/sam4e-ek/usbnsh/defconfig index 0ea1481ce880eeb8c11875e04609ead0181c4b58..a422f34571e2822187852fbf54b0ba168d68cf20 100644 --- a/configs/sam4e-ek/usbnsh/defconfig +++ b/configs/sam4e-ek/usbnsh/defconfig @@ -1275,7 +1275,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FLASH_ERASEALL is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/sam4l-xplained/nsh/defconfig b/configs/sam4l-xplained/nsh/defconfig index c848386d6b3f1040f0b7ba55b943638d371a73dd..34dd699cd7e0fb3eacf374a8ee74bce2f02bc9a9 100644 --- a/configs/sam4l-xplained/nsh/defconfig +++ b/configs/sam4l-xplained/nsh/defconfig @@ -922,7 +922,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sam4s-xplained-pro/nsh/defconfig b/configs/sam4s-xplained-pro/nsh/defconfig index eae881f10a4c4c88eac7f072a7643b48d2a0e930..9e87745c51bf6c79ee12faa780cd71ae829ab1d3 100644 --- a/configs/sam4s-xplained-pro/nsh/defconfig +++ b/configs/sam4s-xplained-pro/nsh/defconfig @@ -1082,7 +1082,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sam4s-xplained-pro/src/sam4s-xplained-pro.h b/configs/sam4s-xplained-pro/src/sam4s-xplained-pro.h index 791be9c596bf63acadd6474999530ea045e7dfbb..081e8f73f290891937430bcea773d22a83c1bc11 100644 --- a/configs/sam4s-xplained-pro/src/sam4s-xplained-pro.h +++ b/configs/sam4s-xplained-pro/src/sam4s-xplained-pro.h @@ -106,7 +106,7 @@ # undef CONFIG_USBDEV_TRACE #endif -#if !defined(CONFIG_SYSTEM_USBMONITOR) && !defined(CONFIG_USBDEV_TRACE) +#if !defined(CONFIG_USBMONITOR) && !defined(CONFIG_USBDEV_TRACE) # undef HAVE_USBMONITOR #endif diff --git a/configs/sam4s-xplained-pro/src/sam_appinit.c b/configs/sam4s-xplained-pro/src/sam_appinit.c index 7e0d3c3d086dcae81fa9e221052812f02ad192b3..7ac7f1587c4f1f9e4aac24703204e1e11be85ba8 100644 --- a/configs/sam4s-xplained-pro/src/sam_appinit.c +++ b/configs/sam4s-xplained-pro/src/sam_appinit.c @@ -63,8 +63,8 @@ # include #endif -#ifdef CONFIG_SYSTEM_USBMONITOR -# include +#ifdef CONFIG_USBMONITOR +# include #endif #include "sam4s-xplained-pro.h" @@ -169,7 +169,7 @@ int board_app_initialize(uintptr_t arg) /* Start the USB Monitor */ syslog(LOG_INFO, "Starting USB Monitor\n"); - ret = usbmonitor_start(0, NULL); + ret = usbmonitor_start(); if (ret != OK) { syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d (%d)\n", ret, errno); diff --git a/configs/sam4s-xplained/nsh/defconfig b/configs/sam4s-xplained/nsh/defconfig index 10afa826f1d9f3cb1a51c9efa7d0e896fc1eb665..6d4512f72c3500a72c1daaadcaec31b363b8fd24 100644 --- a/configs/sam4s-xplained/nsh/defconfig +++ b/configs/sam4s-xplained/nsh/defconfig @@ -895,7 +895,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sama5d2-xult/nsh/defconfig b/configs/sama5d2-xult/nsh/defconfig index bbedda86974be5c0f8e2ad14160206ae310dd631..86220f7ed3ab84ce28c0f30dde738fde4e752d3a 100644 --- a/configs/sama5d2-xult/nsh/defconfig +++ b/configs/sama5d2-xult/nsh/defconfig @@ -1076,7 +1076,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set CONFIG_SYSTEM_NXPLAYER=y diff --git a/configs/sama5d3-xplained/README.txt b/configs/sama5d3-xplained/README.txt index 336008da1eb077f299f45a9265ebe3f2d54b2b0f..89610babeda1c331f7c91e6957cfc491b3702ebf 100644 --- a/configs/sama5d3-xplained/README.txt +++ b/configs/sama5d3-xplained/README.txt @@ -1374,15 +1374,15 @@ USB High-Speed Device CONFIG_NSH_ARCHINIT=y : Automatically start the USB monitor Application Configuration -> System NSH Add-Ons: - CONFIG_SYSTEM_USBMONITOR=y : Enable the USB monitor daemon - CONFIG_SYSTEM_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size - CONFIG_SYSTEM_USBMONITOR_PRIORITY=50 : USB monitor daemon priority - CONFIG_SYSTEM_USBMONITOR_INTERVAL=1 : Dump trace data every second - CONFIG_SYSTEM_USBMONITOR_TRACEINIT=y : Enable TRACE output - CONFIG_SYSTEM_USBMONITOR_TRACECLASS=y - CONFIG_SYSTEM_USBMONITOR_TRACETRANSFERS=y - CONFIG_SYSTEM_USBMONITOR_TRACECONTROLLER=y - CONFIG_SYSTEM_USBMONITOR_TRACEINTERRUPTS=y + CONFIG_USBMONITOR=y : Enable the USB monitor daemon + CONFIG_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size + CONFIG_USBMONITOR_PRIORITY=50 : USB monitor daemon priority + CONFIG_USBMONITOR_INTERVAL=1 : Dump trace data every second + CONFIG_USBMONITOR_TRACEINIT=y : Enable TRACE output + CONFIG_USBMONITOR_TRACECLASS=y + CONFIG_USBMONITOR_TRACETRANSFERS=y + CONFIG_USBMONITOR_TRACECONTROLLER=y + CONFIG_USBMONITOR_TRACEINTERRUPTS=y NOTE: If USB debug output is also enabled, both outputs will appear on the serial console. However, the debug output will be asynchronous with the @@ -1568,10 +1568,10 @@ file1: CONFIG_USBHOST_ISOC_DISABLE=y CONFIG_NSH_ARCHINIT=y : Automatically start the USB monitor Application Configuration -> System NSH Add-Ons: - CONFIG_SYSTEM_USBMONITOR=y : Enable the USB monitor daemon - CONFIG_SYSTEM_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size - CONFIG_SYSTEM_USBMONITOR_PRIORITY=50 : USB monitor daemon priority - CONFIG_SYSTEM_USBMONITOR_INTERVAL=1 : Dump trace data every second + CONFIG_USBMONITOR=y : Enable the USB monitor daemon + CONFIG_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size + CONFIG_USBMONITOR_PRIORITY=50 : USB monitor daemon priority + CONFIG_USBMONITOR_INTERVAL=1 : Dump trace data every second NOTE: If USB debug output is also enabled, both outpus will appear on the serial console. However, the debug output will be asynchronous with the diff --git a/configs/sama5d3-xplained/bridge/defconfig b/configs/sama5d3-xplained/bridge/defconfig index a32be2985d23494165e845eb953c83f6fd6d420f..f1fb1d55783eab832c41d9250a0b27b57ed23a30 100644 --- a/configs/sama5d3-xplained/bridge/defconfig +++ b/configs/sama5d3-xplained/bridge/defconfig @@ -1077,7 +1077,7 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set CONFIG_SYSTEM_RAMTEST=y diff --git a/configs/sama5d3-xplained/nsh/defconfig b/configs/sama5d3-xplained/nsh/defconfig index 7733b5bd3959a015e96457b5a79f65c7e3249062..8a42f500de326bdc4af1b3ca2b178ff93ce0a91e 100644 --- a/configs/sama5d3-xplained/nsh/defconfig +++ b/configs/sama5d3-xplained/nsh/defconfig @@ -949,7 +949,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sama5d3-xplained/src/sam_ajoystick.c b/configs/sama5d3-xplained/src/sam_ajoystick.c index 15b53d3f70d7f9002759a568d18fe007bf8de8cc..7ff2f021957bf51feba1781afbab3580b17aa623 100644 --- a/configs/sama5d3-xplained/src/sam_ajoystick.c +++ b/configs/sama5d3-xplained/src/sam_ajoystick.c @@ -187,7 +187,8 @@ static int ajoy_sample(FAR const struct ajoy_lowerhalf_s *lower, * channels are enabled). */ - nread = file_read(&g_adcfile, adcmsg, MAX_ADC_CHANNELS * sizeof(struct adc_msg_s)); + nread = file_read(&g_adcfile, adcmsg, + MAX_ADC_CHANNELS * sizeof(struct adc_msg_s)); if (nread < 0) { int errcode = get_errno(); diff --git a/configs/sama5d3-xplained/src/sam_appinit.c b/configs/sama5d3-xplained/src/sam_appinit.c index cfee95be1f8bcd91decaffefe7ec7b47d3816fd2..34073c9f17707ef91493f0eb10e1750eb749a9a5 100644 --- a/configs/sama5d3-xplained/src/sam_appinit.c +++ b/configs/sama5d3-xplained/src/sam_appinit.c @@ -48,8 +48,8 @@ #include -#ifdef CONFIG_SYSTEM_USBMONITOR -# include +#ifdef CONFIG_USBMONITOR +# include #endif #include "sama5d3-xplained.h" @@ -155,7 +155,7 @@ int board_app_initialize(uintptr_t arg) #ifdef HAVE_USBMONITOR /* Start the USB Monitor */ - ret = usbmonitor_start(0, NULL); + ret = usbmonitor_start(); if (ret != OK) { syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); diff --git a/configs/sama5d3-xplained/src/sama5d3-xplained.h b/configs/sama5d3-xplained/src/sama5d3-xplained.h index 9b4c56b93da01debb31165ce79e20b06b0ebad92..66e1231a4c03c39f1aaf5dcdf68a8d495a6fadf7 100644 --- a/configs/sama5d3-xplained/src/sama5d3-xplained.h +++ b/configs/sama5d3-xplained/src/sama5d3-xplained.h @@ -237,7 +237,7 @@ /* Check if we should enable the USB monitor before starting NSH */ -#ifndef CONFIG_SYSTEM_USBMONITOR +#ifndef CONFIG_USBMONITOR # undef HAVE_USBMONITOR #endif diff --git a/configs/sama5d3x-ek/README.txt b/configs/sama5d3x-ek/README.txt index f6601d26533d96c821ef206e46717b3f1a705957..73d3ef0b94d103517dd819048c69d8ac7b0ca7c6 100644 --- a/configs/sama5d3x-ek/README.txt +++ b/configs/sama5d3x-ek/README.txt @@ -1552,15 +1552,15 @@ USB High-Speed Device CONFIG_NSH_ARCHINIT=y : Automatically start the USB monitor Application Configuration -> System NSH Add-Ons: - CONFIG_SYSTEM_USBMONITOR=y : Enable the USB monitor daemon - CONFIG_SYSTEM_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size - CONFIG_SYSTEM_USBMONITOR_PRIORITY=50 : USB monitor daemon priority - CONFIG_SYSTEM_USBMONITOR_INTERVAL=1 : Dump trace data every second - CONFIG_SYSTEM_USBMONITOR_TRACEINIT=y : Enable TRACE output - CONFIG_SYSTEM_USBMONITOR_TRACECLASS=y - CONFIG_SYSTEM_USBMONITOR_TRACETRANSFERS=y - CONFIG_SYSTEM_USBMONITOR_TRACECONTROLLER=y - CONFIG_SYSTEM_USBMONITOR_TRACEINTERRUPTS=y + CONFIG_USBMONITOR=y : Enable the USB monitor daemon + CONFIG_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size + CONFIG_USBMONITOR_PRIORITY=50 : USB monitor daemon priority + CONFIG_USBMONITOR_INTERVAL=1 : Dump trace data every second + CONFIG_USBMONITOR_TRACEINIT=y : Enable TRACE output + CONFIG_USBMONITOR_TRACECLASS=y + CONFIG_USBMONITOR_TRACETRANSFERS=y + CONFIG_USBMONITOR_TRACECONTROLLER=y + CONFIG_USBMONITOR_TRACEINTERRUPTS=y NOTE: If USB debug output is also enabled, both outputs will appear on the serial console. However, the debug output will be asynchronous with the @@ -1736,10 +1736,10 @@ USB High-Speed Host CONFIG_NSH_ARCHINIT=y : Automatically start the USB monitor Application Configuration -> System NSH Add-Ons: - CONFIG_SYSTEM_USBMONITOR=y : Enable the USB monitor daemon - CONFIG_SYSTEM_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size - CONFIG_SYSTEM_USBMONITOR_PRIORITY=50 : USB monitor daemon priority - CONFIG_SYSTEM_USBMONITOR_INTERVAL=1 : Dump trace data every second + CONFIG_USBMONITOR=y : Enable the USB monitor daemon + CONFIG_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size + CONFIG_USBMONITOR_PRIORITY=50 : USB monitor daemon priority + CONFIG_USBMONITOR_INTERVAL=1 : Dump trace data every second NOTE: If USB debug output is also enabled, both outpus will appear on the serial console. However, the debug output will be asynchronous with the diff --git a/configs/sama5d3x-ek/demo/defconfig b/configs/sama5d3x-ek/demo/defconfig index 318b920ec84b13228329d4238f9c650a042b3f09..c142bb83eb71e463ef0ba90a17be43ac7e3bec18 100644 --- a/configs/sama5d3x-ek/demo/defconfig +++ b/configs/sama5d3x-ek/demo/defconfig @@ -1149,7 +1149,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FLASH_ERASEALL is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sama5d3x-ek/hello/defconfig b/configs/sama5d3x-ek/hello/defconfig index 711ff3aab8c262001a89e4b5edd909a415ffe659..bd18ec13931b01e743213b76d78e00d1f36c8bc4 100644 --- a/configs/sama5d3x-ek/hello/defconfig +++ b/configs/sama5d3x-ek/hello/defconfig @@ -809,7 +809,7 @@ CONFIG_EXAMPLES_HELLO_STACKSIZE=2048 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sama5d3x-ek/norboot/defconfig b/configs/sama5d3x-ek/norboot/defconfig index f09730318886d3da079cb1d43a846cd0c587f4d8..0eae073a7b3d117d25f57aa9a4d9da9671cb7208 100644 --- a/configs/sama5d3x-ek/norboot/defconfig +++ b/configs/sama5d3x-ek/norboot/defconfig @@ -823,7 +823,7 @@ CONFIG_EXAMPLES_HELLO_STACKSIZE=2048 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sama5d3x-ek/nsh/defconfig b/configs/sama5d3x-ek/nsh/defconfig index a83632746f33a319a85e998c72b512750d2da506..28ddf8a8202ad83aed417f2b1960d2ef8c75ee82 100644 --- a/configs/sama5d3x-ek/nsh/defconfig +++ b/configs/sama5d3x-ek/nsh/defconfig @@ -962,7 +962,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sama5d3x-ek/nx/defconfig b/configs/sama5d3x-ek/nx/defconfig index a9110cb25781cb0763ec36e5d4bbd055b67f449f..204384004ccfb8af0242fb58962efe3cdfd2cfd6 100644 --- a/configs/sama5d3x-ek/nx/defconfig +++ b/configs/sama5d3x-ek/nx/defconfig @@ -982,7 +982,7 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sama5d3x-ek/nxplayer/defconfig b/configs/sama5d3x-ek/nxplayer/defconfig index 222d4832fe55a21c54a80c32e8b189784c62ca71..421064ada2986f9400f7161bfe751b875bdd17a4 100644 --- a/configs/sama5d3x-ek/nxplayer/defconfig +++ b/configs/sama5d3x-ek/nxplayer/defconfig @@ -1095,7 +1095,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_I2CTOOL is not set # CONFIG_SYSTEM_INSTALL is not set diff --git a/configs/sama5d3x-ek/nxwm/defconfig b/configs/sama5d3x-ek/nxwm/defconfig index d9ca7a557674ef63f4dd2e59c854a4b23d5f23ac..aa75930aca3bd3c2df714f89b2320e61ce73cda3 100644 --- a/configs/sama5d3x-ek/nxwm/defconfig +++ b/configs/sama5d3x-ek/nxwm/defconfig @@ -1341,7 +1341,7 @@ CONFIG_NXWM_HEXCALCULATOR_FONTID=6 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sama5d3x-ek/ov2640/defconfig b/configs/sama5d3x-ek/ov2640/defconfig index 62fc4177eb0df4f7c6d5ed626614402f7fe56fe7..e117995124f6456b065ed9aba890a9d6cd98911e 100644 --- a/configs/sama5d3x-ek/ov2640/defconfig +++ b/configs/sama5d3x-ek/ov2640/defconfig @@ -892,7 +892,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_I2CTOOL is not set # CONFIG_SYSTEM_INSTALL is not set diff --git a/configs/sama5d3x-ek/src/sam_appinit.c b/configs/sama5d3x-ek/src/sam_appinit.c index 9f4fff0f73da9d3196ce5ea91f5f02b22b74e76d..b3fb39f67605b33fd3b042b63c7a2b5257e78f29 100644 --- a/configs/sama5d3x-ek/src/sam_appinit.c +++ b/configs/sama5d3x-ek/src/sam_appinit.c @@ -48,8 +48,8 @@ #include -#ifdef CONFIG_SYSTEM_USBMONITOR -# include +#ifdef CONFIG_USBMONITOR +# include #endif #include "sama5d3x-ek.h" @@ -170,7 +170,7 @@ int board_app_initialize(uintptr_t arg) #ifdef HAVE_USBMONITOR /* Start the USB Monitor */ - ret = usbmonitor_start(0, NULL); + ret = usbmonitor_start(); if (ret != OK) { syslog(LOG_ERR, "ERROR: Start USB monitor: %d\n", ret); diff --git a/configs/sama5d3x-ek/src/sama5d3x-ek.h b/configs/sama5d3x-ek/src/sama5d3x-ek.h index 403412a71c9d28c8d62737758503e3a1d01106ff..6521211395740220040ee7ef8bcc3b5289c1adb9 100644 --- a/configs/sama5d3x-ek/src/sama5d3x-ek.h +++ b/configs/sama5d3x-ek/src/sama5d3x-ek.h @@ -297,7 +297,7 @@ /* Check if we should enable the USB monitor before starting NSH */ -#ifndef CONFIG_SYSTEM_USBMONITOR +#ifndef CONFIG_USBMONITOR # undef HAVE_USBMONITOR #endif diff --git a/configs/sama5d4-ek/README.txt b/configs/sama5d4-ek/README.txt index ee5408b0d0f2e552ebfc355f1176d1c7fdceb240..eec9b595109ef1745d8427ab90a9b93f69b7ec29 100644 --- a/configs/sama5d4-ek/README.txt +++ b/configs/sama5d4-ek/README.txt @@ -1928,15 +1928,15 @@ USB High-Speed Device CONFIG_NSH_ARCHINIT=y : Automatically start the USB monitor Application Configuration -> System NSH Add-Ons: - CONFIG_SYSTEM_USBMONITOR=y : Enable the USB monitor daemon - CONFIG_SYSTEM_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size - CONFIG_SYSTEM_USBMONITOR_PRIORITY=50 : USB monitor daemon priority - CONFIG_SYSTEM_USBMONITOR_INTERVAL=1 : Dump trace data every second - CONFIG_SYSTEM_USBMONITOR_TRACEINIT=y : Enable TRACE output - CONFIG_SYSTEM_USBMONITOR_TRACECLASS=y - CONFIG_SYSTEM_USBMONITOR_TRACETRANSFERS=y - CONFIG_SYSTEM_USBMONITOR_TRACECONTROLLER=y - CONFIG_SYSTEM_USBMONITOR_TRACEINTERRUPTS=y + CONFIG_USBMONITOR=y : Enable the USB monitor daemon + CONFIG_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size + CONFIG_USBMONITOR_PRIORITY=50 : USB monitor daemon priority + CONFIG_USBMONITOR_INTERVAL=1 : Dump trace data every second + CONFIG_USBMONITOR_TRACEINIT=y : Enable TRACE output + CONFIG_USBMONITOR_TRACECLASS=y + CONFIG_USBMONITOR_TRACETRANSFERS=y + CONFIG_USBMONITOR_TRACECONTROLLER=y + CONFIG_USBMONITOR_TRACEINTERRUPTS=y NOTE: If USB debug output is also enabled, both outputs will appear on the serial console. However, the debug output will be asynchronous with the @@ -2120,10 +2120,10 @@ USB High-Speed Host CONFIG_NSH_ARCHINIT=y : Automatically start the USB monitor Application Configuration -> System NSH Add-Ons: - CONFIG_SYSTEM_USBMONITOR=y : Enable the USB monitor daemon - CONFIG_SYSTEM_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size - CONFIG_SYSTEM_USBMONITOR_PRIORITY=50 : USB monitor daemon priority - CONFIG_SYSTEM_USBMONITOR_INTERVAL=1 : Dump trace data every second + CONFIG_USBMONITOR=y : Enable the USB monitor daemon + CONFIG_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size + CONFIG_USBMONITOR_PRIORITY=50 : USB monitor daemon priority + CONFIG_USBMONITOR_INTERVAL=1 : Dump trace data every second NOTE: If USB debug output is also enabled, both outpus will appear on the serial console. However, the debug output will be asynchronous with the diff --git a/configs/sama5d4-ek/at25boot/defconfig b/configs/sama5d4-ek/at25boot/defconfig index 7fec0ba4aac11322fc54f6a6fb307f8c35ec1b48..542da7876ccab786022b8c5bb21e042f3050124f 100644 --- a/configs/sama5d4-ek/at25boot/defconfig +++ b/configs/sama5d4-ek/at25boot/defconfig @@ -927,8 +927,8 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -CONFIG_SYSTEM_HEX2BIN=y -# CONFIG_SYSTEM_HEX2BIN_DEBUG is not set +CONFIG_LIB_HEX2BIN=y +# CONFIG_LIB_HEX2BIN_DEBUG is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sama5d4-ek/bridge/defconfig b/configs/sama5d4-ek/bridge/defconfig index 76a5894a9d5724de49995bdd180d4acea0ef7f6c..dc6c38984f238e302a713b0520026f34c0338314 100644 --- a/configs/sama5d4-ek/bridge/defconfig +++ b/configs/sama5d4-ek/bridge/defconfig @@ -1110,7 +1110,7 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set CONFIG_SYSTEM_RAMTEST=y diff --git a/configs/sama5d4-ek/dramboot/defconfig b/configs/sama5d4-ek/dramboot/defconfig index 20692044399511de9cd4b82086fc3ad4a2b37ea1..973422845685017bd861edf9d93b0d38d287fc7d 100644 --- a/configs/sama5d4-ek/dramboot/defconfig +++ b/configs/sama5d4-ek/dramboot/defconfig @@ -878,8 +878,8 @@ CONFIG_BUILTIN_PROXY_STACKSIZE=1024 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -CONFIG_SYSTEM_HEX2BIN=y -# CONFIG_SYSTEM_HEX2BIN_DEBUG is not set +CONFIG_LIB_HEX2BIN=y +# CONFIG_LIB_HEX2BIN_DEBUG is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sama5d4-ek/elf/defconfig b/configs/sama5d4-ek/elf/defconfig index 7b2b355e2da0fc42eb360627ecea5d62c1200cfe..0fc618424689c52fbfefb0a4d70120e3304eff40 100644 --- a/configs/sama5d4-ek/elf/defconfig +++ b/configs/sama5d4-ek/elf/defconfig @@ -931,7 +931,7 @@ CONFIG_EXAMPLES_ELF_CXXINITIALIZE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_I2CTOOL is not set # CONFIG_SYSTEM_INSTALL is not set diff --git a/configs/sama5d4-ek/ipv6/defconfig b/configs/sama5d4-ek/ipv6/defconfig index a5400f4e90e9853fd85dfc3fb9b1b03c513a5504..d25afb5066760480a8ce0f6c57855ba865de5ca3 100644 --- a/configs/sama5d4-ek/ipv6/defconfig +++ b/configs/sama5d4-ek/ipv6/defconfig @@ -1594,7 +1594,7 @@ CONFIG_NSH_MAX_ROUNDTRIP=20 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set CONFIG_SYSTEM_I2CTOOL=y CONFIG_I2CTOOL_MINBUS=0 diff --git a/configs/sama5d4-ek/knsh/defconfig b/configs/sama5d4-ek/knsh/defconfig index d08f54cfd0e63df6923031f381510942e90e7abf..64f29e3e0592df6d9a7c6253355c0c9b2f088324 100644 --- a/configs/sama5d4-ek/knsh/defconfig +++ b/configs/sama5d4-ek/knsh/defconfig @@ -1074,7 +1074,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sama5d4-ek/nsh/defconfig b/configs/sama5d4-ek/nsh/defconfig index bf72a2a86b21a8926d6f7dc83ebdb0a10a58ea38..7758f5bd93925a675c12b5ed6f19eac2309933df 100644 --- a/configs/sama5d4-ek/nsh/defconfig +++ b/configs/sama5d4-ek/nsh/defconfig @@ -1595,7 +1595,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set CONFIG_SYSTEM_I2CTOOL=y CONFIG_I2CTOOL_MINBUS=0 diff --git a/configs/sama5d4-ek/nxwm/defconfig b/configs/sama5d4-ek/nxwm/defconfig index add09daf5fb7d9c39da6323bc4b1e125b185c27e..3bf40dbcadc3c26e9effdd95bffa94350dc3542f 100644 --- a/configs/sama5d4-ek/nxwm/defconfig +++ b/configs/sama5d4-ek/nxwm/defconfig @@ -1784,7 +1784,7 @@ CONFIG_NXWM_MEDIAPLAYER_MINVOLUMEHEIGHT=6 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set CONFIG_SYSTEM_I2CTOOL=y CONFIG_I2CTOOL_MINBUS=0 diff --git a/configs/sama5d4-ek/ramtest/defconfig b/configs/sama5d4-ek/ramtest/defconfig index 00c135747eefcb4063219d633702314cd46e956a..3c618b63650381fe28c19d3ffd1722c32b45884a 100644 --- a/configs/sama5d4-ek/ramtest/defconfig +++ b/configs/sama5d4-ek/ramtest/defconfig @@ -976,7 +976,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set CONFIG_SYSTEM_RAMTEST=y diff --git a/configs/sama5d4-ek/src/at25_main.c b/configs/sama5d4-ek/src/at25_main.c index 078ee1725d10f762a35ac4d9a5e0ba4dd874286c..699f613b10e364c0b966560f4d63b0c627a084ed 100644 --- a/configs/sama5d4-ek/src/at25_main.c +++ b/configs/sama5d4-ek/src/at25_main.c @@ -1,7 +1,7 @@ /**************************************************************************** * configs/sama5d4-ek/src/at25_main.c * - * Copyright (C) 2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -47,10 +47,10 @@ #include #include #include +#include #include #include -#include #include "sama5d4-ek.h" diff --git a/configs/sama5d4-ek/src/dram_main.c b/configs/sama5d4-ek/src/dram_main.c index a36b646646425620fcf3f285a979d428e514556e..e84a9ddcff5762926c0e6e0edba2c6cab1aa7180 100644 --- a/configs/sama5d4-ek/src/dram_main.c +++ b/configs/sama5d4-ek/src/dram_main.c @@ -41,9 +41,9 @@ #include #include +#include #include -#include #include "up_arch.h" #include "mmu.h" diff --git a/configs/sama5d4-ek/src/sam_bringup.c b/configs/sama5d4-ek/src/sam_bringup.c index bc32caa21057e9cd7b8de37a306585922bdd9ad5..831dc06da7525e535e27c6529fe823d2796a0861 100644 --- a/configs/sama5d4-ek/src/sam_bringup.c +++ b/configs/sama5d4-ek/src/sam_bringup.c @@ -46,8 +46,8 @@ #include #include -#ifdef CONFIG_SYSTEM_USBMONITOR -# include +#ifdef CONFIG_USBMONITOR +# include #endif #include @@ -286,7 +286,7 @@ int sam_bringup(void) #ifdef HAVE_USBMONITOR /* Start the USB Monitor */ - ret = usbmonitor_start(0, NULL); + ret = usbmonitor_start(); if (ret != OK) { _err("ERROR: Failed to start the USB monitor: %d\n", ret); diff --git a/configs/sama5d4-ek/src/sama5d4-ek.h b/configs/sama5d4-ek/src/sama5d4-ek.h index de3dac7cb9daa06cbd5397af01edca79132cb164..ed7ff6bd2b352e589e7f972a8d229aed5f176b10 100644 --- a/configs/sama5d4-ek/src/sama5d4-ek.h +++ b/configs/sama5d4-ek/src/sama5d4-ek.h @@ -352,7 +352,7 @@ /* Check if we should enable the USB monitor before starting NSH */ -#ifndef CONFIG_SYSTEM_USBMONITOR +#ifndef CONFIG_USBMONITOR # undef HAVE_USBMONITOR #endif diff --git a/configs/samd20-xplained/nsh/defconfig b/configs/samd20-xplained/nsh/defconfig index 5b77260e57e63b7e16314d94f5a6f37d861afdce..e6477997172d6442cff9c390cf8617d15aadf01f 100644 --- a/configs/samd20-xplained/nsh/defconfig +++ b/configs/samd20-xplained/nsh/defconfig @@ -897,7 +897,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/samd21-xplained/nsh/defconfig b/configs/samd21-xplained/nsh/defconfig index 4b5a9b44ce9540461e361e3d3361e98bce6fcb2c..c11eec68ebb5fb717d94961171ce87a141106877 100644 --- a/configs/samd21-xplained/nsh/defconfig +++ b/configs/samd21-xplained/nsh/defconfig @@ -895,7 +895,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/same70-xplained/netnsh/defconfig b/configs/same70-xplained/netnsh/defconfig index 0f03d530c1db9ebe94fc194b7d116976d024371a..a60a2a7aff6540894512bde2d69e0876bd534471 100644 --- a/configs/same70-xplained/netnsh/defconfig +++ b/configs/same70-xplained/netnsh/defconfig @@ -283,6 +283,7 @@ CONFIG_SAMV7_GPIOC_IRQ=y # TWIHS device driver options # CONFIG_SAMV7_TWIHS0_FREQUENCY=100000 +CONFIG_SAMV7_TWIHS0_GLITCH_FILTER=1 # # HSMCI device driver options @@ -387,12 +388,11 @@ CONFIG_ARCH_HAVE_BUTTONS=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_HAVE_IRQBUTTONS=y CONFIG_ARCH_IRQBUTTONS=y -CONFIG_NSH_MMCSDMINOR=0 -CONFIG_NSH_MMCSDSLOTNO=0 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set @@ -528,10 +528,11 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set # CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set # CONFIG_PWM is not set -# CONFIG_ARCH_HAVE_I2CRESET is not set +CONFIG_ARCH_HAVE_I2CRESET=y CONFIG_I2C=y # CONFIG_I2C_SLAVE is not set # CONFIG_I2C_POLLED is not set +# CONFIG_I2C_RESET is not set # CONFIG_I2C_TRACE is not set CONFIG_I2C_DRIVER=y CONFIG_SPI=y @@ -558,7 +559,12 @@ CONFIG_SPI_EXCHANGE=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -994,6 +1000,7 @@ CONFIG_NETDB_DNSSERVER_NOADDR=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -1213,6 +1220,8 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 # # Configure Command Options diff --git a/configs/same70-xplained/nsh/defconfig b/configs/same70-xplained/nsh/defconfig index cb89c826f118328f9ec8e0a304589ef12bca34e3..5e3c9e924bad6f898891d4617259a09e144ccca8 100644 --- a/configs/same70-xplained/nsh/defconfig +++ b/configs/same70-xplained/nsh/defconfig @@ -289,6 +289,7 @@ CONFIG_SAMV7_SDRAMSIZE=2097152 # TWIHS device driver options # CONFIG_SAMV7_TWIHS0_FREQUENCY=100000 +CONFIG_SAMV7_TWIHS0_GLITCH_FILTER=1 # # HSMCI device driver options @@ -372,12 +373,11 @@ CONFIG_ARCH_HAVE_BUTTONS=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_HAVE_IRQBUTTONS=y CONFIG_ARCH_IRQBUTTONS=y -CONFIG_NSH_MMCSDMINOR=0 -CONFIG_NSH_MMCSDSLOTNO=0 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set @@ -513,10 +513,11 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set # CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set # CONFIG_PWM is not set -# CONFIG_ARCH_HAVE_I2CRESET is not set +CONFIG_ARCH_HAVE_I2CRESET=y CONFIG_I2C=y # CONFIG_I2C_SLAVE is not set # CONFIG_I2C_POLLED is not set +# CONFIG_I2C_RESET is not set # CONFIG_I2C_TRACE is not set CONFIG_I2C_DRIVER=y CONFIG_SPI=y @@ -543,7 +544,12 @@ CONFIG_SPI_EXCHANGE=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -815,6 +821,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -1014,6 +1021,8 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 # # Configure Command Options diff --git a/configs/same70-xplained/src/sam_appinit.c b/configs/same70-xplained/src/sam_appinit.c index 5e8a871522aee5903b2d4af44cc27ce6345a2ec5..4dd89315b75dfd1f0bd980d33d7436bbd982af9c 100644 --- a/configs/same70-xplained/src/sam_appinit.c +++ b/configs/same70-xplained/src/sam_appinit.c @@ -45,7 +45,7 @@ #include "same70-xplained.h" -#if defined(CONFIG_LIB_BOARDCTL) && !defined(CONFIG_BUILD_KERNEL) +#ifdef CONFIG_LIB_BOARDCTL /**************************************************************************** * Public Functions @@ -87,4 +87,4 @@ int board_app_initialize(uintptr_t arg) #endif } -#endif /* CONFIG_LIB_BOARDCTL && !CONFIG_BUILD_KERNEL */ +#endif /* CONFIG_LIB_BOARDCTL */ diff --git a/configs/same70-xplained/src/sam_bringup.c b/configs/same70-xplained/src/sam_bringup.c index 759811328e625d8a9ed82c677732a345f41a28ed..3ac5d205858aa3c162a0da78c2f642be336395c9 100644 --- a/configs/same70-xplained/src/sam_bringup.c +++ b/configs/same70-xplained/src/sam_bringup.c @@ -46,8 +46,8 @@ #include #include -#ifdef CONFIG_SYSTEM_USBMONITOR -# include +#ifdef CONFIG_USBMONITOR +# include #endif #include @@ -311,7 +311,7 @@ int sam_bringup(void) #ifdef HAVE_USBMONITOR /* Start the USB Monitor */ - ret = usbmonitor_start(0, NULL); + ret = usbmonitor_start(); if (ret != OK) { _err("ERROR: Failed to start the USB monitor: %d\n", ret); diff --git a/configs/same70-xplained/src/same70-xplained.h b/configs/same70-xplained/src/same70-xplained.h index db003b48ce53c203123339faa7dfdfb48f67ce78..838e0668c111bace95d82d9595b466a7b20e89ce 100644 --- a/configs/same70-xplained/src/same70-xplained.h +++ b/configs/same70-xplained/src/same70-xplained.h @@ -157,7 +157,7 @@ # undef CONFIG_USBDEV_TRACE #endif -#if !defined(CONFIG_SYSTEM_USBMONITOR) || !defined(CONFIG_USBDEV_TRACE) +#if !defined(CONFIG_USBMONITOR) || !defined(CONFIG_USBDEV_TRACE) # undef HAVE_USBMONITOR #endif diff --git a/configs/saml21-xplained/nsh/defconfig b/configs/saml21-xplained/nsh/defconfig index 7d37c41d4e49c48f5a89172b606a0fa67ee20f76..6aa541a803511d7b650df72a65c7278ae255dba0 100644 --- a/configs/saml21-xplained/nsh/defconfig +++ b/configs/saml21-xplained/nsh/defconfig @@ -883,7 +883,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/samv71-xult/knsh/defconfig b/configs/samv71-xult/knsh/defconfig index 64d931ab93216519b737a11c6a465b8aeeabbdaa..1a95add801270ed14e684430247bb1f2aeba1195 100644 --- a/configs/samv71-xult/knsh/defconfig +++ b/configs/samv71-xult/knsh/defconfig @@ -296,6 +296,7 @@ CONFIG_SAMV7_SDRAMSIZE=2097152 # TWIHS device driver options # CONFIG_SAMV7_TWIHS0_FREQUENCY=100000 +CONFIG_SAMV7_TWIHS0_GLITCH_FILTER=1 # # HSMCI device driver options @@ -379,13 +380,12 @@ CONFIG_ARCH_HAVE_BUTTONS=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_HAVE_IRQBUTTONS=y CONFIG_ARCH_IRQBUTTONS=y -CONFIG_NSH_MMCSDMINOR=0 -CONFIG_NSH_MMCSDSLOTNO=0 # # Board-Specific Options # # CONFIG_SAMV71XULT_MXTXPLND is not set +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set @@ -522,10 +522,11 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set # CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set # CONFIG_PWM is not set -# CONFIG_ARCH_HAVE_I2CRESET is not set +CONFIG_ARCH_HAVE_I2CRESET=y CONFIG_I2C=y # CONFIG_I2C_SLAVE is not set # CONFIG_I2C_POLLED is not set +# CONFIG_I2C_RESET is not set # CONFIG_I2C_TRACE is not set CONFIG_I2C_DRIVER=y CONFIG_SPI=y @@ -552,7 +553,12 @@ CONFIG_SPI_EXCHANGE=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -826,6 +832,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_LIB_USRWORK is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -1005,6 +1012,8 @@ CONFIG_NSH_DISABLE_MKRD=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 # # Configure Command Options diff --git a/configs/samv71-xult/module/defconfig b/configs/samv71-xult/module/defconfig index dcd165c2aede59ff6abfdc74176e2e2792dfc827..77748a6517e89e76631fb164c48e0e0b56a667d1 100644 --- a/configs/samv71-xult/module/defconfig +++ b/configs/samv71-xult/module/defconfig @@ -353,12 +353,12 @@ CONFIG_ARCH_HAVE_BUTTONS=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_HAVE_IRQBUTTONS=y CONFIG_ARCH_IRQBUTTONS=y -CONFIG_NSH_MMCSDMINOR=0 # # Board-Specific Options # # CONFIG_SAMV71XULT_MXTXPLND is not set +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_OS_SYMTAB=y @@ -499,7 +499,7 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set # CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set # CONFIG_PWM is not set -# CONFIG_ARCH_HAVE_I2CRESET is not set +CONFIG_ARCH_HAVE_I2CRESET=y # CONFIG_I2C is not set # CONFIG_SPI is not set # CONFIG_I2S is not set @@ -515,7 +515,12 @@ CONFIG_DEV_NULL=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -736,6 +741,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -931,6 +937,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 # # Configure Command Options diff --git a/configs/samv71-xult/mxtxplnd/defconfig b/configs/samv71-xult/mxtxplnd/defconfig index 24970c51a2ff5842f15032faaa801637e663d1da..a7e6d9f2bc4f127d3db0259a50854c2cd8812f31 100644 --- a/configs/samv71-xult/mxtxplnd/defconfig +++ b/configs/samv71-xult/mxtxplnd/defconfig @@ -284,6 +284,7 @@ CONFIG_SAMV7_GPIOD_IRQ=y # TWIHS device driver options # CONFIG_SAMV7_TWIHS0_FREQUENCY=100000 +CONFIG_SAMV7_TWIHS0_GLITCH_FILTER=1 # # HSMCI device driver options @@ -367,8 +368,6 @@ CONFIG_ARCH_HAVE_BUTTONS=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_HAVE_IRQBUTTONS=y CONFIG_ARCH_IRQBUTTONS=y -CONFIG_NSH_MMCSDMINOR=0 -CONFIG_NSH_MMCSDSLOTNO=0 # # Board-Specific Options @@ -379,6 +378,7 @@ CONFIG_SAMV71XULT_MXTXPLND_LCD=y CONFIG_SAMV71XULT_MXT_I2CFREQUENCY=400000 CONFIG_SAMV71XULT_MXT_DEVMINOR=0 CONFIG_SAMV71XULT_LCD_BGCOLOR=0x00 +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_TSCTEST=y @@ -514,10 +514,11 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set # CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set # CONFIG_PWM is not set -# CONFIG_ARCH_HAVE_I2CRESET is not set +CONFIG_ARCH_HAVE_I2CRESET=y CONFIG_I2C=y # CONFIG_I2C_SLAVE is not set # CONFIG_I2C_POLLED is not set +# CONFIG_I2C_RESET is not set # CONFIG_I2C_TRACE is not set CONFIG_I2C_DRIVER=y CONFIG_SPI=y @@ -555,7 +556,12 @@ CONFIG_MXT_THRESHY=8 # CONFIG_BUTTONS is not set # CONFIG_DJOYSTICK is not set # CONFIG_AJOYSTICK is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -944,6 +950,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -1155,6 +1162,8 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 # # Configure Command Options diff --git a/configs/samv71-xult/netnsh/defconfig b/configs/samv71-xult/netnsh/defconfig index 90595673e0175f1aab30a96bed05601be2605bd5..72d049526b0ad7d368e23231842baf50b73ae86c 100644 --- a/configs/samv71-xult/netnsh/defconfig +++ b/configs/samv71-xult/netnsh/defconfig @@ -285,6 +285,7 @@ CONFIG_SAMV7_GPIOD_IRQ=y # TWIHS device driver options # CONFIG_SAMV7_TWIHS0_FREQUENCY=100000 +CONFIG_SAMV7_TWIHS0_GLITCH_FILTER=1 # # HSMCI device driver options @@ -389,13 +390,12 @@ CONFIG_ARCH_HAVE_BUTTONS=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_HAVE_IRQBUTTONS=y CONFIG_ARCH_IRQBUTTONS=y -CONFIG_NSH_MMCSDMINOR=0 -CONFIG_NSH_MMCSDSLOTNO=0 # # Board-Specific Options # # CONFIG_SAMV71XULT_MXTXPLND is not set +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set @@ -531,10 +531,11 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set # CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set # CONFIG_PWM is not set -# CONFIG_ARCH_HAVE_I2CRESET is not set +CONFIG_ARCH_HAVE_I2CRESET=y CONFIG_I2C=y # CONFIG_I2C_SLAVE is not set # CONFIG_I2C_POLLED is not set +# CONFIG_I2C_RESET is not set # CONFIG_I2C_TRACE is not set CONFIG_I2C_DRIVER=y CONFIG_SPI=y @@ -561,7 +562,12 @@ CONFIG_SPI_EXCHANGE=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -998,6 +1004,7 @@ CONFIG_NETDB_DNSSERVER_IPv4ADDR=0x0a000001 # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -1217,6 +1224,8 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 # # Configure Command Options diff --git a/configs/samv71-xult/nsh/defconfig b/configs/samv71-xult/nsh/defconfig index 03913ee6a10e549747ae5c062679c4a29f3f03d2..7ad935aa3222798aa6ff43742838b8c356a050e6 100644 --- a/configs/samv71-xult/nsh/defconfig +++ b/configs/samv71-xult/nsh/defconfig @@ -290,6 +290,8 @@ CONFIG_SAMV7_SDRAMSIZE=2097152 # TWIHS device driver options # CONFIG_SAMV7_TWIHS0_FREQUENCY=100000 +CONFIG_SAMV7_TWIHS0_GLITCH_FILTER=0 +CONFIG_SAMV7_TWIHS0_SINGLE_MASTER=y # # HSMCI device driver options @@ -373,13 +375,12 @@ CONFIG_ARCH_HAVE_BUTTONS=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_HAVE_IRQBUTTONS=y CONFIG_ARCH_IRQBUTTONS=y -CONFIG_NSH_MMCSDMINOR=0 -CONFIG_NSH_MMCSDSLOTNO=0 # # Board-Specific Options # # CONFIG_SAMV71XULT_MXTXPLND is not set +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set @@ -515,10 +516,11 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set # CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set # CONFIG_PWM is not set -# CONFIG_ARCH_HAVE_I2CRESET is not set +CONFIG_ARCH_HAVE_I2CRESET=y CONFIG_I2C=y # CONFIG_I2C_SLAVE is not set # CONFIG_I2C_POLLED is not set +CONFIG_I2C_RESET=y # CONFIG_I2C_TRACE is not set CONFIG_I2C_DRIVER=y CONFIG_SPI=y @@ -545,7 +547,12 @@ CONFIG_SPI_EXCHANGE=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -817,6 +824,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -1016,6 +1024,8 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 # # Configure Command Options diff --git a/configs/samv71-xult/nxwm/defconfig b/configs/samv71-xult/nxwm/defconfig index c6e14be293ab344a9362878e3db5ffe80e0ea6d4..006b3160fa9b438089943583e5508e6e37d7f8be 100644 --- a/configs/samv71-xult/nxwm/defconfig +++ b/configs/samv71-xult/nxwm/defconfig @@ -284,6 +284,7 @@ CONFIG_SAMV7_GPIOD_IRQ=y # TWIHS device driver options # CONFIG_SAMV7_TWIHS0_FREQUENCY=100000 +CONFIG_SAMV7_TWIHS0_GLITCH_FILTER=1 # # HSMCI device driver options @@ -367,8 +368,6 @@ CONFIG_ARCH_HAVE_BUTTONS=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_HAVE_IRQBUTTONS=y CONFIG_ARCH_IRQBUTTONS=y -CONFIG_NSH_MMCSDMINOR=0 -CONFIG_NSH_MMCSDSLOTNO=0 # # Board-Specific Options @@ -379,6 +378,7 @@ CONFIG_SAMV71XULT_MXTXPLND_LCD=y CONFIG_SAMV71XULT_MXT_I2CFREQUENCY=400000 CONFIG_SAMV71XULT_MXT_DEVMINOR=0 CONFIG_SAMV71XULT_LCD_BGCOLOR=0x95fa +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_TSCTEST=y @@ -517,10 +517,11 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set # CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set # CONFIG_PWM is not set -# CONFIG_ARCH_HAVE_I2CRESET is not set +CONFIG_ARCH_HAVE_I2CRESET=y CONFIG_I2C=y # CONFIG_I2C_SLAVE is not set # CONFIG_I2C_POLLED is not set +# CONFIG_I2C_RESET is not set # CONFIG_I2C_TRACE is not set CONFIG_I2C_DRIVER=y CONFIG_SPI=y @@ -558,7 +559,12 @@ CONFIG_MXT_THRESHY=8 # CONFIG_BUTTONS is not set # CONFIG_DJOYSTICK is not set # CONFIG_AJOYSTICK is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -959,6 +965,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -1156,6 +1163,8 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 # # Configure Command Options diff --git a/configs/samv71-xult/src/sam_appinit.c b/configs/samv71-xult/src/sam_appinit.c index f7215ff46507c3aeaeca433fb5751ada19642134..9e59395cc1016d8684283a11031579c1a7448c3b 100644 --- a/configs/samv71-xult/src/sam_appinit.c +++ b/configs/samv71-xult/src/sam_appinit.c @@ -45,7 +45,7 @@ #include "samv71-xult.h" -#if defined(CONFIG_LIB_BOARDCTL) && !defined(CONFIG_BUILD_KERNEL) +#ifdef CONFIG_LIB_BOARDCTL /**************************************************************************** * Public Functions @@ -87,4 +87,4 @@ int board_app_initialize(uintptr_t arg) #endif } -#endif /* CONFIG_LIB_BOARDCTL && !CONFIG_BUILD_KERNEL */ +#endif /* CONFIG_LIB_BOARDCTL */ diff --git a/configs/samv71-xult/src/sam_bringup.c b/configs/samv71-xult/src/sam_bringup.c index b6a33379722791e64d595e8a3b60548e2a0aa63d..845e00df9a2fea12f6c7abe3570154702a724678 100644 --- a/configs/samv71-xult/src/sam_bringup.c +++ b/configs/samv71-xult/src/sam_bringup.c @@ -46,8 +46,8 @@ #include #include -#ifdef CONFIG_SYSTEM_USBMONITOR -# include +#ifdef CONFIG_USBMONITOR +# include #endif #include @@ -477,7 +477,7 @@ int sam_bringup(void) #ifdef HAVE_USBMONITOR /* Start the USB Monitor */ - ret = usbmonitor_start(0, NULL); + ret = usbmonitor_start(); if (ret != OK) { _err("ERROR: Failed to start the USB monitor: %d\n", ret); diff --git a/configs/samv71-xult/src/samv71-xult.h b/configs/samv71-xult/src/samv71-xult.h index 08394c5c8148c4ec2d81670387bccfdff19f4254..3ce8ed2673160dbd9d5d032df2865f3286785582 100644 --- a/configs/samv71-xult/src/samv71-xult.h +++ b/configs/samv71-xult/src/samv71-xult.h @@ -166,7 +166,7 @@ # undef CONFIG_USBDEV_TRACE #endif -#if !defined(CONFIG_SYSTEM_USBMONITOR) || !defined(CONFIG_USBDEV_TRACE) +#if !defined(CONFIG_USBMONITOR) || !defined(CONFIG_USBDEV_TRACE) # undef HAVE_USBMONITOR #endif diff --git a/configs/samv71-xult/vnc/defconfig b/configs/samv71-xult/vnc/defconfig index df447f54cf6d02fedfbca11bd65a47364124990d..61869888460bcef8578f21cf2d6afe4450a59338 100644 --- a/configs/samv71-xult/vnc/defconfig +++ b/configs/samv71-xult/vnc/defconfig @@ -284,6 +284,7 @@ CONFIG_SAMV7_GPIOD_IRQ=y # TWIHS device driver options # CONFIG_SAMV7_TWIHS0_FREQUENCY=100000 +CONFIG_SAMV7_TWIHS0_GLITCH_FILTER=1 # # HSMCI device driver options @@ -388,13 +389,12 @@ CONFIG_ARCH_HAVE_BUTTONS=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_HAVE_IRQBUTTONS=y CONFIG_ARCH_IRQBUTTONS=y -CONFIG_NSH_MMCSDMINOR=0 -CONFIG_NSH_MMCSDSLOTNO=0 # # Board-Specific Options # # CONFIG_SAMV71XULT_MXTXPLND is not set +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set @@ -531,10 +531,11 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set # CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set # CONFIG_PWM is not set -# CONFIG_ARCH_HAVE_I2CRESET is not set +CONFIG_ARCH_HAVE_I2CRESET=y CONFIG_I2C=y # CONFIG_I2C_SLAVE is not set # CONFIG_I2C_POLLED is not set +# CONFIG_I2C_RESET is not set # CONFIG_I2C_TRACE is not set CONFIG_I2C_DRIVER=y CONFIG_SPI=y @@ -561,7 +562,12 @@ CONFIG_SPI_EXCHANGE=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -1090,6 +1096,7 @@ CONFIG_LIBC_NETDB=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -1301,6 +1308,8 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 # # Configure Command Options diff --git a/configs/samv71-xult/vnxwm/defconfig b/configs/samv71-xult/vnxwm/defconfig index f4327906b8b3ef6393df57038b2ec747918464b8..9823caf7900e6025ce94ee4d42bd2d82beb16d2f 100644 --- a/configs/samv71-xult/vnxwm/defconfig +++ b/configs/samv71-xult/vnxwm/defconfig @@ -284,6 +284,7 @@ CONFIG_SAMV7_GPIOD_IRQ=y # TWIHS device driver options # CONFIG_SAMV7_TWIHS0_FREQUENCY=100000 +CONFIG_SAMV7_TWIHS0_GLITCH_FILTER=1 # # HSMCI device driver options @@ -388,13 +389,12 @@ CONFIG_ARCH_HAVE_BUTTONS=y CONFIG_ARCH_BUTTONS=y CONFIG_ARCH_HAVE_IRQBUTTONS=y CONFIG_ARCH_IRQBUTTONS=y -CONFIG_NSH_MMCSDMINOR=0 -CONFIG_NSH_MMCSDSLOTNO=0 # # Board-Specific Options # # CONFIG_SAMV71XULT_MXTXPLND is not set +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set @@ -534,10 +534,11 @@ CONFIG_DEV_NULL=y # CONFIG_ARCH_HAVE_PWM_PULSECOUNT is not set # CONFIG_ARCH_HAVE_PWM_MULTICHAN is not set # CONFIG_PWM is not set -# CONFIG_ARCH_HAVE_I2CRESET is not set +CONFIG_ARCH_HAVE_I2CRESET=y CONFIG_I2C=y # CONFIG_I2C_SLAVE is not set # CONFIG_I2C_POLLED is not set +# CONFIG_I2C_RESET is not set # CONFIG_I2C_TRACE is not set CONFIG_I2C_DRIVER=y CONFIG_SPI=y @@ -564,7 +565,12 @@ CONFIG_SPI_EXCHANGE=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -1114,6 +1120,7 @@ CONFIG_LIBC_NETDB=y # CONFIG_LIB_CRC64_FAST is not set # CONFIG_LIB_KBDCODEC is not set # CONFIG_LIB_SLCDCODEC is not set +# CONFIG_LIB_HEX2BIN is not set # # Basic CXX Support @@ -1322,6 +1329,8 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 # # Configure Command Options diff --git a/configs/shenzhou/nsh/defconfig b/configs/shenzhou/nsh/defconfig index af9e9154390028b2039f170beabe795c613ef73a..2ef672ff6971b52cc4affab6cae0f5118b8d6c36 100644 --- a/configs/shenzhou/nsh/defconfig +++ b/configs/shenzhou/nsh/defconfig @@ -1394,7 +1394,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/shenzhou/nxwm/defconfig b/configs/shenzhou/nxwm/defconfig index dd76d669aa82955ff036fa4fca239401cf64b30b..944936912a5be46c9683396452fd834d7bd3baa5 100644 --- a/configs/shenzhou/nxwm/defconfig +++ b/configs/shenzhou/nxwm/defconfig @@ -1721,7 +1721,7 @@ CONFIG_NXWM_HEXCALCULATOR_FONTID=5 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/shenzhou/thttpd/defconfig b/configs/shenzhou/thttpd/defconfig index a1150884ef1ab89ae80f6187bdf711ace213f4b4..64cb41b51703cf491869e24192216416a2a5ed55 100644 --- a/configs/shenzhou/thttpd/defconfig +++ b/configs/shenzhou/thttpd/defconfig @@ -1499,7 +1499,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FLASH_ERASEALL is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/sim/bas/defconfig b/configs/sim/bas/defconfig index 0045828f2e902991d2ea766ed40d62932c8a2ff5..28b919a3eec021bdb1920c0cdae624da7cc02040 100644 --- a/configs/sim/bas/defconfig +++ b/configs/sim/bas/defconfig @@ -717,7 +717,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_FSUTILS_INIFILE is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sim/configdata/defconfig b/configs/sim/configdata/defconfig index 1f8af42edf55000dc2978d1fbd67bdeefde87409..7b5ffd275e709d9dc7f888778880a12923389be3 100644 --- a/configs/sim/configdata/defconfig +++ b/configs/sim/configdata/defconfig @@ -625,7 +625,7 @@ CONFIG_PLATFORM_CONFIGDATA=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_FSUTILS_INIFILE is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sim/cxxtest/defconfig b/configs/sim/cxxtest/defconfig index aceb1fc38d89cda9681519df0517f00f342f4c67..11b482a7282c9a3dba9e2bb3177a672ce9fcb37d 100644 --- a/configs/sim/cxxtest/defconfig +++ b/configs/sim/cxxtest/defconfig @@ -600,7 +600,7 @@ CONFIG_EXAMPLES_CXXTEST=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_FSUTILS_INIFILE is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sim/mount/defconfig b/configs/sim/mount/defconfig index 60d8ee2f281fb883091331d1f286cf5593c01037..e9031cd22e436a2d42d61b4584c12cc774743426 100644 --- a/configs/sim/mount/defconfig +++ b/configs/sim/mount/defconfig @@ -598,7 +598,7 @@ CONFIG_EXAMPLES_MOUNT_DEVNAME="/dev/ram0" # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_FSUTILS_INIFILE is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sim/mtdpart/defconfig b/configs/sim/mtdpart/defconfig index df0f7c19a466171e46c62e9eb0089a2975045f26..74c851f7f2f0ca36ece64f74048f10b729453694 100644 --- a/configs/sim/mtdpart/defconfig +++ b/configs/sim/mtdpart/defconfig @@ -607,7 +607,7 @@ CONFIG_EXAMPLES_MTDPART_NPARTITIONS=3 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_FSUTILS_INIFILE is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sim/mtdrwb/defconfig b/configs/sim/mtdrwb/defconfig index f7da4507c064d71d923a690d837aa24a920f1664..6e56c95229f1724fff54a9c8ef0747d6505c7794 100644 --- a/configs/sim/mtdrwb/defconfig +++ b/configs/sim/mtdrwb/defconfig @@ -639,7 +639,7 @@ CONFIG_EXAMPLES_MTDRWB_NEBLOCKS=32 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_FSUTILS_INIFILE is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sim/nettest/defconfig b/configs/sim/nettest/defconfig index a5124f251aafb6e06609c2da12b48fda2fd5a4e2..f16f365741d701d6c5f6c321c7f9bc72404dd548 100644 --- a/configs/sim/nettest/defconfig +++ b/configs/sim/nettest/defconfig @@ -728,7 +728,7 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_RAMTEST is not set # CONFIG_READLINE_HAVE_EXTMATCH is not set diff --git a/configs/sim/nsh/defconfig b/configs/sim/nsh/defconfig index b0eb7f0c9fb3e9ab00a95941ed2df97e4a4a7c41..1cd2e2842ca34bcb641b71a70aae51ad7a013e18 100644 --- a/configs/sim/nsh/defconfig +++ b/configs/sim/nsh/defconfig @@ -764,7 +764,7 @@ CONFIG_NSH_LOGIN_FAILCOUNT=3 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sim/nsh2/defconfig b/configs/sim/nsh2/defconfig index bc6571c458a53c245dbb77c9b55ce5a7f28bfd9b..baefa6fdcecdaf4b0d49cf7167968e531d6dc874 100644 --- a/configs/sim/nsh2/defconfig +++ b/configs/sim/nsh2/defconfig @@ -841,7 +841,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_FSUTILS_INIFILE is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sim/nx/defconfig b/configs/sim/nx/defconfig index 688161175d96a925ce5223cc105682a87aadca5e..8c2777349d769b771b8dd153eb212bd4ce0738b8 100644 --- a/configs/sim/nx/defconfig +++ b/configs/sim/nx/defconfig @@ -672,7 +672,7 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_FSUTILS_INIFILE is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sim/nx11/defconfig b/configs/sim/nx11/defconfig index d1987dc8aba20011d784ed70ca0e2def5e3b3ef6..b43102e8d60d6c22bd15317c0a956287181ba3e1 100644 --- a/configs/sim/nx11/defconfig +++ b/configs/sim/nx11/defconfig @@ -674,7 +674,7 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_FSUTILS_INIFILE is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sim/nxffs/defconfig b/configs/sim/nxffs/defconfig index 1cd792167e30bb7546c61fadfe71569d776bb41a..49f9a76e56448eaf6a4affaa835c02f7f6eb5612 100644 --- a/configs/sim/nxffs/defconfig +++ b/configs/sim/nxffs/defconfig @@ -596,7 +596,7 @@ CONFIG_EXAMPLES_NXFFS_NLOOPS=100 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_FSUTILS_INIFILE is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sim/nxlines/defconfig b/configs/sim/nxlines/defconfig index 28f3880aedb24728f983fdfe1cdd5d0705be38e5..4bb0377e58612d2fc6b9b4a268ecd023a6943959 100644 --- a/configs/sim/nxlines/defconfig +++ b/configs/sim/nxlines/defconfig @@ -813,7 +813,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_FSUTILS_INIFILE is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sim/nxwm/defconfig b/configs/sim/nxwm/defconfig index 9287f229bd6b424b0584294f6b248d6b5158a063..9413d2dbe6bf03e7b4f905e1ef51767eec1e5a5b 100644 --- a/configs/sim/nxwm/defconfig +++ b/configs/sim/nxwm/defconfig @@ -969,7 +969,7 @@ CONFIG_NXWM_CALIBRATION_LISTENERSTACK=2048 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_FSUTILS_INIFILE is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sim/ostest/defconfig b/configs/sim/ostest/defconfig index 8928a46a2e7199e36d5679443f8318859319f460..e96b5b2232300efe045ad20ed8733f30cf76221b 100644 --- a/configs/sim/ostest/defconfig +++ b/configs/sim/ostest/defconfig @@ -608,7 +608,7 @@ CONFIG_EXAMPLES_OSTEST_WAITRESULT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_RAMTEST is not set # CONFIG_READLINE_HAVE_EXTMATCH is not set diff --git a/configs/sim/pashello/defconfig b/configs/sim/pashello/defconfig index c82757a6aa8b1a2b637d9445f8ebf13324c492df..0b9ea16bb07cbe6136789b627af9a714bcb5fc8f 100644 --- a/configs/sim/pashello/defconfig +++ b/configs/sim/pashello/defconfig @@ -576,7 +576,7 @@ CONFIG_INTERPRETERS_PCODE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_FSUTILS_INIFILE is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sim/src/Makefile b/configs/sim/src/Makefile index 9f45e7e93bf00c22dfc590b460c71c76cdf7441f..1ab3f04975fc243fc565a5408ed5c183d309cdfd 100644 --- a/configs/sim/src/Makefile +++ b/configs/sim/src/Makefile @@ -48,12 +48,12 @@ endif ifeq ($(CONFIG_BOARD_INITIALIZE),y) CSRCS += sim_bringup.c -ifeq ($(CONFIG_SYSTEM_ZONEINFO_ROMFS),y) +ifeq ($(CONFIG_LIB_ZONEINFO_ROMFS),y) CSRCS += sim_zoneinfo.c endif else ifeq ($(CONFIG_LIB_BOARDCTL),y) CSRCS += sim_bringup.c -ifeq ($(CONFIG_SYSTEM_ZONEINFO_ROMFS),y) +ifeq ($(CONFIG_LIB_ZONEINFO_ROMFS),y) CSRCS += sim_zoneinfo.c endif endif diff --git a/configs/sim/src/sim.h b/configs/sim/src/sim.h index 355d085022ead524dba01c36624d1d1dd2a785af..0e1f27937d3fb0813d006c1f208eece7a564d1f1 100644 --- a/configs/sim/src/sim.h +++ b/configs/sim/src/sim.h @@ -73,7 +73,7 @@ int sim_bringup(void); * Name: sim_zoneinfo * * Description: - * Mount the TZ database. The apps/system/zoneinfo directory contains + * Mount the TZ database. The nuttx/zoneinfo directory contains * logic to create a version of the TZ/Olson database. * This database is required if localtime() support is selected via * CONFIG_LIBC_LOCALTIME. This logic in that directory does the following: @@ -107,7 +107,7 @@ int sim_bringup(void); * ****************************************************************************/ -#ifdef CONFIG_SYSTEM_ZONEINFO_ROMFS +#ifdef CONFIG_LIB_ZONEINFO_ROMFS int sim_zoneinfo(int minor); #endif diff --git a/configs/sim/src/sim_bringup.c b/configs/sim/src/sim_bringup.c index d65d99edb3b8ab078c48627c70a0ccb9e2609204..86790206dd3a2b94b4b2e4b3a9e8fc15afe0db09 100644 --- a/configs/sim/src/sim_bringup.c +++ b/configs/sim/src/sim_bringup.c @@ -71,7 +71,7 @@ int sim_bringup(void) int ret; #endif -#ifdef CONFIG_SYSTEM_ZONEINFO_ROMFS +#ifdef CONFIG_LIB_ZONEINFO_ROMFS /* Mount the TZ database */ (void)sim_zoneinfo(3); diff --git a/configs/sim/src/sim_zoneinfo.c b/configs/sim/src/sim_zoneinfo.c index 1e3840917c321a4bdaafdbf0d3d3a47fce126627..dbb85025e7934baf2d7f63c1c70e83a03dfe9f6c 100644 --- a/configs/sim/src/sim_zoneinfo.c +++ b/configs/sim/src/sim_zoneinfo.c @@ -1,7 +1,7 @@ /**************************************************************************** * config/sim/src/sim_zoneinfo.c * - * Copyright (C) 2015 Gregory Nutt. All rights reserved. + * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -45,9 +45,9 @@ #include #include -#include +#include -#ifdef CONFIG_SYSTEM_ZONEINFO_ROMFS +#ifdef CONFIG_LIB_ZONEINFO_ROMFS /**************************************************************************** * Pre-processor Definitions @@ -80,7 +80,7 @@ * Name: sim_zoneinfo * * Description: - * Mount the TZ database. The apps/system/zoneinfo directory contains + * Mount the TZ database. The nuttx/zoneinfo directory contains * logic to create a version of the TZ/Olson database. * This database is required if localtime() support is selected via * CONFIG_LIBC_LOCALTIME. This logic in that directory does the following: @@ -149,5 +149,5 @@ int sim_zoneinfo(int minor) return OK; } -#endif /* CONFIG_SYSTEM_ZONEINFO_ROMFS */ +#endif /* CONFIG_LIB_ZONEINFO_ROMFS */ diff --git a/configs/sim/touchscreen/defconfig b/configs/sim/touchscreen/defconfig index 01012d9eed0614e499f4549f2d8244db9a73588e..7be0481745558695e0fcdaa5cdfe173713a0f663 100644 --- a/configs/sim/touchscreen/defconfig +++ b/configs/sim/touchscreen/defconfig @@ -694,7 +694,7 @@ CONFIG_EXAMPLES_TOUCHSCREEN_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_FSUTILS_INIFILE is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sim/traveler/defconfig b/configs/sim/traveler/defconfig index 4c260ef8943d56808ebe269d866876701755adf1..b38a951a5e5ce2c9760cb3c9468f99dfe7cfdb6e 100644 --- a/configs/sim/traveler/defconfig +++ b/configs/sim/traveler/defconfig @@ -638,7 +638,7 @@ CONFIG_GRAPHICS_TRAVELER_DEBUG_LEVEL=0 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set CONFIG_FSUTILS_INIFILE=y CONFIG_FSUTILS_INIFILE_MAXLINE=256 CONFIG_FSUTILS_INIFILE_DEBUGLEVEL=0 diff --git a/configs/sim/udgram/defconfig b/configs/sim/udgram/defconfig index 2c747306d8907d250323920eb2f6ebeaaeb2f8eb..7ed422934d7f7c94999e608fa33cb4f0853a83d2 100644 --- a/configs/sim/udgram/defconfig +++ b/configs/sim/udgram/defconfig @@ -852,7 +852,7 @@ CONFIG_NSH_MAX_ROUNDTRIP=20 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/sim/unionfs/defconfig b/configs/sim/unionfs/defconfig index 7bfe0b1ec3b25d4b395d40838b0f8253084c9986..077ef2661c4ca67dd65e185b7f1101621057efeb 100644 --- a/configs/sim/unionfs/defconfig +++ b/configs/sim/unionfs/defconfig @@ -715,7 +715,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_FSUTILS_INIFILE is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sim/ustream/defconfig b/configs/sim/ustream/defconfig index 54a65071316165aa934453678cd8808b3d6bb341..38338722ee788023d91ef7e375cb14cd03fb72b0 100644 --- a/configs/sim/ustream/defconfig +++ b/configs/sim/ustream/defconfig @@ -847,7 +847,7 @@ CONFIG_NSH_MAX_ROUNDTRIP=20 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/spark/composite/defconfig b/configs/spark/composite/defconfig index 1ef402810f6b1676fac8e1bc648ac3f970414b0a..ebae43436a4c74041678bfcc494d1387a94f554f 100644 --- a/configs/spark/composite/defconfig +++ b/configs/spark/composite/defconfig @@ -1294,7 +1294,7 @@ CONFIG_SYSTEM_COMPOSITE_BUFSIZE=256 # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FLASH_ERASEALL is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set @@ -1305,7 +1305,7 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set # CONFIG_SYSTEM_UBLOXMODEM is not set -# CONFIG_SYSTEM_USBMONITOR is not set +# CONFIG_USBMONITOR is not set # CONFIG_SYSTEM_USBMSC is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/spark/nsh/defconfig b/configs/spark/nsh/defconfig index 749fdc5e65eec8fdd02dac06ccd3e4c8a479d41e..d9a47e30fe4706e7b6a14eb2c667bd619d68c948 100644 --- a/configs/spark/nsh/defconfig +++ b/configs/spark/nsh/defconfig @@ -1280,7 +1280,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FLASH_ERASEALL is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set @@ -1291,7 +1291,7 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set # CONFIG_SYSTEM_UBLOXMODEM is not set -# CONFIG_SYSTEM_USBMONITOR is not set +# CONFIG_USBMONITOR is not set # CONFIG_SYSTEM_USBMSC is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/spark/src/spark.h b/configs/spark/src/spark.h index 4eb5ed6a840f4a2d57c2c771d3f46c1690150d3e..0bfd4e3a0566dbdf8cca2e8673d637cb136cf469 100644 --- a/configs/spark/src/spark.h +++ b/configs/spark/src/spark.h @@ -45,6 +45,7 @@ #include #include #include +#include /************************************************************************************ * Pre-processor Definitions diff --git a/configs/spark/src/stm32_appinit.c b/configs/spark/src/stm32_appinit.c index ebb3518af77825507cd10c6540d55e0a65e5c8dc..1b484caa4893b821f4193a9e90a284b0b87842e4 100644 --- a/configs/spark/src/stm32_appinit.c +++ b/configs/spark/src/stm32_appinit.c @@ -54,8 +54,8 @@ # include #endif -#ifdef CONFIG_SYSTEM_USBMONITOR -# include +#ifdef CONFIG_USBMONITOR +# include #endif #ifdef CONFIG_USBDEV @@ -112,7 +112,7 @@ /* Check if we should enable the USB monitor before starting NSH */ -#if !defined(CONFIG_USBDEV_TRACE) || !defined(CONFIG_SYSTEM_USBMONITOR) +#if !defined(CONFIG_USBDEV_TRACE) || !defined(CONFIG_USBMONITOR) # undef HAVE_USBMONITOR #endif @@ -305,7 +305,7 @@ int board_app_initialize(uintptr_t arg) /* Start the USB Monitor */ - ret = usbmonitor_start(0, NULL); + ret = usbmonitor_start(); if (ret != OK) { syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); diff --git a/configs/spark/src/stm32_composite.c b/configs/spark/src/stm32_composite.c index e38c769e64d147c5a1a239f404d00d15ea60600d..2c50a59a1f89c948f4b5c3e299b3ddbbb5f003be 100644 --- a/configs/spark/src/stm32_composite.c +++ b/configs/spark/src/stm32_composite.c @@ -54,8 +54,8 @@ # include #endif -#ifdef CONFIG_SYSTEM_USBMONITOR -# include +#ifdef CONFIG_USBMONITOR +# include #endif #ifdef CONFIG_USBDEV @@ -112,7 +112,7 @@ /* Check if we should enable the USB monitor before starting NSH */ -#if !defined(CONFIG_USBDEV_TRACE) || !defined(CONFIG_SYSTEM_USBMONITOR) +#if !defined(CONFIG_USBDEV_TRACE) || !defined(CONFIG_USBMONITOR) # undef HAVE_USBMONITOR #endif @@ -269,7 +269,7 @@ static int stm32_composite_initialize(void) #ifdef HAVE_USBMONITOR /* Start the USB Monitor */ - ret = usbmonitor_start(0, NULL); + ret = usbmonitor_start(); if (ret != OK) { ferr("ERROR: Failed to start USB monitor: %d\n", ret); diff --git a/configs/spark/usbmsc/defconfig b/configs/spark/usbmsc/defconfig index 9e05a1f1b467a67ea92cf04fb46e91cc57efcb38..4f991586f5e65267ca4cf06cd4e160703e8f5b8b 100644 --- a/configs/spark/usbmsc/defconfig +++ b/configs/spark/usbmsc/defconfig @@ -1242,7 +1242,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FLASH_ERASEALL is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set @@ -1253,7 +1253,7 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set # CONFIG_SYSTEM_UBLOXMODEM is not set -# CONFIG_SYSTEM_USBMONITOR is not set +# CONFIG_USBMONITOR is not set CONFIG_SYSTEM_USBMSC=y CONFIG_SYSTEM_USBMSC_NLUNS=1 CONFIG_SYSTEM_USBMSC_DEVMINOR1=0 diff --git a/configs/spark/usbnsh/defconfig b/configs/spark/usbnsh/defconfig index 1316e8034d2d718deb85ea004ce9bee0c6bdd7cc..5a07b8ca541384b7bc752658497c2c3b47522bca 100644 --- a/configs/spark/usbnsh/defconfig +++ b/configs/spark/usbnsh/defconfig @@ -1225,7 +1225,7 @@ CONFIG_USBDEV_MINOR=0 # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FLASH_ERASEALL is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set @@ -1236,6 +1236,6 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set # CONFIG_SYSTEM_UBLOXMODEM is not set -# CONFIG_SYSTEM_USBMONITOR is not set +# CONFIG_USBMONITOR is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/spark/usbserial/defconfig b/configs/spark/usbserial/defconfig index 76625f70fa284c63efd4fd2e4328da0094114f89..4f8ad4de4b6c4832fad853e9820778bf0e4af8e3 100644 --- a/configs/spark/usbserial/defconfig +++ b/configs/spark/usbserial/defconfig @@ -1161,7 +1161,7 @@ CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set @@ -1169,6 +1169,6 @@ CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=y # CONFIG_SYSTEM_READLINE is not set # CONFIG_SYSTEM_SUDOKU is not set # CONFIG_SYSTEM_UBLOXMODEM is not set -# CONFIG_SYSTEM_USBMONITOR is not set +# CONFIG_USBMONITOR is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm3210e-eval/buttons/defconfig b/configs/stm3210e-eval/buttons/defconfig index 6253cf21939652ccead6c663ecea4f307187d158..15ea4b73960fc7f2764b728e377d55c6004b9f01 100644 --- a/configs/stm3210e-eval/buttons/defconfig +++ b/configs/stm3210e-eval/buttons/defconfig @@ -1021,7 +1021,7 @@ CONFIG_EXAMPLES_BUTTONS_NAME7="UP" # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm3210e-eval/composite/defconfig b/configs/stm3210e-eval/composite/defconfig index fa4db610c0c29896914afb0823d5e78233fb1b4e..ac8c38d7e32bdde99f50901e97e941ed0689e389 100644 --- a/configs/stm3210e-eval/composite/defconfig +++ b/configs/stm3210e-eval/composite/defconfig @@ -1185,7 +1185,7 @@ CONFIG_SYSTEM_COMPOSITE_BUFSIZE=256 # CONFIG_SYSTEM_COMPOSITE_DEBUGMM is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm3210e-eval/nsh/defconfig b/configs/stm3210e-eval/nsh/defconfig index fc951bb2b63a413ae3e1c4a7e8d5b15ad6df28d1..0f9a0ad3e8a6e50cf8bae15a27edd1b731217680 100644 --- a/configs/stm3210e-eval/nsh/defconfig +++ b/configs/stm3210e-eval/nsh/defconfig @@ -1222,7 +1222,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm3210e-eval/nsh2/defconfig b/configs/stm3210e-eval/nsh2/defconfig index e5f10041dd97d2af53f35037c297d8e20d4dbcfd..1497a49383399388de25b320595e9a4ee248a0a8 100644 --- a/configs/stm3210e-eval/nsh2/defconfig +++ b/configs/stm3210e-eval/nsh2/defconfig @@ -1419,7 +1419,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FLASH_ERASEALL is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set CONFIG_SYSTEM_I2CTOOL=y CONFIG_I2CTOOL_MINBUS=1 diff --git a/configs/stm3210e-eval/nx/defconfig b/configs/stm3210e-eval/nx/defconfig index 451e9024a9b1671e62563aab123d56d6991244e2..655e709976711bd117063b3c5309c9a26711459a 100644 --- a/configs/stm3210e-eval/nx/defconfig +++ b/configs/stm3210e-eval/nx/defconfig @@ -1197,7 +1197,7 @@ CONFIG_EXAMPLES_NX_TOOLBAR_HEIGHT=16 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm3210e-eval/nxterm/defconfig b/configs/stm3210e-eval/nxterm/defconfig index 02bf3d366a538cb9ba28de4bb3ba4c7fe4860b6e..50f19608b6b792a6a9d059847f17b98c8a58a930 100644 --- a/configs/stm3210e-eval/nxterm/defconfig +++ b/configs/stm3210e-eval/nxterm/defconfig @@ -1289,7 +1289,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm3210e-eval/pm/defconfig b/configs/stm3210e-eval/pm/defconfig index b23c795374b0eef7845c7155348e198f9a48f9e1..59f7f4a72c363413a193446aed3127295fb4ca70 100644 --- a/configs/stm3210e-eval/pm/defconfig +++ b/configs/stm3210e-eval/pm/defconfig @@ -1342,7 +1342,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm3210e-eval/src/stm32_pmbuttons.c b/configs/stm3210e-eval/src/stm32_pmbuttons.c index 3e723af37fb7441c2dd51e012a738fa50ee15e87..50a06cc95d5bad99f26474bd4fd29ab4a9012115 100644 --- a/configs/stm3210e-eval/src/stm32_pmbuttons.c +++ b/configs/stm3210e-eval/src/stm32_pmbuttons.c @@ -318,9 +318,9 @@ void stm32_pmbuttons(void) if (oldhandler != NULL) { - warn("WARNING: oldhandler:%p is not NULL! " - "Button events may be lost or aliased!\n", - oldhandler); + swarn("WARNING: oldhandler:%p is not NULL! " + "Button events may be lost or aliased!\n", + oldhandler); } } #endif diff --git a/configs/stm3210e-eval/usbmsc/defconfig b/configs/stm3210e-eval/usbmsc/defconfig index 4914b222edfb037c7ee4c437c1749ae1f54f42e2..8f3417861854e6c516f13d28b39b31a65eafa2bf 100644 --- a/configs/stm3210e-eval/usbmsc/defconfig +++ b/configs/stm3210e-eval/usbmsc/defconfig @@ -1099,7 +1099,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm3210e-eval/usbserial/defconfig b/configs/stm3210e-eval/usbserial/defconfig index f8223e3a144a823614c87f57af3efb345f3af80a..e28ddba956753655b4c8cd8fc9c35489395a94a7 100644 --- a/configs/stm3210e-eval/usbserial/defconfig +++ b/configs/stm3210e-eval/usbserial/defconfig @@ -1062,7 +1062,7 @@ CONFIG_EXAMPLES_USBSERIAL_BUFSIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm3220g-eval/dhcpd/defconfig b/configs/stm3220g-eval/dhcpd/defconfig index 0d999829eecbde5e2344feba801220309dd5acfe..5bd2028bcfc6cd84d82c1ad50486a3bcb465c5fc 100644 --- a/configs/stm3220g-eval/dhcpd/defconfig +++ b/configs/stm3220g-eval/dhcpd/defconfig @@ -1197,7 +1197,7 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm3220g-eval/nettest/defconfig b/configs/stm3220g-eval/nettest/defconfig index 061c77ea53e15c54553d27bec5af90e5dc6a6ffe..a2f0466d3b9bf35ab180cdc8c818de84280c99ef 100644 --- a/configs/stm3220g-eval/nettest/defconfig +++ b/configs/stm3220g-eval/nettest/defconfig @@ -1195,7 +1195,7 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm3220g-eval/nsh/defconfig b/configs/stm3220g-eval/nsh/defconfig index fd7610f652cc344da997b9984f5f129024103304..d7743130a194debcebed079e79d8090a45e101b2 100644 --- a/configs/stm3220g-eval/nsh/defconfig +++ b/configs/stm3220g-eval/nsh/defconfig @@ -1422,7 +1422,7 @@ CONFIG_NSH_MAX_ROUNDTRIP=20 # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FLASH_ERASEALL is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_I2CTOOL is not set # CONFIG_SYSTEM_INSTALL is not set diff --git a/configs/stm3220g-eval/nsh2/defconfig b/configs/stm3220g-eval/nsh2/defconfig index 263355865c2789169e84f1ee6a0263c5f24cc31c..5565d734b72807e9e7fbfeae5276f6c6f1dd09e0 100644 --- a/configs/stm3220g-eval/nsh2/defconfig +++ b/configs/stm3220g-eval/nsh2/defconfig @@ -1438,7 +1438,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FLASH_ERASEALL is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set CONFIG_SYSTEM_I2CTOOL=y CONFIG_I2CTOOL_MINBUS=1 diff --git a/configs/stm3220g-eval/nxwm/defconfig b/configs/stm3220g-eval/nxwm/defconfig index 1ab3afe8326225ba3ddf6b4d279cbaf3d73da394..30457480d52a2326b84bc01a194b3b327e874358 100644 --- a/configs/stm3220g-eval/nxwm/defconfig +++ b/configs/stm3220g-eval/nxwm/defconfig @@ -1754,7 +1754,7 @@ CONFIG_NXWM_HEXCALCULATOR_FONTID=5 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_I2CTOOL is not set # CONFIG_SYSTEM_INSTALL is not set diff --git a/configs/stm3220g-eval/telnetd/defconfig b/configs/stm3220g-eval/telnetd/defconfig index 9e57584d8e913dbc18781bb4bff4bd2468e608b1..9e0ac7839fe5902153ed8ff62d32321918759800 100644 --- a/configs/stm3220g-eval/telnetd/defconfig +++ b/configs/stm3220g-eval/telnetd/defconfig @@ -1192,7 +1192,7 @@ CONFIG_NETUTILS_TELNETD=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm3240g-eval/dhcpd/defconfig b/configs/stm3240g-eval/dhcpd/defconfig index 368ea6cf041c303f83f6902d71feecfdc5bbc100..d83dbbbcc5bf5c2687f8bc5e861cba4c49bc56d9 100644 --- a/configs/stm3240g-eval/dhcpd/defconfig +++ b/configs/stm3240g-eval/dhcpd/defconfig @@ -1201,7 +1201,7 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm3240g-eval/discover/defconfig b/configs/stm3240g-eval/discover/defconfig index a6948166b70c9324d15093478b53ab310c185c41..126b6e8cc119558a7ae605d6bb560dc7436ea15d 100644 --- a/configs/stm3240g-eval/discover/defconfig +++ b/configs/stm3240g-eval/discover/defconfig @@ -1266,7 +1266,7 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_I2CTOOL is not set # CONFIG_SYSTEM_INSTALL is not set diff --git a/configs/stm3240g-eval/knxwm/defconfig b/configs/stm3240g-eval/knxwm/defconfig index 0c9c596c53f6e8644ac8ca884fb9d1f4d26c0185..68cd61dc901dbb0fc450ac39fa6835dd8a109655 100644 --- a/configs/stm3240g-eval/knxwm/defconfig +++ b/configs/stm3240g-eval/knxwm/defconfig @@ -1430,7 +1430,7 @@ CONFIG_NXWM_HEXCALCULATOR_FONTID=5 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_I2CTOOL is not set # CONFIG_SYSTEM_INSTALL is not set diff --git a/configs/stm3240g-eval/nettest/defconfig b/configs/stm3240g-eval/nettest/defconfig index 42672a45da38e8697516f366a2452015f8606e3a..76c0f2e2e30bdf5db1a5dfea26088951c02fc580 100644 --- a/configs/stm3240g-eval/nettest/defconfig +++ b/configs/stm3240g-eval/nettest/defconfig @@ -1199,7 +1199,7 @@ CONFIG_NETUTILS_NETLIB=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm3240g-eval/nsh/defconfig b/configs/stm3240g-eval/nsh/defconfig index 82ba6591df93eeac8590af65a71c981f4389dacf..159479c01ce45974d75d08d1ab14a17f27e7bbc4 100644 --- a/configs/stm3240g-eval/nsh/defconfig +++ b/configs/stm3240g-eval/nsh/defconfig @@ -1411,7 +1411,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set CONFIG_SYSTEM_I2CTOOL=y CONFIG_I2CTOOL_MINBUS=1 diff --git a/configs/stm3240g-eval/nsh2/defconfig b/configs/stm3240g-eval/nsh2/defconfig index 2d7a66a331941714fb22b855915f1b398c37c704..195f485d54e9c6701f4b38de8e371108b0a81da7 100644 --- a/configs/stm3240g-eval/nsh2/defconfig +++ b/configs/stm3240g-eval/nsh2/defconfig @@ -1442,7 +1442,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FLASH_ERASEALL is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set CONFIG_SYSTEM_I2CTOOL=y CONFIG_I2CTOOL_MINBUS=1 diff --git a/configs/stm3240g-eval/nxterm/defconfig b/configs/stm3240g-eval/nxterm/defconfig index 9c793c79c6ad89d3095a0505f6dd596ffdd95122..c432e138410e874730da1f789f446df974723b68 100644 --- a/configs/stm3240g-eval/nxterm/defconfig +++ b/configs/stm3240g-eval/nxterm/defconfig @@ -1541,7 +1541,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set CONFIG_SYSTEM_I2CTOOL=y CONFIG_I2CTOOL_MINBUS=1 diff --git a/configs/stm3240g-eval/nxwm/defconfig b/configs/stm3240g-eval/nxwm/defconfig index d12bd75e5399146e4bcf54182acd8419a3d8fcff..fdcaf161defd2fc782a4cb5a49ddce5b90f5beba 100644 --- a/configs/stm3240g-eval/nxwm/defconfig +++ b/configs/stm3240g-eval/nxwm/defconfig @@ -1759,7 +1759,7 @@ CONFIG_NXWM_HEXCALCULATOR_FONTID=5 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_I2CTOOL is not set # CONFIG_SYSTEM_INSTALL is not set diff --git a/configs/stm3240g-eval/telnetd/defconfig b/configs/stm3240g-eval/telnetd/defconfig index 7a6aa7a884542c94ff936d6b0750ae81b8ff6ee9..8ab255c4e84a7c8f419a3ff12a958b0e3161fb73 100644 --- a/configs/stm3240g-eval/telnetd/defconfig +++ b/configs/stm3240g-eval/telnetd/defconfig @@ -1196,7 +1196,7 @@ CONFIG_NETUTILS_TELNETD=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm3240g-eval/webserver/defconfig b/configs/stm3240g-eval/webserver/defconfig index 916ec6c8d05ea6b47cd406fd9ccac2ff1a3487b7..de6911b78588b741fb7c045cadb5cc748fcee629 100644 --- a/configs/stm3240g-eval/webserver/defconfig +++ b/configs/stm3240g-eval/webserver/defconfig @@ -1440,7 +1440,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_I2CTOOL is not set # CONFIG_SYSTEM_INSTALL is not set diff --git a/configs/stm3240g-eval/xmlrpc/defconfig b/configs/stm3240g-eval/xmlrpc/defconfig index 24cc0a0c4d2fe33a92e1f41043835bf1e5ba063a..558a3803eae467cbeef2d8f7f3bfe7ce14b62609 100644 --- a/configs/stm3240g-eval/xmlrpc/defconfig +++ b/configs/stm3240g-eval/xmlrpc/defconfig @@ -1261,7 +1261,7 @@ CONFIG_XMLRPC_STRINGSIZE=64 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_I2CTOOL is not set # CONFIG_SYSTEM_INSTALL is not set diff --git a/configs/stm32_tiny/README.txt b/configs/stm32_tiny/README.txt index 29a8cbb43ff14289277d3ad5c7cec02f7937aabd..7abbc4ccb0ef12d3f9b674c75662bc1a2b02a8b3 100644 --- a/configs/stm32_tiny/README.txt +++ b/configs/stm32_tiny/README.txt @@ -624,7 +624,7 @@ Where is one of the following: infinite loops and deadlocks: Debug output generates USB debug output which generatates USB debug output, etc. If you want USB debug output, you should consider enabling USB trace - (CONFIG_USBDEV_TRACE) and perhaps the USB monitor (CONFIG_SYSTEM_USBMONITOR). + (CONFIG_USBDEV_TRACE) and perhaps the USB monitor (CONFIG_USBMONITOR). See the usbnsh configuration below for more information on configuring USB trace output and the USB monitor. @@ -674,16 +674,16 @@ Where is one of the following: CONFIG_USBDEV_TRACE_NRECORDS=128 : Buffer 128 records in memory CONFIG_NSH_USBDEV_TRACE=n : No builtin tracing from NSH CONFIG_NSH_ARCHINIT=y : Automatically start the USB monitor - CONFIG_SYSTEM_USBMONITOR=y : Enable the USB monitor daemon - CONFIG_SYSTEM_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size - CONFIG_SYSTEM_USBMONITOR_PRIORITY=50 : USB monitor daemon priority - CONFIG_SYSTEM_USBMONITOR_INTERVAL=2 : Dump trace data every 2 seconds - - CONFIG_SYSTEM_USBMONITOR_TRACEINIT=y : Enable TRACE output - CONFIG_SYSTEM_USBMONITOR_TRACECLASS=y - CONFIG_SYSTEM_USBMONITOR_TRACETRANSFERS=y - CONFIG_SYSTEM_USBMONITOR_TRACECONTROLLER=y - CONFIG_SYSTEM_USBMONITOR_TRACEINTERRUPTS=y + CONFIG_USBMONITOR=y : Enable the USB monitor daemon + CONFIG_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size + CONFIG_USBMONITOR_PRIORITY=50 : USB monitor daemon priority + CONFIG_USBMONITOR_INTERVAL=2 : Dump trace data every 2 seconds + + CONFIG_USBMONITOR_TRACEINIT=y : Enable TRACE output + CONFIG_USBMONITOR_TRACECLASS=y + CONFIG_USBMONITOR_TRACETRANSFERS=y + CONFIG_USBMONITOR_TRACECONTROLLER=y + CONFIG_USBMONITOR_TRACEINTERRUPTS=y 5. By default, this project assumes that you are *NOT* using the DFU bootloader. diff --git a/configs/stm32_tiny/nsh/defconfig b/configs/stm32_tiny/nsh/defconfig index efa50a903f5a103590a60956033bbb0e2bb19e6d..33ccfb5562697a68f8b3acc318464bc4074458cf 100644 --- a/configs/stm32_tiny/nsh/defconfig +++ b/configs/stm32_tiny/nsh/defconfig @@ -1126,7 +1126,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm32_tiny/usbnsh/defconfig b/configs/stm32_tiny/usbnsh/defconfig index 847b090897a61a21fe4f2ea81a7e187c7941ff70..d5d2102a02c75b55f6105caa090895dfe3dbbe45 100644 --- a/configs/stm32_tiny/usbnsh/defconfig +++ b/configs/stm32_tiny/usbnsh/defconfig @@ -1143,7 +1143,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set @@ -1154,6 +1154,6 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set # CONFIG_SYSTEM_UBLOXMODEM is not set -# CONFIG_SYSTEM_USBMONITOR is not set +# CONFIG_USBMONITOR is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm32f103-minimum/README.txt b/configs/stm32f103-minimum/README.txt index edd0fc92e1a3b3b071416168c29bef487208827d..942f0458d600568feb0aab25f770ccfb94aba352 100644 --- a/configs/stm32f103-minimum/README.txt +++ b/configs/stm32f103-minimum/README.txt @@ -607,16 +607,16 @@ Where is one of the following: CONFIG_USBDEV_TRACE_NRECORDS=128 : Buffer 128 records in memory CONFIG_NSH_USBDEV_TRACE=n : No builtin tracing from NSH CONFIG_NSH_ARCHINIT=y : Automatically start the USB monitor - CONFIG_SYSTEM_USBMONITOR=y : Enable the USB monitor daemon - CONFIG_SYSTEM_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size - CONFIG_SYSTEM_USBMONITOR_PRIORITY=50 : USB monitor daemon priority - CONFIG_SYSTEM_USBMONITOR_INTERVAL=2 : Dump trace data every 2 seconds - - CONFIG_SYSTEM_USBMONITOR_TRACEINIT=y : Enable TRACE output - CONFIG_SYSTEM_USBMONITOR_TRACECLASS=y - CONFIG_SYSTEM_USBMONITOR_TRACETRANSFERS=y - CONFIG_SYSTEM_USBMONITOR_TRACECONTROLLER=y - CONFIG_SYSTEM_USBMONITOR_TRACEINTERRUPTS=y + CONFIG_USBMONITOR=y : Enable the USB monitor daemon + CONFIG_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size + CONFIG_USBMONITOR_PRIORITY=50 : USB monitor daemon priority + CONFIG_USBMONITOR_INTERVAL=2 : Dump trace data every 2 seconds + + CONFIG_USBMONITOR_TRACEINIT=y : Enable TRACE output + CONFIG_USBMONITOR_TRACECLASS=y + CONFIG_USBMONITOR_TRACETRANSFERS=y + CONFIG_USBMONITOR_TRACECONTROLLER=y + CONFIG_USBMONITOR_TRACEINTERRUPTS=y 5. By default, this project assumes that you are *NOT* using the DFU bootloader. diff --git a/configs/stm32f103-minimum/minnsh/defconfig b/configs/stm32f103-minimum/minnsh/defconfig index da3a0941ce3130216b7b9beef984a24eb10c0027..09b5db03bf424b9fa99a93922744586e3a019817 100644 --- a/configs/stm32f103-minimum/minnsh/defconfig +++ b/configs/stm32f103-minimum/minnsh/defconfig @@ -1046,7 +1046,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm32f103-minimum/nsh/defconfig b/configs/stm32f103-minimum/nsh/defconfig index ee5bcaeee3b5bf3f38841402916b5a8377df1a22..5b5fbf73fa482a334f049f25a797b042251e4fb7 100644 --- a/configs/stm32f103-minimum/nsh/defconfig +++ b/configs/stm32f103-minimum/nsh/defconfig @@ -1101,7 +1101,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm32f103-minimum/usbnsh/defconfig b/configs/stm32f103-minimum/usbnsh/defconfig index 9a0e98417776fdceacf2fb99de14082be3d19c62..b60882cbdbc6572575f4096f49df2269e98c614f 100644 --- a/configs/stm32f103-minimum/usbnsh/defconfig +++ b/configs/stm32f103-minimum/usbnsh/defconfig @@ -1143,7 +1143,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set @@ -1154,6 +1154,6 @@ CONFIG_READLINE_ECHO=y # CONFIG_READLINE_CMD_HISTORY is not set # CONFIG_SYSTEM_SUDOKU is not set # CONFIG_SYSTEM_UBLOXMODEM is not set -# CONFIG_SYSTEM_USBMONITOR is not set +# CONFIG_USBMONITOR is not set # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/stm32f3discovery/README.txt b/configs/stm32f3discovery/README.txt index 64eb13ba18bed67c242c4c5c1116f0fe630b67d3..8cb94aa2f70032c679913c5168204f9b2b331238 100644 --- a/configs/stm32f3discovery/README.txt +++ b/configs/stm32f3discovery/README.txt @@ -806,15 +806,15 @@ Where is one of the following: CONFIG_NSH_ARCHINIT=y : Automatically start the USB monitor Application Configuration -> System NSH Add-Ons: - CONFIG_SYSTEM_USBMONITOR=y : Enable the USB monitor daemon - CONFIG_SYSTEM_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size - CONFIG_SYSTEM_USBMONITOR_PRIORITY=50 : USB monitor daemon priority - CONFIG_SYSTEM_USBMONITOR_INTERVAL=1 : Dump trace data every second - CONFIG_SYSTEM_USBMONITOR_TRACEINIT=y : Enable TRACE output - CONFIG_SYSTEM_USBMONITOR_TRACECLASS=y - CONFIG_SYSTEM_USBMONITOR_TRACETRANSFERS=y - CONFIG_SYSTEM_USBMONITOR_TRACECONTROLLER=y - CONFIG_SYSTEM_USBMONITOR_TRACEINTERRUPTS=y + CONFIG_USBMONITOR=y : Enable the USB monitor daemon + CONFIG_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size + CONFIG_USBMONITOR_PRIORITY=50 : USB monitor daemon priority + CONFIG_USBMONITOR_INTERVAL=1 : Dump trace data every second + CONFIG_USBMONITOR_TRACEINIT=y : Enable TRACE output + CONFIG_USBMONITOR_TRACECLASS=y + CONFIG_USBMONITOR_TRACETRANSFERS=y + CONFIG_USBMONITOR_TRACECONTROLLER=y + CONFIG_USBMONITOR_TRACEINTERRUPTS=y NOTE: USB debug output also be enabled in this case. Both will appear on the serial SYSLOG output. However, the debug output will be diff --git a/configs/stm32f3discovery/nsh/defconfig b/configs/stm32f3discovery/nsh/defconfig index 4cb1dfd5e2091d71bc0bcedeb9b30fc0d5d1ff09..09e1c665ff5545c75bb722ae31983ccc77cae1ae 100644 --- a/configs/stm32f3discovery/nsh/defconfig +++ b/configs/stm32f3discovery/nsh/defconfig @@ -1172,7 +1172,7 @@ CONFIG_SYSTEM_CDCACM_DEVMINOR=0 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm32f3discovery/src/stm32_appinit.c b/configs/stm32f3discovery/src/stm32_appinit.c index 3d23db62969d10c60d783a748c6810b7de135796..c95837c9c52957a2294a383863efb86713f83951 100644 --- a/configs/stm32f3discovery/src/stm32_appinit.c +++ b/configs/stm32f3discovery/src/stm32_appinit.c @@ -46,8 +46,8 @@ #include -#ifdef CONFIG_SYSTEM_USBMONITOR -# include +#ifdef CONFIG_USBMONITOR +# include #endif #include "stm32.h" @@ -80,7 +80,7 @@ /* Check if we should enable the USB monitor before starting NSH */ -#if !defined(CONFIG_USBDEV_TRACE) || !defined(CONFIG_SYSTEM_USBMONITOR) +#if !defined(CONFIG_USBDEV_TRACE) || !defined(CONFIG_USBMONITOR) # undef HAVE_USBMONITOR #endif @@ -120,7 +120,7 @@ int board_app_initialize(uintptr_t arg) /* Start the USB Monitor */ - ret = usbmonitor_start(0, NULL); + ret = usbmonitor_start(); if (ret != OK) { syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); diff --git a/configs/stm32f3discovery/usbnsh/defconfig b/configs/stm32f3discovery/usbnsh/defconfig index 3d771a5f9972fa285c1cb498be7cb47ba83d88b4..bfc67b744d471958542462d291a2d3b3dd12712a 100644 --- a/configs/stm32f3discovery/usbnsh/defconfig +++ b/configs/stm32f3discovery/usbnsh/defconfig @@ -1187,7 +1187,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm32f411e-disco/nsh/defconfig b/configs/stm32f411e-disco/nsh/defconfig index 1845e9d48a6499ed6b784533d824be901cb03f5f..378f737c2cf5816c8dfb15bde7aece2013d5aee5 100644 --- a/configs/stm32f411e-disco/nsh/defconfig +++ b/configs/stm32f411e-disco/nsh/defconfig @@ -1106,7 +1106,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm32f429i-disco/README.txt b/configs/stm32f429i-disco/README.txt index d14134e068037f6e33e45fe6b5019122987f6711..5cbb0acfcab9606a481d0584561973584be9c403 100644 --- a/configs/stm32f429i-disco/README.txt +++ b/configs/stm32f429i-disco/README.txt @@ -733,7 +733,7 @@ Where is one of the following: infinite loops and deadlocks: Debug output generates USB debug output which generatates USB debug output, etc. If you want USB debug output, you should consider enabling USB trace - (CONFIG_USBDEV_TRACE) and perhaps the USB monitor (CONFIG_SYSTEM_USBMONITOR). + (CONFIG_USBDEV_TRACE) and perhaps the USB monitor (CONFIG_USBMONITOR). See the usbnsh configuration below for more information on configuring USB trace output and the USB monitor. diff --git a/configs/stm32f429i-disco/extflash/defconfig b/configs/stm32f429i-disco/extflash/defconfig index f4e687e9afb058a06c4166d0d8a1154f6acdd2e4..72fa8f02fdd48e14917fa59da5d8c8d3ccb95a51 100644 --- a/configs/stm32f429i-disco/extflash/defconfig +++ b/configs/stm32f429i-disco/extflash/defconfig @@ -1257,7 +1257,7 @@ CONFIG_PLATFORM_CONFIGDATA=y # CONFIG_SYSTEM_CUTERM is not set CONFIG_SYSTEM_FLASH_ERASEALL=y # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm32f429i-disco/lcd/defconfig b/configs/stm32f429i-disco/lcd/defconfig index cca650004b62aef768c6541618d91896d460936a..61403bc2974237e7c4925668115999ff0d00ba05 100644 --- a/configs/stm32f429i-disco/lcd/defconfig +++ b/configs/stm32f429i-disco/lcd/defconfig @@ -1300,7 +1300,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm32f429i-disco/ltdc/defconfig b/configs/stm32f429i-disco/ltdc/defconfig index 138dacd2e6a66cb67dc42e5c865600aca9c9e8bf..ac7f9e336f7fb97c0a3a3496419e9adbc0df529d 100644 --- a/configs/stm32f429i-disco/ltdc/defconfig +++ b/configs/stm32f429i-disco/ltdc/defconfig @@ -1349,7 +1349,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm32f429i-disco/nsh/defconfig b/configs/stm32f429i-disco/nsh/defconfig index 14893669401f1f44037a9bb4e9abe1e9f3686eed..fd8f1dffed90d0c631a55c69a340d35c40c6c374 100644 --- a/configs/stm32f429i-disco/nsh/defconfig +++ b/configs/stm32f429i-disco/nsh/defconfig @@ -1154,7 +1154,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm32f429i-disco/src/stm32_appinit.c b/configs/stm32f429i-disco/src/stm32_appinit.c index c7f1d4fb76597f83b95d2d49e000db1e76d57929..415884fa5bf46f64f4c8d2aaffbb7d27572648e4 100644 --- a/configs/stm32f429i-disco/src/stm32_appinit.c +++ b/configs/stm32f429i-disco/src/stm32_appinit.c @@ -55,8 +55,8 @@ # include #endif -#ifdef CONFIG_SYSTEM_USBMONITOR -# include +#ifdef CONFIG_USBMONITOR +# include #endif #ifndef CONFIG_STM32F429I_DISCO_FLASH_MINOR @@ -109,7 +109,7 @@ /* Check if we should enable the USB monitor before starting NSH */ -#if !defined(CONFIG_USBDEV_TRACE) || !defined(CONFIG_SYSTEM_USBMONITOR) +#if !defined(CONFIG_USBDEV_TRACE) || !defined(CONFIG_USBMONITOR) # undef HAVE_USBMONITOR #endif @@ -371,7 +371,7 @@ int board_app_initialize(uintptr_t arg) #ifdef HAVE_USBMONITOR /* Start the USB Monitor */ - ret = usbmonitor_start(0, NULL); + ret = usbmonitor_start(); if (ret != OK) { syslog(LOG_ERR, "ERROR: Failed to start USB monitor: %d\n", ret); diff --git a/configs/stm32f429i-disco/usbmsc/defconfig b/configs/stm32f429i-disco/usbmsc/defconfig index c041a1a207dccd25d2cdc7a8a452a543c9865d47..a2ef06d9caa7c0e7161b0965bd3f09354c46e1c5 100644 --- a/configs/stm32f429i-disco/usbmsc/defconfig +++ b/configs/stm32f429i-disco/usbmsc/defconfig @@ -1199,7 +1199,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm32f429i-disco/usbnsh/defconfig b/configs/stm32f429i-disco/usbnsh/defconfig index 9b72f2bf72be00d599a8eed7fc6fd36580ec3936..a25d95b5095b2bda4aea705e6f5727907e8caeca 100644 --- a/configs/stm32f429i-disco/usbnsh/defconfig +++ b/configs/stm32f429i-disco/usbnsh/defconfig @@ -1218,7 +1218,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set CONFIG_SYSTEM_RAMTEST=y diff --git a/configs/stm32f4discovery/README.txt b/configs/stm32f4discovery/README.txt index e0c912d16484b9bdba1e53af234c4cd70d8d112e..430f78c913472f29a86a175185a534ec592f52c4 100644 --- a/configs/stm32f4discovery/README.txt +++ b/configs/stm32f4discovery/README.txt @@ -1659,7 +1659,7 @@ Where is one of the following: infinite loops and deadlocks: Debug output generates USB debug output which generatates USB debug output, etc. If you want USB debug output, you should consider enabling USB trace - (CONFIG_USBDEV_TRACE) and perhaps the USB monitor (CONFIG_SYSTEM_USBMONITOR). + (CONFIG_USBDEV_TRACE) and perhaps the USB monitor (CONFIG_USBMONITOR). See the usbnsh configuration below for more information on configuring USB trace output and the USB monitor. @@ -2002,16 +2002,16 @@ Where is one of the following: CONFIG_USBDEV_TRACE_NRECORDS=128 : Buffer 128 records in memory CONFIG_NSH_USBDEV_TRACE=n : No builtin tracing from NSH CONFIG_NSH_ARCHINIT=y : Automatically start the USB monitor - CONFIG_SYSTEM_USBMONITOR=y : Enable the USB monitor daemon - CONFIG_SYSTEM_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size - CONFIG_SYSTEM_USBMONITOR_PRIORITY=50 : USB monitor daemon priority - CONFIG_SYSTEM_USBMONITOR_INTERVAL=2 : Dump trace data every 2 seconds - - CONFIG_SYSTEM_USBMONITOR_TRACEINIT=y : Enable TRACE output - CONFIG_SYSTEM_USBMONITOR_TRACECLASS=y - CONFIG_SYSTEM_USBMONITOR_TRACETRANSFERS=y - CONFIG_SYSTEM_USBMONITOR_TRACECONTROLLER=y - CONFIG_SYSTEM_USBMONITOR_TRACEINTERRUPTS=y + CONFIG_USBMONITOR=y : Enable the USB monitor daemon + CONFIG_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size + CONFIG_USBMONITOR_PRIORITY=50 : USB monitor daemon priority + CONFIG_USBMONITOR_INTERVAL=2 : Dump trace data every 2 seconds + + CONFIG_USBMONITOR_TRACEINIT=y : Enable TRACE output + CONFIG_USBMONITOR_TRACECLASS=y + CONFIG_USBMONITOR_TRACETRANSFERS=y + CONFIG_USBMONITOR_TRACECONTROLLER=y + CONFIG_USBMONITOR_TRACEINTERRUPTS=y 5. By default, this project assumes that you are *NOT* using the DFU bootloader. diff --git a/configs/stm32f4discovery/cxxtest/defconfig b/configs/stm32f4discovery/cxxtest/defconfig index ccb07593a897e580360552ed5a33f729f1d9f070..70f37d0b3293763634693911698bff3e94bbe6c9 100644 --- a/configs/stm32f4discovery/cxxtest/defconfig +++ b/configs/stm32f4discovery/cxxtest/defconfig @@ -1040,7 +1040,7 @@ CONFIG_EXAMPLES_CXXTEST_CXXINITIALIZE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm32f4discovery/elf/defconfig b/configs/stm32f4discovery/elf/defconfig index fcf650368eca86cc9cf072558768413092e1092d..8bdd64b1b25c0a9286cde7eedd6e6cfcb67253e2 100644 --- a/configs/stm32f4discovery/elf/defconfig +++ b/configs/stm32f4discovery/elf/defconfig @@ -1060,7 +1060,7 @@ CONFIG_EXAMPLES_ELF_DEVPATH="/dev/ram0" # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm32f4discovery/ipv6/defconfig b/configs/stm32f4discovery/ipv6/defconfig index 8e11faeb129763e36088fc9d3a52821b6fa4733c..397b216393cbcf52a14a9bb45f84040293875cec 100644 --- a/configs/stm32f4discovery/ipv6/defconfig +++ b/configs/stm32f4discovery/ipv6/defconfig @@ -1455,7 +1455,7 @@ CONFIG_NSH_MAX_ROUNDTRIP=20 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/stm32f4discovery/kostest/defconfig b/configs/stm32f4discovery/kostest/defconfig index 1d1f1c310ce79de651f5c07f836c3076815fb735..6219fe09a9c7e905589fc3ab0baa61dea5f658ad 100644 --- a/configs/stm32f4discovery/kostest/defconfig +++ b/configs/stm32f4discovery/kostest/defconfig @@ -1041,7 +1041,7 @@ CONFIG_EXAMPLES_OSTEST_WAITRESULT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm32f4discovery/netnsh/defconfig b/configs/stm32f4discovery/netnsh/defconfig index 0ba6e716798825492e157250a2ae54c6c5ff8a01..2e78007b4bffdaaeb74b01d652fc2923152dfcc6 100644 --- a/configs/stm32f4discovery/netnsh/defconfig +++ b/configs/stm32f4discovery/netnsh/defconfig @@ -1460,7 +1460,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_MDIO is not set diff --git a/configs/stm32f4discovery/nsh/defconfig b/configs/stm32f4discovery/nsh/defconfig index 9db07e2797f3f0379ad4b07b4a5390a4bcb8da6e..7fa1c99d9e17ecac7979938f39a7f124897e0e5d 100644 --- a/configs/stm32f4discovery/nsh/defconfig +++ b/configs/stm32f4discovery/nsh/defconfig @@ -1173,7 +1173,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm32f4discovery/nxlines/defconfig b/configs/stm32f4discovery/nxlines/defconfig index 5c1a2c84387e45d23177ac56190ec3a38b59ed15..ede193ec75c4fd64f38e6e685d1ea9e2f26726dc 100644 --- a/configs/stm32f4discovery/nxlines/defconfig +++ b/configs/stm32f4discovery/nxlines/defconfig @@ -1301,7 +1301,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm32f4discovery/pm/defconfig b/configs/stm32f4discovery/pm/defconfig index 80912483b2d5832beb218bc4116b144da45afe75..b58f62296b6dac791ad3c45ee86848a7c008e835 100644 --- a/configs/stm32f4discovery/pm/defconfig +++ b/configs/stm32f4discovery/pm/defconfig @@ -1197,7 +1197,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm32f4discovery/posix_spawn/defconfig b/configs/stm32f4discovery/posix_spawn/defconfig index 54d5abeea9ae9c29635480bb661ab5c0bf90d1f4..a896c3140017d78bbb7b3791bb296652aa33e0a6 100644 --- a/configs/stm32f4discovery/posix_spawn/defconfig +++ b/configs/stm32f4discovery/posix_spawn/defconfig @@ -1062,7 +1062,7 @@ CONFIG_EXAMPLES_POSIXSPAWN_DEVPATH="/dev/ram0" # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm32f4discovery/rgbled/defconfig b/configs/stm32f4discovery/rgbled/defconfig index d7f39c44ce3865944bd66bdc70178b37673abc1d..10e9ac486d065a8268cacc8c2fa7e7e12f32acb7 100644 --- a/configs/stm32f4discovery/rgbled/defconfig +++ b/configs/stm32f4discovery/rgbled/defconfig @@ -1214,7 +1214,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm32f4discovery/src/stm32_bringup.c b/configs/stm32f4discovery/src/stm32_bringup.c index d958042ebda16bd22b8e9f97e8b180080fdcb6c1..a6aec33f8570b33072fa9eaa2ce477ba07c23cf7 100644 --- a/configs/stm32f4discovery/src/stm32_bringup.c +++ b/configs/stm32f4discovery/src/stm32_bringup.c @@ -45,8 +45,8 @@ #include #include -#ifdef CONFIG_SYSTEM_USBMONITOR -# include +#ifdef CONFIG_USBMONITOR +# include #endif #include @@ -151,7 +151,7 @@ int stm32_bringup(void) #ifdef HAVE_USBMONITOR /* Start the USB Monitor */ - ret = usbmonitor_start(0, NULL); + ret = usbmonitor_start(); if (ret != OK) { uerr("ERROR: Failed to start USB monitor: %d\n", ret); diff --git a/configs/stm32f4discovery/src/stm32f4discovery.h b/configs/stm32f4discovery/src/stm32f4discovery.h index 3d3400920b44983ab08c75155edf50d324d117a4..bc2f7f98bdc6a9d7640c8b9ec92629ea0942dbd5 100644 --- a/configs/stm32f4discovery/src/stm32f4discovery.h +++ b/configs/stm32f4discovery/src/stm32f4discovery.h @@ -98,7 +98,7 @@ /* Check if we should enable the USB monitor before starting NSH */ -#if !defined(CONFIG_USBDEV_TRACE) || !defined(CONFIG_SYSTEM_USBMONITOR) +#if !defined(CONFIG_USBDEV_TRACE) || !defined(CONFIG_USBMONITOR) # undef HAVE_USBMONITOR #endif diff --git a/configs/stm32f4discovery/uavcan/defconfig b/configs/stm32f4discovery/uavcan/defconfig index fcdac447bc7839c965534ce5e0fd766cfce0b57e..11043832344d1c48b117093a44a55dd7dc621776 100644 --- a/configs/stm32f4discovery/uavcan/defconfig +++ b/configs/stm32f4discovery/uavcan/defconfig @@ -1008,7 +1008,7 @@ CONFIG_EXAMPLES_UAVCAN_NODE_NAME="org.nuttx.apps.examples.uavcan" # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm32f4discovery/usbnsh/defconfig b/configs/stm32f4discovery/usbnsh/defconfig index b85e4d48690da423af30da878de8d94f1186f134..405bdea939e8956e961eef4a647b05530fe3c485 100644 --- a/configs/stm32f4discovery/usbnsh/defconfig +++ b/configs/stm32f4discovery/usbnsh/defconfig @@ -1224,7 +1224,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm32f4discovery/winbuild/defconfig b/configs/stm32f4discovery/winbuild/defconfig index e52bc101ae301bba7283aff37ca4557c8067ea2d..dcdefd1af5c539ebd751403e6db16ee2d047efd7 100644 --- a/configs/stm32f4discovery/winbuild/defconfig +++ b/configs/stm32f4discovery/winbuild/defconfig @@ -934,7 +934,7 @@ CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_FSUTILS_INIFILE is not set # CONFIG_SYSTEM_RAMTEST is not set # CONFIG_READLINE_HAVE_EXTMATCH is not set diff --git a/configs/stm32f746-ws/nsh/defconfig b/configs/stm32f746-ws/nsh/defconfig index 88c143a392f4aa6f1e9434531a05d8f0423d5559..8eaa8c035797d14c7073fc1c394598a1e6434e40 100644 --- a/configs/stm32f746-ws/nsh/defconfig +++ b/configs/stm32f746-ws/nsh/defconfig @@ -1059,7 +1059,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set CONFIG_SYSTEM_I2CTOOL=y CONFIG_I2CTOOL_MINBUS=1 diff --git a/configs/stm32f746g-disco/README.txt b/configs/stm32f746g-disco/README.txt index 48ba63ec41a40b6c1af878b60c7c448045e307ef..66dfb79ba4f86ebe882fc7c2c953d0b8cc23527a 100644 --- a/configs/stm32f746g-disco/README.txt +++ b/configs/stm32f746g-disco/README.txt @@ -527,136 +527,6 @@ Configurations Configuration Directories ------------------------- - kostest: - ------- - This is identical to the nsh configuration below except that NuttX is - built as a kernel-mode, monolithic module and the user applications are - built separately. Is is recommended to use a special make command; - not just 'make' but make with the following two arguments: - - make pass1 pass2 - - In the normal case (just 'make'), make will attempt to build both user- - and kernel-mode blobs more or less interleaved. This actual works! - However, for me it is very confusing so I prefer the above make command: - Make the user-space binaries first (pass1), then make the kernel-space - binaries (pass2) - - NOTES: - - 1. At the end of the build, there will be several files in the top-level - NuttX build directory: - - PASS1: - nuttx_user.elf - The pass1 user-space ELF file - nuttx_user.hex - The pass1 Intel HEX format file (selected in defconfig) - User.map - Symbols in the user-space ELF file - - PASS2: - nuttx - The pass2 kernel-space ELF file - nuttx.hex - The pass2 Intel HEX file (selected in defconfig) - System.map - Symbols in the kernel-space ELF file - - 2. Combining .hex files. If you plan to use the STM32 ST-Link Utility to - load the .hex files into FLASH, then you need to combine the two hex - files into a single .hex file. Here is how you can do that. - - a. The 'tail' of the nuttx.hex file should look something like this - (with my comments added): - - $ tail nuttx.hex - # 00, data records - ... - :10 9DC0 00 01000000000800006400020100001F0004 - :10 9DD0 00 3B005A0078009700B500D400F300110151 - :08 9DE0 00 30014E016D0100008D - # 05, Start Linear Address Record - :04 0000 05 0800 0419 D2 - # 01, End Of File record - :00 0000 01 FF - - Use an editor such as vi to remove the 05 and 01 records. - - b. The 'head' of the nuttx_user.hex file should look something like - this (again with my comments added): - - $ head nuttx_user.hex - # 04, Extended Linear Address Record - :02 0000 04 0801 F1 - # 00, data records - :10 8000 00 BD89 01084C800108C8110208D01102087E - :10 8010 00 0010 00201C1000201C1000203C16002026 - :10 8020 00 4D80 01085D80010869800108ED83010829 - ... - - Nothing needs to be done here. The nuttx_user.hex file should - be fine. - - c. Combine the edited nuttx.hex and un-edited nuttx_user.hex - file to produce a single combined hex file: - - $ cat nuttx.hex nuttx_user.hex >combined.hex - - Then use the combined.hex file with the STM32 ST-Link tool. The - mbed interface does not seem to except .hex files, but you can - also convert the .hex file to binary with this command: - - arm-none-eabi-objcopy.exe -I ihex -O binary combined.hex combined.bin - - If you do this a lot, you will probably want to invest a little time - to develop a tool to automate these steps. - - netnsh: - ------ - This is a NetShell (NSH) very similar to the nsh configuration described - below. It differs in that it has networking enabled. - - NOTES: - - 1. Both IPv4 and IPv6 protocoals are enabled. Fixed IP addresses are - used. The default configurationi target has these IP address: - - IPv4: 10.0.0.2 - IPv6: fc00::2 - - These are, of course, easily changes by reconfiguring via 'make - menuconfig' - - 2. UDP, TCIP/IP, ARP, ICMP, and ICMPv6 are also enabled. - - 3. NSH offers several network oriented commands such as: ipconfig, - ifup, ifdown, ping, and ping6. - - 4. Telnet sessions are supported. You can start a Telnet session from - any host on the network using a command like: - - $ telnet 10.0.0.2 - Trying 10.0.0.2... - Connected to 10.0.0.2. - Escape character is '^]'. - - NuttShell (NSH) NuttX-7.10 - nsh> help - help usage: help [-v] [] - - [ dd hexdump mb ping6 sleep - ? echo ifconfig mkdir ps test - break exec ifdown mkfifo pwd true - cat exit ifup mh rm uname - cd false kill mv rmdir unset - cp free losetup mw set usleep - cmp help ls ping sh xd - - Builtin Apps: - nsh> - - Under either Linux or Cygwin - - 5. The PHY address is either 0 or 1, depending on the state of the - LAN8720 RXER/PHYAD0 when the hardware is reset. That connects to the - STM32 F7 via PG2. PG2 is not controlled but appears to result in a - PHY address of 0. - nsh: --- Configures the NuttShell (NSH) located at apps/examples/nsh. The diff --git a/configs/stm32f746g-disco/nsh/defconfig b/configs/stm32f746g-disco/nsh/defconfig index 73f36d894f9a67e6dade475750d1a676a750b3d5..3f71f4a39e874b75d64a064da0cb16b1f85cb325 100644 --- a/configs/stm32f746g-disco/nsh/defconfig +++ b/configs/stm32f746g-disco/nsh/defconfig @@ -1015,7 +1015,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm32l476vg-disco/include/board.h b/configs/stm32l476vg-disco/include/board.h index c05f74a7e5d290affea31bdfbba55ac5d5358a78..ee28c35a06e67a0e645eb86bca6340e6529e57df 100644 --- a/configs/stm32l476vg-disco/include/board.h +++ b/configs/stm32l476vg-disco/include/board.h @@ -271,7 +271,7 @@ #define BUTTON_CENTER_BIT (1 << BUTTON_CENTER) #define BUTTON_LEFT_BIT (1 << BUTTON_LEFT) #define BUTTON_DOWN_BIT (1 << BUTTON_DOWN) -#define BUTTON_TIGHT_BIT (1 << BUTTON_RIGHT) +#define BUTTON_RIGHT_BIT (1 << BUTTON_RIGHT) #define BUTTON_UP_BIT (1 << BUTTON_UP) /************************************************************************************ diff --git a/configs/stm32l476vg-disco/nsh/defconfig b/configs/stm32l476vg-disco/nsh/defconfig index 7bb5a7b16c17695a69c0339981f905110fb60996..9d451b5fa29fc1bc822289eefa62ced2fbde17a9 100644 --- a/configs/stm32l476vg-disco/nsh/defconfig +++ b/configs/stm32l476vg-disco/nsh/defconfig @@ -1085,7 +1085,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FLASH_ERASEALL is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm32ldiscovery/nsh/defconfig b/configs/stm32ldiscovery/nsh/defconfig index 17293ae1cb7caed979bf79fde6910922c71acfa0..2e13a6c77d61e4ce3dab9de43249369f4b323224 100644 --- a/configs/stm32ldiscovery/nsh/defconfig +++ b/configs/stm32ldiscovery/nsh/defconfig @@ -1069,7 +1069,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/stm32vldiscovery/nsh/defconfig b/configs/stm32vldiscovery/nsh/defconfig index c40099da6296d22ab82337a3aaad6d47bd07afda..588a4f9703faf5908d450663de9a13c6250a4d5f 100644 --- a/configs/stm32vldiscovery/nsh/defconfig +++ b/configs/stm32vldiscovery/nsh/defconfig @@ -1124,7 +1124,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sure-pic32mx/README.txt b/configs/sure-pic32mx/README.txt index da415a98055d9ae985bcbca7f2a46e4295975c60..07c89ad9d3704e02b50c2a9f193d24fb13dd1cec 100644 --- a/configs/sure-pic32mx/README.txt +++ b/configs/sure-pic32mx/README.txt @@ -882,15 +882,15 @@ Where is one of the following: CONFIG_NSH_ARCHINIT=y : Automatically start the USB monitor Application Configuration -> System NSH Add-Ons: - CONFIG_SYSTEM_USBMONITOR=y : Enable the USB monitor daemon - CONFIG_SYSTEM_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size - CONFIG_SYSTEM_USBMONITOR_PRIORITY=50 : USB monitor daemon priority - CONFIG_SYSTEM_USBMONITOR_INTERVAL=1 : Dump trace data every second - CONFIG_SYSTEM_USBMONITOR_TRACEINIT=y : Enable TRACE output - CONFIG_SYSTEM_USBMONITOR_TRACECLASS=y - CONFIG_SYSTEM_USBMONITOR_TRACETRANSFERS=y - CONFIG_SYSTEM_USBMONITOR_TRACECONTROLLER=y - CONFIG_SYSTEM_USBMONITOR_TRACEINTERRUPTS=y + CONFIG_USBMONITOR=y : Enable the USB monitor daemon + CONFIG_USBMONITOR_STACKSIZE=2048 : USB monitor daemon stack size + CONFIG_USBMONITOR_PRIORITY=50 : USB monitor daemon priority + CONFIG_USBMONITOR_INTERVAL=1 : Dump trace data every second + CONFIG_USBMONITOR_TRACEINIT=y : Enable TRACE output + CONFIG_USBMONITOR_TRACECLASS=y + CONFIG_USBMONITOR_TRACETRANSFERS=y + CONFIG_USBMONITOR_TRACECONTROLLER=y + CONFIG_USBMONITOR_TRACEINTERRUPTS=y NOTE: USB debug output also be enabled in this case. Both will appear on the serial SYSLOG output. However, the debug output will be diff --git a/configs/sure-pic32mx/nsh/defconfig b/configs/sure-pic32mx/nsh/defconfig index 8219ec829f89eb05ff4593f03a3c3b4b58802367..271065aa30fffeca3b9cfa634ccb5e6c7e43c8df 100644 --- a/configs/sure-pic32mx/nsh/defconfig +++ b/configs/sure-pic32mx/nsh/defconfig @@ -318,6 +318,8 @@ CONFIG_RAM_SIZE=32768 # CONFIG_ARCH_BOARD_SUREPIC32MX=y # CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD_CUSTOM_DIR="configs/dummy" +CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y CONFIG_ARCH_BOARD="sure-pic32mx" # @@ -328,13 +330,13 @@ CONFIG_ARCH_LEDS=y CONFIG_ARCH_HAVE_BUTTONS=y # CONFIG_ARCH_BUTTONS is not set CONFIG_ARCH_HAVE_IRQBUTTONS=y -CONFIG_NSH_MMCSDMINOR=0 # # Board-Specific Options # CONFIG_ARCH_DBDP11215=y # CONFIG_ARCH_DBDP11212 is not set +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set @@ -479,7 +481,12 @@ CONFIG_DEV_NULL=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -860,6 +867,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 # # Configure Command Options @@ -900,7 +908,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/sure-pic32mx/src/pic32mx_appinit.c b/configs/sure-pic32mx/src/pic32mx_appinit.c index ef09c7641c93f37a2ca53047fb2cb27f213ebf85..ae36428317f8cc08b7470b9f8bb06495b288b244 100644 --- a/configs/sure-pic32mx/src/pic32mx_appinit.c +++ b/configs/sure-pic32mx/src/pic32mx_appinit.c @@ -51,8 +51,8 @@ #include #include -#ifdef CONFIG_SYSTEM_USBMONITOR -# include +#ifdef CONFIG_USBMONITOR +# include #endif #include "pic32mx.h" @@ -152,7 +152,7 @@ /* Check if we should enable the USB monitor before starting NSH */ -#if !defined(CONFIG_USBDEV_TRACE) || !defined(CONFIG_SYSTEM_USBMONITOR) +#if !defined(CONFIG_USBDEV_TRACE) || !defined(CONFIG_USBMONITOR) # undef NSH_HAVE_USBMONITOR #endif @@ -415,7 +415,7 @@ int board_app_initialize(uintptr_t arg) { /* Start the USB Monitor */ - ret = usbmonitor_start(0, NULL); + ret = usbmonitor_start(); } #endif diff --git a/configs/sure-pic32mx/usbnsh/defconfig b/configs/sure-pic32mx/usbnsh/defconfig index 3bf95a77509e38564d8b5a42c9ab3493f4b600e4..ba6b357806ef201076d239b1880ecaba0dd17a70 100644 --- a/configs/sure-pic32mx/usbnsh/defconfig +++ b/configs/sure-pic32mx/usbnsh/defconfig @@ -319,6 +319,8 @@ CONFIG_RAM_SIZE=32768 # CONFIG_ARCH_BOARD_SUREPIC32MX=y # CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD_CUSTOM_DIR="configs/dummy" +CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y CONFIG_ARCH_BOARD="sure-pic32mx" # @@ -329,13 +331,13 @@ CONFIG_ARCH_LEDS=y CONFIG_ARCH_HAVE_BUTTONS=y # CONFIG_ARCH_BUTTONS is not set CONFIG_ARCH_HAVE_IRQBUTTONS=y -CONFIG_NSH_MMCSDMINOR=0 # # Board-Specific Options # CONFIG_ARCH_DBDP11215=y # CONFIG_ARCH_DBDP11212 is not set +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set CONFIG_BOARDCTL_USBDEVCTRL=y @@ -481,7 +483,12 @@ CONFIG_DEV_NULL=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -902,6 +909,7 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 # # Configure Command Options @@ -944,7 +952,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/teensy-2.0/hello/defconfig b/configs/teensy-2.0/hello/defconfig index 01eeae917e3e95b121e9d05ce115ec50132b8d2a..9442cd2b0918eac2d51d2b1f374f8520fef93544 100644 --- a/configs/teensy-2.0/hello/defconfig +++ b/configs/teensy-2.0/hello/defconfig @@ -583,7 +583,7 @@ CONFIG_EXAMPLES_HELLO_STACKSIZE=2048 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_FSUTILS_INIFILE is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/teensy-2.0/nsh/defconfig b/configs/teensy-2.0/nsh/defconfig index b1bbef7702892fab64f512d7a50f2586b767c53a..125663eb913f25f604c921e59d29a2a915f1e70a 100644 --- a/configs/teensy-2.0/nsh/defconfig +++ b/configs/teensy-2.0/nsh/defconfig @@ -678,7 +678,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_FSUTILS_INIFILE is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/teensy-2.0/usbmsc/defconfig b/configs/teensy-2.0/usbmsc/defconfig index 5facac91d5cf7fa21757f3c57f75c0e1a5a4e252..1d9b27f4c3a1fc3753b5eff05aec31b881762e9c 100644 --- a/configs/teensy-2.0/usbmsc/defconfig +++ b/configs/teensy-2.0/usbmsc/defconfig @@ -660,7 +660,7 @@ CONFIG_LIB_SENDFILE_BUFSIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_FSUTILS_INIFILE is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/teensy-3.x/nsh/defconfig b/configs/teensy-3.x/nsh/defconfig index cc089e31f510c44619363c7f9ef6bfff3b07c791..7698ce06960be84f407b25d986adbb0487768586 100644 --- a/configs/teensy-3.x/nsh/defconfig +++ b/configs/teensy-3.x/nsh/defconfig @@ -878,7 +878,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/teensy-3.x/src/k20_autoleds.c b/configs/teensy-3.x/src/k20_autoleds.c index 67ce3776a3003f55e3e3080d0d0b0b9b9a544970..7682bab7f52b531d08b3319a9b0c810153e438c2 100644 --- a/configs/teensy-3.x/src/k20_autoleds.c +++ b/configs/teensy-3.x/src/k20_autoleds.c @@ -48,18 +48,6 @@ #ifdef CONFIG_ARCH_LEDS -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Private Functions - ****************************************************************************/ - /**************************************************************************** * Public Functions ****************************************************************************/ diff --git a/configs/teensy-3.x/usbnsh/defconfig b/configs/teensy-3.x/usbnsh/defconfig index 41fb535e7a4c2cfd5b8621db9c946b63b7f833ab..d214df33c5b40b0c3ea79454f5175174800f26c9 100644 --- a/configs/teensy-3.x/usbnsh/defconfig +++ b/configs/teensy-3.x/usbnsh/defconfig @@ -939,7 +939,7 @@ CONFIG_SYSTEM_CDCACM_DEVMINOR=0 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set CONFIG_SYSTEM_HEXED=y CONFIG_SYSTEM_HEXED_STACKSIZE=2048 CONFIG_SYSTEM_HEXED_PRIORITY=100 @@ -956,14 +956,14 @@ CONFIG_READLINE_CMD_HISTORY_LINELEN=80 CONFIG_READLINE_CMD_HISTORY_LEN=16 # CONFIG_SYSTEM_SUDOKU is not set # CONFIG_SYSTEM_UBLOXMODEM is not set -CONFIG_SYSTEM_USBMONITOR=y -CONFIG_SYSTEM_USBMONITOR_STACKSIZE=2048 -CONFIG_SYSTEM_USBMONITOR_PRIORITY=50 -CONFIG_SYSTEM_USBMONITOR_INTERVAL=2 -CONFIG_SYSTEM_USBMONITOR_TRACEINIT=y -CONFIG_SYSTEM_USBMONITOR_TRACECLASS=y -CONFIG_SYSTEM_USBMONITOR_TRACETRANSFERS=y -CONFIG_SYSTEM_USBMONITOR_TRACECONTROLLER=y -CONFIG_SYSTEM_USBMONITOR_TRACEINTERRUPTS=y +CONFIG_USBMONITOR=y +CONFIG_USBMONITOR_STACKSIZE=2048 +CONFIG_USBMONITOR_PRIORITY=50 +CONFIG_USBMONITOR_INTERVAL=2 +CONFIG_USBMONITOR_TRACEINIT=y +CONFIG_USBMONITOR_TRACECLASS=y +CONFIG_USBMONITOR_TRACETRANSFERS=y +CONFIG_USBMONITOR_TRACECONTROLLER=y +CONFIG_USBMONITOR_TRACEINTERRUPTS=y # CONFIG_SYSTEM_VI is not set # CONFIG_SYSTEM_ZMODEM is not set diff --git a/configs/teensy-lc/nsh/defconfig b/configs/teensy-lc/nsh/defconfig index 73ad8e56346a29ffc256f1ba05a6a0f9a696969d..9954cea330081551c685fc9c2426782c41056920 100644 --- a/configs/teensy-lc/nsh/defconfig +++ b/configs/teensy-lc/nsh/defconfig @@ -866,7 +866,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/tm4c123g-launchpad/nsh/defconfig b/configs/tm4c123g-launchpad/nsh/defconfig index 0a6233316e2836513363d31f7bfc0b51e1e5a3e2..34f15d30638ad0aea901a42e96ec45254ade66f0 100644 --- a/configs/tm4c123g-launchpad/nsh/defconfig +++ b/configs/tm4c123g-launchpad/nsh/defconfig @@ -902,7 +902,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/tm4c1294-launchpad/ipv6/defconfig b/configs/tm4c1294-launchpad/ipv6/defconfig index 47b86bf68c031c13f09cd0a0038efb3c8cbcf6dc..4676156316d131d5b744f2ea482eca7c78d659bf 100644 --- a/configs/tm4c1294-launchpad/ipv6/defconfig +++ b/configs/tm4c1294-launchpad/ipv6/defconfig @@ -1125,7 +1125,7 @@ CONFIG_NSH_MAX_ROUNDTRIP=20 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set CONFIG_SYSTEM_I2CTOOL=y CONFIG_I2CTOOL_MINBUS=6 diff --git a/configs/tm4c1294-launchpad/nsh/defconfig b/configs/tm4c1294-launchpad/nsh/defconfig index 15a4e83331880b335bef3e6fe769c9184a8b9912..8457971387b83053e0f3547ffae7680070773074 100644 --- a/configs/tm4c1294-launchpad/nsh/defconfig +++ b/configs/tm4c1294-launchpad/nsh/defconfig @@ -1126,7 +1126,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set CONFIG_SYSTEM_I2CTOOL=y CONFIG_I2CTOOL_MINBUS=6 diff --git a/configs/twr-k60n512/include/board.h b/configs/twr-k60n512/include/board.h index 92c6dce940483dc7cae38c3dc4c62fd94efa2563..ea464c0d439ec572d4083401bfbacb335539c4cf 100644 --- a/configs/twr-k60n512/include/board.h +++ b/configs/twr-k60n512/include/board.h @@ -154,8 +154,8 @@ #define BUTTON_SW1 0 #define BUTTON_SW2 1 -#define BUTTON_SW1_BIT (1 << BUTTON_WAKEUP) -#define BUTTON_SW2_BIT (1 << BUTTON_TAMPER) +#define BUTTON_SW1_BIT (1 << BUTTON_SW1) +#define BUTTON_SW2_BIT (1 << BUTTON_SW2) /* Alternative pin resolution *******************************************************/ /* If there are alternative configurations for various pins in the diff --git a/configs/twr-k60n512/nsh/defconfig b/configs/twr-k60n512/nsh/defconfig index 65e1a1a01cef6a808a8501aeddb50f4bc5004398..7a495c00e6027590c4456cd2957af864d417d729 100644 --- a/configs/twr-k60n512/nsh/defconfig +++ b/configs/twr-k60n512/nsh/defconfig @@ -871,7 +871,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/u-blox-c027/nsh/defconfig b/configs/u-blox-c027/nsh/defconfig index eff1c86df15fc401664c5f5a33db61f596b13d42..1070431c0474c05e8ce3d977b22d2f82b7a34cd0 100644 --- a/configs/u-blox-c027/nsh/defconfig +++ b/configs/u-blox-c027/nsh/defconfig @@ -1244,7 +1244,7 @@ CONFIG_SYSTEM_CLE=y CONFIG_SYSTEM_CLE_DEBUGLEVEL=0 # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/ubw32/nsh/defconfig b/configs/ubw32/nsh/defconfig index f30d05b11848b76e6d5e07a8cdd5f4dfdc1ca86e..bb425839734e2293a81cc6ba4ef390654bd4d52a 100644 --- a/configs/ubw32/nsh/defconfig +++ b/configs/ubw32/nsh/defconfig @@ -319,6 +319,8 @@ CONFIG_RAM_SIZE=32768 # CONFIG_ARCH_BOARD_PCBLOGICPIC32MX is not set CONFIG_ARCH_BOARD_UBW32=y # CONFIG_ARCH_BOARD_CUSTOM is not set +CONFIG_ARCH_BOARD_CUSTOM_DIR="configs/dummy" +CONFIG_ARCH_BOARD_CUSTOM_DIR_RELPATH=y CONFIG_ARCH_BOARD="ubw32" # @@ -329,12 +331,11 @@ CONFIG_ARCH_LEDS=y CONFIG_ARCH_HAVE_BUTTONS=y # CONFIG_ARCH_BUTTONS is not set CONFIG_ARCH_HAVE_IRQBUTTONS=y -CONFIG_NSH_MMCSDMINOR=0 -CONFIG_NSH_MMCSDSLOTNO=0 # # Board-Specific Options # +# CONFIG_BOARD_CRASHDUMP is not set CONFIG_LIB_BOARDCTL=y # CONFIG_BOARDCTL_UNIQUEID is not set # CONFIG_BOARDCTL_TSCTEST is not set @@ -479,7 +480,12 @@ CONFIG_DEV_NULL=y # CONFIG_VIDEO_DEVICES is not set # CONFIG_BCH is not set # CONFIG_INPUT is not set + +# +# IO Expander/GPIO Support +# # CONFIG_IOEXPANDER is not set +# CONFIG_DEV_GPIO is not set # # LCD Driver Support @@ -881,6 +887,8 @@ CONFIG_NSH_DISABLE_LOSMART=y # CONFIG_NSH_DISABLE_USLEEP is not set # CONFIG_NSH_DISABLE_WGET is not set # CONFIG_NSH_DISABLE_XD is not set +CONFIG_NSH_MMCSDMINOR=0 +CONFIG_NSH_MMCSDSLOTNO=0 # # Configure Command Options @@ -921,7 +929,7 @@ CONFIG_NSH_ARCHINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/viewtool-stm32f107/highpri/defconfig b/configs/viewtool-stm32f107/highpri/defconfig index 578e69700c0eb55548cacb9e1ac729a62891cfdb..1799fad74c9c9d0cce7fefedf217d2bdbac6c6ba 100644 --- a/configs/viewtool-stm32f107/highpri/defconfig +++ b/configs/viewtool-stm32f107/highpri/defconfig @@ -1018,7 +1018,7 @@ CONFIG_ARCH_HAVE_TLS=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/viewtool-stm32f107/netnsh/defconfig b/configs/viewtool-stm32f107/netnsh/defconfig index 93163ab9c28ccde55077a1fb97e13a8e29e5b09e..a86887820401597553349ff72d80f6971052d56b 100644 --- a/configs/viewtool-stm32f107/netnsh/defconfig +++ b/configs/viewtool-stm32f107/netnsh/defconfig @@ -1350,7 +1350,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/viewtool-stm32f107/nsh/defconfig b/configs/viewtool-stm32f107/nsh/defconfig index 8a9aec658098d2b41e972c057d8670e07b44c51c..ecb91533d6a6257326650e738442390b9543e70f 100644 --- a/configs/viewtool-stm32f107/nsh/defconfig +++ b/configs/viewtool-stm32f107/nsh/defconfig @@ -1113,7 +1113,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/z8encore000zco/ostest/defconfig b/configs/z8encore000zco/ostest/defconfig index 499f1d6ea8534263e7fd75c3701fc2d9b9e25418..9f47341e903d3a666473683e544d2e4db2c2fbd4 100644 --- a/configs/z8encore000zco/ostest/defconfig +++ b/configs/z8encore000zco/ostest/defconfig @@ -658,7 +658,7 @@ CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_RAMTEST is not set # CONFIG_READLINE_HAVE_EXTMATCH is not set diff --git a/configs/z8f64200100kit/ostest/defconfig b/configs/z8f64200100kit/ostest/defconfig index 0d9e7ba4e7e3d982cb8607bb78b80d4f88222b99..1373c7e85767f6dc66faaccac3c9d2a6b4489bc3 100644 --- a/configs/z8f64200100kit/ostest/defconfig +++ b/configs/z8f64200100kit/ostest/defconfig @@ -659,7 +659,7 @@ CONFIG_EXAMPLES_OSTEST_RR_RUNS=10 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_INSTALL is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_RAMTEST is not set # CONFIG_READLINE_HAVE_EXTMATCH is not set diff --git a/configs/zkit-arm-1769/hello/defconfig b/configs/zkit-arm-1769/hello/defconfig index 183e232cfb6a0289000bc8f86de9c02835c6ccf1..60e67adb45687f4f302146866aee2f8cd6b67892 100644 --- a/configs/zkit-arm-1769/hello/defconfig +++ b/configs/zkit-arm-1769/hello/defconfig @@ -924,7 +924,7 @@ CONFIG_EXAMPLES_HELLO_STACKSIZE=2048 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/zkit-arm-1769/nsh/defconfig b/configs/zkit-arm-1769/nsh/defconfig index 10d3e9835744ae947714a175995757be5e5e3cab..dd6372c82cba18abfb15ca4d2457f8f1c6bd9b17 100644 --- a/configs/zkit-arm-1769/nsh/defconfig +++ b/configs/zkit-arm-1769/nsh/defconfig @@ -1125,7 +1125,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/zkit-arm-1769/nxhello/defconfig b/configs/zkit-arm-1769/nxhello/defconfig index 6412e6686fd84de0f0e965949cc6016f07a9a43b..4e3a8d38a1de5ad2f63b66686e07d93d83fa216e 100644 --- a/configs/zkit-arm-1769/nxhello/defconfig +++ b/configs/zkit-arm-1769/nxhello/defconfig @@ -1253,7 +1253,7 @@ CONFIG_NSH_IOBUFFER_SIZE=512 # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_NETDB is not set diff --git a/configs/zkit-arm-1769/src/lpc17_spi.c b/configs/zkit-arm-1769/src/lpc17_spi.c index ca01150deedae7ee014e4161a1c859c5138847ec..4418cb5bdfc45ab1ac8467ddc4fea4ff4a602148 100644 --- a/configs/zkit-arm-1769/src/lpc17_spi.c +++ b/configs/zkit-arm-1769/src/lpc17_spi.c @@ -65,7 +65,7 @@ /* Dump GPIO registers */ -#if CONFIG_DEBUG_SPI_INFO +#ifdef CONFIG_DEBUG_SPI_INFO # define spi_dumpgpio(m) lpc17_dumpgpio(SDCCS_GPIO, m) #else # define spi_dumpgpio(m) diff --git a/configs/zkit-arm-1769/src/lpc17_ssp.c b/configs/zkit-arm-1769/src/lpc17_ssp.c index 2302f15bd81b2b0e8dd83de77a3e31b447f173c1..09cf3833c85bbe6cd8697516324c4224b13e5380 100644 --- a/configs/zkit-arm-1769/src/lpc17_ssp.c +++ b/configs/zkit-arm-1769/src/lpc17_ssp.c @@ -65,7 +65,7 @@ /* Dump GPIO registers */ -#if CONFIG_DEBUG_SPI_INFO +#ifdef CONFIG_DEBUG_SPI_INFO # define ssp_dumpgpio(m) lpc17_dumpgpio(SDCCS_GPIO, m) #else # define ssp_dumpgpio(m) diff --git a/configs/zkit-arm-1769/thttpd/defconfig b/configs/zkit-arm-1769/thttpd/defconfig index 124e511bfc079b177827fb738102dd4c5006e0b4..21283879063e8a7f37ca80706145fce41a2e8fe7 100644 --- a/configs/zkit-arm-1769/thttpd/defconfig +++ b/configs/zkit-arm-1769/thttpd/defconfig @@ -956,7 +956,7 @@ CONFIG_THTTPD_TILDE_MAP_NONE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/zp214xpa/nsh/defconfig b/configs/zp214xpa/nsh/defconfig index 4f9e75d13b7f13e85a9b364423af0f29b008556b..54d6a26c8f24fcd21f4b00564b0923d2c3141900 100644 --- a/configs/zp214xpa/nsh/defconfig +++ b/configs/zp214xpa/nsh/defconfig @@ -800,7 +800,7 @@ CONFIG_NSH_CONSOLE=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/configs/zp214xpa/nxlines/defconfig b/configs/zp214xpa/nxlines/defconfig index 95d24c83693cb7a5cade09c6ee55462181837db0..6754cfcc3209d8de67b864e5b435c0683aab732d 100644 --- a/configs/zp214xpa/nxlines/defconfig +++ b/configs/zp214xpa/nxlines/defconfig @@ -859,7 +859,7 @@ CONFIG_EXAMPLES_NXLINES_EXTERNINIT=y # CONFIG_SYSTEM_CLE is not set # CONFIG_SYSTEM_CUTERM is not set # CONFIG_SYSTEM_FREE is not set -# CONFIG_SYSTEM_HEX2BIN is not set +# CONFIG_LIB_HEX2BIN is not set # CONFIG_SYSTEM_HEXED is not set # CONFIG_SYSTEM_INSTALL is not set # CONFIG_SYSTEM_RAMTEST is not set diff --git a/drivers/Kconfig b/drivers/Kconfig index 011850d6c90d0783bba35386bd15c4e7bf8b4575..bc506ee1e00628cd958a045dc2834db1c9fce51f 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -515,6 +515,24 @@ if USBHOST source drivers/usbhost/Kconfig endif # USBHOST +config HAVE_USBTRACE + bool + default n + +menuconfig USBMONITOR + bool "USB Monitor" + default n + depends on HAVE_USBTRACE + ---help--- + If USB device tracing (USBDEV_TRACE) AND/OR USB host tracing + (USBHOST_TRACE) are enabled then this option will select the USB + monitor. The USB monitor is a daemon that will periodically collect + the buffered USB trace data and dump it to the SYSLOG device. + +if USBMONITOR +source drivers/usbmonitor/Kconfig +endif # USBMONITOR + menuconfig DRIVERS_WIRELESS bool "Wireless Device Support" default n diff --git a/drivers/Makefile b/drivers/Makefile index 224cd78f6e53b097902a50c2903060155f662a3d..ff0a00b5b5a31f4a6e3b970dd22a91ab19914758 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -73,6 +73,7 @@ include syslog$(DELIM)Make.defs include timers$(DELIM)Make.defs include usbdev$(DELIM)Make.defs include usbhost$(DELIM)Make.defs +include usbmonitor$(DELIM)Make.defs include video$(DELIM)Make.defs include wireless$(DELIM)Make.defs diff --git a/drivers/ioexpander/Kconfig b/drivers/ioexpander/Kconfig index fd6abd77155ab60308e79ca1890b6a23fca61eed..de3b5d09a14011385ab07b6543c1b0d550ae5c4b 100644 --- a/drivers/ioexpander/Kconfig +++ b/drivers/ioexpander/Kconfig @@ -52,6 +52,26 @@ config IOEXPANDER_MULTIPIN This settings enable the definition of routines for optimized simultaneous access to multiple pins. +config IOEXPANDER_SHADOW_MODE + bool "Use Shadow Mode instead of Read-Modify-Write Operations" + default n + ---help--- + This setting enables a mode where the output and pin + configuration registers are held in RAM. + With this for example we do not need to read back the + output-register every time we want to change one pin. + We do instead change the bit in the internal register + and then just write this register to the IO-Expander. + This reduces bus traffic and eliminates the problem of + EMC-caused toggling of output pins. + +config IOEXPANDER_RETRY + bool "Retry to send commands and data at I2C communication errors" + default n + ---help--- + Retry to send commands and data if a I2C-communication + error occurs (eg. caused by EMC). + endif # IOEXPANDER config DEV_GPIO diff --git a/drivers/ioexpander/gpio.c b/drivers/ioexpander/gpio.c index d7f1e966fa9cd6ccd928d31fc21a8fbf58efb3fa..291652eb4dfde5b26b5f65469c798bd4a67f91db 100644 --- a/drivers/ioexpander/gpio.c +++ b/drivers/ioexpander/gpio.c @@ -56,11 +56,11 @@ static int gpio_open(FAR struct file *filep); static int gpio_close(FAR struct file *filep); static ssize_t gpio_read(FAR struct file *filep, FAR char *buffer, - size_t buflen); + size_t buflen); static ssize_t gpio_write(FAR struct file *filep, FAR const char *buffer, - size_t buflen); + size_t buflen); static int gpio_ioctl(FAR struct file *filep, int cmd, - unsigned long arg); + unsigned long arg); /**************************************************************************** * Private Data @@ -86,7 +86,7 @@ static const struct file_operations g_gpio_output_ops = { gpio_open, /* open */ gpio_close, /* close */ - NULL, /* read */ + gpio_read, /* read */ gpio_write, /* write */ NULL, /* seek */ gpio_ioctl /* ioctl */ @@ -168,7 +168,7 @@ static int gpio_ioctl(FAR struct file *filep, int cmd, unsigned long arg) { FAR struct inode *inode; FAR struct gpio_common_dev_s *dev; - int ret = OK; + int ret; DEBUGASSERT(filep != NULL && filep->f_inode != NULL); inode = filep->f_inode; @@ -176,52 +176,66 @@ static int gpio_ioctl(FAR struct file *filep, int cmd, unsigned long arg) dev = inode->i_private; switch (cmd) - { - /* Command: GPIO_WRITE - * Description: Set the value of an output GPIO - * Argument: 0=output a low value; 1=outut a high value - */ - - case GPIO_WRITE: - if (dev->gp_output) - { - FAR struct gpio_output_dev_s *outdev = - (FAR struct gpio_output_dev_s *)dev; - - DEBUGASSERT(outdev->gpout_write != NULL); - ret = outdev->gpout_write(outdev, (int)arg); - } - else - { - ret = -EACCES; - } - break; - - /* Command: GPIO_READ - * Description: Read the value of an input or output GPIO - * Argument: A pointer to an integer value to receive the result: - * 0=low value; 1=high value. - */ - - case GPIO_READ: - if (dev->gp_output) - { - FAR struct gpio_output_dev_s *outdev = - (FAR struct gpio_output_dev_s *)dev; - - DEBUGASSERT(outdev->gpout_read != NULL); - ret = outdev->gpout_read(outdev); - } - else - { - FAR struct gpio_input_dev_s *indev = - (FAR struct gpio_input_dev_s *)dev; - - DEBUGASSERT(indev->gpin_read != NULL); - ret = indev->gpin_read(indev); - } - break; - } + { + /* Command: GPIO_WRITE + * Description: Set the value of an output GPIO + * Argument: 0=output a low value; 1=outut a high value + */ + + case GPIO_WRITE: + if (dev->gp_output) + { + FAR struct gpio_output_dev_s *outdev = + (FAR struct gpio_output_dev_s *)dev; + + DEBUGASSERT(outdev->gpout_write != NULL && + ((arg == 0UL) || (arg == 1UL))); + ret = outdev->gpout_write(outdev, (int)arg); + } + else + { + ret = -EACCES; + } + break; + + /* Command: GPIO_READ + * Description: Read the value of an input or output GPIO + * Argument: A pointer to an integer value to receive the result: + * 0=low value; 1=high value. + */ + + case GPIO_READ: + { + FAR int *ptr = (FAR int *)((uintptr_t)arg); + DEBUGASSERT(ptr != NULL); + + if (dev->gp_output) + { + FAR struct gpio_output_dev_s *outdev = + (FAR struct gpio_output_dev_s *)dev; + + DEBUGASSERT(outdev->gpout_read != NULL); + ret = outdev->gpout_read(outdev, ptr); + } + else + { + FAR struct gpio_input_dev_s *indev = + (FAR struct gpio_input_dev_s *)dev; + + DEBUGASSERT(indev->gpin_read != NULL); + ret = indev->gpin_read(indev, ptr); + } + + DEBUGASSERT(ret < 0 || *ptr == 0 || *ptr == 1); + } + break; + + /* Unrecognized command */ + + default: + ret = -ENOTTY; + break; + } return ret; } @@ -242,9 +256,10 @@ int gpio_input_register(FAR struct gpio_input_dev_s *dev, int minor) { char devname[16]; - DEBUGASSERT(dev != NULL && !dev->output && (unsigned int)minor < 100); - snprintf(devname, 16, "/dev/gpin%u", (unsigned int)minor); + DEBUGASSERT(dev != NULL && !dev->gpin_output && dev->gpin_read != NULL && + (unsigned int)minor < 100); + snprintf(devname, 16, "/dev/gpin%u", (unsigned int)minor); return register_driver(devname, &g_gpio_input_ops, 0444, dev); } @@ -260,9 +275,10 @@ int gpio_output_register(FAR struct gpio_output_dev_s *dev, int minor) { char devname[16]; - DEBUGASSERT(dev != NULL && dev->output && (unsigned int)minor < 100); - snprintf(devname, 16, "/dev/gpout%u", (unsigned int)minor); + DEBUGASSERT(dev != NULL && dev->gpout_output && dev->gpout_read != NULL && + dev->gpout_write != NULL &&(unsigned int)minor < 100); + snprintf(devname, 16, "/dev/gpout%u", (unsigned int)minor); return register_driver(devname, &g_gpio_output_ops, 0222, dev); } diff --git a/drivers/ioexpander/pca9555.c b/drivers/ioexpander/pca9555.c index c01f7c37a58449cd14cb01f4151e4bfd006831af..34000d07eb31a76ed08b9fe80a88048762851fa7 100644 --- a/drivers/ioexpander/pca9555.c +++ b/drivers/ioexpander/pca9555.c @@ -223,11 +223,20 @@ static int pca9555_setbit(FAR struct pca9555_dev_s *pca, uint8_t addr, buf[0] = addr; +#ifdef CONFIG_IOEXPANDER_SHADOW_MODE + /* Get the shadowed register value */ + + buf[1] = pca->sreg[addr]; + +#else + /* Get the register value from the IO-Expander */ + ret = pca9555_writeread(pca, &buf[0], 1, &buf[1], 1); if (ret < 0) { return ret; } +#endif if (bitval) { @@ -238,7 +247,23 @@ static int pca9555_setbit(FAR struct pca9555_dev_s *pca, uint8_t addr, buf[1] &= ~(1 << pin); } - return pca9555_write(pca, buf, 2); +#ifdef CONFIG_IOEXPANDER_SHADOW_MODE + /* Save the new register value in the shadow register */ + + pca->sreg[addr] = buf[1]; +#endif + + ret = pca9555_write(pca, buf, 2); +#ifdef CONFIG_IOEXPANDER_RETRY + if (ret != OK) + { + /* Try again (only once) */ + + ret = pca9555_write(pca, buf, 2); + } +#endif + + return ret; } /**************************************************************************** @@ -271,6 +296,12 @@ static int pca9555_getbit(FAR struct pca9555_dev_s *pca, uint8_t addr, return ret; } +#ifdef CONFIG_IOEXPANDER_SHADOW_MODE + /* Save the new register value in the shadow register */ + + pca->sreg[addr] = buf; +#endif + *val = (buf >> pin) & 1; return OK; } @@ -417,6 +448,13 @@ static int pca9555_getmultibits(FAR struct pca9555_dev_s *pca, uint8_t addr, return ret; } +#ifdef CONFIG_IOEXPANDER_SHADOW_MODE + /* Save the new register value in the shadow register */ + + pca->sreg[addr] = buf[0]; + pca->sreg[addr+1] = buf[1]; +#endif + /* Read the requested bits */ for (i = 0; i < count; i++) @@ -465,15 +503,22 @@ static int pca9555_multiwritepin(FAR struct ioexpander_dev_s *dev, /* Start by reading both registers, whatever the pins to change. We could * attempt to read one port only if all pins were on the same port, but - * this would not save much. */ + * this would not save much. + */ +#ifndef CONFIG_IOEXPANDER_SHADOW_MODE ret = pca9555_writeread(pca, &addr, 1, &buf[1], 2); if (ret < 0) { - pca9555_unlock(pca); return ret; } +#else + /* In Shadow-Mode we "read" the pin status from the shadow registers */ + + buf[1] = pca->sreg[addr]; + buf[2] = pca->sreg[addr+1]; +#endif /* Apply the user defined changes */ @@ -505,6 +550,11 @@ static int pca9555_multiwritepin(FAR struct ioexpander_dev_s *dev, /* Now write back the new pins states */ buf[0] = addr; +#ifdef CONFIG_IOEXPANDER_SHADOW_MODE + /* Save the new register values in the shadow register */ + pca->sreg[addr] = buf[1]; + pca->sreg[addr+1] = buf[2]; +#endif ret = pca9555_write(pca, buf, 3); pca9555_unlock(pca); @@ -585,6 +635,11 @@ static void pca9555_irqworker(void *arg) ret = pca9555_writeread(pca, &addr, 1, buf, 2); if (ret == OK) { +#ifdef CONFIG_IOEXPANDER_SHADOW_MODE + /* Don't forget to update the shadow registers at this point */ + + pca->sreg[addr] = buf; +#endif bits = ((unsigned int)buf[0] << 8) | buf[1]; /* If signal PID is registered, enqueue signal. */ diff --git a/drivers/ioexpander/pca9555.h b/drivers/ioexpander/pca9555.h index 39435f23d61e23e8c76315a0d129564f80c31050..7152a58bb13a0c7ee414be58b8d29fc8ad11a5c8 100644 --- a/drivers/ioexpander/pca9555.h +++ b/drivers/ioexpander/pca9555.h @@ -61,6 +61,7 @@ /******************************************************************************************** * Pre-processor Definitions ********************************************************************************************/ + /* Configuration ****************************************************************************/ /* Prerequisites: * CONFIG_I2C @@ -118,11 +119,12 @@ struct pca9555_dev_s { struct ioexpander_dev_s dev; /* Nested structure to allow casting as public gpio * expander. */ - +#ifdef CONFIG_IOEXPANDER_SHADOW_MODE + uint8_t sreg[8]; /* Shadowed registers of the PCA9555 */ +#endif #ifdef CONFIG_PCA9555_MULTIPLE FAR struct pca9555_dev_s *flink; /* Supports a singly linked list of drivers */ #endif - FAR struct pca9555_config_s *config; /* Board configuration data */ FAR struct i2c_master_s *i2c; /* Saved I2C driver instance */ sem_t exclsem; /* Mutual exclusion */ diff --git a/drivers/mtd/at25.c b/drivers/mtd/at25.c index efc2e355a7664767924860efa16fe4e0677a99f7..777ff3877f328081bb79e550f3cf8bf0514e05be 100644 --- a/drivers/mtd/at25.c +++ b/drivers/mtd/at25.c @@ -673,7 +673,7 @@ FAR struct mtd_dev_s *at25_initialize(FAR struct spi_dev_s *dev) ferr("ERROR: Unrecognized\n"); kmm_free(priv); - priv = NULL; + return NULL; } else { diff --git a/drivers/mtd/is25xp.c b/drivers/mtd/is25xp.c index 2228f760b033b188fd7bc6869e3fa9844f2100b1..55b677b38a32bcb482de12ed6b2bbba8e97adb44 100644 --- a/drivers/mtd/is25xp.c +++ b/drivers/mtd/is25xp.c @@ -978,7 +978,7 @@ FAR struct mtd_dev_s *is25xp_initialize(FAR struct spi_dev_s *dev) ferr("ERROR: Unrecognized\n"); kmm_free(priv); - priv = NULL; + return NULL; } else { @@ -999,4 +999,3 @@ FAR struct mtd_dev_s *is25xp_initialize(FAR struct spi_dev_s *dev) finfo("Return %p\n", priv); return (FAR struct mtd_dev_s *)priv; } - diff --git a/drivers/mtd/m25px.c b/drivers/mtd/m25px.c index eb2cade8ee520d02268a0d26215bbadb8360ea27..4402995afbc326d51e7d127f675f49584efe5360 100644 --- a/drivers/mtd/m25px.c +++ b/drivers/mtd/m25px.c @@ -1033,7 +1033,7 @@ FAR struct mtd_dev_s *m25p_initialize(FAR struct spi_dev_s *dev) ferr("ERROR: Unrecognized\n"); kmm_free(priv); - priv = NULL; + return NULL; } } diff --git a/drivers/mtd/ramtron.c b/drivers/mtd/ramtron.c index a81469f92ee125dd88fbf97a07109a2ea644d25a..0152475b98b9484f915f3fc14f8ecc701d6ca6c6 100644 --- a/drivers/mtd/ramtron.c +++ b/drivers/mtd/ramtron.c @@ -826,7 +826,7 @@ FAR struct mtd_dev_s *ramtron_initialize(FAR struct spi_dev_s *dev) /* Unrecognized! Discard all of that work we just did and return NULL */ kmm_free(priv); - priv = NULL; + return NULL; } } diff --git a/drivers/mtd/sst25.c b/drivers/mtd/sst25.c index 89d21324aa31fefeeb177ee9d4b6dd5fedee7c70..8da5778d840eb7846dfa7e3c32b166642e415482 100644 --- a/drivers/mtd/sst25.c +++ b/drivers/mtd/sst25.c @@ -1208,7 +1208,7 @@ FAR struct mtd_dev_s *sst25_initialize(FAR struct spi_dev_s *dev) ferr("ERROR: Unrecognized\n"); kmm_free(priv); - priv = NULL; + return NULL; } else { diff --git a/drivers/mtd/sst25xx.c b/drivers/mtd/sst25xx.c index 4d30be50bbedb448122b43f23429f59270228320..9f883483af71896ddf6add9b98d8558f64ea7266 100644 --- a/drivers/mtd/sst25xx.c +++ b/drivers/mtd/sst25xx.c @@ -956,7 +956,7 @@ FAR struct mtd_dev_s *sst25xx_initialize(FAR struct spi_dev_s *dev) ferr("ERROR: Unrecognized\n"); kmm_free(priv); - priv = NULL; + return NULL; } else { diff --git a/drivers/mtd/sst26.c b/drivers/mtd/sst26.c index 91eb045fcf4e316e3eef2bc75b51abc4bd40b859..51888da063b272f04e4c0d42ae14a56886f3df9c 100644 --- a/drivers/mtd/sst26.c +++ b/drivers/mtd/sst26.c @@ -934,7 +934,7 @@ FAR struct mtd_dev_s *sst26_initialize_spi(FAR struct spi_dev_s *dev) ssterr("ERROR: Unrecognized\n"); kmm_free(priv); - priv = NULL; + return NULL; } else { diff --git a/drivers/mtd/w25.c b/drivers/mtd/w25.c index 3559f8d6a5c5a1307c6b3df0b8a9ea899db6663c..da015a8c421f036e172ae1e4e46c67d8b2dbc260 100644 --- a/drivers/mtd/w25.c +++ b/drivers/mtd/w25.c @@ -1258,7 +1258,7 @@ FAR struct mtd_dev_s *w25_initialize(FAR struct spi_dev_s *spi) ferr("ERROR: Unrecognized\n"); kmm_free(priv); - priv = NULL; + return NULL; } else { diff --git a/drivers/spi/Make.defs b/drivers/spi/Make.defs index 9581a2736f6de47a3478b1b5460986e4a6df394e..43e5654faa84acceaabb64527b4ef096c98b482d 100644 --- a/drivers/spi/Make.defs +++ b/drivers/spi/Make.defs @@ -49,4 +49,3 @@ DEPPATH += --dep-path spi VPATH += :spi CFLAGS += ${shell $(INCDIR) $(INCDIROPT) "$(CC)" $(TOPDIR)$(DELIM)drivers$(DELIM)spi} endif - diff --git a/drivers/syslog/Kconfig b/drivers/syslog/Kconfig index 07a7f92a4c88e7a890e6845c9974407a97848d9d..3ac22d8b684eb960cf5602725066034cb7ee5c55 100644 --- a/drivers/syslog/Kconfig +++ b/drivers/syslog/Kconfig @@ -172,7 +172,7 @@ config SYSLOG_CHAR_CRLF config SYSLOG_DEVPATH string "System log device" - default "/dev/syslog" + default "/dev/ttyS1" depends on SYSLOG_CHAR ---help--- The full path to the system logging device. For the RAMLOG SYSLOG device, @@ -180,4 +180,17 @@ config SYSLOG_DEVPATH some other existing character device (or file) supported by the configuration (such as "/dev/ttyS1")/ +config SYSLOG_CHARDEV + bool "SYSLOG character device" + default n + ---help--- + Enables support for a simple character driver at /dev/syslog whose + write() method will transfer data to the SYSLOG device. This can be + useful if, for example, you want to redirect the output of a program + to the SYSLOG. + + NOTE that unlike other syslog output, this data is unformatted raw + byte output with no time-stamping or any other SYSLOG features + supported. + endmenu # System logging diff --git a/drivers/syslog/Make.defs b/drivers/syslog/Make.defs index 95583059e16bb954976e0344bef0d69f3b90313f..2cad218e5ae11518cd7baab3ce99f91285a610b7 100644 --- a/drivers/syslog/Make.defs +++ b/drivers/syslog/Make.defs @@ -80,7 +80,9 @@ ifeq ($(CONFIG_SYSLOG_FILE),y) CSRCS += syslog_filechannel.c endif -# (Add other SYSLOG drivers here) +ifeq ($(CONFIG_SYSLOG_CHARDEV),y) +CSRCS += syslog_chardev.c +endif ifeq ($(CONFIG_CONSOLE_SYSLOG),y) CSRCS += syslog_console.c diff --git a/drivers/syslog/syslog_chardev.c b/drivers/syslog/syslog_chardev.c new file mode 100644 index 0000000000000000000000000000000000000000..b852db05a214664db87f5fe2904d53cadbbe7070 --- /dev/null +++ b/drivers/syslog/syslog_chardev.c @@ -0,0 +1,129 @@ +/**************************************************************************** + * drivers/syslog/syslog_chardev.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include + +#include +#include + +#include "syslog.h" + +#ifdef CONFIG_SYSLOG_CHARDEV + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static ssize_t syslog_write(FAR struct file *filep, FAR const char *buffer, + size_t buflen); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static const struct file_operations syslog_fops = +{ + NULL, /* open */ + NULL, /* close */ + NULL, /* read */ + syslog_write, /* write */ + NULL, /* seek */ + NULL /* ioctl */ +#ifndef CONFIG_DISABLE_POLL + , NULL /* poll */ +#endif +#ifndef CONFIG_DISABLE_PSEUDOFS_OPERATIONS + , NULL /* unlink */ +#endif +}; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: syslog_write + ****************************************************************************/ + +static ssize_t syslog_write(FAR struct file *filep, FAR const char *buffer, + size_t len) +{ + size_t nwritten; + int ret; + + for (nwritten = 0; nwritten < len; nwritten++) + { + int ch = *buffer++; + ret = syslog_putc(ch); + UNUSED(ret); + } + + return len; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: syslog_register + * + * Description: + * Register a simple character driver at /dev/syslog whose write() method + * will transfer data to the SYSLOG device. This can be useful if, for + * example, you want to redirect the output of a program to the SYSLOG. + * + * NOTE that unlike other syslog output, this data is unformatted raw + * byte output with no time-stamping or any other SYSLOG features + * supported. + * + ****************************************************************************/ + +void syslog_register(void) +{ + (void)register_driver("/dev/syslog", &syslog_fops, 0222, NULL); +} + +#endif /* CONFIG_SYSLOG_CHARDEV */ diff --git a/drivers/syslog/syslog_devchannel.c b/drivers/syslog/syslog_devchannel.c index fbc912ad78b11377376778c42fb6676560910294..e0251efc8e2e0ec1dd9910c3d3a84d63a89a703b 100644 --- a/drivers/syslog/syslog_devchannel.c +++ b/drivers/syslog/syslog_devchannel.c @@ -102,11 +102,11 @@ static int syslog_devchan_putc(int ch) /* Check for a linefeed */ - if (ch == '/n') + if (ch == '\n') { /* Pre-pend a carriage return */ - ret = syslog_dev_putc('/r'); + ret = syslog_dev_putc('\r'); if (ret < 0) { return ret; diff --git a/drivers/syslog/syslog_device.c b/drivers/syslog/syslog_device.c index 22bc08eb35876239ecc9d69012ba7ccf89dac9a3..c3bf74834a7e0930d1a33aaf13c866625470e74d 100644 --- a/drivers/syslog/syslog_device.c +++ b/drivers/syslog/syslog_device.c @@ -133,9 +133,9 @@ static inline int syslog_dev_takesem(void) int ret; /* Does this thread already hold the semaphore? That could happen if - * we wer called recursively, i.e., if the logic kicked off by - * syslog_dev_write() where to generate more debug output. Return an error - * in that case. + * we were called recursively, i.e., if the logic kicked off by + * file_write() where to generate more debug output. Return an + * error in that case. */ if (g_syslog_dev.sl_holder == me) @@ -184,26 +184,6 @@ static inline void syslog_dev_givesem(void) sem_post(&g_syslog_dev.sl_sem); } -/**************************************************************************** - * Name: syslog_dev_write - * - * Description: - * Write to the syslog device - * - ****************************************************************************/ - -static inline ssize_t syslog_dev_write(FAR const void *buf, size_t nbytes) -{ - FAR struct inode *inode; - - /* Let the driver perform the write */ - - inode = g_syslog_dev.sl_file.f_inode; - DEBUGASSERT(inode != NULL); - - return inode->u.i_ops->write(&g_syslog_dev.sl_file, buf, nbytes); -} - /**************************************************************************** * Public Functions ****************************************************************************/ @@ -505,7 +485,7 @@ int syslog_dev_putc(int ch) if (ret < 0) { /* We probably already hold the semaphore and were probably - * re-entered by the logic kicked off by syslog_dev_write(). + * re-entered by the logic kicked off by file_write(). * We might also have been interrupted by a signal. Either * way, we are outta here. */ @@ -520,7 +500,7 @@ int syslog_dev_putc(int ch) { /* Write the CR-LF sequence */ - nbytes = syslog_dev_write(g_syscrlf, 2); + nbytes = file_write(&g_syslog_dev.sl_file, g_syscrlf, 2); /* Synchronize the file when each CR-LF is encountered (i.e., * implements line buffering always). @@ -538,7 +518,7 @@ int syslog_dev_putc(int ch) /* Write the non-newline character (and don't flush) */ uch = (uint8_t)ch; - nbytes = syslog_dev_write(&uch, 1); + nbytes = file_write(&g_syslog_dev.sl_file, &uch, 1); } syslog_dev_givesem(); @@ -576,24 +556,16 @@ errout_with_errcode: int syslog_dev_flush(void) { - int ret = 0;; - #if defined(CONFIG_SYSLOG_FILE) && !defined(CONFIG_DISABLE_MOUNTPOINT) - FAR struct inode *inode = g_syslog_dev.sl_file.f_inode; - - /* Is this a mountpoint? Does it support the sync method? */ - - if (inode != NULL && /* File opened (i.e., has inode)? */ - INODE_IS_MOUNTPT(inode) && /* Inode is a mountpoint? */ - inode->u.i_mops->sync != NULL) /* And supports synce method? */ - { - /* Yes... synchronize to the stream */ + /* Ignore return value, always return success. file_fsync() could fail + * because the file is not open, the inode is not a mountpoint, or the + * mountpoint does not support the sync() method. + */ - ret = inode->u.i_mops->sync(&g_syslog_dev.sl_file); - } + (void)file_fsync(&g_syslog_dev.sl_file); #endif - return ret; + return OK; } #endif /* CONFIG_NFILE_DESCRIPTORS > 0 */ diff --git a/drivers/usbdev/Kconfig b/drivers/usbdev/Kconfig index efcf0def0bda113604ca4e156b8e4835d5660f26..f68b2be67f374bee0f244ec86605cc3ac6230699 100644 --- a/drivers/usbdev/Kconfig +++ b/drivers/usbdev/Kconfig @@ -91,6 +91,7 @@ config ARCH_USBDEV_STALLQUEUE menuconfig USBDEV_TRACE bool "Enable USB tracing for debug" default n + select HAVE_USBTRACE ---help--- Enables USB tracing for debug diff --git a/drivers/usbhost/Kconfig b/drivers/usbhost/Kconfig index 4e9c024c615368ccdb14ba0f9d963e6b8f3e2579..e8768896901df874d1b744441bb271ecbd3a0ac5 100644 --- a/drivers/usbhost/Kconfig +++ b/drivers/usbhost/Kconfig @@ -508,6 +508,7 @@ endif # USBHOST_RTL8187 config USBHOST_TRACE bool "Enable USB HCD tracing for debug" default n + select HAVE_USBTRACE ---help--- Enables USB tracing for debug. Only supported for the HCD and, further, no supported by all HCD implementations. diff --git a/drivers/usbmonitor/Kconfig b/drivers/usbmonitor/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..e35c47e49086969cd2f0f56f5bad1d9e8305231b --- /dev/null +++ b/drivers/usbmonitor/Kconfig @@ -0,0 +1,58 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + + +config USBMONITOR_STACKSIZE + int "USB Monitor daemon stack size" + default 2048 + ---help--- + The stack size to use the the USB monitor daemon. Default: 2048 + +config USBMONITOR_PRIORITY + int "USB Monitor daemon priority" + default 50 + ---help--- + The priority to use the the USB monitor daemon. Default: 50 + +config USBMONITOR_INTERVAL + int "USB Monitor dump frequency" + default 2 + ---help--- + The rate in seconds that the USB monitor will wait before dumping + the next set of buffered USB trace data. Default: 2 seconds. + +if USBDEV && USBDEV_TRACE + +config USBMONITOR_TRACEINIT + bool "Show USB device initialization events" + default n + ---help--- + Show initialization events + +config USBMONITOR_TRACECLASS + bool "Show USB device class driver events" + default n + ---help--- + Show class driver events + +config USBMONITOR_TRACETRANSFERS + bool "Show USB device data transfer events" + default n + ---help--- + Show data transfer events + +config USBMONITOR_TRACECONTROLLER + bool "Show USB device controller events" + default n + ---help--- + Show controller events + +config USBMONITOR_TRACEINTERRUPTS + bool "Show USB device interrupt-related events" + default n + ---help--- + Show interrupt-related events + +endif # USBDEV && USBDEV_TRACE diff --git a/drivers/usbmonitor/Make.defs b/drivers/usbmonitor/Make.defs new file mode 100644 index 0000000000000000000000000000000000000000..3c80ad6c4bb3220cc10807cfa1e40f3b5e5e6e85 --- /dev/null +++ b/drivers/usbmonitor/Make.defs @@ -0,0 +1,51 @@ +############################################################################ +# drivers/usbmonitor/Make.defs +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +# Don't build anything if there is no USB monitor support + +ifeq ($(CONFIG_USBMONITOR),y) + +# Include the USB monitor + +CSRCS += usbmonitor.c + +# Include USB monitor build support + +DEPPATH += --dep-path usbmonitor +VPATH += :usbmonitor +CFLAGS += ${shell $(INCDIR) $(INCDIROPT) "$(CC)" $(TOPDIR)$(DELIM)drivers$(DELIM)usbmonitor} + +endif + diff --git a/drivers/usbmonitor/usbmonitor.c b/drivers/usbmonitor/usbmonitor.c new file mode 100644 index 0000000000000000000000000000000000000000..22e34ed5e49bb1f737ff3acb139134d14eeb4f15 --- /dev/null +++ b/drivers/usbmonitor/usbmonitor.c @@ -0,0 +1,292 @@ +/**************************************************************************** + * drivers/usbmonitor/usbmonitor.c + * + * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#ifdef CONFIG_USBMONITOR + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration ************************************************************/ + +#ifndef CONFIG_USBMONITOR_STACKSIZE +# define CONFIG_USBMONITOR_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBMONITOR_PRIORITY +# define CONFIG_USBMONITOR_PRIORITY 50 +#endif + +#ifndef CONFIG_USBMONITOR_INTERVAL +# define CONFIG_USBMONITOR_INTERVAL 2 +#endif + +/* USB device trace selection */ + +#ifdef CONFIG_USBDEV_TRACE +# ifdef CONFIG_USBMONITOR_TRACEINIT +# define TRACE_INIT_BITS (TRACE_INIT_BIT) +# else +# define TRACE_INIT_BITS (0) +# endif + +# define TRACE_ERROR_BITS (TRACE_DEVERROR_BIT|TRACE_CLSERROR_BIT) + +# ifdef CONFIG_USBMONITOR_TRACECLASS +# define TRACE_CLASS_BITS (TRACE_CLASS_BIT|TRACE_CLASSAPI_BIT|\ + TRACE_CLASSSTATE_BIT) +# else +# define TRACE_CLASS_BITS (0) +# endif + +# ifdef CONFIG_USBMONITOR_TRACETRANSFERS +# define TRACE_TRANSFER_BITS (TRACE_OUTREQQUEUED_BIT|TRACE_INREQQUEUED_BIT|\ + TRACE_READ_BIT|TRACE_WRITE_BIT|\ + TRACE_COMPLETE_BIT) +# else +# define TRACE_TRANSFER_BITS (0) +# endif + +# ifdef CONFIG_USBMONITOR_TRACECONTROLLER +# define TRACE_CONTROLLER_BITS (TRACE_EP_BIT|TRACE_DEV_BIT) +# else +# define TRACE_CONTROLLER_BITS (0) +# endif + +# ifdef CONFIG_USBMONITOR_TRACEINTERRUPTS +# define TRACE_INTERRUPT_BITS (TRACE_INTENTRY_BIT|TRACE_INTDECODE_BIT|\ + TRACE_INTEXIT_BIT) +# else +# define TRACE_INTERRUPT_BITS (0) +# endif + +# define TRACE_BITSET (TRACE_INIT_BITS|TRACE_ERROR_BITS|\ + TRACE_CLASS_BITS|TRACE_TRANSFER_BITS|\ + TRACE_CONTROLLER_BITS|TRACE_INTERRUPT_BITS) +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct usbmon_state_s +{ + volatile bool started; + volatile bool stop; + pid_t pid; +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static struct usbmon_state_s g_usbmonitor; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +#ifdef CONFIG_USBDEV_TRACE +static int usbtrace_syslog(FAR const char *fmt, ...) +{ + va_list ap; + int ret; + + /* Let vsyslog do the real work */ + + va_start(ap, fmt); + ret = vsyslog(LOG_INFO, fmt, ap); + va_end(ap); + return ret; +} + +static int usbmonitor_tracecallback(struct usbtrace_s *trace, void *arg) +{ + usbtrace_trprintf(usbtrace_syslog, trace->event, trace->value); + return 0; +} +#endif + +static int usbmonitor_daemon(int argc, char **argv) +{ + uinfo("Running: %d\n", g_usbmonitor.pid); + + /* Loop until we detect that there is a request to stop. */ + + while (!g_usbmonitor.stop) + { + sleep(CONFIG_USBMONITOR_INTERVAL); +#ifdef CONFIG_USBDEV_TRACE + (void)usbtrace_enumerate(usbmonitor_tracecallback, NULL); +#endif +#ifdef CONFIG_USBHOST_TRACE + (void)usbhost_trdump(); +#endif + } + + /* Stopped */ + + g_usbmonitor.stop = false; + g_usbmonitor.started = false; + uinfo("Stopped: %d\n", g_usbmonitor.pid); + + return 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: usbmonitor_start + * + * Start the USB monitor kernal daemon. + * + * Input Parameters: + * None + * + * Returned values: + * Zero (OK) is returned on success; a negated errno value is return on + * any failure. + * + ****************************************************************************/ + +int usbmonitor_start(void) +{ + /* Has the monitor already started? */ + + sched_lock(); + if (!g_usbmonitor.started) + { + int ret; + + /* No.. start it now */ + +#ifdef CONFIG_USBDEV_TRACE + /* First, initialize any USB tracing options that were requested */ + + usbtrace_enable(TRACE_BITSET); +#endif + + /* Then start the USB monitoring daemon */ + + g_usbmonitor.started = true; + g_usbmonitor.stop = false; + + ret = kernel_thread("USB Monitor", CONFIG_USBMONITOR_PRIORITY, + CONFIG_USBMONITOR_STACKSIZE, + (main_t)usbmonitor_daemon, + (FAR char * const *)NULL); + if (ret < 0) + { + int errcode = errno; + uerr("ERROR: Failed to start the USB monitor: %d\n", + errcode); + UNUSED(errcode); + } + else + { + g_usbmonitor.pid = ret; + uinfo("Started: %d\n", g_usbmonitor.pid); + } + + sched_unlock(); + return 0; + } + + sched_unlock(); + uinfo("%s: %d\n", + g_usbmonitor.stop ? "Stopping" : "Running", g_usbmonitor.pid); + return 0; +} + +/**************************************************************************** + * Name: usbmonitor_stop + * + * Stop the USB monitor kernel daemon. + * + * Input Parameters: + * None + * + * Returned values: + * Zero (OK) is returned on success; a negated errno value is return on + * any failure. + * + ****************************************************************************/ + +int usbmonitor_stop(void) +{ + /* Has the monitor already started? */ + + if (g_usbmonitor.started) + { + /* Stop the USB monitor. The next time the monitor wakes up, + * it will see the the stop indication and will exist. + */ + + uinfo("Stopping: %d\n", g_usbmonitor.pid); + g_usbmonitor.stop = true; + +#ifdef CONFIG_USBDEV_TRACE + /* We may as well disable tracing since there is no listener */ + + usbtrace_enable(0); +#endif + } + + uinfo("Stopped: %d\n", g_usbmonitor.pid); + return 0; +} + +#endif /* CONFIG_USBMONITOR */ diff --git a/fs/vfs/fs_ioctl.c b/fs/vfs/fs_ioctl.c index 238da907a7940c9e4da313f5fa38bd187d629dcb..97a5056a39bc04b71cf6d51d180253bfba274417 100644 --- a/fs/vfs/fs_ioctl.c +++ b/fs/vfs/fs_ioctl.c @@ -1,7 +1,7 @@ /**************************************************************************** * fs/vfs/fs_ioctl.c * - * Copyright (C) 2007-2010, 2012-2014 Gregory Nutt. All rights reserved. + * Copyright (C) 2007-2010, 2012-2014, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -56,6 +56,47 @@ * Public Functions ****************************************************************************/ +/**************************************************************************** + * Name: file_ioctl + * + * Description: + * Perform device specific operations. + * + * Parameters: + * file File structure instance + * req The ioctl command + * arg The argument of the ioctl cmd + * + * Return: + * See ioctl() below. + * + ****************************************************************************/ + +#if CONFIG_NFILE_DESCRIPTORS > 0 +int file_ioctl(FAR struct file *filep, int req, unsigned long arg) +{ + FAR struct inode *inode; + int ret; + + /* Is a driver registered? Does it support the ioctl method? */ + + inode = filep->f_inode; + if (inode && inode->u.i_ops && inode->u.i_ops->ioctl) + { + /* Yes, then let it perform the ioctl */ + + ret = (int)inode->u.i_ops->ioctl(filep, req, arg); + if (ret < 0) + { + set_errno(-ret); + return ERROR; + } + } + + return OK; +} +#endif /* CONFIG_NFILE_DESCRIPTORS > 0 */ + /**************************************************************************** * Name: ioctl/fs_ioctl * @@ -93,9 +134,7 @@ int ioctl(int fd, int req, unsigned long arg) { int errcode; #if CONFIG_NFILE_DESCRIPTORS > 0 - FAR struct file *filep; - FAR struct inode *inode; - int ret = OK; + FAR struct file *filep; /* Did we get a valid file descriptor? */ @@ -130,20 +169,9 @@ int ioctl(int fd, int req, unsigned long arg) /* Is a driver registered? Does it support the ioctl method? */ - inode = filep->f_inode; - if (inode && inode->u.i_ops && inode->u.i_ops->ioctl) - { - /* Yes, then let it perform the ioctl */ - - ret = (int)inode->u.i_ops->ioctl(filep, req, arg); - if (ret < 0) - { - errcode = -ret; - goto errout; - } - } - - return ret; + return file_ioctl(filep, req, arg); +#else + errcode = ENOTTY; #endif errout: diff --git a/include/cxx/csignal b/include/cxx/csignal index 2303a864dd10e879acf74a85f3679234dfc707be..c66473bb57fd4d2e3ea2e13b44bacea618a05544 100644 --- a/include/cxx/csignal +++ b/include/cxx/csignal @@ -1,7 +1,7 @@ //*************************************************************************** // include/cxx/csignal // -// Copyright (C) 2009 Gregory Nutt. All rights reserved. +// Copyright (C) 2009, 2016 Gregory Nutt. All rights reserved. // Author: Gregory Nutt // // Redistribution and use in source and binary forms, with or without @@ -55,6 +55,7 @@ namespace std using ::siginfo_t; using ::sigaction; using ::kill; + using ::raise; using ::sigemptyset; using ::sigfillset; using ::sigaddset; diff --git a/include/hex2bin.h b/include/hex2bin.h new file mode 100644 index 0000000000000000000000000000000000000000..3217c54560eeda31e858f6286188dbc7ed885cb2 --- /dev/null +++ b/include/hex2bin.h @@ -0,0 +1,244 @@ +/**************************************************************************** + * include/hex2bin.h + * + * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __INCLUDE_HEX2BIN_H +#define __INCLUDE_HEX2BIN_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include + +#ifdef CONFIG_LIB_HEX2BIN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Some environments may return CR as end-of-line, others LF, and others + * both. If not specified, the logic here assumes either (but not both) as + * the default. + */ + +#if defined(CONFIG_EOL_IS_CR) +# undef CONFIG_EOL_IS_LF +# undef CONFIG_EOL_IS_BOTH_CRLF +# undef CONFIG_EOL_IS_EITHER_CRLF +#elif defined(CONFIG_EOL_IS_LF) +# undef CONFIG_EOL_IS_CR +# undef CONFIG_EOL_IS_BOTH_CRLF +# undef CONFIG_EOL_IS_EITHER_CRLF +#elif defined(CONFIG_EOL_IS_BOTH_CRLF) +# undef CONFIG_EOL_IS_CR +# undef CONFIG_EOL_IS_LF +# undef CONFIG_EOL_IS_EITHER_CRLF +#elif defined(CONFIG_EOL_IS_EITHER_CRLF) +# undef CONFIG_EOL_IS_CR +# undef CONFIG_EOL_IS_LF +# undef CONFIG_EOL_IS_BOTH_CRLF +#else +# undef CONFIG_EOL_IS_CR +# undef CONFIG_EOL_IS_LF +# undef CONFIG_EOL_IS_BOTH_CRLF +# define CONFIG_EOL_IS_EITHER_CRLF 1 +#endif + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Intel HEX data steams are normally in big endian order. The following + * enumeration selects other ordering. + */ + +enum hex2bin_swap_e +{ + HEX2BIN_NOSWAP = 0, /* No swap, stream is in the correct byte order */ + HEX2BIN_SWAP16 = 1, /* Swap bytes in 16-bit values */ + HEX2BIN_SWAP32 = 2 /* Swap bytes in 32-bit values */ +}; + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: hex2bin + * + * Description: + * Read the Intel HEX ASCII data provided on the serial IN stream and write + * the binary to the seek-able serial OUT stream. + * + * These streams may be files or, in another usage example, the IN stream + * could be a serial port and the OUT stream could be a memory stream. This + * would decode and write the serial input to memory. + * + * Input Parameters: + * instream - The incoming stream from which Intel HEX data will be + * received. + * outstream - The outgoing stream in which binary data will be written. + * baseaddr - The base address of the outgoing stream. Seeking in the + * output stream will be relative to this address. + * endpaddr - The end address (plus 1) of the outgoing stream. This + * value is used only for range checking. endpaddr must + * be larger than baseaddr. A zero value for endpaddr + * disables range checking. + * swap - Controls byte ordering. See enum hex2bin_swap_e for + * description of the values. + * + * Returned Value + * Zero (OK) is returned on success; a negated errno value is returned on + * failure. + * + ****************************************************************************/ + +struct lib_instream_s; +struct lib_sostream_s; +int hex2bin(FAR struct lib_instream_s *instream, + FAR struct lib_sostream_s *outstream, uint32_t baseaddr, + uint32_t endpaddr, enum hex2bin_swap_e swap); + +/**************************************************************************** + * Name hex2mem + * + * Description: + * Read the Intel HEX ASCII data provided on the file descriptor 'fd' and + * write the binary to memory. + * + * If, for example, fd is zero (corresponding to stdin), then the HEX + * ASCII data would be taken from the console and written to memory. + * + * Input Parameters: + * fd - The file descriptor from which Intel HEX data will be + * received. + * baseaddr - The base address of the memory region stream. + * endpaddr - The end address (plus 1) of the memory region. + * swap - Controls byte ordering. See enum hex2bin_swap_e for + * description of the values. + * + * Returned Value + * Zero (OK) is returned on success; a negated errno value is returned on + * failure. + * + ****************************************************************************/ + +int hex2mem(int fd, uint32_t baseaddr, uint32_t endpaddr, + enum hex2bin_swap_e swap); + +/**************************************************************************** + * Name fhex2mem + * + * Description: + * Read the Intel HEX ASCII data provided on the standard stream + * 'instream' and write the binary to memory. + * + * If, for example, instream is stdin, then the HEX ASCII data would be + * taken from the console and written to memory. + * + * Input Parameters: + * instream - The incoming standard stream from which Intel HEX data + * will be received. + * baseaddr - The base address of the memory region stream. + * endpaddr - The end address (plus 1) of the memory region. + * swap - Controls byte ordering. See enum hex2bin_swap_e for + * description of the values. + * + * Returned Value + * Zero (OK) is returned on success; a negated errno value is returned on + * failure. + * + ****************************************************************************/ + +int fhex2mem(FAR FILE *instream, uint32_t baseaddr, uint32_t endpaddr, + enum hex2bin_swap_e swap); + +/**************************************************************************** + * Name: hex2bin_main + * + * Description: + * Main entry point when hex2bin is built as an NSH built-in task. + * + * Input Parameters: + * Standard task inputs + * + * Returned Value + * EXIT_SUCESS on success; EXIT_FAILURE on failure + * + ****************************************************************************/ + +#ifdef CONFIG_SYSTEM_HEX2BIN_BUILTIN +int hex2bin_main(int argc, char **argv); +#endif /* CONFIG_SYSTEM_HEX2BIN_BUILTIN */ + +/**************************************************************************** + * Name: hex2mem_main + * + * Description: + * Main entry point when hex2mem is built as an NSH built-in task. + * + * Input Parameters: + * Standard task inputs + * + * Returned Value + * EXIT_SUCESS on success; EXIT_FAILURE on failure + * + ****************************************************************************/ + +#ifdef CONFIG_SYSTEM_HEX2MEM_BUILTIN +int hex2mem_main(int argc, char **argv); +#endif /* CONFIG_SYSTEM_HEX2MEM_BUILTIN */ + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* CONFIG_SYSTEM_HEX2BIN */ +#endif /* __INCLUDE_HEX2BIN_H */ diff --git a/include/nuttx/fs/fs.h b/include/nuttx/fs/fs.h index f1bc737ffe8b0a9477c69432f771108df1bbd5c2..f383c4ac06a40668d03aacf008555b9d2e2e4ce4 100644 --- a/include/nuttx/fs/fs.h +++ b/include/nuttx/fs/fs.h @@ -895,6 +895,26 @@ off_t file_seek(FAR struct file *filep, off_t offset, int whence); int file_fsync(FAR struct file *filep); #endif +/**************************************************************************** + * Name: file_ioctl + * + * Description: + * Perform device specific operations. + * + * Parameters: + * file File structure instance + * req The ioctl command + * arg The argument of the ioctl cmd + * + * Return: + * See ioctl() below. + * + ****************************************************************************/ + +#if CONFIG_NFILE_DESCRIPTORS > 0 +int file_ioctl(FAR struct file *filep, int req, unsigned long arg); +#endif + /**************************************************************************** * Name: file_vfcntl * diff --git a/include/nuttx/ioexpander/gpio.h b/include/nuttx/ioexpander/gpio.h index 1e5ae50cc739bc800422e33e816bf2e400facd1a..ce6e13794b779adee571773fdce6ca9c9e9975b2 100644 --- a/include/nuttx/ioexpander/gpio.h +++ b/include/nuttx/ioexpander/gpio.h @@ -78,19 +78,33 @@ struct gpio_common_dev_s struct gpio_input_dev_s { + /* Common fields */ + bool gpin_output; uint8_t gpin_unused[3]; - CODE int (*gpin_read)(FAR struct gpio_input_dev_s *dev); + + /* Fields unique to input pins */ + + CODE int (*gpin_read)(FAR struct gpio_input_dev_s *dev, FAR int *value); + + /* Lower-half private definitions may follow */ }; /* The interface to a GPIO input pin */ struct gpio_output_dev_s { + /* Common fields */ + bool gpout_output; uint8_t gpout_unused[3]; - CODE int (*gpout_read)(FAR struct gpio_output_dev_s *dev); + + /* Fields unique to output pins */ + + CODE int (*gpout_read)(FAR struct gpio_output_dev_s *dev, FAR int *value); CODE int (*gpout_write)(FAR struct gpio_output_dev_s *dev, int value); + + /* Lower-half private definitions may follow */ }; /**************************************************************************** diff --git a/include/nuttx/net/net.h b/include/nuttx/net/net.h index 4fadfd2c8fea2d2c0469b73e19a244c607292f5f..74abc0d701c58220c4534adaa33c3da2bb35ae3a 100644 --- a/include/nuttx/net/net.h +++ b/include/nuttx/net/net.h @@ -968,6 +968,39 @@ int psock_getsockopt(FAR struct socket *psock, int level, int option, int psock_setsockopt(FAR struct socket *psock, int level, int option, FAR const void *value, socklen_t value_len); +/**************************************************************************** + * Name: psock_ioctl + * + * Description: + * Perform network device specific operations. + * + * Parameters: + * psock A pointer to a NuttX-specific, internal socket structure + * cmd The ioctl command + * arg The argument of the ioctl cmd + * + * Return: + * >=0 on success (positive non-zero values are cmd-specific) + * On a failure, -1 is returned with errno set appropriately + * + * EBADF + * 'psock' is not a valid, connected socket structure. + * EFAULT + * 'arg' references an inaccessible memory area. + * ENOTTY + * 'cmd' not valid. + * EINVAL + * 'arg' is not valid. + * ENOTTY + * 'sockfd' is not associated with a network device. + * ENOTTY + * The specified request does not apply to the kind of object that the + * descriptor 'sockfd' references. + * + ****************************************************************************/ + +int psock_ioctl(FAR struct socket *psock, int cmd, unsigned long arg); + /**************************************************************************** * Name: netdev_ioctl * @@ -984,7 +1017,7 @@ int psock_setsockopt(FAR struct socket *psock, int level, int option, * On a failure, -1 is returned with errno set appropriately * * EBADF - * 'sockfd' is not a valid descriptor. + * 'sockfd' is not a valid socket descriptor. * EFAULT * 'arg' references an inaccessible memory area. * ENOTTY diff --git a/include/nuttx/syslog/syslog.h b/include/nuttx/syslog/syslog.h index fdb2794b79b5f711c5b7a9d033942a4335b0296e..01de19736d2f496242d9ef5b8ed7e32ff6340bf3 100644 --- a/include/nuttx/syslog/syslog.h +++ b/include/nuttx/syslog/syslog.h @@ -271,6 +271,24 @@ int syslog_flush(void); int _vsyslog(int priority, FAR const IPTR char *src, FAR va_list *ap); +/**************************************************************************** + * Name: syslog_register + * + * Description: + * Register a simple character driver at /dev/syslog whose write() method + * will transfer data to the SYSLOG device. This can be useful if, for + * example, you want to redirect the output of a program to the SYSLOG. + * + * NOTE that unlike other syslog output, this data is unformatted raw + * byte output with no time-stamping or any other SYSLOG features + * supported. + * + ****************************************************************************/ + +#ifdef CONFIG_SYSLOG_CHARDEV +void syslog_register(void); +#endif + #undef EXTERN #ifdef __cplusplus } diff --git a/include/nuttx/usb/usbmonitor.h b/include/nuttx/usb/usbmonitor.h new file mode 100644 index 0000000000000000000000000000000000000000..d5be243e0546592ab653206ec753c48dbbce74af --- /dev/null +++ b/include/nuttx/usb/usbmonitor.h @@ -0,0 +1,90 @@ +/**************************************************************************** + * include/nuttx/usb/usbmonitor.h + * + * Copyright (C) 2013, 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_USB_USBMONITOR_H +#define __INCLUDE_NUTTX_USB_USBMONITOR_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_USBMONITOR + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Name: usbmonitor_start and usbmonitor_stop + * + * Start and stop the USB monitor kernel deamon. + * + * Input Parameters: + * None + * + * Returned values: + * Zero (OK) is returned on success; a negated errno value is return on + * any failure. + * + ****************************************************************************/ + +int usbmonitor_start(void); +int usbmonitor_stop(void); + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* CONFIG_USBMONITOR */ +#endif /* __INCLUDE_NUTTX_USB_USBMONITOR_H */ diff --git a/include/nuttx/zoneinfo.h b/include/nuttx/zoneinfo.h new file mode 100644 index 0000000000000000000000000000000000000000..67f4214e0b3f5d28842a9354a11c71c4863946de --- /dev/null +++ b/include/nuttx/zoneinfo.h @@ -0,0 +1,83 @@ +/**************************************************************************** + * include/nuttx/zoneinfo.h + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_ZONEINFO_H +#define __INCLUDE_NUTTX_ZONEINFO_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#ifdef CONFIG_LIB_ZONEINFO_ROMFS + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/* If the TZ database is built as a ROMFS file system, then these variables + * provide (1) the address of the array in FLASH/ROM that contains the + * ROMFS file system image, and (2) the size of the ROMFS file system image + * in bytes. This is sufficient information to permit external logic to + * mount the ROMF file system. + */ + +EXTERN unsigned char romfs_zoneinfo_img[]; +EXTERN unsigned int romfs_zoneinfo_img_len; + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* CONFIG_LIB_ZONEINFO_ROMFS */ +#endif /* __INCLUDE_NUTTX_ZONEINFO_H */ diff --git a/include/signal.h b/include/signal.h index 7cfc93b136bb8393b815137891698d9b7bca7a8f..bd8ee9f31760c2157898394187b10a9e8c5de5b3 100644 --- a/include/signal.h +++ b/include/signal.h @@ -280,8 +280,9 @@ extern "C" #define EXTERN extern #endif -int kill(pid_t, int); -int sigaction(int sig, FAR const struct sigaction *act, +int kill(pid_t pid, int signo); +int raise(int signo); +int sigaction(int signo, FAR const struct sigaction *act, FAR struct sigaction *oact); int sigaddset(FAR sigset_t *set, int signo); int sigdelset(FAR sigset_t *set, int signo); @@ -290,7 +291,7 @@ int sigfillset(FAR sigset_t *set); int sighold(int signo); int sigismember(FAR const sigset_t *set, int signo); int sigignore(int signo); -CODE void (*signal(int sig, CODE void (*func)(int signo)))(int signo); +CODE void (*signal(int signo, CODE void (*func)(int signo)))(int signo); int sigprocmask(int how, FAR const sigset_t *set, FAR sigset_t *oset); int sigpause(int signo); int sigpending(FAR sigset_t *set); @@ -300,7 +301,7 @@ int sigqueue(int pid, int signo, union sigval value); int sigqueue(int pid, int signo, FAR void *sival_ptr); #endif int sigrelse(int signo); -CODE void (*sigset(int sig, CODE void (*func)(int signo)))(int signo); +CODE void (*sigset(int signo, CODE void (*func)(int signo)))(int signo); int sigtimedwait(FAR const sigset_t *set, FAR struct siginfo *value, FAR const struct timespec *timeout); int sigsuspend(FAR const sigset_t *sigmask); diff --git a/libc/Kconfig b/libc/Kconfig index 59f41f73eda601dc9677ecb25d628b04bf377910..4a2fa5ed49e8b5eaabce898b8385ea0ff97f3ec6 100644 --- a/libc/Kconfig +++ b/libc/Kconfig @@ -288,7 +288,7 @@ config LIBC_LOCALTIME environment variable TZ must be set to the name of that timezone file when tzset() is called. - See https://www.iana.org/time-zones . See also apps/system/zoneinfo + See https://www.iana.org/time-zones . See also nuttx/zoneinfo which provides a framework for incorporating the TZ database into a NuttX build. @@ -321,7 +321,23 @@ config LIBC_TZDIR This is the full path to the location where the TZ database is expected to be found. -endif +config LIB_ZONEINFO + bool "TZ database" + default n + ---help--- + Download and build the TZ/Olson database. + +if LIB_ZONEINFO + +config LIB_ZONEINFO_ROMFS + bool "Build ROMFS filesystem" + default n + depends on FS_ROMFS + ---help--- + Build a mountable ROMFS filesystem containing the TZ/Olson database + +endif # LIB_ZONEINFO +endif # LIBC_LOCALTIME config TIME_EXTENDED bool "Add day of week, year support" @@ -877,3 +893,10 @@ config LIB_SLCDCODEC include/nuttx/lcd/slcd_codec.h. While not correctly a part of the C library, it is included here because the encoding side of this interface must be accessible by end user programs. + +config LIB_HEX2BIN + bool "Intel HEX to binary conversion library" + default n + ---help--- + Build in support for conversions from Intel Hex format to binary. + This selection enables the interfaces of include/hex2bin.h. diff --git a/libc/Makefile b/libc/Makefile index f07366f07687fc4f519839f2ee8316323cd7a75c..1399de558a843918007e9acea1be41afeb549a0c 100644 --- a/libc/Makefile +++ b/libc/Makefile @@ -1,7 +1,7 @@ ############################################################################ # libc/Makefile # -# Copyright (C) 2007-2014 Gregory Nutt. All rights reserved. +# Copyright (C) 2007-2014, 2016 Gregory Nutt. All rights reserved. # Author: Gregory Nutt # # Redistribution and use in source and binary forms, with or without @@ -65,6 +65,7 @@ include aio/Make.defs include audio/Make.defs include dirent/Make.defs include fixedmath/Make.defs +include hex2bin/Make.defs include libgen/Make.defs include math/Make.defs include misc/Make.defs @@ -116,6 +117,9 @@ $(COBJS): $(BINDIR)$(DELIM)%$(OBJEXT): %.c $(BIN): $(OBJS) $(call ARCHIVE, $@, $(OBJS)) +ifeq ($(CONFIG_LIB_ZONEINFO_ROMFS),y) + $(Q) $(MAKE) -C zoneinfo all TOPDIR=$(TOPDIR) BIN=$(BIN) +endif # C library for the user phase of the two-pass kernel build @@ -131,6 +135,13 @@ $(KBIN): $(Q) $(MAKE) $(KBIN) BIN=$(KBIN) BINDIR=kbin TOPDIR=$(TOPDIR) EXTRADEFINES=$(EXTRADEFINES) endif +# Context + +context: +ifeq ($(CONFIG_LIB_ZONEINFO_ROMFS),y) + $(Q) $(MAKE) -C zoneinfo context TOPDIR=$(TOPDIR) BIN=$(BIN) +endif + # Dependencies .depend: Makefile $(SRCS) @@ -139,6 +150,9 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y) $(Q) $(MKDEP) --obj-path kbin --obj-suffix $(OBJEXT) $(DEPPATH) "$(CC)" -- $(CFLAGS) $(KDEFINE) -- $(SRCS) >Make_kbin.dep else $(Q) $(MKDEP) --obj-path bin --obj-suffix $(OBJEXT) $(DEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make_bin.dep +endif +ifeq ($(CONFIG_LIB_ZONEINFO_ROMFS),y) + $(Q) $(MAKE) -C zoneinfo depend TOPDIR=$(TOPDIR) BIN=$(BIN) endif $(Q) touch $@ @@ -150,6 +164,7 @@ clean: $(Q) $(MAKE) -C bin clean TOPDIR=$(TOPDIR) $(Q) $(MAKE) -C ubin clean TOPDIR=$(TOPDIR) $(Q) $(MAKE) -C kbin clean TOPDIR=$(TOPDIR) + $(Q) $(MAKE) -C zoneinfo clean TOPDIR=$(TOPDIR) BIN=$(BIN) $(call DELFILE, $(BIN)) $(call DELFILE, $(UBIN)) $(call DELFILE, $(KBIN)) @@ -161,6 +176,7 @@ distclean: clean $(Q) $(MAKE) -C bin distclean TOPDIR=$(TOPDIR) $(Q) $(MAKE) -C ubin distclean TOPDIR=$(TOPDIR) $(Q) $(MAKE) -C kbin distclean TOPDIR=$(TOPDIR) + $(Q) $(MAKE) -C zoneinfo distclean TOPDIR=$(TOPDIR) BIN=$(BIN) $(call DELFILE, Make_bin.dep) $(call DELFILE, Make_ubin.dep) $(call DELFILE, Make_kbin.dep) diff --git a/libc/README.txt b/libc/README.txt index 6ccc1dd53bc3685b0baa02789c35f331e04b86e6..4b329205ebf4255c1d34f4b30d21c6c9b4bac331 100644 --- a/libc/README.txt +++ b/libc/README.txt @@ -28,7 +28,8 @@ The files in the libc/ directory are organized (mostly) according which file in the include/ directory provides the prototype for library functions. So we have: - audio - This part of the audio system: nuttx/audio/audio.h + audio - This part of he audio system: nuttx/audio/audio.h + hex2bin - hex2bin.h libgen - libgen.h fixedmath - fixedmath.h math - math.h @@ -43,6 +44,9 @@ we have: time - time.h unistd - unistd.h +Most of these are "standard" header files; some are not: hex2bin.h and +fixemath.h are non-standard. + There is also a misc/ subdirectory that contains various internal functions and interfaces from header files that are too few to warrant their own sub- directory: diff --git a/libc/hex2bin/Make.defs b/libc/hex2bin/Make.defs new file mode 100644 index 0000000000000000000000000000000000000000..e1ce1f5d46d3bd5ab9d8f23a5673cc7d8bd247c9 --- /dev/null +++ b/libc/hex2bin/Make.defs @@ -0,0 +1,47 @@ +############################################################################ +# libc/hex2bin/Make.defs +# +# Copyright (C) 2016 Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +ifeq ($(CONFIG_LIB_HEX2BIN),y) + +# Add the hex2bin sources to the build + +CSRCS += lib_fhex2mem.c lib_hex2bin.c lib_hex2mem.c + +# Add the hex2bin directory to the build + +DEPPATH += --dep-path hex2bin +VPATH += :hex2bin + +endif diff --git a/libc/hex2bin/lib_fhex2mem.c b/libc/hex2bin/lib_fhex2mem.c new file mode 100644 index 0000000000000000000000000000000000000000..1967dd1adeb6faf90245ebb87853ca6497f9d203 --- /dev/null +++ b/libc/hex2bin/lib_fhex2mem.c @@ -0,0 +1,103 @@ +/**************************************************************************** + * libc/hex2bin/fhex2mem.c + * + * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#ifdef CONFIG_LIB_HEX2BIN + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name fhex2mem + * + * Description: + * Read the Intel HEX ASCII data provided on the standard stream + * 'instream' and write the binary to memory. + * + * If, for example, instream is stdin, then the HEX ASCII data would be + * taken from the console and written to memory. + * + * Input Parameters: + * instream - The incoming standard stream from which Intel HEX data + * will be received. + * baseaddr - The base address of the memory region stream. + * endpaddr - The end address (plus 1) of the memory region. + * swap - Controls byte ordering. See enum hex2bin_swap_e for + * description of the values. + * + * Returned Value + * Zero (OK) is returned on success; a negated errno value is returned on + * failure. + * + ****************************************************************************/ + +int fhex2mem(FAR FILE *instream, uint32_t baseaddr, uint32_t endpaddr, + enum hex2bin_swap_e swap) +{ + struct lib_stdinstream_s stdinstream; + struct lib_memsostream_s memoutstream; + + /* Check memory addresses */ + + DEBUGASSERT(instream != NULL && endpaddr > baseaddr); + + /* Wrap the file descriptor as raw stream; wrap the memory as a memory + * stream. + */ + + lib_stdinstream(&stdinstream, instream); + lib_memsostream(&memoutstream, (FAR char *)baseaddr, + (int)(endpaddr - baseaddr)); + + /* And do the deed */ + + return hex2bin(&stdinstream.public, &memoutstream.public, + (uint32_t)baseaddr, (uint32_t)endpaddr, + (enum hex2bin_swap_e)swap); +} + +#endif /* CONFIG_LIB_HEX2BIN */ diff --git a/libc/hex2bin/lib_hex2bin.c b/libc/hex2bin/lib_hex2bin.c new file mode 100644 index 0000000000000000000000000000000000000000..2dc5d32d97b7175e62ba511911e296f357354b66 --- /dev/null +++ b/libc/hex2bin/lib_hex2bin.c @@ -0,0 +1,705 @@ +/**************************************************************************** + * libc/hex2bin/hex2bin.c + * + * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * References: + * - http://en.wikipedia.org/wiki/Intel_HEX + * - Hexadecimal Object File Format Specification, Revision A January 6, + * 1988, Intel + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include + +#include + +#ifdef CONFIG_LIB_HEX2BIN + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* ASCII record sizes */ + +#define BYTECOUNT_ASCSIZE 2 +#define ADDRESS_ASCSIZE 4 +#define RECTYPE_ASCSIZE 2 + +#define BYTECOUNT_LINENDX (0) +#define ADDRESS_LINENDX (BYTECOUNT_LINENDX + BYTECOUNT_ASCSIZE) +#define RECTYPE_LINENDX (ADDRESS_LINENDX + ADDRESS_ASCSIZE) +#define DATA_LINENDX (RECTYPE_LINENDX + RECTYPE_ASCSIZE) +#define HEADER_ASCSIZE DATA_LINENDX + +#define CHECKSUM_ASCSIZE 2 +#define TRAILER_SIZE (CHECKSUM_ASCSIZE) + +#define MAXDATA_BINSIZE 255 +#define RECORD_ASCSIZE(n) (HEADER_ASCSIZE + TRAILER_SIZE + 2*(n)) +#define MAXRECORD_ASCSIZE RECORD_ASCSIZE(MAXDATA_BINSIZE) +#define MINRECORD_ASCSIZE RECORD_ASCSIZE(0) +#define LINE_ALLOC MAXRECORD_ASCSIZE + +/* Binary record sizes */ + +#define BYTECOUNT_BINSIZE 1 +#define ADDRESS_BINSIZE 2 +#define RECTYPE_BINSIZE 1 + +#define BYTECOUNT_BINNDX (0) +#define ADDRESS_BINNDX (BYTECOUNT_BINNDX + BYTECOUNT_BINSIZE) +#define RECTYPE_BINNDX (ADDRESS_BINNDX + ADDRESS_BINSIZE) +#define DATA_BINNDX (RECTYPE_BINNDX + RECTYPE_BINSIZE) +#define HEADER_BINSIZE DATA_BINNDX + +#define CHECKSUM_BINSIZE 1 +#define TRAILER_BINSIZE CHECKSUM_BINSIZE + +#define RECORD_BINSIZE(n) (HEADER_BINSIZE + TRAILER_BINSIZE + (n)) +#define MAXRECORD_BINSIZE RECORD_BINSIZE(MAXDATA_BINSIZE) +#define MINRECORD_BKINSIZE RECORD_BINSIZE(0) +#define BIN_ALLOC MAXRECORD_BINSIZE + +/* Record start code */ + +#define RECORD_STARTCODE ':' + +/* Record Types */ + +#define RECORD_DATA 0 /* Data */ +#define RECORD_EOF 1 /* End of file */ +#define RECORD_EXT_SEGADDR 2 /* Extended segment address record */ +#define RECORD_START_SEGADDR 3 /* Start segment address record */ +#define RECORD_EXT_LINADDR 4 /* Extended linear address record */ +#define RECORD_START_LINADDR 5 /* Start linear address record */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: nibble2bin + ****************************************************************************/ + +static int nibble2bin(uint8_t ascii) +{ + if (ascii >= '0' && ascii <= '9') + { + return (ascii - 0x30); + } + else if (ascii >= 'a' && ascii <= 'f') + { + return (ascii - 'a' + 10); + } + else if (ascii >= 'A' && ascii <= 'F') + { + return (ascii - 'A' + 10); + } + + return -EINVAL; +} + +/**************************************************************************** + * Name: byte2bin + ****************************************************************************/ + +static int byte2bin(FAR const uint8_t *ascii) +{ + int nibble; + int byte; + + /* Get the MS nibble (big endian order) */ + + nibble = nibble2bin(*ascii++); + if (nibble < 0) + { + return nibble; + } + + byte = (nibble << 4); + + /* Get the MS nibble */ + + nibble = nibble2bin(*ascii); + if (nibble < 0) + { + return nibble; + } + + byte |= nibble; + return byte; +} + +/**************************************************************************** + * Name: word2bin + ****************************************************************************/ + +#if 0 /* Not used */ +static int word2bin(FAR const char *ascii) +{ + int byte; + int word; + + /* Get the MS byte (big endian order) */ + + byte = word2bin(ascii); + if (byte < 0) + { + return byte; + } + + word = (byte << 8); + + /* Get the MS byte */ + + byte = word2bin(ascii + 2); + if (byte < 0) + { + return byte; + } + + word |= byte; + return word; +} +#endif + +/**************************************************************************** + * Name: data2bin + ****************************************************************************/ + +int data2bin(FAR uint8_t* dest, FAR const uint8_t *src, int nsrcbytes) +{ + int byte; + + /* An even number of source bytes is expected */ + + if ((nsrcbytes & 1) != 0) + { + return -EINVAL; + } + + /* Convert src bytes in groups of 2, writing one byte to the output on each + * pass through the loop. */ + + while (nsrcbytes > 0) + { + /* Get the MS nibble (big endian order) */ + + byte = byte2bin(src); + if (byte < 0) + { + return byte; + } + + src += 2; + + /* And write the byte to the destination */ + + *dest++ = byte; + nsrcbytes -= 2; + } + + return OK; +} + +/**************************************************************************** + * Name: readstream + ****************************************************************************/ + +static int readstream(FAR struct lib_instream_s *instream, + FAR uint8_t *line, unsigned int lineno) +{ + int nbytes = 0; + int ch; + + /* Skip until the beginning of line start code is encountered */ + + ch = instream->get(instream); + while (ch != RECORD_STARTCODE && ch != EOF) + { + ch = instream->get(instream); + } + + /* Skip over the startcode */ + + if (ch != EOF) + { + ch = instream->get(instream); + } + + /* Then read, verify, and buffer until the end of line is encountered */ + + while (ch != EOF && nbytes < (MAXRECORD_ASCSIZE-1)) + { +#if defined(CONFIG_EOL_IS_LF) + if (ch == '\n') + { + *line = '\0'; + return nbytes; + } + +#elif defined(CONFIG_EOL_IS_BOTH_CRLF) + if (ch == '\r') + { + continue; + } + else if (ch == '\n') + { + *line = '\0'; + return nbytes; + } +#elif defined(CONFIG_EOL_IS_CR) + if (ch == '\r') + { + *line = '\0'; + return nbytes; + } +#elif defined(CONFIG_EOL_IS_EITHER_CRLF) + if (ch == '\n' || ch == '\r') + { + *line = '\0'; + return nbytes; + } +#endif + /* Only hex data goes into the line buffer */ + + else if (isxdigit(ch)) + { + *line++ = ch; + nbytes++; + } + else if (!isspace(ch)) /* Not expected */ + { + lerr("Line %u ERROR: Unexpected character %c[%02x] in stream\n", + lineno, isprint(ch) ? ch : '.', ch); + break; + } + + /* Read the next character from the input stream */ + + ch = instream->get(instream); + } + + /* Some error occurred: Unexpected EOF, line too long, or bad character in + * stream + */ + + lerr("Line %u ERROR: Failed to read line. %d characters read\n", + lineno, nbytes); + return EOF; +} + +/**************************************************************************** + * Name: hex2bin_swap16 and hex2bin_swap32 + ****************************************************************************/ + +static inline void hex2bin_swap16(FAR uint8_t *data, int bytecount) +{ + for (; bytecount > 0; bytecount -= 2) + { + uint8_t b0 = data[0]; + uint8_t b1 = data[1]; + + *data++ = b1; + *data++ = b0; + } +} + +static inline void hex2bin_swap32(FAR uint8_t *data, int bytecount) +{ + for (; bytecount > 0; bytecount -= 4) + { + uint8_t b0 = data[0]; + uint8_t b1 = data[1]; + uint8_t b2 = data[2]; + uint8_t b3 = data[3]; + + *data++ = b3; + *data++ = b2; + *data++ = b1; + *data++ = b0; + } +} + +/**************************************************************************** + * Name: writedata + ****************************************************************************/ + +static inline void writedata(FAR struct lib_sostream_s *outstream, + FAR uint8_t *data, int bytecount) +{ + for (; bytecount > 0; bytecount--) + { + outstream->put(outstream, *data++); + } +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: hex2bin + * + * Description: + * Read the Intel HEX ASCII data provided on the serial IN stream and write + * the binary to the seek-able serial OUT stream. + * + * These streams may be files or, in another usage example, the IN stream + * could be a serial port and the OUT stream could be a memory stream. This + * would decode and write the serial input to memory. + * + * Input Parameters: + * instream - The incoming stream from which Intel HEX data will be + * received. + * outstream - The outgoing stream in which binary data will be written. + * baseaddr - The base address of the outgoing stream. Seeking in the + * output stream will be relative to this address. + * endpaddr - The end address (plus 1) of the outgoing stream. This + * value is used only for range checking. endpaddr must + * be larger than baseaddr. A zero value for endpaddr + * disables range checking. + * swap - Controls byte ordering. See enum hex2bin_swap_e for + * description of the values. + * + * Returned Value + * Zero (OK) is returned on success; a negated errno value is returned on + * failure. + * + ****************************************************************************/ + +int hex2bin(FAR struct lib_instream_s *instream, + FAR struct lib_sostream_s *outstream, uint32_t baseaddr, + uint32_t endpaddr, enum hex2bin_swap_e swap) +{ + FAR uint8_t *alloc; + FAR uint8_t *line; + FAR uint8_t *bin; + int nbytes; + int bytecount; + uint32_t address; + uint32_t endaddr; + uint32_t expected; + uint16_t extension; + uint16_t address16; + uint8_t checksum; + unsigned int lineno; + int i; + int ret = OK; + + /* Allocate buffer memory */ + + alloc = (FAR uint8_t *)malloc(LINE_ALLOC + BIN_ALLOC); + if (alloc == NULL) + { + lerr("ERROR: Failed to allocate memory\n"); + return -ENOMEM; + } + + line = alloc; + bin = &alloc[LINE_ALLOC]; + + extension = 0; + expected = 0; + lineno = 0; + + while ((nbytes = readstream(instream, line, lineno)) != EOF) + { + /* Increment the line number */ + + lineno++; + + /* Did we read enough data to do anything? */ + + if (nbytes < MINRECORD_ASCSIZE) + { + lerr("Line %u ERROR: Record too short: %d\n", lineno, nbytes); + goto errout_with_einval; + } + + /* We should always read an even number of bytes */ + + if ((nbytes & 1) != 0) + { + lerr("Line %u ERROR: Record length is odd: %d\n", lineno, nbytes); + goto errout_with_einval; + } + + /* Get the data byte count */ + + bytecount = byte2bin(&line[BYTECOUNT_LINENDX]); + if (bytecount < 0) + { + lerr("Line %u ERROR: Failed to read bytecount: %d\n", + lineno, bytecount); + ret = bytecount; + goto errout_with_buffers; + } + + /* Verify that the bytecount matches the length of the record */ + + if (RECORD_ASCSIZE(bytecount) != nbytes) + { + lerr("Line %u ERROR: Expected %d bytes, read %d\n", + lineno, RECORD_ASCSIZE(bytecount), nbytes); + goto errout_with_einval; + } + + /* Convert the entire line to binary. We need to do this for + * checksum calculation which includes the entire line (minus + * the start code and the checksum at the end of the line itself) + */ + + ret = data2bin(bin, line, nbytes); + if (ret < 0) + { + lerr("Line %u ERROR: Failed to convert line to binary: %d\n", + lineno, ret); + goto errout_with_buffers; + } + + /* Calculate and verify the checksum over all of the data */ + + nbytes >>= 1; /* Number of bytes in bin[] */ + checksum = 0; + + for (i = 0; i < nbytes; i++) + { + checksum += bin[i]; + } + + if (checksum != 0) + { + lerr("Line %u ERROR: Bad checksum %02x\n", lineno, checksum); + goto errout_with_einval; + } + + /* Get the 16-bit (unextended) address from the record */ + + address16 = (uint16_t)bin[ADDRESS_BINNDX] << 8 | + (uint16_t)bin[ADDRESS_BINNDX+1]; + + /* Handle the record by its record type */ + + switch (bin[RECTYPE_BINNDX]) + { + case RECORD_DATA: /* Data */ + { + /* Swap data in place in the binary buffer as required */ + + switch (swap) + { + case HEX2BIN_NOSWAP: /* No swap, stream is the correct byte order */ + break; + + case HEX2BIN_SWAP16: /* Swap bytes in 16-bit values */ + { + if ((bytecount & 1) != 0) + { + lerr("Line %d ERROR: Byte count %d is not a multiple of 2\n", + lineno, bytecount); + goto errout_with_einval; + } + + /* Do the byte swap */ + + hex2bin_swap16(&bin[DATA_BINNDX], bytecount); + } + break; + + case HEX2BIN_SWAP32: /* Swap bytes in 32-bit values */ + { + if ((bytecount & 3) != 0) + { + lerr("Line %d ERROR: Byte count %d is not a multiple of 4\n", + lineno, bytecount); + goto errout_with_einval; + } + + /* Do the byte swap */ + + hex2bin_swap32(&bin[DATA_BINNDX], bytecount); + } + break; + + default: + { + lerr("ERROR: Invalid swap argument: %d\n", swap); + goto errout_with_einval; + } + } + + /* Get and verify the full 32-bit address */ + + address = ((uint32_t)extension << 16) | (uint32_t)address16; + endaddr = address + bytecount; + + if (address < baseaddr || (endpaddr != 0 && endaddr >= endpaddr)) + { + lerr("Line %d ERROR: Extended address %08lx is out of range\n", + lineno, (unsigned long)address); + goto errout_with_einval; + } + + /* Seek to the correct position in the OUT stream if we have + * made an unexpected jump in the data address. + */ + + if (address != expected) + { + off_t pos = outstream->seek(outstream, address - baseaddr, SEEK_SET); + if (pos == (off_t)-1) + { + lerr("Line %u ERROR: Seek to address %08lu failed\n", + lineno, (unsigned long)address); + ret = -ESPIPE; + goto errout_with_buffers; + } + } + + /* Transfer data to the OUT stream */ + + writedata(outstream, &bin[DATA_BINNDX], bytecount); + + /* This is the next data address that we expect to see */ + + expected = address + bytecount; + } + break; + + case RECORD_EOF: /* End of file */ + /* End Of File record. Must occur exactly once per file in the + * last line of the file. The byte count is 00 and the data field + * is empty. Usually the address field is also 0000. + */ + + if (bytecount == 0) + { + ret = OK; + goto exit_with_buffers; + } + + lerr("Line %u ERROR: Nonzero bytecount %d in EOF\n", + lineno, bytecount); + goto errout_with_einval; + + case RECORD_EXT_SEGADDR: /* Extended segment address record */ + /* The address specified by the data field is multiplied by 16 + * (shifted 4 bits left) and added to the subsequent data record + * addresses. This allows addressing of up to a megabyte of + * address space. The address field of this record has to be + * 0000, the byte count is 02 (the segment is 16-bit). The + * least significant hex digit of the segment address is always + * 0. + */ + + if (bytecount != 2 || address16 != 0 || bin[DATA_BINNDX+1] != 0) + { + lerr("Line %u ERROR: Invalid segment address\n", lineno); + lerr(" bytecount=%d address=%04x segment=%02x%02x\n", + bytecount, address16, bin[DATA_BINNDX], + bin[DATA_BINNDX+1]); + goto errout_with_einval; + } + + extension = (uint16_t)bin[DATA_BINNDX]; + break; + + case RECORD_START_SEGADDR: /* Start segment address record */ + /* For 80x86 processors, it specifies the initial content of + * the CS:IP registers. The address field is 0000, the byte + * count is 04, the first two bytes are the CS value, the + * latter two are the IP value. + */ + + break; + + case RECORD_EXT_LINADDR: /* Extended linear address record */ + /* The address field is 0000, the byte count is 02. The two + * data bytes (two hex digit pairs in big endian order) + * represent the upper 16 bits of the 32 bit address for + * all subsequent 00 type records until the next 04 type + * record comes. If there is not a 04 type record, the + * upper 16 bits default to 0000. To get the absolute + * address for subsequent 00 type records, the address + * specified by the data field of the most recent 04 record + * is added to the 00 record addresses. + */ + + if (bytecount != 2 || address16 != 0) + { + lerr("Line %u ERROR: Invalid linear address\n", lineno); + lerr(" bytecount=%d address=%04x\n", bytecount, address16); + goto errout_with_einval; + } + + extension = (uint16_t)bin[DATA_BINNDX] << 8 | + (uint16_t)bin[DATA_BINNDX+1]; + break; + + case RECORD_START_LINADDR: /* Start linear address record */ + /* The address field is 0000, the byte count is 04. The 4 + * data bytes represent the 32-bit value loaded into the EIP + * register of the 80386 and higher CPU. + */ + + break; + + default: + break; + } + } + + lerr("ERROR: No EOF record found\n"); + +errout_with_einval: + ret = -EINVAL; + +errout_with_buffers: +exit_with_buffers: + free(alloc); + return ret; +} + +#endif /* CONFIG_LIB_HEX2BIN */ diff --git a/libc/hex2bin/lib_hex2mem.c b/libc/hex2bin/lib_hex2mem.c new file mode 100644 index 0000000000000000000000000000000000000000..12c284cf5403019affd8a71af7b577293389434e --- /dev/null +++ b/libc/hex2bin/lib_hex2mem.c @@ -0,0 +1,103 @@ +/**************************************************************************** + * libc/hex2bin/hex2mem.c + * + * Copyright (C) 2014, 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include + +#ifdef CONFIG_LIB_HEX2BIN + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name hex2mem + * + * Description: + * Read the Intel HEX ASCII data provided on the file descriptor 'fd' and + * write the binary to memory. + * + * If, for example, fd is zero (stdin), then the HEX ASCII data would be + * taken from the console and written to memory. + * + * Input Parameters: + * fd - The file descriptor from which Intel HEX data will be + * received. + * baseaddr - The base address of the memory region stream. + * endpaddr - The end address (plus 1) of the memory region. + * swap - Controls byte ordering. See enum hex2bin_swap_e for + * description of the values. + * + * Returned Value + * Zero (OK) is returned on success; a negated errno value is returned on + * failure. + * + ****************************************************************************/ + +int hex2mem(int fd, uint32_t baseaddr, uint32_t endpaddr, + enum hex2bin_swap_e swap) +{ + struct lib_rawinstream_s rawinstream; + struct lib_memsostream_s memoutstream; + + /* Check memory addresses */ + + DEBUGASSERT(fd >= 0 && endpaddr > baseaddr); + + /* Wrap the file descriptor as raw stream; wrap the memory as a memory + * stream. + */ + + lib_rawinstream(&rawinstream, fd); + lib_memsostream(&memoutstream, (FAR char *)baseaddr, + (int)(endpaddr - baseaddr)); + + /* And do the deed */ + + return hex2bin(&rawinstream.public, &memoutstream.public, + (uint32_t)baseaddr, (uint32_t)endpaddr, + (enum hex2bin_swap_e)swap); +} + +#endif /* CONFIG_LIB_HEX2BIN */ diff --git a/libc/signal/Make.defs b/libc/signal/Make.defs index 0c642ff8c75458fa6343fddef8f62d8770e56ef3..bedee1895e8be3d5701a87c1452cbb3fcdd30781 100644 --- a/libc/signal/Make.defs +++ b/libc/signal/Make.defs @@ -37,9 +37,9 @@ ifneq ($(CONFIG_DISABLE_SIGNALS),y) # Add the signal C files to the build -CSRCS += sig_emptyset.c sig_fillset.c sig_addset.c sig_delset.c -CSRCS += sig_ismember.c sig_hold.c sig_relse.c sig_ignore.c sig_pause.c -CSRCS += sig_set.c signal.c +CSRCS += sig_addset.c sig_delset.c sig_emptyset.c sig_fillset.c +CSRCS += sig_hold.c sig_ignore.c sig_ismember.c sig_pause.c sig_raise.c +CSRCS += sig_relse.c sig_set.c signal.c # Add the signal directory to the build diff --git a/libc/signal/sig_raise.c b/libc/signal/sig_raise.c new file mode 100644 index 0000000000000000000000000000000000000000..e2e1b326541ab67ec9e8e2842bf9be021996c91c --- /dev/null +++ b/libc/signal/sig_raise.c @@ -0,0 +1,88 @@ +/**************************************************************************** + * libc/signal/sig_raise.c + * + * Copyright (C) 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: sig_raise + * + * Description: + * The raise() function sends the signal signo to the executing thread or + * process. If a signal handler is called, the raise() function does not + * return until after the signal handler does. + * + * If the implementation supports the Threads option, the effect of the + * raise() function is equivalent to calling: + * + * pthread_kill(pthread_self(), signo); + * + * except that on failures, -1 (ERROR) is returned and the errno() variable + * is set accordingly. Otherwise, the effect of the raise() function is + * equivalent to calling: + * + * kill(getpid(), signo) + * + ****************************************************************************/ + +int raise(int signo) +{ +#ifndef CONFIG_DISABLE_PTHREAD + int errcode = pthread_kill(pthread_self(), signo); + if (errcode != OK) + { + DEBUGASSERT(errcode > 0); + set_errno(errcode); + return ERROR; + } + + return OK; + +#else + return kill(getpid(), signo); +#endif +} diff --git a/libc/zoneinfo/.gitignore b/libc/zoneinfo/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..91d1ddb7d02d65c013b294e51d78ae1648e94a8e --- /dev/null +++ b/libc/zoneinfo/.gitignore @@ -0,0 +1,10 @@ +/.built +/.tzbuilt +/.tzunpack +/romfs_zoneinfo.img +/romfs_zoneinfo.h +/tzbin +/tzcode-latest.tar.gz +/tzcode +/tzdata-latest.tar.gz + diff --git a/libc/zoneinfo/Makefile b/libc/zoneinfo/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..2be9c649a1056179008c11d9f768d3e0623b20bd --- /dev/null +++ b/libc/zoneinfo/Makefile @@ -0,0 +1,157 @@ +############################################################################ +# libc/zoneinfo/Makefile +# +# Copyright (C) 2015-2016, Gregory Nutt. All rights reserved. +# Author: Gregory Nutt +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/.config +-include $(TOPDIR)/Make.defs + +ifeq ($(WINTOOL),y) +INCDIROPT = -w +endif + +# Zoneinfo database + +ASRCS = +CSRCS = + +ifeq ($(CONFIG_LIB_ZONEINFO_ROMFS),y) +CSRCS += tzromfs.c +endif + +AOBJS = $(ASRCS:.S=$(OBJEXT)) +COBJS = $(CSRCS:.c=$(OBJEXT)) + +SRCS = $(ASRCS) $(CSRCS) +OBJS = $(AOBJS) $(COBJS) + +ZONEINFO_PATH = $(TOPDIR)/libc/zoneinfo +TZBIN_PATH = $(ZONEINFO_PATH)/tzbin +TZCODE_PATH = $(ZONEINFO_PATH)/tzcode + +ROOTDEPPATH = --dep-path . + +# Common build + +VPATH = + +all: .built +.PHONY: romfs register context depend clean distclean + +$(AOBJS): %$(OBJEXT): %.S + $(call ASSEMBLE, $<, $@) + +$(COBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +.built: .tzbuilt romfs $(OBJS) + $(call ARCHIVE, ..$(DELIM)$(BIN), $(OBJS)) + $(Q) touch .built + +# ROMFS file system containing the TZ database + +ifeq ($(CONFIG_LIB_ZONEINFO_ROMFS),y) + +checkgenromfs: + @genromfs -h 1>/dev/null 2>&1 || { \ + echo "Host executable genromfs not available in PATH"; \ + echo "You may need to download in from http://romfs.sourceforge.net/"; \ + exit 1; \ + } + +romfs_zoneinfo.img : checkgenromfs .tzbuilt + @genromfs -f $@ -d $(TZBIN_PATH)/etc/zoneinfo -V "TZDatbase" || { echo "genromfs failed" ; exit 1 ; } + +romfs_zoneinfo.h : romfs_zoneinfo.img + @xxd -i $< >$@ || { echo "xxd of $< failed" ; exit 1 ; } + +romfs: romfs_zoneinfo.h + +else + +romfs: + +endif # CONFIG_LIB_ZONEINFO_ROMFS + +# Build TZ database + +tzcode: + mkdir tzcode + +tzbin: + mkdir tzbin + +tzcode-latest.tar.gz: + $(Q) wget --retr-symlinks ftp://ftp.iana.org/tz/tzcode-latest.tar.gz + +tzdata-latest.tar.gz: + $(Q) wget --retr-symlinks ftp://ftp.iana.org/tz/tzdata-latest.tar.gz + +.tzunpack: tzcode tzcode-latest.tar.gz tzdata-latest.tar.gz + $(Q) tar zx -C tzcode -f tzcode-latest.tar.gz + $(Q) tar zx -C tzcode -f tzdata-latest.tar.gz + $(Q) touch .tzunpack + +.tzbuilt: tzcode tzbin .tzunpack + $(Q) $(MAKE) -C tzcode TOPDIR=$(TZBIN_PATH) install + $(Q) touch .tzbuilt + +# Create initial context + +context: .tzbuilt romfs + +# Create dependencies + +.depend: Makefile $(SRCS) + $(Q) $(MKDEP) $(ROOTDEPPATH) "$(CC)" -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) touch $@ + +depend: .depend + +clean: + $(call DELFILE, .built) + $(call CLEAN) + +distclean: clean + $(call DELFILE, Make.dep) + $(call DELFILE, .depend) + $(call DELFILE, .tzunpack) + $(call DELFILE, .tzbuilt) + $(call DELFILE, romfs_zoneinfo.img) + $(call DELFILE, romfs_zoneinfo.h) + $(call DELFILE, tzdata-latest.tar.gz) + $(call DELFILE, tzcode-latest.tar.gz) + $(call DELDIR, tzbin) + $(call DELDIR, tzcode) + +-include Make.dep diff --git a/libc/zoneinfo/README.txt b/libc/zoneinfo/README.txt new file mode 100644 index 0000000000000000000000000000000000000000..7aea826ea8baab0fc737ca5e244f8d75ad361bd2 --- /dev/null +++ b/libc/zoneinfo/README.txt @@ -0,0 +1,180 @@ +apps/system/zoninfo/README.txt +Author: Gregory Nutt + +Directory Contents +================== + +This directory contains logic to create a version of the TZ/Olson database. +This database is required if localtime() support is selected via +CONFIG_LIBC_LOCALTIME. This logic in this directory does the following: + + - It downloads the current TZ database from the IANA website + - It downloads the current timezone tools from the same location + - It builds the tools and constructs the binary TZ database + - It will then, optionally, build a ROMFS filesystem image containing + the data base. + +Creating and Mounting a ROMFS TZ Database +========================================= + +The ROMFS filesystem image can that be mounted during the boot-up sequence +so that it is available for the localtime() logic. There are two steps to +doing this: + + - First, a ROM disk device must be created. This is done by calling + the function romdisk_register() as described in + nuttx/include/nuttx/fs/ramdisk.h. This is an OS level operation + and must be done in the board-level logic before your application + starts. + + romdisk_register() will create a block driver at /dev/ramN where N + is the device minor number that was provided to romdisk_regsiter. + + - The second step is to mount the file system. This step can be + performed either in your board configuration logic or by your + application using the mount() interface described in + nuttx/include/sys/mount.h. + + These steps, however, must be done very early in initialization, + before there is any need for time-related services. + +Both of these steps are shown together in the following code sample at the +end of this README file. + +Example Configuration +===================== + +I have tested this using the sim/nsh configuration. Here are the +modifications to the configuration that I used for testing: + + CONFIG_BOARD_INITIALIZE=y + + CONFIG_LIBC_LOCALTIME=y + CONFIG_LIBC_TZDIR="/share/zoneinfo" + CONFIG_LIBC_TZ_MAX_TIMES=370 + CONFIG_LIBC_TZ_MAX_TYPES=20 + + CONFIG_LIB_ZONEINFO=y + CONFIG_LIB_ZONEINFO_ROMFS=y + +NOTE: The full TZ database is quite large. To create a reasonable sized +ROMFS image, I had to trim some of the files like this: + + cd nuttx + cd tools + ./configure.sh sim/nsh + cd .. + make menuconfig + +Select the above localtime() and nuttx/zoneinfo configuration settings. +Then: + + make context + cd ../nuttx/zoneinfo/tzbin/etc/zoneinfo + +Remove as many timezone files as you can. Do not remove the GMT, localtime, +or posixrules files. Those might be needed in any event. Then you can +force rebuilding of the ROMFS filesystem be removing some files: + + cd ../../.. + rm romfs_zoneinfo.* + rm *.o + cd ../../nuttx + make + +If you have problems building the simulator on your platform, check out +nuttx/configs/sim/README.txt. You might find some help there. + +Here is a sample run. I have not seen any errors in single stepping through +the logic but neither am I certain that everything is working properly: + + NuttShell (NSH) + nsh> date + Jul 01 00:00:02 2008 + nsh> set TZ US/Mountain + nsh> date -s "Apr 11 11:53:00 2015" + nsh> date + Apr 11 17:53:00 2015 + +NOTE: Because of daylight savings time, US/Mountain is GMT-6 on Apr 11. The +above suggests that perhaps the NSH data command may be setting local time, +but printing GMT time? + +Sample Code to Mount the ROMFS Filesystem +========================================= + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include + +#include +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#ifndef CONFIG_LIBC_TZDIR +# errror CONFIG_LIBC_TZDIR is not defined +#endif + +#ifdef CONFIG_DISABLE_MOUNTPOINT +# error "Mountpoint support is disabled" +#endif + +#if CONFIG_NFILE_DESCRIPTORS < 4 +# error "Not enough file descriptors" +#endif + +#ifndef CONFIG_FS_ROMFS +# error "ROMFS support not enabled" +#endif + +#define SECTORSIZE 64 +#define NSECTORS(b) (((b)+SECTORSIZE-1)/SECTORSIZE) + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +int mount_zoneinfo(int minor) +{ + char devname[32]; + int ret; + + /* Create a RAM disk for the test */ + + ret = romdisk_register(minor, romfs_zoneinfo_img, + NSECTORS(romfs_zoneinfo_img_len), SECTORSIZE); + if (ret < 0) + { + printf("ERROR: Failed to create RAM disk\n"); + return ret; + } + + /* Use the minor number to create a name for the ROM disk block device */ + + snprintf(devname, 32, "/dev/ram%d", minor); + + /* Mount the ROMFS file system */ + + printf("Mounting ROMFS filesystem at target=%s with source=%s\n", + CONFIG_LIBC_TZDIR, devname); + + ret = mount(devname, CONFIG_LIBC_TZDIR, "romfs", MS_RDONLY, NULL); + if (ret < 0) + { + printf("ERROR: Mount failed: %d\n", errno); + return ret; + } + + printf("TZ database mounted at %s\n", CONFIG_LIBC_TZDIR); + return OK; +} diff --git a/libc/zoneinfo/tzromfs.c b/libc/zoneinfo/tzromfs.c new file mode 100644 index 0000000000000000000000000000000000000000..64d71ebe51b18377305d53bdf5e3b558defa5cd6 --- /dev/null +++ b/libc/zoneinfo/tzromfs.c @@ -0,0 +1,51 @@ +/**************************************************************************** + * libc/zoneinfo/tzromfs.c + * + * Copyright (C) 2015-2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#include "romfs_zoneinfo.h" diff --git a/net/netdev/netdev_ioctl.c b/net/netdev/netdev_ioctl.c index d12d3bdbbd666f5286492bfea655988d4b971981..10d9bf2df694fd723927810b64036c28bea53bf2 100644 --- a/net/netdev/netdev_ioctl.c +++ b/net/netdev/netdev_ioctl.c @@ -1026,13 +1026,13 @@ static int netdev_rtioctl(FAR struct socket *psock, int cmd, ****************************************************************************/ /**************************************************************************** - * Name: netdev_ioctl + * Name: psock_ioctl * * Description: * Perform network device specific operations. * * Parameters: - * sockfd Socket descriptor of device + * psock A pointer to a NuttX-specific, internal socket structure * cmd The ioctl command * arg The argument of the ioctl cmd * @@ -1041,7 +1041,7 @@ static int netdev_rtioctl(FAR struct socket *psock, int cmd, * On a failure, -1 is returned with errno set appropriately * * EBADF - * 'sockfd' is not a valid descriptor. + * 'psock' is not a valid, connected socket structure. * EFAULT * 'arg' references an inaccessible memory area. * ENOTTY @@ -1056,9 +1056,8 @@ static int netdev_rtioctl(FAR struct socket *psock, int cmd, * ****************************************************************************/ -int netdev_ioctl(int sockfd, int cmd, unsigned long arg) +int psock_ioctl(FAR struct socket *psock, int cmd, unsigned long arg) { - FAR struct socket *psock = sockfd_socket(sockfd); int ret; /* Check if this is a valid command. In all cases, arg is a pointer that has @@ -1072,9 +1071,9 @@ int netdev_ioctl(int sockfd, int cmd, unsigned long arg) goto errout; } - /* Verify that the sockfd corresponds to valid, allocated socket */ + /* Verify that the psock corresponds to valid, allocated socket */ - if (!psock || psock->s_crefs <= 0) + if (psock == NULL || psock->s_crefs <= 0) { ret = -EBADF; goto errout; @@ -1125,6 +1124,44 @@ errout: return ERROR; } +/**************************************************************************** + * Name: netdev_ioctl + * + * Description: + * Perform network device specific operations. + * + * Parameters: + * sockfd Socket descriptor of device + * cmd The ioctl command + * arg The argument of the ioctl cmd + * + * Return: + * >=0 on success (positive non-zero values are cmd-specific) + * On a failure, -1 is returned with errno set appropriately + * + * EBADF + * 'sockfd' is not a valid socket descriptor. + * EFAULT + * 'arg' references an inaccessible memory area. + * ENOTTY + * 'cmd' not valid. + * EINVAL + * 'arg' is not valid. + * ENOTTY + * 'sockfd' is not associated with a network device. + * ENOTTY + * The specified request does not apply to the kind of object that the + * descriptor 'sockfd' references. + * + ****************************************************************************/ + +int netdev_ioctl(int sockfd, int cmd, unsigned long arg) +{ + FAR struct socket *psock = sockfd_socket(sockfd); + + return psock_ioctl(psock, cmd, arg); +} + /**************************************************************************** * Name: netdev_ifup / netdev_ifdown * diff --git a/sched/pthread/pthread_kill.c b/sched/pthread/pthread_kill.c index a53842308af7adf18961ae1f2f08e6c023bf8f0e..902cbcd78c26676db99b329e72f8d5efe08b2166 100644 --- a/sched/pthread/pthread_kill.c +++ b/sched/pthread/pthread_kill.c @@ -86,8 +86,8 @@ int pthread_kill(pthread_t thread, int signo) { #ifdef HAVE_GROUP_MEMBERS - /* If group members are support then pthread_kill() differs from kill(). - * kill(), in this case, must following the POSIX rules for delivery of + /* If group members are supported then pthread_kill() differs from kill(). + * kill(), in this case, must follow the POSIX rules for delivery of * signals in the group environment. Otherwise, kill(), like * pthread_kill() will just deliver the signal to the thread ID it is * requested to use. diff --git a/sched/semaphore/sem_post.c b/sched/semaphore/sem_post.c index 97235de42818534b5eab7df1cd34617d4cfea57b..c985ceb9c49d7fdae1261a2f6ed9cc364578291e 100644 --- a/sched/semaphore/sem_post.c +++ b/sched/semaphore/sem_post.c @@ -41,6 +41,7 @@ #include #include +#include #include #include @@ -157,6 +158,10 @@ int sem_post(FAR sem_t *sem) leave_critical_section(flags); } + else + { + set_errno(EINVAL); + } return ret; } diff --git a/sched/semaphore/sem_wait.c b/sched/semaphore/sem_wait.c index 86fb013696073248073bc176b0546782cbfd490f..49371e0ae6d6b3a3e04856b02885e5ed8958605c 100644 --- a/sched/semaphore/sem_wait.c +++ b/sched/semaphore/sem_wait.c @@ -86,9 +86,7 @@ int sem_wait(FAR sem_t *sem) DEBUGASSERT(up_interrupt_context() == false); - /* Assume any errors reported are due to invalid arguments. */ - - set_errno(EINVAL); + /* Make sure we were supplied with a valid semaphore. */ if (sem) { @@ -190,6 +188,10 @@ int sem_wait(FAR sem_t *sem) leave_critical_section(flags); } + else + { + set_errno(EINVAL); + } return ret; } diff --git a/tools/README.txt b/tools/README.txt index 44b0427427fa52236adac5d99185d32fafc662b9..408bccad7b35e9472a8dc0c723ce671f34d2d862 100644 --- a/tools/README.txt +++ b/tools/README.txt @@ -580,7 +580,7 @@ refresh.sh This is a bash script that automatics refreshing of board default configuration (defconfig) files. It does not do anything special - thet you cannot do manually, but is useful for me when I have to + that you cannot do manually, but is useful for me when I have to update dozens of confuration files. Configuration files have to be updated because over time, the diff --git a/tools/mkconfig.c b/tools/mkconfig.c index 307e7381d5db0a709e81f50e7b4e584d04926acb..579e29df00a65748d44bdcb6fa7132cb6b8f0469 100644 --- a/tools/mkconfig.c +++ b/tools/mkconfig.c @@ -132,7 +132,7 @@ int main(int argc, char **argv, char **envp) printf("# define CONFIG_RR_INTERVAL 0\n"); printf("#endif\n\n"); - printf("/* The correct way to disable filesystem supuport is to set the number of\n"); + printf("/* The correct way to disable filesystem support is to set the number of\n"); printf(" * file descriptors to zero.\n"); printf(" */\n\n"); printf("#ifndef CONFIG_NFILE_DESCRIPTORS\n"); @@ -220,10 +220,18 @@ int main(int argc, char **argv, char **envp) printf("# define CONFIG_DISABLE_MQUEUE 1\n"); printf("#endif\n\n"); + printf("/* The correct way to disable socket support is to set the number of\n"); + printf(" * socket descriptors to zero.\n"); + printf(" */\n\n"); + printf("#ifndef CONFIG_NSOCKET_DESCRIPTORS\n"); + printf("# define CONFIG_NSOCKET_DESCRIPTORS 0\n"); + printf("#endif\n\n"); + printf("/* There can be no network support with no socket descriptors */\n\n"); printf("#if CONFIG_NSOCKET_DESCRIPTORS <= 0\n"); printf("# undef CONFIG_NET\n"); printf("#endif\n\n"); + printf("/* Conversely, if there is no network support, there is no need for\n"); printf(" * socket descriptors\n"); printf(" */\n\n");