diff --git a/arch/arm/src/lpc313x/Make.defs b/arch/arm/src/lpc313x/Make.defs
index 77b6e6b1859b66f6d8214e923e214c825e212aaf..b3f27c94f7c7f626f8205e44aa433ef44a9fef3b 100755
--- a/arch/arm/src/lpc313x/Make.defs
+++ b/arch/arm/src/lpc313x/Make.defs
@@ -47,7 +47,8 @@ CMN_CSRCS = up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
CGU_ASRCS =
CGU_CSRCS = lpc313x_clkdomain.c lpc313x_clkfreq.c lpc313x_esrndx.c \
- lpc313x_fdcndx.c lpc313x_freqin.c lpc313x_softreset.c
+ lpc313x_fdcndx.c lpc313x_freqin.c lpc313x_pllconfig.c \
+ lpc313x_setfreqin.c lpc313x_softreset.c
CHIP_ASRCS = $(CGU_ASRCS)
CHIP_CSRCS = lpc313x_allocateheap.c lpc313x_boot.c lpc313x_irq.c \
diff --git a/arch/arm/src/lpc313x/lpc313x_cgu.h b/arch/arm/src/lpc313x/lpc313x_cgu.h
index 4660c86ae15e79fce687c6b872e96666e2ea3bc0..2d5dc4ba70e4a42c71bde5317dc48c942aa7565e 100755
--- a/arch/arm/src/lpc313x/lpc313x_cgu.h
+++ b/arch/arm/src/lpc313x/lpc313x_cgu.h
@@ -541,6 +541,29 @@
#define LPC313X_CGU_AHBMPMCRFRST_OFFSET 0x0e8 /* Reset refresh generator used for MPMC */
#define LPC313X_CGU_INTCRST_OFFSET 0x0ec /* Reset Interrupt Controller */
+/* HP PLL controls */
+
+#define LPC313x_CGU_HP0PLL_OFFSET 0x0f0 /* Base offset to HP0 PLL registers */
+#define LPC313x_CGU_HP1PLL_OFFSET 0x128 /* Base offset to HP1 PLL registers */
+#define CGU_HP0PLL 0 /* HP0 PLL selector */
+#define CGU_HP1PLL 1 /* HP1 PLL selector */
+#define LPC313x_CGU_HPPLL_OFFSET(n) ((n) ? LPC313x_CGU_HP1PLL_OFFSET : LPC313x_CGU_HP0PLL_OFFSET)
+
+#define LPC313X_CGU_HPFINSEL_OFFSET 0x000 /* Register for selecting input to high HPPLL0/1 */
+#define LPC313X_CGU_HPMDEC_OFFSET 0x004 /* M-divider register of HP0/1 PLL */
+#define LPC313X_CGU_HPNDEC_OFFSET 0x008 /* N-divider register of HP0/1 PLL */
+#define LPC313X_CGU_HPPDEC_OFFSET 0x00c /* P-divider register of HP0/1 PLL */
+#define LPC313X_CGU_HPMODE_OFFSET 0x010 /* Mode register of HP0/1 PLL */
+#define LPC313X_CGU_HPSTATUS_OFFSET 0x014 /* Status register of HP0/1 PLL */
+#define LPC313X_CGU_HPACK_OFFSET 0x018 /* Ratio change acknowledge register of HP0/1 PLL */
+#define LPC313X_CGU_HPREQ_OFFSET 0x01c /* Ratio change request register of HP0/1 PLL */
+#define LPC313X_CGU_HPINSELR_OFFSET 0x020 /* Bandwidth selection register of HP0/1 PLL */
+#define LPC313X_CGU_HPINSELI_OFFSET 0x024 /* Bandwidth selection register of HP0/1 PLL */
+#define LPC313X_CGU_HPINSELP_OFFSET 0x028 /* Bandwidth selection register of HP0/1 PLL */
+#define LPC313X_CGU_HPSELR_OFFSET 0x02c /* Bandwidth selection register of HP0/1 PLL */
+#define LPC313X_CGU_HPSELI_OFFSET 0x030 /* Bandwidth selection register of HP0/1 PLL */
+#define LPC313X_CGU_HPSELP_OFFSET 0x034 /* Bandwidth selection register of HP0/1 PLL */
+
/* HP0 PLL control (audio PLL) */
#define LPC313X_CGU_HP0FINSEL_OFFSET 0x0f0 /* Register for selecting input to high HPPLL0 */
@@ -1045,6 +1068,12 @@
#define LPC313X_CGU_AHBMPMCRFRST (LPC313X_CGU_CFG_VBASE+LPC313X_CGU_AHBMPMCRFRST_OFFSET)
#define LPC313X_CGU_INTCRST (LPC313X_CGU_CFG_VBASE+LPC313X_CGU_INTCRST_OFFSET)
+/* HP PLL controls */
+
+#define LPC313x_CGU_HP0PLL (LPC313X_CGU_CFG_VBASE+LPC313x_CGU_HP0PLL_OFFSET)
+#define LPC313x_CGU_HP1PLL (LPC313X_CGU_CFG_VBASE+LPC313x_CGU_HP1PLL_OFFSET)
+#define LPC313x_CGU_HPPLL(n) ((n) ? LPC313x_CGU_HP1PLL : LPC313x_CGU_HP0PLL)
+
/* HPO PLL control (audio PLL) */
#define LPC313X_CGU_HP0FINSEL (LPC313X_CGU_CFG_VBASE+LPC313X_CGU_HP0FINSEL_OFFSET)
@@ -1101,29 +1130,19 @@
#define CGU_SCR_ENF2 (1 << 1) /* Bit 1: Enable side #2 of switch */
#define CGU_SCR_ENF1 (1 << 0) /* Bit 0: Enable side #1 of switch */
-/* Frequency select register 1 FS1_0 to FS1_11, addresses 0x13004030 to 0x1300405c */
-
-#define CGU_FS1_SHIFT (0) /* Bits 0-2: Selects input frequency for side #1 of frequency switch */
-#define CGU_FS1_MASK (7 << CGU_FS1_SHIFT)
-# define CGU_FS1_FFAST (CGU_FREQIN_FFAST << CGU_FS1_SHIFT) /* ffast 12 MHz */
-# define CGU_FS1_I2SRXBCK0 (CGU_FREQIN_I2SRXBCK0 << CGU_FS1_SHIFT) /* I2SRX_BCK0 */
-# define CGU_FS1_I2SRXWS0 (CGU_FREQIN_I2SRXWS0 << CGU_FS1_SHIFT) /* I2SRX_WS0 */
-# define CGU_FS1_I2SRXBCK1 (CGU_FREQIN_I2SRXBCK1 << CGU_FS1_SHIFT) /* I2SRX_BCK1 */
-# define CGU_FS1_I2SRXWS1 (CGU_FREQIN_I2SRXWS1 << CGU_FS1_SHIFT) /* I2SRX_WS1 */
-# define CGU_FS1_HPPLL0 (CGU_FREQIN_HPPLL0 << CGU_FS1_SHIFT) /* HPPLL0 (Audio/I2S PLL) */
-# define CGU_FS1_HPPLL1 (CGU_FREQIN_HPPLL1 << CGU_FS1_SHIFT) /* HPPLL1 (System PLL) */
-
-/* Frequency Select register 2 FS2_0 to FS2_11, addresses 0x13004060 to 0x1300408c */
-
-#define CGU_FS2_SHIFT (0) /* Bits 0-2: Selects input frequency for side #2 of frequency switch */
-#define CGU_FS2_MASK (7 << CGU_FS2_SHIFT)
-# define CGU_FS2_FFAST (CGU_FREQIN_FFAST << CGU_FS2_SHIFT) /* ffast 12 MHz */
-# define CGU_FS2_I2SRXBCK0 (CGU_FREQIN_I2SRXBCK0 << CGU_FS2_SHIFT) /* I2SRX_BCK0 */
-# define CGU_FS2_I2SRXWS0 (CGU_FREQIN_I2SRXWS0 << CGU_FS2_SHIFT) /* I2SRX_WS0 */
-# define CGU_FS2_I2SRXBCK1 (CGU_FREQIN_I2SRXBCK1 << CGU_FS2_SHIFT) /* I2SRX_BCK1 */
-# define CGU_FS2_I2SRXWS1 (CGU_FREQIN_I2SRXWS1 << CGU_FS2_SHIFT) /* I2SRX_WS1 */
-# define CGU_FS2_HPPLL0 (CGU_FREQIN_HPPLL0 << CGU_FS2_SHIFT) /* HPPLL0 (Audio/I2S PLL) */
-# define CGU_FS2_HPPLL1 (CGU_FREQIN_HPPLL1 << CGU_FS2_SHIFT) /* HPPLL1 (System PLL) */
+/* Frequency select register 1 FS1_0 to FS1_11, addresses 0x13004030 to 0x1300405c,
+ * Frequency Select register 2 FS2_0 to FS2_11, addresses 0x13004060 to 0x1300408c
+ */
+
+#define CGU_FS_SHIFT (0) /* Bits 0-2: Selects input frequency for either side of frequency switch */
+#define CGU_FS_MASK (7 << CGU_FS_SHIFT)
+# define CGU_FS_FFAST (CGU_FREQIN_FFAST << CGU_FS_SHIFT) /* ffast 12 MHz */
+# define CGU_FS_I2SRXBCK0 (CGU_FREQIN_I2SRXBCK0 << CGU_FS_SHIFT) /* I2SRX_BCK0 */
+# define CGU_FS_I2SRXWS0 (CGU_FREQIN_I2SRXWS0 << CGU_FS_SHIFT) /* I2SRX_WS0 */
+# define CGU_FS_I2SRXBCK1 (CGU_FREQIN_I2SRXBCK1 << CGU_FS_SHIFT) /* I2SRX_BCK1 */
+# define CGU_FS_I2SRXWS1 (CGU_FREQIN_I2SRXWS1 << CGU_FS_SHIFT) /* I2SRX_WS1 */
+# define CGU_FS_HPPLL0 (CGU_FREQIN_HPPLL0 << CGU_FS_SHIFT) /* HPPLL0 (Audio/I2S PLL) */
+# define CGU_FS_HPPLL1 (CGU_FREQIN_HPPLL1 << CGU_FS_SHIFT) /* HPPLL1 (System PLL) */
/* Switch Status register SSR0 to SSR11, addresses 0x13004090 to 0x1300 40bc */
@@ -1137,7 +1156,7 @@
# define CGU_SSR_HPPLL0 (CGU_FREQIN_HPPLL0 << CGU_SSR_FS_SHIFT) /* HPPLL0 (Audio/I2S PLL) */
# define CGU_SSR_HPPLL1 (CGU_FREQIN_HPPLL1 << CGU_SSR_FS_SHIFT) /* HPPLL1 (System PLL) */
#define CGU_SSR_FS2STAT (1 << 1) /* Bit 1: Enable side #2 of the frequency switch */
-#define CGU_SSR_F1STAT (1 << 0) /* Bit 0: Enable side #1 of the frequency switch */
+#define CGU_SSR_FS1STAT (1 << 0) /* Bit 0: Enable side #1 of the frequency switch */
/* Power Control register PCR0 to PCR91, addresses 0x130040c0 to 0x1300422c */
@@ -1465,175 +1484,120 @@
#define CGU_INTCRST_RESET (1 << 0) /* Bit 0: Reset for Interrupt Controller */
/* PLL control registers */
-/* HP0 Frequency Input Select register HP0_FIN_SELECT, address 0x13004cf0 */
-
-#define CGU_HP0FINSEL_SHIFT (0) /* Bits 0-3: Select input to high HPPLL0 */
-#define CGU_HP0FINSEL_MASK (15 << CGU_HP0FINSEL_SHIFT)
-# define CGU_HP0FINSEL_FFAST (CGU_FREQIN_FFAST << CGU_HP0FINSEL_SHIFT) /* ffast (12 Mhz) */
-# define CGU_HP0FINSEL_I2SRXBCK0 (CGU_FREQIN_I2SRXBCK0 << CGU_HP0FINSEL_SHIFT) /* I2SRX_BCK0 */
-# define CGU_HP0FINSEL_I2SRXWS0 (CGU_FREQIN_I2SRXWS0 << CGU_HP0FINSEL_SHIFT) /* I2SRX_WS0 */
-# define CGU_HP0FINSEL_I2SRXBCK1 (CGU_FREQIN_I2SRXBCK1 << CGU_HP0FINSEL_SHIFT) /* I2SRX_BCK1 */
-# define CGU_HP0FINSEL_I2SRXWS1 (CGU_FREQIN_I2SRXWS1 << CGU_HP0FINSEL_SHIFT) /* I2SRX_WS1 */
-# define CGU_HP0FINSEL_HP1FOUT (CGU_FREQIN_HPPLL1 << CGU_HP0FINSEL_SHIFT) /* HP1_FOUT */
-
-/* HP0 M-divider register HP0_MDEC, address 0x13004cF4 */
-
-#define CGU_HP0MDEC_SHIFT (0) /* Bits 0-16: Decoded divider ratio for M-divider */
-#define CGU_HP0MDEC_MASK (0x1ffff << CGU_HP0MDEC_SHIFT)
-
-/* HP0 N-divider register HP0_NDEC, address 0x13004cf8 */
-
-#define CGU_HP0NDEC_SHIFT (0) /* Bits 0-9: Decoded divider ratio for N-divider */
-#define CGU_HP0NDEC_MASK (0x3ff << CGU_HP0NDEC_SHIFT)
-
-/* HP0 P-divider register HP0_PDEC, address 0x13004cfc */
-
-#define CGU_HP0PDEC_SHIFT (0) /* Bits 0-6: Decoded divider ratio for P-divider */
-#define CGU_HP0PDEC_MASK (0x7F << CGU_HP0PDEC_SHIFT)
-
-/* HP0 Mode register HP0_MODE, address 0x13004d00 */
-
-#define CGU_HP0MODE_BYPASS (1 << 8) /* Bit 8: Bypass mode */
-#define CGU_HP0MODE_LIMUPOFF (1 << 7) /* Bit 7: Up limiter */
-#define CGU_HP0MODE_BANDSEL (1 << 6) /* Bit 6: Bandwidth adjustment pin */
-#define CGU_HP0MODE_FRM (1 << 5) /* Bit 5: Free Running Mode */
-#define CGU_HP0MODE_DIRECTI (1 << 4) /* Bit 4: Normal operation with DIRECTO */
-#define CGU_HP0MODE_DIRECTO (1 << 3) /* Bit 3: Normal operation with DIRECTI */
-#define CGU_HP0MODE_PD (1 << 2) /* Bit 2: Power down mode */
-#define CGU_HP0MODE_SKEWEN (1 << 1) /* Bit 1: Skew mode */
-#define CGU_HP0MODE_CLKEN (1 << 0) /* Bit 0: Enable mode */
-
-/* HP0 Status register HP0_STATUS, address 0x13004d04 */
-
-#define CGU_HP0STATUS_FR (1 << 1) /* Bit 1: Free running detector */
-#define CGU_HP0STATUS_LOCK (1 << 0) /* Bit 0: Lock detector */
-
-/* HP0 Acknowledge register HP0_ACK, address 0x13004d08 */
-
-#define CGU_HP0ACK_P (1 << 2) /* Bit 2: Post-divider ratio change acknowledge */
-#define CGU_HP0ACK_N (1 << 1) /* Bit 1: Pre-divider ratio change acknowledge */
-#define CGU_HP0ACK_M (1 << 0) /* Bit 0: Feedback divider ratio change acknowledge */
-
-/* HP0 request register HP0_REQ, address 0x13004d0c */
-
-#define CGU_HP0REQ_P (1 << 2) /* Bit 2: Post-divider ratio change request */
-#define CGU_HP0REQ_N (1 << 1) /* Bit 1: Pre-divider ratio change request */
-#define CGU_HP0REQ_M (1 << 0) /* Bit 0: Feedback divider ratio change request */
-
-/* HP0 Bandwith Selection register HP0_INSELR, address 0x13004d10 */
-
-#define CGU_HP0INSELR_SHIFT (0) /* Bits 0-3: Pins to select the bandwidth */
-#define CGU_HP0INSELR_MASK (15 << CGU_HP0INSELR_SHIFT)
-
-/* HP0 Bandwith Selection register HP0_INSELI, address 0x13004d14 */
-
-#define CGU_HP0INSELI_SHIFT (0) /* Bits 0-5: Bandwidth selection register of HP0 PLL */
-#define CGU_HP0INSELI_MASK (63 << CGU_HP0INSELI_SHIFT)
-
-/* HP0 Bandwith Selection register HP0_INSELP, address 0x13004d18 */
-
-#define CGU_HP0INSELP_SHIFT (0) /* Bits 0-4: Bandwidth selection register of HP0 PLL */
-#define CGU_HP0INSELP_MASK (31 << CGU_HP0INSELP_SHIFT)
-
-/* HP0 Bandwith Selection register HP0_INSELP, address 0x13004d18 */
-
-#define CGU_HP0SELR_SHIFT (0) /* Bits 0-3: Bandwidth selection register of HP0 PLL */
-#define CGU_HP0SELR_MASK (15 << CGU_HP0SELR_SHIFT)
-
-/* HP0 Bandwith Selection register HP0_SELI, address 0x13004d20 */
-
-#define CGU_HP0SELI_SHIFT (0) /* Bits 0-5: Bandwidth selection register of HP0 PLL */
-#define CGU_HP0SELI_MASK (63 << CGU_HP0SELI_SHIFT)
-
-/* HP0 Bandwith Selection register HP0_SELP, address 0x13004d24 */
-
-#define CGU_HP0SELP_SHIFT (0) /* Bits 0-4: Bandwidth selection register of HP0 PLL */
-#define CGU_HP0IELP_MASK (31 << CGU_HP0SELP_SHIFT)
-
-/* HP1 Frequency Input Select register HP1_FIN_SELECT, address 0x13004d28 */
-
-#define CGU_HP1FINSEL_SHIFT (0) /* Bits 0-3: Select input to high HPPLL0 */
-#define CGU_HP1FINSEL_MASK (15 << CGU_HP1FINSEL_SHIFT)
-# define CGU_HP1FINSEL_FFAST (CGU_FREQIN_FFAST << CGU_HP1FINSEL_SHIFT) /* ffast (12 Mhz) */
-# define CGU_HP1FINSEL_I2SRXBCK0 (CGU_FREQIN_I2SRXBCK0 << CGU_HP1FINSEL_SHIFT) /* I2SRX_BCK0 */
-# define CGU_HP1FINSEL_I2SRXWS0 (CGU_FREQIN_I2SRXWS0 << CGU_HP1FINSEL_SHIFT) /* I2SRX_WS0 */
-# define CGU_HP1FINSEL_I2SRXBCK1 (CGU_FREQIN_I2SRXBCK1 << CGU_HP1FINSEL_SHIFT) /* I2SRX_BCK1 */
-# define CGU_HP1FINSEL_I2SRXWS1 (CGU_FREQIN_I2SRXWS1 << CGU_HP1FINSEL_SHIFT) /* I2SRX_WS1 */
-# define CGU_HP1FINSEL_HP0FOUT (CGU_FREQIN_HPPLL0 << CGU_HP1FINSEL_SHIFT) /* HP0_FOUT */
-
-/* HP1 M-divider register HP1_MDEC, address 0x13004d2C */
-
-#define CGU_HP1MDEC_SHIFT (0) /* Bits 0-16: Decoded divider ratio for M-divider */
-#define CGU_HP1MDEC_MASK (0x1ffff << CGU_HP1MDEC_SHIFT)
-
-/* HP1 N-divider register HP1_NDEC, address 0x13004D30 */
-
-#define CGU_HP1NDEC_SHIFT (0) /* Bits 0-9: Decoded divider ratio for N-divider */
-#define CGU_HP1NDEC_MASK (0x3ff << CGU_HP1NDEC_SHIFT)
-
-/* HP1 P-diver register HP1_PDEC, address 0x13004D34 */
-
-#define CGU_HP1PDEC_SHIFT (0) /* Bits 0-6: Decoded divider ratio for P-divider */
-#define CGU_HP1PDEC_MASK (0x7F << CGU_HP1PDEC_SHIFT)
-
-/* HP1 Mode register HP1_MODE, address 0x13004d38 */
-
-#define CGU_HP1MODE_BYPASS (1 << 8) /* Bit 8: Bypass mode */
-#define CGU_HP1MODE_LIMUPOFF (1 << 7) /* Bit 7: Up limiter */
-#define CGU_HP1MODE_BANDSEL (1 << 6) /* Bit 6: Bandwidth adjustment pin */
-#define CGU_HP1MODE_FRM (1 << 5) /* Bit 5: Free Running Mode */
-#define CGU_HP1MODE_DIRECTI (1 << 4) /* Bit 4: Normal operation with DIRECTO */
-#define CGU_HP1MODE_DIRECTO (1 << 3) /* Bit 3: Normal operation with DIRECTI */
-#define CGU_HP1MODE_PD (1 << 2) /* Bit 2: Power down mode */
-#define CGU_HP1MODE_SKEWEN (1 << 1) /* Bit 1: Skew mode */
-#define CGU_HP1MODE_CLKEN (1 << 0) /* Bit 0: Enable mode */
-
-/* HP1 Status register HP1_STATUS, address 0x13004d3C */
-
-#define CGU_HP1STATUS_FR (1 << 1) /* Bit 1: Free running detector */
-#define CGU_HP1STATUS_LOCK (1 << 0) /* Bit 0: Lock detector */
-
-/* HP1 Acknowledge register HP1_ACK, address 0x13004d40 */
-
-#define CGU_HP1ACK_P (1 << 2) /* Bit 2: Post-divider ratio change acknowledge */
-#define CGU_HP1ACK_N (1 << 1) /* Bit 1: Pre-divider ratio change acknowledge */
-#define CGU_HP1ACK_M (1 << 0) /* Bit 0: Feedback divider ratio change acknowledge */
-
-/* HP1 Request register HP1_REQ, address 0x13004d44 */
-
-#define CGU_HP1REQ_P (1 << 2) /* Bit 2: Post-divider ratio change request */
-#define CGU_HP1REQ_N (1 << 1) /* Bit 1: Pre-divider ratio change request */
-#define CGU_HP1REQ_M (1 << 0) /* Bit 0: Feedback divider ratio change request */
-
-/* HP1 bandwith Selection register HP1_INSELR, address 0x13004d48 */
-
-#define CGU_HP1INSELR_SHIFT (0) /* Bits 0-3: Pins to select the bandwidth */
-#define CGU_HP1INSELR_MASK (15 << CGU_HP1INSELR_SHIFT)
-
-/* HP1 bandwith Selection register HP1_INSELI, address 0x13004d4c */
-
-#define CGU_HP1INSELI_SHIFT (0) /* Bits 0-5: Bandwidth selection register of HP1 PLL */
-#define CGU_HP1INSELI_MASK (63 << CGU_HP1INSELI_SHIFT)
-
-/* HP1 bandwith Selection register HP1_INSELP, address 0x13004d50 */
-
-#define CGU_HP1INSELP_SHIFT (0) /* Bits 0-4: Bandwidth selection register of HP1 PLL */
-#define CGU_HP1INSELP_MASK (31 << CGU_HP1INSELP_SHIFT)
-
-/* HP1 bandwith Selection register HP1_SELR, address 0x13004d54 */
-
-#define CGU_HP1SELR_SHIFT (0) /* Bits 0-3: Bandwidth selection register of HP1 PLL */
-#define CGU_HP1SELR_MASK (15 << CGU_HP1SELR_SHIFT)
-
-/* HP1 bandwith Selection register HP1_SELI, address 0x13004d58 */
-
-#define CGU_HP1SELI_SHIFT (0) /* Bits 0-5: Bandwidth selection register of HP1 PLL */
-#define CGU_HP1SELI_MASK (63 << CGU_HP1SELI_SHIFT)
+/* HP0 Frequency Input Select register HP0_FIN_SELECT, address 0x13004cf0,
+ * HP1 Frequency Input Select register HP1_FIN_SELECT, address 0x13004d28
+ */
+
+#define CGU_HPFINSEL_SHIFT (0) /* Bits 0-3: Select input to high HPPLL0 */
+#define CGU_HPFINSEL_MASK (15 << CGU_HPFINSEL_SHIFT)
+# define CGU_HPFINSEL_FFAST (CGU_FREQIN_FFAST << CGU_HPFINSEL_SHIFT) /* ffast (12 Mhz) */
+# define CGU_HPFINSEL_I2SRXBCK0 (CGU_FREQIN_I2SRXBCK0 << CGU_HPFINSEL_SHIFT) /* I2SRX_BCK0 */
+# define CGU_HPFINSEL_I2SRXWS0 (CGU_FREQIN_I2SRXWS0 << CGU_HPFINSEL_SHIFT) /* I2SRX_WS0 */
+# define CGU_HPFINSEL_I2SRXBCK1 (CGU_FREQIN_I2SRXBCK1 << CGU_HPFINSEL_SHIFT) /* I2SRX_BCK1 */
+# define CGU_HPFINSEL_I2SRXWS1 (CGU_FREQIN_I2SRXWS1 << CGU_HPFINSEL_SHIFT) /* I2SRX_WS1 */
+# define CGU_HPFINSEL_HP0FOUT (CGU_FREQIN_HPPLL0 << CGU_HPFINSEL_SHIFT) /* HP0_FOUT */
+# define CGU_HPFINSEL_HP1FOUT (CGU_FREQIN_HPPLL1 << CGU_HPFINSEL_SHIFT) /* HP1_FOUT */
+
+/* HP0 M-divider register HP0_MDEC, address 0x13004cF4,
+ * HP1 M-divider register HP1_MDEC, address 0x13004d2C
+ */
+
+#define CGU_HPMDEC_SHIFT (0) /* Bits 0-16: Decoded divider ratio for M-divider */
+#define CGU_HPMDEC_MASK (0x1ffff << CGU_HPMDEC_SHIFT)
+
+/* HP0 N-divider register HP0_NDEC, address 0x13004cf8,
+ * HP1 N-divider register HP1_NDEC, address 0x13004D30
+ */
+
+#define CGU_HPNDEC_SHIFT (0) /* Bits 0-9: Decoded divider ratio for N-divider */
+#define CGU_HPNDEC_MASK (0x3ff << CGU_HPNDEC_SHIFT)
+
+/* HP0 P-divider register HP0_PDEC, address 0x13004cfc.
+ * HP1 P-divider register HP1_PDEC, address 0x13004D34
+ */
+
+#define CGU_HPPDEC_SHIFT (0) /* Bits 0-6: Decoded divider ratio for P-divider */
+#define CGU_HPPDEC_MASK (0x7F << CGU_HPPDEC_SHIFT)
+
+/* HP0 Mode register HP0_MODE, address 0x13004d00,
+ * HP1 Mode register HP1_MODE, address 0x13004d38
+ */
+
+#define CGU_HPMODE_BYPASS (1 << 8) /* Bit 8: Bypass mode */
+#define CGU_HPMODE_LIMUPOFF (1 << 7) /* Bit 7: Up limiter */
+#define CGU_HPMODE_BANDSEL (1 << 6) /* Bit 6: Bandwidth adjustment pin */
+#define CGU_HPMODE_FRM (1 << 5) /* Bit 5: Free Running Mode */
+#define CGU_HPMODE_DIRECTI (1 << 4) /* Bit 4: Normal operation with DIRECTO */
+#define CGU_HPMODE_DIRECTO (1 << 3) /* Bit 3: Normal operation with DIRECTI */
+#define CGU_HPMODE_PD (1 << 2) /* Bit 2: Power down mode */
+#define CGU_HPMODE_SKEWEN (1 << 1) /* Bit 1: Skew mode */
+#define CGU_HPMODE_CLKEN (1 << 0) /* Bit 0: Enable mode */
+
+/* HP0 Status register HP0_STATUS, address 0x13004d04,
+ * HP1 Status register HP1_STATUS, address 0x13004d3c
+ */
+
+#define CGU_HPSTATUS_FR (1 << 1) /* Bit 1: Free running detector */
+#define CGU_HPSTATUS_LOCK (1 << 0) /* Bit 0: Lock detector */
+
+/* HP0 Acknowledge register HP0_ACK, address 0x13004d08,
+ * HP1 Acknowledge register HP1_ACK, address 0x13004d40
+ */
+
+#define CGU_HPACK_P (1 << 2) /* Bit 2: Post-divider ratio change acknowledge */
+#define CGU_HPACK_N (1 << 1) /* Bit 1: Pre-divider ratio change acknowledge */
+#define CGU_HPACK_M (1 << 0) /* Bit 0: Feedback divider ratio change acknowledge */
+
+/* HP0 request register HP0_REQ, address 0x13004d0c,
+ * HP1 Request register HP1_REQ, address 0x13004d44
+ */
+
+#define CGU_HPREQ_P (1 << 2) /* Bit 2: Post-divider ratio change request */
+#define CGU_HPREQ_N (1 << 1) /* Bit 1: Pre-divider ratio change request */
+#define CGU_HPREQ_M (1 << 0) /* Bit 0: Feedback divider ratio change request */
+
+/* HP0 Bandwith Selection register HP0_INSELR, address 0x13004d10,
+ * HP1 bandwith Selection register HP1_INSELR, address 0x13004d48
+ */
+
+#define CGU_HPINSELR_SHIFT (0) /* Bits 0-3: Pins to select the bandwidth */
+#define CGU_HPINSELR_MASK (15 << CGU_HPINSELR_SHIFT)
+
+/* HP0 Bandwith Selection register HP0_INSELI, address 0x13004d14,
+ * HP1 bandwith Selection register HP1_INSELI, address 0x13004d4c
+ */
+
+#define CGU_HPINSELI_SHIFT (0) /* Bits 0-5: Bandwidth selection register of HP0/1 PLL */
+#define CGU_HPINSELI_MASK (63 << CGU_HPINSELI_SHIFT)
+
+
+/* HP0 Bandwith Selection register HP0_INSELP, address 0x13004d18,
+ * HP1 bandwith Selection register HP1_INSELP, address 0x13004d50
+ */
+
+#define CGU_HPINSELP_SHIFT (0) /* Bits 0-4: Bandwidth selection register of HP0/1 PLL */
+#define CGU_HPINSELP_MASK (31 << CGU_HPINSELP_SHIFT)
+
+/* HP0 Bandwith Selection register HP0_SELR, address 0x13004d1c,
+ * HP1 bandwith Selection register HP1_SELR, address 0x13004d54
+ */
+
+#define CGU_HPSELR_SHIFT (0) /* Bits 0-3: Bandwidth selection register of HP0/1 PLL */
+#define CGU_HPSELR_MASK (15 << CGU_HPSELR_SHIFT)
+
+/* HP0 Bandwith Selection register HP0_SELI, address 0x13004d20
+ * HP1 bandwith Selection register HP1_SELI, address 0x13004d58
+ */
+
+#define CGU_HPSELI_SHIFT (0) /* Bits 0-5: Bandwidth selection register of HP0/1 PLL */
+#define CGU_HPSELI_MASK (63 << CGU_HPSELI_SHIFT)
-/* HP1 bandwith Selection register HP1_SELP, address 0x13004d5c */
+/* HP0 Bandwith Selection register HP0_SELP, address 0x13004d24,
+ * HP1 bandwith Selection register HP1_SELP, address 0x13004d5c
+ */
-#define CGU_HP1SELP_SHIFT (0) /* Bits 0-4: Bandwidth selection register of HP1 PLL */
-#define CGU_HP1IELP_MASK (31 << CGU_HP1SELP_SHIFT)
+#define CGU_HPSELP_SHIFT (0) /* Bits 0-4: Bandwidth selection register of HP0/1 PLL */
+#define CGU_HPIELP_MASK (31 << CGU_HPSELP_SHIFT)
/************************************************************************************************
* Public Types
diff --git a/arch/arm/src/lpc313x/lpc313x_cgudrvr.h b/arch/arm/src/lpc313x/lpc313x_cgudrvr.h
index 3462badb288a5f87fe7c1a258125147addd18bcd..9b7afedd71411d378953e05e09c0f5e64cf3a818 100755
--- a/arch/arm/src/lpc313x/lpc313x_cgudrvr.h
+++ b/arch/arm/src/lpc313x/lpc313x_cgudrvr.h
@@ -396,27 +396,45 @@ enum lpc313x_resetid_e
RESETID_INTCRST, /* 55 Interrupt Controller */
};
+/* This structure is used to pass PLL configuration data to
+ * lpc313x_pllconfig()
+ */
+
+struct lpc313x_pllconfig_s
+{
+ uint8_t hppll; /* PLL selection: 0=HPLL0 1=HPLL1 */
+ uint8_t pdec; /* PLL P-divider value: 0-0x7f */
+ uint8_t selr; /* SELR bandwidth selection: 0-15 */
+ uint8_t seli; /* SELI bandwidth selection: 0-63 */
+ uint8_t selp; /* SELP bandwidth selection: 0-31 */
+ uint16_t ndec; /* PLL N-divider value: 0-0x3ff */
+ uint16_t mode; /* PLL mode: 9-bits */
+ uint32_t freq; /* Frequency of the PLL in MHz */
+ uint32_t finsel; /* Frequency input selection: CGU_HPFINSEL_* */
+ uint32_t mdec; /* PLL M-divider value: 0-0x1ffff */
+};
+
/************************************************************************
* Public Data
************************************************************************/
/* This array provides the programmed frequency of every input source */
-EXTERN const int32_t g_boardfreqin[CGU_NFREQIN];
+EXTERN uint32_t g_boardfreqin[CGU_NFREQIN];
/************************************************************************
* Inline Functions
************************************************************************/
/************************************************************************
- * Name: lpc313x_basefreq
+ * Name: lpc313x_getbasefreq
*
* Description:
* Return the base frequency associated with a clock domain
*
************************************************************************/
-static inline int32_t lpc313x_basefreq(enum lpc313x_domainid_e dmnid)
+static inline uint32_t lpc313x_getbasefreq(enum lpc313x_domainid_e dmnid)
{
uint32_t regval;
int ndx;
@@ -472,6 +490,36 @@ static inline void lpc313x_disableclock(enum lpc313x_clockid_e clkid)
* Public Functions
************************************************************************/
+/****************************************************************************
+ * Name: lpc313x_pllconfig
+ *
+ * Description:
+ * Re-onfigure the PLL according to the provided selections.
+ *
+ ****************************************************************************/
+
+EXTERN void lpc313x_pllconfig(const struct lpc313x_pllconfig_s * const cfg);
+
+/************************************************************************
+ * Name: lpc313x_hp0pllconfig
+ *
+ * Description:
+ * Configure the HP0 PLL according to the board.h default selections.
+ *
+ ************************************************************************/
+
+EXTERN void lpc313x_hp0pllconfig(void);
+
+/************************************************************************
+ * Name: lpc313x_hp1pllconfig
+ *
+ * Description:
+ * Configure the HP1 PLL according to the board.h default selections.
+ *
+ ************************************************************************/
+
+EXTERN void lpc313x_hp1pllconfig(void);
+
/************************************************************************
* Name: lpc313x_softreset
*
@@ -529,7 +577,18 @@ EXTERN int lpc313x_fdcndx(enum lpc313x_clockid_e clkid,
enum lpc313x_domainid_e dmnid);
/************************************************************************
- * Name: lpc313x_fdcndx
+ * Name: lpc313x_selectfreqin
+ *
+ * Description:
+ * Set the base frequency source selection for with a clock domain
+ *
+ ************************************************************************/
+
+EXTERN void lpc313x_selectfreqin(enum lpc313x_domainid_e dmnid,
+ uint32_t finsel);
+
+/************************************************************************
+ * Name: lpc313x_clkfreq
*
* Description:
* Given a clock ID and its domain ID, return the frequency of the
diff --git a/arch/arm/src/lpc313x/lpc313x_clkfreq.c b/arch/arm/src/lpc313x/lpc313x_clkfreq.c
index 8d4f9fb35f90b3b985b5fa0ebaa05a9f7185957d..17252c9ca9812f2904296effb793579d5f946af9 100755
--- a/arch/arm/src/lpc313x/lpc313x_clkfreq.c
+++ b/arch/arm/src/lpc313x/lpc313x_clkfreq.c
@@ -85,7 +85,7 @@ uint32_t lpc313x_clkfreq(enum lpc313x_clockid_e clkid,
/* Get base frequency for the domain */
- freq = lpc313x_basefreq(dmnid);
+ freq = lpc313x_getbasefreq(dmnid);
/* If there is no fractional divider associated with the clodk, then the
* connection is directo and we just return the base frequency.
diff --git a/arch/arm/src/lpc313x/lpc313x_freqin.c b/arch/arm/src/lpc313x/lpc313x_freqin.c
index 4b44741b8aac0b76cb19d40ced344e6528999188..deec499111ce37877fd6ff5d997b338160f3e7a7 100755
--- a/arch/arm/src/lpc313x/lpc313x_freqin.c
+++ b/arch/arm/src/lpc313x/lpc313x_freqin.c
@@ -1,5 +1,5 @@
/****************************************************************************
- * configs/ea3131/src/up_cgu.c
+ * arch/arm/src/lpc313x/lpc313x_freqin.c
*
* Copyright (C) 2009 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
@@ -46,24 +46,33 @@
#include "lpc313x_cgudrvr.h"
/****************************************************************************
- * Definitions
+ * Pre-processor Definitions
****************************************************************************/
-const int32_t g_boardfreqin[CGU_NFREQIN] =
-{
- BOARD_FREQIN_FFAST, /* Index=CGU_FREQIN_FFAST */
- BOARD_FREQIN_I2SRXBCK0, /* Index=CGU_FREQIN_I2SRXBCK0 */
- BOARD_FREQIN_I2SRXWS0, /* Index=CGU_FREQIN_I2SRXWS0 */
- BOARD_FREQIN_I2SRXBCK1, /* Index=CGU_FREQIN_I2SRXBCK1 */
- BOARD_FREQIN_I2SRXWS1, /* Index=CGU_FREQIN_I2SRXWS1 */
- BOARD_FREQIN_HPPLL0, /* Index=CGU_FREQIN_HPPLL0 (Audio/I2S PLL) */
- BOARD_FREQIN_HPPLL1 /* Index=CGU_FREQIN_HPPLL1 (System PLL) */
-};
-
/****************************************************************************
* Private Data
****************************************************************************/
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/* This array provides the programmed frequency of every input source. The
+ * board FFAST input crystal frequency is the only value known initially.
+ * Additional frequencies will be added to the table as they are determined
+ */
+
+uint32_t g_boardfreqin[CGU_NFREQIN] =
+{
+ BOARD_FREQIN_FFAST, /* Index=CGU_FREQIN_FFAST */
+ 0, /* Index=CGU_FREQIN_I2SRXBCK0 */
+ 0, /* Index=CGU_FREQIN_I2SRXWS0 */
+ 0, /* Index=CGU_FREQIN_I2SRXBCK1 */
+ 0, /* Index=CGU_FREQIN_I2SRXWS1 */
+ 0, /* Index=CGU_FREQIN_HPPLL0 (Audio/I2S PLL) */
+ 0 /* Index=CGU_FREQIN_HPPLL1 (System PLL) */
+};
+
/****************************************************************************
* Private Functions
****************************************************************************/
diff --git a/arch/arm/src/lpc313x/lpc313x_pllconfig.c b/arch/arm/src/lpc313x/lpc313x_pllconfig.c
new file mode 100755
index 0000000000000000000000000000000000000000..13d2acf5550f64db2ba984097469e361ea7803f1
--- /dev/null
+++ b/arch/arm/src/lpc313x/lpc313x_pllconfig.c
@@ -0,0 +1,267 @@
+/****************************************************************************
+ * arch/arm/src/lpc313x/lpc313x_pllconfig.c
+ *
+ * Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * References:
+ * - NXP UM10314 LPC3130/31 User manual Rev. 1.01 � 9 September 2009
+ * - NXP lpc313x.cdl.drivers.zip example driver code
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+#include <arch/board/board.h>
+
+#include "lpc313x_cgudrvr.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc313x_switchdomains
+ *
+ * Description:
+ * Temporarily switch the referemce clock of all domains whose selected
+ * input is the PLL-to-be configured .
+ *
+ ****************************************************************************/
+
+static inline uint16_t
+lpc313x_switchdomains(const struct lpc313x_pllconfig_s * const cfg)
+{
+ uint32_t hppll = (cfg->hppll ? CGU_SSR_HPPLL1 : CGU_SSR_HPPLL0);
+ uint32_t address;
+ uint32_t regval;
+ uint16_t dmnset = 0;
+ int i;
+
+ /* Check each domain */
+
+ for (i = 0; i < CGU_NDOMAINS; i++)
+ {
+ /* Get the switch status registers (SSR) for this frequency input domain */
+
+ address = LPC313X_CGU_SSR_OFFSET(i);
+ regval = getreg32(address);
+
+ /* Check if the current frequency selection is the PLL-to-be-configured */
+
+ if ((regval & CGU_SSR_FS_MASK) == hppll)
+ {
+ /* Yes.. switch reference clock in to FFAST */
+
+ lpc313x_selectfreqin(i, CGU_FS_FFAST);
+
+ /* Add the domain to the set to be restored after the PLL is configured */
+
+ dmnset |= (1 << i);
+ }
+ }
+
+ return dmnset;
+}
+
+/****************************************************************************
+ * Name: lpc313x_restoredomains
+ *
+ * Description:
+ * Restore the PLL reference clock to the domains that were temporarily
+ switched to FFAST by lpc313x_switchdomains.
+ *
+ ****************************************************************************/
+
+static inline void
+lpc313x_restoredomains(const struct lpc313x_pllconfig_s * const cfg,
+ uint16_t dmnset)
+{
+ uint32_t finsel = (cfg->hppll ? CGU_FS_HPPLL1 : CGU_FS_HPPLL0);
+ int i;
+
+ /* Check each domain */
+
+ for (i = 0; i < CGU_NDOMAINS; i++)
+ {
+ /* Was this one switched? */
+
+ if ((dmnset & (1 << i)) != 0)
+ {
+ /* Switch input reference clock to newly configured HPLL */
+
+ lpc313x_selectfreqin(i, finsel);
+ }
+ }
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc313x_pllconfig
+ *
+ * Description:
+ * Configure the PLL according to the provided selections.
+ *
+ ****************************************************************************/
+
+void lpc313x_pllconfig(const struct lpc313x_pllconfig_s * const cfg)
+{
+ uint32_t pllbase;
+ uint16_t dmnset = 0;
+
+ /* Switch domains connected to HPLL to FFAST */
+
+ dmnset = lpc313x_switchdomains(cfg);
+
+ /* Get the PLL register base address */
+
+ pllbase = LPC313x_CGU_HPPLL(cfg->hppll);
+
+ /* Disable clock, disable skew enable, power down pll, (dis/en)able post
+ * divider, (dis/en)able pre-divider, disable free running mode, disable bandsel,
+ * enable up limmiter, disable bypass
+ */
+
+ putreg32(CGU_HPMODE_PD, pllbase + LPC313X_CGU_HPMODE_OFFSET);
+
+ /* Select PLL input frequency source */
+
+ putreg32(cfg->finsel, pllbase + LPC313X_CGU_HPFINSEL_OFFSET);
+
+ /* Set M divider */
+
+ putreg32(cfg->mdec & CGU_HPMDEC_MASK, pllbase + LPC313X_CGU_HPMDEC_OFFSET);
+
+ /* Set N divider */
+
+ putreg32(cfg->ndec & CGU_HPNDEC_MASK, pllbase + LPC313X_CGU_HPNDEC_OFFSET);
+
+ /* Set P divider */
+
+ putreg32(cfg->pdec & CGU_HPPDEC_MASK, pllbase + LPC313X_CGU_HPPDEC_OFFSET);
+
+ /* Set bandwidth */
+
+ putreg32(cfg->selr, pllbase + LPC313X_CGU_HPSELR_OFFSET);
+ putreg32(cfg->seli, pllbase + LPC313X_CGU_HPSELI_OFFSET);
+ putreg32(cfg->selp, pllbase + LPC313X_CGU_HPSELP_OFFSET);
+
+ /* Power up pll */
+
+ putreg32((cfg->mode & ~CGU_HPMODE_PD) | CGU_HPMODE_CLKEN, pllbase + LPC313X_CGU_HPMODE_OFFSET);
+
+ /* Save the estimated freq in driver data for future clk calcs */
+
+ g_boardfreqin[CGU_FREQIN_HPPLL0 + cfg->hppll] = cfg->freq;
+
+ /* Wait for PLL to lock */
+
+ while ((getreg32(pllbase + LPC313X_CGU_HPSTATUS_OFFSET) & CGU_HPSTATUS_LOCK) == 0);
+
+ /* Switch the domains that were temporarily switched to FFAST back to the HPPLL */
+
+ lpc313x_restoredomains(cfg, dmnset);
+}
+
+/************************************************************************
+ * Name: lpc313x_hp0pllconfig
+ *
+ * Description:
+ * Configure the HP0 PLL according to the board.h selections.
+ *
+ ************************************************************************/
+
+void lpc313x_hp0pllconfig(void)
+{
+ struct lpc313x_pllconfig_s cfg =
+ {
+ .hppll = CGU_HP0PLL,
+ .finsel = BOARD_HPLL0_FINSEL,
+ .ndec = BOARD_HPLL0_NDEC,
+ .mdec = BOARD_HPLL0_MDEC,
+ .pdec = BOARD_HPLL0_PDEC,
+ .selr = BOARD_HPLL0_SELR,
+ .seli = BOARD_HPLL0_SELI,
+ .selp = BOARD_HPLL0_SELP,
+ .mode = BOARD_HPLL0_MODE,
+ .freq = BOARD_HPLL0_FREQ
+ };
+
+ lpc313x_pllconfig(&cfg);
+}
+
+/************************************************************************
+ * Name: lpc313x_hp1pllconfig
+ *
+ * Description:
+ * Configure the HP1 PLL according to the board.h selections.
+ *
+ ************************************************************************/
+
+void lpc313x_hp1pllconfig(void)
+{
+ struct lpc313x_pllconfig_s cfg =
+ {
+ .hppll = CGU_HP1PLL,
+ .finsel = BOARD_HPLL1_FINSEL,
+ .ndec = BOARD_HPLL1_NDEC,
+ .mdec = BOARD_HPLL1_MDEC,
+ .pdec = BOARD_HPLL1_PDEC,
+ .selr = BOARD_HPLL1_SELR,
+ .seli = BOARD_HPLL1_SELI,
+ .selp = BOARD_HPLL1_SELP,
+ .mode = BOARD_HPLL1_MODE,
+ .freq = BOARD_HPLL1_FREQ
+ };
+
+ lpc313x_pllconfig(&cfg);
+}
+
diff --git a/arch/arm/src/lpc313x/lpc313x_setfreqin.c b/arch/arm/src/lpc313x/lpc313x_setfreqin.c
new file mode 100755
index 0000000000000000000000000000000000000000..20411f3200db8eb564f4127e1e080502ab2fe29a
--- /dev/null
+++ b/arch/arm/src/lpc313x/lpc313x_setfreqin.c
@@ -0,0 +1,119 @@
+/****************************************************************************
+ * arch/arm/src/lpc313x/lpc313x_setfreqin.c
+ *
+ * Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * References:
+ * - NXP UM10314 LPC3130/31 User manual Rev. 1.01 � 9 September 2009
+ * - NXP lpc313x.cdl.drivers.zip example driver code
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+#include <arch/board/board.h>
+
+#include "lpc313x_cgudrvr.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: lpc313x_selectfreqin
+ *
+ * Description:
+ * Set the base frequency source selection for with a clock domain
+ *
+ ****************************************************************************/
+
+void lpc313x_selectfreqin(enum lpc313x_domainid_e dmnid, uint32_t finsel)
+{
+ uint32_t scraddr = LPC313X_CGU_SCR(dmnid);
+ uint32_t fs1addr = LPC313X_CGU_FS1(dmnid);
+ uint32_t fs2addr = LPC313X_CGU_FS2(dmnid);
+ uint32_t scrbits;
+
+ /* Get the frequency selection from the switch configuration register (SCR)
+ * for this domain.
+ */
+
+ scrbits = getreg32(scraddr) & ~(CGU_SCR_ENF1|CGU_SCR_ENF2);
+
+ /* If FS1 is currently enabled set the reference clock to FS2 and enable FS2 */
+
+ if (getreg32(LPC313X_CGU_SSR(dmnid) & CGU_SSR_FS1STAT) != 0)
+ {
+ /* Check if the selected frequency, FS1, is same as requested */
+
+ if ((getreg32(fs1addr) & CGU_FS_MASK) != finsel)
+ {
+ /* No.. Set up FS2 */
+
+ putreg32(finsel, fs2addr);
+ putreg32(scrbits | CGU_SCR_ENF2, scraddr);
+ }
+ }
+
+ /* FS1 is not currently enabled, check if the selected frequency, FS2,
+ * is same as requested
+ */
+
+ else if ((getreg32(fs2addr) & CGU_FS_MASK) != finsel)
+ {
+ /* No.. Set up FS1 */
+
+ putreg32(finsel, fs1addr);
+ putreg32(scrbits | CGU_SCR_ENF1, scraddr);
+ }
+}
diff --git a/configs/ea3131/include/board.h b/configs/ea3131/include/board.h
index c3ce4451ae5d07783749a948ec4847d2b19cd6e3..8eb6c3acab0961b9131bc70ca632c3a987ff029a 100755
--- a/configs/ea3131/include/board.h
+++ b/configs/ea3131/include/board.h
@@ -52,15 +52,33 @@
************************************************************************************/
/* Clocking *************************************************************************/
-/* Frequency of the all inputs */
+/* Frequency of the FFAST input */
#define BOARD_FREQIN_FFAST (12000000) /* ffast (12 MHz crystal) */
-#define BOARD_FREQIN_I2SRXBCK0 0 /* I2SRX_BCK0 */
-#define BOARD_FREQIN_I2SRXWS0 0 /* I2SRX_WS0 */
-#define BOARD_FREQIN_I2SRXBCK1 0 /* I2SRX_BCK1 */
-#define BOARD_FREQIN_I2SRXWS1 0 /* I2SRX_WS1 */
-#define BOARD_FREQIN_HPPLL0 0 /* HPPLL0 (Audio/I2S PLL)) */
-#define BOARD_FREQIN_HPPLL1 0 /* HPPLL1 (System PLL */
+
+/* HPLL0 configuration */
+
+#define BOARD_HPLL0_FINSEL CGU_HPFINSEL_FFAST /* Frequency input selection */
+#define BOARD_HPLL0_NDEC 131 /* PLL N-divider value */
+#define BOARD_HPLL0_MDEC 29784 /* PLL M-divider value */
+#define BOARD_HPLL0_PDEC 7 /* PLL P-divider value */
+#define BOARD_HPLL0_SELR 0 /* SELR bandwidth selection */
+#define BOARD_HPLL0_SELI 8 /* SELI bandwidth selection */
+#define BOARD_HPLL0_SELP 31 /* SELP bandwidth selection */
+#define BOARD_HPLL0_MODE 0 /* PLL mode */
+#define BOARD_HPLL0_FREQ 406425600 /* Frequency of the PLL in MHz */
+
+/* HPLL1 configuration */
+
+#define BOARD_HPLL1_FINSEL CGU_HPFINSEL_FFAST /* Frequency input selection */
+#define BOARD_HPLL1_NDEC 770 /* PLL N-divider value */
+#define BOARD_HPLL1_MDEC 8191 /* PLL M-divider value */
+#define BOARD_HPLL1_PDEC 98 /* PLL P-divider value */
+#define BOARD_HPLL1_SELR 0 /* SELR bandwidth selection */
+#define BOARD_HPLL1_SELI 16 /* SELI bandwidth selection */
+#define BOARD_HPLL1_SELP 8 /* SELP bandwidth selection */
+#define BOARD_HPLL1_MODE 0 /* PLL mode */
+#define BOARD_HPLL1_FREQ 180000000 /* Frequency of the PLL in MHz */
/* The following 3 bitsets determine which clocks will be enabled at initialization
* time.