diff --git a/arch/mips/include/pic32mx/irq.h b/arch/mips/include/pic32mx/irq.h
index 2ca2992e4e56fa409524c3cbc6ec137def10b6df..269acceb3120d3fff3e5340db1efdf4358e5e825 100755
--- a/arch/mips/include/pic32mx/irq.h
+++ b/arch/mips/include/pic32mx/irq.h
@@ -45,9 +45,56 @@
****************************************************************************/
/****************************************************************************
- * Definitions
+ * Pre-processor Definitions
****************************************************************************/
+#define PIC32MX_IRQ_CT 0 /* Vector: 0, Core Timer Interrupt */
+#define PIC32MX_IRQ_CS0 1 /* Vector: 1, Core Software Interrupt 0 */
+#define PIC32MX_IRQ_CS1 2 /* Vector: 2, Core Software Interrupt 1 */
+#define PIC32MX_IRQ_INT0 3 /* Vector: 3, External Interrupt 0 */
+#define PIC32MX_IRQ_T1 4 /* Vector: 4, Timer 1 */
+#define PIC32MX_IRQ_IC1 5 /* Vector: 5, Input Capture 1 */
+#define PIC32MX_IRQ_OC1 6 /* Vector: 6, Output Compare 1 */
+#define PIC32MX_IRQ_INT1 7 /* Vector: 7, External Interrupt 1 */
+#define PIC32MX_IRQ_T2 8 /* Vector: 8, Timer 2 */
+#define PIC32MX_IRQ_IC2 9 /* Vector: 9, Input Capture 2 */
+#define PIC32MX_IRQ_OC2 10 /* Vector: 10, Output Compare 2 */
+#define PIC32MX_IRQ_INT2 11 /* Vector: 11, External Interrupt 2 */
+#define PIC32MX_IRQ_T3 12 /* Vector: 12, Timer 3 */
+#define PIC32MX_IRQ_IC3 13 /* Vector: 13, Input Capture 3 */
+#define PIC32MX_IRQ_OC3 14 /* Vector: 14, Output Compare 3 */
+#define PIC32MX_IRQ_INT3 15 /* Vector: 15, External Interrupt 3 */
+#define PIC32MX_IRQ_T4 16 /* Vector: 16, Timer 4 */
+#define PIC32MX_IRQ_IC4 17 /* Vector: 17, Input Capture 4 */
+#define PIC32MX_IRQ_OC4 18 /* Vector: 18, Output Compare 4 */
+#define PIC32MX_IRQ_INT4 19 /* Vector: 19, External Interrupt 4 */
+#define PIC32MX_IRQ_T5 20 /* Vector: 20, Timer 5 */
+#define PIC32MX_IRQ_IC5 21 /* Vector: 21, Input Capture 5 */
+#define PIC32MX_IRQ_OC5 22 /* Vector: 22, Output Compare 5 */
+#define PIC32MX_IRQ_SPI1E 23 /* Vector: 23, SPI1 */
+#define PIC32MX_IRQ_U1E 24 /* Vector: 24, UART1 */
+#define PIC32MX_IRQ_I2C1B 25 /* Vector: 25, I2C1 */
+#define PIC32MX_IRQ_CN 26 /* Vector: 26, Input Change Interrupt */
+#define PIC32MX_IRQ_AD1 27 /* Vector: 27, ADC1 Convert Done */
+#define PIC32MX_IRQ_PMP 28 /* Vector: 28, Parallel Master Port */
+#define PIC32MX_IRQ_CMP1 29 /* Vector: 29, Comparator Interrupt */
+#define PIC32MX_IRQ_CMP2 30 /* Vector: 30, Comparator Interrupt */
+#define PIC32MX_IRQ_SPI2E 31 /* Vector: 31, SPI2 */
+#define PIC32MX_IRQ_U2E 32 /* Vector: 32, UART2 */
+#define PIC32MX_IRQ_I2C2B 33 /* Vector: 33, I2C2 */
+#define PIC32MX_IRQ_FSCM 34 /* Vector: 34, Fail-Safe Clock Monitor */
+#define PIC32MX_IRQ_RTCC 35 /* Vector: 35, Real-Time Clock and Calendar */
+#define PIC32MX_IRQ_DMA0 36 /* Vector: 36, DMA Channel 0 */
+#define PIC32MX_IRQ_DMA1 37 /* Vector: 37, DMA Channel 1 */
+#define PIC32MX_IRQ_DMA2 38 /* Vector: 38, DMA Channel 2 */
+#define PIC32MX_IRQ_DMA3 39 /* Vector: 39, DMA Channel 3 */
+ /* Vectors 40-43: Not used */
+#define PIC32MX_IRQ_FCE 44 /* Vector: 44, Flash Control Event */
+#define PIC32MX_IRQ_USB 45 /* Vector: 45, USB */
+
+#define PIC32MX_IRQ_BAD 46 /* Not a real IRQ number */
+#define NR_IRQS 46
+
/****************************************************************************
* Public Types
****************************************************************************/
diff --git a/arch/mips/src/pic32mx/chip.h b/arch/mips/src/pic32mx/chip.h
index fdd38412750dd2712f7c9e444d46ea1228e9f7d1..8f9b9f32ff3bfc76f7257aec6bcbf3c6674b1228 100755
--- a/arch/mips/src/pic32mx/chip.h
+++ b/arch/mips/src/pic32mx/chip.h
@@ -47,6 +47,401 @@
****************************************************************************/
/* Configuration ************************************************************/
+#if defined(CONFIG_ARCH_CHIP_PIC32MX320F032H)
+# define CHIP_PIC32MX3 1
+# undef CHIP_PIC32MX4
+# define CHIP_NPINS 64 /* Package PT, MR */
+# define CHIP_MHZ 40
+# define CHIP_BOOTFLASH_KB 12
+# define CHIP_PROGFLASH_KB 32
+# define CHIP_DATAMEM_KB 8
+# define CHIP_NTIMERS 5
+# define CHIP_NCAPTURE 5
+# define CHIP_NCOMPARE 5
+# define CHIP_NDMACHAN 0
+# define CHIP_NUSBDMACHAN 0
+# define CHIP_VREG
+# undef CHIP_TRACE
+# define CHIP_NEUARTS 2
+# define CHIP_NSPI 2
+# define CHIP_NI2C 2
+# define CHIP_NADC10 16
+# define CHIP_NCOMPARATORS 2
+# define CHIP_PMP
+# define CHIP_PSP
+# define CHIP_JTAH
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX320F064H)
+# define CHIP_PIC32MX3 1
+# undef CHIP_PIC32MX4
+# define CHIP_NPINS 64 /* Package PT, MR */
+# define CHIP_MHZ 80
+# define CHIP_BOOTFLASH_KB 12
+# define CHIP_PROGFLASH_KB 64
+# define CHIP_DATAMEM_KB 16
+# define CHIP_NTIMERS 5
+# define CHIP_NCAPTURE 5
+# define CHIP_NCOMPARE 5
+# define CHIP_NDMACHAN 0
+# define CHIP_NUSBDMACHAN 0
+# define CHIP_VREG
+# undef CHIP_TRACE
+# define CHIP_NEUARTS 2
+# define CHIP_NSPI 2
+# define CHIP_NI2C 2
+# define CHIP_NADC10 16
+# define CHIP_NCOMPARATORS 2
+# define CHIP_PMP
+# define CHIP_PSP
+# define CHIP_JTAH
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX320F128H)
+# define CHIP_PIC32MX3 1
+# undef CHIP_PIC32MX4
+# define CHIP_NPINS 64 /* Package PT, MR */
+# define CHIP_MHZ 80
+# define CHIP_BOOTFLASH_KB 12
+# define CHIP_PROGFLASH_KB 128
+# define CHIP_DATAMEM_KB 16
+# define CHIP_NTIMERS 5
+# define CHIP_NCAPTURE 5
+# define CHIP_NCOMPARE 5
+# define CHIP_NDMACHAN 0
+# define CHIP_NUSBDMACHAN 0
+# define CHIP_VREG
+# undef CHIP_TRACE
+# define CHIP_NEUARTS 2
+# define CHIP_NSPI 2
+# define CHIP_NI2C 2
+# define CHIP_NADC10 16
+# define CHIP_NCOMPARATORS 2
+# define CHIP_PMP
+# define CHIP_PSP
+# define CHIP_JTAH
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX340F128H)
+# define CHIP_PIC32MX3 1
+# undef CHIP_PIC32MX4
+# define CHIP_NPINS 64 /* Package PT, MR */
+# define CHIP_MHZ 80
+# define CHIP_BOOTFLASH_KB 12
+# define CHIP_PROGFLASH_KB 128
+# define CHIP_DATAMEM_KB 32
+# define CHIP_NTIMERS 5
+# define CHIP_NCAPTURE 5
+# define CHIP_NCOMPARE 5
+# define CHIP_NDMACHAN 4
+# define CHIP_NUSBDMACHAN 0
+# define CHIP_VREG
+# undef CHIP_TRACE
+# define CHIP_NEUARTS 2
+# define CHIP_NSPI 2
+# define CHIP_NI2C 2
+# define CHIP_NADC10 16
+# define CHIP_NCOMPARATORS 2
+# define CHIP_PMP
+# define CHIP_PSP
+# define CHIP_JTAH
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX340F256H)
+# define CHIP_PIC32MX3 1
+# undef CHIP_PIC32MX4
+# define CHIP_NPINS 64 /* Package PT, MR */
+# define CHIP_MHZ 80
+# define CHIP_BOOTFLASH_KB 12
+# define CHIP_PROGFLASH_KB 256
+# define CHIP_DATAMEM_KB 32
+# define CHIP_NTIMERS 5
+# define CHIP_NCAPTURE 5
+# define CHIP_NCOMPARE 5
+# define CHIP_NDMACHAN 4
+# define CHIP_NUSBDMACHAN 0
+# define CHIP_VREG
+# undef CHIP_TRACE
+# define CHIP_NEUARTS 2
+# define CHIP_NSPI 2
+# define CHIP_NI2C 2
+# define CHIP_NADC10 16
+# define CHIP_NCOMPARATORS 2
+# define CHIP_PMP
+# define CHIP_PSP
+# define CHIP_JTAH
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX340F512H)
+# define CHIP_PIC32MX3 1
+# undef CHIP_PIC32MX4
+# define CHIP_NPINS 64 /* Package PT, MR */
+# define CHIP_MHZ 80
+# define CHIP_BOOTFLASH_KB 12
+# define CHIP_PROGFLASH_KB 512
+# define CHIP_DATAMEM_KB 32
+# define CHIP_NTIMERS 5
+# define CHIP_NCAPTURE 5
+# define CHIP_NCOMPARE 5
+# define CHIP_NDMACHAN 4
+# define CHIP_NUSBDMACHAN 0
+# define CHIP_VREG
+# undef CHIP_TRACE
+# define CHIP_NEUARTS 2
+# define CHIP_NSPI 2
+# define CHIP_NI2C 2
+# define CHIP_NADC10 16
+# define CHIP_NCOMPARATORS 2
+# define CHIP_PMP
+# define CHIP_PSP
+# define CHIP_JTAH
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX320F128L)
+# define CHIP_PIC32MX3 1
+# undef CHIP_PIC32MX4
+# define CHIP_NPINS 100 /* Package PT=100 BG=121 */
+# define CHIP_MHZ 80
+# define CHIP_BOOTFLASH_KB 12
+# define CHIP_PROGFLASH_KB 128
+# define CHIP_DATAMEM_KB 16
+# define CHIP_NTIMERS 5
+# define CHIP_NCAPTURE 5
+# define CHIP_NCOMPARE 5
+# define CHIP_NDMACHAN 0
+# define CHIP_NUSBDMACHAN 0
+# define CHIP_VREG
+# undef CHIP_TRACE
+# define CHIP_NEUARTS 2
+# define CHIP_NSPI 2
+# define CHIP_NI2C 2
+# define CHIP_NADC10 16
+# define CHIP_NCOMPARATORS 2
+# define CHIP_PMP
+# define CHIP_PSP
+# define CHIP_JTAH
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX340F128L)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4 1
+# define CHIP_NPINS 100 /* Package PT=100 BG=121 */
+# define CHIP_MHZ 80
+# define CHIP_BOOTFLASH_KB 12
+# define CHIP_PROGFLASH_KB 128
+# define CHIP_DATAMEM_KB 32
+# define CHIP_NTIMERS 5
+# define CHIP_NCAPTURE 5
+# define CHIP_NCOMPARE 5
+# define CHIP_NDMACHAN 4
+# define CHIP_NUSBDMACHAN 0
+# define CHIP_VREG
+# undef CHIP_TRACE
+# define CHIP_NEUARTS 2
+# define CHIP_NSPI 2
+# define CHIP_NI2C 2
+# define CHIP_NADC10 16
+# define CHIP_NCOMPARATORS 2
+# define CHIP_PMP
+# define CHIP_PSP
+# define CHIP_JTAH
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX360F256L)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4 1
+# define CHIP_NPINS 100 /* Package PT=100 BG=121 */
+# define CHIP_MHZ 80
+# define CHIP_BOOTFLASH_KB 12
+# define CHIP_PROGFLASH_KB 256
+# define CHIP_DATAMEM_KB 32
+# define CHIP_NTIMERS 5
+# define CHIP_NCAPTURE 5
+# define CHIP_NCOMPARE 5
+# define CHIP_NDMACHAN 4
+# define CHIP_NUSBDMACHAN 0
+# define CHIP_VREG
+# define CHIP_TRACE
+# define CHIP_NEUARTS 2
+# define CHIP_NSPI 2
+# define CHIP_NI2C 2
+# define CHIP_NADC10 16
+# define CHIP_NCOMPARATORS 2
+# define CHIP_PMP
+# define CHIP_PSP
+# define CHIP_JTAH
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX360F512L)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4 1
+# define CHIP_NPINS 100 /* Package PT=100 BG=121 */
+# define CHIP_MHZ 80
+# define CHIP_BOOTFLASH_KB 12
+# define CHIP_PROGFLASH_KB 512
+# define CHIP_DATAMEM_KB 32
+# define CHIP_NTIMERS 5
+# define CHIP_NCAPTURE 5
+# define CHIP_NCOMPARE 5
+# define CHIP_NDMACHAN 4
+# define CHIP_NUSBDMACHAN 0
+# define CHIP_VREG
+# define CHIP_TRACE
+# define CHIP_NEUARTS 2
+# define CHIP_NSPI 2
+# define CHIP_NI2C 2
+# define CHIP_NADC10 16
+# define CHIP_NCOMPARATORS 2
+# define CHIP_PMP
+# define CHIP_PSP
+# define CHIP_JTAH
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX420F032H)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4 1
+# define CHIP_NPINS 64 /* Package PT, MR */
+# define CHIP_MHZ 40
+# define CHIP_BOOTFLASH_KB 12
+# define CHIP_PROGFLASH_KB 32
+# define CHIP_DATAMEM_KB 8
+# define CHIP_NTIMERS 5
+# define CHIP_NCAPTURE 5
+# define CHIP_NCOMPARE 5
+# define CHIP_NDMACHAN 0
+# define CHIP_NUSBDMACHAN 2
+# define CHIP_VREG
+# undef CHIP_TRACE
+# define CHIP_NEUARTS 2
+# define CHIP_NSPI 1
+# define CHIP_NI2C 2
+# define CHIP_NADC10 16
+# define CHIP_NCOMPARATORS 2
+# define CHIP_PMP
+# define CHIP_PSP
+# define CHIP_JTAH
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX440F128H)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4 1
+# define CHIP_NPINS 64 /* Package PT, MR */
+# define CHIP_MHZ 40
+# define CHIP_BOOTFLASH_KB 12
+# define CHIP_PROGFLASH_KB 128
+# define CHIP_DATAMEM_KB 32
+# define CHIP_NTIMERS 5
+# define CHIP_NCAPTURE 5
+# define CHIP_NCOMPARE 5
+# define CHIP_NDMACHAN 4
+# define CHIP_NUSBDMACHAN 2
+# define CHIP_VREG
+# undef CHIP_TRACE
+# define CHIP_NEUARTS 2
+# define CHIP_NSPI 1
+# define CHIP_NI2C 2
+# define CHIP_NADC10 16
+# define CHIP_NCOMPARATORS 2
+# define CHIP_PMP
+# define CHIP_PSP
+# define CHIP_JTAH
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX440F256H)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4 1
+# define CHIP_NPINS 64 /* Package PT, MR */
+# define CHIP_MHZ 80
+# define CHIP_BOOTFLASH_KB 12
+# define CHIP_PROGFLASH_KB 256
+# define CHIP_DATAMEM_KB 32
+# define CHIP_NTIMERS 5
+# define CHIP_NCAPTURE 5
+# define CHIP_NCOMPARE 5
+# define CHIP_NDMACHAN 4
+# define CHIP_NUSBDMACHAN 2
+# define CHIP_VREG
+# undef CHIP_TRACE
+# define CHIP_NEUARTS 2
+# define CHIP_NSPI 1
+# define CHIP_NI2C 2
+# define CHIP_NADC10 16
+# define CHIP_NCOMPARATORS 2
+# define CHIP_PMP
+# define CHIP_PSP
+# define CHIP_JTAH
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX440F512H)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4 1
+# define CHIP_NPINS 64 /* Package PT, MR */
+# define CHIP_MHZ 80
+# define CHIP_BOOTFLASH_KB 12
+# define CHIP_PROGFLASH_KB 512
+# define CHIP_DATAMEM_KB 32
+# define CHIP_NTIMERS 5
+# define CHIP_NCAPTURE 5
+# define CHIP_NCOMPARE 5
+# define CHIP_NDMACHAN 4
+# define CHIP_NUSBDMACHAN 2
+# define CHIP_VREG
+# undef CHIP_TRACE
+# define CHIP_NEUARTS 2
+# define CHIP_NSPI 1
+# define CHIP_NI2C 2
+# define CHIP_NADC10 16
+# define CHIP_NCOMPARATORS 2
+# define CHIP_PMP
+# define CHIP_PSP
+# define CHIP_JTAH
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX440F128L)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4 1
+# define CHIP_NPINS 100 /* Package PT=100 BG=121 */
+# define CHIP_MHZ 80
+# define CHIP_BOOTFLASH_KB 12
+# define CHIP_PROGFLASH_KB 128
+# define CHIP_DATAMEM_KB 32
+# define CHIP_NTIMERS 5
+# define CHIP_NCAPTURE 5
+# define CHIP_NCOMPARE 5
+# define CHIP_NDMACHAN 4
+# define CHIP_NUSBDMACHAN 2
+# define CHIP_VREG
+# undef CHIP_TRACE
+# define CHIP_NEUARTS 2
+# define CHIP_NSPI 2
+# define CHIP_NI2C 2
+# define CHIP_NADC10 16
+# define CHIP_NCOMPARATORS 2
+# define CHIP_PMP
+# define CHIP_PSP
+# define CHIP_JTAH
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX460F256L)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4 1
+# define CHIP_NPINS 100 /* Package PT=100 BG=121 */
+# define CHIP_MHZ 80
+# define CHIP_BOOTFLASH_KB 12
+# define CHIP_PROGFLASH_KB 256
+# define CHIP_DATAMEM_KB 32
+# define CHIP_NTIMERS 5
+# define CHIP_NCAPTURE 5
+# define CHIP_NCOMPARE 5
+# define CHIP_NDMACHAN 4
+# define CHIP_NUSBDMACHAN 2
+# define CHIP_VREG
+# define CHIP_TRACE
+# define CHIP_NEUARTS 2
+# define CHIP_NSPI 2
+# define CHIP_NI2C 2
+# define CHIP_NADC10 16
+# define CHIP_NCOMPARATORS 2
+# define CHIP_PMP
+# define CHIP_PSP
+# define CHIP_JTAH
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX460F512L)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4 1
+# define CHIP_NPINS 100 /* Package PT=100 BG=121 */
+# define CHIP_MHZ 80
+# define CHIP_BOOTFLASH_KB 12
+# define CHIP_PROGFLASH_KB 512
+# define CHIP_DATAMEM_KB 32
+# define CHIP_NTIMERS 5
+# define CHIP_NCAPTURE 5
+# define CHIP_NCOMPARE 5
+# define CHIP_NDMACHAN 4
+# define CHIP_NUSBDMACHAN 2
+# define CHIP_VREG
+# define CHIP_TRACE
+# define CHIP_NEUARTS 2
+# define CHIP_NSPI 2
+# define CHIP_NI2C 2
+# define CHIP_NADC10 16
+# define CHIP_NCOMPARATORS 2
+# define CHIP_PMP
+# define CHIP_PSP
+# define CHIP_JTAH
+#else
+# error "Unrecognized PIC32 device
+#endif
+
/****************************************************************************
* Public Types
****************************************************************************/
diff --git a/arch/mips/src/pic32mx/pic32mx-devcfg.h b/arch/mips/src/pic32mx/pic32mx-devcfg.h
new file mode 100755
index 0000000000000000000000000000000000000000..b5b9127bbce3ec01bf3e5300e47f3e194f5100b9
--- /dev/null
+++ b/arch/mips/src/pic32mx/pic32mx-devcfg.h
@@ -0,0 +1,230 @@
+/****************************************************************************
+ * arch/mips/src/pic32mx/pic32mx-devcfg.h
+ *
+ * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DEVCFG_H
+#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DEVCFG_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "pic32mx-memorymap.h"
+
+/****************************************************************************
+ * Pre-Processor Definitions
+ ****************************************************************************/
+/* Register Offsets *********************************************************/
+
+#define PIC32MX_DEVCFG3_OFFSET 0x0000 /* Device configuration word 3 */
+#define PIC32MX_DEVCFG2_OFFSET 0x0004 /* Device configuration word 2 */
+#define PIC32MX_DEVCFG1_OFFSET 0x0008 /* Device configuration word 1 */
+#define PIC32MX_DEVCFG0_OFFSET 0x000c /* Device configuration word 0 */
+
+/* Register Addresses *******************************************************/
+
+#define PIC32MX_DEVCFG3 (PIC32MX_DEVCFG_K1BASE+PIC32MX_DEVCFG3_OFFSET)
+#define PIC32MX_DEVCFG2 (PIC32MX_DEVCFG_K1BASE+PIC32MX_DEVCFG2_OFFSET)
+#define PIC32MX_DEVCFG1 (PIC32MX_DEVCFG_K1BASE+PIC32MX_DEVCFG1_OFFSET)
+#define PIC32MX_DEVCFG0 (PIC32MX_DEVCFG_K1BASE+PIC32MX_DEVCFG0_OFFSET)
+
+/* Register Bit-Field Definitions *******************************************/
+
+/* Device configuration word 3 */
+
+#define DEVCFG3_USERID(n) (1 << (n))
+#define DEVCFG3_USERID0 (1 << 0) /* Bit 0: xx */
+#define DEVCFG3_USERID1 (1 << 1) /* Bit 1: xx */
+#define DEVCFG3_USERID2 (1 << 2) /* Bit 2: xx */
+#define DEVCFG3_USERID3 (1 << 3) /* Bit 3: xx */
+#define DEVCFG3_USERID4 (1 << 4) /* Bit 4: xx */
+#define DEVCFG3_USERID5 (1 << 5) /* Bit 5: xx */
+#define DEVCFG3_USERID6 (1 << 6) /* Bit 6: xx */
+#define DEVCFG3_USERID7 (1 << 7) /* Bit 7: xx */
+#define DEVCFG3_USERID8 (1 << 8) /* Bit 8: xx */
+#define DEVCFG3_USERID9 (1 << 9) /* Bit 9: xx */
+#define DEVCFG3_USERID10 (1 << 10) /* Bit 10: xx */
+#define DEVCFG3_USERID11 (1 << 11) /* Bit 11: xx */
+#define DEVCFG3_USERID12 (1 << 12) /* Bit 12: xx */
+#define DEVCFG3_USERID13 (1 << 13) /* Bit 13: xx */
+#define DEVCFG3_USERID14 (1 << 14) /* Bit 14: xx */
+#define DEVCFG3_USERID15 (1 << 15) /* Bit 15: xx */
+
+/* Device configuration word 2 */
+
+#define DEVCFG2_FPLLIDIV_SHIFT (0) /* Bits 0-2: PLL input divider value */
+#define DEVCFG2_FPLLIDIV_MASK (7 << DEVCFG2_FPLLIDIV_SHIFT)
+# define DEVCFG2_FPLLIDIV_DIV1 (0 << DEVCFG2_FPLLIDIV_SHIFT)
+# define DEVCFG2_FPLLIDIV_DIV2 (1 << DEVCFG2_FPLLIDIV_SHIFT)
+# define DEVCFG2_FPLLIDIV_DIV3 (2 << DEVCFG2_FPLLIDIV_SHIFT)
+# define DEVCFG2_FPLLIDIV_DIV4 (3 << DEVCFG2_FPLLIDIV_SHIFT)
+# define DEVCFG2_FPLLIDIV_DIV5 (4 << DEVCFG2_FPLLIDIV_SHIFT)
+# define DEVCFG2_FPLLIDIV_DIV6 (5 << DEVCFG2_FPLLIDIV_SHIFT)
+# define DEVCFG2_FPLLIDIV_DIV10 (6 << DEVCFG2_FPLLIDIV_SHIFT)
+# define DEVCFG2_FPLLIDIV_DIV12 (7 << DEVCFG2_FPLLIDIV_SHIFT)
+#define DEVCFG2_FPLLMULT_SHIFT (4) /* Bits 4-6: Initial PLL multiplier value */
+#define DEVCFG2_FPLLMULT_MASK (7 << DEVCFG2_FPLLMULT_SHIFT)
+# define DEVCFG2_FPLLMULT_MUL15 (0 << DEVCFG2_FPLLMULT_SHIFT)
+# define DEVCFG2_FPLLMULT_MUL16 (1 << DEVCFG2_FPLLMULT_SHIFT)
+# define DEVCFG2_FPLLMULT_MUL17 (2 << DEVCFG2_FPLLMULT_SHIFT)
+# define DEVCFG2_FPLLMULT_MUL18 (3 << DEVCFG2_FPLLMULT_SHIFT)
+# define DEVCFG2_FPLLMULT_MUL19 (4 << DEVCFG2_FPLLMULT_SHIFT)
+# define DEVCFG2_FPLLMULT_MUL20 (5 << DEVCFG2_FPLLMULT_SHIFT)
+# define DEVCFG2_FPLLMULT_MUL21 (6 << DEVCFG2_FPLLMULT_SHIFT)
+# define DEVCFG2_FPLLMULT_MUL24 (7 << DEVCFG2_FPLLMULT_SHIFT)
+#define DEVCFG2_FUPLLIDIV_SHIFT (8) /* Bits 8-10: PLL input divider */
+#define DEVCFG2_FUPLLIDIV_MASK (7 << DEVCFG2_FUPLLIDIV_SHIFT)
+# define DEVCFG2_FUPLLIDIV_DIV1 (0 << DEVCFG2_FUPLLIDIV_SHIFT)
+# define DEVCFG2_FUPLLIDIV_DIV2 (1 << DEVCFG2_FUPLLIDIV_SHIFT)
+# define DEVCFG2_FUPLLIDIV_DIV3 (2 << DEVCFG2_FUPLLIDIV_SHIFT)
+# define DEVCFG2_FUPLLIDIV_DIV4 (3 << DEVCFG2_FUPLLIDIV_SHIFT)
+# define DEVCFG2_FUPLLIDIV_DIV5 (4 << DEVCFG2_FUPLLIDIV_SHIFT)
+# define DEVCFG2_FUPLLIDIV_DIV6 (5 << DEVCFG2_FUPLLIDIV_SHIFT)
+# define DEVCFG2_FUPLLIDIV_DIV10 (6 << DEVCFG2_FUPLLIDIV_SHIFT)
+# define DEVCFG2_FUPLLIDIV_DIV12 (7 << DEVCFG2_FUPLLIDIV_SHIFT)
+#define DEVCFG2_FUPLLEN (1 << 15) /* Bit 15: USB PLL enable */
+#define DEVCFG2_FPLLODIV_SHIFT (16) /* Bits 16-18: Default postscaler for PLL bits */
+#define DEVCFG2_FPLLODIV_MASK (7 << DEVCFG2_FPLLODIV_SHIFT)
+# define DEVCFG2_FPLLODIV_DIV1 (0 << DEVCFG2_FPLLODIV_SHIFT)
+# define DEVCFG2_FPLLODIV_DIV2 (1 << DEVCFG2_FPLLODIV_SHIFT)
+# define DEVCFG2_FPLLODIV_DIV4 (2 << DEVCFG2_FPLLODIV_SHIFT)
+# define DEVCFG2_FPLLODIV_DIV8 (3 << DEVCFG2_FPLLODIV_SHIFT)
+# define DEVCFG2_FPLLODIV_DIV16 (4 << DEVCFG2_FPLLODIV_SHIFT)
+# define DEVCFG2_FPLLODIV_DIV32 (5 << DEVCFG2_FPLLODIV_SHIFT)
+# define DEVCFG2_FPLLODIV_DIV64 (6 << DEVCFG2_FPLLODIV_SHIFT)
+# define DEVCFG2_FPLLODIV_DIV256 (7 << DEVCFG2_FPLLODIV_SHIFT)
+
+/* Device configuration word 1 */
+
+#define DEVCFG1_FNOSC_SHIFT (0) /* Bits 0-2: Oscillator xelection */
+#define DEVCFG1_FNOSC_MASK (7 << DEVCFG1_FNOSC_SHIFT)
+# define DEVCFG1_FNOSC_ FRC (0 << DEVCFG1_FNOSC_SHIFT) /* FRC oscillator */
+# define DEVCFG1_FNOSC_ FRCPLL (1 << DEVCFG1_FNOSC_SHIFT) /* FRC w/PLL module */
+# define DEVCFG1_FNOSC_ POSC (2 << DEVCFG1_FNOSC_SHIFT) /* Primary oscillator */
+# define DEVCFG1_FNOSC_ POSCPLL (3 << DEVCFG1_FNOSC_SHIFT) /* Primary oscillator w/PLL */
+# define DEVCFG1_FNOSC_ SOSC (4 << DEVCFG1_FNOSC_SHIFT) /* Secondary oscillator */
+# define DEVCFG1_FNOSC_ LPRC (5 << DEVCFG1_FNOSC_SHIFT) /* Low power RC oscillator */
+# define DEVCFG1_FNOSC_ FRCDIV (7 << DEVCFG1_FNOSC_SHIFT) /* FRC oscillator with FRCDIV */
+#define DEVCFG1_FSOSCEN (1 << 5) /* Bit 5: Secondary oscillator (sosc) enable bit */
+#define DEVCFG1_IESO (1 << 7) /* Bit 7: Internal external switch over */
+#define DEVCFG1_POSCMOD_SHIFT (8) /* Bits 8-9: Primary oscillator (posc) configuration */
+#define DEVCFG1_POSCMOD_MASK (3 << DEVCFG1_POSCMOD_SHIFT)
+# define DEVCFG1_POSCMOD_ EC (0 << DEVCFG1_POSCMOD_SHIFT) /* EC mode */
+# define DEVCFG1_POSCMOD_ XT (1 << DEVCFG1_POSCMOD_SHIFT) /* XT mode */
+# define DEVCFG1_POSCMOD_ HS (2 << DEVCFG1_POSCMOD_SHIFT) /* HS mode */
+# define DEVCFG1_POSCMOD_DIS (3 << DEVCFG1_POSCMOD_SHIFT) /* Primary Oscillator disabled */
+#define DEVCFG1_OSCIOFNC (1 << 10) /* Bit 10: CLKO (clock-out) enable configuration */
+#define DEVCFG1_FPBDIV_SHIFT (12) /* Bits 12-13: Peripheral bus clock divisor default value */
+#define DEVCFG1_FPBDIV_MASK (3 << DEVCFG1_FPBDIV_SHIFT)
+# define DEVCFG1_FPBDIV_DIV1 (0 << DEVCFG1_FPBDIV_SHIFT) /* PBCLK is SYSCLK/1 */
+# define DEVCFG1_FPBDIV_DIV2 (1 << DEVCFG1_FPBDIV_SHIFT) /* PBCLK is SYSCLK/2 */
+# define DEVCFG1_FPBDIV_DIV4 (2 << DEVCFG1_FPBDIV_SHIFT) /* PBCLK is SYSCLK/4 */
+# define DEVCFG1_FPBDIV_DIV8 (3 << DEVCFG1_FPBDIV_SHIFT) /* PBCLK is SYSCLK /8 */
+#define DEVCFG1_FCKSM_SHIFT (14) /* Bits 14-15: Clock switching and monitor selection configuration */
+#define DEVCFG1_FCKSM_MASK (3 << DEVCFG1_FCKSM_SHIFT)
+# define DEVCFG1_FCKSM_BOTH (0 << DEVCFG1_FCKSM_SHIFT) /* Clock switching and FSCM are enabled */
+# define DEVCFG1_FCKSM_CSONLY (1 << DEVCFG1_FCKSM_SHIFT) /* Clock switching is enabled, FSCM is disabled */
+# define DEVCFG1_FCKSM_NONE (2 << DEVCFG1_FCKSM_SHIFT) /* Clock switching and FSCM are disabled */
+#define DEVCFG1_WDTPS_SHIFT (16) /* Bits 16-20: WDT postscaler select */
+#define DEVCFG1_WDTPS_MASK (31 << DEVCFG1_WDTPS_SHIFT)
+# define DEVCFG1_WDTPS_1 (0 << DEVCFG1_WDTPS_SHIFT) /* 1:1 */
+# define DEVCFG1_WDTPS_2 (1 << DEVCFG1_WDTPS_SHIFT) /* 1:2 */
+# define DEVCFG1_WDTPS_4 (2 << DEVCFG1_WDTPS_SHIFT) /* 1:4 */
+# define DEVCFG1_WDTPS_8 (3 << DEVCFG1_WDTPS_SHIFT) /* 1:8 */
+# define DEVCFG1_WDTPS_16 (4 << DEVCFG1_WDTPS_SHIFT) /* 1:16 */
+# define DEVCFG1_WDTPS_32 (5 << DEVCFG1_WDTPS_SHIFT) /* 1:32 */
+# define DEVCFG1_WDTPS_64 (6 << DEVCFG1_WDTPS_SHIFT) /* 1:64 */
+# define DEVCFG1_WDTPS_128 (7 << DEVCFG1_WDTPS_SHIFT) /* 1:128 */
+# define DEVCFG1_WDTPS_256 (8 << DEVCFG1_WDTPS_SHIFT) /* 1:256 */
+# define DEVCFG1_WDTPS_512 (9 << DEVCFG1_WDTPS_SHIFT) /* 1:512 */
+# define DEVCFG1_WDTPS_1024 (10 << DEVCFG1_WDTPS_SHIFT) /* 1:1024 */
+# define DEVCFG1_WDTPS_2048 (11 << DEVCFG1_WDTPS_SHIFT) /* 1:2048 */
+# define DEVCFG1_WDTPS_4096 (12 << DEVCFG1_WDTPS_SHIFT) /* 1:4096 */
+# define DEVCFG1_WDTPS_8192 (13 << DEVCFG1_WDTPS_SHIFT) /* 1:8192 */
+# define DEVCFG1_WDTPS_16384 (14 << DEVCFG1_WDTPS_SHIFT) /* 1:16384 */
+# define DEVCFG1_WDTPS_32768 (15 << DEVCFG1_WDTPS_SHIFT) /* 1:32768 */
+# define DEVCFG1_WDTPS_65536 (16 << DEVCFG1_WDTPS_SHIFT) /* 1:65536 */
+# define DEVCFG1_WDTPS_131072 (17 << DEVCFG1_WDTPS_SHIFT) /* 1:131072 */
+# define DEVCFG1_WDTPS_262144 (18 << DEVCFG1_WDTPS_SHIFT) /* 1:262144 */
+# define DEVCFG1_WDTPS_524288 (19 << DEVCFG1_WDTPS_SHIFT) /* 1:524288 */
+# define DEVCFG1_WDTPS_1048576 (20 << DEVCFG1_WDTPS_SHIFT) /* 1:1048576 */
+#define DEVCFG1_FWDTEN (1 << 23) /* Bit 23: WDT enable */
+
+/* Device configuration word 0 */
+
+
+#define DEVCFG0_DEBUG_SHIFT (0) /* Bits 0-1: xx */
+#define DEVCFG0_DEBUG_MASK (3 << DEVCFG0_DEBUG_SHIFT)
+#define DEVCFG0_ICESEL (1 << 3) /* Bit 3: xx */
+#define DEVCFG0_PWP12 (1 << 12) /* Bit 12: xx */
+#define DEVCFG0_PWP13 (1 << 13) /* Bit 13: xx */
+#define DEVCFG0_PWP14 (1 << 14) /* Bit 14: xx */
+#define DEVCFG0_PWP15 (1 << 15) /* Bit 15: xx */
+#define DEVCFG0_PWP16 (1 << 16) /* Bit 16: xx */
+#define DEVCFG0_PWP17 (1 << 17) /* Bit 17: xx */
+#define DEVCFG0_PWP18 (1 << 18) /* Bit 18: xx */
+#define DEVCFG0_PWP19 (1 << 19) /* Bit 19: xx */
+#define DEVCFG0_BWP (1 << 24) /* Bit 24: xx */
+#define DEVCFG0_CP (1 << 28) /* Bit 28: xx */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_DEVCFG_H */
diff --git a/arch/mips/src/pic32mx/pic32mx-memorymap.h b/arch/mips/src/pic32mx/pic32mx-memorymap.h
new file mode 100755
index 0000000000000000000000000000000000000000..544fc5da2cad9e82b1a2ab39d5e7295edd8d8dfe
--- /dev/null
+++ b/arch/mips/src/pic32mx/pic32mx-memorymap.h
@@ -0,0 +1,225 @@
+/****************************************************************************
+ * arch/mips/src/pic32mx/pic32mx-memorymap.h
+ *
+ * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_MEMORYMAP_H
+#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_MEMORYMAP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "mips32-memorymap.h"
+
+/****************************************************************************
+ * Pre-Processor Definitions
+ ****************************************************************************/
+/* Physical Memory Map ******************************************************/
+
+#define PIC32MX_DATAMEM_PBASE 0x00000000 /* Size depends on CHIP_DATAMEM_KB */
+#define PIC32MX_PROGFLASH_PBASE 0x1d000000 /* Size depends on CHIP_PROGFLASH_KB */
+#define PIC32MX_SFR_PBASE 0x1f800000 /* Special function registers */
+#define PIC32MX_BOOTFLASH_PBASE 0x1fc00000 /* Size depends on CHIP_BOOTFLASH_KB */
+#define PIC32MX_DEVCFG_PBASE 0x1fc02ff0 /* Device configuration registers */
+
+/* Virtual Memory Map *******************************************************/
+
+#define PIC32MX_DATAMEM_K0BASE (KSEG0_BASE + PIC32MX_DATAMEM_PBASE)
+#define PIC32MX_PROGFLASH_K0BASE (KSEG0_BASE + PIC32MX_PROGFLASH_PBASE)
+#define PIC32MX_BOOTFLASH_K0BASE (KSEG0_BASE + PIC32MX_BOOTFLASH_PBASE)
+#define PIC32MX_DEVCFG_K0BASE (KSEG0_BASE + PIC32MX_DEVCFG_PBASE)
+
+#define PIC32MX_DATAMEM_K1BASE (KSEG1_BASE + PIC32MX_DATAMEM_PBASE)
+#define PIC32MX_PROGFLASH_K1BASE (KSEG1_BASE + PIC32MX_PROGFLASH_PBASE)
+#define PIC32MX_SFR_K1BASE (KSEG1_BASE + PIC32MX_SFR_PBASE)
+#define PIC32MX_BOOTFLASH_K1BASE (KSEG1_BASE + PIC32MX_BOOTFLASH_PBASE)
+#define PIC32MX_DEVCFG_K1BASE (KSEG1_BASE + PIC32MX_DEVCFG_PBASE)
+
+/* Register Base Addresses **************************************************/
+
+/* Watchdog Register Base Address */
+
+#define PIC32MX_WDT_K1BASE (PIC32MX_SFR_K1BASE + 0x00000000)
+
+/* RTCC Register Base Address */
+
+#define PIC32MX_RTCC_K1BASE (PIC32MX_SFR_K1BASE + 0x00000200)
+
+/* Timer 1-5 Register Base Addresses */
+
+#define PIC32MX_TIMER1_K1BASE (PIC32MX_SFR_K1BASE + 0x00000600)
+#define PIC32MX_TIMER2_K1BASE (PIC32MX_SFR_K1BASE + 0x00000800)
+#define PIC32MX_TIMER3_K1BASE (PIC32MX_SFR_K1BASE + 0x00000a00)
+#define PIC32MX_TIMER4_K1BASE (PIC32MX_SFR_K1BASE + 0x00000c00)
+#define PIC32MX_TIMER5_K1BASE (PIC32MX_SFR_K1BASE + 0x00000e00)
+
+/* Input Capture 1-5 Register Base Addresses */
+
+#define PIC32MX_INCAP1_K1BASE (PIC32MX_SFR_K1BASE + 0x00002000)
+#define PIC32MX_INCAP2_K1BASE (PIC32MX_SFR_K1BASE + 0x00002200)
+#define PIC32MX_INCAP3_K1BASE (PIC32MX_SFR_K1BASE + 0x00002400)
+#define PIC32MX_INCAP4_K1BASE (PIC32MX_SFR_K1BASE + 0x00002600)
+#define PIC32MX_INCAP5_K1BASE (PIC32MX_SFR_K1BASE + 0x00002800)
+
+/* Output Compare 1-5 Register Base Addresses */
+
+#define PIC32MX_OUTCMP1_K1BASE (PIC32MX_SFR_K1BASE + 0x00003000)
+#define PIC32MX_OUTCMP2_K1BASE (PIC32MX_SFR_K1BASE + 0x00003200)
+#define PIC32MX_OUTCMP3_K1BASE (PIC32MX_SFR_K1BASE + 0x00003400)
+#define PIC32MX_OUTCMP4_K1BASE (PIC32MX_SFR_K1BASE + 0x00003600)
+#define PIC32MX_OUTCMP5_K1BASE (PIC32MX_SFR_K1BASE + 0x00003800)
+
+/* I2C 1-2 Register Base Addresses */
+
+#define PIC32MX_I2C1_K1BASE (PIC32MX_SFR_K1BASE + 0x00005000)
+#define PIC32MX_I2C2_K1BASE (PIC32MX_SFR_K1BASE + 0x00005200)
+
+/* SPI 1-2 Register Base Addresses */
+
+#define PIC32MX_SPI1_K1BASE (PIC32MX_SFR_K1BASE + 0x00005800)
+#define PIC32MX_SPI2_K1BASE (PIC32MX_SFR_K1BASE + 0x00005a00)
+
+/* UART 1-2 Register Base Addresses */
+
+#define PIC32MX_UART1_K1BASE (PIC32MX_SFR_K1BASE + 0x00006000)
+#define PIC32MX_UART2_K1BASE (PIC32MX_SFR_K1BASE + 0x00006200)
+
+/* Parallel Master Register Base Address */
+
+#define PCI32MX_PMSTR_K1BASE (PIC32MX_SFR_K1BASE + 0x00007000)
+
+/* ADC Register Base Addresses */
+
+#define PIC32MX_ADC_K1BASE (PIC32MX_SFR_K1BASE + 0x00009000)
+
+/* Comparator Voltage Reference Register Base Addresses */
+
+#define PIC32MX_VREF_K1BASE (PIC32MX_SFR_K1BASE + 0x00009800)
+
+/* Comparator Register Base Addresses */
+
+#define PIC32MX_COMP_K1BASE (PIC32MX_SFR_K1BASE + 0x0000a000)
+
+/* Oscillator Control Register Base Addresses */
+
+#define PIC32MX_OSC_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f000)
+
+/* Programming and Diagnostics Register Base Addresses */
+
+#define PIC32MX_SYSCON_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f200)
+
+/* FLASH Controller Register Base Addresses */
+
+#define PIC32MX_FLASH_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f400)
+
+/* Reset Control Register Base Address */
+
+#define PIC32MX_RCON_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f600)
+
+/* Interrupt Register Base Address */
+
+#define PIC32MX_INTCON_K1BASE (PIC32MX_SFR_K1BASE + 0x00081000)
+
+/* Bus Matrix Register Base Address */
+
+#define PIC32MX_BMX_K1BASE (PIC32MX_SFR_K1BASE + 0x00082000)
+
+/* DMA Register Base Address */
+
+#define PIC32MX_DMA_K1BASE (PIC32MX_SFR_K1BASE + 0x00083000)
+#define PIC32MX_DMACHAN_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00083060 + 0xc0*(n))
+#define PIC32MX_DMACHAN0_K1BASE (PIC32MX_SFR_K1BASE + 0x00083060)
+#define PIC32MX_DMACHAN1_K1BASE (PIC32MX_SFR_K1BASE + 0x00083120)
+#define PIC32MX_DMACHAN2_K1BASE (PIC32MX_SFR_K1BASE + 0x000831e0)
+#define PIC32MX_DMACHAN3_K1BASE (PIC32MX_SFR_K1BASE + 0x000832a0)
+
+/* Prefetch Register Base Address */
+
+#define PIC32MX_CHE_K1BASE (PIC32MX_SFR_K1BASE + 0x00084000)
+
+/* USB2 Register Base Addresses */
+
+#define PIC32MX_USB_K1BASE (PIC32MX_SFR_K1BASE + 0x00085000)
+
+/* Port Register Base Addresses */
+
+#define PIC32MX_PORTA 0
+#define PIC32MX_PORTB 1
+#define PIC32MX_PORTC 2
+#define PIC32MX_PORTD 3
+#define PIC32MX_PORTE 4
+#define PIC32MX_PORTF 5
+#define PIC32MX_PORTG 6
+#define PIC32MX_PORT_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00086000 + 0x20*(n))
+
+#define PIC32MX_PORTA_K1BASE (PIC32MX_SFR_K1BASE + 0x00086000)
+#define PIC32MX_PORTB_K1BASE (PIC32MX_SFR_K1BASE + 0x00086040)
+#define PIC32MX_PORTC_K1BASE (PIC32MX_SFR_K1BASE + 0x00086080)
+#define PIC32MX_PORTD_K1BASE (PIC32MX_SFR_K1BASE + 0x000860c0)
+#define PIC32MX_PORTE_K1BASE (PIC32MX_SFR_K1BASE + 0x00086100)
+#define PIC32MX_PORTF_K1BASE (PIC32MX_SFR_K1BASE + 0x00086140)
+#define PIC32MX_PORTG_K1BASE (PIC32MX_SFR_K1BASE + 0x00086180)
+
+#define PIC32MX_CNCON_K1BASE (PIC32MX_SFR_K1BASE + 0x000861c0)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_MEMORYMAP_H */
diff --git a/arch/mips/src/pic32mx/pic32mx-osc.h b/arch/mips/src/pic32mx/pic32mx-osc.h
new file mode 100755
index 0000000000000000000000000000000000000000..9142b19a2d0769bd1cc9f013c8cac4f7d3f9c9cc
--- /dev/null
+++ b/arch/mips/src/pic32mx/pic32mx-osc.h
@@ -0,0 +1,165 @@
+/****************************************************************************
+ * arch/mips/src/pic32mx/pic32mx-osc.h
+ *
+ * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_OSC_H
+#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_OSC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "pic32mx-memorymap.h"
+
+/****************************************************************************
+ * Pre-Processor Definitions
+ ****************************************************************************/
+/* Register Offsets *********************************************************/
+
+#define PIC32MX_OSCCON_OFFSET 0x0000 /* Oscillator control register offset */
+#define PIC32MX_OSCTUN_OFFSET 0x0010 /* FRC tuning register offset */
+
+/* Register Addresses *******************************************************/
+
+#define PIC32MX_OSCCON (PIC32MX_OSC_K1BASE+PIC32MX_OSCCON_OFFSET)
+#define PIC32MX_OSCTUN (PIC32MX_OSC_K1BASE+PIC32MX_OSCTUN_OFFSET)
+
+/* Register Bit-Field Definitions *******************************************/
+
+/* Oscillator control register offset */
+
+#define OSCCON_OSWEN (1 << 0) /* Bit 0: Oscillator switch enable */
+#define OSCCON_SOSCEN (1 << 1) /* Bit 1: 32.768kHz secondary oscillator enable */
+#define OSCCON_UFRCEN (1 << 2) /* Bit 2: USB FRC clock enable */
+#define OSCCON_CF (1 << 3) /* Bit 3: Clock fail detect */
+#define OSCCON_SLPEN (1 << 4) /* Bit 4: Sleep mode enable */
+#define OSCCON_SLOCK (1 << 5) /* Bit 5: PLL lock status */
+#define OSCCON_ULOCK (1 << 6) /* Bit 6: USB PLL lock status */
+#define OSCCON_CLKLOCK (1 << 7) /* Bit 7: Clock selection lock enable */
+#define OSCCON_NOSC_SHIFT (8) /* Bits 8-10: New oscillator selection */
+#define OSCCON_NOSC_MASK (7 << OSCCON_NOSC_SHIFT)
+# define OSCCON_NOSC_FRC (0 << OSCCON_NOSC_SHIFT) /* FRC oscillator */
+# define OSCCON_NOSC_FRCPLL (1 << OSCCON_NOSC_SHIFT) /* FRC w/PLL postscaler */
+# define OSCCON_NOSC_POSC (2 << OSCCON_NOSC_SHIFT) /* Primary oscillator */
+# define OSCCON_NOSC_POSCPLL (3 << OSCCON_NOSC_SHIFT) /* Primary oscillator with PLL */
+# define OSCCON_NOSC_SOSC (4 << OSCCON_NOSC_SHIFT) /* Secondary oscillator */
+# define OSCCON_NOSC_LPRC (5 << OSCCON_NOSC_SHIFT) /* Low power RC oscillator */
+# define OSCCON_NOSC_FRCDIV16 (6 << OSCCON_NOSC_SHIFT) /* FRC divided by 16 */
+# define OSCCON_NOSC_FRCDIV (7 << OSCCON_NOSC_SHIFT) /* FRC dived by FRCDIV */
+#define OSCCON_COSC_SHIFT (12) /* Bits 12-14: Current oscillator selection */
+#define OSCCON_COSC_MASK (7 << OSCCON_COSC_SHIFT)
+# define OSCCON_COSC_FRC (0 << OSCCON_COSC_SHIFT) /* FRC oscillator */
+# define OSCCON_COSC_FRCPLL (1 << OSCCON_COSC_SHIFT) /* FRC w/PLL postscaler */
+# define OSCCON_COSC_POSC (2 << OSCCON_COSC_SHIFT) /* Primary oscillator */
+# define OSCCON_COSC_POSCPLL (3 << OSCCON_COSC_SHIFT) /* Primary oscillator with PLL */
+# define OSCCON_COSC_SOSC (4 << OSCCON_COSC_SHIFT) /* Secondary oscillator */
+# define OSCCON_COSC_LPRC (5 << OSCCON_COSC_SHIFT) /* Low power RC oscillator */
+# define OSCCON_COSC_FRCDIV16 (6 << OSCCON_COSC_SHIFT) /* FRC divided by 16 */
+# define OSCCON_COSC_FRCDIV (7 << OSCCON_COSC_SHIFT) /* FRC dived by FRCDIV */
+#define OSCCON_PLLMULT_SHIFT (16) /* Bits 16-18: PLL multiplier */
+#define OSCCON_PLLMULT_MASK (7 << OSCCON_PLLMULT_SHIFT)
+# define OSCCON_PLLMULT_MUL15 (0 << OSCCON_PLLMULT_SHIFT)
+# define OSCCON_PLLMULT_MUL16 (1 << OSCCON_PLLMULT_SHIFT)
+# define OSCCON_PLLMULT_MUL17 (2 << OSCCON_PLLMULT_SHIFT)
+# define OSCCON_PLLMULT_MUL18 (3 << OSCCON_PLLMULT_SHIFT)
+# define OSCCON_PLLMULT_MUL19 (4 << OSCCON_PLLMULT_SHIFT)
+# define OSCCON_PLLMULT_MUL20 (5 << OSCCON_PLLMULT_SHIFT)
+# define OSCCON_PLLMULT_MUL21 (6 << OSCCON_PLLMULT_SHIFT)
+# define OSCCON_PLLMULT_MUL24 (7 << OSCCON_PLLMULT_SHIFT)
+#define OSCCON_PBDIV_SHIFT (19) /* Bits 19-20: PBVLK divisor */
+#define OSCCON_PBDIV_SMASK (3 << OSCCON_PBDIV_SHIFT)
+# define OSCCON_PBDIV_DIV1 (0 << OSCCON_PBDIV_SHIFT)
+# define OSCCON_PBDIV_DIV2 (1 << OSCCON_PBDIV_SHIFT)
+# define OSCCON_PBDIV_DIV4 (2 << OSCCON_PBDIV_SHIFT)
+# define OSCCON_PBDIV_DIV8 (3 << OSCCON_PBDIV_SHIFT)
+#define OSCCON_SOSCRDY (1 << 22) /* Bit 22: Secondary oscillator ready */
+#define OSCCON_FRCDIV_SHIFT (24) /* Bits 24-26: FRC oscillator divider */
+#define OSCCON_FRCDIV_MASK (7 << OSCCON_FRCDIV_SHIFT)
+# define OSCCON_FRCDIV_DIV1 (0 << OSCCON_FRCDIV_SHIFT)
+# define OSCCON_FRCDIV_DIV2 (1 << OSCCON_FRCDIV_SHIFT)
+# define OSCCON_FRCDIV_DIV4 (2 << OSCCON_FRCDIV_SHIFT)
+# define OSCCON_FRCDIV_DIV8 (3 << OSCCON_FRCDIV_SHIFT)
+# define OSCCON_FRCDIV_DIV16 (4 << OSCCON_FRCDIV_SHIFT)
+# define OSCCON_FRCDIV_DIV32 (5 << OSCCON_FRCDIV_SHIFT)
+# define OSCCON_FRCDIV_DIV64 (6 << OSCCON_FRCDIV_SHIFT)
+# define OSCCON_FRCDIV_DIV256 (7 << OSCCON_FRCDIV_SHIFT)
+#define OSCCON_PLL0DIV_SHIFT (27) /* Bits 27-29: Output divider for PLL */
+#define OSCCON_PLL0DIV_MASK (7 << OSCCON_PLL0DIV_SHIFT)
+# define OSCCON_PLL0DIV_DIV1 (0 << OSCCON_PLL0DIV_SHIFT)
+# define OSCCON_PLL0DIV_DIV2 (1 << OSCCON_PLL0DIV_SHIFT)
+# define OSCCON_PLL0DIV_DIV4 (2 << OSCCON_PLL0DIV_SHIFT)
+# define OSCCON_PLL0DIV_DIV8 (3 << OSCCON_PLL0DIV_SHIFT)
+# define OSCCON_PLL0DIV_DIV16 (4 << OSCCON_PLL0DIV_SHIFT)
+# define OSCCON_PLL0DIV_DIV32 (5 << OSCCON_PLL0DIV_SHIFT)
+# define OSCCON_PLL0DIV_DIV64 (6 << OSCCON_PLL0DIV_SHIFT)
+# define OSCCON_PLL0DIV_DIV256 (7 << OSCCON_PLL0DIV_SHIFT)
+
+/* FRC tuning register offset (6-bit, signed twos complement) */
+
+#define OSCTUN_SHIFT (0) /* Bits 0-5: FRC tuning bits */
+#define OSCTUN_MASK (0x3f << OSCTUN_SHIFT)
+# define OSCTUN_MIN (0x20 << OSCTUN_SHIFT)
+# define OSCTUN_CENTER (0x00 << OSCTUN_SHIFT)
+# define OSCTUN_MAX (0x1f << OSCTUN_SHIFT)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_OSC_H */