diff --git a/ChangeLog b/ChangeLog
index 56fda0aad30195147a598baca50ccedbcf9af590..c91093852f159c7c7a469d173f62919633ebc8ec 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -2153,4 +2153,6 @@
are not met
* configs/stm3210e-eval/src/up_lcd.c: Color corrections for SPFD5408B LCD
do not work with R61580 LCD.
+ * configs/pic32-starterkit: Beginning of a configuratin for the Microchip
+ PIC32 Ethernet Starter Kit.
diff --git a/arch/mips/src/pic32mx/Make.defs b/arch/mips/src/pic32mx/Make.defs
old mode 100755
new mode 100644
diff --git a/arch/mips/src/pic32mx/chip.h b/arch/mips/src/pic32mx/chip.h
old mode 100755
new mode 100644
index 0dac54c2ddf3546689cd22ad63b14ec3c3f27e19..e269fb68902c8ecbe487e41c2e583b869c9085d1
--- a/arch/mips/src/pic32mx/chip.h
+++ b/arch/mips/src/pic32mx/chip.h
@@ -1,489 +1,1386 @@
-/****************************************************************************
- * arch/mips/src/pic32mx/chip.h
- *
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ****************************************************************************/
-
-#ifndef __ARCH_MIPS_SRC_PIC32MX_CHIP_H
-#define __ARCH_MIPS_SRC_PIC32MX_CHIP_H
-
-/****************************************************************************
- * Included Files
- ****************************************************************************/
-
-#include <nuttx/config.h>
-
-/****************************************************************************
- * Pre-Processor Definitions
- ****************************************************************************/
-/* Configuration ************************************************************/
-
-#if defined(CONFIG_ARCH_CHIP_PIC32MX320F032H)
-# define CHIP_PIC32MX3 1
-# undef CHIP_PIC32MX4
-# define CHIP_NPINS 64 /* Package PT, MR */
-# define CHIP_MHZ 40
-# define CHIP_BOOTFLASH_KB 12
-# define CHIP_PROGFLASH_KB 32
-# define CHIP_DATAMEM_KB 8
-# define CHIP_NTIMERS 5
-# define CHIP_NIC 5
-# define CHIP_NOC 5
-# define CHIP_NDMACH 0
-# define CHIP_NUSBDMACHAN 0
-# define CHIP_CVR
-# undef CHIP_TRACE
-# define CHIP_NEUARTS 2
-# define CHIP_UARTFIFOD 4
-# define CHIP_NSPI 2
-# define CHIP_NI2C 2
-# define CHIP_NADC10 16
-# define CHIP_NCM 2
-# define CHIP_PMP
-# define CHIP_PSP
-# define CHIP_JTAH
-#elif defined(CONFIG_ARCH_CHIP_PIC32MX320F064H)
-# define CHIP_PIC32MX3 1
-# undef CHIP_PIC32MX4
-# define CHIP_NPINS 64 /* Package PT, MR */
-# define CHIP_MHZ 80
-# define CHIP_BOOTFLASH_KB 12
-# define CHIP_PROGFLASH_KB 64
-# define CHIP_DATAMEM_KB 16
-# define CHIP_NTIMERS 5
-# define CHIP_NIC 5
-# define CHIP_NOC 5
-# define CHIP_NDMACH 0
-# define CHIP_NUSBDMACHAN 0
-# define CHIP_CVR
-# undef CHIP_TRACE
-# define CHIP_NEUARTS 2
-# define CHIP_UARTFIFOD 4
-# define CHIP_NSPI 2
-# define CHIP_NI2C 2
-# define CHIP_NADC10 16
-# define CHIP_NCM 2
-# define CHIP_PMP
-# define CHIP_PSP
-# define CHIP_JTAH
-#elif defined(CONFIG_ARCH_CHIP_PIC32MX320F128H)
-# define CHIP_PIC32MX3 1
-# undef CHIP_PIC32MX4
-# define CHIP_NPINS 64 /* Package PT, MR */
-# define CHIP_MHZ 80
-# define CHIP_BOOTFLASH_KB 12
-# define CHIP_PROGFLASH_KB 128
-# define CHIP_DATAMEM_KB 16
-# define CHIP_NTIMERS 5
-# define CHIP_NIC 5
-# define CHIP_NOC 5
-# define CHIP_NDMACH 0
-# define CHIP_NUSBDMACHAN 0
-# define CHIP_CVR
-# undef CHIP_TRACE
-# define CHIP_NEUARTS 2
-# define CHIP_UARTFIFOD 4
-# define CHIP_NSPI 2
-# define CHIP_NI2C 2
-# define CHIP_NADC10 16
-# define CHIP_NCM 2
-# define CHIP_PMP
-# define CHIP_PSP
-# define CHIP_JTAH
-#elif defined(CONFIG_ARCH_CHIP_PIC32MX340F128H)
-# define CHIP_PIC32MX3 1
-# undef CHIP_PIC32MX4
-# define CHIP_NPINS 64 /* Package PT, MR */
-# define CHIP_MHZ 80
-# define CHIP_BOOTFLASH_KB 12
-# define CHIP_PROGFLASH_KB 128
-# define CHIP_DATAMEM_KB 32
-# define CHIP_NTIMERS 5
-# define CHIP_NIC 5
-# define CHIP_NOC 5
-# define CHIP_NDMACH 4
-# define CHIP_NUSBDMACHAN 0
-# define CHIP_CVR
-# undef CHIP_TRACE
-# define CHIP_NEUARTS 2
-# define CHIP_UARTFIFOD 4
-# define CHIP_NSPI 2
-# define CHIP_NI2C 2
-# define CHIP_NADC10 16
-# define CHIP_NCM 2
-# define CHIP_PMP
-# define CHIP_PSP
-# define CHIP_JTAH
-#elif defined(CONFIG_ARCH_CHIP_PIC32MX340F256H)
-# define CHIP_PIC32MX3 1
-# undef CHIP_PIC32MX4
-# define CHIP_NPINS 64 /* Package PT, MR */
-# define CHIP_MHZ 80
-# define CHIP_BOOTFLASH_KB 12
-# define CHIP_PROGFLASH_KB 256
-# define CHIP_DATAMEM_KB 32
-# define CHIP_NTIMERS 5
-# define CHIP_NIC 5
-# define CHIP_NOC 5
-# define CHIP_NDMACH 4
-# define CHIP_NUSBDMACHAN 0
-# define CHIP_CVR
-# undef CHIP_TRACE
-# define CHIP_NEUARTS 2
-# define CHIP_UARTFIFOD 4
-# define CHIP_NSPI 2
-# define CHIP_NI2C 2
-# define CHIP_NADC10 16
-# define CHIP_NCM 2
-# define CHIP_PMP
-# define CHIP_PSP
-# define CHIP_JTAH
-#elif defined(CONFIG_ARCH_CHIP_PIC32MX340F512H)
-# define CHIP_PIC32MX3 1
-# undef CHIP_PIC32MX4
-# define CHIP_NPINS 64 /* Package PT, MR */
-# define CHIP_MHZ 80
-# define CHIP_BOOTFLASH_KB 12
-# define CHIP_PROGFLASH_KB 512
-# define CHIP_DATAMEM_KB 32
-# define CHIP_NTIMERS 5
-# define CHIP_NIC 5
-# define CHIP_NOC 5
-# define CHIP_NDMACH 4
-# define CHIP_NUSBDMACHAN 0
-# define CHIP_CVR
-# undef CHIP_TRACE
-# define CHIP_NEUARTS 2
-# define CHIP_UARTFIFOD 4
-# define CHIP_NSPI 2
-# define CHIP_NI2C 2
-# define CHIP_NADC10 16
-# define CHIP_NCM 2
-# define CHIP_PMP
-# define CHIP_PSP
-# define CHIP_JTAH
-#elif defined(CONFIG_ARCH_CHIP_PIC32MX320F128L)
-# define CHIP_PIC32MX3 1
-# undef CHIP_PIC32MX4
-# define CHIP_NPINS 100 /* Package PT=100 BG=121 */
-# define CHIP_MHZ 80
-# define CHIP_BOOTFLASH_KB 12
-# define CHIP_PROGFLASH_KB 128
-# define CHIP_DATAMEM_KB 16
-# define CHIP_NTIMERS 5
-# define CHIP_NIC 5
-# define CHIP_NOC 5
-# define CHIP_NDMACH 0
-# define CHIP_NUSBDMACHAN 0
-# define CHIP_CVR
-# undef CHIP_TRACE
-# define CHIP_NEUARTS 2
-# define CHIP_UARTFIFOD 4
-# define CHIP_NSPI 2
-# define CHIP_NI2C 2
-# define CHIP_NADC10 16
-# define CHIP_NCM 2
-# define CHIP_PMP
-# define CHIP_PSP
-# define CHIP_JTAH
-#elif defined(CONFIG_ARCH_CHIP_PIC32MX340F128L)
-# undef CHIP_PIC32MX3
-# define CHIP_PIC32MX4 1
-# define CHIP_NPINS 100 /* Package PT=100 BG=121 */
-# define CHIP_MHZ 80
-# define CHIP_BOOTFLASH_KB 12
-# define CHIP_PROGFLASH_KB 128
-# define CHIP_DATAMEM_KB 32
-# define CHIP_NTIMERS 5
-# define CHIP_NIC 5
-# define CHIP_NOC 5
-# define CHIP_NDMACH 4
-# define CHIP_NUSBDMACHAN 0
-# define CHIP_CVR
-# undef CHIP_TRACE
-# define CHIP_NEUARTS 2
-# define CHIP_UARTFIFOD 4
-# define CHIP_NSPI 2
-# define CHIP_NI2C 2
-# define CHIP_NADC10 16
-# define CHIP_NCM 2
-# define CHIP_PMP
-# define CHIP_PSP
-# define CHIP_JTAH
-#elif defined(CONFIG_ARCH_CHIP_PIC32MX360F256L)
-# undef CHIP_PIC32MX3
-# define CHIP_PIC32MX4 1
-# define CHIP_NPINS 100 /* Package PT=100 BG=121 */
-# define CHIP_MHZ 80
-# define CHIP_BOOTFLASH_KB 12
-# define CHIP_PROGFLASH_KB 256
-# define CHIP_DATAMEM_KB 32
-# define CHIP_NTIMERS 5
-# define CHIP_NIC 5
-# define CHIP_NOC 5
-# define CHIP_NDMACH 4
-# define CHIP_NUSBDMACHAN 0
-# define CHIP_CVR
-# define CHIP_TRACE
-# define CHIP_NEUARTS 2
-# define CHIP_UARTFIFOD 4
-# define CHIP_NSPI 2
-# define CHIP_NI2C 2
-# define CHIP_NADC10 16
-# define CHIP_NCM 2
-# define CHIP_PMP
-# define CHIP_PSP
-# define CHIP_JTAH
-#elif defined(CONFIG_ARCH_CHIP_PIC32MX360F512L)
-# undef CHIP_PIC32MX3
-# define CHIP_PIC32MX4 1
-# define CHIP_NPINS 100 /* Package PT=100 BG=121 */
-# define CHIP_MHZ 80
-# define CHIP_BOOTFLASH_KB 12
-# define CHIP_PROGFLASH_KB 512
-# define CHIP_DATAMEM_KB 32
-# define CHIP_NTIMERS 5
-# define CHIP_NIC 5
-# define CHIP_NOC 5
-# define CHIP_NDMACH 4
-# define CHIP_NUSBDMACHAN 0
-# define CHIP_CVR
-# define CHIP_TRACE
-# define CHIP_NEUARTS 2
-# define CHIP_UARTFIFOD 4
-# define CHIP_NSPI 2
-# define CHIP_NI2C 2
-# define CHIP_NADC10 16
-# define CHIP_NCM 2
-# define CHIP_PMP
-# define CHIP_PSP
-# define CHIP_JTAH
-#elif defined(CONFIG_ARCH_CHIP_PIC32MX420F032H)
-# undef CHIP_PIC32MX3
-# define CHIP_PIC32MX4 1
-# define CHIP_NPINS 64 /* Package PT, MR */
-# define CHIP_MHZ 40
-# define CHIP_BOOTFLASH_KB 12
-# define CHIP_PROGFLASH_KB 32
-# define CHIP_DATAMEM_KB 8
-# define CHIP_NTIMERS 5
-# define CHIP_NIC 5
-# define CHIP_NOC 5
-# define CHIP_NDMACH 0
-# define CHIP_NUSBDMACHAN 2
-# define CHIP_CVR
-# undef CHIP_TRACE
-# define CHIP_NEUARTS 2
-# define CHIP_UARTFIFOD 4
-# define CHIP_NSPI 1
-# define CHIP_NI2C 2
-# define CHIP_NADC10 16
-# define CHIP_NCM 2
-# define CHIP_PMP
-# define CHIP_PSP
-# define CHIP_JTAH
-#elif defined(CONFIG_ARCH_CHIP_PIC32MX440F128H)
-# undef CHIP_PIC32MX3
-# define CHIP_PIC32MX4 1
-# define CHIP_NPINS 64 /* Package PT, MR */
-# define CHIP_MHZ 40
-# define CHIP_BOOTFLASH_KB 12
-# define CHIP_PROGFLASH_KB 128
-# define CHIP_DATAMEM_KB 32
-# define CHIP_NTIMERS 5
-# define CHIP_NIC 5
-# define CHIP_NOC 5
-# define CHIP_NDMACH 4
-# define CHIP_NUSBDMACHAN 2
-# define CHIP_CVR
-# undef CHIP_TRACE
-# define CHIP_NEUARTS 2
-# define CHIP_UARTFIFOD 4
-# define CHIP_NSPI 1
-# define CHIP_NI2C 2
-# define CHIP_NADC10 16
-# define CHIP_NCM 2
-# define CHIP_PMP
-# define CHIP_PSP
-# define CHIP_JTAH
-#elif defined(CONFIG_ARCH_CHIP_PIC32MX440F256H)
-# undef CHIP_PIC32MX3
-# define CHIP_PIC32MX4 1
-# define CHIP_NPINS 64 /* Package PT, MR */
-# define CHIP_MHZ 80
-# define CHIP_BOOTFLASH_KB 12
-# define CHIP_PROGFLASH_KB 256
-# define CHIP_DATAMEM_KB 32
-# define CHIP_NTIMERS 5
-# define CHIP_NIC 5
-# define CHIP_NOC 5
-# define CHIP_NDMACH 4
-# define CHIP_NUSBDMACHAN 2
-# define CHIP_CVR
-# undef CHIP_TRACE
-# define CHIP_NEUARTS 2
-# define CHIP_UARTFIFOD 4
-# define CHIP_NSPI 1
-# define CHIP_NI2C 2
-# define CHIP_NADC10 16
-# define CHIP_NCM 2
-# define CHIP_PMP
-# define CHIP_PSP
-# define CHIP_JTAH
-#elif defined(CONFIG_ARCH_CHIP_PIC32MX440F512H)
-# undef CHIP_PIC32MX3
-# define CHIP_PIC32MX4 1
-# define CHIP_NPINS 64 /* Package PT, MR */
-# define CHIP_MHZ 80
-# define CHIP_BOOTFLASH_KB 12
-# define CHIP_PROGFLASH_KB 512
-# define CHIP_DATAMEM_KB 32
-# define CHIP_NTIMERS 5
-# define CHIP_NIC 5
-# define CHIP_NOC 5
-# define CHIP_NDMACH 4
-# define CHIP_NUSBDMACHAN 2
-# define CHIP_CVR
-# undef CHIP_TRACE
-# define CHIP_NEUARTS 2
-# define CHIP_UARTFIFOD 4
-# define CHIP_NSPI 1
-# define CHIP_NI2C 2
-# define CHIP_NADC10 16
-# define CHIP_NCM 2
-# define CHIP_PMP
-# define CHIP_PSP
-# define CHIP_JTAH
-#elif defined(CONFIG_ARCH_CHIP_PIC32MX440F128L)
-# undef CHIP_PIC32MX3
-# define CHIP_PIC32MX4 1
-# define CHIP_NPINS 100 /* Package PT=100 BG=121 */
-# define CHIP_MHZ 80
-# define CHIP_BOOTFLASH_KB 12
-# define CHIP_PROGFLASH_KB 128
-# define CHIP_DATAMEM_KB 32
-# define CHIP_NTIMERS 5
-# define CHIP_NIC 5
-# define CHIP_NOC 5
-# define CHIP_NDMACH 4
-# define CHIP_NUSBDMACHAN 2
-# define CHIP_CVR
-# undef CHIP_TRACE
-# define CHIP_NEUARTS 2
-# define CHIP_UARTFIFOD 4
-# define CHIP_NSPI 2
-# define CHIP_NI2C 2
-# define CHIP_NADC10 16
-# define CHIP_NCM 2
-# define CHIP_PMP
-# define CHIP_PSP
-# define CHIP_JTAH
-#elif defined(CONFIG_ARCH_CHIP_PIC32MX460F256L)
-# undef CHIP_PIC32MX3
-# define CHIP_PIC32MX4 1
-# define CHIP_NPINS 100 /* Package PT=100 BG=121 */
-# define CHIP_MHZ 80
-# define CHIP_BOOTFLASH_KB 12
-# define CHIP_PROGFLASH_KB 256
-# define CHIP_DATAMEM_KB 32
-# define CHIP_NTIMERS 5
-# define CHIP_NIC 5
-# define CHIP_NOC 5
-# define CHIP_NDMACH 4
-# define CHIP_NUSBDMACHAN 2
-# define CHIP_CVR
-# define CHIP_TRACE
-# define CHIP_NEUARTS 2
-# define CHIP_UARTFIFOD 4
-# define CHIP_NSPI 2
-# define CHIP_NI2C 2
-# define CHIP_NADC10 16
-# define CHIP_NCM 2
-# define CHIP_PMP
-# define CHIP_PSP
-# define CHIP_JTAH
-#elif defined(CONFIG_ARCH_CHIP_PIC32MX460F512L)
-# undef CHIP_PIC32MX3
-# define CHIP_PIC32MX4 1
-# define CHIP_NPINS 100 /* Package PT=100 BG=121 */
-# define CHIP_MHZ 80
-# define CHIP_BOOTFLASH_KB 12
-# define CHIP_PROGFLASH_KB 512
-# define CHIP_DATAMEM_KB 32
-# define CHIP_NTIMERS 5
-# define CHIP_NIC 5
-# define CHIP_NOC 5
-# define CHIP_NDMACH 4
-# define CHIP_NUSBDMACHAN 2
-# define CHIP_CVR
-# define CHIP_TRACE
-# define CHIP_NEUARTS 2
-# define CHIP_UARTFIFOD 4
-# define CHIP_NSPI 2
-# define CHIP_NI2C 2
-# define CHIP_NADC10 16
-# define CHIP_NCM 2
-# define CHIP_PMP
-# define CHIP_PSP
-# define CHIP_JTAH
-#else
-# error "Unrecognized PIC32 device
-#endif
-
-/****************************************************************************
- * Public Types
- ****************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/****************************************************************************
- * Inline Functions
- ****************************************************************************/
-
-/****************************************************************************
- * Public Function Prototypes
- ****************************************************************************/
-
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C" {
-#else
-#define EXTERN extern
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_MIPS_SRC_PIC32MX_CHIP_H */
+/****************************************************************************
+ * arch/mips/src/pic32mx/chip.h
+ *
+ * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_MIPS_SRC_PIC32MX_CHIP_H
+#define __ARCH_MIPS_SRC_PIC32MX_CHIP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-Processor Definitions
+ ****************************************************************************/
+/* Configuration ************************************************************/
+
+#if defined(CONFIG_ARCH_CHIP_PIC32MX320F032H)
+# define CHIP_PIC32MX3 1
+# undef CHIP_PIC32MX4
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 64 /* Package PT, MR */
+# define CHIP_MHZ 40 /* 40MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 32 /* 32Kb program FLASH */
+# define CHIP_DATAMEM_KB 8 /* 8Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 0 /* No programmable DMA channels */
+# define CHIP_NUSBDMACHAN 0
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# undef CHIP_TRACE /* No trace capability */
+# define CHIP_NEUARTS 2 /* 2 UARTS */
+# define CHIP_UARTFIFOD 4
+# define CHIP_NSPI 2 /* 2 SPI interfaces */
+# define CHIP_NI2C 2 /* 2 I2C interfaces */
+# define CHIP_NCAN 0 /* No CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 0 /* No Ethernet */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX320F064H)
+# define CHIP_PIC32MX3 1
+# undef CHIP_PIC32MX4
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 64 /* Package PT, MR */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
+# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 0 /* No programmable DMA channels */
+# define CHIP_NUSBDMACHAN 0
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# undef CHIP_TRACE /* No trace capability */
+# define CHIP_NEUARTS 2 /* 2 UARTS */
+# define CHIP_UARTFIFOD 4
+# define CHIP_NSPI 2 /* 2 SPI interfaces */
+# define CHIP_NI2C 2 /* 2 I2C interfaces */
+# define CHIP_NCAN 0 /* No CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 0 /* No Ethernet */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX320F128H)
+# define CHIP_PIC32MX3 1
+# undef CHIP_PIC32MX4
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 64 /* Package PT, MR */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
+# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 0 /* No programmable DMA channels */
+# define CHIP_NUSBDMACHAN 0
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# undef CHIP_TRACE /* No trace capability */
+# define CHIP_NEUARTS 2 /* 2 UARTS */
+# define CHIP_UARTFIFOD 4
+# define CHIP_NSPI 2 /* 2 SPI interfaces */
+# define CHIP_NI2C 2 /* 2 I2C interfaces */
+# define CHIP_NCAN 0 /* No CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 0 /* No Ethernet */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX340F128H)
+# define CHIP_PIC32MX3 1
+# undef CHIP_PIC32MX4
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 64 /* Package PT, MR */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
+# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
+# define CHIP_NUSBDMACHAN 0
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# undef CHIP_TRACE /* No trace capability */
+# define CHIP_NEUARTS 2 /* 2 UARTS */
+# define CHIP_UARTFIFOD 4
+# define CHIP_NSPI 2 /* 2 SPI interfaces */
+# define CHIP_NI2C 2 /* 2 I2C interfaces */
+# define CHIP_NCAN 0 /* No CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 0 /* No Ethernet */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX340F256H)
+# define CHIP_PIC32MX3 1
+# undef CHIP_PIC32MX4
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 64 /* Package PT, MR */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */
+# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
+# define CHIP_NUSBDMACHAN 0
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# undef CHIP_TRACE /* No trace capability */
+# define CHIP_NEUARTS 2 /* 2 UARTS */
+# define CHIP_UARTFIFOD 4
+# define CHIP_NSPI 2 /* 2 SPI interfaces */
+# define CHIP_NI2C 2 /* 2 I2C interfaces */
+# define CHIP_NCAN 0 /* No CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 0 /* No Ethernet */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX340F512H)
+# define CHIP_PIC32MX3 1
+# undef CHIP_PIC32MX4
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 64 /* Package PT, MR */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
+# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
+# define CHIP_NUSBDMACHAN 0
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# undef CHIP_TRACE /* No trace capability */
+# define CHIP_NEUARTS 2 /* 2 UARTS */
+# define CHIP_UARTFIFOD 4
+# define CHIP_NSPI 2 /* 2 SPI interfaces */
+# define CHIP_NI2C 2 /* 2 I2C interfaces */
+# define CHIP_NCAN 0 /* No CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 0 /* No Ethernet */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX320F128L)
+# define CHIP_PIC32MX3 1
+# undef CHIP_PIC32MX4
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 100 /* Package PT=100 BG=121 */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
+# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 0 /* No programmable DMA channels */
+# define CHIP_NUSBDMACHAN 0
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# undef CHIP_TRACE /* No trace capability */
+# define CHIP_NEUARTS 2 /* 2 UARTS */
+# define CHIP_UARTFIFOD 4
+# define CHIP_NSPI 2 /* 2 SPI interfaces */
+# define CHIP_NI2C 2 /* 2 I2C interfaces */
+# define CHIP_NCAN 0 /* No CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 0 /* No Ethernet */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX340F128L)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4 1
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 100 /* Package PT=100 BG=121 */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
+# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
+# define CHIP_NUSBDMACHAN 0
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# undef CHIP_TRACE /* No trace capability */
+# define CHIP_NEUARTS 2 /* 2 UARTS */
+# define CHIP_UARTFIFOD 4
+# define CHIP_NSPI 2 /* 2 SPI interfaces */
+# define CHIP_NI2C 2 /* 2 I2C interfaces */
+# define CHIP_NCAN 0 /* No CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 0 /* No Ethernet */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX360F256L)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4 1
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 100 /* Package PT=100 BG=121 */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */
+# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
+# define CHIP_NUSBDMACHAN 0
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# define CHIP_TRACE 1 /* Have trace capability */
+# define CHIP_NEUARTS 2 /* 2 UARTS */
+# define CHIP_UARTFIFOD 4
+# define CHIP_NSPI 2 /* 2 SPI interfaces */
+# define CHIP_NI2C 2 /* 2 I2C interfaces */
+# define CHIP_NCAN 0 /* No CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 0 /* No Ethernet */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX360F512L)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4 1
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 100 /* Package PT=100 BG=121 */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
+# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
+# define CHIP_NUSBDMACHAN 0
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# define CHIP_TRACE 1 /* Have trace capability */
+# define CHIP_NEUARTS 2 /* 2 UARTS */
+# define CHIP_UARTFIFOD 4
+# define CHIP_NSPI 2 /* 2 SPI interfaces */
+# define CHIP_NI2C 2 /* 2 I2C interfaces */
+# define CHIP_NCAN 0 /* No CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 0 /* No Ethernet */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX420F032H)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4 1
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 64 /* Package PT, MR */
+# define CHIP_MHZ 40 /* 40MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 32 /* 32Kb program FLASH */
+# define CHIP_DATAMEM_KB 8 /* 8Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 0 /* No programmable DMA channels */
+# define CHIP_NUSBDMACHAN 2
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# undef CHIP_TRACE /* No trace capability */
+# define CHIP_NEUARTS 2 /* 2 UARTS */
+# define CHIP_UARTFIFOD 4
+# define CHIP_NSPI 1 /* 2 SPI interfaces */
+# define CHIP_NI2C 2 /* 2 I2C interfaces */
+# define CHIP_NCAN 0 /* No CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 0 /* No Ethernet */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX440F128H)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4 1
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 64 /* Package PT, MR */
+# define CHIP_MHZ 40 /* 40MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
+# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
+# define CHIP_NUSBDMACHAN 2
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# undef CHIP_TRACE /* No trace capability */
+# define CHIP_NEUARTS 2 /* 2 UARTS */
+# define CHIP_UARTFIFOD 4
+# define CHIP_NSPI 1 /* 2 SPI interfaces */
+# define CHIP_NI2C 2 /* 2 I2C interfaces */
+# define CHIP_NCAN 0 /* No CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 0 /* No Ethernet */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX440F256H)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4 1
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 64 /* Package PT, MR */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */
+# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
+# define CHIP_NUSBDMACHAN 2
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# undef CHIP_TRACE /* No trace capability */
+# define CHIP_NEUARTS 2 /* 2 UARTS */
+# define CHIP_UARTFIFOD 4
+# define CHIP_NSPI 1 /* 2 SPI interfaces */
+# define CHIP_NI2C 2 /* 2 I2C interfaces */
+# define CHIP_NCAN 0 /* No CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 0 /* No Ethernet */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX440F512H)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4 1
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 64 /* Package PT, MR */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
+# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
+# define CHIP_NUSBDMACHAN 2
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# undef CHIP_TRACE /* No trace capability */
+# define CHIP_NEUARTS 2 /* 2 UARTS */
+# define CHIP_UARTFIFOD 4
+# define CHIP_NSPI 1 /* 2 SPI interfaces */
+# define CHIP_NI2C 2 /* 2 I2C interfaces */
+# define CHIP_NCAN 0 /* No CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 0 /* No Ethernet */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX440F128L)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4 1
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 100 /* Package PT=100 BG=121 */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
+# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
+# define CHIP_NUSBDMACHAN 2
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# undef CHIP_TRACE /* No trace capability */
+# define CHIP_NEUARTS 2 /* 2 UARTS */
+# define CHIP_UARTFIFOD 4
+# define CHIP_NSPI 2 /* 2 SPI interfaces */
+# define CHIP_NI2C 2 /* 2 I2C interfaces */
+# define CHIP_NCAN 0 /* No CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 0 /* No Ethernet */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX460F256L)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4 1
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 100 /* Package PT=100 BG=121 */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */
+# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
+# define CHIP_NUSBDMACHAN 2
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# define CHIP_TRACE 1 /* Have trace capability */
+# define CHIP_NEUARTS 2 /* 2 UARTS */
+# define CHIP_UARTFIFOD 4
+# define CHIP_NSPI 2 /* 2 SPI interfaces */
+# define CHIP_NI2C 2 /* 2 I2C interfaces */
+# define CHIP_NCAN 0 /* No CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 0 /* No Ethernet */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX460F512L)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4 1
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 100 /* Package PT=100 BG=121 */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
+# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 4 /* 4 programmable DMA channels */
+# define CHIP_NUSBDMACHAN 2
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# define CHIP_TRACE 1 /* Have trace capability */
+# define CHIP_NEUARTS 2 /* 2 UARTS */
+# define CHIP_UARTFIFOD 4
+# define CHIP_NSPI 2 /* 2 SPI interfaces */
+# define CHIP_NI2C 2 /* 2 I2C interfaces */
+# define CHIP_NCAN 0 /* No CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 0 /* No Ethernet */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX534F064H)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4
+# undef CHIP_PIC32MX5 1
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 64 /* Package PT,MR */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
+# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */
+# define CHIP_NUSBDMACHAN tbd
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# undef CHIP_TRACE /* No trace capability */
+# define CHIP_NEUARTS 6 /* 6 UARTS */
+# define CHIP_UARTFIFOD tbd
+# define CHIP_NSPI 3 /* 3 SPI interfaces */
+# define CHIP_NI2C 4 /* 4 I2C interfaces */
+# define CHIP_NCAN 1 /* 1 CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 0 /* No Ethernet */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX564F064H)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4
+# undef CHIP_PIC32MX5 1
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 64 /* Package PT,MR */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
+# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */
+# define CHIP_NUSBDMACHAN tbd
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# undef CHIP_TRACE /* No trace capability */
+# define CHIP_NEUARTS 6 /* 6 UARTS */
+# define CHIP_UARTFIFOD tbd
+# define CHIP_NSPI 3 /* 3 SPI interfaces */
+# define CHIP_NI2C 4 /* 4 I2C interfaces */
+# define CHIP_NCAN 1 /* 1 CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 0 /* No Ethernet */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX564F128H)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4
+# undef CHIP_PIC32MX5 1
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 64 /* Package PT,MR */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
+# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */
+# define CHIP_NUSBDMACHAN tbd
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# undef CHIP_TRACE /* No trace capability */
+# define CHIP_NEUARTS 6 /* 6 UARTS */
+# define CHIP_UARTFIFOD tbd
+# define CHIP_NSPI 3 /* 3 SPI interfaces */
+# define CHIP_NI2C 4 /* 4 I2C interfaces */
+# define CHIP_NCAN 1 /* 1 CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 0 /* No Ethernet */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX575F256H)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4
+# undef CHIP_PIC32MX5 1
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 64 /* Package PT,MR */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */
+# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 8 /* 8 programmable DMA channels (4 dedicated) */
+# define CHIP_NUSBDMACHAN tbd
+# undef CHIP_CVR /* No comparator voltage reference */
+# undef CHIP_TRACE /* No trace capability */
+# define CHIP_NEUARTS 6 /* 6 UARTS */
+# define CHIP_UARTFIFOD tbd
+# define CHIP_NSPI 3 /* 3 SPI interfaces */
+# define CHIP_NI2C 4 /* 4 I2C interfaces */
+# define CHIP_NCAN 1 /* 1 CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 0 /* No Ethernet */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX575F512H)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4
+# undef CHIP_PIC32MX5 1
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 64 /* Package PT,MR */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
+# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 8 /* 8 programmable DMA channels (4 dedicated) */
+# define CHIP_NUSBDMACHAN tbd
+# undef CHIP_CVR /* No comparator voltage reference */
+# undef CHIP_TRACE /* No trace capability */
+# define CHIP_NEUARTS 6 /* 6 UARTS */
+# define CHIP_UARTFIFOD tbd
+# define CHIP_NSPI 3 /* 3 SPI interfaces */
+# define CHIP_NI2C 4 /* 4 I2C interfaces */
+# define CHIP_NCAN 1 /* 1 CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 0 /* No Ethernet */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX534F064L)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4
+# undef CHIP_PIC32MX5 1
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 100 /* Package PT,PF,BG */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
+# define CHIP_DATAMEM_KB 16 /* 16Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */
+# define CHIP_NUSBDMACHAN tbd
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# define CHIP_TRACE 1 /* Have trace capability */
+# define CHIP_NEUARTS 6 /* 6 UARTS */
+# define CHIP_UARTFIFOD tbd
+# define CHIP_NSPI 4 /* 4 SPI interfaces */
+# define CHIP_NI2C 5 /* 5 I2C interfaces */
+# define CHIP_NCAN 1 /* 1 CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 0 /* No Ethernet */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX564F064L)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4
+# undef CHIP_PIC32MX5 1
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 100 /* Package PT,PF,BG */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
+# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */
+# define CHIP_NUSBDMACHAN tbd
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# define CHIP_TRACE 1 /* Have trace capability */
+# define CHIP_NEUARTS 6 /* 6 UARTS */
+# define CHIP_UARTFIFOD tbd
+# define CHIP_NSPI 4 /* 4 SPI interfaces */
+# define CHIP_NI2C 5 /* 5 I2C interfaces */
+# define CHIP_NCAN 1 /* 1 CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 0 /* No Ethernet */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX564F128L)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4
+# undef CHIP_PIC32MX5 1
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 100 /* Package PT,PF,BG */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
+# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */
+# define CHIP_NUSBDMACHAN tbd
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# define CHIP_TRACE 1 /* Have trace capability */
+# define CHIP_NEUARTS 6 /* 6 UARTS */
+# define CHIP_UARTFIFOD tbd
+# define CHIP_NSPI 4 /* 4 SPI interfaces */
+# define CHIP_NI2C 5 /* 5 I2C interfaces */
+# define CHIP_NCAN 1 /* 1 CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 0 /* No Ethernet */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX575F256L)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4
+# undef CHIP_PIC32MX5 1
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 100 /* Package PT,PF,BG */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */
+# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 8 /* 8 programmable DMA channels (4 dedicated) */
+# define CHIP_NUSBDMACHAN tbd
+# undef CHIP_CVR /* No comparator voltage reference */
+# define CHIP_TRACE 1 /* Have trace capability */
+# define CHIP_NEUARTS 6 /* 6 UARTS */
+# define CHIP_UARTFIFOD tbd
+# define CHIP_NSPI 4 /* 4 SPI interfaces */
+# define CHIP_NI2C 5 /* 5 I2C interfaces */
+# define CHIP_NCAN 1 /* 1 CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 0 /* No Ethernet */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX575F512L)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4
+# undef CHIP_PIC32MX5 1
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 100 /* Package PT,PF,BG */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
+# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */ /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 8 /* 8 programmable DMA channels (4 dedicated) */
+# define CHIP_NUSBDMACHAN tbd
+# undef CHIP_CVR /* No comparator voltage reference */
+# define CHIP_TRACE 1 /* Have trace capability */
+# define CHIP_NEUARTS 6 /* 6 UARTS */
+# define CHIP_UARTFIFOD tbd
+# define CHIP_NSPI 4 /* 4 SPI interfaces */
+# define CHIP_NI2C 5 /* 5 I2C interfaces */
+# define CHIP_NCAN 1 /* 1 CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 0 /* No Ethernet */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX664F064H)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6 1
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 64 /* Package PT,MR */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
+# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */ /* 5 output compare */
+# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */
+# define CHIP_NUSBDMACHAN tbd
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# undef CHIP_TRACE /* No trace capability */
+# define CHIP_NEUARTS 6 /* 6 UARTS */
+# define CHIP_UARTFIFOD tbd
+# define CHIP_NSPI 3 /* 3 SPI interfaces */
+# define CHIP_NI2C 4 /* 4 I2C interfaces */
+# define CHIP_NCAN 0 /* No CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 1 /* 1 Ethernett interface */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX664F128H)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6 1
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 64 /* Package PT,MR */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
+# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */
+# define CHIP_NUSBDMACHAN tbd
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# undef CHIP_TRACE /* No trace capability */
+# define CHIP_NEUARTS 6 /* 6 UARTS */
+# define CHIP_UARTFIFOD tbd
+# define CHIP_NSPI 3 /* 3 SPI interfaces */
+# define CHIP_NI2C 4 /* 4 I2C interfaces */
+# define CHIP_NCAN 0 /* No CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 1 /* 1 Ethernett interface */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX675F256H)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6 1
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 64 /* Package PT,MR */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */
+# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 8 /* 8 programmable DMA channels (4 dedicated) */
+# define CHIP_NUSBDMACHAN tbd
+# undef CHIP_CVR /* No comparator voltage reference */
+# undef CHIP_TRACE /* No trace capability */
+# define CHIP_NEUARTS 6 /* 6 UARTS */
+# define CHIP_UARTFIFOD tbd
+# define CHIP_NSPI 3 /* 3 SPI interfaces */
+# define CHIP_NI2C 4 /* 4 I2C interfaces */
+# define CHIP_NCAN 0 /* No CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 1 /* 1 Ethernett interface */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX675F512H)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6 1
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 64 /* Package PT,MR */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
+# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 8 /* 8 programmable DMA channels (4 dedicated) */
+# define CHIP_NUSBDMACHAN tbd
+# undef CHIP_CVR /* No comparator voltage reference */
+# undef CHIP_TRACE /* No trace capability */
+# define CHIP_NEUARTS 6 /* 6 UARTS */
+# define CHIP_UARTFIFOD tbd
+# define CHIP_NSPI 3 /* 3 SPI interfaces */
+# define CHIP_NI2C 4 /* 4 I2C interfaces */
+# define CHIP_NCAN 0 /* No CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 1 /* 1 Ethernett interface */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX695F512H)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6 1
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 64 /* Package PT,MR */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
+# define CHIP_DATAMEM_KB 128 /* 128Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 8 /* 8 programmable DMA channels (4 dedicated) */
+# define CHIP_NUSBDMACHAN tbd
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# undef CHIP_TRACE /* No trace capability */
+# define CHIP_NEUARTS 6 /* 6 UARTS */
+# define CHIP_UARTFIFOD tbd
+# define CHIP_NSPI 3 /* 3 SPI interfaces */
+# define CHIP_NI2C 4 /* 4 I2C interfaces */
+# define CHIP_NCAN 0 /* No CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 1 /* 1 Ethernett interface */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX664F064L)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6 1
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 100 /* Package PT,PF,BG */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 64 /* 64Kb program FLASH */
+# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */
+# define CHIP_NUSBDMACHAN tbd
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# define CHIP_TRACE 1 /* Have trace capability */
+# define CHIP_NEUARTS 6 /* 6 UARTS */
+# define CHIP_UARTFIFOD tbd
+# define CHIP_NSPI 4 /* 4 SPI interfaces */
+# define CHIP_NI2C 5 /* 5 I2C interfaces */
+# define CHIP_NCAN 0 /* No CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 1 /* 1 Ethernett interface */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX664F128L)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6 1
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 100 /* Package PT,PF,BG */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
+# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 4 /* 4 programmable DMA channels (4 dedicated) */
+# define CHIP_NUSBDMACHAN tbd
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# define CHIP_TRACE 1 /* Have trace capability */
+# define CHIP_NEUARTS 6 /* 6 UARTS */
+# define CHIP_UARTFIFOD tbd
+# define CHIP_NSPI 4 /* 4 SPI interfaces */
+# define CHIP_NI2C 5 /* 5 I2C interfaces */
+# define CHIP_NCAN 0 /* No CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 1 /* 1 Ethernett interface */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX675F256L)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6 1
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 100 /* Package PT,PF,BG */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */
+# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 8 /* 8 programmable DMA channels (4 dedicated) */
+# define CHIP_NUSBDMACHAN tbd
+# undef CHIP_CVR /* No comparator voltage reference */
+# define CHIP_TRACE 1 /* Have trace capability */
+# define CHIP_NEUARTS 6 /* 6 UARTS */
+# define CHIP_UARTFIFOD tbd
+# define CHIP_NSPI 4 /* 4 SPI interfaces */
+# define CHIP_NI2C 5 /* 5 I2C interfaces */
+# define CHIP_NCAN 0 /* No CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 1 /* 1 Ethernett interface */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX675F512L)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6 1
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 100 /* Package PT,PF,BG */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
+# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 8 /* 8 programmable DMA channels (4 dedicated) */
+# define CHIP_NUSBDMACHAN tbd
+# undef CHIP_CVR /* No comparator voltage reference */
+# define CHIP_TRACE 1 /* Have trace capability */
+# define CHIP_NEUARTS 6 /* 6 UARTS */
+# define CHIP_UARTFIFOD tbd
+# define CHIP_NSPI 4 /* 4 SPI interfaces */
+# define CHIP_NI2C 5 /* 5 I2C interfaces */
+# define CHIP_NCAN 0 /* No CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 1 /* 1 Ethernett interface */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX695F512L)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6 1
+# undef CHIP_PIC32MX7
+# define CHIP_NPINS 100 /* Package PT,PF,BG */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
+# define CHIP_DATAMEM_KB 128 /* 128Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 8 /* xx programmable DMA channels (4 dedicated) */
+# define CHIP_NUSBDMACHAN tbd
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# define CHIP_TRACE 1 /* Have trace capability */
+# define CHIP_NEUARTS 6 /* 6 UARTS */
+# define CHIP_UARTFIFOD tbd
+# define CHIP_NSPI 4 /* 4 SPI interfaces */
+# define CHIP_NI2C 5 /* 5 I2C interfaces */
+# define CHIP_NCAN 0 /* No CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 1 /* 1 Ethernett interface */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX764F128H)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7 1
+# define CHIP_NPINS 64 /* Package PT,MR */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
+# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 4 /* 4 programmable DMA channels (6 dedicated) */
+# define CHIP_NUSBDMACHAN tbd
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# undef CHIP_TRACE /* No trace capability */
+# define CHIP_NEUARTS 6 /* 6 UARTS */
+# define CHIP_UARTFIFOD tbd
+# define CHIP_NSPI 3 /* 3 SPI interfaces */
+# define CHIP_NI2C 4 /* 4 I2C interfaces */
+# define CHIP_NCAN 1 /* 1 CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 1 /* 1 Ethernett interface */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX775F256H)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7 1
+# define CHIP_NPINS 64 /* Package PT,MR */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */
+# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 8 /* 8 programmable DMA channels (8 dedicated) */
+# define CHIP_NUSBDMACHAN tbd
+# undef CHIP_CVR /* No comparator voltage reference */
+# undef CHIP_TRACE /* No trace capability */
+# define CHIP_NEUARTS 6 /* 6 UARTS */
+# define CHIP_UARTFIFOD tbd
+# define CHIP_NSPI 3 /* 3 SPI interfaces */
+# define CHIP_NI2C 4 /* 4 I2C interfaces */
+# define CHIP_NCAN 2 /* 2 CAN interfaces */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 1 /* 1 Ethernet interface */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX775F512H)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7 1
+# define CHIP_NPINS 64 /* Package PT,MR */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
+# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 8 /* 8 programmable DMA channels (8 dedicated) */
+# define CHIP_NUSBDMACHAN tbd
+# undef CHIP_CVR /* No comparator voltage reference */
+# undef CHIP_TRACE /* No trace capability */
+# define CHIP_NEUARTS 6 /* 6 UARTS */
+# define CHIP_UARTFIFOD tbd
+# define CHIP_NSPI 3 /* 3 SPI interfaces */
+# define CHIP_NI2C 4 /* 4 I2C interfaces */
+# define CHIP_NCAN 2 /* 2 CAN interfaces */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 1 /* 1 Ethernet interface */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX795F512H)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7 1
+# define CHIP_NPINS 64 /* Package PT,MR */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
+# define CHIP_DATAMEM_KB 128 /* 128Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 8 /* 8 programmable DMA channels (8 dedicated) */
+# define CHIP_NUSBDMACHAN tbd
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# undef CHIP_TRACE /* No trace capability */
+# define CHIP_NEUARTS 6 /* 6 UARTS */
+# define CHIP_UARTFIFOD tbd
+# define CHIP_NSPI 3 /* 3 SPI interfaces */
+# define CHIP_NI2C 4 /* 4 I2C interfaces */
+# define CHIP_NCAN 2 /* 2 CAN interfaces */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 1 /* 1 Ethernet interface */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX764F128L)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7 1
+# define CHIP_NPINS 100 /* Package PT,PF,BG */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 128 /* 128Kb program FLASH */
+# define CHIP_DATAMEM_KB 32 /* 32Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 4 /* 4 programmable DMA channels (6 dedicated) */
+# define CHIP_NUSBDMACHAN tbd
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# define CHIP_TRACE 1 /* Have trace capability */
+# define CHIP_NEUARTS 6 /* 6 UARTS */
+# define CHIP_UARTFIFOD tbd
+# define CHIP_NSPI 4 /* 4 SPI interfaces */
+# define CHIP_NI2C 5 /* 5 I2C interfaces */
+# define CHIP_NCAN 1 /* 1 CAN interface */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 1 /* 1 Ethernet interface */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX775F256L)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7 1
+# define CHIP_NPINS 100 /* Package PT,PF,BG */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 256 /* 256Kb program FLASH */
+# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 8 /* 8 programmable DMA channels (8 dedicated) */
+# define CHIP_NUSBDMACHAN tbd
+# undef CHIP_CVR /* No comparator voltage reference */
+# define CHIP_TRACE 1 /* Have trace capability */
+# define CHIP_NEUARTS 6 /* 6 UARTS */
+# define CHIP_UARTFIFOD tbd
+# define CHIP_NSPI 4 /* 4 SPI interfaces */
+# define CHIP_NI2C 5 /* 5 I2C interfaces */
+# define CHIP_NCAN 2 /* 2 CAN interfaces */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 1 /* 1 Ethernet interface */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX775F512L)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7 1
+# define CHIP_NPINS 100 /* Package PT,PF,BG */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
+# define CHIP_DATAMEM_KB 64 /* 64Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 8 /* 8 programmable DMA channels (8 dedicated) */
+# define CHIP_NUSBDMACHAN tbd
+# undef CHIP_CVR /* No comparator voltage reference */
+# define CHIP_TRACE 1 /* Have trace capability */
+# define CHIP_NEUARTS 6 /* 6 UARTS */
+# define CHIP_UARTFIFOD tbd
+# define CHIP_NSPI 4 /* 4 SPI interfaces */
+# define CHIP_NI2C 5 /* 5 I2C interfaces */
+# define CHIP_NCAN 2 /* 2 CAN interfaces */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 1 /* 1 Ethernet interface */
+# define CHIP_JTAG
+#elif defined(CONFIG_ARCH_CHIP_PIC32MX795F512L)
+# undef CHIP_PIC32MX3
+# define CHIP_PIC32MX4
+# undef CHIP_PIC32MX5
+# undef CHIP_PIC32MX6
+# undef CHIP_PIC32MX7 1
+# define CHIP_NPINS 100 /* Package PT,PF,BG */
+# define CHIP_MHZ 80 /* 80MHz maximum frequency */
+# define CHIP_BOOTFLASH_KB 12 /* 12Kb boot FLASH */
+# define CHIP_PROGFLASH_KB 512 /* 512Kb program FLASH */
+# define CHIP_DATAMEM_KB 128 /* 128Kb data memory */
+# define CHIP_NTIMERS 5 /* 5 timers */
+# define CHIP_NIC 5 /* 5 input capture */
+# define CHIP_NOC 5 /* 5 output compare */
+# define CHIP_NDMACH 8 /* 8 programmable DMA channels (8 dedicated) */
+# define CHIP_NUSBDMACHAN tbd
+# define CHIP_CVR 1 /* Have comparator voltage reference */
+# define CHIP_TRACE 1 /* Have trace capability */
+# define CHIP_NEUARTS 6 /* 6 UARTS */
+# define CHIP_UARTFIFOD tbd
+# define CHIP_NSPI 4 /* 4 SPI interfaces */
+# define CHIP_NI2C 5 /* 5 I2C interfaces */
+# define CHIP_NCAN 2 /* 2 CAN interfaces */
+# define CHIP_NADC10 16 /* 16 10-bit ADC channels */
+# define CHIP_NCM 2 /* 2 Comparators */
+# define CHIP_PMP 1 /* Have parallel master port */
+# define CHIP_PSP 1 /* Have parallel slave port */
+# define CHIP_NETHERNET 1 /* 1 Ethernet interface */
+# define CHIP_JTAG
+#else
+# error "Unrecognized PIC32 device
+#endif
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_MIPS_SRC_PIC32MX_CHIP_H */
diff --git a/arch/mips/src/pic32mx/excptmacros.h b/arch/mips/src/pic32mx/excptmacros.h
old mode 100755
new mode 100644
diff --git a/arch/mips/src/pic32mx/pic32mx-adc.h b/arch/mips/src/pic32mx/pic32mx-adc.h
old mode 100755
new mode 100644
diff --git a/arch/mips/src/pic32mx/pic32mx-bmx.h b/arch/mips/src/pic32mx/pic32mx-bmx.h
old mode 100755
new mode 100644
diff --git a/arch/mips/src/pic32mx/pic32mx-che.h b/arch/mips/src/pic32mx/pic32mx-che.h
old mode 100755
new mode 100644
diff --git a/arch/mips/src/pic32mx/pic32mx-cm.h b/arch/mips/src/pic32mx/pic32mx-cm.h
old mode 100755
new mode 100644
diff --git a/arch/mips/src/pic32mx/pic32mx-config.h b/arch/mips/src/pic32mx/pic32mx-config.h
old mode 100755
new mode 100644
diff --git a/arch/mips/src/pic32mx/pic32mx-cvr.h b/arch/mips/src/pic32mx/pic32mx-cvr.h
old mode 100755
new mode 100644
diff --git a/arch/mips/src/pic32mx/pic32mx-ddp.h b/arch/mips/src/pic32mx/pic32mx-ddp.h
old mode 100755
new mode 100644
diff --git a/arch/mips/src/pic32mx/pic32mx-devcfg.h b/arch/mips/src/pic32mx/pic32mx-devcfg.h
old mode 100755
new mode 100644
diff --git a/arch/mips/src/pic32mx/pic32mx-dma.h b/arch/mips/src/pic32mx/pic32mx-dma.h
old mode 100755
new mode 100644
diff --git a/arch/mips/src/pic32mx/pic32mx-flash.h b/arch/mips/src/pic32mx/pic32mx-flash.h
old mode 100755
new mode 100644
diff --git a/arch/mips/src/pic32mx/pic32mx-i2c.h b/arch/mips/src/pic32mx/pic32mx-i2c.h
old mode 100755
new mode 100644
diff --git a/arch/mips/src/pic32mx/pic32mx-ic.h b/arch/mips/src/pic32mx/pic32mx-ic.h
old mode 100755
new mode 100644
diff --git a/arch/mips/src/pic32mx/pic32mx-int.h b/arch/mips/src/pic32mx/pic32mx-int.h
old mode 100755
new mode 100644
diff --git a/arch/mips/src/pic32mx/pic32mx-internal.h b/arch/mips/src/pic32mx/pic32mx-internal.h
old mode 100755
new mode 100644
diff --git a/arch/mips/src/pic32mx/pic32mx-ioport.h b/arch/mips/src/pic32mx/pic32mx-ioport.h
old mode 100755
new mode 100644
diff --git a/arch/mips/src/pic32mx/pic32mx-irq.c b/arch/mips/src/pic32mx/pic32mx-irq.c
old mode 100755
new mode 100644
diff --git a/arch/mips/src/pic32mx/pic32mx-memorymap.h b/arch/mips/src/pic32mx/pic32mx-memorymap.h
old mode 100755
new mode 100644
index e883dcef6d72ee1e4d86f3a91f712f6795bab4ee..c6bb71ffbbf74672d6cc51d74fae6947643076f2
--- a/arch/mips/src/pic32mx/pic32mx-memorymap.h
+++ b/arch/mips/src/pic32mx/pic32mx-memorymap.h
@@ -1,239 +1,247 @@
-/************************************************************************************
- * arch/mips/src/pic32mx/pic32mx-memorymap.h
- *
- * Copyright (C) 2011 Gregory Nutt. All rights reserved.
- * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in
- * the documentation and/or other materials provided with the
- * distribution.
- * 3. Neither the name NuttX nor the names of its contributors may be
- * used to endorse or promote products derived from this software
- * without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- ****
- // *********************************************************************************/
-
-#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_MEMORYMAP_H
-#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_MEMORYMAP_H
-
-/************************************************************************************
- * Included Files
- ************************************************************************************/
-
-#include <nuttx/config.h>
-
-#include "chip.h"
-#include "mips32-memorymap.h"
-
-/************************************************************************************
- * Pre-Processor Definitions
- ************************************************************************************/
-/* This memory may be valid for other chips as well, but I don't know that */
-
-#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4)
-
-/* Physical Memory Map **************************************************************/
-
-# define PIC32MX_DATAMEM_PBASE 0x00000000 /* Size depends on CHIP_DATAMEM_KB */
-# define PIC32MX_PROGFLASH_PBASE 0x1d000000 /* Size depends on CHIP_PROGFLASH_KB */
-# define PIC32MX_SFR_PBASE 0x1f800000 /* Special function registers */
-# define PIC32MX_BOOTFLASH_PBASE 0x1fc00000 /* Size depends on CHIP_BOOTFLASH_KB */
-# define PIC32MX_DEVCFG_PBASE 0x1fc02ff0 /* Device configuration registers */
-
-/* Virtual Memory Map ***************************************************************/
-
-# define PIC32MX_DATAMEM_K0BASE (KSEG0_BASE + PIC32MX_DATAMEM_PBASE)
-# define PIC32MX_PROGFLASH_K0BASE (KSEG0_BASE + PIC32MX_PROGFLASH_PBASE)
-# define PIC32MX_BOOTFLASH_K0BASE (KSEG0_BASE + PIC32MX_BOOTFLASH_PBASE)
-# define PIC32MX_DEVCFG_K0BASE (KSEG0_BASE + PIC32MX_DEVCFG_PBASE)
-
-# define PIC32MX_DATAMEM_K1BASE (KSEG1_BASE + PIC32MX_DATAMEM_PBASE)
-# define PIC32MX_PROGFLASH_K1BASE (KSEG1_BASE + PIC32MX_PROGFLASH_PBASE)
-# define PIC32MX_SFR_K1BASE (KSEG1_BASE + PIC32MX_SFR_PBASE)
-# define PIC32MX_BOOTFLASH_K1BASE (KSEG1_BASE + PIC32MX_BOOTFLASH_PBASE)
-# define PIC32MX_DEVCFG_K1BASE (KSEG1_BASE + PIC32MX_DEVCFG_PBASE)
-
-/* Register Base Addresses **********************************************************/
-
-/* Watchdog Register Base Address */
-
-# define PIC32MX_WDT_K1BASE (PIC32MX_SFR_K1BASE + 0x00000000)
-
-/* RTCC Register Base Address */
-
-# define PIC32MX_RTCC_K1BASE (PIC32MX_SFR_K1BASE + 0x00000200)
-
-/* Timer 1-5 Register Base Addresses */
-
-# define PIC32MX_TIMER_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00000600 + 0x200*(n-1))
-# define PIC32MX_TIMER1_K1BASE (PIC32MX_SFR_K1BASE + 0x00000600)
-# define PIC32MX_TIMER2_K1BASE (PIC32MX_SFR_K1BASE + 0x00000800)
-# define PIC32MX_TIMER3_K1BASE (PIC32MX_SFR_K1BASE + 0x00000a00)
-# define PIC32MX_TIMER4_K1BASE (PIC32MX_SFR_K1BASE + 0x00000c00)
-# define PIC32MX_TIMER5_K1BASE (PIC32MX_SFR_K1BASE + 0x00000e00)
-
-/* Input Capture 1-5 Register Base Addresses */
-
-# define PIC32MX_IC_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00002000 + 0x200*(n-1))
-# define PIC32MX_IC1_K1BASE (PIC32MX_SFR_K1BASE + 0x00002000)
-# define PIC32MX_IC2_K1BASE (PIC32MX_SFR_K1BASE + 0x00002200)
-# define PIC32MX_IC3_K1BASE (PIC32MX_SFR_K1BASE + 0x00002400)
-# define PIC32MX_IC4_K1BASE (PIC32MX_SFR_K1BASE + 0x00002600)
-# define PIC32MX_IC5_K1BASE (PIC32MX_SFR_K1BASE + 0x00002800)
-
-/* Output Compare 1-5 Register Base Addresses */
-
-# define PIC32MX_OC_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00003000 + 0x200*(n-1))
-# define PIC32MX_OC1_K1BASE (PIC32MX_SFR_K1BASE + 0x00003000)
-# define PIC32MX_OC2_K1BASE (PIC32MX_SFR_K1BASE + 0x00003200)
-# define PIC32MX_OC3_K1BASE (PIC32MX_SFR_K1BASE + 0x00003400)
-# define PIC32MX_OC4_K1BASE (PIC32MX_SFR_K1BASE + 0x00003600)
-# define PIC32MX_OC5_K1BASE (PIC32MX_SFR_K1BASE + 0x00003800)
-
-/* I2C 1-2 Register Base Addresses */
-
-# define PIC32MX_I2C1_K1BASE (PIC32MX_SFR_K1BASE + 0x00005000)
-# define PIC32MX_I2C2_K1BASE (PIC32MX_SFR_K1BASE + 0x00005200)
-
-/* SPI 1-2 Register Base Addresses */
-
-# define PIC32MX_SPI1_K1BASE (PIC32MX_SFR_K1BASE + 0x00005800)
-# define PIC32MX_SPI2_K1BASE (PIC32MX_SFR_K1BASE + 0x00005a00)
-
-/* UART 1-2 Register Base Addresses */
-
-# define PIC32MX_UART1_K1BASE (PIC32MX_SFR_K1BASE + 0x00006000)
-# define PIC32MX_UART2_K1BASE (PIC32MX_SFR_K1BASE + 0x00006200)
-
-/* Parallel Master Register Base Address */
-
-# define PIC32MX_PMP_K1BASE (PIC32MX_SFR_K1BASE + 0x00007000)
-
-/* ADC Register Base Addresses */
-
-# define PIC32MX_ADC_K1BASE (PIC32MX_SFR_K1BASE + 0x00009000)
-
-/* Comparator Voltage Reference Register Base Addresses */
-
-# define PIC32MX_CVR_K1BASE (PIC32MX_SFR_K1BASE + 0x00009800)
-
-/* Comparator Register Base Addresses */
-
-# define PIC32MX_CM_K1BASE (PIC32MX_SFR_K1BASE + 0x0000a000)
-# define PIC32MX_CM1_K1BASE (PIC32MX_SFR_K1BASE + 0x0000a000)
-# define PIC32MX_CM2_K1BASE (PIC32MX_SFR_K1BASE + 0x0000a010)
-
-/* Oscillator Control Register Base Addresses */
-
-# define PIC32MX_OSC_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f000)
-
-/* Programming and Diagnostics Register Base Addresses */
-
-# define PIC32MX_DDP_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f200)
-
-/* FLASH Controller Register Base Addresses */
-
-# define PIC32MX_FLASH_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f400)
-
-/* Reset Control Register Base Address */
-
-# define PIC32MX_RESET_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f600)
-
-/* Interrupt Register Base Address */
-
-# define PIC32MX_INT_K1BASE (PIC32MX_SFR_K1BASE + 0x00081000)
-
-/* Bus Matrix Register Base Address */
-
-# define PIC32MX_BMX_K1BASE (PIC32MX_SFR_K1BASE + 0x00082000)
-
-/* DMA Register Base Address */
-
-# define PIC32MX_DMA_K1BASE (PIC32MX_SFR_K1BASE + 0x00083000)
-# define PIC32MX_DMACH_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00083060 + 0xc0*(n))
-# define PIC32MX_DMACH0_K1BASE (PIC32MX_SFR_K1BASE + 0x00083060)
-# define PIC32MX_DMACH1_K1BASE (PIC32MX_SFR_K1BASE + 0x00083120)
-# define PIC32MX_DMACH2_K1BASE (PIC32MX_SFR_K1BASE + 0x000831e0)
-# define PIC32MX_DMACH3_K1BASE (PIC32MX_SFR_K1BASE + 0x000832a0)
-
-/* Prefetch Cache Register Base Address */
-
-# define PIC32MX_CHE_K1BASE (PIC32MX_SFR_K1BASE + 0x00084000)
-
-/* USB2 Register Base Addresses */
-
-# define PIC32MX_USB_K1BASE (PIC32MX_SFR_K1BASE + 0x00085000)
-
-/* Port Register Base Addresses */
-
-# define PIC32MX_IOPORTA 0
-# define PIC32MX_IOPORTB 1
-# define PIC32MX_IOPORTC 2
-# define PIC32MX_IOPORTD 3
-# define PIC32MX_IOPORTE 4
-# define PIC32MX_IOPORTF 5
-# define PIC32MX_IOPORTG 6
-# define PIC32MX_IOPORT_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00086000 + 0x40*(n))
-
-# define PIC32MX_IOPORTA_K1BASE (PIC32MX_SFR_K1BASE + 0x00086000)
-# define PIC32MX_IOPORTB_K1BASE (PIC32MX_SFR_K1BASE + 0x00086040)
-# define PIC32MX_IOPORTC_K1BASE (PIC32MX_SFR_K1BASE + 0x00086080)
-# define PIC32MX_IOPORTD_K1BASE (PIC32MX_SFR_K1BASE + 0x000860c0)
-# define PIC32MX_IOPORTE_K1BASE (PIC32MX_SFR_K1BASE + 0x00086100)
-# define PIC32MX_IOPORTF_K1BASE (PIC32MX_SFR_K1BASE + 0x00086140)
-# define PIC32MX_IOPORTG_K1BASE (PIC32MX_SFR_K1BASE + 0x00086180)
-
-# define PIC32MX_IOPORTCN_K1BASE (PIC32MX_SFR_K1BASE + 0x000861c0)
-
-#else
-# error "Memory map unknown for this PIC32 chip"
-#endif
-
-/************************************************************************************
- * Public Types
- ************************************************************************************/
-
-#ifndef __ASSEMBLY__
-
-/************************************************************************************
- * Inline Functions
- ************************************************************************************/
-
-/************************************************************************************
- * Public Function Prototypes
- ************************************************************************************/
-
-#ifdef __cplusplus
-#define EXTERN extern "C"
-extern "C" {
-#else
-#define EXTERN extern
-#endif
-
-#undef EXTERN
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_MEMORYMAP_H */
+/************************************************************************************
+ * arch/mips/src/pic32mx/pic32mx-memorymap.h
+ *
+ * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ ****
+ // *********************************************************************************/
+
+#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_MEMORYMAP_H
+#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_MEMORYMAP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+#include "mips32-memorymap.h"
+
+/************************************************************************************
+ * Pre-Processor Definitions
+ ************************************************************************************/
+/* This top-level memory map is valid for the PIC32MX3xx/4xx as well as the
+ * PIC32MX5xx/6xx/7xx families.
+ */
+
+#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4) || defined(CHIP_PIC32MX5) ||
+ defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
+
+/* Physical Memory Map **************************************************************/
+
+# define PIC32MX_DATAMEM_PBASE 0x00000000 /* Size depends on CHIP_DATAMEM_KB */
+# define PIC32MX_PROGFLASH_PBASE 0x1d000000 /* Size depends on CHIP_PROGFLASH_KB */
+# define PIC32MX_SFR_PBASE 0x1f800000 /* Special function registers */
+# define PIC32MX_BOOTFLASH_PBASE 0x1fc00000 /* Size depends on CHIP_BOOTFLASH_KB */
+# define PIC32MX_DEVCFG_PBASE 0x1fc02ff0 /* Device configuration registers */
+
+/* Virtual Memory Map ***************************************************************/
+
+# define PIC32MX_DATAMEM_K0BASE (KSEG0_BASE + PIC32MX_DATAMEM_PBASE)
+# define PIC32MX_PROGFLASH_K0BASE (KSEG0_BASE + PIC32MX_PROGFLASH_PBASE)
+# define PIC32MX_BOOTFLASH_K0BASE (KSEG0_BASE + PIC32MX_BOOTFLASH_PBASE)
+# define PIC32MX_DEVCFG_K0BASE (KSEG0_BASE + PIC32MX_DEVCFG_PBASE)
+
+# define PIC32MX_DATAMEM_K1BASE (KSEG1_BASE + PIC32MX_DATAMEM_PBASE)
+# define PIC32MX_PROGFLASH_K1BASE (KSEG1_BASE + PIC32MX_PROGFLASH_PBASE)
+# define PIC32MX_SFR_K1BASE (KSEG1_BASE + PIC32MX_SFR_PBASE)
+# define PIC32MX_BOOTFLASH_K1BASE (KSEG1_BASE + PIC32MX_BOOTFLASH_PBASE)
+# define PIC32MX_DEVCFG_K1BASE (KSEG1_BASE + PIC32MX_DEVCFG_PBASE)
+#endif
+
+/* Register Base Addresses **********************************************************/
+
+#if defined(CHIP_PIC32MX3) || defined(CHIP_PIC32MX4)
+
+/* Watchdog Register Base Address */
+
+# define PIC32MX_WDT_K1BASE (PIC32MX_SFR_K1BASE + 0x00000000)
+
+/* RTCC Register Base Address */
+
+# define PIC32MX_RTCC_K1BASE (PIC32MX_SFR_K1BASE + 0x00000200)
+
+/* Timer 1-5 Register Base Addresses */
+
+# define PIC32MX_TIMER_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00000600 + 0x200*(n-1))
+# define PIC32MX_TIMER1_K1BASE (PIC32MX_SFR_K1BASE + 0x00000600)
+# define PIC32MX_TIMER2_K1BASE (PIC32MX_SFR_K1BASE + 0x00000800)
+# define PIC32MX_TIMER3_K1BASE (PIC32MX_SFR_K1BASE + 0x00000a00)
+# define PIC32MX_TIMER4_K1BASE (PIC32MX_SFR_K1BASE + 0x00000c00)
+# define PIC32MX_TIMER5_K1BASE (PIC32MX_SFR_K1BASE + 0x00000e00)
+
+/* Input Capture 1-5 Register Base Addresses */
+
+# define PIC32MX_IC_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00002000 + 0x200*(n-1))
+# define PIC32MX_IC1_K1BASE (PIC32MX_SFR_K1BASE + 0x00002000)
+# define PIC32MX_IC2_K1BASE (PIC32MX_SFR_K1BASE + 0x00002200)
+# define PIC32MX_IC3_K1BASE (PIC32MX_SFR_K1BASE + 0x00002400)
+# define PIC32MX_IC4_K1BASE (PIC32MX_SFR_K1BASE + 0x00002600)
+# define PIC32MX_IC5_K1BASE (PIC32MX_SFR_K1BASE + 0x00002800)
+
+/* Output Compare 1-5 Register Base Addresses */
+
+# define PIC32MX_OC_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00003000 + 0x200*(n-1))
+# define PIC32MX_OC1_K1BASE (PIC32MX_SFR_K1BASE + 0x00003000)
+# define PIC32MX_OC2_K1BASE (PIC32MX_SFR_K1BASE + 0x00003200)
+# define PIC32MX_OC3_K1BASE (PIC32MX_SFR_K1BASE + 0x00003400)
+# define PIC32MX_OC4_K1BASE (PIC32MX_SFR_K1BASE + 0x00003600)
+# define PIC32MX_OC5_K1BASE (PIC32MX_SFR_K1BASE + 0x00003800)
+
+/* I2C 1-2 Register Base Addresses */
+
+# define PIC32MX_I2C1_K1BASE (PIC32MX_SFR_K1BASE + 0x00005000)
+# define PIC32MX_I2C2_K1BASE (PIC32MX_SFR_K1BASE + 0x00005200)
+
+/* SPI 1-2 Register Base Addresses */
+
+# define PIC32MX_SPI1_K1BASE (PIC32MX_SFR_K1BASE + 0x00005800)
+# define PIC32MX_SPI2_K1BASE (PIC32MX_SFR_K1BASE + 0x00005a00)
+
+/* UART 1-2 Register Base Addresses */
+
+# define PIC32MX_UART1_K1BASE (PIC32MX_SFR_K1BASE + 0x00006000)
+# define PIC32MX_UART2_K1BASE (PIC32MX_SFR_K1BASE + 0x00006200)
+
+/* Parallel Master Register Base Address */
+
+# define PIC32MX_PMP_K1BASE (PIC32MX_SFR_K1BASE + 0x00007000)
+
+/* ADC Register Base Addresses */
+
+# define PIC32MX_ADC_K1BASE (PIC32MX_SFR_K1BASE + 0x00009000)
+
+/* Comparator Voltage Reference Register Base Addresses */
+
+# define PIC32MX_CVR_K1BASE (PIC32MX_SFR_K1BASE + 0x00009800)
+
+/* Comparator Register Base Addresses */
+
+# define PIC32MX_CM_K1BASE (PIC32MX_SFR_K1BASE + 0x0000a000)
+# define PIC32MX_CM1_K1BASE (PIC32MX_SFR_K1BASE + 0x0000a000)
+# define PIC32MX_CM2_K1BASE (PIC32MX_SFR_K1BASE + 0x0000a010)
+
+/* Oscillator Control Register Base Addresses */
+
+# define PIC32MX_OSC_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f000)
+
+/* Programming and Diagnostics Register Base Addresses */
+
+# define PIC32MX_DDP_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f200)
+
+/* FLASH Controller Register Base Addresses */
+
+# define PIC32MX_FLASH_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f400)
+
+/* Reset Control Register Base Address */
+
+# define PIC32MX_RESET_K1BASE (PIC32MX_SFR_K1BASE + 0x0000f600)
+
+/* Interrupt Register Base Address */
+
+# define PIC32MX_INT_K1BASE (PIC32MX_SFR_K1BASE + 0x00081000)
+
+/* Bus Matrix Register Base Address */
+
+# define PIC32MX_BMX_K1BASE (PIC32MX_SFR_K1BASE + 0x00082000)
+
+/* DMA Register Base Address */
+
+# define PIC32MX_DMA_K1BASE (PIC32MX_SFR_K1BASE + 0x00083000)
+# define PIC32MX_DMACH_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00083060 + 0xc0*(n))
+# define PIC32MX_DMACH0_K1BASE (PIC32MX_SFR_K1BASE + 0x00083060)
+# define PIC32MX_DMACH1_K1BASE (PIC32MX_SFR_K1BASE + 0x00083120)
+# define PIC32MX_DMACH2_K1BASE (PIC32MX_SFR_K1BASE + 0x000831e0)
+# define PIC32MX_DMACH3_K1BASE (PIC32MX_SFR_K1BASE + 0x000832a0)
+
+/* Prefetch Cache Register Base Address */
+
+# define PIC32MX_CHE_K1BASE (PIC32MX_SFR_K1BASE + 0x00084000)
+
+/* USB2 Register Base Addresses */
+
+# define PIC32MX_USB_K1BASE (PIC32MX_SFR_K1BASE + 0x00085000)
+
+/* Port Register Base Addresses */
+
+# define PIC32MX_IOPORTA 0
+# define PIC32MX_IOPORTB 1
+# define PIC32MX_IOPORTC 2
+# define PIC32MX_IOPORTD 3
+# define PIC32MX_IOPORTE 4
+# define PIC32MX_IOPORTF 5
+# define PIC32MX_IOPORTG 6
+# define PIC32MX_IOPORT_K1BASE(n) (PIC32MX_SFR_K1BASE + 0x00086000 + 0x40*(n))
+
+# define PIC32MX_IOPORTA_K1BASE (PIC32MX_SFR_K1BASE + 0x00086000)
+# define PIC32MX_IOPORTB_K1BASE (PIC32MX_SFR_K1BASE + 0x00086040)
+# define PIC32MX_IOPORTC_K1BASE (PIC32MX_SFR_K1BASE + 0x00086080)
+# define PIC32MX_IOPORTD_K1BASE (PIC32MX_SFR_K1BASE + 0x000860c0)
+# define PIC32MX_IOPORTE_K1BASE (PIC32MX_SFR_K1BASE + 0x00086100)
+# define PIC32MX_IOPORTF_K1BASE (PIC32MX_SFR_K1BASE + 0x00086140)
+# define PIC32MX_IOPORTG_K1BASE (PIC32MX_SFR_K1BASE + 0x00086180)
+
+# define PIC32MX_IOPORTCN_K1BASE (PIC32MX_SFR_K1BASE + 0x000861c0)
+
+#elif defined(CHIP_PIC32MX5) || defined(CHIP_PIC32MX6) || defined(CHIP_PIC32MX7)
+# error "Missing definitions"
+#else
+# error "Memory map unknown for this PIC32 chip"
+#endif
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_MEMORYMAP_H */
diff --git a/arch/mips/src/pic32mx/pic32mx-oc.h b/arch/mips/src/pic32mx/pic32mx-oc.h
old mode 100755
new mode 100644
diff --git a/arch/mips/src/pic32mx/pic32mx-osc.h b/arch/mips/src/pic32mx/pic32mx-osc.h
old mode 100755
new mode 100644
diff --git a/arch/mips/src/pic32mx/pic32mx-pmp.h b/arch/mips/src/pic32mx/pic32mx-pmp.h
old mode 100755
new mode 100644
diff --git a/arch/mips/src/pic32mx/pic32mx-reset.h b/arch/mips/src/pic32mx/pic32mx-reset.h
old mode 100755
new mode 100644
diff --git a/arch/mips/src/pic32mx/pic32mx-rtcc.h b/arch/mips/src/pic32mx/pic32mx-rtcc.h
old mode 100755
new mode 100644
diff --git a/arch/mips/src/pic32mx/pic32mx-spi.h b/arch/mips/src/pic32mx/pic32mx-spi.h
old mode 100755
new mode 100644
diff --git a/arch/mips/src/pic32mx/pic32mx-timer.h b/arch/mips/src/pic32mx/pic32mx-timer.h
old mode 100755
new mode 100644
diff --git a/arch/mips/src/pic32mx/pic32mx-timerisr.c b/arch/mips/src/pic32mx/pic32mx-timerisr.c
old mode 100755
new mode 100644
diff --git a/arch/mips/src/pic32mx/pic32mx-uart.h b/arch/mips/src/pic32mx/pic32mx-uart.h
old mode 100755
new mode 100644
diff --git a/arch/mips/src/pic32mx/pic32mx-usbotg.h b/arch/mips/src/pic32mx/pic32mx-usbotg.h
old mode 100755
new mode 100644
diff --git a/arch/mips/src/pic32mx/pic32mx-wdt.h b/arch/mips/src/pic32mx/pic32mx-wdt.h
old mode 100755
new mode 100644
diff --git a/configs/pic32-starterkit/README.txt b/configs/pic32-starterkit/README.txt
new file mode 100644
index 0000000000000000000000000000000000000000..ca32814ae8925ed7817f69dc9ebe1c56893c33d7
--- /dev/null
+++ b/configs/pic32-starterkit/README.txt
@@ -0,0 +1,542 @@
+configs/pic32-starterkit README
+===============================
+
+
+This README file discusses the port of NuttX to the Microchip PIC32 Ethernet
+Starter Kit (DM320004) with the Multimedia Expansion Board (MEB, DM320005).
+Advanced USB Storage. See www.microchip.com for further information.
+
+The PIC32 Ethernet Starter Kit includes:
+
+- PIC32MX795F512L 32-bit microcontroller.
+- PIC32MX795F512L USB microcontroller for on-board debugging.
+- Green power indicator LED.
+- Orange debug indicator LED.
+- Three user-defined indicator LEDs.
+- Ethernet 10/100 bus speed indicator LED.
+- Three push button switches for user-defined inputs.
+- On-board crystal for precision microcontroller clocking (8 MHz).
+- 50 MHz Ethernet PHY oscillator.
+- 32 kHz oscillator (optional).
+- USB connectivity for on-board debugger communications.
+- USB Host and OTG power supply for powering PIC32 USB applications.
+- USB Type A receptacle connectivity for PIC32 host-based applications.
+- USB Type micro-AB receptacle for OTG and USB device connectivity for PIC32
+ OTG/device-based applications.
+- RJ-45 Ethernet port (External Ethernet PHY).
+
+The MEB adds:
+
+- 3.2 inch (8.1 cm) QVGA touch screen display with backlight
+- Solomon Systech Graphics Controller (SSD1926)
+- Five user-controlled LEDs
+- Power LED
+- Four-way joystick
+- Fire button
+- Headphone jack
+- Line output jack
+- Microphone input jack
+- microSD card slot.
+- Accelerometer and temperature sensor
+- 24LC08 EEPROM.
+- SPI Flash
+- 24-bit audio codec
+- CPLD for SPI and Chip Select configuration
+- Integrated 802.11 wireless connectivity
+
+Contents
+========
+
+ PIC32MX795F512L Pin Out
+ Toolchains
+ Loading NuttX with PICkit2
+ PIC32MX Configuration Options
+ Configurations
+
+PIC32MX795F512L Pin Out
+=======================
+
+ LEFT SIDE, TOP-TO-BOTTOM (if pin 1 is in upper left)
+PIN CONFIGURATIONS SIGNAL NAME
+ (Table 1-1) (User Guide)
+--- ---------------------------------- -------------------------- -----------------------------------------------
+ 1 RG15/AERXERR ERXERR Ethernet RX_ER/MDIX_IN
+ 2 VDD P32_VDD ---
+ 3 PMD5/RE5 PMPD5/RE5 J2 pin 13
+ 4 PMD6/RE6 PMPD6/RE6 J2 pin 9
+ 5 PMD7/RE7 PMPD7/RE7 J2 pin 7
+ 6 RC1/T2CK T2CLK/RC1 J2 pin 35 (timer)
+ 7 RC2/AC2TX/T3CK T3CLK/RC2 J2 pin 37 (timer)
+ 8 RC3/AC2RX/T4CK T4CLK/RC3 J2 pin 39 (timer)
+ 9 RC4/SDI1/T5CK SDI1/T4CLK/RC4 J2 pin 41 (timer)
+ J2 pin 93 (SPI1)
+ 10 PMA5/CN8/ECOL/RG6/SCK2/U3RTS/U6TX PMPA5/SCM2C/CN8/RG6 J2 pin 45 (SPI2)
+ J2 pin 117 (PMP address)
+ 11 PMA4/CN9/ECRS/RG7/SDA4/SDI2/U3RX PMPA4/SCM2A/CN9/RG7 J2 pin 47 (SPI2)
+ J2 pin 119 (PMP address)
+ 12 PMA3/AECRSDV/AERXDV/CN10/ECRSDV/ ECRS_DV Ethernet CRS/CRS_DV/LED_CFG
+ ERXDV/RG8/SCL4/SDO2/U3TX
+ 13 MCLR PIC32_MCLR (pulled up)
+ PIC32MX440F512H debug processor
+ J2 pin 130 (ICSP)
+ 14 PMA2/AEREFCLK/AERXCLK/CN11/ EREF_CLK 50MHz clock, Ethernet X1
+ EREFCLK/ERXCLK/RG9/SS2/U3CTS/
+ U6RX
+ 15 VSS (grounded) ---
+ 16 VDD P32_VDD ---
+ 17 RA0/TMS TMS/RA0 J2 pin 126 (JTAG/GPIO)
+ 18 AERXD0/INT1/RE8 ERXD0(2) Ethernet RXD_0/PHYAD1
+ 19 AERXD1/INT2/RE9 ERXD1(2) Ethernet RXD_1/PHYAD2
+ 20 AN5/C1IN+/CN7/RB5/VBUSON VBUSON/C1IN+/AN5/CN7/RB5 USB host power supply, TPS20x1B ~EN,
+ Low enables power to host port (J4)
+ USB OTG power supply, MCP1253_MSOP ~SHDN
+ Enables power to device/OTG port (J5)
+ J2 pin 63 (comparator 1)
+ J2 pin 62 (A/D)
+ 21 AN4/C1IN-/CN6/RB4 USBOEN/C1IN-/AN4/CN6/RB4 J2 pin 65 (comparator 1)
+ J2 pin 64 (A/D)
+ 22 AN3/C2IN+/CN5/RB3 C2IN+/AN3/CN5/RB3 TPS20x1B ~OC, sense host port power
+ MCP1253_MSOP PGOOD, sense device/OTG port power
+ J2 pin 67 (comparator 2)
+ J2 pin 66 (A/D)
+ 23 AN2/C2IN-/CN4/RB2 C2IN-/AN2/CN4/RB2 J2 pin 69 (comparator 2)
+ J2 pin 101
+ J2 pin 68 (A/D)
+ 24 AN1/CN3/PGEC1/RB1 PGC1/AN1/CN3/RB1 J2 pin 70 (A/D)
+ 25 AN0/CN2/PGED1/RB0 PGD1/AN0/CN2/RB0 J2 pin 72 (A/D)
+
+ BOTTOM SIDE, LEFT-TO-RIGHT (if pin 1 is in upper left)
+PIN CONFIGURATIONS SIGNAL NAME
+ (Table 1-1) (User Guide)
+--- ---------------------------------- -------------------------- -----------------------------------------------
+ 26 AN6/OCFA/PGEC2/RB6 PIC32_PGC2 PIC32MX440F512H debug processor
+ J2 pin 128 (ICSP)
+ 27 AN7/PGED2/RB7 PIC32_PGD2/DBG_SD0 PIC32MX440F512H debug processor
+ J2 pin 132 (ICSP)
+ 28 PMA7/AERXD2/CVREF-/RA9 PMPA7/VREF-/RA9 J2 pin 113 (PMP address)
+ J2 pin 114 (A/D ref)
+ 29 PMA6/AERXD3/CVREF+/RA10/VREF+ PMPA6/VREF+/RA10 J2 pin 115 (PMP address)
+ J2 pin 116 (A/D ref)
+ 30 AVDD P32_VDD ---
+ 31 AVSS (grounded) ---
+ 32 AN8/C1OUT/RB8 C1OUT/AN8/RB8 J2 pin 71
+ 33 AN9/C2OUT/RB9 C2OUT/AN9/RB9 J2 pin 73
+ 34 PMA13/AN10/RB10/CVREFOUT PMPA13/CVREF/AN10 J2 pin 101 (PMP address)
+ J2 pin 102 (Comparator ref)
+ 35 PMA12/AETXERR/AN11/ERXERR/RB11 PMPA12/AN11/RB11 J2 pin 103 (PMP address)
+ 36 VSS (grounded) ---
+ 37 VDD P32_VDD ---
+ 38 RA1/TCK TCK/RA1 PIC32MX440F512H debug processor
+ J2 pin 124 (JTAG/GPIO)
+ 39 AC1TX/RF13/SCK4/U2RTS/U5TX SCM3D/BCLK2/RF13 J2 pin 106 (UART2)
+ 40 AC1RX/RF12/SS4/U2CTS/U5RX SCM3C/FR12 J2 pin 108 (UART2)
+ 41 PMA11/AECRS/AN12/ERXD0/RB12 PMPA11/AN12/RB12 J2 pin 105 (PMP address)
+ 42 PMA10/AECOL/AN13/ERXD1/RB13 PMPA10/AN13/RB13 J2 pin 107 (PMP address)
+ 43 PMA1/AETXD3/AN14/ERXD2/PMALH/RB14 PMPA1/AN14/RB14 J2 pin 127 (PMP address)
+ 44 PMA0/AETXD2/AN15/CN12/ERXD3/OCFB/ PMPA0/AN15/OCFB/CN12 J2 pin 129 (PMP address)
+ PMALL/RB15 J2 pin 36
+ 45 VSS (grounded) ---
+ 46 VDD P32_VDD ---
+ 47 AETXD0/CN20/RD14/SS3/U1CTS/U4RX EXTD0(2) Ethernet TXD_0
+ 48 AETXD1/CN21/RD15/SCK3/U1RTS/U4TX EXTD1(2) Ethernet TXD_1
+ 49 PMA9/CN17/RF4/SDA5/SDI4/U2RX PMPA9/SCM3A/CN17/RF4 J2 pin 109 (PMP address)
+ J2 pin 110 (UART2)
+ 50 PMA8/CN18/RF5/SCL5/SDO4/U2TX PMPA8/SCM3B/CN18/RF5 J2 pin 111 (PMP address)
+ J2 pin 112 (UART2)
+
+ RIGHT SIDE, TOP-TO-BOTTOM (if pin 1 is in upper left)
+PIN CONFIGURATIONS SIGNAL NAME
+ (Table 1-1) (User Guide)
+--- ---------------------------------- -------------------------- -----------------------------------------------
+ 75 VSS (grounded)
+ 74 CN0/RC14/SOSCO/T1CK SOSC0/T1CK/CN0/RC14 32kHz Oscillator, J2 pin (timer)
+ J2 pin 32 (secondary OSC)
+ 73 CN1/RC13/SOSCI SOSC1/CN1/RC13 32kHz Oscillator
+ J2 pin 32 (secondary OSC)
+ 72 OC1/INT0/RD0/SDO1 SDO1/INT0/OC1/RD0 User LED D4 (high illuminates)
+ J2 pin 87 (EXT_INT)
+ J2 pin 95 (SPI1)
+ J2 pin 46 (OC/PWN_
+ 71 PMA14/AEMDC/EMDC/IC4/PMCS1/RD11 EMDC Ethernet MDC
+ 70 PMA15/IC3/PMCS2/RD10/SCK1 SCK1/IC3/PMPCS2/RD10 J2 pin 29 (PMP control)
+ J2 pin 91 (SPI1)
+ J2 pin 52 (input capture)
+ 69 IC2/RD9/SS1 SS1/IC2/RD9 J2 pin 54 (input capture)
+ 68 AEMDIO/EMDIO/IC1/RD8/RTCC EMDIO Ethernet MDIO
+ 67 AETXEN/INT4/RA15/SDA1 ETXEN(2) Ethernet TX_EN
+ 66 AETXCLK/INT3/RA14/SCL1 INT3/SCL1/RA14 Ethernet PWR_DOWN/INT
+ 65 VSS (grounded) ---
+ 64 CLKO/OSC2/RC15 8MHz crystal
+ 63 CLKI/OSC1/RC12 8MHz crystal
+ 62 VDD P32_VDD ---
+ 61 RA5/TDO TDO/RA5 PIC32MX440F512H debug processor
+ J2 pin 118 (JTAG/GPIO)
+ 60 RA4/TDI TDI/RA4 PIC32MX440F512H debug processor
+ 59 RA3/SDA2 SDA2/RA3 J2 pin 74 (I2C2)
+ 58 RA2/SCL2 SCL2/RA2 J2 pin 76 (I2C2)
+ 57 D+/RG2 D+/RG2 Host port (J4), Device OTG port (J5)
+ 56 D-/RG3 D-/RG3 Host port (J4), Device OTG port (J5)
+ 55 VUSB P32_VDD ---
+ 54 VBUS P32_VBUS ---
+ 53 RF8/SCL3/SDO3/U1TX SCM1B/RF8 J2 pin 90 (UART1)
+ 52 RF2/SDA3/SDI3/U1RX SCM1A/RF2 J2 pin 88 (UART1)
+ 51 RF3/USBID USBID/RF3 Device OTG port (J5)
+
+ TOP SIDE, LEFT-TO-RIGHT (if pin 1 is in upper left)
+PIN CONFIGURATIONS SIGNAL NAME
+ (Table 1-1) (User Guide)
+--- ---------------------------------- -------------------------- -----------------------------------------------
+100 PMD4/RE4 PMPD4/RE4 J2 pin 15 (PMP data)
+ 99 PMD3/RE3 PMPD3/RE3 J2 pin 17 (PMP data)
+ 98 PMD2/RE2 PMPD2/RE2 J2 pin 19 (PMP data)
+ 97 RG13/TRD0 TRD0/RG13 J2 pin 8 (Trace/GPIO)
+ 96 RG12/TRD1 TRD1/RG12 J2 pin 5
+ 95 RG14/TRD2 TRD2/RG14 J2 pin 3
+ 94 PMD1/RE1 PMPD1/RE1 J2 pin 21 (PMP data)
+ 93 PMD0/RE0 PMPD0/RE0 J2 pin 23 (PMP data)
+ 92 RA7/TRD3 TRD3/RA7 J2 pin 6 (Trace/GPIO)
+ 91 RA6/TRCLK TRCLK/RA6 J2 pin 4 (Trace/GPIO)
+ 90 PMD8/C2RX/RG0 PMPD8/RG0 J2 pin 10 (PMP data)
+ 89 PMD9/C2TX/ETXERR/RG1 PMPD9/RG1 J2 pin 14 (PMP data)
+ 88 PMD10/C1TX/ETXD0/RF1 PMPD10/RF1 J2 pin 16 (PMP data)
+ 87 PMD11/C1RX/ETXD1/RF0 PMPD11/RF0 J2 pin 18 (PMP data)
+ 86 VDD P32_VDD ---
+ 85 VCAP/VCORE (capacitor to ground) ---
+ 84 PMD15/CN16/ETXCLK/RD7 PMPD15/CN16/RD7 Switch SW2 (low when closed)
+ J2 pin 26 (PMP data)
+ 83 PMD14/CN15/ETXEN/RD6 PMPD14/CN15/RD6 Switch SW1 (low when closed)
+ J2 pin 24 (PMP data)
+ 82 CN14/PMRD/RD5 PMPRD/CN14/RD5 J2 pin 25
+ 81 CN13/OC5/PMWR/RD4 PMPWR/OC5/C13/RD4 J2 pin 28 (PMP control)
+ J2 pin 38
+ 80 PMD13/CN19/ETXD3/RD13 CN19/PMPD13/RD13 Switch SW3 (low when closed)
+ J2 pin 22 (PMP data)
+ 79 PMD12/ETXD2/IC5/RD12 IC5/PMPD12/RD12 J2 pin 20 (PMP data)
+ J2 pin 48
+ 78 OC4/RD3 OC4/RD3 J2 pin 40 (OC/PWM)
+ 77 OC3/RD2 OC3/RD2 User LED D5 (high illuminates)
+ J2 pin 42 (OC/PWM)
+ 76 OC2/RD1 OC1/RD1 User LED D6 (high illuminates)
+ J2 pin 44 (OC/PWM)
+
+Toolchains
+==========
+
+ I am using the free, LITE version of the PIC32MX toolchain available
+ for download from the microchip.com web site. I am using the Windows
+ version. The MicroChip toolchain is the only toolchaing currently
+ supported in these configurations, but it should be a simple matter to
+ adapt to other toolchains by modifying the Make.defs file include in
+ each configuration.
+
+ Toolchain Options:
+
+ CONFIG_PIC32MX_MICROCHIPW - MicroChip full toolchain for Windows
+ CONFIG_PIC32MX_MICROCHIPL - MicroChip full toolchain for Linux
+ CONFIG_PIC32MX_MICROCHIPW_LITE - MicroChip LITE toolchain for Windows
+ CONFIG_PIC32MX_MICROCHIPL_LITE - MicroChip LITE toolchain for Linux
+
+ Windows Native Toolchains
+
+ NOTE: There are several limitations to using a Windows based toolchain in a
+ Cygwin environment. The three biggest are:
+
+ 1. The Windows toolchain cannot follow Cygwin paths. Path conversions are
+ performed automatically in the Cygwin makefiles using the 'cygpath' utility
+ but you might easily find some new path problems. If so, check out 'cygpath -w'
+
+ 2. Windows toolchains cannot follow Cygwin symbolic links. Many symbolic links
+ are used in Nuttx (e.g., include/arch). The make system works around these
+ problems for the Windows tools by copying directories instead of linking them.
+ But this can also cause some confusion for you: For example, you may edit
+ a file in a "linked" directory and find that your changes had not effect.
+ That is because you are building the copy of the file in the "fake" symbolic
+ directory. If you use a Windows toolchain, you should get in the habit of
+ making like this:
+
+ make clean_context all
+
+ An alias in your .bashrc file might make that less painful.
+
+ 3. Dependencies are not made when using Windows versions of the GCC. This is
+ because the dependencies are generated using Windows pathes which do not
+ work with the Cygwin make.
+
+ Support has been added for making dependencies with the windows-native toolchains.
+ That support can be enabled by modifying your Make.defs file as follows:
+
+ - MKDEP = $(TOPDIR)/tools/mknulldeps.sh
+ + MKDEP = $(TOPDIR)/tools/mkdeps.sh --winpaths "$(TOPDIR)"
+
+ If you have problems with the dependency build (for example, if you are not
+ building on C:), then you may need to modify tools/mkdeps.sh
+
+Loading NuttX with PICkit2
+==========================
+
+ NOTE: You need a PICKit3 if you plan to use the MPLAB debugger! The PICKit2
+ can, however, still be used to load problems. Instructions for the PICKit3
+ are similar.
+
+ Intel Hex Forma Files:
+ ----------------------
+
+ When NuttX is built it will produce two files in the top-level NuttX
+ directory:
+
+ 1) nuttx - This is an ELF file, and
+ 2) nuttx.ihx - This is an Intel Hex format file. This is controlled by
+ the setting CONFIG_INTELHEX_BINARY in the .config file.
+
+ The PICkit tool wants an Intel Hex format file to burn into FLASH.
+ However, there are two problems with the generated nutt.ihx:
+
+ 1) The tool expects Intel Hex format files to be named *.hex. This
+ is not a significant issue. However, just renaming the file to
+ nuttx.hex is *not* sufficient. There is another problem:
+ 2) The tool expects the nuttx.hex file to contain physical addresses.
+ But the nuttx.ihx file generated from the top-level make will have
+ address in the KSEG0 and KSEG1 regions.
+
+ tools/mkpichex:
+ ---------------
+
+ There is a simple tool in the configs/pic32-starterkit/tools directory
+ that can be used to solve both issues with the nuttx.ihx file. But,
+ first, you must build the the tools:
+
+ cd configs/pic32-starterkit/tools
+ make
+
+ Now you will have an excecutable file call mkpichex (or mkpichex.exe on
+ Cygwin). This program will take the nutt.ihx file as an input, it will
+ convert all of the KSEG0 and KSEG1 addresses to physical address, and
+ it will write the modified file as nuttx.hex.
+
+ To use this file, you need to do the following things:
+
+ . ./setenv.sh # Source setenv.sh. Among other this, this script
+ # will add configs/pic32-starterkit/tools to your
+ # PATH variable
+ make # Build nuttx and nuttx.ihx
+ mkpichex $PWD # Convert nuttx.ihx to nuttx.hex. $PWD is the path
+ # to the top-level build directory. It is the only
+ # required input to mkpichex.
+
+PIC32MX Configuration Options
+=============================
+
+ General Architecture Settings:
+
+ CONFIG_ARCH - Identifies the arch/ subdirectory. This should
+ be set to:
+
+ CONFIG_ARCH=mips
+
+ CONFIG_ARCH_family - For use in C code:
+
+ CONFIG_ARCH_MIPS=y
+
+ CONFIG_ARCH_architecture - For use in C code:
+
+ CONFIG_ARCH_MIPS32=y
+
+ CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
+
+ CONFIG_ARCH_CHIP=pic32mx
+
+ CONFIG_ARCH_CHIP_name - For use in C code to identify the exact
+ chip:
+
+ CONFIG_ARCH_CHIP_PIC32MX795F512L=y
+
+ CONFIG_ARCH_BOARD - Identifies the configs subdirectory and
+ hence, the board that supports the particular chip or SoC.
+
+ CONFIG_ARCH_BOARD=pic32-starterkit
+
+ CONFIG_ARCH_BOARD_name - For use in C code
+
+ CONFIG_ARCH_BOARD_PIC32_STARTERKIT=y
+
+ CONFIG_ARCH_LOOPSPERMSEC - Must be calibrated for correct operation
+ of delay loops
+
+ CONFIG_ENDIAN_BIG - define if big endian (default is little
+ endian)
+
+ CONFIG_DRAM_SIZE - Describes the installed DRAM (CPU SRAM in this case):
+
+ CONFIG_DRAM_SIZE=(32*1024) (32Kb)
+
+ There is an additional 32Kb of SRAM in AHB SRAM banks 0 and 1.
+
+ CONFIG_DRAM_START - The start address of installed DRAM
+
+ CONFIG_DRAM_START=0x10000000
+
+ CONFIG_DRAM_END - Last address+1 of installed RAM
+
+ CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE)
+
+ CONFIG_ARCH_IRQPRIO - The PIC32MXx supports interrupt prioritization
+
+ CONFIG_ARCH_IRQPRIO=y
+
+ CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to boards that
+ have LEDs
+
+ CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
+ stack. If defined, this symbol is the size of the interrupt
+ stack in bytes. If not defined, the user task stacks will be
+ used during interrupt handling.
+
+ CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
+
+ CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture.
+
+ CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that
+ cause a 100 second delay during boot-up. This 100 second delay
+ serves no purpose other than it allows you to calibratre
+ CONFIG_ARCH_LOOPSPERMSEC. You simply use a stop watch to measure
+ the 100 second delay then adjust CONFIG_ARCH_LOOPSPERMSEC until
+ the delay actually is 100 seconds.
+
+ PIC32MX Configuration
+
+ CONFIG_PIC32MX_MVEC - Select muli- vs. single-vectored interrupts
+
+ Individual subsystems can be enabled:
+
+ CONFIG_PIC32MX_WDT - Watchdog timer
+ CONFIG_PIC32MX_T2 - Timer 2 (Timer 1 is the system time and always enabled)
+ CONFIG_PIC32MX_T3 - Timer 3
+ CONFIG_PIC32MX_T4 - Timer 4
+ CONFIG_PIC32MX_T5 - Timer 5
+ CONFIG_PIC32MX_IC1 - Input Capture 1
+ CONFIG_PIC32MX_IC2 - Input Capture 2
+ CONFIG_PIC32MX_IC3 - Input Capture 3
+ CONFIG_PIC32MX_IC4 - Input Capture 4
+ CONFIG_PIC32MX_IC5 - Input Capture 5
+ CONFIG_PIC32MX_OC1 - Output Compare 1
+ CONFIG_PIC32MX_OC2 - Output Compare 2
+ CONFIG_PIC32MX_OC3 - Output Compare 3
+ CONFIG_PIC32MX_OC4 - Output Compare 4
+ CONFIG_PIC32MX_OC5 - Output Compare 5
+ CONFIG_PIC32MX_I2C1 - I2C 1
+ CONFIG_PIC32MX_I2C2 - I2C 2
+ CONFIG_PIC32MX_SPI2 - SPI 2
+ CONFIG_PIC32MX_UART1 - UART 1
+ CONFIG_PIC32MX_UART2 - UART 2
+ CONFIG_PIC32MX_ADC - ADC 1
+ CONFIG_PIC32MX_PMP - Parallel Master Port
+ CONFIG_PIC32MX_CM1 - Comparator 1
+ CONFIG_PIC32MX_CM2 - Comparator 2
+ CONFIG_PIC32MX_RTCC - Real-Time Clock and Calendar
+ CONFIG_PIC32MX_DMA - DMA
+ CONFIG_PIC32MX_FLASH - FLASH
+ CONFIG_PIC32MX_USBDEV - USB device
+ CONFIG_PIC32MX_USBHOST - USB host
+
+
+ PIC32MX Configuration Settings
+ DEVCFG0:
+ CONFIG_PIC32MX_DEBUGGER - Background Debugger Enable. Default 3 (disabled). The
+ value 2 enables.
+ CONFIG_PIC32MX_ICESEL - In-Circuit Emulator/Debugger Communication Channel Select
+ Default 1 (PG2)
+ CONFIG_PIC32MX_PROGFLASHWP - Program FLASH write protect. Default 0xff (disabled)
+ CONFIG_PIC32MX_BOOTFLASHWP - Default 1 (disabled)
+ CONFIG_PIC32MX_CODEWP - Default 1 (disabled)
+ DEVCFG1: (All settings determined by selections in board.h)
+ DEVCFG2: (All settings determined by selections in board.h)
+ DEVCFG3:
+ CONFIG_PIC32MX_USBIDO - USB USBID Selection. Default 1 if USB enabled
+ (USBID pin is controlled by the USB module), but 0 (GPIO) otherwise.
+ CONFIG_PIC32MX_VBUSIO - USB VBUSON Selection (Default 1 if USB enabled
+ (VBUSON pin is controlled by the USB module, but 0 (GPIO) otherwise.
+ CONFIG_PIC32MX_WDENABLE - Enabled watchdog on power up. Default 0 (watchdog
+ can be enabled later by software).
+
+ The priority of interrupts may be specified. The value ranage of
+ priority is 4-31. The default (16) will be used if these any of these
+ are undefined.
+
+ CONFIG_PIC32MX_CTPRIO - Core Timer Interrupt
+ CONFIG_PIC32MX_CS0PRIO - Core Software Interrupt 0
+ CONFIG_PIC32MX_CS1PRIO - Core Software Interrupt 1
+ CONFIG_PIC32MX_INT0PRIO - External Interrupt 0
+ CONFIG_PIC32MX_INT1PRIO - External Interrupt 1
+ CONFIG_PIC32MX_INT2PRIO - External Interrupt 2
+ CONFIG_PIC32MX_INT3PRIO - External Interrupt 3
+ CONFIG_PIC32MX_INT4PRIO - External Interrupt 4
+ CONFIG_PIC32MX_FSCMPRIO - Fail-Safe Clock Monitor
+ CONFIG_PIC32MX_T1PRIO - Timer 1 (System timer) priority
+ CONFIG_PIC32MX_T2PRIO - Timer 2 priority
+ CONFIG_PIC32MX_T3PRIO - Timer 3 priority
+ CONFIG_PIC32MX_T4PRIO - Timer 4 priority
+ CONFIG_PIC32MX_T5PRIO - Timer 5 priority
+ CONFIG_PIC32MX_IC1PRIO - Input Capture 1
+ CONFIG_PIC32MX_IC2PRIO - Input Capture 2
+ CONFIG_PIC32MX_IC3PRIO - Input Capture 3
+ CONFIG_PIC32MX_IC4PRIO - Input Capture 4
+ CONFIG_PIC32MX_IC5PRIO - Input Capture 5
+ CONFIG_PIC32MX_OC1PRIO - Output Compare 1
+ CONFIG_PIC32MX_OC2PRIO - Output Compare 2
+ CONFIG_PIC32MX_OC3PRIO - Output Compare 3
+ CONFIG_PIC32MX_OC4PRIO - Output Compare 4
+ CONFIG_PIC32MX_OC5PRIO - Output Compare 5
+ CONFIG_PIC32MX_I2C1PRIO - I2C 1
+ CONFIG_PIC32MX_I2C2PRIO - I2C 2
+ CONFIG_PIC32MX_SPI2PRIO - SPI 2
+ CONFIG_PIC32MX_UART1PRIO - UART 1
+ CONFIG_PIC32MX_UART2PRIO - UART 2
+ CONFIG_PIC32MX_CN - Input Change Interrupt
+ CONFIG_PIC32MX_ADCPRIO - ADC1 Convert Done
+ CONFIG_PIC32MX_PMPPRIO - Parallel Master Port
+ CONFIG_PIC32MX_CM1PRIO - Comparator 1
+ CONFIG_PIC32MX_CM2PRIO - Comparator 2
+ CONFIG_PIC32MX_FSCMPRIO - Fail-Safe Clock Monitor
+ CONFIG_PIC32MX_RTCCPRIO - Real-Time Clock and Calendar
+ CONFIG_PIC32MX_DMA0PRIO - DMA Channel 0
+ CONFIG_PIC32MX_DMA1PRIO - DMA Channel 1
+ CONFIG_PIC32MX_DMA2PRIO - DMA Channel 2
+ CONFIG_PIC32MX_DMA3PRIO - DMA Channel 3
+ CONFIG_PIC32MX_FCEPRIO - Flash Control Event
+ CONFIG_PIC32MX_USBPRIO - USB
+
+ PIC32MXx specific device driver settings. NOTE: For the Sure board,
+ UART2 is brought out to the DB9 connector and serves as the serial
+ console.
+
+ CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the
+ console and ttys0 (default is the UART0).
+ CONFIG_UARTn_RXBUFSIZE - Characters are buffered as received.
+ This specific the size of the receive buffer
+ CONFIG_UARTn_TXBUFSIZE - Characters are buffered before
+ being sent. This specific the size of the transmit buffer
+ CONFIG_UARTn_BAUD - The configure BAUD of the UART. Must be
+ CONFIG_UARTn_BITS - The number of bits. Must be either 7 or 8.
+ CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
+ CONFIG_UARTn_2STOP - Two stop bits
+
+ PIC32MXx USB Device Configuration
+
+ PIC32MXx USB Host Configuration (the PIC32MX does not support USB Host)
+
+Configurations
+==============
+
+Each PIC32MX configuration is maintained in a sudirectory and can be
+selected as follow:
+
+ cd tools
+ ./configure.sh pic32-starterkit/<subdir>
+ cd -
+ . ./setenv.sh
+
+Where <subdir> is one of the following:
+
+ ostest:
+ This configuration directory, performs a simple OS test using
+ apps/examples/ostest.
diff --git a/configs/pic32-starterkit/include/board.h b/configs/pic32-starterkit/include/board.h
new file mode 100644
index 0000000000000000000000000000000000000000..8df81b4b9145a785dca91df5183619752350baa1
--- /dev/null
+++ b/configs/pic32-starterkit/include/board.h
@@ -0,0 +1,133 @@
+/****************************************************************************
+ * configs/pic32-starterkit/include/board.h
+ * include/arch/board/board.h
+ *
+ * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __CONFIGS_SURE_PIC32MX_INCLUDE_BOARD_H
+#define __CONFIGS_SURE_PIC32MX_INCLUDE_BOARD_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-Processor Definitions
+ ****************************************************************************/
+/* Configuration ************************************************************/
+
+/* Clocking *****************************************************************/
+/* Crystal frequencies */
+
+#define BOARD_POSC_FREQ 20000000 /* Primary OSC XTAL frequency (20MHz) */
+#define BOARD_SOSC_FREQ 32768 /* Secondary OSC XTAL frequency (32.768KHz) */
+
+/* PLL configuration and resulting CPU clock.
+ * CPU_CLOCK = ((POSC_FREQ / IDIV) * MULT) / ODIV
+ */
+
+#define BOARD_PLL_IDIV 5 /* PLL input divider */
+#define BOARD_PLL_MULT 15 /* PLL multiplier */
+#define BOARD_PLL_ODIV 1 /* PLL output divider */
+
+#define BOARD_CPU_CLOCK 60000000 /* CPU clock (60MHz = (20MHz / 5) * 15 / 1) */
+
+/* USB PLL configuration.
+ * USB_CLOCK = ((POSC_XTAL / IDIV) * 24) / 2
+ */
+
+#define BOARD_UPLL_IDIV 5 /* USB PLL divider */
+#define BOARD_USB_CLOCK 48000000 /* USB clock ((20MHz / 5) * 24) */
+
+/* Peripheral clock is *not* divided down from CPU clock.
+ * PBCLOCK = CPU_CLOCK / PBDIV
+ */
+
+#define BOARD_PBDIV 1 /* Peripheral clock divisor (PBDIV) */
+#define BOARD_PBCLOCK 60000000 /* Peripheral clock (PBCLK = 60MHz/1) */
+
+/* Watchdog pre-scaler (re-visit) */
+
+#define BOARD_WD_ENABLE 0 /* Watchdog is disabled */
+#define BOARD_WD_PRESCALER 8 /* Watchdog pre-scaler */
+
+/* LED definitions **********************************************************/
+/* The Sure PIC32MX board has five LEDs. One (D4, lablel "Power") is not
+ * controllable by software. Four are controllable by software:
+ *
+ * D7 "USB" Yellow RD7 Low illuminates
+ * D8 "SD" Yellow RD6 Low illuminates
+ * D9 "Flash" Yellow RF0 Low illuminates
+ * D10 "Error" Red RF1 Low illuminates
+ */
+ /* ON OFF */
+ /* USB SD FLASH ERROR USB SD FLASH ERROR */
+#define LED_STARTED 0 /* OFF OFF OFF OFF --- --- --- --- */
+#define LED_HEAPALLOCATE 1 /* ON OFF N/C N/C --- --- --- --- */
+#define LED_IRQSENABLED 2 /* OFF ON N/C N/C --- --- --- --- */
+#define LED_STACKCREATED 3 /* ON ON N/C N/C --- --- --- --- */
+#define LED_INIRQ 4 /* N/C N/C ON N/C N/C N/C OFF N/C */
+#define LED_SIGNAL 4 /* N/C N/C ON N/C N/C N/C OFF N/C */
+#define LED_ASSERTION 4 /* N/C N/C ON N/C N/C N/C OFF N/C */
+#define LED_PANIC 5 /* N/C N/C N/C ON N/C N/C N/C OFF */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __CONFIGS_SURE_PIC32MX_INCLUDE_BOARD_H */
diff --git a/configs/pic32-starterkit/ostest/Make.defs b/configs/pic32-starterkit/ostest/Make.defs
new file mode 100644
index 0000000000000000000000000000000000000000..586135a3e2584ab3afcd6ec08b576e795b8180c9
--- /dev/null
+++ b/configs/pic32-starterkit/ostest/Make.defs
@@ -0,0 +1,160 @@
+############################################################################
+# configs/pic32-starterkit/ostest/Make.defs
+#
+# Copyright (C) 2011 Gregory Nutt. All rights reserved.
+# Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+# used to endorse or promote products derived from this software
+# without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+include ${TOPDIR}/.config
+
+# Setup for the selected toolchain
+
+ifeq ($(CONFIG_PIC32MX_MICROCHIPW),y)
+ # Microchip toolchain under Windows
+ CROSSDEV = pic32-
+ WINTOOL = y
+ MAXOPTIMIZATION = -O2
+ ARCHCPUFLAGS = -mprocessor=elf32pic32mx -mno-float -mlong32 -membedded-data
+ ARCHPICFLAGS = -fpic -membedded-pic
+ LDFLAGS += -nostartfiles -nodefaultlibs
+endif
+ifeq ($(CONFIG_PIC32MX_MICROCHIPW_LITE),y)
+ # Microchip toolchain under Windows
+ CROSSDEV = pic32-
+ WINTOOL = y
+# MAXOPTIMIZATION = -O2
+ ARCHCPUFLAGS = -mprocessor=elf32pic32mx -mno-float -mlong32 -membedded-data
+ ARCHPICFLAGS = -fpic -membedded-pic
+ LDFLAGS += -nostartfiles -nodefaultlibs
+endif
+ifeq ($(CONFIG_PIC32MX_MICROCHIPL),y)
+ # Microchip toolchain under Linux
+ CROSSDEV = pic32-
+ MAXOPTIMIZATION = -O2
+ ARCHCPUFLAGS = -mprocessor=elf32pic32mx -mno-float -mlong32 -membedded-data
+ ARCHPICFLAGS = -fpic -membedded-pic
+ LDFLAGS += -nostartfiles -nodefaultlibs
+endif
+ifeq ($(CONFIG_PIC32MX_MICROCHIPL_LITE),y)
+ # Microchip toolchain under Linux
+ CROSSDEV = pic32-
+# MAXOPTIMIZATION = -O2
+ ARCHCPUFLAGS = -mprocessor=elf32pic32mx -mno-float -mlong32 -membedded-data
+ ARCHPICFLAGS = -fpic -membedded-pic
+ LDFLAGS += -nostartfiles -nodefaultlibs
+endif
+
+ifeq ($(WINTOOL),y)
+ # Windows-native toolchains
+ DIRLINK = $(TOPDIR)/tools/winlink.sh
+ DIRUNLINK = $(TOPDIR)/tools/unlink.sh
+ MKDEP = $(TOPDIR)/tools/mknulldeps.sh
+ ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
+ ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
+ ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/ostest/ld.script}"
+else
+ # Linux/Cygwin-native toolchain
+ MKDEP = $(TOPDIR)/tools/mkdeps.sh
+ ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
+ ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
+ ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/ostest/ld.script
+endif
+
+CC = $(CROSSDEV)gcc
+CXX = $(CROSSDEV)g++
+CPP = $(CROSSDEV)gcc -E
+LD = $(CROSSDEV)ld
+AR = $(CROSSDEV)ar rcs
+NM = $(CROSSDEV)nm
+OBJCOPY = $(CROSSDEV)objcopy
+OBJDUMP = $(CROSSDEV)objdump
+
+ifeq ("${CONFIG_DEBUG_SYMBOLS}","y")
+ ARCHOPTIMIZATION = -g
+else
+ ARCHOPTIMIZATION = $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
+endif
+
+ARCHCFLAGS = -fno-builtin
+ARCHCXXFLAGS = -fno-builtin -fno-exceptions
+ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow
+ARCHWARNINGSXX = -Wall -Wshadow
+ARCHDEFINES =
+
+CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
+AFLAGS = $(CFLAGS) -D__ASSEMBLY__
+
+NXFLATLDFLAGS1 = -r -d -warn-common
+NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat.ld -no-check-sections
+LDNXFLATFLAGS = -e main -s 2048
+
+OBJEXT = .o
+LIBEXT = .a
+EXEEXT =
+
+define PREPROCESS
+ @echo "CPP: $1->$2"
+ @$(CPP) $(CPPFLAGS) $1 -o $2
+endef
+
+define COMPILE
+ @echo "CC: $1"
+ @$(CC) -c $(CFLAGS) $1 -o $2
+endef
+
+define COMPILEXX
+ @echo "CXX: $1"
+ @$(CXX) -c $(CXXFLAGS) $1 -o $2
+endef
+
+define ASSEMBLE
+ @echo "AS: $1"
+ @$(CC) -c $(AFLAGS) $1 -o $2
+endef
+
+define ARCHIVE
+ echo "AR: $2"; \
+ $(AR) $1 $2 || { echo "$(AR) $1 $2 FAILED!" ; exit 1 ; }
+endef
+
+define CLEAN
+ @rm -f *.o *.a
+endef
+
+HOSTCC = gcc
+HOSTINCLUDES = -I.
+HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -g -pipe
+HOSTLDFLAGS =
+
diff --git a/configs/pic32-starterkit/ostest/appconfig b/configs/pic32-starterkit/ostest/appconfig
new file mode 100644
index 0000000000000000000000000000000000000000..0f7fb6876d14ce901b481f74a7d84e80a99a020b
--- /dev/null
+++ b/configs/pic32-starterkit/ostest/appconfig
@@ -0,0 +1,39 @@
+############################################################################
+# configs/pic32-starterkit/ostest/appconfig
+#
+# Copyright (C) 2011 Gregory Nutt. All rights reserved.
+# Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+# used to endorse or promote products derived from this software
+# without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+# Path to example in apps/examples containing the user_start entry point
+
+CONFIGURED_APPS += examples/ostest
+
diff --git a/configs/pic32-starterkit/ostest/defconfig b/configs/pic32-starterkit/ostest/defconfig
new file mode 100644
index 0000000000000000000000000000000000000000..f88505a5c09826390dbc5bac0e87a38929efd013
--- /dev/null
+++ b/configs/pic32-starterkit/ostest/defconfig
@@ -0,0 +1,872 @@
+############################################################################
+# configs/pic32-starterkit/ostest/defconfig
+#
+# Copyright (C) 2011 Gregory Nutt. All rights reserved.
+# Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+# used to endorse or promote products derived from this software
+# without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+#
+# architecture selection
+#
+# CONFIG_ARCH - identifies the arch subdirectory and, hence, the
+# processor architecture.
+# CONFIG_ARCH_family - for use in C code. This identifies the
+# particular chip family that the architecture is implemented
+# in.
+# CONFIG_ARCH_architecture - for use in C code. This identifies the
+# specific architecture within the chip family.
+# CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
+# CONFIG_ARCH_CHIP_name - For use in C code
+# CONFIG_ARCH_BOARD - identifies the configs subdirectory and, hence,
+# the board that supports the particular chip or SoC.
+# CONFIG_ARCH_BOARD_name - for use in C code
+# CONFIG_ENDIAN_BIG - define if big endian (default is little endian)
+# NOTE: The PIC32MX is always little endian.
+# CONFIG_BOARD_LOOPSPERMSEC - for delay loops
+# CONFIG_DRAM_SIZE - Describes the installed DRAM.
+# CONFIG_DRAM_START - The start address of DRAM (physical)
+# CONFIG_DRAM_END - Last address+1 of installed RAM
+# CONFIG_ARCH_IRQPRIO - The PIC32MX supports interrupt prioritization
+# CONFIG_ARCH_INTERRUPTSTACK - This architecture supports an interrupt
+# stack. If defined, this symbol is the size of the interrupt
+# stack in bytes. If not defined, the user task stacks will be
+# used during interrupt handling.
+# CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
+# CONFIG_ARCH_BOOTLOADER - Set if you are using a bootloader.
+# CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to board architecture.
+# CONFIG_ARCH_BUTTONS - Enable support for buttons. Unique to board architecture.
+# CONFIG_ARCH_CALIBRATION - Enables some build in instrumentation that
+# cause a 100 second delay during boot-up. This 100 second delay
+# serves no purpose other than it allows you to calibrate
+# CONFIG_BOARD_LOOPSPERMSEC. You simply use a stop watch to measure
+# the 100 second delay then adjust CONFIG_BOARD_LOOPSPERMSEC until
+# the delay actually is 100 seconds.
+# CONFIG_ARCH_DMA - Support DMA initialization
+#
+CONFIG_ARCH=mips
+CONFIG_ARCH_MIPS=y
+CONFIG_ARCH_MIPS32=y
+CONFIG_ARCH_CHIP=pic32mx
+CONFIG_ARCH_CHIP_PIC32MX795F512L=y
+CONFIG_ARCH_BOARD=pic32-starterkit
+CONFIG_ARCH_BOARD_PIC32_STARTERKIT=y
+CONFIG_BOARD_LOOPSPERMSEC=8079
+CONFIG_DRAM_SIZE=(32*1024)
+CONFIG_DRAM_START=0xa0000000
+CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE)
+CONFIG_ARCH_IRQPRIO=y
+CONFIG_ARCH_INTERRUPTSTACK=n
+CONFIG_ARCH_STACKDUMP=y
+CONFIG_ARCH_BOOTLOADER=n
+CONFIG_ARCH_LEDS=n
+CONFIG_ARCH_BUTTONS=n
+CONFIG_ARCH_CALIBRATION=n
+CONFIG_ARCH_DMA=n
+
+#
+# Identify toolchain and linker options
+#
+CONFIG_PIC32MX_MICROCHIPW=n
+CONFIG_PIC32MX_MICROCHIPL=n
+CONFIG_PIC32MX_MICROCHIPW_LITE=y
+CONFIG_PIC32MX_MICROCHIPL_LITE=n
+
+#
+# Individual subsystems can be enabled:
+#
+
+CONFIG_PIC32MX_WDT=n
+CONFIG_PIC32MX_RTCC=n
+CONFIG_PIC32MX_TIMER1=n
+CONFIG_PIC32MX_TIMER2=n
+CONFIG_PIC32MX_TIMER3=n
+CONFIG_PIC32MX_TIMER4=n
+CONFIG_PIC32MX_TIMER5=n
+CONFIG_PIC32MX_IC1=n
+CONFIG_PIC32MX_IC2=n
+CONFIG_PIC32MX_IC3=n
+CONFIG_PIC32MX_IC4=n
+CONFIG_PIC32MX_IC5=n
+CONFIG_PIC32MX_OC1=n
+CONFIG_PIC32MX_OC2=n
+CONFIG_PIC32MX_OC3=n
+CONFIG_PIC32MX_OC4=n
+CONFIG_PIC32MX_OC5=n
+CONFIG_PIC32MX_I2C1=n
+CONFIG_PIC32MX_I2C2=n
+CONFIG_PIC32MX_SPI2=n
+CONFIG_PIC32MX_UART1=n
+CONFIG_PIC32MX_UART2=y
+CONFIG_PIC32MX_PMP=n
+CONFIG_PIC32MX_ADC=n
+CONFIG_PIC32MX_CVR=n
+CONFIG_PIC32MX_CM1=n
+CONFIG_PIC32MX_CM2=n
+CONFIG_PIC32MX_OSC=y
+CONFIG_PIC32MX_DDP=n
+CONFIG_PIC32MX_FLASH=n
+CONFIG_PIC32MX_BMX=n
+CONFIG_PIC32MX_DMA=n
+CONFIG_PIC32MX_CHE=n
+CONFIG_PIC32MX_USBDEV=n
+CONFIG_PIC32MX_USBHOST=n
+CONFIG_PIC32MX_IOPORTA=y
+CONFIG_PIC32MX_IOPORTB=y
+CONFIG_PIC32MX_IOPORTC=y
+CONFIG_PIC32MX_IOPORTD=y
+CONFIG_PIC32MX_IOPORTE=y
+CONFIG_PIC32MX_IOPORTF=y
+CONFIG_PIC32MX_IOPORTG=y
+
+#
+# PIC32MX Configuration Settings
+#
+# DEVCFG0:
+# CONFIG_PIC32MX_DEBUGGER - Background Debugger Enable. Default 3 (disabled). The
+# value 2 enables.
+# CONFIG_PIC32MX_ICESEL - In-Circuit Emulator/Debugger Communication Channel Select
+# Default 1 (PG2)
+# CONFIG_PIC32MX_PROGFLASHWP - Program FLASH write protect. Default 0xff (disabled)
+# CONFIG_PIC32MX_BOOTFLASHWP - Default 1 (disabled)
+# CONFIG_PIC32MX_CODEWP - Default 1 (disabled)
+# DEVCFG1: (All settings determined by selections in board.h)
+# DEVCFG2: (All settings determined by selections in board.h)
+# DEVCFG3:
+# CONFIG_PIC32MX_USBIDO - USB USBID Selection. Default 1 if USB enabled
+# (USBID pin is controlled by the USB module), but 0 (GPIO) otherwise.
+# CONFIG_PIC32MX_VBUSIO - USB VBUSON Selection (Default 1 if USB enabled
+# (VBUSON pin is controlled by the USB module, but 0 (GPIO) otherwise.
+# CONFIG_PIC32MX_WDENABLE - Enabled watchdog on power up. Default 0 (watchdog
+# can be enabled later by software).
+#
+CONFIG_PIC32MX_DEBUGGER=2
+CONFIG_PIC32MX_ICESEL=0
+
+#
+# PIC32MX specific serial device driver settings
+#
+# CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the
+# console and ttys0 (default is the UART1).
+# CONFIG_UARTn_RXBUFSIZE - Characters are buffered as received.
+# This specific the size of the receive buffer
+# CONFIG_UARTn_TXBUFSIZE - Characters are buffered before
+# being sent. This specific the size of the transmit buffer
+# CONFIG_UARTn_BAUD - The configure BAUD of the UART. Must be
+# CONFIG_UARTn_BITS - The number of bits. Must be either 7 or 8.
+# CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity
+# CONFIG_UARTn_2STOP - Two stop bits
+#
+CONFIG_UART1_SERIAL_CONSOLE=n
+CONFIG_UART2_SERIAL_CONSOLE=y
+
+CONFIG_UART1_TXBUFSIZE=256
+CONFIG_UART2_TXBUFSIZE=256
+
+CONFIG_UART1_RXBUFSIZE=256
+CONFIG_UART2_RXBUFSIZE=256
+
+CONFIG_UART1_BAUD=115200
+CONFIG_UART2_BAUD=115200
+
+CONFIG_UART1_BITS=8
+CONFIG_UART2_BITS=8
+
+CONFIG_UART1_PARITY=0
+CONFIG_UART2_PARITY=0
+
+CONFIG_UART1_2STOP=0
+CONFIG_UART2_2STOP=0
+
+#
+# General build options
+#
+# CONFIG_RRLOAD_BINARY - make the rrload binary format used with
+# BSPs from www.ridgerun.com using the tools/mkimage.sh script
+# CONFIG_INTELHEX_BINARY - make the Intel HEX binary format
+# used with many different loaders using the GNU objcopy program
+# Should not be selected if you are not using the GNU toolchain.
+# CONFIG_MOTOROLA_SREC - make the Motorola S-Record binary format
+# used with many different loaders using the GNU objcopy program
+# Should not be selected if you are not using the GNU toolchain.
+# CONFIG_RAW_BINARY - make a raw binary format file used with many
+# different loaders using the GNU objcopy program. This option
+# should not be selected if you are not using the GNU toolchain.
+# CONFIG_HAVE_LIBM - toolchain supports libm.a
+#
+CONFIG_RRLOAD_BINARY=n
+CONFIG_INTELHEX_BINARY=y
+CONFIG_MOTOROLA_SREC=n
+CONFIG_RAW_BINARY=n
+CONFIG_HAVE_LIBM=n
+
+#
+# General OS setup
+#
+# CONFIG_APPS_DIR - Identifies the relative path to the directory
+# that builds the application to link with NuttX. Default: ../apps
+# CONFIG_DEBUG - enables built-in debug options
+# CONFIG_DEBUG_VERBOSE - enables verbose debug output
+# CONFIG_DEBUG_SYMBOLS - build without optimization and with
+# debug symbols (needed for use with a debugger).
+# CONFIG_MM_REGIONS - If the architecture includes multiple
+# regions of memory to allocate from, this specifies the
+# number of memory regions that the memory manager must
+# handle and enables the API mm_addregion(start, end);
+# CONFIG_ARCH_LOWPUTC - architecture supports low-level, boot
+# time console output
+# CONFIG_MSEC_PER_TICK - The default system timer is 100Hz
+# or MSEC_PER_TICK=10. This setting may be defined to
+# inform NuttX that the processor hardware is providing
+# system timer interrupts at some interrupt interval other
+# than 10 msec.
+# CONFIG_RR_INTERVAL - The round robin timeslice will be set
+# this number of milliseconds; Round robin scheduling can
+# be disabled by setting this value to zero.
+# CONFIG_SCHED_INSTRUMENTATION - enables instrumentation in
+# scheduler to monitor system performance
+# CONFIG_TASK_NAME_SIZE - Spcifies that maximum size of a
+# task name to save in the TCB. Useful if scheduler
+# instrumentation is selected. Set to zero to disable.
+# CONFIG_START_YEAR, CONFIG_START_MONTH, CONFIG_START_DAY -
+# Used to initialize the internal time logic.
+# CONFIG_GREGORIAN_TIME - Enables Gregorian time conversions.
+# You would only need this if you are concerned about accurate
+# time conversions in the past or in the distant future.
+# CONFIG_JULIAN_TIME - Enables Julian time conversions. You
+# would only need this if you are concerned about accurate
+# time conversion in the distand past. You must also define
+# CONFIG_GREGORIAN_TIME in order to use Julian time.
+# CONFIG_DEV_CONSOLE - Set if architecture-specific logic
+# provides /dev/console. Enables stdout, stderr, stdin.
+# CONFIG_DEV_LOWCONSOLE - Use the simple, low-level serial console
+# driver (minimul support)
+# CONFIG_MUTEX_TYPES: Set to enable support for recursive and
+# errorcheck mutexes. Enables pthread_mutexattr_settype().
+# CONFIG_PRIORITY_INHERITANCE : Set to enable support for priority
+# inheritance on mutexes and semaphores.
+# CONFIG_SEM_PREALLOCHOLDERS: This setting is only used if priority
+# inheritance is enabled. It defines the maximum number of
+# different threads (minus one) that can take counts on a
+# semaphore with priority inheritance support. This may be
+# set to zero if priority inheritance is disabled OR if you
+# are only using semaphores as mutexes (only one holder) OR
+# if no more than two threads participate using a counting
+# semaphore.
+# CONFIG_SEM_NNESTPRIO. If priority inheritance is enabled,
+# then this setting is the maximum number of higher priority
+# threads (minus 1) than can be waiting for another thread
+# to release a count on a semaphore. This value may be set
+# to zero if no more than one thread is expected to wait for
+# a semaphore.
+# CONFIG_FDCLONE_DISABLE. Disable cloning of all file descriptors
+# by task_create() when a new task is started. If set, all
+# files/drivers will appear to be closed in the new task.
+# CONFIG_FDCLONE_STDIO. Disable cloning of all but the first
+# three file descriptors (stdin, stdout, stderr) by task_create()
+# when a new task is started. If set, all files/drivers will
+# appear to be closed in the new task except for stdin, stdout,
+# and stderr.
+# CONFIG_SDCLONE_DISABLE. Disable cloning of all socket
+# desciptors by task_create() when a new task is started. If
+# set, all sockets will appear to be closed in the new task.
+# CONFIG_SCHED_WORKQUEUE. Create a dedicated "worker" thread to
+# handle delayed processing from interrupt handlers. This feature
+# is required for some drivers but, if there are not complaints,
+# can be safely disabled. The worker thread also performs
+# garbage collection -- completing any delayed memory deallocations
+# from interrupt handlers. If the worker thread is disabled,
+# then that clean will be performed by the IDLE thread instead
+# (which runs at the lowest of priority and may not be appropriate
+# if memory reclamation is of high priority). If CONFIG_SCHED_WORKQUEUE
+# is enabled, then the following options can also be used:
+# CONFIG_SCHED_WORKPRIORITY - The execution priority of the worker
+# thread. Default: 50
+# CONFIG_SCHED_WORKPERIOD - How often the worker thread checks for
+# work in units of microseconds. Default: 50*1000 (50 MS).
+# CONFIG_SCHED_WORKSTACKSIZE - The stack size allocated for the worker
+# thread. Default: CONFIG_IDLETHREAD_STACKSIZE.
+# CONFIG_SIG_SIGWORK - The signal number that will be used to wake-up
+# the worker thread. Default: 4
+#
+#CONFIG_APPS_DIR=
+CONFIG_DEBUG=n
+CONFIG_DEBUG_VERBOSE=n
+CONFIG_DEBUG_SYMBOLS=n
+CONFIG_DEBUG_SCHED=n
+CONFIG_MM_REGIONS=1
+CONFIG_ARCH_LOWPUTC=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_INSTRUMENTATION=n
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_START_YEAR=2011
+CONFIG_START_MONTH=4
+CONFIG_START_DAY=8
+CONFIG_GREGORIAN_TIME=n
+CONFIG_JULIAN_TIME=n
+CONFIG_DEV_CONSOLE=y
+CONFIG_DEV_LOWCONSOLE=y
+CONFIG_MUTEX_TYPES=n
+CONFIG_PRIORITY_INHERITANCE=n
+CONFIG_SEM_PREALLOCHOLDERS=0
+CONFIG_SEM_NNESTPRIO=0
+CONFIG_FDCLONE_DISABLE=n
+CONFIG_FDCLONE_STDIO=n
+CONFIG_SDCLONE_DISABLE=y
+CONFIG_SCHED_WORKQUEUE=n
+CONFIG_SCHED_WORKPRIORITY=50
+CONFIG_SCHED_WORKPERIOD=(50*1000)
+CONFIG_SCHED_WORKSTACKSIZE=1024
+CONFIG_SIG_SIGWORK=4
+
+#
+# Settings for nxflat
+# CONFIG_NXFLAT. Enable support for the NXFLAT binary format.
+# This format will support execution of NuttX binaries located
+# in a ROMFS filesystem (see examples/nxflat).
+# CONFIG_NXFLAT_DUMPBUFFER. Dump a most buffers that NXFFLAT deals
+# with. CONFIG_DEBUG, CONFIG_DEBUG_VERBOSE, and
+# CONFIG_DEBUG_BINFMT have to be defined or
+# CONFIG_NXFLAT_DUMPBUFFER does nothing.
+# CONFIG_SYMTAB_ORDEREDBYNAME. Select if the system symbol table
+# is ordered by symbol name
+#
+CONFIG_NXFLAT=n
+CONFIG_NXFLAT_DUMPBUFFER=n
+CONFIG_SYMTAB_ORDEREDBYNAME=y
+
+#
+# The following can be used to disable categories of
+# APIs supported by the OS. If the compiler supports
+# weak functions, then it should not be necessary to
+# disable functions unless you want to restrict usage
+# of those APIs.
+#
+# There are certain dependency relationships in these
+# features.
+#
+# o mq_notify logic depends on signals to awaken tasks
+# waiting for queues to become full or empty.
+# o pthread_condtimedwait() depends on signals to wake
+# up waiting tasks.
+#
+CONFIG_DISABLE_CLOCK=n
+CONFIG_DISABLE_POSIX_TIMERS=n
+CONFIG_DISABLE_PTHREAD=n
+CONFIG_DISABLE_SIGNALS=n
+CONFIG_DISABLE_MQUEUE=n
+CONFIG_DISABLE_MOUNTPOINT=y
+CONFIG_DISABLE_ENVIRON=y
+CONFIG_DISABLE_POLL=y
+
+#
+# Misc libc settings
+#
+# CONFIG_NOPRINTF_FIELDWIDTH - sprintf-related logic is a
+# little smaller if we do not support fieldwidthes
+#
+CONFIG_NOPRINTF_FIELDWIDTH=n
+
+#
+# Allow for architecture optimized implementations
+#
+# The architecture can provide optimized versions of the
+# following to improve system performance
+#
+CONFIG_ARCH_MEMCPY=n
+CONFIG_ARCH_MEMCMP=n
+CONFIG_ARCH_MEMMOVE=n
+CONFIG_ARCH_MEMSET=n
+CONFIG_ARCH_STRCMP=n
+CONFIG_ARCH_STRCPY=n
+CONFIG_ARCH_STRNCPY=n
+CONFIG_ARCH_STRLEN=n
+CONFIG_ARCH_STRNLEN=n
+CONFIG_ARCH_BZERO=n
+
+#
+# Sizes of configurable things (0 disables)
+#
+# CONFIG_MAX_TASKS - The maximum number of simultaneously
+# active tasks. This value must be a power of two.
+# CONFIG_MAX_TASK_ARGS - This controls the maximum number of
+# of parameters that a task may receive (i.e., maxmum value
+# of 'argc')
+# CONFIG_NPTHREAD_KEYS - The number of items of thread-
+# specific data that can be retained
+# CONFIG_NFILE_DESCRIPTORS - The maximum number of file
+# descriptors (one for each open)
+# CONFIG_NFILE_STREAMS - The maximum number of streams that
+# can be fopen'ed
+# CONFIG_NAME_MAX - The maximum size of a file name.
+# CONFIG_STDIO_BUFFER_SIZE - Size of the buffer to allocate
+# on fopen. (Only if CONFIG_NFILE_STREAMS > 0)
+# CONFIG_NUNGET_CHARS - Number of characters that can be
+# buffered by ungetc() (Only if CONFIG_NFILE_STREAMS > 0)
+# CONFIG_PREALLOC_MQ_MSGS - The number of pre-allocated message
+# structures. The system manages a pool of preallocated
+# message structures to minimize dynamic allocations
+# CONFIG_MQ_MAXMSGSIZE - Message structures are allocated with
+# a fixed payload size given by this settin (does not include
+# other message structure overhead.
+# CONFIG_MAX_WDOGPARMS - Maximum number of parameters that
+# can be passed to a watchdog handler
+# CONFIG_PREALLOC_WDOGS - The number of pre-allocated watchdog
+# structures. The system manages a pool of preallocated
+# watchdog structures to minimize dynamic allocations
+# CONFIG_PREALLOC_TIMERS - The number of pre-allocated POSIX
+# timer structures. The system manages a pool of preallocated
+# timer structures to minimize dynamic allocations. Set to
+# zero for all dynamic allocations.
+#
+CONFIG_MAX_TASKS=16
+CONFIG_MAX_TASK_ARGS=4
+CONFIG_NPTHREAD_KEYS=4
+CONFIG_NFILE_DESCRIPTORS=8
+CONFIG_NFILE_STREAMS=8
+CONFIG_NAME_MAX=32
+CONFIG_STDIO_BUFFER_SIZE=256
+CONFIG_NUNGET_CHARS=2
+CONFIG_PREALLOC_MQ_MSGS=4
+CONFIG_MQ_MAXMSGSIZE=32
+CONFIG_MAX_WDOGPARMS=2
+CONFIG_PREALLOC_WDOGS=4
+CONFIG_PREALLOC_TIMERS=4
+
+#
+# Filesystem configuration
+#
+# CONFIG_FS_FAT - Enable FAT filesystem support
+# CONFIG_FAT_SECTORSIZE - Max supported sector size
+# CONFIG_FS_ROMFS - Enable ROMFS filesystem support
+#
+CONFIG_FS_FAT=n
+CONFIG_FS_ROMFS=n
+
+#
+# SPI-based MMC/SD driver
+#
+# CONFIG_MMCSD_NSLOTS
+# Number of MMC/SD slots supported by the driver
+# CONFIG_MMCSD_READONLY
+# Provide read-only access (default is read/write)
+# CONFIG_MMCSD_SPICLOCK - Maximum SPI clock to drive MMC/SD card.
+# Default is 20MHz.
+#
+CONFIG_MMCSD_NSLOTS=1
+CONFIG_MMCSD_READONLY=n
+CONFIG_MMCSD_SPICLOCK=12500000
+
+#
+# Block driver buffering
+#
+# CONFIG_FS_READAHEAD
+# Enable read-ahead buffering
+# CONFIG_FS_WRITEBUFFER
+# Enable write buffering
+#
+CONFIG_FS_READAHEAD=n
+CONFIG_FS_WRITEBUFFER=n
+
+#
+# SDIO-based MMC/SD driver
+#
+# CONFIG_SDIO_DMA
+# SDIO driver supports DMA
+# CONFIG_MMCSD_MMCSUPPORT
+# Enable support for MMC cards
+# CONFIG_MMCSD_HAVECARDDETECT
+# SDIO driver card detection is 100% accurate
+#
+CONFIG_SDIO_DMA=n
+CONFIG_MMCSD_MMCSUPPORT=n
+CONFIG_MMCSD_HAVECARDDETECT=n
+
+#
+# TCP/IP and UDP support via uIP
+# CONFIG_NET - Enable or disable all network features
+# CONFIG_NET_IPv6 - Build in support for IPv6
+# CONFIG_NSOCKET_DESCRIPTORS - Maximum number of socket descriptors per task/thread.
+# CONFIG_NET_SOCKOPTS - Enable or disable support for socket options
+# CONFIG_NET_BUFSIZE - uIP buffer size
+# CONFIG_NET_TCP - TCP support on or off
+# CONFIG_NET_TCP_CONNS - Maximum number of TCP connections (all tasks)
+# CONFIG_NET_TCP_READAHEAD_BUFSIZE - Size of TCP read-ahead buffers
+# CONFIG_NET_NTCP_READAHEAD_BUFFERS - Number of TCP read-ahead buffers (may be zero)
+# CONFIG_NET_TCPBACKLOG - Incoming connections pend in a backlog until
+# accept() is called. The size of the backlog is selected when listen() is called.
+# CONFIG_NET_MAX_LISTENPORTS - Maximum number of listening TCP ports (all tasks)
+# CONFIG_NET_UDP - UDP support on or off
+# CONFIG_NET_UDP_CHECKSUMS - UDP checksums on or off
+# CONFIG_NET_UDP_CONNS - The maximum amount of concurrent UDP connections
+# CONFIG_NET_ICMP - ICMP ping response support on or off
+# CONFIG_NET_ICMP_PING - ICMP ping request support on or off
+# CONFIG_NET_PINGADDRCONF - Use "ping" packet for setting IP address
+# CONFIG_NET_STATISTICS - uIP statistics on or off
+# CONFIG_NET_RECEIVE_WINDOW - The size of the advertised receiver's window
+# CONFIG_NET_ARPTAB_SIZE - The size of the ARP table
+# CONFIG_NET_BROADCAST - Broadcast support
+# CONFIG_NET_FWCACHE_SIZE - number of packets to remember when looking for duplicates
+#
+CONFIG_NET=n
+CONFIG_NET_IPv6=n
+CONFIG_NSOCKET_DESCRIPTORS=0
+CONFIG_NET_SOCKOPTS=y
+CONFIG_NET_BUFSIZE=420
+CONFIG_NET_TCP=n
+CONFIG_NET_TCP_CONNS=40
+CONFIG_NET_MAX_LISTENPORTS=40
+CONFIG_NET_UDP=n
+CONFIG_NET_UDP_CHECKSUMS=y
+#CONFIG_NET_UDP_CONNS=10
+CONFIG_NET_ICMP=n
+CONFIG_NET_ICMP_PING=n
+#CONFIG_NET_PINGADDRCONF=0
+CONFIG_NET_STATISTICS=y
+#CONFIG_NET_RECEIVE_WINDOW=
+#CONFIG_NET_ARPTAB_SIZE=8
+CONFIG_NET_BROADCAST=n
+#CONFIG_NET_FWCACHE_SIZE=2
+
+#
+# UIP Network Utilities
+# CONFIG_NET_DHCP_LIGHT - Reduces size of DHCP
+# CONFIG_NET_RESOLV_ENTRIES - Number of resolver entries
+#
+CONFIG_NET_DHCP_LIGHT=n
+CONFIG_NET_RESOLV_ENTRIES=4
+
+#
+# USB Device Configuration
+#
+# CONFIG_USBDEV
+# Enables USB device support
+# CONFIG_USBDEV_ISOCHRONOUS
+# Build in extra support for isochronous endpoints
+# CONFIG_USBDEV_DUALSPEED
+# Hardware handles high and full speed operation (USB 2.0)
+# CONFIG_USBDEV_SELFPOWERED
+# Will cause USB features to indicate that the device is
+# self-powered
+# CONFIG_USBDEV_MAXPOWER
+# Maximum power consumption in mA
+# CONFIG_USBDEV_TRACE
+# Enables USB tracing for debug
+# CONFIG_USBDEV_TRACE_NRECORDS
+# Number of trace entries to remember
+#
+CONFIG_USBDEV=n
+CONFIG_USBDEV_ISOCHRONOUS=n
+CONFIG_USBDEV_DUALSPEED=n
+CONFIG_USBDEV_SELFPOWERED=y
+CONFIG_USBDEV_REMOTEWAKEUP=n
+CONFIG_USBDEV_MAXPOWER=100
+CONFIG_USBDEV_TRACE=n
+CONFIG_USBDEV_TRACE_NRECORDS=128
+
+#
+# USB Serial Device Configuration
+#
+# CONFIG_USBSER
+# Enable compilation of the USB serial driver
+# CONFIG_USBSER_EPINTIN
+# The logical 7-bit address of a hardware endpoint that supports
+# interrupt IN operation
+# CONFIG_USBSER_EPBULKOUT
+# The logical 7-bit address of a hardware endpoint that supports
+# bulk OUT operation
+# CONFIG_USBSER_EPBULKIN
+# The logical 7-bit address of a hardware endpoint that supports
+# bulk IN operation
+# # CONFIG_USBSER_NWRREQS and CONFIG_USBSER_NRDREQS
+# The number of write/read requests that can be in flight
+# CONFIG_USBSER_VENDORID and CONFIG_USBSER_VENDORSTR
+# The vendor ID code/string
+# CONFIG_USBSER_PRODUCTID and CONFIG_USBSER_PRODUCTSTR
+# The product ID code/string
+# CONFIG_USBSER_RXBUFSIZE and CONFIG_USBSER_TXBUFSIZE
+# Size of the serial receive/transmit buffers
+#
+CONFIG_USBSER=n
+CONFIG_USBSER_EPINTIN=1
+CONFIG_USBSER_EPBULKOUT=2
+CONFIG_USBSER_EPBULKIN=5
+CONFIG_USBSER_NWRREQS=4
+CONFIG_USBSER_NRDREQS=4
+CONFIG_USBSER_VENDORID=0x067b
+CONFIG_USBSER_PRODUCTID=0x2303
+CONFIG_USBSER_VENDORSTR="Nuttx"
+CONFIG_USBSER_PRODUCTSTR="USBdev Serial"
+CONFIG_USBSER_RXBUFSIZE=512
+CONFIG_USBSER_TXBUFSIZE=512
+
+#
+# USB Storage Device Configuration
+#
+# CONFIG_USBSTRG
+# Enable compilation of the USB storage driver
+# CONFIG_USBSTRG_EP0MAXPACKET
+# Max packet size for endpoint 0
+# CONFIG_USBSTRG_EPBULKOUT and CONFIG_USBSTRG_EPBULKIN
+# The logical 7-bit address of a hardware endpoints that support
+# bulk OUT and IN operations
+# CONFIG_USBSTRG_NWRREQS and CONFIG_USBSTRG_NRDREQS
+# The number of write/read requests that can be in flight
+# CONFIG_USBSTRG_BULKINREQLEN and CONFIG_USBSTRG_BULKOUTREQLEN
+# The size of the buffer in each write/read request. This
+# value needs to be at least as large as the endpoint
+# maxpacket and ideally as large as a block device sector.
+# CONFIG_USBSTRG_VENDORID and CONFIG_USBSTRG_VENDORSTR
+# The vendor ID code/string
+# CONFIG_USBSTRG_PRODUCTID and CONFIG_USBSTRG_PRODUCTSTR
+# The product ID code/string
+# CONFIG_USBSTRG_REMOVABLE
+# Select if the media is removable
+#
+CONFIG_USBSTRG=n
+CONFIG_USBSTRG_EP0MAXPACKET=64
+CONFIG_USBSTRG_EPBULKOUT=2
+CONFIG_USBSTRG_EPBULKIN=5
+CONFIG_USBSTRG_NRDREQS=2
+CONFIG_USBSTRG_NWRREQS=2
+CONFIG_USBSTRG_BULKINREQLEN=256
+CONFIG_USBSTRG_BULKOUTREQLEN=256
+CONFIG_USBSTRG_VENDORID=0x584e
+CONFIG_USBSTRG_VENDORSTR="NuttX"
+CONFIG_USBSTRG_PRODUCTID=0x5342
+CONFIG_USBSTRG_PRODUCTSTR="USBdev Storage"
+CONFIG_USBSTRG_VERSIONNO=0x0399
+CONFIG_USBSTRG_REMOVABLE=y
+
+#
+# Settings for examples/uip
+#
+CONFIG_EXAMPLE_UIP_IPADDR=(10<<24|0<<16|0<<8|2)
+CONFIG_EXAMPLE_UIP_DRIPADDR=(10<<24|0<<16|0<<8|1)
+CONFIG_EXAMPLE_UIP_NETMASK=(255<<24|255<<16|255<<8|0)
+CONFIG_EXAMPLE_UIP_DHCPC=n
+
+#
+# Settings for examples/nettest
+#
+# CONFIG_EXAMPLE_NETTEST_SERVER - The target board can act
+# as either the client side or server side of the test
+# CONFIG_EXAMPLE_NETTEST_PERFORMANCE - If set, then the
+# client side simply receives messages forever, allowing
+# measurement of throughput
+# CONFIG_EXAMPLE_NETTEST_NOMAC - Set if the hardware has
+# no MAC address; one will be assigned
+# CONFIG_EXAMPLE_NETTEST_IPADDR - Target board IP address
+# CONFIG_EXAMPLE_NETTEST_DRIPADDR - Default router address
+# CONFIG_EXAMPLE_NETTEST_NETMASK - Network mask
+# CONFIG_EXAMPLE_NETTEST_CLIENTIP - IP address of the
+# client side of the test (may be target or host)
+#
+CONFIG_EXAMPLE_NETTEST_SERVER=n
+CONFIG_EXAMPLE_NETTEST_PERFORMANCE=n
+CONFIG_EXAMPLE_NETTEST_NOMAC=y
+CONFIG_EXAMPLE_NETTEST_IPADDR=(10<<24|0<<16|0<<8|2)
+CONFIG_EXAMPLE_NETTEST_DRIPADDR=(10<<24|0<<16|0<<8|1)
+CONFIG_EXAMPLE_NETTEST_NETMASK=(255<<24|255<<16|255<<8|0)
+CONFIG_EXAMPLE_NETTEST_CLIENTIP=(10<<24|0<<16|0<<8|1)
+
+#
+# Settings for examples/ostest
+#
+CONFIG_EXAMPLES_OSTEST_LOOPS=1
+CONFIG_EXAMPLES_OSTEST_STACKSIZE=2048
+CONFIG_EXAMPLES_OSTEST_NBARRIER_THREADS=3
+
+#
+# Settings for apps/nshlib
+#
+# CONFIG_NSH_FILEIOSIZE - Size of a static I/O buffer
+# CONFIG_NSH_STRERROR - Use strerror(errno)
+# CONFIG_NSH_LINELEN - Maximum length of one command line
+# CONFIG_NSH_STACKSIZE - Stack size to use for new threads.
+# CONFIG_NSH_NESTDEPTH - Max number of nested if-then[-else]-fi
+# CONFIG_NSH_DISABLESCRIPT - Disable scripting support
+# CONFIG_NSH_DISABLEBG - Disable background commands
+# CONFIG_NSH_ROMFSETC - Use startup script in /etc
+# CONFIG_NSH_CONSOLE - Use serial console front end
+# CONFIG_NSH_TELNET - Use telnetd console front end
+# CONFIG_NSH_ARCHINIT - Platform provides architecture
+# specific initialization (nsh_archinitialize()).
+#
+# If CONFIG_NSH_TELNET is selected:
+# CONFIG_NSH_IOBUFFER_SIZE -- Telnetd I/O buffer size
+# CONFIG_NSH_DHCPC - Obtain address using DHCP
+# CONFIG_NSH_IPADDR - Provides static IP address
+# CONFIG_NSH_DRIPADDR - Provides static router IP address
+# CONFIG_NSH_NETMASK - Provides static network mask
+# CONFIG_NSH_NOMAC - Use a bogus MAC address
+#
+# If CONFIG_NSH_ROMFSETC is selected:
+# CONFIG_NSH_ROMFSMOUNTPT - ROMFS mountpoint
+# CONFIG_NSH_INITSCRIPT - Relative path to init script
+# CONFIG_NSH_ROMFSDEVNO - ROMFS RAM device minor
+# CONFIG_NSH_ROMFSSECTSIZE - ROMF sector size
+# CONFIG_NSH_FATDEVNO - FAT FS RAM device minor
+# CONFIG_NSH_FATSECTSIZE - FAT FS sector size
+# CONFIG_NSH_FATNSECTORS - FAT FS number of sectors
+# CONFIG_NSH_FATMOUNTPT - FAT FS mountpoint
+#
+CONFIG_NSH_FILEIOSIZE=512
+CONFIG_NSH_STRERROR=n
+CONFIG_NSH_LINELEN=64
+CONFIG_NSH_STACKSIZE=2048
+CONFIG_NSH_NESTDEPTH=3
+CONFIG_NSH_DISABLESCRIPT=n
+CONFIG_NSH_DISABLEBG=n
+CONFIG_NSH_ROMFSETC=n
+CONFIG_NSH_CONSOLE=y
+CONFIG_NSH_TELNET=n
+CONFIG_NSH_ARCHINIT=n
+CONFIG_NSH_IOBUFFER_SIZE=512
+CONFIG_NSH_DHCPC=n
+CONFIG_NSH_NOMAC=n
+CONFIG_NSH_IPADDR=(10<<24|0<<16|0<<8|2)
+CONFIG_NSH_DRIPADDR=(10<<24|0<<16|0<<8|1)
+CONFIG_NSH_NETMASK=(255<<24|255<<16|255<<8|0)
+CONFIG_NSH_ROMFSMOUNTPT="/etc"
+CONFIG_NSH_INITSCRIPT="init.d/rcS"
+CONFIG_NSH_ROMFSDEVNO=0
+CONFIG_NSH_ROMFSSECTSIZE=64
+CONFIG_NSH_FATDEVNO=1
+CONFIG_NSH_FATSECTSIZE=512
+CONFIG_NSH_FATNSECTORS=1024
+CONFIG_NSH_FATMOUNTPT=/tmp
+
+#
+# Architecture-specific NSH options
+#
+CONFIG_NSH_MMCSDSPIPORTNO=1
+CONFIG_NSH_MMCSDSLOTNO=0
+CONFIG_NSH_MMCSDMINOR=0
+
+#
+# Settings for examples/usbserial
+#
+# CONFIG_EXAMPLES_USBSERIAL_INONLY
+# Only verify IN (device-to-host) data transfers. Default: both
+# CONFIG_EXAMPLES_USBSERIAL_OUTONLY
+# Only verify OUT (host-to-device) data transfers. Default: both
+# CONFIG_EXAMPLES_USBSERIAL_ONLYSMALL
+# Send only small, single packet messages. Default: Send large and small.
+# CONFIG_EXAMPLES_USBSERIAL_ONLYBIG
+# Send only large, multi-packet messages. Default: Send large and small.
+#
+CONFIG_EXAMPLES_USBSERIAL_INONLY=n
+CONFIG_EXAMPLES_USBSERIAL_OUTONLY=n
+CONFIG_EXAMPLES_USBSERIAL_ONLYSMALL=n
+CONFIG_EXAMPLES_USBSERIAL_ONLYBIG=n
+
+CONFIG_EXAMPLES_USBSERIAL_TRACEINIT=n
+CONFIG_EXAMPLES_USBSERIAL_TRACECLASS=n
+CONFIG_EXAMPLES_USBSERIAL_TRACETRANSFERS=n
+CONFIG_EXAMPLES_USBSERIAL_TRACECONTROLLER=n
+CONFIG_EXAMPLES_USBSERIAL_TRACEINTERRUPTS=n
+
+#
+# Settings for examples/usbstorage
+#
+# CONFIG_EXAMPLES_USBSTRG_NLUNS
+# Defines the number of logical units (LUNs) exported by the USB storage
+# driver. Each LUN corresponds to one exported block driver (or partition
+# of a block driver). May be 1, 2, or 3. Default is 1.
+# CONFIG_EXAMPLES_USBSTRG_DEVMINOR1
+# The minor device number of the block driver for the first LUN. For
+# example, N in /dev/mmcsdN. Used for registering the block driver. Default
+# is zero.
+# CONFIG_EXAMPLES_USBSTRG_DEVPATH1
+# The full path to the registered block driver. Default is "/dev/mmcsd0"
+# CONFIG_EXAMPLES_USBSTRG_DEVMINOR2 and CONFIG_EXAMPLES_USBSTRG_DEVPATH2
+# Similar parameters that would have to be provided if CONFIG_EXAMPLES_USBSTRG_NLUNS
+# is 2 or 3. No defaults.
+# CONFIG_EXAMPLES_USBSTRG_DEVMINOR3 and CONFIG_EXAMPLES_USBSTRG_DEVPATH3
+# Similar parameters that would have to be provided if CONFIG_EXAMPLES_USBSTRG_NLUNS
+# is 3. No defaults.
+#
+# If CONFIG_USBDEV_TRACE is enabled (or CONFIG_DEBUG and CONFIG_DEBUG_USB), then
+# the example code will also manage the USB trace output. The amount of trace output
+# can be controlled using:
+#
+# CONFIG_EXAMPLES_USBSTRG_TRACEINIT
+# Show initialization events
+# CONFIG_EXAMPLES_USBSTRG_TRACECLASS
+# Show class driver events
+# CONFIG_EXAMPLES_USBSTRG_TRACETRANSFERS
+# Show data transfer events
+# CONFIG_EXAMPLES_USBSTRG_TRACECONTROLLER
+# Show controller events
+# CONFIG_EXAMPLES_USBSTRG_TRACEINTERRUPTS
+# Show interrupt-related events.
+#
+CONFIG_EXAMPLES_USBSTRG_NLUNS=1
+CONFIG_EXAMPLES_USBSTRG_DEVMINOR1=0
+CONFIG_EXAMPLES_USBSTRG_DEVPATH1="/dev/mmcsd0"
+CONFIG_EXAMPLES_USBSTRG_TRACEINIT=n
+CONFIG_EXAMPLES_USBSTRG_TRACECLASS=n
+CONFIG_EXAMPLES_USBSTRG_TRACETRANSFERS=n
+CONFIG_EXAMPLES_USBSTRG_TRACECONTROLLER=n
+CONFIG_EXAMPLES_USBSTRG_TRACEINTERRUPTS=n
+
+#
+# Stack and heap information
+#
+# CONFIG_BOOT_RUNFROMFLASH - Some configurations support XIP
+# operation from FLASH but must copy initialized .data sections to RAM.
+# (should also be =n for the PIC32MX which always runs from flash)
+# CONFIG_BOOT_COPYTORAM - Some configurations boot in FLASH
+# but copy themselves entirely into RAM for better performance.
+# CONFIG_CUSTOM_STACK - The up_ implementation will handle
+# all stack operations outside of the nuttx model.
+# CONFIG_STACK_POINTER - The initial stack pointer (arm7tdmi only)
+# CONFIG_IDLETHREAD_STACKSIZE - The size of the initial stack.
+# This is the thread that (1) performs the inital boot of the system up
+# to the point where user_start() is spawned, and (2) there after is the
+# IDLE thread that executes only when there is no other thread ready to
+# run.
+# CONFIG_USERMAIN_STACKSIZE - The size of the stack to allocate
+# for the main user thread that begins at the user_start() entry point.
+# CONFIG_PTHREAD_STACK_MIN - Minimum pthread stack size
+# CONFIG_PTHREAD_STACK_DEFAULT - Default pthread stack size
+# CONFIG_HEAP_BASE - The beginning of the heap
+# CONFIG_HEAP_SIZE - The size of the heap
+#
+CONFIG_BOOT_RUNFROMFLASH=n
+CONFIG_BOOT_COPYTORAM=n
+CONFIG_CUSTOM_STACK=n
+CONFIG_STACK_POINTER=
+CONFIG_IDLETHREAD_STACKSIZE=1024
+CONFIG_USERMAIN_STACKSIZE=2048
+CONFIG_PTHREAD_STACK_MIN=256
+CONFIG_PTHREAD_STACK_DEFAULT=2048
+CONFIG_HEAP_BASE=
+CONFIG_HEAP_SIZE=
diff --git a/configs/pic32-starterkit/ostest/ld.script b/configs/pic32-starterkit/ostest/ld.script
new file mode 100644
index 0000000000000000000000000000000000000000..255e48a4f77ab66ee52f9d35e89bb287b36e64c9
--- /dev/null
+++ b/configs/pic32-starterkit/ostest/ld.script
@@ -0,0 +1,305 @@
+/****************************************************************************
+ * configs/pic32-starterkit/ostest/ld.script
+ *
+ * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+/* Memory Regions ***********************************************************/
+
+MEMORY
+{
+ /* The PIC32MX440F512H has 512Kb of program FLASH at physical address
+ * 0x1d000000 but is always accessed at KSEG0 address 0x9d00:0000
+ */
+
+ kseg0_progmem (rx) : ORIGIN = 0x9d000000, LENGTH = 512K
+
+ /* The PIC32MX440F512H has 12Kb of boot FLASH at physical address
+ * 0x1fc00000. The initial reset vector is in KSEG1, but all other
+ * accesses are in KSEG0.
+ *
+ * REGION PHYSICAL KSEG SIZE
+ * DESCRIPTION START ADDR (BYTES)
+ * ------------- ---------- ------ ----------------------
+ * Exceptions:*
+ * Reset 0x1fc00000 KSEG1 512 512
+ * TLB Refill 0x1fc00200 KSEG1 256 768
+ * Cache Error 0x1fc00300 KSEG1 128 896
+ * Others 0x1fc00380 KSEG1 128 1024 (1Kb)
+ * Interrupt 0x1fc00400 KSEG1 128 1152
+ * JTAG 0x1fc00480 KSEG1 16 1168
+ * Exceptions 0x1fc00490 KSEG0 8192-1168 8192 (4Kb)
+ * Debug code 0x1fc02000 KSEG1 4096-16 12272
+ * DEVCFG3-0 0x1fc02ff0 KSEG1 16 12288 (12Kb)
+ *
+ * Exceptions assme:
+ *
+ * STATUS: BEV=1 and EXL=0
+ * CAUSE: IV=1
+ * JTAG: ProbEn=0
+ * And multi-vector support disabled
+ */
+
+ kseg1_reset (rx) : ORIGIN = 0xbfc00000, LENGTH = 896
+ kseg1_bevexcpt (rx) : ORIGIN = 0xbfc00380, LENGTH = 128
+ kseg1_intexcpt (rx) : ORIGIN = 0xbfc00400, LENGTH = 128
+ kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00480, LENGTH = 16
+ kseg0_bootmem (rx) : ORIGIN = 0x9fc00490, LENGTH = 8192-1168
+ kseg1_dbgcode (rx) : ORIGIN = 0xbfc02000, LENGTH = 4096-16
+ kseg1_devcfg (r) : ORIGIN = 0xbfc02ff0, LENGTH = 16
+
+ /* The PIC32MX440F512H has 32Kb of data memory at physical address
+ * 0x00000000. Since the PIC32MX has no data cache, this memory is
+ * always accessed through KSEG1.
+ */
+
+ kseg1_datamem (w!x) : ORIGIN = 0xa0000000, LENGTH = 32K
+}
+
+OUTPUT_FORMAT("elf32-tradlittlemips")
+OUTPUT_ARCH(pic32mx)
+ENTRY(__start)
+
+SECTIONS
+{
+ /* Boot FLASH sections */
+
+ .reset :
+ {
+ KEEP (*(.reset))
+ } > kseg1_reset
+
+ /* Exception handlers. The following is assumed:
+ *
+ * STATUS: BEV=1 and EXL=0
+ * CAUSE: IV=1
+ * JTAG: ProbEn=0
+ * And multi-vector support disabled
+ *
+ * In that configuration, the vector locations become:
+ *
+ * Reset, Soft Reset bfc0:0000
+ * TLB Refill bfc0:0200
+ * Cache Error bfc0:0300
+ * All others bfc0:0380
+ * Interrupt bfc0:0400
+ * EJTAG Debug bfc0:0480
+ */
+
+ /* KSEG1 exception handler "trampolines" */
+
+ .bev_excpt :
+ {
+ KEEP (*(.bev_excpt))
+ } > kseg1_bevexcpt
+
+ .int_excpt :
+ {
+ KEEP (*(.int_excpt))
+ } > kseg1_intexcpt
+
+ .dbg_excpt = ORIGIN(kseg1_dbgexcpt);
+
+ .start :
+ {
+ /* KSEG0 Reset startup logic */
+
+ *(.start)
+
+ /* KSEG0 exception handlers */
+
+ *(.nmi_handler)
+ *(.bev_handler)
+ *(.int_handler)
+ } > kseg0_bootmem
+
+ .dbg_code = ORIGIN(kseg1_dbgcode);
+
+ .devcfg :
+ {
+ KEEP (*(.devcfg))
+ } > kseg1_devcfg
+
+ /* Program FLASH sections */
+
+ .text :
+ {
+ _stext = ABSOLUTE(.);
+ *(.text .text.*)
+ *(.stub)
+ KEEP (*(.text.*personality*))
+ *(.gnu.linkonce.t.*)
+ *(.gnu.warning)
+ *(.mips16.fn.*)
+ *(.mips16.call.*)
+
+ /* Read-only data is included in the text section */
+
+ *(.rodata .rodata.*)
+ *(.rodata1)
+ *(.gnu.linkonce.r.*)
+
+ /* Small initialized constant global and static data */
+
+ *(.sdata2 .sdata2.*)
+ *(.gnu.linkonce.s2.*)
+
+ /* Uninitialized constant global and static data */
+
+ *(.sbss2 .sbss2.*)
+ *(.gnu.linkonce.sb2.*)
+ _etext = ABSOLUTE(.);
+ } > kseg0_progmem
+
+ /* Initialization data begins here in progmem */
+
+ _data_loaddr = LOADADDR(.data);
+
+ .eh_frame_hdr : { *(.eh_frame_hdr) }
+ .eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
+
+ /* RAM functions are positioned at the beginning of RAM so that
+ * they can be guaranteed to satisfy the 2Kb alignment requirement.
+ */
+/*
+ .ramfunc ALIGN(2K) :
+ {
+ _sramfunc = ABSOLUTE(.);
+ *(.ramfunc .ramfunc.*)
+ _eramfunc = ABSOLUTE(.);
+ } > kseg1_datamem AT > kseg0_progmem
+
+ _ramfunc_loadaddr = LOADADDR(.ramfunc);
+ _ramfunc_sizeof = SIZEOF(.ramfunc);
+ _bmxdkpba_address = _sramfunc - ORIGIN(kseg1_datamem) ;
+ _bmxdudba_address = LENGTH(kseg1_datamem) ;
+ _bmxdupba_address = LENGTH(kseg1_datamem) ;
+*/
+ .dbg_data (NOLOAD) :
+ {
+ . += (DEFINED (_DEBUGGER) ? 0x200 : 0x0);
+ } > kseg1_datamem
+
+ .data :
+ {
+ _sdata = ABSOLUTE(.);
+ *(.data .data.*)
+ *(.gnu.linkonce.d.*)
+ KEEP (*(.gnu.linkonce.d.*personality*))
+ *(.data1)
+ } > kseg1_datamem AT > kseg0_progmem
+
+ .eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) }
+ _gp = ALIGN(16) + 0x7FF0 ;
+
+ .got :
+ {
+ *(.got.plt) *(.got)
+ } > kseg1_datamem AT > kseg0_progmem
+
+ .sdata :
+ {
+ *(.sdata .sdata.* .gnu.linkonce.s.*)
+ } > kseg1_datamem AT > kseg0_progmem
+
+ .lit8 :
+ {
+ *(.lit8)
+ } > kseg1_datamem AT > kseg0_progmem
+
+ .lit4 :
+ {
+ *(.lit4)
+ _edata = ABSOLUTE(.);
+ } >kseg1_datamem AT>kseg0_progmem
+
+ .sbss :
+ {
+ _sbss = ABSOLUTE(.);
+ *(.dynsbss)
+ *(.sbss .sbss.* .gnu.linkonce.sb.*)
+ *(.scommon)
+ } >kseg1_datamem
+
+ .bss :
+ {
+ *(.dynbss)
+ *(.bss .bss.*)
+ *(.gnu.linkonce.b.*)
+ *(COMMON)
+ _ebss = ABSOLUTE(.);
+ } > kseg1_datamem
+
+ /* Stabs debugging sections */
+
+ .stab 0 : { *(.stab) }
+ .stabstr 0 : { *(.stabstr) }
+ .stab.excl 0 : { *(.stab.excl) }
+ .stab.exclstr 0 : { *(.stab.exclstr) }
+ .stab.index 0 : { *(.stab.index) }
+ .stab.indexstr 0 : { *(.stab.indexstr) }
+ .comment 0 : { *(.comment) }
+
+ /* DWARF debug sections */
+ /* DWARF 1 */
+
+ .debug 0 : { *(.debug) }
+ .line 0 : { *(.line) }
+
+ /* GNU DWARF 1 extensions */
+
+ .debug_srcinfo 0 : { *(.debug_srcinfo) }
+ .debug_sfnames 0 : { *(.debug_sfnames) }
+
+ /* DWARF 1.1 and DWARF 2 */
+
+ .debug_aranges 0 : { *(.debug_aranges) }
+ .debug_pubnames 0 : { *(.debug_pubnames) }
+
+ /* DWARF 2 */
+
+ .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
+ .debug_abbrev 0 : { *(.debug_abbrev) }
+ .debug_line 0 : { *(.debug_line) }
+ .debug_frame 0 : { *(.debug_frame) }
+ .debug_str 0 : { *(.debug_str) }
+ .debug_loc 0 : { *(.debug_loc) }
+ .debug_macinfo 0 : { *(.debug_macinfo) }
+
+ /* SGI/MIPS DWARF 2 extensions */
+
+ .debug_weaknames 0 : { *(.debug_weaknames) }
+ .debug_funcnames 0 : { *(.debug_funcnames) }
+ .debug_typenames 0 : { *(.debug_typenames) }
+ .debug_varnames 0 : { *(.debug_varnames) }
+
+ /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/configs/pic32-starterkit/ostest/setenv.sh b/configs/pic32-starterkit/ostest/setenv.sh
new file mode 100755
index 0000000000000000000000000000000000000000..9a852dde5b8d5875718c7b25bfbfb521230babea
--- /dev/null
+++ b/configs/pic32-starterkit/ostest/setenv.sh
@@ -0,0 +1,61 @@
+#!/bin/bash
+# configs/pic32-starterkit/ostest/setenv.sh
+#
+# Copyright (C) 2011 Gregory Nutt. All rights reserved.
+# Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+# used to endorse or promote products derived from this software
+# without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+if [ "$_" = "$0" ] ; then
+ echo "You must source this script, not run it!" 1>&2
+ exit 1
+fi
+
+if [ -z "${PATH_ORIG}" ]; then export PATH_ORIG="${PATH}"; fi
+
+WD=`pwd`
+if [ ! -x "setenv.sh" ]; then
+ echo "This script must be executed from the top-level NuttX build directory"
+ exit 1
+fi
+
+# This the Cygwin path to the location where I installed the MicroChip
+# PIC32MX toolchain under windows. This is *not* the default install
+# location so you will probably have to edit this. You will also have
+# to edit this if you install a different version of if you install
+# the Linux PIC32MX toolchain as well
+export TOOLCHAIN_BIN="/cygdrive/c/MicroChip/mplabc32/v1.12/bin"
+
+# This is the path to the toosl subdirectory
+export PIC32TOOL_DIR="${WD}/configs/pic32-starterkit/tools"
+
+# Add the path to the toolchain to the PATH varialble
+export PATH="${TOOLCHAIN_BIN}:${PIC32TOOL_DIR}:/sbin:/usr/sbin:${PATH_ORIG}"
+
+echo "PATH : ${PATH}"
diff --git a/configs/pic32-starterkit/src/Makefile b/configs/pic32-starterkit/src/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..366cb9412a0aa80f6003825d39dbd0cc9a514f5f
--- /dev/null
+++ b/configs/pic32-starterkit/src/Makefile
@@ -0,0 +1,92 @@
+############################################################################
+# configs/pic32-starterkit/src/Makefile
+#
+# Copyright (C) 2011 Gregory Nutt. All rights reserved.
+# Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+# used to endorse or promote products derived from this software
+# without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+-include $(TOPDIR)/Make.defs
+
+CFLAGS += -I$(TOPDIR)/sched
+
+ASRCS =
+CSRCS = up_boot.c up_spi.c
+
+ifeq ($(CONFIG_ARCH_LEDS),y)
+CSRCS += up_leds.c
+endif
+
+ifeq ($(CONFIG_NSH_ARCHINIT),y)
+CSRCS += up_nsh.c
+endif
+
+AOBJS = $(ASRCS:.S=$(OBJEXT))
+COBJS = $(CSRCS:.c=$(OBJEXT))
+
+SRCS = $(ASRCS) $(CSRCS)
+OBJS = $(AOBJS) $(COBJS)
+
+ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src
+ifeq ($(WINTOOL),y)
+ CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" \
+ -I "${shell cygpath -w $(ARCH_SRCDIR)/common}" \
+ -I "${shell cygpath -w $(ARCH_SRCDIR)/mips32}"
+else
+ CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(ARCH_SRCDIR)/mips32
+endif
+
+all: libboard$(LIBEXT)
+
+$(AOBJS): %$(OBJEXT): %.S
+ $(call ASSEMBLE, $<, $@)
+
+$(COBJS) $(LINKOBJS): %$(OBJEXT): %.c
+ $(call COMPILE, $<, $@)
+
+libboard$(LIBEXT): $(OBJS)
+ @( for obj in $(OBJS) ; do \
+ $(call ARCHIVE, $@, $${obj}); \
+ done ; )
+
+.depend: Makefile $(SRCS)
+ @$(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep
+ @touch $@
+
+depend: .depend
+
+clean:
+ @rm -f libboard$(LIBEXT) *~ .*.swp
+ $(call CLEAN)
+
+distclean: clean
+ @rm -f Make.dep .depend
+
+-include Make.dep
diff --git a/configs/pic32-starterkit/src/starterkit_internal.h b/configs/pic32-starterkit/src/starterkit_internal.h
new file mode 100644
index 0000000000000000000000000000000000000000..5fc26caaa22cd1ab330089a70db7762034488d1b
--- /dev/null
+++ b/configs/pic32-starterkit/src/starterkit_internal.h
@@ -0,0 +1,110 @@
+/****************************************************************************
+ * configs/pic32-starterkit/src/starterkit_internal.h
+ *
+ * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __CONFIGS_PIC32_STARTERKIT_SRC_STARTERKIT_INTERNAL_H
+#define __CONFIGS_PIC32_STARTERKIT_SRC_STARTERKIT_INTERNAL_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+/****************************************************************************
+ * Pre-Processor Definitions
+ ****************************************************************************/
+/* Configuration ************************************************************/
+
+/* The Sure PIC32MX board has five LEDs. One (D4, lablel "Power") is not
+ * controllable by software. Four are controllable by software:
+ *
+ * D7 "USB" Yellow RD7 Low illuminates
+ * D8 "SD" Yellow RD6 Low illuminates
+ * D9 "Flash" Yellow RF0 Low illuminates
+ * D10 "Error" Red RF1 Low illuminates
+ */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Inline Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Name: pic32mx_spiinitialize
+ *
+ * Description:
+ * Called to configure SPI chip select GPIO pins for the PCB Logic board.
+ *
+ ************************************************************************************/
+
+#if defined(CONFIG_PIC32MX_SPI2)
+EXTERN void weak_function pic32mx_spiinitialize(void);
+#endif
+
+/************************************************************************************
+ * Name: pic32mx_ledinit
+ *
+ * Description:
+ * Configure on-board LEDs if LED support has been selected.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_ARCH_LEDS
+EXTERN void pic32mx_ledinit(void);
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __CONFIGS_PIC32_STARTERKIT_SRC_STARTERKIT_INTERNAL_H */
diff --git a/configs/pic32-starterkit/src/up_boot.c b/configs/pic32-starterkit/src/up_boot.c
new file mode 100644
index 0000000000000000000000000000000000000000..5a88a98b74d431427778f26bda280ef965bc26e8
--- /dev/null
+++ b/configs/pic32-starterkit/src/up_boot.c
@@ -0,0 +1,93 @@
+/************************************************************************************
+ * configs/pic32-starterkit/src/up_boot.c
+ * arch/mips/src/board/up_boot.c
+ *
+ * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <debug.h>
+
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "up_internal.h"
+
+#include "pic32mx-internal.h"
+#include "starterkit_internal.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: pic32mx_boardinitialize
+ *
+ * Description:
+ * All PIC32MX architectures must provide the following entry point. This entry
+ * point is called early in the intitialization -- after all memory has been
+ * configured and mapped but before any devices have been initialized.
+ *
+ ************************************************************************************/
+
+void pic32mx_boardinitialize(void)
+{
+ /* Configure SPI chip selects if 1) at least one SPI is enabled, and 2) the weak
+ * function pic32mx_spiinitialize() has been brought into the link.
+ */
+
+#if defined(CONFIG_PIC32MX_SPI2)
+ if (pic32mx_spiinitialize)
+ {
+ pic32mx_spiinitialize();
+ }
+#endif
+
+ /* Configure on-board LEDs if LED support has been selected. */
+
+#ifdef CONFIG_ARCH_LEDS
+ pic32mx_ledinit();
+#endif
+}
diff --git a/configs/pic32-starterkit/src/up_leds.c b/configs/pic32-starterkit/src/up_leds.c
new file mode 100644
index 0000000000000000000000000000000000000000..ff2fffa92a0b332b158f6ec0df85e9ac06cd0946
--- /dev/null
+++ b/configs/pic32-starterkit/src/up_leds.c
@@ -0,0 +1,139 @@
+/****************************************************************************
+ * configs/pic32-starterkit/src/up_leds.c
+ * arch/arm/src/board/up_leds.c
+ *
+ * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "up_arch.h"
+#include "up_internal.h"
+
+#include "pic32mx-internal.h"
+#include "starterkit_internal.h"
+
+#ifdef CONFIG_ARCH_LEDS
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+/* The Sure PIC32MX board has five LEDs. One (D4, lablel "Power") is not
+ * controllable by software. Four are controllable by software:
+ *
+ * D7 "USB" Yellow RD7 Low illuminates
+ * D8 "SD" Yellow RD6 Low illuminates
+ * D9 "Flash" Yellow RF0 Low illuminates
+ * D10 "Error" Red RF1 Low illuminates
+ *
+ * ON OFF
+ * USB SD FLASH ERROR USB SD FLASH ERROR
+ * LED_STARTED 0 OFF OFF OFF OFF --- --- --- ---
+ * LED_HEAPALLOCATE 1 ON OFF N/C N/C --- --- --- ---
+ * LED_IRQSENABLED 2 OFF ON N/C N/C --- --- --- ---
+ * LED_STACKCREATED 3 ON ON N/C N/C --- --- --- ---
+ * LED_INIRQ 4 N/C N/C ON N/C N/C N/C OFF N/C
+ * LED_SIGNAL 4 N/C N/C ON N/C N/C N/C OFF N/C
+ * LED_ASSERTION 4 N/C N/C ON N/C N/C N/C OFF N/C
+ * LED_PANIC 5 N/C N/C N/C ON N/C N/C N/C OFF
+ */
+
+/* Enables debug output from this file (needs CONFIG_DEBUG with
+ * CONFIG_DEBUG_VERBOSE too)
+ */
+
+#undef LED_DEBUG /* Define to enable debug */
+#undef LED_VERBOSE /* Define to enable verbose debug */
+
+#ifdef LED_DEBUG
+# define leddbg lldbg
+# ifdef LED_VERBOSE
+# define ledvdbg lldbg
+# else
+# define ledvdbg(x...)
+# endif
+#else
+# undef LED_VERBOSE
+# define leddbg(x...)
+# define ledvdbg(x...)
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_ledinit
+ ****************************************************************************/
+
+void up_ledinit(void)
+{
+#warning "Missing logic"
+}
+
+/****************************************************************************
+ * Name: up_ledon
+ ****************************************************************************/
+
+void up_ledon(int led)
+{
+#warning "Missing logic"
+}
+
+/****************************************************************************
+ * Name: up_ledoff
+ ****************************************************************************/
+
+void up_ledoff(int led)
+{
+#warning "Missing logic"
+}
+#endif /* CONFIG_ARCH_LEDS */
diff --git a/configs/pic32-starterkit/src/up_nsh.c b/configs/pic32-starterkit/src/up_nsh.c
new file mode 100644
index 0000000000000000000000000000000000000000..d66a651cdfaaae7f1167306fccf1c01144729e1a
--- /dev/null
+++ b/configs/pic32-starterkit/src/up_nsh.c
@@ -0,0 +1,322 @@
+/****************************************************************************
+ * config/pic32-starterkit/src/up_nsh.c
+ * arch/arm/src/board/up_nsh.c
+ *
+ * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdio.h>
+#include <unistd.h>
+#include <debug.h>
+#include <errno.h>
+
+#include <nuttx/spi.h>
+#include <nuttx/mmcsd.h>
+#include <nuttx/usb/usbhost.h>
+
+#include "pic32mx-internal.h"
+#include "starterkit_internal.h"
+
+/****************************************************************************
+ * Pre-Processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+/* PORT and SLOT number probably depend on the board configuration */
+
+#ifdef CONFIG_ARCH_BOARD_SUREPIC32MX
+# define CONFIG_NSH_HAVEMMCSD 1
+# define CONFIG_NSH_HAVEUSBHOST 1
+# if !defined(CONFIG_NSH_MMCSDSPIPORTNO) || CONFIG_NSH_MMCSDSPIPORTNO != 1
+# error "The Sure PIC32MX MMC/SD is on SPI2"
+# undef CONFIG_NSH_MMCSDSPIPORTNO
+# define CONFIG_NSH_MMCSDSPIPORTNO 2
+# endif
+# if !defined(CONFIG_NSH_MMCSDSLOTNO) || CONFIG_NSH_MMCSDSLOTNO != 0
+# error "The Sure PIC32MX MMC/SD is only one slot (0)"
+# undef CONFIG_NSH_MMCSDSLOTNO
+# define CONFIG_NSH_MMCSDSLOTNO 0
+# endif
+# ifndef CONFIG_PIC32MX_SPI2
+# warning "CONFIG_PIC32MX_SPI2 is not enabled"
+# undef CONFIG_NSH_HAVEMMCSD
+# endif
+#else
+# error "Unrecognized board"
+# undef CONFIG_NSH_HAVEMMCSD
+# undef CONFIG_NSH_HAVEUSBHOST
+#endif
+
+/* Can't support MMC/SD features if mountpoints are disabled */
+
+#if defined(CONFIG_DISABLE_MOUNTPOINT)
+# undef CONFIG_NSH_HAVEMMCSD
+#endif
+
+#ifndef CONFIG_NSH_MMCSDMINOR
+# define CONFIG_NSH_MMCSDMINOR 0
+#endif
+
+/* USB Host */
+
+#ifdef CONFIG_USBHOST
+# ifndef CONFIG_PIC32MX_USBHOST
+# error "CONFIG_PIC32MX_USBHOST is not selected"
+# endif
+#endif
+
+#ifdef CONFIG_PIC32MX_USBHOST
+# ifndef CONFIG_USBHOST
+# warning "CONFIG_USBHOST is not selected"
+# endif
+#endif
+
+#if !defined(CONFIG_USBHOST) || !defined(CONFIG_PIC32MX_USBHOST)
+# undef CONFIG_NSH_HAVEUSBHOST
+#endif
+
+#ifdef CONFIG_NSH_HAVEUSBHOST
+# ifndef CONFIG_USBHOST_DEFPRIO
+# define CONFIG_USBHOST_DEFPRIO 50
+# endif
+# ifndef CONFIG_USBHOST_STACKSIZE
+# define CONFIG_USBHOST_STACKSIZE 1024
+# endif
+#endif
+
+/* Debug ********************************************************************/
+
+#ifdef CONFIG_CPP_HAVE_VARARGS
+# ifdef CONFIG_DEBUG
+# define message(...) lib_lowprintf(__VA_ARGS__)
+# else
+# define message(...) printf(__VA_ARGS__)
+# endif
+#else
+# ifdef CONFIG_DEBUG
+# define message lib_lowprintf
+# else
+# define message printf
+# endif
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_NSH_HAVEUSBHOST
+static struct usbhost_driver_s *g_drvr;
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nsh_waiter
+ *
+ * Description:
+ * Wait for USB devices to be connected.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_NSH_HAVEUSBHOST
+static int nsh_waiter(int argc, char *argv[])
+{
+ bool connected = false;
+ int ret;
+
+ message("nsh_waiter: Running\n");
+ for (;;)
+ {
+ /* Wait for the device to change state */
+
+ ret = DRVR_WAIT(g_drvr, connected);
+ DEBUGASSERT(ret == OK);
+
+ connected = !connected;
+ message("nsh_waiter: %s\n", connected ? "connected" : "disconnected");
+
+ /* Did we just become connected? */
+
+ if (connected)
+ {
+ /* Yes.. enumerate the newly connected device */
+
+ (void)DRVR_ENUMERATE(g_drvr);
+ }
+ }
+
+ /* Keep the compiler from complaining */
+
+ return 0;
+}
+#endif
+
+/****************************************************************************
+ * Name: nsh_sdinitialize
+ *
+ * Description:
+ * Initialize SPI-based microSD.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_NSH_HAVEMMCSD
+static int nsh_sdinitialize(void)
+{
+ FAR struct spi_dev_s *ssp;
+ int ret;
+
+ /* Get the SPI port */
+
+ ssp = up_spiinitialize(CONFIG_NSH_MMCSDSPIPORTNO);
+ if (!ssp)
+ {
+ message("nsh_archinitialize: Failed to initialize SPI port %d\n",
+ CONFIG_NSH_MMCSDSPIPORTNO);
+ ret = -ENODEV;
+ goto errout;
+ }
+
+ message("Successfully initialized SPI port %d\n",
+ CONFIG_NSH_MMCSDSPIPORTNO);
+
+ /* Bind the SPI port to the slot */
+
+ ret = mmcsd_spislotinitialize(CONFIG_NSH_MMCSDMINOR,
+ CONFIG_NSH_MMCSDSLOTNO, ssp);
+ if (ret < 0)
+ {
+ message("nsh_sdinitialize: "
+ "Failed to bind SPI port %d to MMC/SD slot %d: %d\n",
+ CONFIG_NSH_MMCSDSPIPORTNO,
+ CONFIG_NSH_MMCSDSLOTNO, ret);
+ goto errout;
+ }
+
+ message("Successfuly bound SPI port %d to MMC/SD slot %d\n",
+ CONFIG_NSH_MMCSDSPIPORTNO,
+ CONFIG_NSH_MMCSDSLOTNO);
+ return OK;
+
+errout:
+ return ret;
+}
+#else
+# define nsh_sdinitialize() (OK)
+#endif
+
+/****************************************************************************
+ * Name: nsh_usbhostinitialize
+ *
+ * Description:
+ * Initialize SPI-based microSD.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_NSH_HAVEUSBHOST
+static int nsh_usbhostinitialize(void)
+{
+ int pid;
+ int ret;
+
+ /* First, register all of the class drivers needed to support the drivers
+ * that we care about:
+ */
+
+ message("nsh_usbhostinitialize: Register class drivers\n");
+ ret = usbhost_storageinit();
+ if (ret != OK)
+ {
+ message("nsh_usbhostinitialize: Failed to register the mass storage class\n");
+ }
+
+ /* Then get an instance of the USB host interface */
+
+ message("nsh_usbhostinitialize: Initialize USB host\n");
+ g_drvr = usbhost_initialize(0);
+ if (g_drvr)
+ {
+ /* Start a thread to handle device connection. */
+
+ message("nsh_usbhostinitialize: Start nsh_waiter\n");
+
+#ifndef CONFIG_CUSTOM_STACK
+ pid = task_create("usbhost", CONFIG_USBHOST_DEFPRIO,
+ CONFIG_USBHOST_STACKSIZE,
+ (main_t)nsh_waiter, (const char **)NULL);
+#else
+ pid = task_create("usbhost", CONFIG_USBHOST_DEFPRIO,
+ (main_t)nsh_waiter, (const char **)NULL);
+#endif
+ return pid < 0 ? -ENOEXEC : OK;
+ }
+ return -ENODEV;
+}
+#else
+# define nsh_usbhostinitialize() (OK)
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: nsh_archinitialize
+ *
+ * Description:
+ * Perform architecture specific initialization
+ *
+ ****************************************************************************/
+
+int nsh_archinitialize(void)
+{
+ int ret;
+
+ /* Initialize SPI-based microSD */
+
+ ret = nsh_sdinitialize();
+ if (ret == OK)
+ {
+ /* Initialize USB host */
+
+ ret = nsh_usbhostinitialize();
+ }
+ return ret;
+}
diff --git a/configs/pic32-starterkit/src/up_spi.c b/configs/pic32-starterkit/src/up_spi.c
new file mode 100644
index 0000000000000000000000000000000000000000..c32c27a2b4f102e10a828feb4a37231a74332cab
--- /dev/null
+++ b/configs/pic32-starterkit/src/up_spi.c
@@ -0,0 +1,144 @@
+/************************************************************************************
+ * configs/pic32-starterkit/src/up_ssp.c
+ * arch/arm/src/board/up_ssp.c
+ *
+ * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+
+#include <nuttx/spi.h>
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "chip.h"
+#include "pic32mx-internal.h"
+#include "starterkit_internal.h"
+
+#if defined(CONFIG_PIC32MX_SPI2)
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* The following enable debug output from this file (needs CONFIG_DEBUG too).
+ *
+ * CONFIG_SPI_DEBUG - Define to enable basic SPI debug
+ * CONFIG_SPI_VERBOSE - Define to enable verbose SPI debug
+ */
+
+#ifdef CONFIG_SPI_DEBUG
+# define sspdbg lldbg
+# ifdef CONFIG_SPI_VERBOSE
+# define sspvdbg lldbg
+# else
+# define sspvdbg(x...)
+# endif
+#else
+# undef CONFIG_SPI_VERBOSE
+# define sspdbg(x...)
+# define sspvdbg(x...)
+#endif
+
+/************************************************************************************
+ * Private Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: pic32mx_sspinitialize
+ *
+ * Description:
+ * Called to configure SPI chip select GPIO pins for the Sure PIC32MX board.
+ *
+ ************************************************************************************/
+
+void weak_function pic32mx_sspinitialize(void)
+{
+ /* Configure the SPI2 chip select GPIOs */
+
+#ifdef CONFIG_PIC32MX_SPI2
+# warning "Missing logic"
+#endif
+}
+
+/************************************************************************************
+ * Name: pic32mx_spi2select and pic32mx_spi2status
+ *
+ * Description:
+ * The external functions, pic32mx_spi2select and pic32mx_spi2status
+ * must be provided by board-specific logic. They are implementations of the select
+ * and status methods of the SPI interface defined by struct spi_ops_s (see
+ * include/nuttx/spi.h). All other methods (including up_spiinitialize())
+ * are provided by common PIC32MX logic. To use this common SPI logic on your
+ * board:
+ *
+ * 1. Provide logic in pic32mx_boardinitialize() to configure SPI/SPI chip select
+ * pins.
+ * 2. Provide pic32mx_spi2select() and pic32mx_spi2status() functions
+ * in your board-specific logic. These functions will perform chip selection
+ * and status operations using GPIOs in the way your board is configured.
+ * 3. Add a calls to up_spiinitialize() in your low level application
+ * initialization logic
+ * 4. The handle returned by up_spiinitialize() may then be used to bind the
+ * SPI driver to higher level logic (e.g., calling
+ * mmcsd_spislotinitialize(), for example, will bind the SPI driver to
+ * the SPI MMC/SD driver).
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_PIC32MX_SPI2
+void pic32mx_spi2select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected)
+{
+ sspdbg("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert");
+#warning "Missing logic"
+}
+
+uint8_t pic32mx_spi2status(FAR struct spi_dev_s *dev, enum spi_dev_e devid)
+{
+ sspdbg("Returning nothing\n");
+#warning "Missing logic"
+ return 0;
+}
+#endif
+#endif /* CONFIG_PIC32MX_SPI2 */
diff --git a/configs/pic32-starterkit/tools/Makefile b/configs/pic32-starterkit/tools/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..b01fbba19eadd3b5734de14742a9a73f737aee99
--- /dev/null
+++ b/configs/pic32-starterkit/tools/Makefile
@@ -0,0 +1,51 @@
+############################################################################
+# configs/pic32-starterkit/tools/Makefile
+#
+# Copyright (C) 2011 Gregory Nutt. All rights reserved.
+# Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in
+# the documentation and/or other materials provided with the
+# distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+# used to endorse or promote products derived from this software
+# without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+all: mkpichex
+default: mkpichex
+.PHONY: clean
+
+# Add CFLAGS=-g on the make command line to build debug versions
+
+CFLAGS = -O2 -Wall -I.
+
+# mkpichex - Convert nuttx.ihx to nuttx.hex
+
+mkconfig: mkpichex.c mkpichex.c
+ @gcc $(CFLAGS) -o mkpichex mkpichex.c
+
+clean:
+ @rm -f *.o *.a *~ .*.swp
+ @rm -f mkpichex mkpichex.exe
diff --git a/configs/pic32-starterkit/tools/mkpichex.c b/configs/pic32-starterkit/tools/mkpichex.c
new file mode 100644
index 0000000000000000000000000000000000000000..0922e6768ee0afd148c3e96683d7012ef062a474
--- /dev/null
+++ b/configs/pic32-starterkit/tools/mkpichex.c
@@ -0,0 +1,299 @@
+/****************************************************************************
+ * configs/pic32-starterkit/tools/mkpichex.c
+ *
+ * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <errno.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define MAX_LINE 1024
+
+/* Line offsets */
+
+#define START_OFFSET 0
+#define LEN_OFFSET 1
+#define ADDR_OFFSET (LEN_OFFSET + 2)
+#define TYPE_OFFSET (ADDR_OFFSET + 4)
+#define PAYLOAD_OFFSET (TYPE_OFFSET + 2)
+#define CHKSUM_OFFSET(n) (PAYLOAD_OFFSET+2*(n))
+
+/* Record types:
+ *
+ * 00, data record, contains data and 16-bit address. The format described
+ * above.
+ * 01, End Of File record, a file termination record. No data. Has to be
+ * the last line of the file, only one per file permitted. Usually
+ * ':00000001FF'. Originally the End Of File record could contain a
+ * start address for the program being loaded, e.g. :00AB2F0125
+ * would make a jump to address AB2F. This was convenient when programs
+ * were loaded from punched paper tape.
+ * 02, Extended Segment Address Record, segment-base address. Used when 16
+ * bits are not enough, identical to 80x86 real mode addressing. The
+ * address specified by the 02 record is multiplied by 16 (shifted 4
+ * bits left) and added to the subsequent 00 record addresses. This
+ * allows addressing of up to a megabyte of address space. The address
+ * field of this record has to be 0000, the byte count is 02 (the segment
+ * is 16-bit). The least significant hex digit of the segment address is
+ * always 0.
+ * 03, Start Segment Address Record. For 80x86 processors, it specifies the
+ * initial content of the CS:IP registers. The address field is 0000, the
+ * byte count is 04, the first two bytes are the CS value, the latter two
+ * are the IP value.
+ * 04, Extended Linear Address Record, allowing for fully 32 bit addressing.
+ * The address field is 0000, the byte count is 02. The two data bytes
+ * represent the upper 16 bits of the 32 bit address, when combined with
+ * the address of the 00 type record.
+ * 05, Start Linear Address Record. The address field is 0000, the byte
+ * count is 04. The 4 data bytes represent the 32-bit value loaded into
+ * the EIP register of the 80386 and higher CPU.
+ */
+
+#define TYPE_DATA 0
+#define TYPE_EOF 1
+#define TYPE_EXTSEG 2
+#define TYPE_STARTSEG 3
+#define TYPE_EXTLIN 4
+#define TYPE_STARTLIN 5
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+struct hex_s
+{
+ unsigned char len; /* Length of the data payload */
+ unsigned char type; /* Record type */
+ unsigned short addr; /* Lower 16-bit address */
+};
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static char line[MAX_LINE+1];
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+static inline char *getfilepath(const char *path, const char *name, const char *extension)
+{
+ snprintf(line, MAX_LINE, "%s/%s.%s", path, name, extension);
+ line[MAX_LINE] = '\0';
+ return strdup(line);
+}
+
+static void show_usage(const char *progname)
+{
+ fprintf(stderr, "USAGE: %s <abs path to nuttx.ihx>\n", progname);
+ exit(1);
+}
+
+static unsigned char get4(char hex)
+{
+ if (hex >= '0' && hex <= '9')
+ {
+ return hex - '0';
+ }
+ else if (hex >= 'a' && hex <= 'f')
+ {
+ return hex - 'a' + 10;
+ }
+ else if (hex >= 'A' && hex <= 'F')
+ {
+ return hex - 'A' + 10;
+ }
+
+ fprintf(stderr, "Bad hex character code: %s\n", line);
+ exit(2);
+}
+
+static unsigned char get8(const char *ptr)
+{
+ return get4(ptr[0]) << 4 | get4(ptr[1]);
+}
+
+static unsigned short get16(const char *ptr)
+{
+ return (unsigned short)get8(&ptr[0]) << 8 | (unsigned short)get8(&ptr[2]);
+}
+
+static int parse_line(struct hex_s *hexline)
+{
+ /* :LLAAAATT... */
+
+ if (line[START_OFFSET] != ':')
+ {
+ fprintf(stderr, "Bad start code: %s\n", line);
+ return 1;
+ }
+
+ hexline->len = get8(&line[LEN_OFFSET]);
+ hexline->addr = get16(&line[ADDR_OFFSET]);
+ hexline->type = get8(&line[TYPE_OFFSET]);
+ return 0;
+}
+
+#if 0
+static unsigned char checksum(chksum_ndx)
+{
+ int chksum = 0;
+ int ndx;
+
+ for (ndx = 1; ndx < chksum_ndx; ndx += 2)
+ {
+ chksum += (int)get8(&line[ndx]);
+ }
+ return (unsigned char)((-chksum) & 0xff);
+}
+#endif
+
+static void adjust_extlin(struct hex_s *hexline)
+{
+ unsigned short segment;
+ int chksum;
+
+ /* Make sure that the payload is exactly 2 bytes */
+
+ if (hexline->len != 2)
+ {
+ fprintf(stderr, "Bad length on extended segment address record\n");
+ fprintf(stderr, " %s", line);
+ }
+
+ /* And the address field is supposed to be zero */
+
+ if (hexline->addr != 0)
+ {
+ fprintf(stderr, "Bad address on extended segment address record\n");
+ fprintf(stderr, " %s", line);
+ }
+
+ /* Decode the 2 byte payload */
+
+ segment = get16(&line[PAYLOAD_OFFSET]);
+
+ /* Convert the address to a 29-bit physical address */
+
+ segment &= 0x1fff;
+
+ /* Recalculate the checksum and make sure that there is a null terminator
+ * Since len=2, addr=0, type=4, the is a trivial calculation.
+ */
+
+ chksum = (-(segment + (segment >> 8) + 6)) & 0xff;
+
+ /* Then create the new output record */
+
+ snprintf(line, MAX_LINE-PAYLOAD_OFFSET, ":02000004%04X%02X\n", segment, chksum);
+}
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+int main(int argc, char **argv, char **envp)
+{
+ struct hex_s hexline;
+ char *srcfile;
+ char *destfile;
+ FILE *src;
+ FILE *dest;
+
+ if (argc != 2)
+ {
+ fprintf(stderr, "Unexpected number of arguments\n");
+ show_usage(argv[0]);
+ }
+
+ srcfile = getfilepath(argv[1], "nuttx", "ihx");
+ if (!srcfile)
+ {
+ fprintf(stderr, "getfilepath failed\n");
+ exit(2);
+ }
+
+ destfile = getfilepath(argv[1], "nuttx", "hex");
+ if (!destfile)
+ {
+ fprintf(stderr, "getfilepath failed\n");
+ exit(2);
+ }
+
+ src = fopen(srcfile, "r");
+ if (!src)
+ {
+ fprintf(stderr, "open %s failed: %s\n", srcfile, strerror(errno));
+ exit(3);
+ }
+
+ dest = fopen(destfile, "w");
+ if (!dest)
+ {
+ fprintf(stderr, "open %s failed: %s\n", destfile, strerror(errno));
+ exit(3);
+ }
+
+ /* Read each line from the source file */
+
+ while (fgets(line, MAX_LINE, src) != NULL)
+ {
+ if (parse_line(&hexline))
+ {
+ fprintf(stderr, "Failed to parse line\n");
+ exit(1);
+ }
+
+ /* Adjust 'Extended Segment Address Records'. */
+
+ if (hexline.type == TYPE_EXTLIN)
+ {
+ adjust_extlin(&hexline);
+ }
+ fputs(line, dest);
+ }
+
+ fclose(src);
+ fclose(dest);
+ return 0;
+}