diff --git a/arch/arm/src/kinetis/chip.h b/arch/arm/src/kinetis/chip.h
index 831dbda10607fdd31d4098b1a143ae52c9d59ac4..704f343e87cb7fdd8ebcfaccb93bfa2f1a0c98ec 100755
--- a/arch/arm/src/kinetis/chip.h
+++ b/arch/arm/src/kinetis/chip.h
@@ -50,8 +50,8 @@
#if defined(CONFIG_ARCH_CHIP_MK40X64VFX50) || defined(CONFIG_ARCH_CHIP_MK40X64VLH50) \
defined(CONFIG_ARCH_CHIP_MK40X64VLK50) || defined(CONFIG_ARCH_CHIP_MK40X64VMB50)
-# define KIENTIS_K40 1 /* Kinetics K40 family */
-# undef KIENTIS_K60 /* Not Kinetis K60 family */
+# define KINETIS_K40 1 /* Kinetics K40 family */
+# undef KINETIS_K60 /* Not Kinetis K60 family */
# define KINETIS_FLASH_SIZE (64*1024) /* 64Kb */
# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */
# define KINETIS_SRAM_SIZE (16*1024) /* 16Kb */
@@ -99,8 +99,8 @@
defined(CONFIG_ARCH_CHIP_MK40X128VFX72) || defined(CONFIG_ARCH_CHIP_MK40X128VLH72) \
defined(CONFIG_ARCH_CHIP_MK40X128VLK72) || defined(CONFIG_ARCH_CHIP_MK40X128VMB72) \
defined(CONFIG_ARCH_CHIP_MK40X128VLL72) || defined(CONFIG_ARCH_CHIP_MK40X128VML72)
-# define KIENTIS_K40 1 /* Kinetics K40 family */
-# undef KIENTIS_K60 /* Not Kinetis K60 family */
+# define KINETIS_K40 1 /* Kinetics K40 family */
+# undef KINETIS_K60 /* Not Kinetis K60 family */
# define KINETIS_FLASH_SIZE (128*1024) /* 128Kb */
# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */
# define KINETIS_SRAM_SIZE (32*1024) /* 32Kb */
@@ -140,8 +140,8 @@
#elif defined(CONFIG_ARCH_CHIP_MK40X256VLK72) || defined(CONFIG_ARCH_CHIP_MK40X256VMB72) \
defined(CONFIG_ARCH_CHIP_MK40X256VLL72) || defined(CONFIG_ARCH_CHIP_MK40X256VML72)
-# define KIENTIS_K40 1 /* Kinetics K40 family */
-# undef KIENTIS_K60 /* Not Kinetis K60 family */
+# define KINETIS_K40 1 /* Kinetics K40 family */
+# undef KINETIS_K60 /* Not Kinetis K60 family */
# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
# define KINETIS_FLEXMEM_SIZE (32*1024) /* 32Kb */
# define KINETIS_SRAM_SIZE (32*1024) /* 64Kb */
@@ -180,8 +180,8 @@
# define KINETIS_NCRC 1 /* CRC */
#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100)
-# define KIENTIS_K40 1 /* Kinetics K40 family */
-# undef KIENTIS_K60 /* Not Kinetis K60 family */
+# define KINETIS_K40 1 /* Kinetics K40 family */
+# undef KINETIS_K60 /* Not Kinetis K60 family */
# define KINETIS_FLASH_SIZE (128*1024) /* 128Kb */
# define KINETIS_FLEXMEM_SIZE (128*1024) /* 128Kb */
# define KINETIS_SRAM_SIZE (32*1024) /* 32Kb */
@@ -220,8 +220,8 @@
# define KINETIS_NCRC 1 /* CRC */
#elif defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100)
-# define KIENTIS_K40 1 /* Kinetics K40 family */
-# undef KIENTIS_K60 /* Not Kinetis K60 family */
+# define KINETIS_K40 1 /* Kinetics K40 family */
+# undef KINETIS_K60 /* Not Kinetis K60 family */
# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
# define KINETIS_FLEXMEM_SIZE (256*1024) /* 256Kb */
# define KINETIS_SRAM_SIZE (64*1024) /* 32Kb */
@@ -262,8 +262,8 @@
#elif defined(CONFIG_ARCH_CHIP_MK40N512VLK100) || defined(CONFIG_ARCH_CHIP_MK40N512VMB100) \
defined(CONFIG_ARCH_CHIP_MK40N512VLL100) || defined(CONFIG_ARCH_CHIP_MK40N512VML100) \
defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100)
-# define KIENTIS_K40 1 /* Kinetics K40 family */
-# undef KIENTIS_K60 /* Not Kinetis K60 family */
+# define KINETIS_K40 1 /* Kinetics K40 family */
+# undef KINETIS_K60 /* Not Kinetis K60 family */
# define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */
# undef KINETIS_FLEXMEM_SIZE /* No FlexMemory */
# define KINETIS_SRAM_SIZE (128*1024) /* 128Kb */
@@ -302,8 +302,8 @@
# define KINETIS_NCRC 1 /* CRC */
#elif defined(CONFIG_ARCH_CHIP_MK60N256VLL100)
-# undef KIENTIS_K40 /* Not Kinetics K40 family */
-# define KIENTIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K40 /* Not Kinetics K40 family */
+# define KINETIS_K60 1 /* Kinetis K60 family */
# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
@@ -345,8 +345,8 @@
# define KINETIS_NCRC 1 /* CRC */
#elif defined(CONFIG_ARCH_CHIP_MK60X256VLL100)
-# undef KIENTIS_K40 /* Not Kinetics K40 family */
-# define KIENTIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K40 /* Not Kinetics K40 family */
+# define KINETIS_K60 1 /* Kinetis K60 family */
# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */
# define KINETIS_FLEXRAM_SIZE (4*1024) /* 32Kb */
@@ -388,8 +388,8 @@
# define KINETIS_NCRC 1 /* CRC */
#elif defined(CONFIG_ARCH_CHIP_MK60N512VLL100)
-# undef KIENTIS_K40 /* Not Kinetics K40 family */
-# define KIENTIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K40 /* Not Kinetics K40 family */
+# define KINETIS_K60 1 /* Kinetis K60 family */
# define KINETIS_FLASH_SIZE (512*1024) /* 256Kb */
# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
@@ -431,8 +431,8 @@
# define KINETIS_NCRC 1 /* CRC */
#elif defined(CONFIG_ARCH_CHIP_MK60N256VML100)
-# undef KIENTIS_K40 /* Not Kinetics K40 family */
-# define KIENTIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K40 /* Not Kinetics K40 family */
+# define KINETIS_K60 1 /* Kinetis K60 family */
# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
@@ -474,8 +474,8 @@
# define KINETIS_NCRC 1 /* CRC */
#elif defined(CONFIG_ARCH_CHIP_MK60X256VML100)
-# undef KIENTIS_K40 /* Not Kinetics K40 family */
-# define KIENTIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K40 /* Not Kinetics K40 family */
+# define KINETIS_K60 1 /* Kinetis K60 family */
# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */
# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
@@ -517,8 +517,8 @@
# define KINETIS_NCRC 1 /* CRC */
#elif defined(CONFIG_ARCH_CHIP_MK60N512VML100)
-# undef KIENTIS_K40 /* Not Kinetics K40 family */
-# define KIENTIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K40 /* Not Kinetics K40 family */
+# define KINETIS_K60 1 /* Kinetis K60 family */
# define KINETIS_FLASH_SIZE (512*1024) /* 256Kb */
# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
@@ -560,8 +560,8 @@
# define KINETIS_NCRC 1 /* CRC */
#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100)
-# undef KIENTIS_K40 /* Not Kinetics K40 family */
-# define KIENTIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K40 /* Not Kinetics K40 family */
+# define KINETIS_K60 1 /* Kinetis K60 family */
# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
@@ -603,8 +603,8 @@
# define KINETIS_NCRC 1 /* CRC */
#elif defined(CONFIG_ARCH_CHIP_MK60X256VLQ100)
-# undef KIENTIS_K40 /* Not Kinetics K40 family */
-# define KIENTIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K40 /* Not Kinetics K40 family */
+# define KINETIS_K60 1 /* Kinetis K60 family */
# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */
# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
@@ -646,8 +646,8 @@
# define KINETIS_NCRC 1 /* CRC */
#elif defined(CONFIG_ARCH_CHIP_MK60N512VLQ100)
-# undef KIENTIS_K40 /* Not Kinetics K40 family */
-# define KIENTIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K40 /* Not Kinetics K40 family */
+# define KINETIS_K60 1 /* Kinetis K60 family */
# define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */
# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
@@ -689,8 +689,8 @@
# define KINETIS_NCRC 1 /* CRC */
#elif defined(CONFIG_ARCH_CHIP_MK60N256VMD100)
-# undef KIENTIS_K40 /* Not Kinetics K40 family */
-# define KIENTIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K40 /* Not Kinetics K40 family */
+# define KINETIS_K60 1 /* Kinetis K60 family */
# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
@@ -732,8 +732,8 @@
# define KINETIS_NCRC 1 /* CRC */
#elif defined(CONFIG_ARCH_CHIP_MK60X256VMD100)
-# undef KIENTIS_K40 /* Not Kinetics K40 family */
-# define KIENTIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K40 /* Not Kinetics K40 family */
+# define KINETIS_K60 1 /* Kinetis K60 family */
# define KINETIS_FLASH_SIZE (256*1024) /* 256Kb */
# define KINETIS_FLEXNVM_SIZE (256*1024) /* 256Kb */
# define KINETIS_FLEXRAM_SIZE (4*1024) /* 4Kb */
@@ -775,8 +775,8 @@
# define KINETIS_NCRC 1 /* CRC */
#elif defined(CONFIG_ARCH_CHIP_MK60N512VMD100)
-# undef KIENTIS_K40 /* Not Kinetics K40 family */
-# define KIENTIS_K60 1 /* Kinetis K60 family */
+# undef KINETIS_K40 /* Not Kinetics K40 family */
+# define KINETIS_K60 1 /* Kinetis K60 family */
# define KINETIS_FLASH_SIZE (512*1024) /* 512Kb */
# undef KINETIS_FLEXNVM_SIZE /* No FlexNVM */
# undef KINETIS_FLEXRAM_SIZE /* No FlexRAM */
diff --git a/arch/arm/src/kinetis/kinetis_gpio.h b/arch/arm/src/kinetis/kinetis_gpio.h
new file mode 100755
index 0000000000000000000000000000000000000000..8a87aa72aa76db6080bd15b00929b553bfd90f27
--- /dev/null
+++ b/arch/arm/src/kinetis/kinetis_gpio.h
@@ -0,0 +1,142 @@
+/************************************************************************************
+ * arch/arm/src/kinetis/kinetis_gpio.h
+ *
+ * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_GPIO_H
+#define __ARCH_ARM_SRC_KINETIS_KINETIS_GPIO_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define KINETIS_GPIO_PDOR_OFFSET 0x0000 /* Port Data Output Register */
+#define KINETIS_GPIO_PSOR_OFFSET 0x0004 /* Port Set Output Register */
+#define KINETIS_GPIO_PCOR_OFFSET 0x0008 /* Port Clear Output Register */
+#define KINETIS_GPIO_PTOR_OFFSET 0x000c /* Port Toggle Output Register */
+#define KINETIS_GPIO_PDIR_OFFSET 0x0010 /* Port Data Input Register */
+#define KINETIS_GPIO_PDDR_OFFSET 0x0014 /* Port Data Direction Register */
+
+/* Register Addresses ***************************************************************/
+
+#define KINETIS_GPIO_PDOR(n) (KINETIS_GPIO_BASE(n)+KINETIS_GPIO_PDOR_OFFSET)
+#define KINETIS_GPIO_PSOR(n) (KINETIS_GPIO_BASE(n)+KINETIS_GPIO_PSOR_OFFSET)
+#define KINETIS_GPIO_PCOR(n) (KINETIS_GPIO_BASE(n)+KINETIS_GPIO_PCOR_OFFSET)
+#define KINETIS_GPIO_PTOR(n) (KINETIS_GPIO_BASE(n)+KINETIS_GPIO_PTOR_OFFSET)
+#define KINETIS_GPIO_PDIR(n) (KINETIS_GPIO_BASE(n)+KINETIS_GPIO_PDIR_OFFSET)
+#define KINETIS_GPIO_PDDR(n) (KINETIS_GPIO_BASE(n)+KINETIS_GPIO_PDDR_OFFSET)
+
+#define KINETIS_GPIOA_PDOR (KINETIS_GPIOA_BASE+KINETIS_GPIO_PDOR_OFFSET)
+#define KINETIS_GPIOA_PSOR (KINETIS_GPIOA_BASE+KINETIS_GPIO_PSOR_OFFSET)
+#define KINETIS_GPIOA_PCOR (KINETIS_GPIOA_BASE+KINETIS_GPIO_PCOR_OFFSET)
+#define KINETIS_GPIOA_PTOR (KINETIS_GPIOA_BASE+KINETIS_GPIO_PTOR_OFFSET)
+#define KINETIS_GPIOA_PDIR (KINETIS_GPIOA_BASE+KINETIS_GPIO_PDIR_OFFSET)
+#define KINETIS_GPIOA_PDDR (KINETIS_GPIOA_BASE+KINETIS_GPIO_PDDR_OFFSET)
+
+#define KINETIS_GPIOB_PDOR (KINETIS_GPIOB_BASE+KINETIS_GPIO_PDOR_OFFSET)
+#define KINETIS_GPIOB_PSOR (KINETIS_GPIOB_BASE+KINETIS_GPIO_PSOR_OFFSET)
+#define KINETIS_GPIOB_PCOR (KINETIS_GPIOB_BASE+KINETIS_GPIO_PCOR_OFFSET)
+#define KINETIS_GPIOB_PTOR (KINETIS_GPIOB_BASE+KINETIS_GPIO_PTOR_OFFSET)
+#define KINETIS_GPIOB_PDIR (KINETIS_GPIOB_BASE+KINETIS_GPIO_PDIR_OFFSET)
+#define KINETIS_GPIOB_PDDR (KINETIS_GPIOB_BASE+KINETIS_GPIO_PDDR_OFFSET)
+
+#define KINETIS_GPIOC_PDOR (KINETIS_GPIOC_BASE+KINETIS_GPIO_PDOR_OFFSET)
+#define KINETIS_GPIOC_PSOR (KINETIS_GPIOC_BASE+KINETIS_GPIO_PSOR_OFFSET)
+#define KINETIS_GPIOC_PCOR (KINETIS_GPIOC_BASE+KINETIS_GPIO_PCOR_OFFSET)
+#define KINETIS_GPIOC_PTOR (KINETIS_GPIOC_BASE+KINETIS_GPIO_PTOR_OFFSET)
+#define KINETIS_GPIOC_PDIR (KINETIS_GPIOC_BASE+KINETIS_GPIO_PDIR_OFFSET)
+#define KINETIS_GPIOC_PDDR (KINETIS_GPIOC_BASE+KINETIS_GPIO_PDDR_OFFSET)
+
+#define KINETIS_GPIOD_PDOR (KINETIS_GPIOD_BASE+KINETIS_GPIO_PDOR_OFFSET)
+#define KINETIS_GPIOD_PSOR (KINETIS_GPIOD_BASE+KINETIS_GPIO_PSOR_OFFSET)
+#define KINETIS_GPIOD_PCOR (KINETIS_GPIOD_BASE+KINETIS_GPIO_PCOR_OFFSET)
+#define KINETIS_GPIOD_PTOR (KINETIS_GPIOD_BASE+KINETIS_GPIO_PTOR_OFFSET)
+#define KINETIS_GPIOD_PDIR (KINETIS_GPIOD_BASE+KINETIS_GPIO_PDIR_OFFSET)
+#define KINETIS_GPIOD_PDDR (KINETIS_GPIOD_BASE+KINETIS_GPIO_PDDR_OFFSET)
+
+#define KINETIS_GPIOE_PDOR (KINETIS_GPIOE_BASE+KINETIS_GPIO_PDOR_OFFSET)
+#define KINETIS_GPIOE_PSOR (KINETIS_GPIOE_BASE+KINETIS_GPIO_PSOR_OFFSET)
+#define KINETIS_GPIOE_PCOR (KINETIS_GPIOE_BASE+KINETIS_GPIO_PCOR_OFFSET)
+#define KINETIS_GPIOE_PTOR (KINETIS_GPIOE_BASE+KINETIS_GPIO_PTOR_OFFSET)
+#define KINETIS_GPIOE_PDIR (KINETIS_GPIOE_BASE+KINETIS_GPIO_PDIR_OFFSET)
+#define KINETIS_GPIOE_PDDR (KINETIS_GPIOE_BASE+KINETIS_GPIO_PDDR_OFFSET)
+
+/* Register Bit Definitions *********************************************************/
+
+/* Port Data Output Register */
+
+#define GPIO_PDOR(n) (1 << (n))
+
+/* Port Set Output Register */
+
+#define GPIO_PSOR(n) (1 << (n))
+
+/* Port Clear Output Register */
+
+#define GPIO_PCOR(n) (1 << (n))
+
+/* Port Toggle Output Register */
+
+#define GPIO_PTOR(n) (1 << (n))
+
+/* Port Data Input Register */
+
+#define GPIO_PDIR(n) (1 << (n))
+
+/* Port Data Direction Register */
+
+#define GPIO_PDDR(n) (1 << (n))
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_GPIO_H */
diff --git a/arch/arm/src/kinetis/kinetis_memorymap.h b/arch/arm/src/kinetis/kinetis_memorymap.h
index e0dba8e85bf8d8140fb6f694a34d2f923a9c856f..2e576e3a0500116cf1b62cb545538785e60f5f3f 100755
--- a/arch/arm/src/kinetis/kinetis_memorymap.h
+++ b/arch/arm/src/kinetis/kinetis_memorymap.h
@@ -161,10 +161,16 @@
# define KINETIS_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */
# define KINETIS_UART4_BASE 0x400ea000 /* UART4 */
# define KINETIS_UART5_BASE 0x400eb000 /* UART5 */
-# define KINETIS_XBAR_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general
- * purpose input/output module that shares the
- * crossbar switch slave port with the AIPS-Lite
- * is accessed at this address. */
+# define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general
+ * purpose input/output module that shares the
+ * crossbar switch slave port with the AIPS-Lite
+ * is accessed at this address. */
+# define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6))
+# define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */
+# define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */
+# define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */
+# define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
+# define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
/* Private Peripheral Bus (PPB) Memory Map ******************************************/
@@ -287,10 +293,16 @@
# define KINETIS_DAC1_BASE 0x400cd000 /* 12-bit digital-to-analog converter (DAC) 1 */
# define KINETIS_UART4_BASE 0x400ea000 /* UART4 */
# define KINETIS_UART5_BASE 0x400eb000 /* UART5 */
-# define KINETIS_XBAR_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general
- * purpose input/output module that shares the
- * crossbar switch slave port with the AIPS-Lite
- * is accessed at this address. */
+# define KINETIS_XBARSS_BASE 0x400ff000 /* Not an AIPS-Lite slot. The 32-bit general
+ * purpose input/output module that shares the
+ * crossbar switch slave port with the AIPS-Lite
+ * is accessed at this address. */
+# define KINETIS_GPIO_BASE(n) (0x400ff000 + ((n) << 6))
+# define KINETIS_GPIOA_BASE 0x400ff000 /* GPIO PORTA registers */
+# define KINETIS_GPIOB_BASE 0x400ff040 /* GPIO PORTB registers */
+# define KINETIS_GPIOC_BASE 0x400ff080 /* GPIO PORTC registers */
+# define KINETIS_GPIOD_BASE 0x400ff0c0 /* GPIO PORTD registers */
+# define KINETIS_GPIOE_BASE 0x400ff100 /* GPIO PORTE registers */
/* Private Peripheral Bus (PPB) Memory Map ******************************************/
diff --git a/arch/arm/src/kinetis/kinetis_sim.h b/arch/arm/src/kinetis/kinetis_sim.h
new file mode 100755
index 0000000000000000000000000000000000000000..47dcf6320aebce6d07bec1492abe70fce3e7b605
--- /dev/null
+++ b/arch/arm/src/kinetis/kinetis_sim.h
@@ -0,0 +1,545 @@
+/************************************************************************************
+ * arch/arm/src/kinetis/kinetis_sim.h
+ *
+ * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_SIM_H
+#define __ARCH_ARM_SRC_KINETIS_KINETIS_SIM_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define KINETIS_SIM_SOPT1_OFFSET 0x0000 /* System Options Register 1 */
+#define KINETIS_SIM_SOPT2_OFFSET 0x0004 /* System Options Register 2 */
+#define KINETIS_SIM_SOPT4_OFFSET 0x000c /* System Options Register 4 */
+#define KINETIS_SIM_SOPT5_OFFSET 0x0010 /* System Options Register 5 */
+#define KINETIS_SIM_SOPT6_OFFSET 0x0014 /* System Options Register 6 */
+#define KINETIS_SIM_SOPT7_OFFSET 0x0018 /* System Options Register 7 */
+#define KINETIS_SIM_SDID_OFFSET 0x0024 /* System Device Identification Register */
+#define KINETIS_SIM_SCGC1_OFFSET 0x0028 /* System Clock Gating Control Register 1 */
+#define KINETIS_SIM_SCGC2_OFFSET 0x002c /* System Clock Gating Control Register 2 */
+#define KINETIS_SIM_SCGC3_OFFSET 0x0030 /* System Clock Gating Control Register 3 */
+#define KINETIS_SIM_SCGC4_OFFSET 0x0034 /* System Clock Gating Control Register 4 */
+#define KINETIS_SIM_SCGC5_OFFSET 0x0038 /* System Clock Gating Control Register 5 */
+#define KINETIS_SIM_SCGC6_OFFSET 0x003c /* System Clock Gating Control Register 6 */
+#define KINETIS_SIM_SCGC7_OFFSET 0x0040 /* System Clock Gating Control Register 7 */
+#define KINETIS_SIM_CLKDIV1_OFFSET 0x0044 /* System Clock Divider Register 1 */
+#define KINETIS_SIM_CLKDIV2_OFFSET 0x0048 /* System Clock Divider Register 2 */
+#define KINETIS_SIM_FCFG1_OFFSET 0x004c /* Flash Configuration Register 1 */
+#define KINETIS_SIM_FCFG2_OFFSET 0x0050 /* Flash Configuration Register 2 */
+#define KINETIS_SIM_UIDH_OFFSET 0x0054 /* Unique Identification Register High */
+#define KINETIS_SIM_UIDMH_OFFSET 0x0058 /* Unique Identification Register Mid-High */
+#define KINETIS_SIM_UIDML_OFFSET 0x005c /* Unique Identification Register Mid Low */
+#define KINETIS_SIM_UIDL_OFFSET 0x0060 /* Unique Identification Register Low */
+
+/* Register Addresses ***************************************************************/
+/* NOTE: The SIM_SOPT1 register is located at a different base address than the
+ * other SIM registers.
+ */
+
+#define KINETIS_SIM_SOPT1 (KINETIS_SIMLP_BASE+KINETIS_SIM_SOPT1_OFFSET)
+#define KINETIS_SIM_SOPT2 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT2_OFFSET)
+#define KINETIS_SIM_SOPT4 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT4_OFFSET)
+#define KINETIS_SIM_SOPT5 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT5_OFFSET)
+#define KINETIS_SIM_SOPT6 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT6_OFFSET)
+#define KINETIS_SIM_SOPT7 (KINETIS_SIM_BASE+KINETIS_SIM_SOPT7_OFFSET)
+#define KINETIS_SIM_SDID (KINETIS_SIM_BASE+KINETIS_SIM_SDID_OFFSET)
+#define KINETIS_SIM_SCGC1 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC1_OFFSET)
+#define KINETIS_SIM_SCGC2 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC2_OFFSET)
+#define KINETIS_SIM_SCGC3 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC3_OFFSET)
+#define KINETIS_SIM_SCGC4 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC4_OFFSET)
+#define KINETIS_SIM_SCGC5 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC5_OFFSET)
+#define KINETIS_SIM_SCGC6 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC6_OFFSET)
+#define KINETIS_SIM_SCGC7 (KINETIS_SIM_BASE+KINETIS_SIM_SCGC7_OFFSET)
+#define KINETIS_SIM_CLKDIV1 (KINETIS_SIM_BASE+KINETIS_SIM_CLKDIV1_OFFSET)
+#define KINETIS_SIM_CLKDIV2 (KINETIS_SIM_BASE+KINETIS_SIM_CLKDIV2_OFFSET)
+#define KINETIS_SIM_FCFG1 (KINETIS_SIM_BASE+KINETIS_SIM_FCFG1_OFFSET)
+#define KINETIS_SIM_FCFG2 (KINETIS_SIM_BASE+KINETIS_SIM_FCFG2_OFFSET)
+#define KINETIS_SIM_UIDH (KINETIS_SIM_BASE+KINETIS_SIM_UIDH_OFFSET)
+#define KINETIS_SIM_UIDMH (KINETIS_SIM_BASE+KINETIS_SIM_UIDMH_OFFSET)
+#define KINETIS_SIM_UIDML (KINETIS_SIM_BASE+KINETIS_SIM_UIDML_OFFSET)
+#define KINETIS_SIM_UIDL (KINETIS_SIM_BASE+KINETIS_SIM_UIDL_OFFSET)
+
+/* Register Bit Definitions *********************************************************/
+
+/* System Options Register 1 */
+ /* Bits 0-11: Reserved */
+#define SIM_SOPT1_RAMSIZE_SHIFT (12) /* Bits 12-15: RAM size */
+#define SIM_SOPT1_RAMSIZE_MASK (15 << SIM_SOPT1_RAMSIZE_SHIFT)
+# define SIM_SOPT1_RAMSIZE_32KB (5 << SIM_SOPT1_RAMSIZE_SHIFT) /* 32 KBytes */
+# define SIM_SOPT1_RAMSIZE_64KB (7 << SIM_SOPT1_RAMSIZE_SHIFT) /* 64 KBytes */
+# define SIM_SOPT1_RAMSIZE_96KB (8 << SIM_SOPT1_RAMSIZE_SHIFT) /* 96 KBytes */
+# define SIM_SOPT1_RAMSIZE_128KB (9 << SIM_SOPT1_RAMSIZE_SHIFT) /* 128 KBytes */
+ /* Bits 16-18: Reserved */
+#define SIM_SOPT1_OSC32KSEL (1 << 19) /* Bit 19: 32K oscillator clock select */
+ /* Bits 20-22: Reserved */
+#define SIM_SOPT1_MS (1 << 23) /* Bit 23: EzPort chip select pin state */
+ /* Bits 24-29: Reserved */
+#define SIM_SOPT1_USBSTBY (1 << 30) /* Bit 30: USB voltage regulator in standby mode */
+#define SIM_SOPT1_USBREGEN (1 << 31) /* Bit 31: USB voltage regulator enable */
+
+/* System Options Register 2 */
+
+#define SIM_SOPT2_MCGCLKSEL (1 << 0) /* Bit 0: MCG clock select */
+ /* Bits 1-7: Reserved */
+#define SIM_SOPT2_FBSL_SHIFT (8) /* Bits 8-9: FlexBus security level */
+#define SIM_SOPT2_FBSL_MASK (3 << SIM_SOPT2_FBSL_SHIFT)
+# define SIM_SOPT2_FBSL_NONE (0 << SIM_SOPT2_FBSL_SHIFT) /* All off-chip accesses disallowed */
+# define SIM_SOPT2_FBSL_DATA (2 << SIM_SOPT2_FBSL_SHIFT) /* Off-chip data accesses are allowed */
+# define SIM_SOPT2_FBSL_ALL (3 << SIM_SOPT2_FBSL_SHIFT) /* All Off-chip accesses allowed */
+ /* Bit 10: Reserved */
+#define SIM_SOPT2_CMTUARTPAD (1 << 11) /* Bit 11: CMT/UART pad drive strength */
+#define SIM_SOPT2_TRACECLKSEL (1 << 12) /* Bit 12: Debug trace clock select */
+ /* Bits 13-15: Reserved */
+#define SIM_SOPT2_PLLFLLSEL (1 << 16) /* Bit 16: PLL/FLL clock select */
+ /* Bit 17: Reserved */
+#define SIM_SOPT2_USBSRC (1 << 18) /* Bit 18: USB clock source select */
+ /* Bit 19: Reserved */
+#ifdef KINETIS_K60
+# define SIM_SOPT2_TIMESRC (1 << 20) /* Bit 20: IEEE 1588 timestamp clock source select (K60) */
+#endif
+ /* Bits 12-23: Reserved */
+#define SIM_SOPT2_I2SSRC_SHIFT (24) /* Bits 24-25: I2S master clock source select */
+#define SIM_SOPT2_I2SSRC_MASK (3 << SIM_SOPT2_I2SSRC_SHIFT)
+# define SIM_SOPT2_I2SCSRC_CORE (0 << SIM_SOPT2_I2SSRC_SHIFT) /* Core/system clock / I2S fractional divider*/
+# define SIM_SOPT2_I2SCSRC_MCGCLK (1 << SIM_SOPT2_I2SSRC_SHIFT) /* MCGPLLCLK/MCGFLLCLK clock/ I2S fractional divider */
+# define SIM_SOPT2_I2SCSRC_OCSERCLK (2 << SIM_SOPT2_I2SSRC_SHIFT) /* OSCERCLK clock */
+# define SIM_SOPT2_I2SCSRC_EXTBYP (3 << SIM_SOPT2_I2SSRC_SHIFT) /* External bypass clock (I2S0_CLKIN) */
+ /* Bits 26-27: Reserved */
+#define SIM_SOPT2_SDHCSRC_SHIFT (28) /* Bits 28-29: SDHC clock source select*/
+#define SIM_SOPT2_SDHCSRC_MASK (3 << SIM_SOPT2_SDHCSRC_SHIFT)
+# define SIM_SOPT2_SDHCSRC_CORE (0 << SIM_SOPT2_SDHCSRC_SHIFT) /* Core/system clock */
+# define SIM_SOPT2_SDHCSRC_MCGCLK (1 << SIM_SOPT2_SDHCSRC_SHIFT) /* MCGPLLCLK/MCGFLLCLK clock */
+# define SIM_SOPT2_SDHCSRC_OCSERCLK (2 << SIM_SOPT2_SDHCSRC_SHIFT) /* OSCERCLK clock */
+# define SIM_SOPT2_SDHCSRC_EXTBYP (3 << SIM_SOPT2_SDHCSRC_SHIFT) /* External bypass clock (SDHC0_CLKIN) */ /* Bits 30-31: Reserved */
+
+/* System Options Register 4 */
+
+#define SIM_SOPT4_FTM0FLT0 (1 << 0) /* Bit 0: FTM0 Fault 0 Select */
+#define SIM_SOPT4_FTM0FLT1 (1 << 1) /* Bit 1: FTM0 Fault 1 Select */
+#define SIM_SOPT4_FTM0FLT2 (1 << 2) /* Bit 2: FTM0 Fault 2 Select */
+ /* Bit 3: Reserved */
+#define SIM_SOPT4_FTM1FLT0 (1 << 4) /* Bit 4: FTM1 Fault 0 Select */
+ /* Bits 5-7: Reserved */
+#define SIM_SOPT4_FTM2FLT0 (1 << 8) /* Bit 8: FTM2 Fault 0 Select */
+ /* Bits 9-17: Reserved */
+#define SIM_SOPT4_FTM1CH0SRC_SHIFT (18) /* Bits 18-19: FTM1 channel 0 input capture source select */
+#define SIM_SOPT4_FTM1CH0SRC_MASK (3 << SIM_SOPT4_FTM1CH0SRC_SHIFT)
+# define SIM_SOPT4_FTM1CH0SRC_CH0 (0 << SIM_SOPT4_FTM1CH0SRC_SHIFT) /* FTM1_CH0 signal */
+# define SIM_SOPT4_FTM1CH0SRC_CMP0 (1 << SIM_SOPT4_FTM1CH0SRC_SHIFT) /* CMP0 output */
+# define SIM_SOPT4_FTM1CH0SRC_CMP1 (2 << SIM_SOPT4_FTM1CH0SRC_SHIFT) /* CMP1 output */
+#define SIM_SOPT4_FTM2CH0SRC_SHIFT (20) /* Bits 20-21: FTM2 channel 0 input capture source select */
+#define SIM_SOPT4_FTM2CH0SRC_MASK (3 << SIM_SOPT4_FTM2CH0SRC_SHIFT)
+# define SIM_SOPT4_FTM2CH0SRC_CH0 (0 << SIM_SOPT4_FTM2CH0SRC_SHIFT) /* FTM2_CH0 signal */
+# define SIM_SOPT4_FTM2CH0SRC_CMP0 (1 << SIM_SOPT4_FTM2CH0SRC_SHIFT) /* CMP0 output */
+# define SIM_SOPT4_FTM2CH0SRC_CMP1 (2 << SIM_SOPT4_FTM2CH0SRC_SHIFT) /* CMP1 output */
+ /* Bits 22-23: Reserved */
+#define SIM_SOPT4_FTM0CLKSEL (1 << 24) /* Bit 24: FlexTimer 0 External Clock Pin Select */
+#define SIM_SOPT4_FTM1CLKSEL (1 << 25) /* Bit 25: FTM1 External Clock Pin Select */
+#define SIM_SOPT4_FTM2CLKSEL (1 << 26) /* Bit 26: FlexTimer 2 External Clock Pin Select */
+ /* Bits 27-31: Reserved */
+
+/* System Options Register 5 */
+
+#define SIM_SOPT5_UART0TXSRC_SHIFT (0) /* Bits 0-1: UART 0 transmit data source select */
+#define SIM_SOPT5_UART0TXSRC_MASK (3 << SIM_SOPT5_UART0TXSRC_SHIFT)
+# define SIM_SOPT5_UART0TXSRC_TX (0 << SIM_SOPT5_UART0TXSRC_SHIFT) /* UART0_TX pin */
+# define SIM_SOPT5_UART0TXSRC_FTM1 (1 << SIM_SOPT5_UART0TXSRC_SHIFT) /* UART0_TX modulated with FTM1 ch0 output */
+# define SIM_SOPT5_UART0TXSRC_FTM2 (2 << SIM_SOPT5_UART0TXSRC_SHIFT) /* UART0_TX modulated with FTM2 ch0 output */
+#define SIM_SOPT5_UART0RXSRC_SHIFT (2) /* Bits 2-3: UART 0 receive data source select */
+#define SIM_SOPT5_UART0RXSRC_MASK (3 << SIM_SOPT5_UART0RXSRC_SHIFT)
+# define SIM_SOPT5_UART0RXSRC_RX (0 << SIM_SOPT5_UART0RXSRC_SHIFT) /* UART0_RX pin */
+# define SIM_SOPT5_UART0RXSRC_CMP0 (1 << SIM_SOPT5_UART0RXSRC_SHIFT) /* CMP0 */
+# define SIM_SOPT5_UART0RXSRC_CMP1 (2 << SIM_SOPT5_UART0RXSRC_SHIFT) /* CMP1 */
+#define SIM_SOPT5_UART1TXSRC_SHIFT (4) /* Bits 4-5: UART 1 transmit data source select */
+#define SIM_SOPT5_UART1TXSRC_MASK (3 << SIM_SOPT5_UART1TXSRC_SHIFT)
+# define SIM_SOPT5_UART1TXSRC_TX (0 << SIM_SOPT5_UART1TXSRC_SHIFT) /* UART1_TX pin */
+# define SIM_SOPT5_UART1TXSRC_FTM1 (1 << SIM_SOPT5_UART1TXSRC_SHIFT) /* UART1_TX modulated with FTM1 ch0 output */
+# define SIM_SOPT5_UART1TXSRC_FTM2 (2 << SIM_SOPT5_UART1TXSRC_SHIFT) /* UART1_TX modulated with FTM2 ch0 output */
+#define SIM_SOPT5_UART1RXSRC_SHIFT (6) /* Bits 6-7: UART 1 receive data source select */
+#define SIM_SOPT5_UART1RXSRC_MASK (3 << SIM_SOPT5_UART1RXSRC_SHIFT)
+# define SIM_SOPT5_UART1RXSRC_RX (0 << SIM_SOPT5_UART1RXSRC_SHIFT) /* UART1_RX pin */
+# define SIM_SOPT5_UART1RXSRC_CMP0 (1 << SIM_SOPT5_UART1RXSRC_SHIFT) /* CMP0 */
+# define SIM_SOPT5_UART1RXSRC_CMP1 (2 << SIM_SOPT5_UART1RXSRC_SHIFT) /* CMP1 */
+ /* Bits 8-31: Reserved */
+/* System Options Register 6 */
+ /* Bits 0-23: Reserved */
+#define SIM_SOPT6_RSTFLTSEL_SHIFT (24) /* Bits 24-28: Reset pin filter select */
+#define SIM_SOPT6_RSTFLTSEL_MASK (31 << SIM_SOPT6_RSTFLTSEL_SHIFT)
+# SIM_SOPT6_RSTFLTSEL(n) (((n)-1) << SIM_SOPT6_RSTFLTSEL_SHIFT) /* Bux clock filter count n, n=1..32 */
+#define SIM_SOPT6_RSTFLTEN_SHIFT (29) /* Bits 29-31: Reset pin filter enable */
+#define SIM_SOPT6_RSTFLTEN_MASK (7 << SIM_SOPT6_RSTFLTEN_SHIFT)
+#define SIM_SOPT6_RSTFLTEN_DISABLED (0 << SIM_SOPT6_RSTFLTEN_SHIFT) /* All filtering disabled */
+# define SIM_SOPT6_RSTFLTEN_ BUSCLK1 (1 << SIM_SOPT6_RSTFLTEN_SHIFT) /* Bus clock filter enabled (normal); LPO clock filter enabled (stop) */
+# define SIM_SOPT6_RSTFLTEN_ LPO1 (2 << SIM_SOPT6_RSTFLTEN_SHIFT) /* LPO clock filter enabled */
+# define SIM_SOPT6_RSTFLTEN_ BUSCLK2 (3 << SIM_SOPT6_RSTFLTEN_SHIFT) /* Bus clock filter enabled (normal); All filtering disabled (stop) */
+# define SIM_SOPT6_RSTFLTEN_ LPO2 (4 << SIM_SOPT6_RSTFLTEN_SHIFT) /* PO clock filter enabled (normal); All filtering disabled (stop) */
+
+/* System Options Register 7 */
+
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT (0) /* Bits 0-3: ADC0 trigger select */
+#define SIM_SOPT7_ADC0TRGSEL_MASK (15 << SIM_SOPT7_ADC0TRGSEL_SHIFT)
+# define SIM_SOPT7_ADC0TRGSEL_PDB (0 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* PDB external trigger (PDB0_EXTRG) */
+# define SIM_SOPT7_ADC0TRGSEL_CMP0 (1 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* High speed comparator 0 output */
+# define SIM_SOPT7_ADC0TRGSEL_CMP1 (2 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* High speed comparator 1 output */
+# define SIM_SOPT7_ADC0TRGSEL_CMP2 (3 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* High speed comparator 2 output */
+# define SIM_SOPT7_ADC0TRGSEL_PIT0 (4 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* PIT trigger 0 */
+# define SIM_SOPT7_ADC0TRGSEL_PIT1 (5 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* PIT trigger 1 */
+# define SIM_SOPT7_ADC0TRGSEL_PIT2 (6 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* PIT trigger 2 */
+# define SIM_SOPT7_ADC0TRGSEL_PIT3 (7 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* PIT trigger 3 */
+# define SIM_SOPT7_ADC0TRGSEL_FTM0 (8 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* FTM0 trigger */
+# define SIM_SOPT7_ADC0TRGSEL_FTM1 (9 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* FTM1 trigger */
+# define SIM_SOPT7_ADC0TRGSEL_FTM2 (10 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* FTM2 trigger */
+# define SIM_SOPT7_ADC0TRGSEL_ALARM (12 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* RTC alarm */
+# define SIM_SOPT7_ADC0TRGSEL_SECS (13 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* RTC seconds */
+# define SIM_SOPT7_ADC0TRGSEL_LPTMR (14 << SIM_SOPT7_ADC0TRGSEL_SHIFT) /* Low-power timer trigger */
+#define SIM_SOPT7_ADC0PRETRGSEL (1 << 4) /* Bit 4: ADC0 pretrigger select */
+ /* Bits 5-6: Reserved */
+#define SIM_SOPT7_ADC0ALTTRGEN (1 << 7) /* Bit 7: ADC0 alternate trigger enable */
+#define SIM_SOPT7_ADC1TRGSEL_SHIFT (8) /* Bits 8-11: ADC1 trigger select */
+#define SIM_SOPT7_ADC1TRGSEL_MASK (15 << SIM_SOPT7_ADC1TRGSEL_SHIFT)
+# define SIM_SOPT7_ADC1TRGSEL_PDB (0 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* PDB external trigger (PDB0_EXTRG) */
+# define SIM_SOPT7_ADC1TRGSEL_CMP0 (1 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* High speed comparator 0 output */
+# define SIM_SOPT7_ADC1TRGSEL_CMP1 (2 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* High speed comparator 1 output */
+# define SIM_SOPT7_ADC1TRGSEL_CMP2 (3 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* High speed comparator 2 output */
+# define SIM_SOPT7_ADC1TRGSEL_PIT0 (4 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* PIT trigger 0 */
+# define SIM_SOPT7_ADC1TRGSEL_PIT1 (5 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* PIT trigger 1 */
+# define SIM_SOPT7_ADC1TRGSEL_PIT2 (6 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* PIT trigger 2 */
+# define SIM_SOPT7_ADC1TRGSEL_PIT3 (7 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* PIT trigger 3 */
+# define SIM_SOPT7_ADC1TRGSEL_FTM0 (8 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* FTM0 trigger */
+# define SIM_SOPT7_ADC1TRGSEL_FTM1 (9 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* FTM1 trigger */
+# define SIM_SOPT7_ADC1TRGSEL_FTM2 (10 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* FTM2 trigger */
+# define SIM_SOPT7_ADC1TRGSEL_ALARM (12 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* RTC alarm */
+# define SIM_SOPT7_ADC1TRGSEL_SECS (13 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* RTC seconds */
+# define SIM_SOPT7_ADC1TRGSEL_LPTMR (14 << SIM_SOPT7_ADC1TRGSEL_SHIFT) /* Low-power timer trigger */
+#define SIM_SOPT7_ADC1PRETRGSEL (1 << 12) /* Bit 12: ADC1 pre-trigger select */
+ /* Bits 13-14: Reserved */
+#define SIM_SOPT7_ADC1ALTTRGEN (1 << 15) /* Bit 15: ADC1 alternate trigger enable */
+ /* Bits 16-31: Reserved */
+/* System Device Identification Register */
+
+#define SIM_SDID_PINID_SHIFT (0) /* Bits 0-3: Pincount identification */
+#define SIM_SDID_PINID_MASK (15 << SIM_SDID_PINID_SHIFT)
+# define SIM_SDID_PINID_32PIN (2 << SIM_SDID_PINID_SHIFT) /* 32-pin */
+# define SIM_SDID_PINID_48PIN (4 << SIM_SDID_PINID_SHIFT) /* 48-pin */
+# define SIM_SDID_PINID_64PIN (5 << SIM_SDID_PINID_SHIFT) /* 64-pin */
+# define SIM_SDID_PINID_80PIN (6 << SIM_SDID_PINID_SHIFT) /* 80-pin */
+# define SIM_SDID_PINID_81PIN (7 << SIM_SDID_PINID_SHIFT) /* 81-pin */
+# define SIM_SDID_PINID_100PIN (8 << SIM_SDID_PINID_SHIFT) /* 100-pin */
+# define SIM_SDID_PINID_121PIN (9 << SIM_SDID_PINID_SHIFT) /* 121-pin */
+# define SIM_SDID_PINID_144PIN (10 << SIM_SDID_PINID_SHIFT) /* 144-pin */
+# define SIM_SDID_PINID_196PIN (12 << SIM_SDID_PINID_SHIFT) /* 196-pin */
+# define SIM_SDID_PINID_256PIN (14 << SIM_SDID_PINID_SHIFT) /* 256-pin */
+#define SIM_SDID_FAMID_SHIFT (4) /* Bits 4-6: Kinetis family identification */
+#define SIM_SDID_FAMID_MASK (7 << SIM_SDID_FAMID_SHIFT)
+# define SIM_SDID_FAMID_K10 (0 << SIM_SDID_FAMID_SHIFT) /* K10 */
+# define SIM_SDID_FAMID_K20 (1 << SIM_SDID_FAMID_SHIFT)) /* K20 */
+# define SIM_SDID_FAMID_K30 (2 << SIM_SDID_FAMID_SHIFT)) /* K30 */
+# define SIM_SDID_FAMID_K40 (3 << SIM_SDID_FAMID_SHIFT)) /* K40 */
+# define SIM_SDID_FAMID_K60 (4 << SIM_SDID_FAMID_SHIFT)) /* K60 */
+# define SIM_SDID_FAMID_K70 (5 << SIM_SDID_FAMID_SHIFT)) /* K70 */
+# define SIM_SDID_FAMID_K50 (6 << SIM_SDID_FAMID_SHIFT)) /* K50 and K52 */
+# define SIM_SDID_FAMID_K51 (7 << SIM_SDID_FAMID_SHIFT)) /* K51 and K53 */
+ /* Bits 7-11: Reserved */
+#define SIM_SDID_REVID_SHIFT (12) /* Bits 12-15: Device revision number */
+#define SIM_SDID_REVID_MASK (15 << SIM_SDID_REVID_SHIFT)
+ /* Bits 16-31: Reserved */
+/* System Clock Gating Control Register 1 */
+ /* Bits 0-9: Reserved */
+#define SIM_SCGC1_UART4 (1 << 10) /* Bit 10: UART4 Clock Gate Control */
+#define SIM_SCGC1_UART5 (1 << 11) /* Bit 11: UART5 Clock Gate Control */
+ /* Bits 12-31: Reserved */
+/* System Clock Gating Control Register 2 */
+
+#ifdef KINETIS_K60
+# define SIM_SCGC2_ENET (1 << 0) /* Bit 0: ENET Clock Gate Control (K60) */
+#endif
+ /* Bits 1-11: Reserved */
+#define SIM_SCGC2_DAC0 (1 << 12) /* Bit 12: DAC0 Clock Gate Control */
+#define SIM_SCGC2_DAC1 (1 << 13) /* Bit 13: DAC1 Clock Gate Control */
+ /* Bits 14-31: Reserved */
+/* System Clock Gating Control Register 3 */
+
+#ifdef KINETIS_K60
+# define SIM_SCGC3_RNGB (1 << 0) /* Bit 0: RNGB Clock Gate Control (K60) */
+#endif
+ /* Bits 1-3: Reserved */
+#define SIM_SCGC3_FLEXCAN1 (1 << 4) /* Bit 4: FlexCAN1 Clock Gate Control */
+ /* Bits 5-11: Reserved */
+#define SIM_SCGC3_SPI2 (1 << 12) /* Bit 12: SPI2 Clock Gate Control */
+ /* Bits 13-16: Reserved */
+#define SIM_SCGC3_SDHC (1 << 17) /* Bit 17: SDHC Clock Gate Control */
+ /* Bits 18-23: Reserved */
+#define SIM_SCGC3_FTM2 (1 << 24) /* Bit 24: FTM2 Clock Gate Control */
+ /* Bits 25-26: Reserved */
+#define SIM_SCGC3_ADC1 (1 << 27) /* Bit 27: ADC1 Clock Gate Control */
+ /* Bits 28-29: Reserved */
+#ifdef KINETIS_K40
+# define SIM_SCGC3_SLCD (1 << 30) /* Bit 30: Segment LCD Clock Gate Control (K40) */
+#endif
+ /* Bit 31: Reserved */
+/* System Clock Gating Control Register 4 */
+ /* Bit 0: Reserved */
+#define SIM_SCGC4_EWM (1 << 1) /* Bit 1: EWM Clock Gate Control */
+#define SIM_SCGC4_CMT (1 << 2) /* Bit 2: CMT Clock Gate Control */
+ /* Bits 3-5: Reserved */
+#define SIM_SCGC4_I2C0 (1 << 6) /* Bit 6: I2C0 Clock Gate Control */
+#define SIM_SCGC4_I2C1 (1 << 7) /* Bit 7: I2C1 Clock Gate Control */
+ /* Bits 8-9: Reserved */
+#define SIM_SCGC4_UART0 (1 << 10) /* Bit 10: UART0 Clock Gate Control */
+#define SIM_SCGC4_UART1 (1 << 11) /* Bit 11: UART1 Clock Gate Control */
+#define SIM_SCGC4_UART2 (1 << 12) /* Bit 12: UART2 Clock Gate Control */
+#define SIM_SCGC4_UART3 (1 << 13) /* Bit 13: UART3 Clock Gate Control */
+ /* Bits 14-17: Reserved */
+#define SIM_SCGC4_USBOTG (1 << 18) /* Bit 18: USB Clock Gate Control */
+#define SIM_SCGC4_CMP (1 << 19) /* Bit 19: Comparator Clock Gate Control */
+#define SIM_SCGC4_VREF (1 << 20) /* Bit 20: VREF Clock Gate Control */
+ /* Bits 21-17: Reserved */
+#define SIM_SCGC4_LLWU (1 << 28) /* Bit 28: LLWU Clock Gate Control */
+ /* Bits 29-31: Reserved */
+/* System Clock Gating Control Register 5 */
+
+#define SIM_SCGC5_LPTIMER (1 << 0) /* Bit 0: Low Power Timer Clock Gate Control */
+#define SIM_SCGC5_REGFILE (1 << 1) /* Bit 1: Register File Clock Gate Control */
+ /* Bits 2-4: Reserved */
+#define SIM_SCGC5_TSI (1 << 5) /* Bit 5: TSI Clock Gate Control */
+ /* Bits 6-8: Reserved */
+#define SIM_SCGC5_PORTA (1 << 9) /* Bit 9: Port A Clock Gate Control */
+#define SIM_SCGC5_PORTB (1 << 10) /* Bit 10: Port B Clock Gate Control */
+#define SIM_SCGC5_PORTC (1 << 11) /* Bit 11: Port C Clock Gate Control */
+#define SIM_SCGC5_PORTD (1 << 12) /* Bit 12: Port D Clock Gate Control */
+#define SIM_SCGC5_PORTE (1 << 13) /* Bit 13: Port E Clock Gate Control */
+ /* Bits 14-31: Reserved */
+/* System Clock Gating Control Register 6 */
+
+#define SIM_SCGC6_FTFL (1 << 0) /* Bit 0: Flash Memory Clock Gate Control */
+#define SIM_SCGC6_DMAMUX (1 << 1) /* Bit 1: DMA Mux Clock Gate Control */
+ /* Bits 2-3: Reserved */
+#define SIM_SCGC6_FLEXCAN0 (1 << 4) /* Bit 4: FlexCAN0 Clock Gate Control */
+ /* Bits 5-11: Reserved */
+#define SIM_SCGC6_SPI0 (1 << 12) /* Bit 12: SPI0 Clock Gate Control */
+#define SIM_SCGC6_SPI1 (1 << 13) /* Bit 13: SPI1 Clock Gate Control */
+ /* Bit 14: Reserved */
+#define SIM_SCGC6_I2S (1 << 15) /* Bit 15: I2S Clock Gate Control */
+ /* Bits 16-17: Reserved */
+#define SIM_SCGC6_CRC (1 << 18) /* Bit 18: CRC Clock Gate Control */
+ /* Bits 19-20: Reserved */
+#define SIM_SCGC6_USBDCD (1 << 21) /* Bit 21: USB DCD Clock Gate Control */
+#define SIM_SCGC6_PDB (1 << 22) /* Bit 22: PDB Clock Gate Control */
+#define SIM_SCGC6_PIT (1 << 23) /* Bit 23: PIT Clock Gate Control */
+#define SIM_SCGC6_FTM0 (1 << 24) /* Bit 24: FTM0 Clock Gate Control */
+#define SIM_SCGC6_FTM1 (1 << 25) /* Bit 25: FTM1 Clock Gate Control */
+ /* Bit 26: Reserved */
+#define SIM_SCGC6_ADC0 (1 << 27) /* Bit 27: ADC0 Clock Gate Control */
+ /* Bit 28: Reserved */
+#define SIM_SCGC6_RTC (1 << 29) /* Bit 29: RTC Clock Gate Control */
+ /* Bits 30-31: Reserved */
+/* System Clock Gating Control Register 7 */
+
+#define SIM_SCGC7_FLEXBUS (1 << 0) /* Bit 0: FlexBus Clock Gate Control */
+#define SIM_SCGC7_DMA (1 << 1) /* Bit 1: DMA Clock Gate Control */
+#define SIM_SCGC7_MPU (1 << 2) /* Bit 2: MPU Clock Gate Control */
+ /* Bits 3-31: Reserved */
+/* System Clock Divider Register 1 */
+ /* Bits 0-15: Reserved */
+#define SIM_CLKDIV1_OUTDIV4_SHIFT (16) /* Bits 16-19: Clock 4 output divider value */
+#define SIM_CLKDIV1_OUTDIV4_MASK (15 << SIM_CLKDIV1_OUTDIV4_SHIFT)
+# define SIM_CLKDIV1_OUTDIV4_DIV(n) (((n)-1) << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by n, n=1..16 */
+# define SIM_CLKDIV1_OUTDIV4_DIV1 (0 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 1 */
+# define SIM_CLKDIV1_OUTDIV4_DIV2 (1 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 2 */
+# define SIM_CLKDIV1_OUTDIV4_DIV3 (2 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 3 */
+# define SIM_CLKDIV1_OUTDIV4_DIV4 (3 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 4 */
+# define SIM_CLKDIV1_OUTDIV4_DIV5 (4 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 5 */
+# define SIM_CLKDIV1_OUTDIV4_DIV6 (5 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 6 */
+# define SIM_CLKDIV1_OUTDIV4_DIV7 (6 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 7 */
+# define SIM_CLKDIV1_OUTDIV4_DIV8 (7 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 8 */
+# define SIM_CLKDIV1_OUTDIV4_DIV9 (8 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 9 */
+# define SIM_CLKDIV1_OUTDIV4_DIV10 (9 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 10 */
+# define SIM_CLKDIV1_OUTDIV4_DIV11 (10 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 11 */
+# define SIM_CLKDIV1_OUTDIV4_DIV12 (11 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 12 */
+# define SIM_CLKDIV1_OUTDIV4_DIV13 (12 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 13 */
+# define SIM_CLKDIV1_OUTDIV4_DIV14 (13 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 14 */
+# define SIM_CLKDIV1_OUTDIV4_DIV15 (14 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 15 */
+# define SIM_CLKDIV1_OUTDIV4_DIV16 (15 << SIM_CLKDIV1_OUTDIV4_SHIFT) /* Divide by 16 */
+#define SIM_CLKDIV1_OUTDIV3_SHIFT (20) /* Bits 20-23: Clock 3 output divider value */
+#define SIM_CLKDIV1_OUTDIV3_MASK (15 << SIM_CLKDIV1_OUTDIV3_SHIFT)
+# define SIM_CLKDIV1_OUTDIV3_DIV(n) (((n)-1) << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by n, n=1..16 */
+# define SIM_CLKDIV1_OUTDIV3_DIV1 (0 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 1 */
+# define SIM_CLKDIV1_OUTDIV3_DIV2 (1 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 2 */
+# define SIM_CLKDIV1_OUTDIV3_DIV3 (2 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 3 */
+# define SIM_CLKDIV1_OUTDIV3_DIV4 (3 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 4 */
+# define SIM_CLKDIV1_OUTDIV3_DIV5 (4 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 5 */
+# define SIM_CLKDIV1_OUTDIV3_DIV6 (5 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 6 */
+# define SIM_CLKDIV1_OUTDIV3_DIV7 (6 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 7 */
+# define SIM_CLKDIV1_OUTDIV3_DIV8 (7 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 8 */
+# define SIM_CLKDIV1_OUTDIV3_DIV9 (8 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 9 */
+# define SIM_CLKDIV1_OUTDIV3_DIV10 (9 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 10 */
+# define SIM_CLKDIV1_OUTDIV3_DIV11 (10 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 11 */
+# define SIM_CLKDIV1_OUTDIV3_DIV12 (11 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 12 */
+# define SIM_CLKDIV1_OUTDIV3_DIV13 (12 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 13 */
+# define SIM_CLKDIV1_OUTDIV3_DIV14 (13 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 14 */
+# define SIM_CLKDIV1_OUTDIV3_DIV15 (14 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 15 */
+# define SIM_CLKDIV1_OUTDIV3_DIV16 (15 << SIM_CLKDIV1_OUTDIV3_SHIFT) /* Divide by 16 */
+#define SIM_CLKDIV1_OUTDIV2_SHIFT (24) /* Bits 24-27: Clock 2 output divider value */
+#define SIM_CLKDIV1_OUTDIV2_MASK (15 << SIM_CLKDIV1_OUTDIV2_SHIFT)
+# define SIM_CLKDIV1_OUTDIV2_DIV(n) (((n)-1) << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by n, n=1..16 */
+# define SIM_CLKDIV1_OUTDIV2_DIV1 (0 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 1 */
+# define SIM_CLKDIV1_OUTDIV2_DIV2 (1 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 2 */
+# define SIM_CLKDIV1_OUTDIV2_DIV3 (2 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 3 */
+# define SIM_CLKDIV1_OUTDIV2_DIV4 (3 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 4 */
+# define SIM_CLKDIV1_OUTDIV2_DIV5 (4 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 5 */
+# define SIM_CLKDIV1_OUTDIV2_DIV6 (5 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 6 */
+# define SIM_CLKDIV1_OUTDIV2_DIV7 (6 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 7 */
+# define SIM_CLKDIV1_OUTDIV2_DIV8 (7 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 8 */
+# define SIM_CLKDIV1_OUTDIV2_DIV9 (8 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 9 */
+# define SIM_CLKDIV1_OUTDIV2_DIV10 (9 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 10 */
+# define SIM_CLKDIV1_OUTDIV2_DIV11 (10 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 11 */
+# define SIM_CLKDIV1_OUTDIV2_DIV12 (11 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 12 */
+# define SIM_CLKDIV1_OUTDIV2_DIV13 (12 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 13 */
+# define SIM_CLKDIV1_OUTDIV2_DIV14 (13 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 14 */
+# define SIM_CLKDIV1_OUTDIV2_DIV15 (14 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 15 */
+# define SIM_CLKDIV1_OUTDIV2_DIV16 (15 << SIM_CLKDIV1_OUTDIV2_SHIFT) /* Divide by 16 */
+#define SIM_CLKDIV1_OUTDIV1_SHIFT (28) /* Bits 28-31: Clock 1 output divider value */
+#define SIM_CLKDIV1_OUTDIV1_MASK (15 << SIM_CLKDIV1_OUTDIV1_SHIFT)
+# define SIM_CLKDIV1_OUTDIV1_DIV(n) (((n)-1) << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by n, n=1..16 */
+# define SIM_CLKDIV1_OUTDIV1_DIV1 (0 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 1 */
+# define SIM_CLKDIV1_OUTDIV1_DIV2 (1 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 2 */
+# define SIM_CLKDIV1_OUTDIV1_DIV3 (2 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 3 */
+# define SIM_CLKDIV1_OUTDIV1_DIV4 (3 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 4 */
+# define SIM_CLKDIV1_OUTDIV1_DIV5 (4 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 5 */
+# define SIM_CLKDIV1_OUTDIV1_DIV6 (5 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 6 */
+# define SIM_CLKDIV1_OUTDIV1_DIV7 (6 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 7 */
+# define SIM_CLKDIV1_OUTDIV1_DIV8 (7 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 8 */
+# define SIM_CLKDIV1_OUTDIV1_DIV9 (8 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 9 */
+# define SIM_CLKDIV1_OUTDIV1_DIV10 (9 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 10 */
+# define SIM_CLKDIV1_OUTDIV1_DIV11 (10 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 11 */
+# define SIM_CLKDIV1_OUTDIV1_DIV12 (11 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 12 */
+# define SIM_CLKDIV1_OUTDIV1_DIV13 (12 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 13 */
+# define SIM_CLKDIV1_OUTDIV1_DIV14 (13 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 14 */
+# define SIM_CLKDIV1_OUTDIV1_DIV15 (14 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 15 */
+# define SIM_CLKDIV1_OUTDIV1_DIV16 (15 << SIM_CLKDIV1_OUTDIV1_SHIFT) /* Divide by 16 */
+
+/* System Clock Divider Register 2 */
+
+#define SIM_CLKDIV2_USBFRAC (1 << 0) /* Bit 0: USB clock divider fraction */
+#define SIM_CLKDIV2_USBDIV_SHIFT (1) /* Bits 1-3: USB clock divider divisor */
+#define SIM_CLKDIV2_USBDIV_MASK (7 << SIM_CLKDIV2_USBDIV_SHIFT)
+ /* Bits 4-7: Reserved */
+#define SIM_CLKDIV2_I2SFRAC_SHIFT (8) /* Bits 8-15: I2S clock divider fraction */
+#define SIM_CLKDIV2_I2SFRAC_MASK (0xff << SIM_CLKDIV2_I2SFRAC_SHIFT)
+ /* Bits 16-19: Reserved */
+#define SIM_CLKDIV2_I2SDIV_SHIFT (20) /* Bits 20-31: I2S clock divider value */
+#define SIM_CLKDIV2_I2SDIV_MASK (0xfff << SIM_CLKDIV2_I2SDIV_SHIFT)
+
+/* Flash Configuration Register 1 */
+ /* Bits 0-7: Reserved */
+#define SIM_FCFG1_DEPART_SHIFT (8) /* Bits 8-11: FlexNVM partition */
+#define SIM_FCFG1_DEPART_MASK (15 << SIM_FCFG1_DEPART_SHIFT)
+ /* Bits 12-15: Reserved */
+#define SIM_FCFG1_EESIZE_SHIFT (16) /* Bits 16-19: EEPROM size*/
+#define SIM_FCFG1_EESIZE_MASK (15 << SIM_FCFG1_EESIZE_SHIFT)
+# define SIM_FCFG1_EESIZE_4KB (2 << SIM_FCFG1_EESIZE_SHIFT) /* 4 KB */
+# define SIM_FCFG1_EESIZE_2KB (3 << SIM_FCFG1_EESIZE_SHIFT) /* 2 KB */
+# define SIM_FCFG1_EESIZE_1KB (4 << SIM_FCFG1_EESIZE_SHIFT) /* 1 KB */
+# define SIM_FCFG1_EESIZE_512B (5 << SIM_FCFG1_EESIZE_SHIFT) /* 512 Bytes */
+# define SIM_FCFG1_EESIZE_256B (6 << SIM_FCFG1_EESIZE_SHIFT) /* 256 Bytes */
+# define SIM_FCFG1_EESIZE_128B (7 << SIM_FCFG1_EESIZE_SHIFT) /* 128 Bytes */
+# define SIM_FCFG1_EESIZE_64B (8 << SIM_FCFG1_EESIZE_SHIFT) /* 64 Bytes */
+# define SIM_FCFG1_EESIZE_32B (9 << SIM_FCFG1_EESIZE_SHIFT) /* 32 Bytes */
+# define SIM_FCFG1_EESIZE_NONE (15 << SIM_FCFG1_EESIZE_SHIFT) /* 0 Bytes */
+ /* Bits 20-23: Reserved */
+#ifdef KINETIS_K40
+#define SIM_FCFG1_PFSIZE_SHIFT (24) /* Bits 24-27: Program flash size (K40) */
+#define SIM_FCFG1_PFSIZE_MASK (15 << SIM_FCFG1_PFSIZE_SHIFT)
+# define SIM_FCFG1_PFSIZE_128KB (7 << SIM_FCFG1_PFSIZE_SHIFT) /* 128KB program flash, 4KB protection region */
+# define SIM_FCFG1_PFSIZE_256KB (9 << SIM_FCFG1_PFSIZE_SHIFT) /* 256KB program flash, 8KB protection region */
+# define SIM_FCFG1_PFSIZE_512KB (11 << SIM_FCFG1_PFSIZE_SHIFT) /* 512KB program flash, 16KB protection region */
+# define SIM_FCFG1_PFSIZE_512KB2 (15 << SIM_FCFG1_PFSIZE_SHIFT) /* 512KB program flash, 16KB protection region */
+#define SIM_FCFG1_NVMSIZE_SHIFT (28) /* Bits 28-31: FlexNVM size (K40)*/
+#define SIM_FCFG1_NVMSIZE_MASK (15 << SIM_FCFG1_NVMSIZE_SHIFT)
+# define SIM_FCFG1_NVMSIZE_NONE (0 << SIM_FCFG1_NVMSIZE_SHIFT) /* 0KB FlexNVM */
+# define SIM_FCFG1_NVMSIZE_128KB (7 << SIM_FCFG1_NVMSIZE_SHIFT) /* 128KB FlexNVM, 16KB protection region */
+# define SIM_FCFG1_NVMSIZE_256KB (9 << SIM_FCFG1_NVMSIZE_SHIFT) /* 256KB FlexNVM, 32KB protection region */
+# define SIM_FCFG1_NVMSIZE_256KB2 (15 << SIM_FCFG1_NVMSIZE_SHIFT) /* 256KB FlexNVM, 32KB protection region */
+#endif
+
+#ifdef KINETIS_K60
+#define SIM_FCFG1_FSIZE_SHIFT (24) /* Bits 24-31: Flash size (K60)*/
+#define SIM_FCFG1_FSIZE_MASK (0xff << SIM_FCFG1_FSIZE_SHIFT)
+# define SIM_FCFG1_FSIZE_32KB (2 << SIM_FCFG1_FSIZE_SHIFT) /* 32KB program flash, 1KB protection region */
+# define SIM_FCFG1_FSIZE_64KB (4 << SIM_FCFG1_FSIZE_SHIFT) /* 64KB program flash, 2KB protection region */
+# define SIM_FCFG1_FSIZE_128KB (6 << SIM_FCFG1_FSIZE_SHIFT) /* 128KB program flash, 4KB protection region */
+# define SIM_FCFG1_FSIZE_256KB (8 << SIM_FCFG1_FSIZE_SHIFT) /* 256KB program flash, 8KB protection region */
+# define SIM_FCFG1_FSIZE_256KB (12 << SIM_FCFG1_FSIZE_SHIFT) /* 512KB program flash, 16KB protection region */
+#endif
+
+/* Flash Configuration Register 2 */
+ /* Bits 0-15: Reserved */
+#define SIM_FCFG2_MAXADDR1_SHIFT (16) /* Bits 16-21: Max address block 1 */
+#define SIM_FCFG2_MAXADDR1_MASK (nn << SIM_FCFG2_MAXADDR1_SHIFT)
+ /* Bit 22: Reserved */
+#define SIM_FCFG2_PFLSH (1 << 23) /* Bit 23: Program flash */
+#define SIM_FCFG2_MAXADDR0_SHIFT (24) /* Bits 24-29: Max address block 0 */
+#define SIM_FCFG2_MAXADDR0_MASK (nn << SIM_FCFG2_MAXADDR0_SHIFT)
+ /* Bit 30: Reserved */
+#define SIM_FCFG2_SWAPPFLSH (1 << 31) /* Bit 31: Swap program flash */
+
+/* Unique Identification Register High. 32-bit Unique Identification. */
+/* Unique Identification Register Mid-High. 32-bit Unique Identification. */
+/* Unique Identification Register Mid Low. 32-bit Unique Identification. */
+/* Unique Identification Register Low. 32-bit Unique Identification. */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_SIM_H */
diff --git a/arch/arm/src/kinetis/kinetis_smc.h b/arch/arm/src/kinetis/kinetis_smc.h
new file mode 100755
index 0000000000000000000000000000000000000000..b596164b05727a09b9dc8f53ef59147bb77d36b3
--- /dev/null
+++ b/arch/arm/src/kinetis/kinetis_smc.h
@@ -0,0 +1,122 @@
+/************************************************************************************
+ * arch/arm/src/kinetis/kinetis_smc.h
+ *
+ * Copyright (C) 2011 Gregory Nutt. All rights reserved.
+ * Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the
+ * distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ * used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_SMC_H
+#define __ARCH_ARM_SRC_KINETIS_KINETIS_SMC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define KINETIS_SMC_SRSH_OFFSET 0x0000 /* System Reset Status Register High */
+#define KINETIS_SMC_SRSL_OFFSET 0x0001 /* System Reset Status Register Low */
+#define KINETIS_SMC_PMPROT_OFFSET 0x0002 /* Power Mode Protection Register */
+#define KINETIS_SMC_PMCTRL_OFFSET 0x0003 /* Power Mode Control Register */
+
+/* Register Addresses ***************************************************************/
+
+#define KINETIS_SMC_SRSH (KINETIS_SMC_BASE+KINETIS_SMC_SRSH_OFFSET)
+#define KINETIS_SMC_SRSL (KINETIS_SMC_BASE+KINETIS_SMC_SRSL_OFFSET)
+#define KINETIS_SMC_PMPROT (KINETIS_SMC_BASE+KINETIS_SMC_PMPROT_OFFSET)
+#define KINETIS_SMC_PMCTRL (KINETIS_SMC_BASE+KINETIS_SMC_PMCTRL_OFFSET)
+
+/* Register Bit Definitions *********************************************************/
+
+/* System Reset Status Register High */
+
+#define SMC_SRSH_JTAG (1 << 0) /* Bit 0: JTAG generated reset */
+#define SMC_SRSH_LOCKUP (1 << 1) /* Bit 1: Core Lock-up */
+#define SMC_SRSH_SW (1 << 2) /* Bit 2: Software */
+ /* Bits 3-7: Reserved */
+
+/* System Reset Status Register Low */
+
+#define SMC_SRSL_WAKEUP (1 << 0) /* Bit 0: Low-leakage wakeup reset */
+#define SMC_SRSL_LVD (1 << 1) /* Bit 1: Low-voltage detect reset */
+#define SMC_SRSL_LOC (1 << 2) /* Bit 2: Loss-of-clock reset */
+ /* Bits 3-4: Reserved */
+#define SMC_SRSL_COP (1 << 5) /* Bit 5: Computer Operating Properly (COP) Watchdog */
+#define SMC_SRSL_PIN (1 << 6) /* Bit 6: External reset pin */
+#define SMC_SRSL_POR (1 << 7) /* Bit 7: Power-on reset */
+
+/* Power Mode Protection Register */
+
+#define SMC_PMPROT_AVLLS1 (1 << 0) /* Bit 0: Allow very low leakage stop 1 mod */
+#define SMC_PMPROT_AVLLS2 (1 << 1) /* Bit 1: Allow very low leakage stop 2 mode */
+#define SMC_PMPROT_AVLLS3 (1 << 2) /* Bit 2: Allow Very Low Leakage Stop 3 Mode */
+ /* Bit 3: Reserved */
+#define SMC_PMPROT_ALLS (1 << 4) /* Bit 4: Allow low leakage stop mode */
+#define SMC_PMPROT_AVLP (1 << 5) /* Bit 5: Allow very low power modes */
+ /* Bits 6-7: Reserved */
+/* Power Mode Control Register */
+
+#define SMC_PMCTRL_LPLLSM_SHIFT (0) /* Bits 0-2: Low Power, Low Leakage Stop Mode */
+#define SMC_PMCTRL_LPLLSM_MASK (7 << SMC_PMCTRL_LPLLSM_SHIFT)
+# define SMC_PMCTRL_LPLLSM_NORMAL (0 << SMC_PMCTRL_LPLLSM_SHIFT) /* Normal stop */
+# define SMC_PMCTRL_LPLLSM_VLPS (2 << SMC_PMCTRL_LPLLSM_SHIFT) /* Very low power stop */
+# define SMC_PMCTRL_LPLLSM_LLS (3 << SMC_PMCTRL_LPLLSM_SHIFT) /* Low leakage stop */
+# define SMC_PMCTRL_LPLLSM_VLLS3 (5 << SMC_PMCTRL_LPLLSM_SHIFT) /* Very low leakage stop 3 */
+# define SMC_PMCTRL_LPLLSM_VLLS2 (6 << SMC_PMCTRL_LPLLSM_SHIFT) /* Very low leakage stop 2 */
+# define SMC_PMCTRL_LPLLSM_VLLS1 (7 << SMC_PMCTRL_LPLLSM_SHIFT) /* Very low leakage stop 1 */
+ /* Bits 3-4: Reserved */
+#define SMC_PMCTRL_RUNM_SHIFT (5) /* Bits 5-6: Run Mode Enable */
+#define SMC_PMCTRL_RUNM_MASK (3 << SMC_PMCTRL_RUNM_SHIFT)
+# define SMC_PMCTRL_RUNM_NORMAL (0 << SMC_PMCTRL_RUNM_SHIFT) /* Normal run mode */
+# define SMC_PMCTRL_RUNM_VLP (2 << SMC_PMCTRL_RUNM_SHIFT) /* Very low power run mode */
+#define SMC_PMCTRL_LPWUI (1 << 7) /* Bit 7: Low Power Wake Up on Interrupt */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_SMC_H */
diff --git a/configs/kwikstik-k40/README.txt b/configs/kwikstik-k40/README.txt
index ef0bdbf77cc3e93d692e700620901b0e3aca3418..3c58a8973868f8472880a5168d73ef66b82cd1ff 100644
--- a/configs/kwikstik-k40/README.txt
+++ b/configs/kwikstik-k40/README.txt
@@ -253,68 +253,56 @@ KwikStik-K40-specific Configuration Options
the delay actually is 100 seconds.
Individual subsystems can be enabled:
- AHB
- ---
- CONFIG_KINETIS_DMA1
- CONFIG_KINETIS_DMA2
- CONFIG_KINETIS_CRC
- CONFIG_KINETIS_FSMC
- CONFIG_KINETIS_SDIO
-
- APB1
- ----
- CONFIG_KINETIS_TIM2
- CONFIG_KINETIS_TIM3
- CONFIG_KINETIS_TIM4
- CONFIG_KINETIS_TIM5
- CONFIG_KINETIS_TIM6
- CONFIG_KINETIS_TIM7
- CONFIG_KINETIS_WWDG
- CONFIG_KINETIS_SPI2
- CONFIG_KINETIS_SPI4
- CONFIG_KINETIS_USART2
- CONFIG_KINETIS_USART3
- CONFIG_KINETIS_UART4
- CONFIG_KINETIS_UART5
- CONFIG_KINETIS_I2C1
- CONFIG_KINETIS_I2C2
- CONFIG_KINETIS_USB
- CONFIG_KINETIS_CAN
- CONFIG_KINETIS_BKP
- CONFIG_KINETIS_PWR
- CONFIG_KINETIS_DAC
- CONFIG_KINETIS_USB
-
- APB2
- ----
- CONFIG_KINETIS_ADC1
- CONFIG_KINETIS_ADC2
- CONFIG_KINETIS_TIM1
- CONFIG_KINETIS_SPI1
- CONFIG_KINETIS_TIM8
- CONFIG_KINETIS_USART1
- CONFIG_KINETIS_ADC3
-
- Alternate pin mappings (should not be used with the KwikStik-K40 board):
-
- CONFIG_KINETIS_TIM1_FULL_REMAP
- CONFIG_KINETIS_TIM1_PARTIAL_REMAP
- CONFIG_KINETIS_TIM2_FULL_REMAP
- CONFIG_KINETIS_TIM2_PARTIAL_REMAP_1
- CONFIG_KINETIS_TIM2_PARTIAL_REMAP_2
- CONFIG_KINETIS_TIM3_FULL_REMAP
- CONFIG_KINETIS_TIM3_PARTIAL_REMAP
- CONFIG_KINETIS_TIM4_REMAP
- CONFIG_KINETIS_USART1_REMAP
- CONFIG_KINETIS_USART2_REMAP
- CONFIG_KINETIS_USART3_FULL_REMAP
- CONFIG_KINETIS_USART3_PARTIAL_REMAP
- CONFIG_KINETIS_SPI1_REMAP
- CONFIG_KINETIS_SPI3_REMAP
- CONFIG_KINETIS_I2C1_REMAP
- CONFIG_KINETIS_CAN1_FULL_REMAP
- CONFIG_KINETIS_CAN1_PARTIAL_REMAP
- CONFIG_KINETIS_CAN2_REMAP
+
+ CONFIG_KINETIS_UART0
+ CONFIG_KINETIS_UART1
+ CONFIG_KINETIS_UART2
+ CONFIG_KINETIS_UART3
+ CONFIG_KINETIS_UART4
+ CONFIG_KINETIS_UART5
+ CONFIG_KINETIS_ETHERNET (K60 only)
+ CONFIG_KINETIS_RNGB (K60 only)
+ CONFIG_KINETIS_FLEXCAN0
+ CONFIG_KINETIS_FLEXCAN1
+ CONFIG_KINETIS_SPI0
+ CONFIG_KINETIS_SPI1
+ CONFIG_KINETIS_SPI2
+ CONFIG_KINETIS_I2C0
+ CONFIG_KINETIS_I2C1
+ CONFIG_KINETIS_I2S
+ CONFIG_KINETIS_DAC0
+ CONFIG_KINETIS_DAC1
+ CONFIG_KINETIS_ADC0
+ CONFIG_KINETIS_ADC1
+ CONFIG_KINETIS_CMP
+ CONFIG_KINETIS_VREF
+ CONFIG_KINETIS_SDHC
+ CONFIG_KINETIS_FTM0
+ CONFIG_KINETIS_FTM1
+ CONFIG_KINETIS_FTM2
+ CONFIG_KINETIS_LPTIMER
+ CONFIG_KINETIS_RTC
+ CONFIG_KINETIS_SLCD (K40 only)
+ CONFIG_KINETIS_EWM
+ CONFIG_KINETIS_CMT
+ CONFIG_KINETIS_USBOTG
+ CONFIG_KINETIS_USBDCD
+ CONFIG_KINETIS_LLWU
+ CONFIG_KINETIS_REGFILE
+ CONFIG_KINETIS_TSI
+ CONFIG_KINETIS_PORTA
+ CONFIG_KINETIS_PORTB
+ CONFIG_KINETIS_PORTC
+ CONFIG_KINETIS_PORTD
+ CONFIG_KINETIS_PORTE
+ CONFIG_KINETIS_FTFL
+ CONFIG_KINETIS_DMA
+ CONFIG_KINETIS_DMAMUX
+ CONFIG_KINETIS_CRC
+ CONFIG_KINETIS_PDB
+ CONFIG_KINETIS_PIT
+ CONFIG_KINETIS_FLEXBUS
+ CONFIG_KINETIS_MPU
Kinetis K40 specific device driver settings