diff --git a/arch/arm/include/lm3s/irq.h b/arch/arm/include/lm3s/irq.h
index de11a602bb9f02a621bc6e544d50a3150c3a55fd..e65540e9768cc71bf0d7c136822c5ea0957f29ce 100644
--- a/arch/arm/include/lm3s/irq.h
+++ b/arch/arm/include/lm3s/irq.h
@@ -264,6 +264,7 @@
# define LM3S_IRQ_ETHCON (58) /* Vector 58: Ethernet Controller */
# define LM3S_IRQ_HIBERNATE (59) /* Vector 59: Hibernation Module */
/* Vectors 60-70: Reserved */
+# define NR_IRQS (60) /* (Really less because of reserved vectors) */
#else
# error "IRQ Numbers not specified for this LM3S chip"
#endif
diff --git a/arch/arm/src/lm3s/lm3s_memorymap.h b/arch/arm/src/lm3s/lm3s_memorymap.h
index 67f5e758f6f02d8c9de855425e5e9a58e9515483..31b4c620594bf5c2da179b3ce1defe2f6fe103da 100644
--- a/arch/arm/src/lm3s/lm3s_memorymap.h
+++ b/arch/arm/src/lm3s/lm3s_memorymap.h
@@ -48,7 +48,7 @@
/* Memory map ***********************************************************************/
-#if defined(CONFIG_ARCH_CHIP_LM3S6918) || defined(CONFIG_ARCH_CHIP_LM3S6965)
+#if defined(CONFIG_ARCH_CHIP_LM3S6918) || defined(CONFIG_ARCH_CHIP_LM3S6965) || defined(CONFIG_ARCH_CHIP_LM3S8962)
# define LM3S_FLASH_BASE 0x00000000 /* -0x0003ffff: On-chip FLASH */
/* -0x1fffffff: Reserved */
# define LM3S_SRAM_BASE 0x20000000 /* -0x2000ffff: Bit-banded on-chip SRAM */
@@ -184,6 +184,51 @@
/* -0xfcfff: Reserved */
# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Ethernet Controller */
# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
+# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
+ /* -0x1ffffff: Reserved */
+#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
+/* FiRM Peripheral Base Addresses */
+
+# define LM3S_WDOG_BASE (LM3S_PERIPH_BASE + 0x00000) /* -0x00fff: Watchdog Timer */
+ /* -0x03fff: Reserved */
+# define LM3S_GPIOA_BASE (LM3S_PERIPH_BASE + 0x04000) /* -0x04fff: GPIO Port A */
+# define LM3S_GPIOB_BASE (LM3S_PERIPH_BASE + 0x05000) /* -0x05fff: GPIO Port B */
+# define LM3S_GPIOC_BASE (LM3S_PERIPH_BASE + 0x06000) /* -0x06fff: GPIO Port C */
+# define LM3S_GPIOD_BASE (LM3S_PERIPH_BASE + 0x07000) /* -0x07fff: GPIO Port D */
+# define LM3S_SSI0_BASE (LM3S_PERIPH_BASE + 0x08000) /* -0x08fff: SSI0 */
+ /* -0x0bfff: Reserved */
+# define LM3S_UART0_BASE (LM3S_PERIPH_BASE + 0x0c000) /* -0x0cfff: UART0 */
+# define LM3S_UART1_BASE (LM3S_PERIPH_BASE + 0x0d000) /* -0x0dfff: UART1 */
+ /* -0x1ffff: Reserved */
+/* Peripheral Base Addresses */
+
+# define LM3S_I2CM0_BASE (LM3S_PERIPH_BASE + 0x20000) /* -0x207ff: I2C Master 0 */
+# define LM3S_I2CS0_BASE (LM3S_PERIPH_BASE + 0x20800) /* -0x20fff: I2C Slave 0 */
+ /* -0x23fff: Reserved */
+# define LM3S_GPIOE_BASE (LM3S_PERIPH_BASE + 0x24000) /* -0x24fff: GPIO Port E */
+# define LM3S_GPIOF_BASE (LM3S_PERIPH_BASE + 0x25000) /* -0x25fff: GPIO Port F */
+# define LM3S_GPIOG_BASE (LM3S_PERIPH_BASE + 0x26000) /* -0x26fff: GPIO Port G */
+ /* -0x27fff: Reserved */
+# define LM3S_PWM0_BASE (LM3S_PERIPH_BASE + 0x28000) /* -0x28fff: PWM */
+ /* -0x2bfff: Reserved */
+# define LM3S_QEI0_BASE (LM3S_PERIPH_BASE + 0x2c000) /* -0x2cfff: QEI0 */
+# define LM3S_QEI1_BASE (LM3S_PERIPH_BASE + 0x2d000) /* -0x2dfff: QEI1 */
+ /* -0x2ffff: Reserved */
+# define LM3S_TIMER0_BASE (LM3S_PERIPH_BASE + 0x30000) /* -0x30fff: Timer 0 */
+# define LM3S_TIMER1_BASE (LM3S_PERIPH_BASE + 0x31000) /* -0x31fff: Timer 1 */
+# define LM3S_TIMER2_BASE (LM3S_PERIPH_BASE + 0x32000) /* -0x32fff: Timer 2 */
+# define LM3S_TIMER3_BASE (LM3S_PERIPH_BASE + 0x33000) /* -0x33fff: Timer 3 */
+ /* -0x37fff: Reserved */
+# define LM3S_ADC_BASE (LM3S_PERIPH_BASE + 0x38000) /* -0x38fff: ADC */
+ /* -0x3bfff: Reserved */
+# define LM3S_COMPARE_BASE (LM3S_PERIPH_BASE + 0x3c000) /* -0x3cfff: Analog Comparators */
+ /* -0x3fffff: Reserved */
+# define LM3S_CANCON_BASE (LM3S_PERIPH_BASE + 0x40000) /* -0x40fff: CAN Controller */
+ /* -0x47fff: Reserved */
+# define LM3S_ETHCON_BASE (LM3S_PERIPH_BASE + 0x48000) /* -0x48fff: Ethernet Controller */
+ /* -0xfcfff: Reserved */
+# define LM3S_HIBERNATE_BASE (LM3S_PERIPH_BASE + 0xfc000) /* -0xfcfff: Hibernation Controller */
+# define LM3S_FLASHCON_BASE (LM3S_PERIPH_BASE + 0xfd000) /* -0xfdfff: FLASH Control */
# define LM3S_SYSCON_BASE (LM3S_PERIPH_BASE + 0xfe000) /* -0xfefff: System Control */
/* -0x1ffffff: Reserved */
#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
diff --git a/arch/arm/src/lm3s/lm3s_vectors.S b/arch/arm/src/lm3s/lm3s_vectors.S
index fe839bc4894745492019fe39cb99ce1dcdf0a8ab..5d6f7962e9b109614049a3f431299da9c9420903 100644
--- a/arch/arm/src/lm3s/lm3s_vectors.S
+++ b/arch/arm/src/lm3s/lm3s_vectors.S
@@ -449,7 +449,7 @@ handlers:
HANDLER lm3s_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */
HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */
HANDLER lm3s_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */
- #elif defined(CONFIG_ARCH_CHIP_LM3S8962)
+#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
HANDLER lm3s_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */
HANDLER lm3s_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */
HANDLER lm3s_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */
@@ -476,7 +476,6 @@ handlers:
HANDLER lm3s_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */
HANDLER lm3s_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */
HANDLER lm3s_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */
- HANDLER lm3s_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */
HANDLER lm3s_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */
HANDLER lm3s_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */
HANDLER lm3s_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */
@@ -486,6 +485,7 @@ handlers:
HANDLER lm3s_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */
HANDLER lm3s_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */
HANDLER lm3s_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */
+ HANDLER lm3s_can0, LM3S_IRQ_CAN0 /* Vector 55: CAN 0 */
HANDLER lm3s_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */
HANDLER lm3s_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */
#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)