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Commits on Source (7)
  • Michael Jung's avatar
  • Ivan Ucherdzhiev's avatar
  • Gregory Nutt's avatar
    Squashed commit of the following: · 1cf67634
    Gregory Nutt authored
        arch/arm/src/imxrt:  Add structures to support list of TCDs for Scatter/Gather DMA.
        arch/arm/src/imxrt:  Add eDMA imxrt_dmach_initconfig().
        arch/arm/src/imxrt:  Add eDMA imxrt_tcd_instantiate().
        arch/arm/src/imxrt:  Replacing some of the logic cloned from SAMv7 XDMAC with eDMA logic from NXP sample code.  I am thinking that the eDMA is too complex to force into the same pattern as for other MCUs.
        arch/arms/src/imxrt/imxrt_edma.c:  Add support for in-memory TCDs.
        arch/arm/src/imxrt/chip:  Add an in-memory representation of the TCD in imxrt_edma.h
    1cf67634
  • Gregory Nutt's avatar
    Squashed commit of the following: · 890656f0
    Gregory Nutt authored
        arch/arm/src/imxrt:  Fixes for clean eDMA driver build with Scatter/Gather enabled.
        arch/arm/src/imxrt:  Fixes for clean eDMA driver build with Scatter/Gather disabled.
        arch/arm/src/imxrt:  Add flags to DMA configuration to control transfer setup.  Remove some user interfaces that are inconsistent with modular design.
        arch/arm/src/imxrt:  Update DMA channel interrupt handler.
        arch/arm/src/imxrt:  Add implementation of eDMA imxrt_dmach_start().
        arch/arm/src/imxrt:  Add implementation of eDMA imxrt_dmach_setup().
        arch/arm/src/imxrt:  Add eDMA imxrt_tcd_chanlink().
        arch/arm/src/imxrt:  Add eDMA imxrt_dmach_getcount; free allocated TCDs automatically when the DMA completes or is aborted.
    890656f0
  • Gregory Nutt's avatar
    Squashed commit of the following: · db0cdfc4
    Gregory Nutt authored
        arch/arm/src/imxrt:  May eDMA channel linking a configuration option.  Add support to select the DMA channel priority and pre-emption controls.
        arch/arm/src/imxrt:  Update some HowTo comments in the eDMA header file.
        arch/arm/src/imxrt:  Fix a logic error in parmater passing.  Caller does not know actual channel number when setting up linked channel, only the channel handler.
    db0cdfc4
  • Gregory Nutt's avatar
  • Gregory Nutt's avatar
    fs/fat: In fs_stat(), when stat'ing the root directory, avoid calculating the... · b3f20f8c
    Gregory Nutt authored
    fs/fat: In fs_stat(), when stat'ing the root directory, avoid calculating the address of the root directory entry.  The calculation is bogus (but not harmful) because the root directory does not have a directory entry.  Noted by Boris Astardzhiev.
    b3f20f8c
......@@ -64,18 +64,17 @@ config IMXRT_HAVE_LPUART
menu "i.MX RT Peripheral Selection"
config IMXRT_EDMA
bool "eDMA"
default n
select ARCH_DMA
menu "FlexIO Peripherals"
endmenu # FlexIO Peripherals
menu "LPUART Peripherals"
config IMXRT_EDMA
bool "eDMA"
default n
select ARCH_DMA
depends on EXPERIMENTAL
config IMXRT_LPUART1
bool "LPUART1"
default n
......@@ -337,25 +336,81 @@ endmenu # Memory Configuration
menu "eDMA Configuration"
depends on IMXRT_EDMA
config IMXRT_EDMA_NTCD
int "Number of transfer descriptors"
default 0
---help---
Number of pre-allocated transfer descriptors. Needed for scatter-
gather DMA. Make to be set to zero to disable in-memory TCDs in
which case only the TCD channel registers will be used and scatter-
will not be supported.
config IMXRT_EDMA_ELINK
bool "Channeling Linking"
default n
---help---
This option enables optional minor or major loop channel linking:
Minor loop channel linking: As the channel completes the minor
loop, this flag enables linking to another channel. The link target
channel initiates a channel service request via an internal
mechanism that sets the TCDn_CSR[START] bit of the specified
channel.
If minor loop channel linking is disabled, this link mechanism is
suppressed in favor of the major loop channel linking.
Major loop channel linking: As the channel completes the minor
loop, this option enables the linking to another channel. The link
target channel initiates a channel service request via an internal
mechanism that sets the TCDn_CSR[START] bit of the linked channel.
config IMXRT_EDMA_ERCA
bool "Round Robin Channel Arbitration"
default n
---help---
Normally, a fixed priority arbitration is used for channel
selection. If this option is selected, round robin arbitration is
used for channel selection.
config IMXRT_EDMA_HOE
bool "Halt On Error"
default y
---help---
Any error causes the HALT bit to set. Subsequently, all service
requests are ignored until the HALT bit is cleared.
config IMXRT_EDMA_CLM
bool "Continuous Link Mode"
default n
---help---
By default, A minor loop channel link made to itself goes through
channel arbitration before being activated again. If this option is
selected, a minor loop channel link made to itself does not go
through channel arbitration before being activated again. Upon minor
loop completion, the channel activates again if that channel has a
minor loop channel link enabled and the link channel is itself. This
effectively applies the minor loop offsets and restarts the next
minor loop.
config IMXRT_EDMA_EMLIM
bool "Minor Loop Mapping"
default n
---help---
Normally TCD word 2 is a 32-bit NBYTES field. When this option is
enabled, TCD word 2 is redefined to include individual enable fields,
an offset field, and the NBYTES field. The individual enable fields
allow the minor loop offset to be applied to the source address, the
destination address, or both. The NBYTES field is reduced when either
offset is enabled.
config IMXRT_EDMA_EDBG
bool "Enable Debug"
default n
---help---
When in debug mode, the DMA stalls the start of a new channel. Executing
channels are allowed to complete. Channel execution resumes when the
system exits debug mode or the EDBG bit is cleared
endmenu # eDMA Global Configuration
endif # ARCH_CHIP_IMXRT
......@@ -89,10 +89,10 @@
#define IMXRT_DMACHAN_FLEXPWM3_RX1 41 /* FlexPWM3 RX sub-module1 capture */
#define IMXRT_DMACHAN_FLEXPWM3_RX2 42 /* FlexPWM3 RX sub-module2 capture */
#define IMXRT_DMACHAN_FLEXPWM3_RX3 43 /* FlexPWM3 RX sub-module3 capture */
#define IMXRT_DMACHAN_FLEXPWM1_TX0 44 /* FlexPWM3 TX sub-module0 value */
#define IMXRT_DMACHAN_FLEXPWM1_TX1 45 /* FlexPWM3 TX sub-module1 value */
#define IMXRT_DMACHAN_FLEXPWM1_TX2 46 /* FlexPWM3 TX sub-module2 value */
#define IMXRT_DMACHAN_FLEXPWM1_TX3 47 /* FlexPWM3 TX sub-module3 value */
#define IMXRT_DMACHAN_FLEXPWM3_TX0 44 /* FlexPWM3 TX sub-module0 value */
#define IMXRT_DMACHAN_FLEXPWM3_TX1 45 /* FlexPWM3 TX sub-module1 value */
#define IMXRT_DMACHAN_FLEXPWM3_TX2 46 /* FlexPWM3 TX sub-module2 value */
#define IMXRT_DMACHAN_FLEXPWM3_TX3 47 /* FlexPWM3 TX sub-module3 value */
#define IMXRT_DMACHAN_QTIMER1_RX0 48 /* QTimer1 RX capture timer 0 */
#define IMXRT_DMACHAN_QTIMER1_RX1 49 /* QTimer1 RX capture timer 1 */
#define IMXRT_DMACHAN_QTIMER1_RX2 50 /* QTimer1 RX capture timer 2 */
......
......@@ -120,7 +120,7 @@
/* 0x400e0000 16KB Reserved */
/* 0x400e4000 16KB Reserved */
#define IMXRT_EDMA_BASE 0x400e8000 /* 16KB EDMA */
#define IMXRT_DMACHMUX_BASE 0x400ec000 /* 16KB DMA_CH_MUX */
#define IMXRT_DMAMUX_BASE 0x400ec000 /* 16KB DMA_CH_MUX */
/* 400f0000 16KB Reserved */
#define IMXRT_GPC_BASE 0x400f4000 /* 16KB GPC */
#define IMXRT_SRC_BASE 0x400f8000 /* 16KB SRC */
......
......@@ -93,7 +93,7 @@
/* DMAMUX Register Addresses ********************************************************/
#define IMXRT_DMAMUX_CHCF(n) (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG_OFFSET(n))
#define IMXRT_DMAMUX_CHCFG(n) (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG_OFFSET(n))
# define IMXRT_DMAMUX_CHCFG0 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG0_OFFSET)
# define IMXRT_DMAMUX_CHCFG1 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG1_OFFSET)
# define IMXRT_DMAMUX_CHCFG2 (IMXRT_DMAMUX_BASE + IMXRT_DMAMUX_CHCFG2_OFFSET)
......
......@@ -44,7 +44,7 @@
#include "chip/imxrt_memorymap.h"
/****************************************************************************************************
* Pre-processor definitions
* Pre-processor Definitions
****************************************************************************************************/
#define IMXRT_EDMA_NCHANNELS 32
......@@ -70,38 +70,40 @@
#define IMXRT_EDMA_DCHPRI_OFFSET(n) (0x0100 + ((n) & ~3) + (3 - ((n) & 3)))
#define IMXRT_EDMA_DCHPRI3_OFFSET 0x0100 /* Channel 0 Priority */
#define IMXRT_EDMA_DCHPRI2_OFFSET 0x0101 /* Channel 1 Priority */
#define IMXRT_EDMA_DCHPRI1_OFFSET 0x0102 /* Channel 2 Priority */
#define IMXRT_EDMA_DCHPRI0_OFFSET 0x0103 /* Channel 3 Priority */
#define IMXRT_EDMA_DCHPRI7_OFFSET 0x0104 /* Channel 4 Priority */
#define IMXRT_EDMA_DCHPRI6_OFFSET 0x0105 /* Channel 5 Priority */
#define IMXRT_EDMA_DCHPRI5_OFFSET 0x0106 /* Channel 6 Priority */
#define IMXRT_EDMA_DCHPRI4_OFFSET 0x0107 /* Channel 7 Priority */
#define IMXRT_EDMA_DCHPRI11_OFFSET 0x0108 /* Channel 8 Priority */
#define IMXRT_EDMA_DCHPRI10_OFFSET 0x0109 /* Channel 9 Priority */
#define IMXRT_EDMA_DCHPRI9_OFFSET 0x010a /* Channel 0 Priority */
#define IMXRT_EDMA_DCHPRI8_OFFSET 0x010b /* Channel 1 Priority */
#define IMXRT_EDMA_DCHPRI15_OFFSET 0x010c /* Channel 2 Priority */
#define IMXRT_EDMA_DCHPRI14_OFFSET 0x010d /* Channel 3 Priority */
#define IMXRT_EDMA_DCHPRI13_OFFSET 0x010e /* Channel 4 Priority */
#define IMXRT_EDMA_DCHPRI12_OFFSET 0x010f /* Channel 5 Priority */
#define IMXRT_EDMA_DCHPRI19_OFFSET 0x0110 /* Channel 6 Priority */
#define IMXRT_EDMA_DCHPRI18_OFFSET 0x0111 /* Channel 7 Priority */
#define IMXRT_EDMA_DCHPRI17_OFFSET 0x0112 /* Channel 8 Priority */
#define IMXRT_EDMA_DCHPRI16_OFFSET 0x0113 /* Channel 9 Priority */
#define IMXRT_EDMA_DCHPRI23_OFFSET 0x0114 /* Channel 0 Priority */
#define IMXRT_EDMA_DCHPRI22_OFFSET 0x0115 /* Channel 1 Priority */
#define IMXRT_EDMA_DCHPRI21_OFFSET 0x0116 /* Channel 2 Priority */
#define IMXRT_EDMA_DCHPRI20_OFFSET 0x0117 /* Channel 3 Priority */
#define IMXRT_EDMA_DCHPRI27_OFFSET 0x0118 /* Channel 4 Priority */
#define IMXRT_EDMA_DCHPRI26_OFFSET 0x0119 /* Channel 5 Priority */
#define IMXRT_EDMA_DCHPRI25_OFFSET 0x011a /* Channel 6 Priority */
#define IMXRT_EDMA_DCHPRI24_OFFSET 0x011b /* Channel 7 Priority */
#define IMXRT_EDMA_DCHPRI31_OFFSET 0x011c /* Channel 8 Priority */
#define IMXRT_EDMA_DCHPRI30_OFFSET 0x011d /* Channel 9 Priority */
#define IMXRT_EDMA_DCHPRI29_OFFSET 0x011e /* Channel 0 Priority */
#define IMXRT_EDMA_DCHPRI28_OFFSET 0x011f /* Channel 1 Priority */
#define IMXRT_EDMA_DCHPRI3_OFFSET 0x0100 /* Channel 3 Priority */
#define IMXRT_EDMA_DCHPRI2_OFFSET 0x0101 /* Channel 2 Priority */
#define IMXRT_EDMA_DCHPRI1_OFFSET 0x0102 /* Channel 1 Priority */
#define IMXRT_EDMA_DCHPRI0_OFFSET 0x0103 /* Channel 0 Priority */
#define IMXRT_EDMA_DCHPRI7_OFFSET 0x0104 /* Channel 7 Priority */
#define IMXRT_EDMA_DCHPRI6_OFFSET 0x0105 /* Channel 6 Priority */
#define IMXRT_EDMA_DCHPRI5_OFFSET 0x0106 /* Channel 5 Priority */
#define IMXRT_EDMA_DCHPRI4_OFFSET 0x0107 /* Channel 4 Priority */
#define IMXRT_EDMA_DCHPRI11_OFFSET 0x0108 /* Channel 11 Priority */
#define IMXRT_EDMA_DCHPRI10_OFFSET 0x0109 /* Channel 10 Priority */
#define IMXRT_EDMA_DCHPRI9_OFFSET 0x010a /* Channel 9 Priority */
#define IMXRT_EDMA_DCHPRI8_OFFSET 0x010b /* Channel 8 Priority */
#define IMXRT_EDMA_DCHPRI15_OFFSET 0x010c /* Channel 15 Priority */
#define IMXRT_EDMA_DCHPRI14_OFFSET 0x010d /* Channel 14 Priority */
#define IMXRT_EDMA_DCHPRI13_OFFSET 0x010e /* Channel 13 Priority */
#define IMXRT_EDMA_DCHPRI12_OFFSET 0x010f /* Channel 12 Priority */
#define IMXRT_EDMA_DCHPRI19_OFFSET 0x0110 /* Channel 19 Priority */
#define IMXRT_EDMA_DCHPRI18_OFFSET 0x0111 /* Channel 18 Priority */
#define IMXRT_EDMA_DCHPRI17_OFFSET 0x0112 /* Channel 17 Priority */
#define IMXRT_EDMA_DCHPRI16_OFFSET 0x0113 /* Channel 16 Priority */
#define IMXRT_EDMA_DCHPRI23_OFFSET 0x0114 /* Channel 23 Priority */
#define IMXRT_EDMA_DCHPRI22_OFFSET 0x0115 /* Channel 22 Priority */
#define IMXRT_EDMA_DCHPRI21_OFFSET 0x0116 /* Channel 21 Priority */
#define IMXRT_EDMA_DCHPRI20_OFFSET 0x0117 /* Channel 20 Priority */
#define IMXRT_EDMA_DCHPRI27_OFFSET 0x0118 /* Channel 27 Priority */
#define IMXRT_EDMA_DCHPRI26_OFFSET 0x0119 /* Channel 26 Priority */
#define IMXRT_EDMA_DCHPRI25_OFFSET 0x011a /* Channel 25 Priority */
#define IMXRT_EDMA_DCHPRI24_OFFSET 0x011b /* Channel 24 Priority */
#define IMXRT_EDMA_DCHPRI31_OFFSET 0x011c /* Channel 31 Priority */
#define IMXRT_EDMA_DCHPRI30_OFFSET 0x011d /* Channel 30 Priority */
#define IMXRT_EDMA_DCHPRI29_OFFSET 0x011e /* Channel 29 Priority */
#define IMXRT_EDMA_DCHPRI28_OFFSET 0x011f /* Channel 28 Priority */
/* Transfer Control Descriptor (TCD) */
#define IMXRT_EDMA_TCD_OFFSET(n) (0x1000 + ((n) << 5))
#define IMXRT_EDMA_TCD_SADDR_OFFSET 0x0000 /* TCD Source Address */
......@@ -537,34 +539,69 @@
#define IMXRT_EDMA_DCHPRI1 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI1_OFFSET)
#define IMXRT_EDMA_DCHPRI2 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI2_OFFSET)
#define IMXRT_EDMA_DCHPRI3 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI3_OFFSET)
#define IMXRT_EDMA_DCHPRI7 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI7_OFFSET)
#define IMXRT_EDMA_DCHPRI6 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI6_OFFSET)
#define IMXRT_EDMA_DCHPRI5 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI5_OFFSET)
#define IMXRT_EDMA_DCHPRI4 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI4_OFFSET)
#define IMXRT_EDMA_DCHPRI11 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI11_OFFSET)
#define IMXRT_EDMA_DCHPRI5 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI5_OFFSET)
#define IMXRT_EDMA_DCHPRI6 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI6_OFFSET)
#define IMXRT_EDMA_DCHPRI7 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI7_OFFSET)
#define IMXRT_EDMA_DCHPRI8 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI8_OFFSET)
#define IMXRT_EDMA_DCHPRI9 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI9_OFFSET)
#define IMXRT_EDMA_DCHPRI10 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI10_OFFSET)
#define IMXRT_EDMA_DCHPRI9 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI8_OFFSET)
#define IMXRT_EDMA_DCHPRI8 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI9_OFFSET)
#define IMXRT_EDMA_DCHPRI15 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI0_OFFSET)
#define IMXRT_EDMA_DCHPRI14 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI1_OFFSET)
#define IMXRT_EDMA_DCHPRI13 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI2_OFFSET)
#define IMXRT_EDMA_DCHPRI12 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI3_OFFSET)
#define IMXRT_EDMA_DCHPRI19 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI0_OFFSET)
#define IMXRT_EDMA_DCHPRI18 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI1_OFFSET)
#define IMXRT_EDMA_DCHPRI17 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI2_OFFSET)
#define IMXRT_EDMA_DCHPRI16 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI3_OFFSET)
#define IMXRT_EDMA_DCHPRI23 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI0_OFFSET)
#define IMXRT_EDMA_DCHPRI22 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI1_OFFSET)
#define IMXRT_EDMA_DCHPRI21 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI2_OFFSET)
#define IMXRT_EDMA_DCHPRI10 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI3_OFFSET)
#define IMXRT_EDMA_DCHPRI27 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI0_OFFSET)
#define IMXRT_EDMA_DCHPRI26 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI1_OFFSET)
#define IMXRT_EDMA_DCHPRI25 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI2_OFFSET)
#define IMXRT_EDMA_DCHPRI24 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI3_OFFSET)
#define IMXRT_EDMA_DCHPRI31 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI0_OFFSET)
#define IMXRT_EDMA_DCHPRI30 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI1_OFFSET)
#define IMXRT_EDMA_DCHPRI29 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI2_OFFSET)
#define IMXRT_EDMA_DCHPRI28 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI3_OFFSET)
#define IMXRT_EDMA_DCHPRI11 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI11_OFFSET)
#define IMXRT_EDMA_DCHPRI12 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI12_OFFSET)
#define IMXRT_EDMA_DCHPRI13 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI13_OFFSET)
#define IMXRT_EDMA_DCHPRI14 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI14_OFFSET)
#define IMXRT_EDMA_DCHPRI15 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI15_OFFSET)
#define IMXRT_EDMA_DCHPRI16 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI16_OFFSET)
#define IMXRT_EDMA_DCHPRI17 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI17_OFFSET)
#define IMXRT_EDMA_DCHPRI18 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI18_OFFSET)
#define IMXRT_EDMA_DCHPRI19 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI19_OFFSET)
#define IMXRT_EDMA_DCHPRI20 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI20_OFFSET)
#define IMXRT_EDMA_DCHPRI21 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI21_OFFSET)
#define IMXRT_EDMA_DCHPRI22 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI22_OFFSET)
#define IMXRT_EDMA_DCHPRI23 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI23_OFFSET)
#define IMXRT_EDMA_DCHPRI24 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI24_OFFSET)
#define IMXRT_EDMA_DCHPRI25 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI25_OFFSET)
#define IMXRT_EDMA_DCHPRI26 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI26_OFFSET)
#define IMXRT_EDMA_DCHPRI27 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI27_OFFSET)
#define IMXRT_EDMA_DCHPRI28 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI28_OFFSET)
#define IMXRT_EDMA_DCHPRI29 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI29_OFFSET)
#define IMXRT_EDMA_DCHPRI30 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI30_OFFSET)
#define IMXRT_EDMA_DCHPRI31 (IMXRT_EDMA_BASE + IMXRT_EDMA_DCHPRI31_OFFSET)
#define IMXRT_EDMA_DCHPRI3_OFFSET 0x0100 /* Channel 3 Priority */
#define IMXRT_EDMA_DCHPRI2_OFFSET 0x0101 /* Channel 2 Priority */
#define IMXRT_EDMA_DCHPRI1_OFFSET 0x0102 /* Channel 1 Priority */
#define IMXRT_EDMA_DCHPRI0_OFFSET 0x0103 /* Channel 0 Priority */
#define IMXRT_EDMA_DCHPRI7_OFFSET 0x0104 /* Channel 7 Priority */
#define IMXRT_EDMA_DCHPRI6_OFFSET 0x0105 /* Channel 6 Priority */
#define IMXRT_EDMA_DCHPRI5_OFFSET 0x0106 /* Channel 5 Priority */
#define IMXRT_EDMA_DCHPRI4_OFFSET 0x0107 /* Channel 4 Priority */
#define IMXRT_EDMA_DCHPRI11_OFFSET 0x0108 /* Channel 11 Priority */
#define IMXRT_EDMA_DCHPRI10_OFFSET 0x0109 /* Channel 10 Priority */
#define IMXRT_EDMA_DCHPRI9_OFFSET 0x010a /* Channel 9 Priority */
#define IMXRT_EDMA_DCHPRI8_OFFSET 0x010b /* Channel 8 Priority */
#define IMXRT_EDMA_DCHPRI15_OFFSET 0x010c /* Channel 15 Priority */
#define IMXRT_EDMA_DCHPRI14_OFFSET 0x010d /* Channel 14 Priority */
#define IMXRT_EDMA_DCHPRI13_OFFSET 0x010e /* Channel 13 Priority */
#define IMXRT_EDMA_DCHPRI12_OFFSET 0x010f /* Channel 12 Priority */
#define IMXRT_EDMA_DCHPRI19_OFFSET 0x0110 /* Channel 19 Priority */
#define IMXRT_EDMA_DCHPRI18_OFFSET 0x0111 /* Channel 18 Priority */
#define IMXRT_EDMA_DCHPRI17_OFFSET 0x0112 /* Channel 17 Priority */
#define IMXRT_EDMA_DCHPRI16_OFFSET 0x0113 /* Channel 16 Priority */
#define IMXRT_EDMA_DCHPRI23_OFFSET 0x0114 /* Channel 23 Priority */
#define IMXRT_EDMA_DCHPRI22_OFFSET 0x0115 /* Channel 22 Priority */
#define IMXRT_EDMA_DCHPRI21_OFFSET 0x0116 /* Channel 21 Priority */
#define IMXRT_EDMA_DCHPRI20_OFFSET 0x0117 /* Channel 20 Priority */
#define IMXRT_EDMA_DCHPRI27_OFFSET 0x0118 /* Channel 27 Priority */
#define IMXRT_EDMA_DCHPRI26_OFFSET 0x0119 /* Channel 26 Priority */
#define IMXRT_EDMA_DCHPRI25_OFFSET 0x011a /* Channel 25 Priority */
#define IMXRT_EDMA_DCHPRI24_OFFSET 0x011b /* Channel 24 Priority */
#define IMXRT_EDMA_DCHPRI31_OFFSET 0x011c /* Channel 31 Priority */
#define IMXRT_EDMA_DCHPRI30_OFFSET 0x011d /* Channel 30 Priority */
#define IMXRT_EDMA_DCHPRI29_OFFSET 0x011e /* Channel 29 Priority */
#define IMXRT_EDMA_DCHPRI28_OFFSET 0x011f /* Channel 28 Priority */
/* Transfer Control Descriptor (TCD) */
#define IMXRT_EDMA_TCD_BASE(n) (IMXRT_EDMA_BASE + IMXRT_EDMA_TCD_OFFSET(n))
#define IMXRT_EDMA_TCD_SADDR(n) (IMXRT_EDMA_TCD_BASE(n) + IMXRT_EDMA_TCD_SADDR_OFFSET)
......@@ -1125,6 +1162,7 @@
#define EDMA_TCD_ATTR_DSIZE_SHIFT (0) /* Bits 0-2: Destination data transfer size */
#define EDMA_TCD_ATTR_DSIZE_MASK (7 << EDMA_TCD_ATTR_DSIZE_SHIFT)
# define EDMA_TCD_ATTR_DSIZE(n) ((uint32_t)(n) << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 8-bit */
# define EDMA_TCD_ATTR_DSIZE_8BIT (TCD_ATTR_SIZE_8BIT << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 8-bit */
# define EDMA_TCD_ATTR_DSIZE_16BIT (TCD_ATTR_SIZE_16BIT << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 16-bit */
# define EDMA_TCD_ATTR_DSIZE_32BIT (TCD_ATTR_SIZE_32BIT << EDMA_TCD_ATTR_DSIZE_SHIFT) /* 32-bit */
......@@ -1135,6 +1173,7 @@
# define EDMA_TCD_ATTR_DMOD(n) ((uint32_t)(n) << EDMA_TCD_ATTR_DMOD_SHIFT)
#define EDMA_TCD_ATTR_SSIZE_SHIFT (8) /* Bits 8-10: Source data transfer size */
#define EDMA_TCD_ATTR_SSIZE_MASK (7 << EDMA_TCD_ATTR_SSIZE_SHIFT)
# define EDMA_TCD_ATTR_SSIZE(n) ((uint32_t)(n) << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 8-bit */
# define EDMA_TCD_ATTR_SSIZE_8BIT (TCD_ATTR_SIZE_8BIT << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 8-bit */
# define EDMA_TCD_ATTR_SSIZE_16BIT (TCD_ATTR_SIZE_16BIT << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-bit */
# define EDMA_TCD_ATTR_SSIZE_32BIT (TCD_ATTR_SIZE_32BIT << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-bit */
......@@ -1208,6 +1247,8 @@
#define EDMA_TCD_CSR_ACTIVE (1 << 6) /* Bit 6: Channel Active */
#define EDMA_TCD_CSR_DONE (1 << 7) /* Bit 7: Channel Done */
#define EDMA_TCD_CSR_MAJORLINKCH_SHIFT (8) /* Bits 8-12: Major Loop Link Channel Number */
#define EDMA_TCD_CSR_MAJORLINKCH_MASK (31 << EDMA_TCD_CSR_MAJORLINKCH_SHIFT)
# define EDMA_TCD_CSR_MAJORLINKCH(n) ((uint32_t)(n) << EDMA_TCD_CSR_MAJORLINKCH_SHIFT)
/* Bit 13: Reserved */
#define EDMA_TCD_CSR_BWC_SHIFT (14) /* Bits 14-15: Bandwidth Control */
#define EDMA_TCD_CSR_BWC_MASK (3 << EDMA_TCD_CSR_BWC_SHIFT)
......@@ -1237,4 +1278,25 @@
#define EDMA_TCD_BITER_ELINK_ELINK (1 << 15) /* Bit 15: Enable channel-to-channel linking
* on minor-loop complete */
/****************************************************************************************************
* Public Types
****************************************************************************************************/
/* In-memory representation of the 32-byte Transfer Control Descriptor (TCD) */
struct imxrt_edmatcd_s
{
uint32_t saddr; /* Offset: 0x0000 TCD Source Address */
uint16_t soff; /* Offset: 0x0004 TCD Signed Source Address Offset */
uint16_t attr; /* Offset: 0x0006 TCD Transfer Attributes */
uint32_t nbytes; /* Offset: 0x0008 TCD Signed Minor Loop Offset / Byte Count */
uint32_t slast; /* Offset: 0x000c TCD Last Source Address Adjustment */
uint32_t daddr; /* Offset: 0x0010 TCD Destination Address */
uint16_t doff; /* Offset: 0x0014 TCD Signed Destination Address Offset */
uint16_t citer; /* Offset: 0x0016 TCD Current Minor Loop Link, Major Loop Count */
uint32_t dlastsga; /* Offset: 0x0018 TCD Last Destination Address Adjustment/Scatter Gather Address */
uint16_t csr; /* Offset: 0x001c TCD Control and Status */
uint16_t biter; /* Offset: 0x001e TCD Beginning Minor Loop Link, Major Loop Count */
};
#endif /* __ARCH_ARM_SRC_IMXRT_CHIP_IMXRT_EDMA_H */
This diff is collapsed.
This diff is collapsed.
......@@ -2863,7 +2863,7 @@ static int lpc17_epsubmit(FAR struct usbdev_ep_s *ep, FAR struct usbdev_req_s *r
/* This there a incoming data pending the availability of a request? */
if (priv->rxpendinig > 0)
if (priv->rxpending > 0)
{
ret = lpc17_rdrequest(privep);
priv->rxpending--;
......
......@@ -1598,6 +1598,12 @@ void sam_dmainitialize(struct sam_xdmac_s *xdmac)
nxsem_init(&xdmac->chsem, 0, 1);
nxsem_init(&xdmac->dsem, 0, SAMV7_NDMACHAN);
/* The 'dsem' is used for signaling rather than mutual exclusion and,
* hence, should not have priority inheritance enabled.
*/
nxsem_setprotocol(&xdmac->dsem, SEM_PRIO_NONE);
}
/****************************************************************************
......
......@@ -4,4 +4,17 @@
#
if ARCH_BOARD_IMXRT1050_EVK
choice
prompt "Boot Flash"
default IMXRT1050_EVK_HYPER_FLASH
config IMXRT1050_EVK_HYPER_FLASH
bool "HYPER Flash"
config IMXRT1050_EVK_NOR_FLASH
bool "Serial NOR Flash"
endchoice # Boot Flash
endif
......@@ -45,7 +45,7 @@ MEMORY
OUTPUT_ARCH(arm)
EXTERN(_vectors)
EXTERN(hyperflash_config)
EXTERN(flash_config)
EXTERN(image_vector_table)
EXTERN(boot_data)
......
......@@ -37,16 +37,18 @@
* Included Files
******************************************************************************/
#include "imxrt_flexspi_nor_flash.h"
/*******************************************************************************
* Public Data
******************************************************************************/
#if defined (CONFIG_IMXRT1050_EVK_HYPER_FLASH)
__attribute__((section(".boot_hdr.conf")))
const struct flexspi_nor_config_s hyperflash_config =
const struct flexspi_nor_config_s flash_config =
{
.mem_config =
.mem_config =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
......@@ -55,7 +57,7 @@ const struct flexspi_nor_config_s hyperflash_config =
.cs_setup_time = 3u,
.column_address_width = 3u,
/* Enable DDR mode, Wordaddassable, Safe configuration, Differential clock */
/* Enable DDR mode, Word addassable, Safe configuration, Differential clock */
.controller_misc_option = (1u << FLEXSPIMISC_OFFSET_DDR_MODE_EN) |
(1u << FLEXSPIMISC_OFFSET_WORD_ADDRESSABLE_EN) |
......@@ -79,3 +81,119 @@ const struct flexspi_nor_config_s hyperflash_config =
.blocksize = 256u * 1024u,
.is_uniform_blocksize = 1,
};
#elif defined (CONFIG_IMXRT1050_EVK_NOR_FLASH)
__attribute__((section(".boot_hdr.conf")))
const struct flexspi_nor_config_s flash_config =
{
.mem_config =
{
.tag = FLEXSPI_CFG_BLK_TAG,
.version = FLEXSPI_CFG_BLK_VERSION,
.read_sample_clksrc = FLASH_READ_SAMPLE_CLK_LOOPBACK_FROM_SCKPAD,
.cs_hold_time = 3u,
.cs_setup_time = 3u,
.column_address_width = 0u,
.device_type = FLEXSPI_DEVICE_TYPE_SERIAL_NOR,
.sflash_pad_type = SERIAL_FLASH_4PADS,
.serial_clk_freq = FLEXSPI_SERIAL_CLKFREQ_60MHz,
.sflash_a1size = 8u * 1024u * 1024u,
.data_valid_time = {16u, 16u},
.lookup_table =
{
/* LUTs */
/* 0 Fast read Quad IO DTR Mode Operation in SPI Mode (normal read)*/
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xED, RADDR_DDR, FLEXSPI_4PAD, 0x18),
FLEXSPI_LUT_SEQ(DUMMY_DDR, FLEXSPI_4PAD, 0x0C, READ_DDR, FLEXSPI_4PAD, 0x08),
FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
/* 1 Read Status */
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x05, READ_SDR, FLEXSPI_1PAD, 0x1),
FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
/* 2 */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
/* 3 */
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x06, STOP, FLEXSPI_1PAD, 0x0),
FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
/* 4 */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
/* 5 Erase Sector */
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xD7, RADDR_SDR, FLEXSPI_1PAD, 0x18),
FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
/* 6 */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
/* 7 */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
/* 8 */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
/* 9 Page Program */
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0x02, RADDR_SDR, FLEXSPI_1PAD, 0x18),
FLEXSPI_LUT_SEQ(WRITE_SDR, FLEXSPI_1PAD, 0x8, STOP, FLEXSPI_1PAD, 0x0),
FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
/* 10 */
0x00000000,
0x00000000,
0x00000000,
0x00000000,
/* 11 Chip Erase */
FLEXSPI_LUT_SEQ(CMD_SDR, FLEXSPI_1PAD, 0xC7, STOP, FLEXSPI_1PAD, 0x0),
FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
FLEXSPI_LUT_SEQ(STOP, FLEXSPI_1PAD, 0x0, STOP, FLEXSPI_1PAD, 0x0),
},
},
.page_size = 256u,
.sector_size = 4u * 1024u,
.blocksize = 32u * 1024u,
.is_uniform_blocksize = false,
};
#else
# error Boot Flash type not chosen!
#endif
......@@ -115,7 +115,7 @@ static int fat_stat_common(FAR struct fat_mountpt_s *fs,
static int fat_stat_file(FAR struct fat_mountpt_s *fs,
FAR uint8_t *direntry, FAR struct stat *buf);
static int fat_stat_root(FAR struct fat_mountpt_s *fs,
FAR uint8_t *direntry, FAR struct stat *buf);
FAR struct stat *buf);
static int fat_stat(struct inode *mountpt, const char *relpath,
FAR struct stat *buf);
......@@ -2807,8 +2807,7 @@ static int fat_stat_file(FAR struct fat_mountpt_s *fs,
*
****************************************************************************/
static int fat_stat_root(FAR struct fat_mountpt_s *fs,
FAR uint8_t *direntry, FAR struct stat *buf)
static int fat_stat_root(FAR struct fat_mountpt_s *fs, FAR struct stat *buf)
{
/* Clear the "struct stat" */
......@@ -2865,18 +2864,18 @@ static int fat_stat(FAR struct inode *mountpt, FAR const char *relpath,
goto errout_with_semaphore;
}
/* Get a pointer to the directory entry */
direntry = &fs->fs_buffer[dirinfo.fd_seq.ds_offset];
/* Get the FAT attribute and map it so some meaningful mode_t values */
if (dirinfo.fd_root)
{
ret = fat_stat_root(fs, direntry, buf);
ret = fat_stat_root(fs, buf);
}
else
{
/* Get a pointer to the directory entry */
direntry = &fs->fs_buffer[dirinfo.fd_seq.ds_offset];
/* Call fat_stat_file() to create the buf and to save information to
* the stat buffer.
*/
......