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EESchema-LIBRARY Version 2.3
#encoding utf-8
#
# STM32F107VCT
#
DEF STM32F107VCT U 0 40 Y Y 12 L N
F0 "U" -2025 -1000 50 H V L BNN
F1 "STM32F107VCT" 525 -1000 50 H V R BNN
F2 "LQFP100" -1150 -950 50 H V R TNN
F3 "" 0 0 50 H V C CNN
$FPLIST
TQFP-100_14x14mm_Pitch0.5mm
$ENDFPLIST
DRAW
# MII
S 600 1050 -250 -1150 1 1 0 N
T 900 -325 0 60 0 1 0 Ethernet Normal 0 C C
X MII_CRS/PA0 23 800 1000 200 L 50 50 1 1 B
X MII_COL/PA3 26 800 900 200 L 50 50 1 1 B
X MII_TXD3/PB8 95 800 700 200 L 50 50 1 1 B
X MII_TXD2/PC2 17 800 600 200 L 50 50 1 1 B
X MII_TXD1/PB13 52 800 500 200 L 50 50 1 1 B
X MII_TXD0/PB12 51 800 400 200 L 50 50 1 1 B
X MII_TX_EN/PB11 48 800 300 200 L 50 50 1 1 B
X MII_TX_CLK/PC3 18 800 200 200 L 50 50 1 1 B
X MII_RXDV/PA7 32 800 0 200 L 50 50 1 1 B
X MII_RXD0/PC4 33 800 -100 200 L 50 50 1 1 B
X MII_RXD1/PC5 34 800 -200 200 L 50 50 1 1 B
X MII_RXD2/PB0 35 800 -300 200 L 50 50 1 1 B
X MII_RXD3/PB1 36 800 -400 200 L 50 50 1 1 B
X MII_RX_ER/PB10 47 800 -500 200 L 50 50 1 1 B
X MII_RX_CLK/PA1 24 800 -600 200 L 50 50 1 1 B
X MII_MDC/PC1 16 800 -800 200 L 50 50 1 1 B
X MII_MDIO/PA2 25 800 -900 200 L 50 50 1 1 B
X MII_PPS_OUT/PB5 91 800 -1100 200 L 50 50 1 1 B
# CAN1 remap=3
S 600 50 0 -150 2 1 0 N
T 900 -75 -50 60 0 2 0 CAN1,~remap=3 Normal 0 C C
X CAN1_RX/PD0 81 800 0 200 L 50 50 2 1 B
X CAN1_TX/PD1 82 800 -100 200 L 50 50 2 1 B
# Debug
S 600 750 -150 -450 3 1 0 N
T 900 -225 175 60 0 3 0 Debug Normal 0 C C
X TDI/PA15 77 800 700 200 L 50 50 3 1 B
X TMS/SWDIO/PA13 72 800 600 200 L 50 50 3 1 B
X TCK/SWCLK/PA14 76 800 500 200 L 50 50 3 1 B
X TDO/SWO/PB3 89 800 400 200 L 50 50 3 1 B
X nTRST/PB4 90 800 300 200 L 50 50 3 1 B
X BOOT0 94 800 200 200 L 50 50 3 1 I
X BOOT1/PB2 37 800 100 200 L 50 50 3 1 B
X TRACECLK/PE2 1 800 0 200 L 50 50 3 1 B
X TRACED0/PE3 2 800 -100 200 L 50 50 3 1 B
X TRACED1/PE4 3 800 -200 200 L 50 50 3 1 B
X TRACED2/PE5 4 800 -300 200 L 50 50 3 1 B
X TRACED3/PE6 5 800 -400 200 L 50 50 3 1 B
# UART1 / USB-OTG
S 600 250 -300 -250 4 1 0 N
T 900 -400 0 60 0 4 0 UART1/USB Normal 0 C C
X U1CTS/OTG_DM/PA11 70 800 200 200 L 50 50 4 1 B
X U1RTS/OTG_DP/PA12 71 800 100 200 L 50 50 4 1 B
X DAC_EXTI9/T3CH4/PC9 66 800 0 200 L 50 50 4 1 B
X U1TX/OTG_VBUS/PA9 68 800 -100 200 L 50 50 4 1 B
X U1RX/OTG_ID/PA10 69 800 -200 200 L 50 50 4 1 B
# I2C1 remap=0
S 600 50 150 -150 5 1 0 N
T 900 75 -50 60 0 5 0 I2C1,~remap=0 Normal 0 C C
X SCL1/PB6 92 800 0 200 L 50 50 5 1 B
X SDA1/PB7 93 800 -100 200 L 50 50 5 1 B
# 32K (if needed)
S 600 50 -350 -150 6 1 0 N
T 900 -425 -50 60 0 6 0 RTC Normal 0 C C
X RCC_OSC32_IN/PC14 8 800 0 200 L 50 50 6 1 B
X RCC_OSC32_OUT/PC15 9 800 -100 200 L 50 50 6 1 B
# SPI3 remap=1
S 600 150 50 -250 7 1 0 N
T 900 -25 -50 60 0 7 0 SPI3,~Remap=1 Normal 0 C C
X NSS3/PA4 29 800 100 200 L 50 50 7 1 B
X SCK3/PC10 78 800 0 200 L 50 50 7 1 B
X MOSI3/PC12 80 800 -100 200 L 50 50 7 1 B
X MISO3/PC11 79 800 -200 200 L 50 50 7 1 B
# UART2
S 600 250 100 -250 8 1 0 N
T 900 25 0 60 0 8 0 UART2 Normal 0 C C
X U2CTS/PD3 84 800 200 200 L 50 50 8 1 B
X U2RTS/PD4 85 800 100 200 L 50 50 8 1 B
X U2TX/PD5 86 800 0 200 L 50 50 8 1 B
X U2RX/PD6 87 800 -100 200 L 50 50 8 1 B
X U2CK/PD7 88 800 -200 200 L 50 50 8 1 B
# UART3 remap=3
S 600 250 50 -250 9 1 0 N
T 900 -25 0 60 0 9 0 UART3,~remap=3 Normal 0 C C
X U3TX/PD8 55 800 200 200 L 50 50 9 1 B
X U3RX/PD9 56 800 100 200 L 50 50 9 1 B
X U3CK/PD10 57 800 0 200 L 50 50 9 1 B
X U3CTS/PD11 58 800 -100 200 L 50 50 9 1 B
X U3RTS/PD12 59 800 -200 200 L 50 50 9 1 B
# Other
S 600 750 -1450 -750 10 1 0 N
T 900 -1525 0 60 0 10 0 OTHER0 Normal 0 C C
X A1IN5/A2IN5/DAC2/SCK1/PA5 30 800 700 200 L 50 50 10 1 B
X A1IN6/A2IN6/MISO1/T1BKIN/T3CH1/PA6 31 800 600 200 L 50 50 10 1 B
X CAN1_TX/DAC_EXTI9/SDA1/T4CH4/PB9 96 800 500 200 L 50 50 10 1 B
X MISO2/T1CH2N/U3RTS/PB14 53 800 400 200 L 50 50 10 1 B
X A1EXTI15/A2EXTI15/I2S2_SD/MOSI2/T1CH3N/PB15 54 800 300 200 L 50 50 10 1 B
X A1IN10/A2IN10/PC0 15 800 200 200 L 50 50 10 1 B
X I2S2_MCK/T3CH1/PC6 63 800 100 200 L 50 50 10 1 B
X I2S3_MCK/T3CH2/PC7 64 800 0 200 L 50 50 10 1 B
X T3CH3/PC8 65 800 -100 200 L 50 50 10 1 B
X MCO/OTG_SOF/PA8 67 800 -200 200 L 50 50 10 1 B
X RTC_OUT/RTC_TAMPER/PC13 7 800 -300 200 L 50 50 10 1 B
X T3ETR/U5RX/PD2 83 800 -400 200 L 50 50 10 1 B
X T4CH2/PD13 60 800 -500 200 L 50 50 10 1 B
X T4CH3/PD14 61 800 -600 200 L 50 50 10 1 B
X A1EXTI15/A2EXTI15/T4CH4/PD15 62 800 -700 200 L 50 50 10 1 B
S 600 750 -800 -350 11 1 0 N
T 900 -875 175 60 0 11 0 OTHER1 Normal 0 C C
X T4ETR/PE0 97 800 700 200 L 50 50 11 1 B
X PE1 98 800 600 200 L 50 50 11 1 B
X T1ETR/PE7 38 800 500 200 L 50 50 11 1 B
X T1CH1N/PE8 39 800 400 200 L 50 50 11 1 B
X DAC_EXTI9/T1CH1/PE9 40 800 300 200 L 50 50 11 1 B
X T1CH2N/PE10 41 800 200 200 L 50 50 11 1 B
X A1EXTI11/A2EXTI11/T1CH2/PE11 42 800 100 200 L 50 50 11 1 B
X T1CH3N/PE12 43 800 0 200 L 50 50 11 1 B
X T1CH3/PE13 44 800 -100 200 L 50 50 11 1 B
X T1CH4/PE14 45 800 -200 200 L 50 50 11 1 B
X A1EXTI15/A2EXTI15/T1BKIN/PE15 46 800 -300 200 L 50 50 11 1 B
T 900 -475 0 60 0 12 0 POWER Normal 0 C C
S -400 -600 400 600 12 1 0 N
X VBAT 6 600 200 200 L 50 50 12 1 W
X RCC_OSC_IN 12 600 100 200 L 50 50 12 1 I
X RCC_OSC_OUT 13 600 0 200 L 50 50 12 1 I
X NC 73 600 -100 200 L 50 50 12 1 N N
X NRST 14 600 -200 200 L 50 50 12 1 I
X VDD 11 -300 800 200 D 50 50 12 1 W
X VDD 28 -200 800 200 D 50 50 12 1 W
X VDD 50 -100 800 200 D 50 50 12 1 W
X VDD 75 0 800 200 D 50 50 12 1 W
X VDD 100 100 800 200 D 50 50 12 1 W
X VDDA 22 200 800 200 D 50 50 12 1 W
X VREF+ 21 300 800 200 D 50 50 12 1 W
X VSS 10 -300 -800 200 U 50 50 12 1 W
X VSS 27 -200 -800 200 U 50 50 12 1 W
X VSS 49 -100 -800 200 U 50 50 12 1 W
X VSS 74 0 -800 200 U 50 50 12 1 W
X VSS 99 100 -800 200 U 50 50 12 1 W
X VSSA 19 200 -800 200 U 50 50 12 1 W
X VREF- 20 300 -800 200 U 50 50 12 1 W
ENDDRAW
ENDDEF
#
#End Library