From 4ebf573692f92a97af6d43a16628d877f5cbcc75 Mon Sep 17 00:00:00 2001 From: Julien Peeters Date: Fri, 11 Nov 2016 18:47:21 +0100 Subject: [PATCH] brain: fix phy clock source init --- software/library/boards/brain.c | 33 +++++++++++++++++++++------------ 1 file changed, 21 insertions(+), 12 deletions(-) diff --git a/software/library/boards/brain.c b/software/library/boards/brain.c index 8d95524..46223e2 100644 --- a/software/library/boards/brain.c +++ b/software/library/boards/brain.c @@ -35,20 +35,20 @@ /* CPU */ DEV_DECLARE_STATIC(cpu_dev, "cpu", DEVICE_FLAG_CPU, arm32m_drv, - DEV_STATIC_RES_ID(0, 0), - DEV_STATIC_RES_FREQ(72000000, 1) + DEV_STATIC_RES_ID(0, 0), + DEV_STATIC_RES_FREQ(72000000, 1) ); /* GPIO A..E. */ DEV_DECLARE_STATIC(gpio_dev, "gpio", 0, stm32_gpio_drv, - DEV_STATIC_RES_DEV_ICU("/cpu"), - DEV_STATIC_RES_IRQ(0, STM32_IRQ_EXTI0, DEV_IRQ_SENSE_HIGH_LEVEL, 0, 0x1), - DEV_STATIC_RES_IRQ(1, STM32_IRQ_EXTI1, DEV_IRQ_SENSE_HIGH_LEVEL, 0, 0x1), - DEV_STATIC_RES_IRQ(2, STM32_IRQ_EXTI2, DEV_IRQ_SENSE_HIGH_LEVEL, 0, 0x1), - DEV_STATIC_RES_IRQ(3, STM32_IRQ_EXTI3, DEV_IRQ_SENSE_HIGH_LEVEL, 0, 0x1), - DEV_STATIC_RES_IRQ(4, STM32_IRQ_EXTI4, DEV_IRQ_SENSE_HIGH_LEVEL, 0, 0x1), - DEV_STATIC_RES_IRQ(5, STM32_IRQ_EXTI9_5, DEV_IRQ_SENSE_HIGH_LEVEL, 0, 0x1), - DEV_STATIC_RES_IRQ(6, STM32_IRQ_EXTI15_10, DEV_IRQ_SENSE_HIGH_LEVEL, 0, 0x1) + DEV_STATIC_RES_DEV_ICU("/cpu"), + DEV_STATIC_RES_IRQ(0, STM32_IRQ_EXTI0, DEV_IRQ_SENSE_HIGH_LEVEL, 0, 0x1), + DEV_STATIC_RES_IRQ(1, STM32_IRQ_EXTI1, DEV_IRQ_SENSE_HIGH_LEVEL, 0, 0x1), + DEV_STATIC_RES_IRQ(2, STM32_IRQ_EXTI2, DEV_IRQ_SENSE_HIGH_LEVEL, 0, 0x1), + DEV_STATIC_RES_IRQ(3, STM32_IRQ_EXTI3, DEV_IRQ_SENSE_HIGH_LEVEL, 0, 0x1), + DEV_STATIC_RES_IRQ(4, STM32_IRQ_EXTI4, DEV_IRQ_SENSE_HIGH_LEVEL, 0, 0x1), + DEV_STATIC_RES_IRQ(5, STM32_IRQ_EXTI9_5, DEV_IRQ_SENSE_HIGH_LEVEL, 0, 0x1), + DEV_STATIC_RES_IRQ(6, STM32_IRQ_EXTI15_10, DEV_IRQ_SENSE_HIGH_LEVEL, 0, 0x1) ); /* UART 4 */ @@ -85,11 +85,12 @@ DEV_DECLARE_STATIC(dwc10100_dev, "eth0", 0, dwc10100_drv, DEV_STATIC_RES_MEM(STM32_ETHERNET_DMA_ADDR, STM32_ETHERNET_DMA_ADDR + STM32_ETHERNET_DMA_SIZE), DEV_STATIC_RES_FREQ(72000000, 1), - DEV_STATIC_RES_DEV_PARAM("gpio", "/gpio"), - DEV_STATIC_RES_DEV_IOMUX("/gpio"), + DEV_STATIC_RES_DEV_IOMUX("/gpio"), DEV_STATIC_RES_IOMUX("mdc", 0, STM32_PC1, 0, 0), DEV_STATIC_RES_IOMUX("mdio", 0, STM32_PA2, 0, 0), + + DEV_STATIC_RES_DEV_PARAM("gpio", "/gpio"), DEV_STATIC_RES_GPIO("resetn", STM32_PC7, 1), DEV_STATIC_RES_DEV_ICU("/cpu"), @@ -100,6 +101,7 @@ DEV_DECLARE_STATIC(dwc10100_dev, "eth0", 0, dwc10100_drv, #include #include #include +#include #include #define __IO volatile @@ -227,4 +229,11 @@ void stm32_clock_init(void) cpu_mem_write_32(STM32_RCC_ADDR + STM32_RCC_AHBRSTR_ADDR, -1); cpu_mem_write_32(STM32_RCC_ADDR + STM32_RCC_AHBRSTR_ADDR, 0); + + // Set MCO pin as alternate function + a = STM32_GPIO_ADDR + STM32_GPIO_CRH_ADDR(0); + x = endian_le32(cpu_mem_read_32(a)); + STM32_GPIO_CRH_CNF_SET(0, x, ALT_PUSH_PULL); + STM32_GPIO_CRH_MODE_SET(0, x, OUTPUT_50_MHZ); + cpu_mem_write_32(a, endian_le32(x)); } -- GitLab