diff --git a/metaclk/main.c b/metaclk/main.c
index ceb1609d6bd20442688ef499505b5b03f405b651..d3ac1dc421a1e8db088621580a18f36077b4d192 100755
--- a/metaclk/main.c
+++ b/metaclk/main.c
@@ -283,6 +283,8 @@ static TERMUI_CON_COMMAND_PROTOTYPE(set_phase) {
     
     termui_con_printf(con, "%d, %d\n", pll_num, step);
     
+    steps[pll_num] += step;
+    
     // pll registers
     pll_num = pll_num * 11 + 52;
     
@@ -318,6 +320,9 @@ static TERMUI_CON_COMMAND_PROTOTYPE(set_phase) {
         dev_i2c_wait_transaction(&pll_i2c, &rq);
     }
     
+    termui_con_printf(con, "Step are 20ps\n");
+    termui_con_printf(con, "pll 0: %d, pll 1: %d, pll 2: %d, pll 3: %d\n", steps[0], steps[1], steps[2], steps[3]);
+    
     return 0;
 }
 
diff --git a/metaclk/register_map.h b/metaclk/register_map.h
index 74277f039b79462f93530418a8a718efd5f4387d..26ad7673b236afd7dfc0ad90c64db269d48d0607 100755
--- a/metaclk/register_map.h
+++ b/metaclk/register_map.h
@@ -2,7 +2,7 @@
 //http://www.silabs.com/clocks 
 //Copyright 2012 Silicon Laboratories
 //#BEGIN_HEADER
-//Date = Monday, March 20, 2017 5:42 PM
+//Date = Sunday, April 02, 2017 10:05 PM
 //File version = 3
 //Software Name = ClockBuilder Desktop
 //Software version = 6.4
@@ -19,43 +19,43 @@
 //P2 = 1
 //FDBK Mux = NoClk
 //PFD Input Frequency (MHz) = 25.000000000
-//VCO Frequency (GHz) = 2.600000
-//N = 104  (104.0000)
+//VCO Frequency (GHz) = 2.500000
+//N = 100  (100.0000)
 //Internal feedback enabled
 //Output Clock 0
-// Output Frequency (MHz) = 100.000000000
+// Output Frequency (MHz) = 250.000000000
 // Mux Selection = IDn
-// MultiSynth = 26  (26.0000)
+// MultiSynth = 10  (10.0000)
 // R = 1
 //Output Clock 1
-// Output Frequency (MHz) = 100.000000000
+// Output Frequency (MHz) = 125.000000000
 // Mux Selection = IDn
-// MultiSynth = 26  (26.0000)
+// MultiSynth = 20  (20.0000)
 // R = 1
 //Output Clock 2
-// Output Frequency (MHz) = 100.000000000
+// Output Frequency (MHz) = 250.000000000
 // Mux Selection = IDn
-// MultiSynth = 26  (26.0000)
+// MultiSynth = 10  (10.0000)
 // R = 1
 //Output Clock 3
 // Output is off
 //Driver 0
 // Enabled
 // Powered on
-// Output voltage = 3.30
-// Output type = 3.3V CMOS on A
+// Output voltage = 2.50
+// Output type = 2.5V CMOS on A
 // Output state when disabled = StopLow
 //Driver 1
 // Enabled
 // Powered on
-// Output voltage = 3.30
-// Output type = 3.3V CMOS on A
+// Output voltage = 2.50
+// Output type = 2.5V CMOS on A
 // Output state when disabled = StopLow
 //Driver 2
 // Enabled
 // Powered on
-// Output voltage = 3.30
-// Output type = 3.3V CMOS on A
+// Output voltage = 2.50
+// Output type = 2.5V CMOS on A
 // Output state when disabled = StopLow
 //Driver 3
 // Disabled
@@ -63,13 +63,18 @@
 // Output voltage = 3.30
 // Output type = 3.3V LVDS
 // Output state when disabled = StopLow
-//Clock 0 phase inc/dec step size (ns) = 0.0200
-//Clock 1 phase inc/dec step size (ns) = 0.0200
-//Clock 2 phase inc/dec step size (ns) = 0.0200
+//Clock 0 phase inc/dec step size (ns) = 0.020
+//Clock 1 phase inc/dec step size (ns) = 0.020
+//Clock 2 phase inc/dec step size (ns) = 0.020
 //Clock 3 phase inc/dec step size (ns) = 0.000
 //Phase increment and decrement pin control is off
+//Clock 0 frequency increment and decrement is enabled 
+//Clock 0 frequency inc/dec step size (Hz) = 2500000.000
+//Clock 1 frequency increment and decrement is enabled 
+//Clock 1 frequency inc/dec step size (Hz) = 1250000.000
+//Clock 2 frequency increment and decrement is enabled 
+//Clock 2 frequency inc/dec step size (Hz) = 2500000.000
 //Frequency increment and decrement pin control is off
-//Frequency increment and decrement is disabled
 //Initial phase offset 0 (ns) = 0.000
 //Initial phase offset 1 (ns) = 0.000
 //Initial phase offset 2 (ns) = 0.000
@@ -118,26 +123,26 @@ Reg_Data Reg_Store[] = {
 { 32,0xC0,0xFF},
 { 33,0xC0,0xFF},
 { 34,0xE3,0xFF},
-{ 35,0x00,0xFF},
+{ 35,0x15,0xFF},
 { 36,0x01,0x1F},
 { 37,0x01,0x1F},
 { 38,0x01,0x1F},
 { 39,0x00,0x1F},
-{ 40,0xF7,0xFF},
-{ 41,0x5E,0x7F},
+{ 40,0x73,0xFF},
+{ 41,0x4E,0x7F},
 { 42,0x23,0x3F},
 { 43,0x00,0x00},
 { 44,0x00,0x00},
 { 45,0x00,0xFF},
 { 46,0x00,0xFF},
 { 47,0x14,0x3F},
-{ 48,0x35,0xFF},
+{ 48,0x3A,0xFF},
 { 49,0x00,0xFF},
-{ 50,0xC3,0xFF},
+{ 50,0xC4,0xFF},
 { 51,0x07,0xFF},
-{ 52,0x10,0xFF},
+{ 52,0x00,0xFF},
 { 53,0x00,0xFF},
-{ 54,0x0B,0xFF},
+{ 54,0x03,0xFF},
 { 55,0x00,0xFF},
 { 56,0x00,0xFF},
 { 57,0x00,0xFF},
@@ -146,9 +151,9 @@ Reg_Data Reg_Store[] = {
 { 60,0x00,0xFF},
 { 61,0x00,0xFF},
 { 62,0x00,0x3F},
-{ 63,0x10,0xFF},
+{ 63,0x00,0xFF},
 { 64,0x00,0xFF},
-{ 65,0x0B,0xFF},
+{ 65,0x08,0xFF},
 { 66,0x00,0xFF},
 { 67,0x00,0xFF},
 { 68,0x00,0xFF},
@@ -157,9 +162,9 @@ Reg_Data Reg_Store[] = {
 { 71,0x00,0xFF},
 { 72,0x00,0xFF},
 { 73,0x00,0x3F},
-{ 74,0x10,0xFF},
+{ 74,0x00,0xFF},
 { 75,0x00,0xFF},
-{ 76,0x0B,0xFF},
+{ 76,0x03,0xFF},
 { 77,0x00,0xFF},
 { 78,0x00,0xFF},
 { 79,0x00,0xFF},
@@ -181,7 +186,7 @@ Reg_Data Reg_Store[] = {
 { 95,0x00,0x3F},
 { 96,0x10,0x00},
 { 97,0x00,0xFF},
-{ 98,0x32,0xFF},
+{ 98,0x30,0xFF},
 { 99,0x00,0xFF},
 {100,0x00,0xFF},
 {101,0x00,0xFF},
@@ -192,23 +197,23 @@ Reg_Data Reg_Store[] = {
 {106,0x80,0xBF},
 {107,0x00,0xFF},
 {108,0x00,0xFF},
-{109,0x07,0xFF},
+{109,0x06,0xFF},
 {110,0x40,0xFF},
 {111,0x00,0xFF},
 {112,0x00,0xFF},
-{113,0x07,0xFF},
+{113,0x06,0xFF},
 {114,0x40,0xFF},
 {115,0x00,0xFF},
 {116,0x80,0xFF},
-{117,0x07,0xFF},
+{117,0x06,0xFF},
 {118,0x40,0xFF},
 {119,0x00,0xFF},
 {120,0x00,0xFF},
 {121,0x00,0xFF},
 {122,0x40,0xFF},
-{123,0x00,0xFF},
-{124,0x00,0xFF},
-{125,0x00,0xFF},
+{123,0x40,0xFF},
+{124,0x42,0xFF},
+{125,0x0F,0xFF},
 {126,0x00,0xFF},
 {127,0x00,0xFF},
 {128,0x00,0xFF},
@@ -218,11 +223,11 @@ Reg_Data Reg_Store[] = {
 {132,0x00,0xFF},
 {133,0x00,0xFF},
 {134,0x00,0xFF},
-{135,0x00,0xFF},
-{136,0x00,0xFF},
-{137,0x00,0xFF},
-{138,0x00,0xFF},
-{139,0x00,0xFF},
+{135,0x27,0xFF},
+{136,0x10,0xFF},
+{137,0x80,0xFF},
+{138,0x96,0xFF},
+{139,0x98,0xFF},
 {140,0x00,0xFF},
 {141,0x00,0xFF},
 {142,0x00,0xFF},
@@ -235,9 +240,9 @@ Reg_Data Reg_Store[] = {
 {149,0x00,0x00},
 {150,0x00,0x00},
 {151,0x00,0x00},
-{152,0x00,0xFF},
-{153,0x00,0xFF},
-{154,0x00,0xFF},
+{152,0x40,0xFF},
+{153,0x42,0xFF},
+{154,0x0F,0xFF},
 {155,0x00,0xFF},
 {156,0x00,0xFF},
 {157,0x00,0xFF},
@@ -247,19 +252,19 @@ Reg_Data Reg_Store[] = {
 {161,0x00,0xFF},
 {162,0x00,0xFF},
 {163,0x00,0xFF},
-{164,0x00,0xFF},
-{165,0x00,0xFF},
+{164,0x27,0xFF},
+{165,0x10,0xFF},
 {166,0x00,0xFF},
-{167,0x00,0xFF},
-{168,0x00,0xFF},
-{169,0x00,0xFF},
+{167,0x2D,0xFF},
+{168,0x31,0xFF},
+{169,0x01,0xFF},
 {170,0x00,0xFF},
 {171,0x00,0xFF},
 {172,0x00,0xFF},
 {173,0x00,0xFF},
-{174,0x00,0xFF},
-{175,0x00,0xFF},
-{176,0x00,0xFF},
+{174,0x40,0xFF},
+{175,0x42,0xFF},
+{176,0x0F,0xFF},
 {177,0x00,0xFF},
 {178,0x00,0xFF},
 {179,0x00,0xFF},
@@ -269,11 +274,11 @@ Reg_Data Reg_Store[] = {
 {183,0x00,0xFF},
 {184,0x00,0xFF},
 {185,0x00,0xFF},
-{186,0x00,0xFF},
-{187,0x00,0xFF},
-{188,0x00,0xFF},
-{189,0x00,0xFF},
-{190,0x00,0xFF},
+{186,0x27,0xFF},
+{187,0x10,0xFF},
+{188,0x80,0xFF},
+{189,0x96,0xFF},
+{190,0x98,0xFF},
 {191,0x00,0xFF},
 {192,0x00,0xFF},
 {193,0x00,0xFF},
@@ -323,7 +328,7 @@ Reg_Data Reg_Store[] = {
 {238,0x14,0x00},
 {239,0x00,0x00},
 {240,0x00,0x00},
-{242,0x02,0x02},
+{242,0x00,0x02},
 {243,0xF0,0x00},
 {244,0x00,0x00},
 {245,0x00,0x00},
@@ -434,4 +439,4 @@ Reg_Data Reg_Store[] = {
 {255,0x00,0xFF},
 {246,0x02,0xFF}, // soft reset
 {230,0x00,0xFF}}; // enable all output
-//End of file
\ No newline at end of file
+//End of file