Commit 49384729 authored by natsfr's avatar natsfr

merging

parents e7b6363d dff8068c
This diff is collapsed.
......@@ -13,77 +13,86 @@ import sys
import math
import cmath
''' Open S2P Files and extract data '''
def parse_spar(file, freq):
f = open(file, "r")
tmpspars = []
for line in f:
tmpspars.append(line.strip().split())
class TransistorBlock:
spars = {}#[] # 1: Freq 2: S11 3: S21 4: S12 5: S22
for l in tmpspars:
if(l[0] != "!" and l[0] != "#"):
tmp = []
#tmp.append(float(l[0])) # FREQ
tmp.append(complex(float(l[1]), float(l[2]))) # S11
tmp.append(complex(float(l[3]), float(l[4]))) # S21
tmp.append(complex(float(l[5]), float(l[6]))) # S12
tmp.append(complex(float(l[7]), float(l[8]))) # S22
#spars.append(tmp)
spars[float(l[0])] = tmp
return spars
''' Calculate John Rollett stability factor '''
def calc_stab(Ds, S):
K = (1 + cmath.polar(Ds)[0] ** 2 - cmath.polar(S[11])[0] ** 2 - \
cmath.polar(S[22])[0] ** 2) / (2 * cmath.polar(S[21])[0] * cmath.polar(S[12])[0])
return K
def __init__(self, file, freq, config):
self.freq = freq
self.config = config
self.parse_spar(file,freq)
''' Caculate Maximum Available Gain '''
def calc_mag(Ds, S, K):
B1 = 1 + cmath.polar(S[11])[0] ** 2 - cmath.polar(S[22])[0] ** 2 - cmath.polar(Ds)[0] ** 2
''' Open S2P Files and extract data '''
def parse_spar(self, file, freq):
f = open(file, "r")
tmpspars = []
for line in f:
tmpspars.append(line.strip().split())
self.spars = {}#[] # 1: Freq 2: S11 3: S21 4: S12 5: S22
for l in tmpspars:
if(l[0] != "!" and l[0] != "#"):
tmp = []
tmp.append(complex(float(l[1]), float(l[2]))) # S11
tmp.append(complex(float(l[3]), float(l[4]))) # S21
tmp.append(complex(float(l[5]), float(l[6]))) # S12
tmp.append(complex(float(l[7]), float(l[8]))) # S22
self.spars[float(l[0])] = tmp
''' Calculate John Rollett stability factor '''
def calc_stab(self):
S = self.S
self.K = (1 + cmath.polar(self.Ds)[0] ** 2 - cmath.polar(S[11])[0] ** 2 - \
cmath.polar(S[22])[0] ** 2) / (2 * cmath.polar(S[21])[0] * cmath.polar(S[12])[0])
''' Caculate Maximum Available Gain '''
def calc_mag(self):
S = self.S
self.B1 = 1 + cmath.polar(S[11])[0] ** 2 - cmath.polar(S[22])[0] ** 2 - cmath.polar(self.Ds)[0] ** 2
ksq = 0.0
if B1 < 0 :
ksq = math.sqrt(K**2 - 1)
else :
ksq = math.sqrt(k**2 - 1) * -1
ksq = 0.0
if self.B1 < 0 :
ksq = math.sqrt(self.K**2 - 1)
else :
ksq = math.sqrt(self.k**2 - 1) * -1
self.MAG = 10 * math.log(cmath.polar(S[11])[0] / cmath.polar(S[12])[0]) + \
10 * math.log(self.K + ksq)
MAG = 10 * math.log(cmath.polar(S[11])[0] / cmath.polar(S[12])[0]) + \
10 * math.log(K + ksq)
def set_freq(self, freq):
self.freq = freq
return MAG
def calc_value(freq, spars, config):
sparam = spars[freq]
S = {}
S[11] = sparam[0]
S[21] = sparam[1]
S[12] = sparam[2]
S[22] = sparam[3]
def calc_stability_mag(self):
self.sparam = self.spars[self.freq]
self.S = {}
self.S[11] = self.sparam[0]
self.S[21] = self.sparam[1]
self.S[12] = self.sparam[2]
self.S[22] = self.sparam[3]
S = self.S
self.Ds = S[11] * S[22] - S[12] * S[21]
self.calc_stab()
if self.K < 1 :
print("Warning ! K factor %f < 1.0 , amplifier could be unstable" % self.K)
print("Undefined Maximum Available Gain")
else :
print("Stable amplifier design. K factor %f >= 1" % self.K)
self.calc_mag()
print("Maximum Available Gain: %fdB" % self.MAG)
Ds = S[11] * S[22] - S[12] * S[21]
K = calc_stab(Ds, S)
def calc_scm(self):
S = self S
if self.K > 1 :
self.C1 = S[11] - (self.Ds * complex.conjugate(S[22]))
self.C2 = S[22] - (self.Ds * complex.conjugate(S[11]))
# B1 is already calculated for MAG
self.B2 = 1 - cmath.polar(S[11])[0] ** 2 - cmath.polar(S[22])[0] ** 2 - cmath.polar(self.Ds)[0] ** 2
else :
print("Can't calculate SCM, K < 1, try lossy match")
if K < 1 :
print("Warning ! K factor %f < 1.0 , amplifier could be unstable" % K)
print("Undefined Maximum Available Gain")
else :
print("Stable amplifier design. K factor %f >= 1" % K)
MAG = calc_mag(Ds, S, K)
print("Maximum Available Gain: %fdB" % MAG)
#Select the kind of configuration for the amplifier
if config == 'SCM' :
# Simultaneous Conjugate Match
print("Simulaneous Conjugate Match")
elif config == 'ONF' :
# Optimum Noise Figure
print("Not yet available")
else :
print("Unknown mode")
if __name__ == '__main__':
if(len(sys.argv) < 4):
print("Error: usage\nauto_match.py spar_file.s2p frequency configuration\n")
......@@ -91,6 +100,6 @@ if __name__ == '__main__':
fname = sys.argv[1]
freq = float(sys.argv[2])
config = sys.argv[3]
spars = parse_spar(fname, freq)
calc_value(freq, spars, config)
\ No newline at end of file
q1 = TransistorBlock(fname, freq, config)
q1.calc_stability_mag()
objs = main.o
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Index: 255 : Write: 1
Index: 31 : Write: 0
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Index: 38 : Write: 0
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Index: 47 : Write: 0
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Index: 52 : Write: 144
Index: 53 : Write: 49
Index: 54 : Write: 0
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Index: 56 : Write: 1
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Index: 68 : Write: 144
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Index: 72 : Write: 1
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%set OUTPUT_NAME metaclk
%append MODULES $(OUTPUT_NAME):$(CONFIGPATH)
CONFIG_LICENSE_APP_BSD
CONFIG_APP_START
%include scripts/options.build
%include arch/arch.build
CONFIG_MUTEK_SHELL
CONFIG_PTHREAD
CONFIG_PTHREAD_MAIN
CONFIG_MUTEK_PRINTK_ADDR 0x40013800
CONFIG_DRIVER_STM32_USART_PRINTK_CLK_FREQ 72000000
CONFIG_DRIVER_STM32_USART_PRINTK_BAUDRATE 115200
CONFIG_DRIVER_STM32_USART_PRINTK
CONFIG_DRIVER_STM32_USART_PRINTK_PIN 9
CONFIG_DRIVER_STM32_USART_PRINTK_AF 0
CONFIG_DRIVER_STM32_SPI
CONFIG_DRIVER_STM32_TIMER
CONFIG_MUTEK_CONSOLE
CONFIG_DRIVER_I2C_BITBANG
\ No newline at end of file
This diff is collapsed.
#ifndef nats_i2c_h
#define nats_i2c_h
#define NATS_I2C1_ADDR 0x40005400
#define NATS_I2C_CR1_ADDR 0x0
#define NATS_I2C_CR2_ADDR 0x4
#define NATS_I2C_OAR1_ADDR 0x8
#define NATS_I2C_OAR2_ADDR 0xC
#define NATS_I2C_DR_ADDR 0x10
#define NATS_I2C_SR1_ADDR 0x14
#define NATS_I2C_SR2_ADDR 0x18
#define NATS_I2C_CCR_ADDR 0x1C
#define NATS_I2C_TRISE_ADDR 0x20
#endif
\ No newline at end of file
//Register map for use with AN428 (JumpStart)
//http://www.silabs.com/clocks
//Copyright 2012 Silicon Laboratories
//#BEGIN_HEADER
//Date = Wednesday, March 15, 2017 12:09 AM
//File version = 3
//Software Name = ClockBuilder Desktop
//Software version = 6.4
//Software date = October 8, 2014
//Chip = Si5338
//Part Number = Si5338
//#END_HEADER
//Input Frequency (MHz) = 25.000000000
//Input Type = Crystal
//P1 = 1
//Input Mux = XoClk
//FDBK Input Frequency (MHz) = 25.000000000
//FDBK Input Type = OFF
//P2 = 1
//FDBK Mux = NoClk
//PFD Input Frequency (MHz) = 25.000000000
//VCO Frequency (GHz) = 2.600000
//N = 104 (104.0000)
//Internal feedback enabled
//Output Clock 0
// Output Frequency (MHz) = 100.000000000
// Mux Selection = IDn
// MultiSynth = 26 (26.0000)
// R = 1
//Output Clock 1
// Output Frequency (MHz) = 100.000000000
// Mux Selection = IDn
// MultiSynth = 26 (26.0000)
// R = 1
//Output Clock 2
// Output Frequency (MHz) = 100.000000000
// Mux Selection = IDn
// MultiSynth = 26 (26.0000)
// R = 1
//Output Clock 3
// Output is off
//Driver 0
// Enabled
// Powered on
// Output voltage = 3.30
// Output type = 3.3V CMOS on A
// Output state when disabled = StopLow
//Driver 1
// Enabled
// Powered on
// Output voltage = 3.30
// Output type = 3.3V CMOS on A
// Output state when disabled = StopLow
//Driver 2
// Enabled
// Powered on
// Output voltage = 3.30
// Output type = 3.3V CMOS on A
// Output state when disabled = StopLow
//Driver 3
// Disabled
// Powered off
// Output voltage = 3.30
// Output type = 3.3V LVDS
// Output state when disabled = StopLow
//Clock 0 phase inc/dec step size (ns) = 0.000
//Clock 1 phase inc/dec step size (ns) = 0.000
//Clock 2 phase inc/dec step size (ns) = 0.000
//Clock 3 phase inc/dec step size (ns) = 0.000
//Phase increment and decrement pin control is off
//Frequency increment and decrement pin control is off
//Frequency increment and decrement is disabled
//Initial phase offset 0 (ns) = 0.000
//Initial phase offset 1 (ns) = 5.000
//Initial phase offset 2 (ns) = 10.000
//Initial phase offset 3 (ns) = 0.000
//SSC is disabled
#define NUM_REGS_MAX 350
typedef struct Reg_Data{
unsigned char Reg_Addr;
unsigned char Reg_Val;
unsigned char Reg_Mask;
} Reg_Data;
Reg_Data Reg_Store[] = {
{ 0,0x00,0x00},
{ 1,0x00,0x00},
{ 2,0x00,0x00},
{ 3,0x00,0x00},
{ 4,0x00,0x00},
{ 5,0x00,0x00},
{ 6,0x08,0x1D},
{ 7,0x00,0x00},
{ 8,0x70,0x00},
{ 9,0x0F,0x00},
{ 10,0x00,0x00},
{ 11,0x00,0x00},
{ 12,0x00,0x00},
{ 13,0x00,0x00},
{ 14,0x00,0x00},
{ 15,0x00,0x00},
{ 16,0x00,0x00},
{ 17,0x00,0x00},
{ 18,0x00,0x00},
{ 19,0x00,0x00},
{ 20,0x00,0x00},
{ 21,0x00,0x00},
{ 22,0x00,0x00},
{ 23,0x00,0x00},
{ 24,0x00,0x00},
{ 25,0x00,0x00},
{ 26,0x00,0x00},
{ 27,0x70,0x80},
{ 28,0x16,0xFF},
{ 29,0x90,0xFF},
{ 30,0xB0,0xFF},
{ 31,0xC0,0xFF},
{ 32,0xC0,0xFF},
{ 33,0xC0,0xFF},
{ 34,0xE3,0xFF},
{ 35,0x00,0xFF},
{ 36,0x01,0x1F},
{ 37,0x01,0x1F},
{ 38,0x01,0x1F},
{ 39,0x00,0x1F},
{ 40,0xF7,0xFF},
{ 41,0x5E,0x7F},
{ 42,0x23,0x3F},
{ 43,0x00,0x00},
{ 44,0x00,0x00},
{ 45,0x00,0xFF},
{ 46,0x00,0xFF},
{ 47,0x14,0x3F},
{ 48,0x35,0xFF},
{ 49,0x00,0xFF},
{ 50,0xC3,0xFF},
{ 51,0x07,0xFF},
{ 52,0x10,0xFF},
{ 53,0x00,0xFF},
{ 54,0x0B,0xFF},
{ 55,0x00,0xFF},
{ 56,0x00,0xFF},
{ 57,0x00,0xFF},
{ 58,0x00,0xFF},
{ 59,0x01,0xFF},
{ 60,0x00,0xFF},
{ 61,0x00,0xFF},
{ 62,0x00,0x3F},
{ 63,0x10,0xFF},
{ 64,0x00,0xFF},
{ 65,0x0B,0xFF},
{ 66,0x00,0xFF},
{ 67,0x00,0xFF},
{ 68,0x00,0xFF},
{ 69,0x00,0xFF},
{ 70,0x01,0xFF},
{ 71,0x00,0xFF},
{ 72,0x00,0xFF},
{ 73,0x00,0x3F},
{ 74,0x10,0xFF},
{ 75,0x00,0xFF},
{ 76,0x0B,0xFF},
{ 77,0x00,0xFF},
{ 78,0x00,0xFF},
{ 79,0x00,0xFF},
{ 80,0x00,0xFF},
{ 81,0x01,0xFF},
{ 82,0x00,0xFF},
{ 83,0x00,0xFF},
{ 84,0x00,0x3F},
{ 85,0x10,0xFF},
{ 86,0x00,0xFF},
{ 87,0x00,0xFF},
{ 88,0x00,0xFF},
{ 89,0x00,0xFF},
{ 90,0x00,0xFF},
{ 91,0x00,0xFF},
{ 92,0x00,0xFF},
{ 93,0x00,0xFF},
{ 94,0x00,0xFF},
{ 95,0x00,0x3F},
{ 96,0x10,0x00},
{ 97,0x00,0xFF},
{ 98,0x32,0xFF},
{ 99,0x00,0xFF},
{100,0x00,0xFF},
{101,0x00,0xFF},
{102,0x00,0xFF},
{103,0x01,0xFF},
{104,0x00,0xFF},
{105,0x00,0xFF},
{106,0x80,0xBF},
{107,0x00,0xFF},
{108,0x00,0xFF},
{109,0x00,0xFF},
{110,0x40,0xFF},
{111,0x80,0xFF},
{112,0x06,0xFF},
{113,0x00,0xFF},
{114,0x40,0xFF},
{115,0x00,0xFF},
{116,0x8D,0xFF},
{117,0x00,0xFF},
{118,0x40,0xFF},
{119,0x00,0xFF},
{120,0x00,0xFF},
{121,0x00,0xFF},
{122,0x40,0xFF},
{123,0x00,0xFF},
{124,0x00,0xFF},
{125,0x00,0xFF},
{126,0x00,0xFF},
{127,0x00,0xFF},
{128,0x00,0xFF},
{129,0x00,0x0F},
{130,0x00,0x0F},
{131,0x00,0xFF},
{132,0x00,0xFF},
{133,0x00,0xFF},
{134,0x00,0xFF},
{135,0x00,0xFF},
{136,0x00,0xFF},
{137,0x00,0xFF},
{138,0x00,0xFF},
{139,0x00,0xFF},
{140,0x00,0xFF},
{141,0x00,0xFF},
{142,0x00,0xFF},
{143,0x00,0xFF},
{144,0x00,0xFF},
{145,0x00,0x00},
{146,0xFF,0x00},
{147,0x00,0x00},
{148,0x00,0x00},
{149,0x00,0x00},
{150,0x00,0x00},
{151,0x00,0x00},
{152,0x00,0xFF},
{153,0x00,0xFF},
{154,0x00,0xFF},
{155,0x00,0xFF},
{156,0x00,0xFF},
{157,0x00,0xFF},
{158,0x00,0x0F},
{159,0x00,0x0F},
{160,0x00,0xFF},
{161,0x00,0xFF},
{162,0x00,0xFF},
{163,0x00,0xFF},
{164,0x00,0xFF},
{165,0x00,0xFF},
{166,0x00,0xFF},
{167,0x00,0xFF},
{168,0x00,0xFF},
{169,0x00,0xFF},
{170,0x00,0xFF},
{171,0x00,0xFF},
{172,0x00,0xFF},
{173,0x00,0xFF},
{174,0x00,0xFF},
{175,0x00,0xFF},
{176,0x00,0xFF},
{177,0x00,0xFF},
{178,0x00,0xFF},
{179,0x00,0xFF},
{180,0x00,0xFF},
{181,0x00