Commit 562a9d99 authored by natsfr's avatar natsfr

working phase shifting function

parent 8565a4bb
File mode changed from 100755 to 100644
File mode changed from 100755 to 100644
......@@ -22,4 +22,6 @@ CONFIG_APP_START
CONFIG_DRIVER_STM32_TIMER
CONFIG_MUTEK_CONSOLE
CONFIG_DRIVER_I2C_BITBANG
CONFIG_LIBTERMUI
CONFIG_LIBTERMUI_CONSOLE
\ No newline at end of file
......@@ -30,6 +30,8 @@ DEV_DECLARE_STATIC(cpu_dev, "cpu", DEVICE_FLAG_CPU, arm32m_drv,
#include <mutek/startup.h>
//#include "nats_i2c.h"
// PLL config
#include "register_map.h"
DEV_DECLARE_STATIC(gpio_dev, "gpio", 0, stm32_gpio_drv,
......@@ -265,6 +267,73 @@ void change_pll_reg(Reg_Data si_reg) {
}
}
static TERMUI_CON_COMMAND_PROTOTYPE(test_command)
{
termui_con_printf(con, "PLL init with 0ps phase offset: use the set_phase with number of 20ps step");
return 0;
}
int16_t steps[4] = {};
// For each step we set the MSn_PHIDCT
static TERMUI_CON_COMMAND_PROTOTYPE(set_phase) {
uint8_t pll_num = strto_intl16(argv[0], NULL, 0);
int16_t step = strto_intl16(argv[1], NULL, 0);
termui_con_printf(con, "%d, %d\n", pll_num, step);
// pll registers
pll_num = pll_num * 11 + 52;
// inc = value to write
uint8_t inc = 0;
if(step > 0) inc = 2;
else if(step < 0) {
step = step *-1;
inc = 3;
} else return 0;
// phase inc/dec should be limited by i2c speed
// si5338.pdf page 27
struct dev_i2c_ctrl_transaction_rq_s rq;
struct dev_i2c_ctrl_transaction_data_s transfer[1];
dev_i2c_transaction_init(&rq);
rq.base.saddr = 0x70;
rq.transfer = transfer;
rq.transfer_count = 1;
uint8_t dwrite[2];
dwrite[0] = pll_num;
dwrite[1] = inc;
transfer[0].data = dwrite;
transfer[0].size = 2;
transfer[0].type = DEV_I2C_CTRL_TRANSACTION_WRITE;
for(int16_t i = 0; i < step; i++) {
dev_i2c_wait_transaction(&pll_i2c, &rq);
}
return 0;
}
static TERMUI_CON_GROUP_DECL(root_group) = {
TERMUI_CON_BUILTIN_HELP(-1)
TERMUI_CON_BUILTIN_LIST(-1)
TERMUI_CON_BUILTIN_QUIT(-1)
TERMUI_CON_ENTRY(test_command, "test")
TERMUI_CON_ENTRY(set_phase, "set_phase", TERMUI_CON_HELP("Set phase offset by step of 20ps", NULL) TERMUI_CON_ARGS(2,2))
TERMUI_CON_LIST_END
};
MUTEK_SHELL_ROOT_GROUP(root_group, "nats")
void main() {
device_get_accessor_by_path(&dac_spi.base, NULL, "spi1", DRIVER_CLASS_SPI_CTRL);
device_get_accessor_by_path(&d_gpio.base, NULL, "gpio", DRIVER_CLASS_GPIO);
......@@ -304,8 +373,10 @@ void main() {
dac_spi_write(&dac_spi, CS_DAC, (const uint8_t*)"\x2F\xFF\x00", 3); // Set all dac to maximum
// test pll init
for(uint16_t i = 0; i < 349; i++) {
for(uint16_t i = 0; i < 351; i++) {
change_pll_reg(Reg_Store[i]);
}
return 0;
}
\ No newline at end of file
File mode changed from 100755 to 100644
......@@ -2,7 +2,7 @@
//http://www.silabs.com/clocks
//Copyright 2012 Silicon Laboratories
//#BEGIN_HEADER
//Date = Wednesday, March 15, 2017 12:09 AM
//Date = Monday, March 20, 2017 5:42 PM
//File version = 3
//Software Name = ClockBuilder Desktop
//Software version = 6.4
......@@ -63,21 +63,19 @@
// Output voltage = 3.30
// Output type = 3.3V LVDS
// Output state when disabled = StopLow
//Clock 0 phase inc/dec step size (ns) = 0.000
//Clock 1 phase inc/dec step size (ns) = 0.000
//Clock 2 phase inc/dec step size (ns) = 0.000
//Clock 0 phase inc/dec step size (ns) = 0.0200
//Clock 1 phase inc/dec step size (ns) = 0.0200
//Clock 2 phase inc/dec step size (ns) = 0.0200
//Clock 3 phase inc/dec step size (ns) = 0.000
//Phase increment and decrement pin control is off
//Frequency increment and decrement pin control is off
//Frequency increment and decrement is disabled
//Initial phase offset 0 (ns) = 0.000
//Initial phase offset 1 (ns) = 5.000
//Initial phase offset 2 (ns) = 10.000
//Initial phase offset 1 (ns) = 0.000
//Initial phase offset 2 (ns) = 0.000
//Initial phase offset 3 (ns) = 0.000
//SSC is disabled
#define NUM_REGS_MAX 350
typedef struct Reg_Data{
unsigned char Reg_Addr;
unsigned char Reg_Val;
......@@ -194,15 +192,15 @@ Reg_Data Reg_Store[] = {
{106,0x80,0xBF},
{107,0x00,0xFF},
{108,0x00,0xFF},
{109,0x00,0xFF},
{109,0x07,0xFF},
{110,0x40,0xFF},
{111,0x80,0xFF},
{112,0x06,0xFF},
{113,0x00,0xFF},
{111,0x00,0xFF},
{112,0x00,0xFF},
{113,0x07,0xFF},
{114,0x40,0xFF},
{115,0x00,0xFF},
{116,0x8D,0xFF},
{117,0x00,0xFF},
{116,0x80,0xFF},
{117,0x07,0xFF},
{118,0x40,0xFF},
{119,0x00,0xFF},
{120,0x00,0xFF},
......@@ -433,5 +431,7 @@ Reg_Data Reg_Store[] = {
{ 92,0x00,0x00},
{ 93,0x00,0x00},
{ 94,0x00,0x00},
{255, 0, 0xFF} }; // set page bit to 0
//End of file
{255,0x00,0xFF},
{246,0x02,0xFF}, // soft reset
{230,0x00,0xFF}}; // enable all output
//End of file
\ No newline at end of file
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