Commit dff8068c authored by natsfr's avatar natsfr

merge

parents a9ee692f 8565a4bb
Index: 6 : Read: 8 - Write: 8
Index: 27 : Read: 112 - Write: 112
Index: 28 : Write: 22
Index: 29 : Write: 144
Index: 30 : Write: 176
Index: 31 : Write: 192
Index: 32 : Write: 192
Index: 33 : Write: 192
Index: 34 : Write: 227
Index: 35 : Write: 0
Index: 36 : Read: 1 - Write: 1
Index: 37 : Read: 1 - Write: 1
Index: 38 : Read: 1 - Write: 1
Index: 39 : Read: 0 - Write: 0
Index: 40 : Write: 247
Index: 41 : Read: 94 - Write: 94
Index: 42 : Read: 35 - Write: 35
Index: 45 : Write: 0
Index: 46 : Write: 0
Index: 47 : Read: 20 - Write: 20
Index: 48 : Write: 53
Index: 49 : Write: 0
Index: 50 : Write: 195
Index: 51 : Write: 7
Index: 52 : Write: 16
Index: 53 : Write: 0
Index: 54 : Write: 11
Index: 55 : Write: 0
Index: 56 : Write: 0
Index: 57 : Write: 0
Index: 58 : Write: 0
Index: 59 : Write: 1
Index: 60 : Write: 0
Index: 61 : Write: 0
Index: 62 : Read: 0 - Write: 0
Index: 63 : Write: 16
Index: 64 : Write: 0
Index: 65 : Write: 11
Index: 66 : Write: 0
Index: 67 : Write: 0
Index: 68 : Write: 0
Index: 69 : Write: 0
Index: 70 : Write: 1
Index: 71 : Write: 0
Index: 72 : Write: 0
Index: 73 : Read: 0 - Write: 0
Index: 74 : Write: 16
Index: 75 : Write: 0
Index: 76 : Write: 11
Index: 77 : Write: 0
Index: 78 : Write: 0
Index: 79 : Write: 0
Index: 80 : Write: 0
Index: 81 : Write: 1
Index: 82 : Write: 0
Index: 83 : Write: 0
Index: 84 : Read: 0 - Write: 0
Index: 85 : Write: 16
Index: 86 : Write: 0
Index: 87 : Write: 0
Index: 88 : Write: 0
Index: 89 : Write: 0
Index: 90 : Write: 0
Index: 91 : Write: 0
Index: 92 : Write: 0
Index: 93 : Write: 0
Index: 94 : Write: 0
Index: 95 : Read: 0 - Write: 0
Index: 97 : Write: 0
Index: 98 : Write: 50
Index: 99 : Write: 0
Index: 100 : Write: 0
Index: 101 : Write: 0
Index: 102 : Write: 0
Index: 103 : Write: 1
Index: 104 : Write: 0
Index: 105 : Write: 0
Index: 106 : Read: 128 - Write: 128
Index: 107 : Write: 0
Index: 108 : Write: 0
Index: 109 : Write: 0
Index: 110 : Write: 64
Index: 111 : Write: 128
Index: 112 : Write: 6
Index: 113 : Write: 0
Index: 114 : Write: 64
Index: 115 : Write: 0
Index: 116 : Write: 141
Index: 117 : Write: 0
Index: 118 : Write: 64
Index: 119 : Write: 0
Index: 120 : Write: 0
Index: 121 : Write: 0
Index: 122 : Write: 64
Index: 123 : Write: 0
Index: 124 : Write: 0
Index: 125 : Write: 0
Index: 126 : Write: 0
Index: 127 : Write: 0
Index: 128 : Write: 0
Index: 129 : Read: 0 - Write: 0
Index: 130 : Read: 0 - Write: 0
Index: 131 : Write: 0
Index: 132 : Write: 0
Index: 133 : Write: 0
Index: 134 : Write: 0
Index: 135 : Write: 0
Index: 136 : Write: 0
Index: 137 : Write: 0
Index: 138 : Write: 0
Index: 139 : Write: 0
Index: 140 : Write: 0
Index: 141 : Write: 0
Index: 142 : Write: 0
Index: 143 : Write: 0
Index: 144 : Write: 0
Index: 152 : Write: 0
Index: 153 : Write: 0
Index: 154 : Write: 0
Index: 155 : Write: 0
Index: 156 : Write: 0
Index: 157 : Write: 0
Index: 158 : Read: 0 - Write: 0
Index: 159 : Read: 0 - Write: 0
Index: 160 : Write: 0
Index: 161 : Write: 0
Index: 162 : Write: 0
Index: 163 : Write: 0
Index: 164 : Write: 0
Index: 165 : Write: 0
Index: 166 : Write: 0
Index: 167 : Write: 0
Index: 168 : Write: 0
Index: 169 : Write: 0
Index: 170 : Write: 0
Index: 171 : Write: 0
Index: 172 : Write: 0
Index: 173 : Write: 0
Index: 174 : Write: 0
Index: 175 : Write: 0
Index: 176 : Write: 0
Index: 177 : Write: 0
Index: 178 : Write: 0
Index: 179 : Write: 0
Index: 180 : Write: 0
Index: 181 : Read: 0 - Write: 0
Index: 182 : Write: 0
Index: 183 : Write: 0
Index: 184 : Write: 0
Index: 185 : Write: 0
Index: 186 : Write: 0
Index: 187 : Write: 0
Index: 188 : Write: 0
Index: 189 : Write: 0
Index: 190 : Write: 0
Index: 191 : Write: 0
Index: 192 : Write: 0
Index: 193 : Write: 0
Index: 194 : Write: 0
Index: 195 : Write: 0
Index: 196 : Write: 0
Index: 197 : Write: 0
Index: 198 : Write: 0
Index: 199 : Write: 0
Index: 200 : Write: 0
Index: 201 : Write: 0
Index: 202 : Write: 0
Index: 203 : Read: 0 - Write: 0
Index: 204 : Write: 0
Index: 205 : Write: 0
Index: 206 : Write: 0
Index: 207 : Write: 0
Index: 208 : Write: 0
Index: 209 : Write: 0
Index: 210 : Write: 0
Index: 211 : Write: 0
Index: 212 : Write: 0
Index: 213 : Write: 0
Index: 214 : Write: 0
Index: 215 : Write: 0
Index: 216 : Write: 0
Index: 217 : Write: 0
Index: 242 : Read: 2 - Write: 2
Index: 255 : Write: 1
Index: 31 : Write: 0
Index: 32 : Write: 0
Index: 33 : Write: 1
Index: 34 : Write: 0
Index: 35 : Write: 0
Index: 36 : Write: 144
Index: 37 : Write: 49
Index: 38 : Write: 0
Index: 39 : Write: 0
Index: 40 : Write: 1
Index: 41 : Write: 0
Index: 42 : Write: 0
Index: 43 : Read: 0 - Write: 0
Index: 47 : Write: 0
Index: 48 : Write: 0
Index: 49 : Write: 1
Index: 50 : Write: 0
Index: 51 : Write: 0
Index: 52 : Write: 144
Index: 53 : Write: 49
Index: 54 : Write: 0
Index: 55 : Write: 0
Index: 56 : Write: 1
Index: 57 : Write: 0
Index: 58 : Write: 0
Index: 59 : Read: 0 - Write: 0
Index: 63 : Write: 0
Index: 64 : Write: 0
Index: 65 : Write: 1
Index: 66 : Write: 0
Index: 67 : Write: 0
Index: 68 : Write: 144
Index: 69 : Write: 49
Index: 70 : Write: 0
Index: 71 : Write: 0
Index: 72 : Write: 1
Index: 73 : Write: 0
Index: 74 : Write: 0
Index: 75 : Read: 0 - Write: 0
Index: 79 : Write: 0
Index: 80 : Write: 0
Index: 81 : Write: 0
Index: 82 : Write: 0
Index: 83 : Write: 0
Index: 84 : Write: 144
Index: 85 : Write: 49
Index: 86 : Write: 0
Index: 87 : Write: 0
Index: 88 : Write: 1
Index: 89 : Write: 0
Index: 90 : Write: 0
Index: 91 : Read: 0 - Write: 0
Index: 255 : Write: 0
......@@ -29,7 +29,8 @@ DEV_DECLARE_STATIC(cpu_dev, "cpu", DEVICE_FLAG_CPU, arm32m_drv,
#include <arch/stm32/f1/rcc.h>
#include <mutek/startup.h>
#include "nats_i2c.h"
//#include "nats_i2c.h"
#include "register_map.h"
DEV_DECLARE_STATIC(gpio_dev, "gpio", 0, stm32_gpio_drv,
DEV_STATIC_RES_DEV_ICU("/cpu"),
......@@ -174,7 +175,7 @@ void stm32_clock_init() {
cpu_mem_write_32(STM32_RCC_ADDR + STM32_RCC_APB2ENR_ADDR, -1);
}
void nats_i2c_init() {
/*void nats_i2c_init() {
uint16_t cr1_old = 0;
uint16_t cr2_old = 0;
uint16_t ccr_old = 0;
......@@ -191,9 +192,10 @@ void nats_i2c_init() {
cpu_mem_write_16(NATS_I2C1_ADDR + NATS_I2C_CCR_ADDR, ccr_old); // set SCK ~= 50kHz
cpu_mem_write_16(NATS_I2C1_ADDR + NATS_I2C_TRISE_ADDR, 0x0025);
}
}*/
struct device_spi_ctrl_s dac_spi;
struct device_i2c_ctrl_s pll_i2c;
struct device_gpio_s d_gpio;
void dac_spi_write(struct device_spi_ctrl_s *spi, uint32_t cs_pin, uint8_t *data, size_t s) {
......@@ -212,9 +214,61 @@ void app_start() {
}
void change_pll_reg(Reg_Data si_reg) {
uint8_t read_buf[1];
struct dev_i2c_ctrl_transaction_rq_s rq;
dev_i2c_transaction_init(&rq);
struct dev_i2c_ctrl_transaction_data_s transfers[2];
rq.base.saddr = 0x70;
rq.transfer = transfers;
if(si_reg.Reg_Mask == 0xFF) {
uint8_t dwrite[2];
dwrite[0] = si_reg.Reg_Addr;
dwrite[1] = si_reg.Reg_Val;
transfers[0].data = dwrite;
transfers[0].size = 2;
transfers[0].type = DEV_I2C_CTRL_TRANSACTION_WRITE;
rq.transfer_count = 1;
dev_i2c_wait_transaction(&pll_i2c, &rq);
printk("Index: %d : Write: %d\n", si_reg.Reg_Addr, dwrite[1]);
} else if(si_reg.Reg_Mask != 0x00) {
uint8_t dwrite[2];
dwrite[0] = si_reg.Reg_Addr;
transfers[0].data = dwrite;
transfers[0].size = 1;
transfers[0].type = DEV_I2C_CTRL_TRANSACTION_WRITE;
rq.transfer_count = 1;
dev_i2c_wait_transaction(&pll_i2c, &rq);
transfers[0].data = read_buf;
transfers[0].size = sizeof(read_buf);
transfers[0].type = DEV_I2C_CTRL_TRANSACTION_READ;
rq.transfer_count = 1;
dev_i2c_wait_transaction(&pll_i2c, &rq);
dwrite[0] = si_reg.Reg_Addr;
dwrite[1] = (read_buf[0] & (~si_reg.Reg_Mask)) | (si_reg.Reg_Val & si_reg.Reg_Mask);
transfers[0].data = dwrite;
transfers[0].size = 2;
transfers[0].type = DEV_I2C_CTRL_TRANSACTION_WRITE;
rq.transfer_count = 1;
dev_i2c_wait_transaction(&pll_i2c, &rq);
printk("Index: %d : Read: %d - Write: %d\n", si_reg.Reg_Addr, read_buf[0], dwrite[1]);
}
}
void main() {
device_get_accessor_by_path(&dac_spi.base, NULL, "spi1", DRIVER_CLASS_SPI_CTRL);
device_get_accessor_by_path(&d_gpio.base, NULL, "gpio", DRIVER_CLASS_GPIO);
device_get_accessor_by_path(&pll_i2c.base, NULL, "i2c0", DRIVER_CLASS_I2C_CTRL);
// Init LED BECAUSE U NO RAVE PARTY !
dev_gpio_mode(&d_gpio, RED_LED, DEV_PIN_PUSHPULL);
......@@ -249,6 +303,9 @@ void main() {
dac_spi_write(&dac_spi, CS_DAC, (const uint8_t*)"\x75\x00\x00", 3); // Set all ref to internal 2.5V
dac_spi_write(&dac_spi, CS_DAC, (const uint8_t*)"\x2F\xFF\x00", 3); // Set all dac to maximum
//nats_i2c_init();
// test pll init
for(uint16_t i = 0; i < 349; i++) {
change_pll_reg(Reg_Store[i]);
}
}
\ No newline at end of file
//Register map for use with AN428 (JumpStart)
//http://www.silabs.com/clocks
//Copyright 2012 Silicon Laboratories
//#BEGIN_HEADER
//Date = Wednesday, March 15, 2017 12:09 AM
//File version = 3
//Software Name = ClockBuilder Desktop
//Software version = 6.4
//Software date = October 8, 2014
//Chip = Si5338
//Part Number = Si5338
//#END_HEADER
//Input Frequency (MHz) = 25.000000000
//Input Type = Crystal
//P1 = 1
//Input Mux = XoClk
//FDBK Input Frequency (MHz) = 25.000000000
//FDBK Input Type = OFF
//P2 = 1
//FDBK Mux = NoClk
//PFD Input Frequency (MHz) = 25.000000000
//VCO Frequency (GHz) = 2.600000
//N = 104 (104.0000)
//Internal feedback enabled
//Output Clock 0
// Output Frequency (MHz) = 100.000000000
// Mux Selection = IDn
// MultiSynth = 26 (26.0000)
// R = 1
//Output Clock 1
// Output Frequency (MHz) = 100.000000000
// Mux Selection = IDn
// MultiSynth = 26 (26.0000)
// R = 1
//Output Clock 2
// Output Frequency (MHz) = 100.000000000
// Mux Selection = IDn
// MultiSynth = 26 (26.0000)
// R = 1
//Output Clock 3
// Output is off
//Driver 0
// Enabled
// Powered on
// Output voltage = 3.30
// Output type = 3.3V CMOS on A
// Output state when disabled = StopLow
//Driver 1
// Enabled
// Powered on
// Output voltage = 3.30
// Output type = 3.3V CMOS on A
// Output state when disabled = StopLow
//Driver 2
// Enabled
// Powered on
// Output voltage = 3.30
// Output type = 3.3V CMOS on A
// Output state when disabled = StopLow
//Driver 3
// Disabled
// Powered off
// Output voltage = 3.30
// Output type = 3.3V LVDS
// Output state when disabled = StopLow
//Clock 0 phase inc/dec step size (ns) = 0.000
//Clock 1 phase inc/dec step size (ns) = 0.000
//Clock 2 phase inc/dec step size (ns) = 0.000
//Clock 3 phase inc/dec step size (ns) = 0.000
//Phase increment and decrement pin control is off
//Frequency increment and decrement pin control is off
//Frequency increment and decrement is disabled
//Initial phase offset 0 (ns) = 0.000
//Initial phase offset 1 (ns) = 5.000
//Initial phase offset 2 (ns) = 10.000
//Initial phase offset 3 (ns) = 0.000
//SSC is disabled
#define NUM_REGS_MAX 350
typedef struct Reg_Data{
unsigned char Reg_Addr;
unsigned char Reg_Val;
unsigned char Reg_Mask;
} Reg_Data;
Reg_Data Reg_Store[] = {
{ 0,0x00,0x00},
{ 1,0x00,0x00},
{ 2,0x00,0x00},
{ 3,0x00,0x00},
{ 4,0x00,0x00},
{ 5,0x00,0x00},
{ 6,0x08,0x1D},
{ 7,0x00,0x00},
{ 8,0x70,0x00},
{ 9,0x0F,0x00},
{ 10,0x00,0x00},
{ 11,0x00,0x00},
{ 12,0x00,0x00},
{ 13,0x00,0x00},
{ 14,0x00,0x00},
{ 15,0x00,0x00},
{ 16,0x00,0x00},
{ 17,0x00,0x00},
{ 18,0x00,0x00},
{ 19,0x00,0x00},
{ 20,0x00,0x00},
{ 21,0x00,0x00},
{ 22,0x00,0x00},
{ 23,0x00,0x00},
{ 24,0x00,0x00},
{ 25,0x00,0x00},
{ 26,0x00,0x00},
{ 27,0x70,0x80},
{ 28,0x16,0xFF},
{ 29,0x90,0xFF},
{ 30,0xB0,0xFF},
{ 31,0xC0,0xFF},
{ 32,0xC0,0xFF},
{ 33,0xC0,0xFF},
{ 34,0xE3,0xFF},
{ 35,0x00,0xFF},
{ 36,0x01,0x1F},
{ 37,0x01,0x1F},
{ 38,0x01,0x1F},
{ 39,0x00,0x1F},
{ 40,0xF7,0xFF},
{ 41,0x5E,0x7F},
{ 42,0x23,0x3F},
{ 43,0x00,0x00},
{ 44,0x00,0x00},
{ 45,0x00,0xFF},
{ 46,0x00,0xFF},
{ 47,0x14,0x3F},
{ 48,0x35,0xFF},
{ 49,0x00,0xFF},
{ 50,0xC3,0xFF},
{ 51,0x07,0xFF},
{ 52,0x10,0xFF},
{ 53,0x00,0xFF},
{ 54,0x0B,0xFF},
{ 55,0x00,0xFF},
{ 56,0x00,0xFF},
{ 57,0x00,0xFF},
{ 58,0x00,0xFF},
{ 59,0x01,0xFF},
{ 60,0x00,0xFF},
{ 61,0x00,0xFF},
{ 62,0x00,0x3F},
{ 63,0x10,0xFF},
{ 64,0x00,0xFF},
{ 65,0x0B,0xFF},
{ 66,0x00,0xFF},
{ 67,0x00,0xFF},
{ 68,0x00,0xFF},
{ 69,0x00,0xFF},
{ 70,0x01,0xFF},
{ 71,0x00,0xFF},
{ 72,0x00,0xFF},
{ 73,0x00,0x3F},
{ 74,0x10,0xFF},
{ 75,0x00,0xFF},
{ 76,0x0B,0xFF},
{ 77,0x00,0xFF},
{ 78,0x00,0xFF},
{ 79,0x00,0xFF},
{ 80,0x00,0xFF},
{ 81,0x01,0xFF},
{ 82,0x00,0xFF},
{ 83,0x00,0xFF},
{ 84,0x00,0x3F},
{ 85,0x10,0xFF},
{ 86,0x00,0xFF},
{ 87,0x00,0xFF},
{ 88,0x00,0xFF},
{ 89,0x00,0xFF},
{ 90,0x00,0xFF},
{ 91,0x00,0xFF},
{ 92,0x00,0xFF},
{ 93,0x00,0xFF},
{ 94,0x00,0xFF},
{ 95,0x00,0x3F},
{ 96,0x10,0x00},
{ 97,0x00,0xFF},
{ 98,0x32,0xFF},
{ 99,0x00,0xFF},
{100,0x00,0xFF},
{101,0x00,0xFF},
{102,0x00,0xFF},
{103,0x01,0xFF},
{104,0x00,0xFF},
{105,0x00,0xFF},
{106,0x80,0xBF},
{107,0x00,0xFF},
{108,0x00,0xFF},
{109,0x00,0xFF},
{110,0x40,0xFF},
{111,0x80,0xFF},
{112,0x06,0xFF},
{113,0x00,0xFF},
{114,0x40,0xFF},
{115,0x00,0xFF},
{116,0x8D,0xFF},
{117,0x00,0xFF},
{118,0x40,0xFF},
{119,0x00,0xFF},
{120,0x00,0xFF},
{121,0x00,0xFF},
{122,0x40,0xFF},
{123,0x00,0xFF},
{124,0x00,0xFF},
{125,0x00,0xFF},
{126,0x00,0xFF},
{127,0x00,0xFF},
{128,0x00,0xFF},
{129,0x00,0x0F},
{130,0x00,0x0F},
{131,0x00,0xFF},
{132,0x00,0xFF},
{133,0x00,0xFF},
{134,0x00,0xFF},
{135,0x00,0xFF},
{136,0x00,0xFF},
{137,0x00,0xFF},
{138,0x00,0xFF},
{139,0x00,0xFF},
{140,0x00,0xFF},
{141,0x00,0xFF},
{142,0x00,0xFF},
{143,0x00,0xFF},
{144,0x00,0xFF},
{145,0x00,0x00},
{146,0xFF,0x00},
{147,0x00,0x00},
{148,0x00,0x00},
{149,0x00,0x00},
{150,0x00,0x00},
{151,0x00,0x00},
{152,0x00,0xFF},
{153,0x00,0xFF},
{154,0x00,0xFF},
{155,0x00,0xFF},
{156,0x00,0xFF},
{157,0x00,0xFF},
{158,0x00,0x0F},
{159,0x00,0x0F},
{160,0x00,0xFF},
{161,0x00,0xFF},
{162,0x00,0xFF},
{163,0x00,0xFF},
{164,0x00,0xFF},
{165,0x00,0xFF},
{166,0x00,0xFF},
{167,0x00,0xFF},
{168,0x00,0xFF},
{169,0x00,0xFF},
{170,0x00,0xFF},
{171,0x00,0xFF},
{172,0x00,0xFF},
{173,0x00,0xFF},
{174,0x00,0xFF},
{175,0x00,0xFF},
{176,0x00,0xFF},
{177,0x00,0xFF},
{178,0x00,0xFF},
{179,0x00,0xFF},
{180,0x00,0xFF},
{181,0x00,0x0F},
{182,0x00,0xFF},
{183,0x00,0xFF},
{184,0x00,0xFF},
{185,0x00,0xFF},
{186,0x00,0xFF},
{187,0x00,0xFF},
{188,0x00,0xFF},
{189,0x00,0xFF},
{190,0x00,0xFF},
{191,0x00,0xFF},
{192,0x00,0xFF},
{193,0x00,0xFF},
{194,0x00,0xFF},
{195,0x00,0xFF},
{196,0x00,0xFF},
{197,0x00,0xFF},
{198,0x00,0xFF},
{199,0x00,0xFF},
{200,0x00,0xFF},
{201,0x00,0xFF},
{202,0x00,0xFF},
{203,0x00,0x0F},
{204,0x00,0xFF},
{205,0x00,0xFF},
{206,0x00,0xFF},
{207,0x00,0xFF},
{208,0x00,0xFF},
{209,0x00,0xFF},
{210,0x00,0xFF},
{211,0x00,0xFF},
{212,0x00,0xFF},
{213,0x00,0xFF},
{214,0x00,0xFF},
{215,0x00,0xFF},
{216,0x00,0xFF},
{217,0x00,0xFF},
{218,0x00,0x00},
{219,0x00,0x00},
{220,0x00,0x00},
{221,0x0D,0x00},
{222,0x00,0x00},
{223,0x00,0x00},
{224,0xF4,0x00},
{225,0xF0,0x00},
{226,0x00,0x00},
{227,0x00,0x00},
{228,0x00,0x00},
{229,0x00,0x00},
{231,0x00,0x00},
{232,0x00,0x00},
{233,0x00,0x00},
{234,0x00,0x00},
{235,0x00,0x00},
{236,0x00,0x00},
{237,0x00,0x00},
{238,0x14,0x00},
{239,0x00,0x00},
{240,0x00,0x00},
{242,0x02,0x02},
{243,0xF0,0x00},
{244,0x00,0x00},
{245,0x00,0x00},
{247,0x00,0x00},
{248,0x00,0x00},
{249,0xA8,0x00},
{250,0x00,0x00},
{251,0x84,0x00},
{252,0x00,0x00},
{253,0x00,0x00},
{254,0x00,0x00},
{255, 1, 0xFF}, // set page bit to 1
{ 0,0x00,0x00},
{ 1,0x00,0x00},
{ 2,0x00,0x00},
{ 3,0x00,0x00},
{ 4,0x00,0x00},
{ 5,0x00,0x00},
{ 6,0x00,0x00},
{ 7,0x00,0x00},
{ 8,0x00,0x00},
{ 9,0x00,0x00},
{ 10,0x00,0x00},
{ 11,0x00,0x00},
{ 12,0x00,0x00},
{ 13,0x00,0x00},
{ 14,0x00,0x00},
{ 15,0x00,0x00},
{ 16,0x00,0x00},
{ 17,0x01,0x00},
{ 18,0x00,0x00},
{ 19,0x00,0x00},
{ 20,0x90,0x00},
{ 21,0x31,0x00},
{ 22,0x00,0x00},
{ 23,0x00,0x00},
{ 24,0x01,0x00},
{ 25,0x00,0x00},
{ 26,0x00,0x00},
{ 27,0x00,0x00},
{ 28,0x00,0x00},
{ 29,0x00,0x00},
{ 30,0x00,0x00},
{ 31,0x00,0xFF},
{ 32,0x00,0xFF},
{ 33,0x01,0xFF},
{ 34,0x00,0xFF},
{ 35,0x00,0xFF},
{ 36,0x90,0xFF},
{ 37,0x31,0xFF},
{ 38,0x00,0xFF},
{ 39,0x00,0xFF},
{ 40,0x01,0xFF},
{ 41,0x00,0xFF},
{ 42,0x00,0xFF},
{ 43,0x00,0x0F},
{ 44,0x00,0x00},
{ 45,0x00,0x00},
{ 46,0x00,0x00},
{ 47,0x00,0xFF},
{ 48,0x00,0xFF},
{ 49,0x01,0xFF},
{ 50,0x00,0xFF},
{ 51,0x00,0xFF},
{ 52,0x90,0xFF},
{ 53,0x31,0xFF},
{ 54,0x00,0xFF},
{ 55,0x00,0xFF},
{ 56,0x01,0xFF},
{ 57,0x00,0xFF},
{ 58,0x00,0xFF},
{ 59,0x00,0x0F},
{ 60,0x00,0x00},
{ 61,0x00,0x00},
{ 62,0x00,0x00},
{ 63,0x00,0xFF},