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`default_nettype none
`timescale 1ns / 1ps

module top(clk, rl, bl, gl);
    
  input wire clk;
  output reg rl;
  output reg bl;
  output reg gl;

  reg [15:0]counter = 16'd0;
  reg [15:0]rtrig = 16'd0;
  reg [15:0]gtrig = 16'd0;
  reg [15:0]btrig = 16'd0;

  always @(posedge clk)
  begin
    rl <= (counter <= rtrig);
    gl <= (counter <= gtrig);
    bl <= (counter <= btrig);
    counter <= counter + 16'd1;
    rtrig <= (counter == 16'hFFFF) ? rtrig + 16'd30 : rtrig;
    btrig <= (counter == 16'hFFFF) ? btrig + 16'd150 : btrig;
    gtrig <= (counter == 16'hFFFF) ? gtrig + 16'd300 : gtrig;

  end

endmodule