Commit 2fb11b94 authored by nats's avatar nats

base project example

parents
*.json
*.bin
*.asc
blink.bin: blink.v blink.pcf
yosys -p "synth_ice40 -blif blink.blif" blink.v
arachne-pnr --device 5k --package sg48 -p blink.pcf blink.blif -o blink.asc
icepack blink.asc blink.bin
icetime -d up5k -P sg48 -mt blink.asc
prog: blink.bin
iceprog blink.bin
nextblink.bin: blink.v blink.pcf
yosys -p "synth_ice40 -json blink.json" blink.v
nextpnr-ice40 --up5k --json blink.json --pcf blink.pcf --asc blink.asc
icepack blink.asc nextblink.bin
gui: blink.v blink.pcf
yosys -p "synth_ice40 -json blink.json" blink.v
nextpnr-ice40 --up5k --json blink.json --pcf blink.pcf --asc blink.asc --gui
icepack blink.asc nextblink.bin
nextprog: nextblink.bin
iceprog nextblink.bin
This diff is collapsed.
set_io clk 35
set_io rl 41
set_io gl 40
set_io bl 39
`default_nettype none
`timescale 1ns / 1ps
module top(clk, rl, bl, gl);
input wire clk;
output reg rl;
output reg bl;
output reg gl;
reg [15:0]counter = 16'd0;
reg [15:0]rtrig = 16'd0;
reg [15:0]gtrig = 16'd0;
reg [15:0]btrig = 16'd0;
always @(posedge clk)
begin
rl <= (counter <= rtrig);
gl <= (counter <= gtrig);
bl <= (counter <= btrig);
counter <= counter + 16'd1;
rtrig <= (counter == 16'hFFFF) ? rtrig + 16'd30 : rtrig;
btrig <= (counter == 16'hFFFF) ? btrig + 16'd150 : btrig;
gtrig <= (counter == 16'hFFFF) ? gtrig + 16'd300 : gtrig;
end
endmodule
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