Commit 484d2583 authored by nats's avatar nats

adding logic and gate

parent 6e290e29
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# SN74LVC1G11
#
DEF SN74LVC1G11 U 0 40 Y Y 1 F N
F0 "U" 50 200 39 H V C CNN
F1 "SN74LVC1G11" 50 250 39 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S -100 150 150 -150 0 1 0 N
X A 1 -200 100 100 R 25 25 1 1 I
X GND 2 250 -100 100 L 25 25 1 1 W
X B 3 -200 0 100 R 25 25 1 1 I
X Y 4 250 0 100 L 25 25 1 1 O
X Vcc 5 250 100 100 L 25 25 1 1 W
X C 6 -200 -100 100 R 25 25 1 1 I
ENDDRAW
ENDDEF
#
#End Library
......@@ -127,6 +127,20 @@ X +1.8VAUX 1 0 0 0 U 30 30 0 0 W N
ENDDRAW
ENDDEF
#
# +1.8VDAC
#
DEF +1.8VDAC #PWR 0 0 Y Y 1 F P
F0 "#PWR" 0 -40 30 H I C CNN
F1 "+1.8VDAC" 0 110 30 H V C CNN
F2 "" 0 0 60 H V C CNN
F3 "" 0 0 60 H V C CNN
DRAW
C 0 60 20 0 1 0 N
P 3 0 1 0 0 0 0 40 0 40 N
X +1.8VDAC 1 0 0 0 U 30 30 0 0 W N
ENDDRAW
ENDDEF
#
# +1.8VDDS
#
DEF +1.8VDDS #PWR 0 0 Y Y 1 F P
......
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