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//-----------------------------------------------------------------------------
// C8051F912_defs.h
//-----------------------------------------------------------------------------
// Copyright 2009 Silicon Laboratories, Inc.
// http://www.silabs.com
//
// Program Description:
//
// Register/bit definitions for the C8051F91x-90x family.
//
//
// Target: C8051F91x/90x
// Tool chain: Keil, SDCC
// Command Line: None
//
//
//
// Release 1.0
// -Ported from 'F93x DEFS rev 1.7 (FB)
// -2 JULY 2007
//
//-----------------------------------------------------------------------------
// Header File Preprocessor Directive
//-----------------------------------------------------------------------------
#ifndef C8051F912_DEFS_H
#define C8051F912_DEFS_H
//-----------------------------------------------------------------------------
// Byte Registers
//-----------------------------------------------------------------------------
SFR (P0, 0x80); // Port 0 Latch
SFR (SP, 0x81); // Stack Pointer
SFR (DPL, 0x82); // Data Pointer Low
SFR (DPH, 0x83); // Data Pointer High
SFR (SPI1CFG, 0x84); // SPI1 Configuration
SFR (SPI1CKR, 0x85); // SPI1 Clock Rate Control
SFR (TOFFL, 0x85); // Temperature Offset Low
SFR (SPI1DAT, 0x86); // SPI1 Data
SFR (TOFFH, 0x86); // Temperature Offset High
SFR (PCON, 0x87); // Power Control
SFR (TCON, 0x88); // Timer/Counter Control
SFR (TMOD, 0x89); // Timer/Counter Mode
SFR (TL0, 0x8A); // Timer/Counter 0 Low
SFR (TL1, 0x8B); // Timer/Counter 1 Low
SFR (TH0, 0x8C); // Timer/Counter 0 High
SFR (TH1, 0x8D); // Timer/Counter 1 High
SFR (CKCON, 0x8E); // Clock Control
SFR (PSCTL, 0x8F); // Program Store R/W Control
SFR (P1, 0x90); // Port 1 Latch
SFR (TMR3CN, 0x91); // Timer/Counter 3 Control
SFR (CRC0DAT, 0x91); // CRC0 Data
SFR (TMR3RLL, 0x92); // Timer/Counter 3 Reload Low
SFR (CRC0CN, 0x92); // CRC0 Control
SFR (TMR3RLH, 0x93); // Timer/Counter 3 Reload High
SFR (CRC0IN, 0x93); // CRC0 Input
SFR (TMR3L, 0x94); // Timer/Counter 3 Low
SFR (DC0MD, 0x94); // DC0 (DC/DC Converter) Mode
SFR (CRC0FLIP, 0x95); // CRC0 Flip
SFR (TMR3H, 0x95); // Timer/Counter 3 High
SFR (DC0CF, 0x96); // DC0 (DC/DC Converter) Configuration
SFR (CRC0AUTO, 0x96); // CRC0 Automatic Control
SFR (DC0CN, 0x97); // DC0 (DC/DC Converter) Control
SFR (CRC0CNT, 0x97); // CRC0 Automatic Flash Sector Count
SFR (SCON0, 0x98); // UART0 Control
SFR (SBUF0, 0x99); // UART0 Data Buffer
SFR (CPT1CN, 0x9A); // Comparator1 Control
SFR (CPT0CN, 0x9B); // Comparator0 Control
SFR (CPT1MD, 0x9C); // Comparator1 Mode Selection
SFR (CPT0MD, 0x9D); // Comparator0 Mode Selection
SFR (CPT1MX, 0x9E); // Comparator1 Mux Selection
SFR (CPT0MX, 0x9F); // Comparator0 Mux Selection
SFR (P2, 0xA0); // Port 2 Latch
SFR (SPI0CFG, 0xA1); // SPI0 Configuration
SFR (SPI0CKR, 0xA2); // SPI0 Clock Rate Control
SFR (SPI0DAT, 0xA3); // SPI0 Data
SFR (P0MDOUT, 0xA4); // Port 0 Output Mode Configuration
SFR (P0DRV, 0xA4); // Port 0 Drive Strength
SFR (P1MDOUT, 0xA5); // Port 1 Output Mode Configuration
SFR (P1DRV, 0xA5); // Port 1 Drive Strength
SFR (P2MDOUT, 0xA6); // Port 2 Output Mode Configuration
SFR (P2DRV, 0xA6); // Port 2 Drive Strength
SFR (SFRPAGE, 0xA7); // SFR Page
SFR (IE, 0xA8); // Interrupt Enable
SFR (CLKSEL, 0xA9); // Clock Select
SFR (EMI0CN, 0xAA); // EMIF Control
SFR (RTC0ADR, 0xAC); // RTC0 Address
SFR (RTC0DAT, 0xAD); // RTC0 Data
SFR (RTC0KEY, 0xAE); // RTC0 Key
SFR (ONESHOT, 0xAF); // ONESHOT Timing Control
SFR (SPI1CN, 0xB0); // SPI1 Control
SFR (OSCXCN, 0xB1); // External Oscillator Control
SFR (OSCICN, 0xB2); // Internal Oscillator Control
SFR (OSCICL, 0xB3); // Internal Oscillator Calibration
SFR (PMU0CF, 0xB5); // PMU0 Configuration
SFR (PMU0MD, 0xB5); // PMU0 Mode
SFR (FLSCL, 0xB6); // Flash Scale Register
SFR (FLKEY, 0xB7); // Flash Lock And Key
SFR (IP, 0xB8); // Interrupt Priority
SFR (IREF0CN, 0xB9); // Current Reference IREF0 Control
SFR (IREF0CF, 0xB9); // Current Reference IREF0 Configuration
SFR (ADC0AC, 0xBA); // ADC0 Accumulator Configuration
SFR (ADC0PWR, 0xBA); // ADC0 Burst Mode Power-Up Time
SFR (ADC0MX, 0xBB); // AMUX0 Channel Select
SFR (ADC0CF, 0xBC); // ADC0 Configuration
SFR (ADC0TK, 0xBD); // ADC0 Tracking Control
SFR (ADC0L, 0xBD); // ADC0 Low
SFR (ADC0H, 0xBE); // ADC0 High
SFR (P1MASK, 0xBF); // Port 1 Mask
SFR (SMB0CN, 0xC0); // SMBus0 Control
SFR (SMB0CF, 0xC1); // SMBus0 Configuration
SFR (SMB0DAT, 0xC2); // SMBus0 Data
SFR (ADC0GTL, 0xC3); // ADC0 Greater-Than Compare Low
SFR (ADC0GTH, 0xC4); // ADC0 Greater-Than Compare High
SFR (ADC0LTL, 0xC5); // ADC0 Less-Than Compare Word Low
SFR (ADC0LTH, 0xC6); // ADC0 Less-Than Compare Word High
SFR (P0MASK, 0xC7); // Port 0 Mask
SFR (TMR2CN, 0xC8); // Timer/Counter 2 Control
SFR (REG0CN, 0xC9); // Voltage Regulator (REG0) Control
SFR (TMR2RLL, 0xCA); // Timer/Counter 2 Reload Low
SFR (TMR2RLH, 0xCB); // Timer/Counter 2 Reload High
SFR (TMR2L, 0xCC); // Timer/Counter 2 Low
SFR (TMR2H, 0xCD); // Timer/Counter 2 High
SFR (PCA0CPM5, 0xCE); // PCA0 Module 5 Mode Register
SFR (P1MAT, 0xCF); // Port 1 Match
SFR (PSW, 0xD0); // Program Status Word
SFR (REF0CN, 0xD1); // Voltage Reference Control
SFR (PCA0CPL5, 0xD2); // PCA0 Capture 5 Low
SFR (PCA0CPH5, 0xD3); // PCA0 Capture 5 High
SFR (P0SKIP, 0xD4); // Port 0 Skip
SFR (P1SKIP, 0xD5); // Port 1 Skip
SFR (P0MAT, 0xD7); // Port 0 Match
SFR (PCA0CN, 0xD8); // PCA0 Control
SFR (PCA0MD, 0xD9); // PCA0 Mode
SFR (PCA0CPM0, 0xDA); // PCA0 Module 0 Mode Register
SFR (PCA0CPM1, 0xDB); // PCA0 Module 1 Mode Register
SFR (PCA0CPM2, 0xDC); // PCA0 Module 2 Mode Register
SFR (PCA0CPM3, 0xDD); // PCA0 Module 3 Mode Register
SFR (PCA0CPM4, 0xDE); // PCA0 Module 4 Mode Register
SFR (PCA0PWM, 0xDF); // PCA0 PWM Configuration
SFR (ACC, 0xE0); // Accumulator
SFR (XBR0, 0xE1); // Port I/O Crossbar Control 0
SFR (XBR1, 0xE2); // Port I/O Crossbar Control 1
SFR (XBR2, 0xE3); // Port I/O Crossbar Control 2
SFR (IT01CF, 0xE4); // INT0/INT1 Configuration
SFR (FLWR, 0xE5); // Flash Write Only Register
SFR (EIE1, 0xE6); // Extended Interrupt Enable 1
SFR (EIE2, 0xE7); // Extended Interrupt Enable 2
SFR (ADC0CN, 0xE8); // ADC0 Control
SFR (PCA0CPL1, 0xE9); // PCA0 Capture 1 Low
SFR (PCA0CPH1, 0xEA); // PCA0 Capture 1 High
SFR (PCA0CPL2, 0xEB); // PCA0 Capture 2 Low
SFR (PCA0CPH2, 0xEC); // PCA0 Capture 2 High
SFR (PCA0CPL3, 0xED); // PCA0 Capture 3 Low
SFR (PCA0CPH3, 0xEE); // PCA0 Capture 3 High
SFR (RSTSRC, 0xEF); // Reset Source Configuration/Status
SFR (B, 0xF0); // B Register
SFR (P0MDIN, 0xF1); // Port 0 Input Mode Configuration
SFR (P1MDIN, 0xF2); // Port 1 Input Mode Configuration
SFR (SMB0ADR, 0xF4); // SMBus Slave Address
SFR (SMB0ADM, 0xF5); // SMBus Slave Address Mask
SFR (EIP1, 0xF6); // Extended Interrupt Priority 1
SFR (EIP2, 0xF7); // Extended Interrupt Priority 2
SFR (SPI0CN, 0xF8); // SPI0 Control
SFR (PCA0L, 0xF9); // PCA0 Counter Low
SFR (PCA0H, 0xFA); // PCA0 Counter High
SFR (PCA0CPL0, 0xFB); // PCA0 Capture 0 Low
SFR (PCA0CPH0, 0xFC); // PCA0 Capture 0 High
SFR (PCA0CPL4, 0xFD); // PCA0 Capture 4 Low
SFR (PCA0CPH4, 0xFE); // PCA0 Capture 4 High
SFR (VDM0CN, 0xFF); // VDD Monitor Control
//-----------------------------------------------------------------------------
// 16-bit Register Definitions (might not be supported by all compilers)
//-----------------------------------------------------------------------------
SFR16 (DP, 0x82); // Data Pointer
SFR16 (TOFF, 0x85); // Temperature Sensor Offset
SFR16 (TMR3RL, 0x92); // Timer 3 Reload
SFR16 (TMR3, 0x94); // Timer 3 Counter
SFR16 (ADC0, 0xBD); // ADC0 Data
SFR16 (ADC0GT, 0xC3); // ADC0 Greater-Than Compare
SFR16 (ADC0LT, 0xC5); // ADC0 Less-Than Compare
SFR16 (TMR2RL, 0xCA); // Timer 2 Reload
SFR16 (TMR2, 0xCC); // Timer 2 Counter
SFR16 (PCA0CP5, 0xD2); // PCA0 Module 5 Capture/Compare
SFR16 (PCA0CP1, 0xE9); // PCA0 Module 1 Capture/Compare
SFR16 (PCA0CP2, 0xEB); // PCA0 Module 2 Capture/Compare
SFR16 (PCA0CP3, 0xED); // PCA0 Module 3 Capture/Compare
SFR16 (PCA0, 0xF9); // PCA0 Counter
SFR16 (PCA0CP0, 0xFB); // PCA0 Module 0 Capture/Compare
SFR16 (PCA0CP4, 0xFD); // PCA0 Module 4 Capture/Compare
//-----------------------------------------------------------------------------
// Indirect RTC Register Addresses
//-----------------------------------------------------------------------------
#define CAPTURE0 0x00 // RTC address of CAPTURE0 register
#define CAPTURE1 0x01 // RTC address of CAPTURE1 register
#define CAPTURE2 0x02 // RTC address of CAPTURE2 register
#define CAPTURE3 0x03 // RTC address of CAPTURE3 register
#define RTC0CN 0x04 // RTC address of RTC0CN register
#define RTC0XCN 0x05 // RTC address of RTC0XCN register
#define RTC0XCF 0x06 // RTC address of RTC0XCF register
#define RTC0PIN 0x07 // RTC address of RTC0PIN register
#define ALARM0 0x08 // RTC address of ALARM0 register
#define ALARM1 0x09 // RTC address of ALARM1 register
#define ALARM2 0x0A // RTC address of ALARM2 register
#define ALARM3 0x0B // RTC address of ALARM3 register
//-----------------------------------------------------------------------------
// Address Definitions for Bit-addressable Registers
//-----------------------------------------------------------------------------
#define SFR_P0 0x80
#define SFR_TCON 0x88
#define SFR_P1 0x90
#define SFR_SCON0 0x98
#define SFR_P2 0xA0
#define SFR_IE 0xA8
#define SFR_SPI1CN 0xB0
#define SFR_IP 0xB8
#define SFR_SMB0CN 0xC0
#define SFR_TMR2CN 0xC8
#define SFR_PSW 0xD0
#define SFR_PCA0CN 0xD8
#define SFR_ACC 0xE0
#define SFR_ADC0CN 0xE8
#define SFR_B 0xF0
#define SFR_SPI0CN 0xF8
//-----------------------------------------------------------------------------
// Bit Definitions
//-----------------------------------------------------------------------------
// TCON 0x88
SBIT (TF1, SFR_TCON, 7); // Timer 1 Overflow Flag
SBIT (TR1, SFR_TCON, 6); // Timer 1 On/Off Control
SBIT (TF0, SFR_TCON, 5); // Timer 0 Overflow Flag
SBIT (TR0, SFR_TCON, 4); // Timer 0 On/Off Control
SBIT (IE1, SFR_TCON, 3); // Ext. Interrupt 1 Edge Flag
SBIT (IT1, SFR_TCON, 2); // Ext. Interrupt 1 Type
SBIT (IE0, SFR_TCON, 1); // Ext. Interrupt 0 Edge Flag
SBIT (IT0, SFR_TCON, 0); // Ext. Interrupt 0 Type
// SCON0 0x98
SBIT (S0MODE, SFR_SCON0, 7); // UART0 Mode
// Bit6 UNUSED
SBIT (MCE0, SFR_SCON0, 5); // UART0 MCE
SBIT (REN0, SFR_SCON0, 4); // UART0 RX Enable
SBIT (TB80, SFR_SCON0, 3); // UART0 TX Bit 8
SBIT (RB80, SFR_SCON0, 2); // UART0 RX Bit 8
SBIT (TI0, SFR_SCON0, 1); // UART0 TX Interrupt Flag
SBIT (RI0, SFR_SCON0, 0); // UART0 RX Interrupt Flag
// IE 0xA8
SBIT (EA, SFR_IE, 7); // Global Interrupt Enable
SBIT (ESPI0, SFR_IE, 6); // SPI0 Interrupt Enable
SBIT (ET2, SFR_IE, 5); // Timer 2 Interrupt Enable
SBIT (ES0, SFR_IE, 4); // UART0 Interrupt Enable
SBIT (ET1, SFR_IE, 3); // Timer 1 Interrupt Enable
SBIT (EX1, SFR_IE, 2); // External Interrupt 1 Enable
SBIT (ET0, SFR_IE, 1); // Timer 0 Interrupt Enable
SBIT (EX0, SFR_IE, 0); // External Interrupt 0 Enable
// SPI1CN 0xB0
SBIT (SPIF1, SFR_SPI1CN, 7); // SPI1 Interrupt Flag
SBIT (WCOL1, SFR_SPI1CN, 6); // SPI1 Write Collision Flag
SBIT (MODF1, SFR_SPI1CN, 5); // SPI1 Mode Fault Flag
SBIT (RXOVRN1, SFR_SPI1CN, 4); // SPI1 RX Overrun Flag
SBIT (NSS1MD1, SFR_SPI1CN, 3); // SPI1 Slave Select Mode 1
SBIT (NSS1MD0, SFR_SPI1CN, 2); // SPI1 Slave Select Mode 0
SBIT (TXBMT1, SFR_SPI1CN, 1); // SPI1 TX Buffer Empty Flag
SBIT (SPI1EN, SFR_SPI1CN, 0); // SPI1 Enable
// IP 0xB8
// Bit7 UNUSED
SBIT (PSPI0, SFR_IP, 6); // SPI0 Priority
SBIT (PT2, SFR_IP, 5); // Timer 2 Priority
SBIT (PS0, SFR_IP, 4); // UART0 Priority
SBIT (PT1, SFR_IP, 3); // Timer 1 Priority
SBIT (PX1, SFR_IP, 2); // External Interrupt 1 Priority
SBIT (PT0, SFR_IP, 1); // Timer 0 Priority
SBIT (PX0, SFR_IP, 0); // External Interrupt 0 Priority
// SMB0CN 0xC0
SBIT (MASTER, SFR_SMB0CN, 7); // SMBus0 Master/Slave
SBIT (TXMODE, SFR_SMB0CN, 6); // SMBus0 Transmit Mode
SBIT (STA, SFR_SMB0CN, 5); // SMBus0 Start Flag
SBIT (STO, SFR_SMB0CN, 4); // SMBus0 Stop Flag
SBIT (ACKRQ, SFR_SMB0CN, 3); // SMBus0 Acknowledge Request
SBIT (ARBLOST, SFR_SMB0CN, 2); // SMBus0 Arbitration Lost
SBIT (ACK, SFR_SMB0CN, 1); // SMBus0 Acknowledge Flag
SBIT (SI, SFR_SMB0CN, 0); // SMBus0 Interrupt Pending Flag
// TMR2CN 0xC8
SBIT (TF2H, SFR_TMR2CN, 7); // Timer 2 High Byte Overflow Flag
SBIT (TF2L, SFR_TMR2CN, 6); // Timer 2 Low Byte Overflow Flag
SBIT (TF2LEN, SFR_TMR2CN, 5); // Timer 2 Low Byte Interrupt Enable
SBIT (TF2CEN, SFR_TMR2CN, 4); // Timer 2 Lfo Capture Enable
SBIT (T2SPLIT, SFR_TMR2CN, 3); // Timer 2 Split Mode Enable
SBIT (TR2, SFR_TMR2CN, 2); // Timer 2 On/Off Control
SBIT (T2RCLK, SFR_TMR2CN, 1); // Timer 2 Capture Mode
SBIT (T2XCLK, SFR_TMR2CN, 0); // Timer 2 External Clock Select
// PSW 0xD0
SBIT (CY, SFR_PSW, 7); // Carry Flag
SBIT (AC, SFR_PSW, 6); // Auxiliary Carry Flag
SBIT (F0, SFR_PSW, 5); // User Flag 0
SBIT (RS1, SFR_PSW, 4); // Register Bank Select 1
SBIT (RS0, SFR_PSW, 3); // Register Bank Select 0
SBIT (OV, SFR_PSW, 2); // Overflow Flag
SBIT (F1, SFR_PSW, 1); // User Flag 1
SBIT (P, SFR_PSW, 0); // Accumulator Parity Flag
// PCA0CN 0xD8
SBIT (CF, SFR_PCA0CN, 7); // PCA0 Counter Overflow Flag
SBIT (CR, SFR_PCA0CN, 6); // PCA0 Counter Run Control Bit
SBIT (CCF5, SFR_PCA0CN, 5); // PCA0 Module 5 Interrupt Flag
SBIT (CCF4, SFR_PCA0CN, 4); // PCA0 Module 4 Interrupt Flag
SBIT (CCF3, SFR_PCA0CN, 3); // PCA0 Module 3 Interrupt Flag
SBIT (CCF2, SFR_PCA0CN, 2); // PCA0 Module 2 Interrupt Flag
SBIT (CCF1, SFR_PCA0CN, 1); // PCA0 Module 1 Interrupt Flag
SBIT (CCF0, SFR_PCA0CN, 0); // PCA0 Module 0 Interrupt Flag
// ADC0CN 0xE8
SBIT (AD0EN, SFR_ADC0CN, 7); // ADC0 Enable
SBIT (BURSTEN, SFR_ADC0CN, 6); // ADC0 Burst Enable
SBIT (AD0INT, SFR_ADC0CN, 5); // ADC0 EOC Interrupt Flag
SBIT (AD0BUSY, SFR_ADC0CN, 4); // ADC0 Busy Flag
SBIT (AD0WINT, SFR_ADC0CN, 3); // ADC0 Window Interrupt Flag
SBIT (AD0CM2, SFR_ADC0CN, 2); // ADC0 Convert Start Mode Bit 2
SBIT (AD0CM1, SFR_ADC0CN, 1); // ADC0 Convert Start Mode Bit 1
SBIT (AD0CM0, SFR_ADC0CN, 0); // ADC0 Convert Start Mode Bit 0
// SPI0CN 0xF8
SBIT (SPIF0, SFR_SPI0CN, 7); // SPI0 Interrupt Flag
SBIT (WCOL0, SFR_SPI0CN, 6); // SPI0 Write Collision Flag
SBIT (MODF0, SFR_SPI0CN, 5); // SPI0 Mode Fault Flag
SBIT (RXOVRN0, SFR_SPI0CN, 4); // SPI0 RX Overrun Flag
SBIT (NSS0MD1, SFR_SPI0CN, 3); // SPI0 Slave Select Mode 1
SBIT (NSS0MD0, SFR_SPI0CN, 2); // SPI0 Slave Select Mode 0
SBIT (TXBMT0, SFR_SPI0CN, 1); // SPI0 TX Buffer Empty Flag
SBIT (SPI0EN, SFR_SPI0CN, 0); // SPI0 Enable
//-----------------------------------------------------------------------------
// Interrupt Priorities
//-----------------------------------------------------------------------------
#define INTERRUPT_INT0 0 // External Interrupt 0
#define INTERRUPT_TIMER0 1 // Timer0 Overflow
#define INTERRUPT_INT1 2 // External Interrupt 1
#define INTERRUPT_TIMER1 3 // Timer1 Overflow
#define INTERRUPT_UART0 4 // Serial Port 0
#define INTERRUPT_TIMER2 5 // Timer2 Overflow
#define INTERRUPT_SPI0 6 // Serial Peripheral Interface 0
#define INTERRUPT_SMBUS0 7 // SMBus0 Interface
#define INTERRUPT_RTC0ALARM 8 // RTC0 (SmaRTClock) Alarm
#define INTERRUPT_ADC0_WINDOW 9 // ADC0 Window Comparison
#define INTERRUPT_ADC0_EOC 10 // ADC0 End Of Conversion
#define INTERRUPT_PCA0 11 // PCA0 Peripheral
#define INTERRUPT_COMPARATOR0 12 // Comparator0
#define INTERRUPT_COMPARATOR1 13 // Comparator1
#define INTERRUPT_TIMER3 14 // Timer3 Overflow
#define INTERRUPT_VDDMON 15 // VDD Monitor Early Warning
#define INTERRUPT_PORT_MATCH 16 // Port Match
#define INTERRUPT_RTC0_OSC_FAIL 17 // RTC0 (smaRTClock) Osc. Fail
#define INTERRUPT_SPI1 18 // Serial Peripheral Interface 1
//-----------------------------------------------------------------------------
// SFR Page Definitions
//-----------------------------------------------------------------------------
#define CONFIG_PAGE 0x0F // SYSTEM AND PORT CONFIGURATION PAGE
#define LEGACY_PAGE 0x00 // LEGACY SFR PAGE
#define CRC0_PAGE 0x0F // CRC0
#define TOFF_PAGE 0x0F // TEMPERATURE SENSOR OFFSET PAGE
//-----------------------------------------------------------------------------
// Header File PreProcessor Directive
//-----------------------------------------------------------------------------
#endif // #define C8051F912_DEFS_H
//-----------------------------------------------------------------------------
// End Of File
//-----------------------------------------------------------------------------
\ No newline at end of file
spino_code/silabs_code/Si446x_CustomPacketTX/src/drivers/C8051F930_defs.h 0 → 100644
View file @ 083b3926
/** \file C8051F930_defs.h
* \brief Register/bit definitions for the C8051F93x/2x family.
*
* \b COPYRIGHT
* \n Copyright 2007 Silicon Laboratories, Inc.
* \n http://www.silabs.com
*
*/
//-----------------------------------------------------------------------------
// C8051F930_defs.h
//-----------------------------------------------------------------------------
// Copyright 2007 Silicon Laboratories, Inc.
// http://www.silabs.com
//
// Program Description:
//
// Register/bit definitions for the C8051F93x/2x family.
//
//
// Target: C8051F93x/92x
// Tool chain: Keil, SDCC
// Command Line: None
//
//
// Release 1.8
// - Removed registers specific to the 'F912 and 'F902.
// - 28 JUL 2009 (FB)
//
// Release 1.7
// - Added new registers specific to the 'F912 and 'F902.
// - Added SmaRTClock Indirect Register Addresses
// - 11 FEB 2009 (FB)
//
// Release 1.6
// - Changed SFR Address of CRC0FLIP from 0x94 to 0x95.
// - 14 AUG 2008 (FB)
//
// Release 1.5
// - Removed #include <compiler_defs.h>
// - Added definition for FLWR
// - 29 JUL 2008 (FB)
//
// Release 1.4
// - Added definitions for ONESHOT and FLSCL.
// - 4 OCT 2007 (FB)
//
// Release 1.3
// - Switched the addresses of DC0CF and DC0CN.
// - 20 SEP 2007 (FB)
//
// Release 1.2
// - Moved SPI1 to interrupt 18 and inserted smaRTClock Osc Fail in its
// original place.
// - SPI1 bit-addressable SFRs corrected to point at the correct address.
// - 7 SEP 2007 (FB, errors found by KAB)
//
// Release 1.1
// -Corrected ADC0TK address from 0xBC to 0xBD
// - 15 AUG 2007 (FB)
//
// Release 1.0
// -Ported from 'F41x DEFS rev 1.0 by FB
// -7 JUNE 2007
//
//-----------------------------------------------------------------------------
// Header File Preprocessor Directive
//-----------------------------------------------------------------------------
#ifndef C8051F930_DEFS_H
#define C8051F930_DEFS_H
//-----------------------------------------------------------------------------
// Byte Registers
//-----------------------------------------------------------------------------
SFR (P0, 0x80); // Port 0 Latch
SFR (SP, 0x81); // Stack Pointer
SFR (DPL, 0x82); // Data Pointer Low
SFR (DPH, 0x83); // Data Pointer High
SFR (SPI1CFG, 0x84); // SPI1 Configuration
SFR (SPI1CKR, 0x85); // SPI1 Clock Rate Control
SFR (TOFFL, 0x85); // Temperature Offset Low
SFR (SPI1DAT, 0x86); // SPI1 Data
SFR (TOFFH, 0x86); // Temperature Offset High
SFR (PCON, 0x87); // Power Control
SFR (TCON, 0x88); // Timer/Counter Control
SFR (TMOD, 0x89); // Timer/Counter Mode
SFR (TL0, 0x8A); // Timer/Counter 0 Low
SFR (TL1, 0x8B); // Timer/Counter 1 Low
SFR (TH0, 0x8C); // Timer/Counter 0 High
SFR (TH1, 0x8D); // Timer/Counter 1 High
SFR (CKCON, 0x8E); // Clock Control
SFR (PSCTL, 0x8F); // Program Store R/W Control
SFR (P1, 0x90); // Port 1 Latch
SFR (TMR3CN, 0x91); // Timer/Counter 3 Control
SFR (CRC0DAT, 0x91); // CRC0 Data
SFR (TMR3RLL, 0x92); // Timer/Counter 3 Reload Low
SFR (CRC0CN, 0x92); // CRC0 Control
SFR (TMR3RLH, 0x93); // Timer/Counter 3 Reload High
SFR (CRC0IN, 0x93); // CRC0 Input
SFR (TMR3L, 0x94); // Timer/Counter 3 Low
SFR (CRC0FLIP, 0x95); // CRC0 Flip
SFR (TMR3H, 0x95); // Timer/Counter 3 High
SFR (DC0CF, 0x96); // DC0 (DC/DC Converter) Configuration
SFR (CRC0AUTO, 0x96); // CRC0 Automatic Control
SFR (DC0CN, 0x97); // DC0 (DC/DC Converter) Control
SFR (CRC0CNT, 0x97); // CRC0 Automatic Flash Sector Count
SFR (SCON0, 0x98); // UART0 Control
SFR (SBUF0, 0x99); // UART0 Data Buffer
SFR (CPT1CN, 0x9A); // Comparator1 Control
SFR (CPT0CN, 0x9B); // Comparator0 Control
SFR (CPT1MD, 0x9C); // Comparator1 Mode Selection
SFR (CPT0MD, 0x9D); // Comparator0 Mode Selection
SFR (CPT1MX, 0x9E); // Comparator1 Mux Selection
SFR (CPT0MX, 0x9F); // Comparator0 Mux Selection
SFR (P2, 0xA0); // Port 2 Latch
SFR (SPI0CFG, 0xA1); // SPI0 Configuration
SFR (SPI0CKR, 0xA2); // SPI0 Clock Rate Control
SFR (SPI0DAT, 0xA3); // SPI0 Data
SFR (P0MDOUT, 0xA4); // Port 0 Output Mode Configuration
SFR (P0DRV, 0xA4); // Port 0 Drive Strength
SFR (P1MDOUT, 0xA5); // Port 1 Output Mode Configuration
SFR (P1DRV, 0xA5); // Port 1 Drive Strength
SFR (P2MDOUT, 0xA6); // Port 2 Output Mode Configuration
SFR (P2DRV, 0xA6); // Port 2 Drive Strength
SFR (SFRPAGE, 0xA7); // SFR Page
SFR (IE, 0xA8); // Interrupt Enable
SFR (CLKSEL, 0xA9); // Clock Select
SFR (EMI0CN, 0xAA); // EMIF Control
SFR (EMI0CF, 0xAB); // EMIF Configuration
SFR (RTC0ADR, 0xAC); // RTC0 Address
SFR (RTC0DAT, 0xAD); // RTC0 Data
SFR (RTC0KEY, 0xAE); // RTC0 Key
SFR (EMI0TC, 0xAF); // EMIF Timing Control
SFR (ONESHOT, 0xAF); // ONESHOT Timing Control
SFR (SPI1CN, 0xB0); // SPI1 Control
SFR (OSCXCN, 0xB1); // External Oscillator Control
SFR (OSCICN, 0xB2); // Internal Oscillator Control
SFR (OSCICL, 0xB3); // Internal Oscillator Calibration
SFR (PMU0CF, 0xB5); // PMU0 Configuration
SFR (FLSCL, 0xB6); // Flash Scale Register
SFR (FLKEY, 0xB7); // Flash Lock And Key
SFR (IP, 0xB8); // Interrupt Priority
SFR (IREF0CN, 0xB9); // Current Reference IREF0 Control
SFR (ADC0AC, 0xBA); // ADC0 Accumulator Configuration
SFR (ADC0PWR, 0xBA); // ADC0 Burst Mode Power-Up Time
SFR (ADC0MX, 0xBB); // AMUX0 Channel Select
SFR (ADC0CF, 0xBC); // ADC0 Configuration
SFR (ADC0TK, 0xBD); // ADC0 Tracking Control
SFR (ADC0L, 0xBD); // ADC0 Low
SFR (ADC0H, 0xBE); // ADC0 High
SFR (P1MASK, 0xBF); // Port 1 Mask
SFR (SMB0CN, 0xC0); // SMBus0 Control
SFR (SMB0CF, 0xC1); // SMBus0 Configuration
SFR (SMB0DAT, 0xC2); // SMBus0 Data
SFR (ADC0GTL, 0xC3); // ADC0 Greater-Than Compare Low
SFR (ADC0GTH, 0xC4); // ADC0 Greater-Than Compare High
SFR (ADC0LTL, 0xC5); // ADC0 Less-Than Compare Word Low
SFR (ADC0LTH, 0xC6); // ADC0 Less-Than Compare Word High
SFR (P0MASK, 0xC7); // Port 0 Mask
SFR (TMR2CN, 0xC8); // Timer/Counter 2 Control
SFR (REG0CN, 0xC9); // Voltage Regulator (REG0) Control
SFR (TMR2RLL, 0xCA); // Timer/Counter 2 Reload Low
SFR (TMR2RLH, 0xCB); // Timer/Counter 2 Reload High
SFR (TMR2L, 0xCC); // Timer/Counter 2 Low
SFR (TMR2H, 0xCD); // Timer/Counter 2 High
SFR (PCA0CPM5, 0xCE); // PCA0 Module 5 Mode Register
SFR (P1MAT, 0xCF); // Port 1 Match
SFR (PSW, 0xD0); // Program Status Word
SFR (REF0CN, 0xD1); // Voltage Reference Control
SFR (PCA0CPL5, 0xD2); // PCA0 Capture 5 Low
SFR (PCA0CPH5, 0xD3); // PCA0 Capture 5 High
SFR (P0SKIP, 0xD4); // Port 0 Skip
SFR (P1SKIP, 0xD5); // Port 1 Skip
SFR (P2SKIP, 0xD6); // Port 2 Skip
SFR (P0MAT, 0xD7); // Port 0 Match
SFR (PCA0CN, 0xD8); // PCA0 Control
SFR (PCA0MD, 0xD9); // PCA0 Mode
SFR (PCA0CPM0, 0xDA); // PCA0 Module 0 Mode Register
SFR (PCA0CPM1, 0xDB); // PCA0 Module 1 Mode Register
SFR (PCA0CPM2, 0xDC); // PCA0 Module 2 Mode Register
SFR (PCA0CPM3, 0xDD); // PCA0 Module 3 Mode Register
SFR (PCA0CPM4, 0xDE); // PCA0 Module 4 Mode Register
SFR (PCA0PWM, 0xDF); // PCA0 PWM Configuration
SFR (ACC, 0xE0); // Accumulator
SFR (XBR0, 0xE1); // Port I/O Crossbar Control 0
SFR (XBR1, 0xE2); // Port I/O Crossbar Control 1
SFR (XBR2, 0xE3); // Port I/O Crossbar Control 2
SFR (IT01CF, 0xE4); // INT0/INT1 Configuration
SFR (FLWR, 0xE5); // Flash Write Only Register
SFR (EIE1, 0xE6); // Extended Interrupt Enable 1
SFR (EIE2, 0xE7); // Extended Interrupt Enable 2
SFR (ADC0CN, 0xE8); // ADC0 Control
SFR (PCA0CPL1, 0xE9); // PCA0 Capture 1 Low
SFR (PCA0CPH1, 0xEA); // PCA0 Capture 1 High
SFR (PCA0CPL2, 0xEB); // PCA0 Capture 2 Low
SFR (PCA0CPH2, 0xEC); // PCA0 Capture 2 High
SFR (PCA0CPL3, 0xED); // PCA0 Capture 3 Low
SFR (PCA0CPH3, 0xEE); // PCA0 Capture 3 High
SFR (RSTSRC, 0xEF); // Reset Source Configuration/Status
SFR (B, 0xF0); // B Register
SFR (P0MDIN, 0xF1); // Port 0 Input Mode Configuration
SFR (P1MDIN, 0xF2); // Port 1 Input Mode Configuration
SFR (P2MDIN, 0xF3); // Port 2 Input Mode Configuration
SFR (SMB0ADR, 0xF4); // SMBus Slave Address
SFR (SMB0ADM, 0xF5); // SMBus Slave Address Mask
SFR (EIP1, 0xF6); // Extended Interrupt Priority 1
SFR (EIP2, 0xF7); // Extended Interrupt Priority 2
SFR (SPI0CN, 0xF8); // SPI0 Control
SFR (PCA0L, 0xF9); // PCA0 Counter Low
SFR (PCA0H, 0xFA); // PCA0 Counter High
SFR (PCA0CPL0, 0xFB); // PCA0 Capture 0 Low
SFR (PCA0CPH0, 0xFC); // PCA0 Capture 0 High
SFR (PCA0CPL4, 0xFD); // PCA0 Capture 4 Low
SFR (PCA0CPH4, 0xFE); // PCA0 Capture 4 High
SFR (VDM0CN, 0xFF); // VDD Monitor Control
//-----------------------------------------------------------------------------
// 16-bit Register Definitions (might not be supported by all compilers)
//-----------------------------------------------------------------------------
SFR16 (DP, 0x82); // Data Pointer
SFR16 (TOFF, 0x85); // Temperature Sensor Offset
SFR16 (TMR3RL, 0x92); // Timer 3 Reload
SFR16 (TMR3, 0x94); // Timer 3 Counter
SFR16 (ADC0, 0xBD); // ADC0 Data
SFR16 (ADC0GT, 0xC3); // ADC0 Greater-Than Compare
SFR16 (ADC0LT, 0xC5); // ADC0 Less-Than Compare
SFR16 (TMR2RL, 0xCA); // Timer 2 Reload
SFR16 (TMR2, 0xCC); // Timer 2 Counter
SFR16 (PCA0CP5, 0xD2); // PCA0 Module 5 Capture/Compare
SFR16 (PCA0CP1, 0xE9); // PCA0 Module 1 Capture/Compare
SFR16 (PCA0CP2, 0xEB); // PCA0 Module 2 Capture/Compare
SFR16 (PCA0CP3, 0xED); // PCA0 Module 3 Capture/Compare
SFR16 (PCA0, 0xF9); // PCA0 Counter
SFR16 (PCA0CP0, 0xFB); // PCA0 Module 0 Capture/Compare
SFR16 (PCA0CP4, 0xFD); // PCA0 Module 4 Capture/Compare
//-----------------------------------------------------------------------------
// Indirect RTC Register Addresses
//-----------------------------------------------------------------------------
#define CAPTURE0 0x00 // RTC address of CAPTURE0 register
#define CAPTURE1 0x01 // RTC address of CAPTURE1 register
#define CAPTURE2 0x02 // RTC address of CAPTURE2 register
#define CAPTURE3 0x03 // RTC address of CAPTURE3 register
#define RTC0CN 0x04 // RTC address of RTC0CN register
#define RTC0XCN 0x05 // RTC address of RTC0XCN register
#define RTC0XCF 0x06 // RTC address of RTC0XCF register
#define RTC0PIN 0x07 // RTC address of RTC0PIN register
#define ALARM0 0x08 // RTC address of ALARM0 register
#define ALARM1 0x09 // RTC address of ALARM1 register
#define ALARM2 0x0A // RTC address of ALARM2 register
#define ALARM3 0x0B // RTC address of ALARM3 register
//-----------------------------------------------------------------------------
// Address Definitions for Bit-addressable Registers
//-----------------------------------------------------------------------------
#define SFR_P0 0x80
#define SFR_TCON 0x88
#define SFR_P1 0x90
#define SFR_SCON0 0x98
#define SFR_P2 0xA0
#define SFR_IE 0xA8
#define SFR_SPI1CN 0xB0
#define SFR_IP 0xB8
#define SFR_SMB0CN 0xC0
#define SFR_TMR2CN 0xC8
#define SFR_PSW 0xD0
#define SFR_PCA0CN 0xD8
#define SFR_ACC 0xE0
#define SFR_ADC0CN 0xE8
#define SFR_B 0xF0
#define SFR_SPI0CN 0xF8
//-----------------------------------------------------------------------------
// Bit Definitions
//-----------------------------------------------------------------------------
// TCON 0x88
SBIT (TF1, SFR_TCON, 7); // Timer 1 Overflow Flag
SBIT (TR1, SFR_TCON, 6); // Timer 1 On/Off Control
SBIT (TF0, SFR_TCON, 5); // Timer 0 Overflow Flag
SBIT (TR0, SFR_TCON, 4); // Timer 0 On/Off Control
SBIT (IE1, SFR_TCON, 3); // Ext. Interrupt 1 Edge Flag
SBIT (IT1, SFR_TCON, 2); // Ext. Interrupt 1 Type
SBIT (IE0, SFR_TCON, 1); // Ext. Interrupt 0 Edge Flag
SBIT (IT0, SFR_TCON, 0); // Ext. Interrupt 0 Type
// SCON0 0x98
SBIT (S0MODE, SFR_SCON0, 7); // UART0 Mode
// Bit6 UNUSED
SBIT (MCE0, SFR_SCON0, 5); // UART0 MCE
SBIT (REN0, SFR_SCON0, 4); // UART0 RX Enable
SBIT (TB80, SFR_SCON0, 3); // UART0 TX Bit 8
SBIT (RB80, SFR_SCON0, 2); // UART0 RX Bit 8
SBIT (TI0, SFR_SCON0, 1); // UART0 TX Interrupt Flag
SBIT (RI0, SFR_SCON0, 0); // UART0 RX Interrupt Flag
// IE 0xA8
SBIT (EA, SFR_IE, 7); // Global Interrupt Enable
SBIT (ESPI0, SFR_IE, 6); // SPI0 Interrupt Enable
SBIT (ET2, SFR_IE, 5); // Timer 2 Interrupt Enable
SBIT (ES0, SFR_IE, 4); // UART0 Interrupt Enable
SBIT (ET1, SFR_IE, 3); // Timer 1 Interrupt Enable
SBIT (EX1, SFR_IE, 2); // External Interrupt 1 Enable
SBIT (ET0, SFR_IE, 1); // Timer 0 Interrupt Enable
SBIT (EX0, SFR_IE, 0); // External Interrupt 0 Enable
// SPI1CN 0xB0
SBIT (SPIF1, SFR_SPI1CN, 7); // SPI1 Interrupt Flag
SBIT (WCOL1, SFR_SPI1CN, 6); // SPI1 Write Collision Flag
SBIT (MODF1, SFR_SPI1CN, 5); // SPI1 Mode Fault Flag
SBIT (RXOVRN1, SFR_SPI1CN, 4); // SPI1 RX Overrun Flag
SBIT (NSS1MD1, SFR_SPI1CN, 3); // SPI1 Slave Select Mode 1
SBIT (NSS1MD0, SFR_SPI1CN, 2); // SPI1 Slave Select Mode 0
SBIT (TXBMT1, SFR_SPI1CN, 1); // SPI1 TX Buffer Empty Flag
SBIT (SPI1EN, SFR_SPI1CN, 0); // SPI1 Enable
// IP 0xB8
// Bit7 UNUSED
SBIT (PSPI0, SFR_IP, 6); // SPI0 Priority
SBIT (PT2, SFR_IP, 5); // Timer 2 Priority
SBIT (PS0, SFR_IP, 4); // UART0 Priority
SBIT (PT1, SFR_IP, 3); // Timer 1 Priority
SBIT (PX1, SFR_IP, 2); // External Interrupt 1 Priority
SBIT (PT0, SFR_IP, 1); // Timer 0 Priority
SBIT (PX0, SFR_IP, 0); // External Interrupt 0 Priority
// SMB0CN 0xC0
SBIT (MASTER, SFR_SMB0CN, 7); // SMBus0 Master/Slave
SBIT (TXMODE, SFR_SMB0CN, 6); // SMBus0 Transmit Mode
SBIT (STA, SFR_SMB0CN, 5); // SMBus0 Start Flag
SBIT (STO, SFR_SMB0CN, 4); // SMBus0 Stop Flag
SBIT (ACKRQ, SFR_SMB0CN, 3); // SMBus0 Acknowledge Request
SBIT (ARBLOST, SFR_SMB0CN, 2); // SMBus0 Arbitration Lost
SBIT (ACK, SFR_SMB0CN, 1); // SMBus0 Acknowledge Flag
SBIT (SI, SFR_SMB0CN, 0); // SMBus0 Interrupt Pending Flag
// TMR2CN 0xC8
SBIT (TF2H, SFR_TMR2CN, 7); // Timer 2 High Byte Overflow Flag
SBIT (TF2L, SFR_TMR2CN, 6); // Timer 2 Low Byte Overflow Flag
SBIT (TF2LEN, SFR_TMR2CN, 5); // Timer 2 Low Byte Interrupt Enable
SBIT (TF2CEN, SFR_TMR2CN, 4); // Timer 2 Lfo Capture Enable
SBIT (T2SPLIT, SFR_TMR2CN, 3); // Timer 2 Split Mode Enable
SBIT (TR2, SFR_TMR2CN, 2); // Timer 2 On/Off Control
SBIT (T2RCLK, SFR_TMR2CN, 1); // Timer 2 Capture Mode
SBIT (T2XCLK, SFR_TMR2CN, 0); // Timer 2 External Clock Select
// PSW 0xD0
SBIT (CY, SFR_PSW, 7); // Carry Flag
SBIT (AC, SFR_PSW, 6); // Auxiliary Carry Flag
SBIT (F0, SFR_PSW, 5); // User Flag 0
SBIT (RS1, SFR_PSW, 4); // Register Bank Select 1
SBIT (RS0, SFR_PSW, 3); // Register Bank Select 0
SBIT (OV, SFR_PSW, 2); // Overflow Flag
SBIT (F1, SFR_PSW, 1); // User Flag 1
SBIT (P, SFR_PSW, 0); // Accumulator Parity Flag
// PCA0CN 0xD8
SBIT (CF, SFR_PCA0CN, 7); // PCA0 Counter Overflow Flag
SBIT (CR, SFR_PCA0CN, 6); // PCA0 Counter Run Control Bit
SBIT (CCF5, SFR_PCA0CN, 5); // PCA0 Module 5 Interrupt Flag
SBIT (CCF4, SFR_PCA0CN, 4); // PCA0 Module 4 Interrupt Flag
SBIT (CCF3, SFR_PCA0CN, 3); // PCA0 Module 3 Interrupt Flag
SBIT (CCF2, SFR_PCA0CN, 2); // PCA0 Module 2 Interrupt Flag
SBIT (CCF1, SFR_PCA0CN, 1); // PCA0 Module 1 Interrupt Flag
SBIT (CCF0, SFR_PCA0CN, 0); // PCA0 Module 0 Interrupt Flag
// ADC0CN 0xE8
SBIT (AD0EN, SFR_ADC0CN, 7); // ADC0 Enable
SBIT (BURSTEN, SFR_ADC0CN, 6); // ADC0 Burst Enable
SBIT (AD0INT, SFR_ADC0CN, 5); // ADC0 EOC Interrupt Flag
SBIT (AD0BUSY, SFR_ADC0CN, 4); // ADC0 Busy Flag
SBIT (AD0WINT, SFR_ADC0CN, 3); // ADC0 Window Interrupt Flag
SBIT (AD0CM2, SFR_ADC0CN, 2); // ADC0 Convert Start Mode Bit 2
SBIT (AD0CM1, SFR_ADC0CN, 1); // ADC0 Convert Start Mode Bit 1
SBIT (AD0CM0, SFR_ADC0CN, 0); // ADC0 Convert Start Mode Bit 0
// SPI0CN 0xF8
SBIT (SPIF0, SFR_SPI0CN, 7); // SPI0 Interrupt Flag
SBIT (WCOL0, SFR_SPI0CN, 6); // SPI0 Write Collision Flag
SBIT (MODF0, SFR_SPI0CN, 5); // SPI0 Mode Fault Flag
SBIT (RXOVRN0, SFR_SPI0CN, 4); // SPI0 RX Overrun Flag
SBIT (NSS0MD1, SFR_SPI0CN, 3); // SPI0 Slave Select Mode 1
SBIT (NSS0MD0, SFR_SPI0CN, 2); // SPI0 Slave Select Mode 0
SBIT (TXBMT0, SFR_SPI0CN, 1); // SPI0 TX Buffer Empty Flag
SBIT (SPI0EN, SFR_SPI0CN, 0); // SPI0 Enable
//-----------------------------------------------------------------------------
// Interrupt Priorities
//-----------------------------------------------------------------------------
#define INTERRUPT_INT0 0 // External Interrupt 0
#define INTERRUPT_TIMER0 1 // Timer0 Overflow
#define INTERRUPT_INT1 2 // External Interrupt 1
#define INTERRUPT_TIMER1 3 // Timer1 Overflow
#define INTERRUPT_UART0 4 // Serial Port 0
#define INTERRUPT_TIMER2 5 // Timer2 Overflow
#define INTERRUPT_SPI0 6 // Serial Peripheral Interface 0
#define INTERRUPT_SMBUS0 7 // SMBus0 Interface
#define INTERRUPT_RTC0ALARM 8 // RTC0 (SmaRTClock) Alarm
#define INTERRUPT_ADC0_WINDOW 9 // ADC0 Window Comparison
#define INTERRUPT_ADC0_EOC 10 // ADC0 End Of Conversion
#define INTERRUPT_PCA0 11 // PCA0 Peripheral
#define INTERRUPT_COMPARATOR0 12 // Comparator0
#define INTERRUPT_COMPARATOR1 13 // Comparator1
#define INTERRUPT_TIMER3 14 // Timer3 Overflow
#define INTERRUPT_VDDMON 15 // VDD Monitor Early Warning
#define INTERRUPT_PORT_MATCH 16 // Port Match
#define INTERRUPT_RTC0_OSC_FAIL 17 // RTC0 (smaRTClock) Osc. Fail
#define INTERRUPT_SPI1 18 // Serial Peripheral Interface 1
//-----------------------------------------------------------------------------
// SFR Page Definitions
//-----------------------------------------------------------------------------
#define CONFIG_PAGE 0x0F // SYSTEM AND PORT CONFIGURATION PAGE
#define LEGACY_PAGE 0x00 // LEGACY SFR PAGE
#define CRC0_PAGE 0x0F // CRC0
#define TOFF_PAGE 0x0F // TEMPERATURE SENSOR OFFSET PAGE
//-----------------------------------------------------------------------------
// Header File PreProcessor Directive
//-----------------------------------------------------------------------------
#endif // #define C8051F930_DEFS_H
//-----------------------------------------------------------------------------
// End Of File
//-----------------------------------------------------------------------------
spino_code/silabs_code/Si446x_CustomPacketTX/src/drivers/C8051F930_defs_add.h 0 → 100644
View file @ 083b3926
/*! @file C8051F930_defs_add.h
* @brief This file contains additional bit and bit-field definitions of registers for the C8051F93x/2x family.
*
* <b> AUTOMATICALLY GENERATED FILE. MAY CONTAIN MISTMATCH TO DATASHEET! </b>
*
* @b COPYRIGHT
* @n Copyright 2012 Silicon Laboratories, Inc.
* @n http://www.silabs.com
*
*/
#ifndef C8051F930_DEFS_ADD_H_
#define C8051F930_DEFS_ADD_H_
// SFR Definition 5.1. ADC0CN: ADC0 Control
#define B_AD0EN 7 // ADC0 Enable.
#define M_AD0EN 0x80 // ADC0 Enable.
#define B_BURSTEN 6 // ADC0 Burst Mode Enable.
#define M_BURSTEN 0x40 // ADC0 Burst Mode Enable.
#define B_AD0INT 5 // ADC0 Conversion Complete Interrupt Flag.
#define M_AD0INT 0x20 // ADC0 Conversion Complete Interrupt Flag.
#define B_AD0BUSY 4 // ADC0 Busy.
#define M_AD0BUSY 0x10 // ADC0 Busy.
#define B_AD0WINT 3 // ADC0 Window Compare Interrupt Flag.
#define M_AD0WINT 0x08 // ADC0 Window Compare Interrupt Flag.
#define BF_ADC0CM 0 // ADC0 Start of Conversion Mode Select.
#define BF_ADC0CM_0 0 // ADC0 Start of Conversion Mode Select.
#define BF_ADC0CM_1 1 // ADC0 Start of Conversion Mode Select.
#define BF_ADC0CM_2 2 // ADC0 Start of Conversion Mode Select.
#define M_ADC0CM 0x07 // ADC0 Start of Conversion Mode Select.
// SFR Definition 5.2. ADC0CF: ADC0 Configuration
#define BF_AD0SC 3 // ADC0 SAR Conversion Clock Divider.
#define BF_AD0SC_0 3 // ADC0 SAR Conversion Clock Divider.
#define BF_AD0SC_1 4 // ADC0 SAR Conversion Clock Divider.
#define BF_AD0SC_2 5 // ADC0 SAR Conversion Clock Divider.
#define BF_AD0SC_3 6 // ADC0 SAR Conversion Clock Divider.
#define BF_AD0SC_4 7 // ADC0 SAR Conversion Clock Divider.
#define M_AD0SC 0xF8 // ADC0 SAR Conversion Clock Divider.
#define B_AD08BE 2 // ADC0 8-Bit Mode Enable.
#define M_AD08BE 0x04 // ADC0 8-Bit Mode Enable.
#define B_AD0TM 1 // ADC0 Track Mode.
#define M_AD0TM 0x02 // ADC0 Track Mode.
#define B_AMP0GN 0 // ADC0 Gain Control.
#define M_AMP0GN 0x01 // ADC0 Gain Control.
// SFR Definition 5.3. ADC0AC: ADC0 Accumulator Configuration
#define B_AD0AE 6 // ADC0 Accumulate Enable.
#define M_AD0AE 0x40 // ADC0 Accumulate Enable.
#define BF_AD0SJST 3 // ADC0 Accumulator Shift and Justify.
#define BF_AD0SJST_0 3 // ADC0 Accumulator Shift and Justify.
#define BF_AD0SJST_1 4 // ADC0 Accumulator Shift and Justify.
#define BF_AD0SJST_2 5 // ADC0 Accumulator Shift and Justify.
#define M_AD0SJST 0x38 // ADC0 Accumulator Shift and Justify.
#define BF_AD0RPT 0 // ADC0 Repeat Count.
#define BF_AD0RPT_0 0 // ADC0 Repeat Count.
#define BF_AD0RPT_1 1 // ADC0 Repeat Count.
#define BF_AD0RPT_2 2 // ADC0 Repeat Count.
#define M_AD0RPT 0x07 // ADC0 Repeat Count.
// SFR Definition 5.4. ADC0PWR: ADC0 Burst Mode Power-Up Time
#define BF_AD0PWR 0 // ADC0 Burst Mode Power-Up Time.
#define BF_AD0PWR_0 0 // ADC0 Burst Mode Power-Up Time.
#define BF_AD0PWR_1 1 // ADC0 Burst Mode Power-Up Time.
#define BF_AD0PWR_2 2 // ADC0 Burst Mode Power-Up Time.
#define BF_AD0PWR_3 3 // ADC0 Burst Mode Power-Up Time.
#define M_AD0PWR 0x0F // ADC0 Burst Mode Power-Up Time.
// SFR Definition 5.5. ADC0TK: ADC0 Burst Mode Track Time
#define BF_AD0TK 0 // ADC0 Burst Mode Track Time.
#define BF_AD0TK_0 0 // ADC0 Burst Mode Track Time.
#define BF_AD0TK_1 1 // ADC0 Burst Mode Track Time.
#define BF_AD0TK_2 2 // ADC0 Burst Mode Track Time.
#define BF_AD0TK_3 3 // ADC0 Burst Mode Track Time.
#define BF_AD0TK_4 4 // ADC0 Burst Mode Track Time.
#define BF_AD0TK_5 5 // ADC0 Burst Mode Track Time.
#define M_AD0TK 0x3F // ADC0 Burst Mode Track Time.
// SFR Definition 5.12. ADC0MX: ADC0 Input Channel Select
#define BF_AD0MX 0 // AMUX0 Positive Input Selection.
#define BF_AD0MX_0 0 // AMUX0 Positive Input Selection.
#define BF_AD0MX_1 1 // AMUX0 Positive Input Selection.
#define BF_AD0MX_2 2 // AMUX0 Positive Input Selection.
#define BF_AD0MX_3 3 // AMUX0 Positive Input Selection.
#define BF_AD0MX_4 4 // AMUX0 Positive Input Selection.
#define M_AD0MX 0x1F // AMUX0 Positive Input Selection.
// SFR Definition 5.14. TOFFL: ADC0 Data Word Low Byte
#define BF_TOFF 6 // Temperature Sensor Offset Low Bits.
#define BF_TOFF_0 6 // Temperature Sensor Offset Low Bits.
#define BF_TOFF_1 7 // Temperature Sensor Offset Low Bits.
#define M_TOFF 0xC0 // Temperature Sensor Offset Low Bits.
// SFR Definition 5.15. REF0CN: Voltage Reference Control
#define B_REFGND 5 // Analog Ground Reference.
#define M_REFGND 0x20 // Analog Ground Reference.
#define BF_REFSL 3 // Voltage Reference Select.
#define BF_REFSL_0 3 // Voltage Reference Select.
#define BF_REFSL_1 4 // Voltage Reference Select.
#define M_REFSL 0x18 // Voltage Reference Select.
#define B_TEMPE 2 // Temperature Sensor Enable.
#define M_TEMPE 0x04 // Temperature Sensor Enable.
#define B_REFOE 0 // Internal Voltage Refe rence Output Enable.
#define M_REFOE 0x01 // Internal Voltage Refe rence Output Enable.
// SFR Definition 6.1. IREF0CN: Current Reference Control
#define B_SINK 7 // IREF0 Current Sink Enable.
#define M_SINK 0x80 // IREF0 Current Sink Enable.
#define B_MDSEL 6 // IREF0 Output Mode Select.
#define M_MDSEL 0x40 // IREF0 Output Mode Select.
#define BF_IREF0DAT 0 // IREF0 Data Word.
#define BF_IREF0DAT_0 0 // IREF0 Data Word.
#define BF_IREF0DAT_1 1 // IREF0 Data Word.
#define BF_IREF0DAT_2 2 // IREF0 Data Word.
#define BF_IREF0DAT_3 3 // IREF0 Data Word.
#define BF_IREF0DAT_4 4 // IREF0 Data Word.
#define BF_IREF0DAT_5 5 // IREF0 Data Word.
#define M_IREF0DAT 0x3F // IREF0 Data Word.
// SFR Definition 7.1. CPT0CN: Comparator 0 Control
#define B_CP0EN 7 // Comparator0 Enable Bit.
#define M_CP0EN 0x80 // Comparator0 Enable Bit.
#define B_CP0OUT 6 // Comparator0 Output State Flag.
#define M_CP0OUT 0x40 // Comparator0 Output State Flag.
#define B_CP0RIF 5 // Comparator0 Rising-Edge Flag. Must be cleared by software.
#define M_CP0RIF 0x20 // Comparator0 Rising-Edge Flag. Must be cleared by software.
#define B_CP0FIF 4 // Comparator0 Falling-Edge Flag. Must be cleared by software.
#define M_CP0FIF 0x10 // Comparator0 Falling-Edge Flag. Must be cleared by software.
// SFR Definition 7.2. CPT0MD: Comparator 0 Mode Selection
#define B_CP0RIE 5 // Comparator0 Rising-Edge Interrupt Enable.
#define M_CP0RIE 0x20 // Comparator0 Rising-Edge Interrupt Enable.
#define B_CP0FIE 4 // Comparator0 Falling-Edge Interrupt Enable.
#define M_CP0FIE 0x10 // Comparator0 Falling-Edge Interrupt Enable.
#define BF_CP0MD 0 // Comparator0 Mode Select
#define BF_CP0MD_0 0 // Comparator0 Mode Select
#define BF_CP0MD_1 1 // Comparator0 Mode Select
#define M_CP0MD 0x03 // Comparator0 Mode Select
// SFR Definition 7.3. CPT1CN: Comparator 1 Control
#define B_CP1EN 7 // Comparator1 Enable Bit.
#define M_CP1EN 0x80 // Comparator1 Enable Bit.
#define B_CP1OUT 6 // Comparator1 Output State Flag.
#define M_CP1OUT 0x40 // Comparator1 Output State Flag.
#define B_CP1RIF 5 // Comparator1 Rising-Edge Flag. Must be cleared by software.
#define M_CP1RIF 0x20 // Comparator1 Rising-Edge Flag. Must be cleared by software.
#define B_CP1FIF 4 // Comparator1 Falling-Edge Flag. Must be cleared by software.
#define M_CP1FIF 0x10 // Comparator1 Falling-Edge Flag. Must be cleared by software.
#define BF_CP1HYP 2 // Comparator1 Positive Hysteresis Control Bits.
#define BF_CP1HYP_0 2 // Comparator1 Positive Hysteresis Control Bits.
#define BF_CP1HYP_1 3 // Comparator1 Positive Hysteresis Control Bits.
#define M_CP1HYP 0x0C // Comparator1 Positive Hysteresis Control Bits.
#define BF_CP1HYN 0 // Comparator1 Negative Hysteresis Control Bits.
#define BF_CP1HYN_0 0 // Comparator1 Negative Hysteresis Control Bits.
#define BF_CP1HYN_1 1 // Comparator1 Negative Hysteresis Control Bits.
#define M_CP1HYN 0x03 // Comparator1 Negative Hysteresis Control Bits.
// SFR Definition 7.4. CPT1MD: Comparator 1 Mode Selection
#define B_CP1RIE 5 // Comparator1 Rising-Edge Interrupt Enable.
#define M_CP1RIE 0x20 // Comparator1 Rising-Edge Interrupt Enable.
#define B_CP1FIE 4 // Comparator1 Falling-Edge Interrupt Enable.
#define M_CP1FIE 0x10 // Comparator1 Falling-Edge Interrupt Enable.
#define BF_CP1MD 0 // Comparator1 Mode Select
#define BF_CP1MD_0 0 // Comparator1 Mode Select
#define BF_CP1MD_1 1 // Comparator1 Mode Select
#define M_CP1MD 0x03 // Comparator1 Mode Select
// SFR Definition 7.5. CPT0MX: Comparator0 Input Channel Select
#define BF_CMX0N 4 // Comparator0 Negative Input Selection.
#define BF_CMX0N_0 4 // Comparator0 Negative Input Selection.
#define BF_CMX0N_1 5 // Comparator0 Negative Input Selection.
#define BF_CMX0N_2 6 // Comparator0 Negative Input Selection.
#define BF_CMX0N_3 7 // Comparator0 Negative Input Selection.
#define M_CMX0N 0xF0 // Comparator0 Negative Input Selection.
#define BF_CMX0P 0 // Comparator0 Positive Input Selection.
#define BF_CMX0P_0 0 // Comparator0 Positive Input Selection.
#define BF_CMX0P_1 1 // Comparator0 Positive Input Selection.
#define BF_CMX0P_2 2 // Comparator0 Positive Input Selection.
#define BF_CMX0P_3 3 // Comparator0 Positive Input Selection.
#define M_CMX0P 0x0F // Comparator0 Positive Input Selection.
// SFR Definition 7.6. CPT1MX: Comparator1 Input Channel Select
#define BF_CMX1N 4 // Comparator1 Negative Input Selection.
#define BF_CMX1N_0 4 // Comparator1 Negative Input Selection.
#define BF_CMX1N_1 5 // Comparator1 Negative Input Selection.
#define BF_CMX1N_2 6 // Comparator1 Negative Input Selection.
#define BF_CMX1N_3 7 // Comparator1 Negative Input Selection.
#define M_CMX1N 0xF0 // Comparator1 Negative Input Selection.
#define BF_CMX1P 0 // Comparator1 Positive Input Selection.
#define BF_CMX1P_0 0 // Comparator1 Positive Input Selection.
#define BF_CMX1P_1 1 // Comparator1 Positive Input Selection.
#define BF_CMX1P_2 2 // Comparator1 Positive Input Selection.
#define BF_CMX1P_3 3 // Comparator1 Positive Input Selection.
#define M_CMX1P 0x0F // Comparator1 Positive Input Selection.
// SFR Definition 8.6. PSW: Program Status Word
#define B_CY 7 // Carry Flag.
#define M_CY 0x80 // Carry Flag.
#define B_AC 6 // Auxiliary Carry Flag.
#define M_AC 0x40 // Auxiliary Carry Flag.
#define B_F0 5 // User Flag 0.
#define M_F0 0x20 // User Flag 0.
#define BF_RS 3 // Register Bank Select.
#define BF_RS_0 3 // Register Bank Select.
#define BF_RS_1 4 // Register Bank Select.
#define M_RS 0x18 // Register Bank Select.
#define B_OV 2 // Overflow Flag.
#define M_OV 0x04 // Overflow Flag.
#define B_F1 1 // User Flag 1.
#define M_F1 0x02 // User Flag 1.
#define B_PARITY 0 // Parity Flag.
#define M_PARITY 0x01 // Parity Flag.
// SFR Definition 10.1. EMI0CN: External Memory Interface Control
#define BF_PGSEL 0 // XRAM Page Select.
#define BF_PGSEL_0 0 // XRAM Page Select.
#define BF_PGSEL_1 1 // XRAM Page Select.
#define BF_PGSEL_2 2 // XRAM Page Select.
#define BF_PGSEL_3 3 // XRAM Page Select.
#define BF_PGSEL_4 4 // XRAM Page Select.
#define M_PGSEL 0x1F // XRAM Page Select.
// SFR Definition 10.2. EMI0CF: External Me mory Configuration
#define BF_EMD 2 // EMIF Operating Mode Select.
#define BF_EMD_0 2 // EMIF Operating Mode Select.
#define BF_EMD_1 3 // EMIF Operating Mode Select.
#define M_EMD 0x0C // EMIF Operating Mode Select.
#define BF_EALE 0 // ALE Pulse Width Select Bits.
#define BF_EALE_0 0 // ALE Pulse Width Select Bits.
#define BF_EALE_1 1 // ALE Pulse Width Select Bits.
#define M_EALE 0x03 // ALE Pulse Width Select Bits.
// SFR Definition 10.3. EMI0TC: External Me mory Timing Control
#define BF_EAS 4 // Address Setup Time Select Bits.
#define BF_EAS_0 4 // Address Setup Time Select Bits.
#define BF_EAS_1 5 // Address Setup Time Select Bits.
#define BF_EAS_2 6 // Address Setup Time Select Bits.
#define BF_EAS_3 7 // Address Setup Time Select Bits.
#define M_EAS 0xF0 // Address Setup Time Select Bits.
#define BF_EWR 2 // RD and WR Pulse Width Select.
#define BF_EWR_0 2 // RD and WR Pulse Width Select.
#define BF_EWR_1 3 // RD and WR Pulse Width Select.
#define M_EWR 0x0C // RD and WR Pulse Width Select.
#define BF_EAH 0 // Address Hold Time Select Bits.
#define BF_EAH_0 0 // Address Hold Time Select Bits.
#define BF_EAH_1 1 // Address Hold Time Select Bits.
#define M_EAH 0x03 // Address Hold Time Select Bits.
// SFR Definition 12.1. IE: Interrupt Enable
#define B_EA 7 // Enable All Interrupts.
#define M_EA 0x80 // Enable All Interrupts.
#define B_ESPI0 6 // Enable Serial Peripheral Interface (SPI0) Interrupt.
#define M_ESPI0 0x40 // Enable Serial Peripheral Interface (SPI0) Interrupt.
#define B_ET2 5 // Enable Timer 2 Interrupt.
#define M_ET2 0x20 // Enable Timer 2 Interrupt.
#define B_ES0 4 // Enable UART0 Interrupt.
#define M_ES0 0x10 // Enable UART0 Interrupt.
#define B_ET1 3 // Enable Timer 1 Interrupt.
#define M_ET1 0x08 // Enable Timer 1 Interrupt.
#define B_EX1 2 // Enable External Interrupt 1.
#define M_EX1 0x04 // Enable External Interrupt 1.
#define B_ET0 1 // Enable Timer 0 Interrupt.
#define M_ET0 0x02 // Enable Timer 0 Interrupt.
#define B_EX0 0 // Enable External Interrupt 0.
#define M_EX0 0x01 // Enable External Interrupt 0.
// SFR Definition 12.2. IP: Interrupt Priority
#define B_PSPI0 6 // Serial Peripheral Interface (SPI0) Interrupt Priority Control.
#define M_PSPI0 0x40 // Serial Peripheral Interface (SPI0) Interrupt Priority Control.
#define B_PT2 5 // Timer 2 Interrupt Priority Control.
#define M_PT2 0x20 // Timer 2 Interrupt Priority Control.
#define B_PS0 4 // UART0 Interrupt Priority Control.
#define M_PS0 0x10 // UART0 Interrupt Priority Control.
#define B_PT1 3 // Timer 1 Interrupt Priority Control.
#define M_PT1 0x08 // Timer 1 Interrupt Priority Control.
#define B_PX1 2 // External Interrupt 1 Priority Control.
#define M_PX1 0x04 // External Interrupt 1 Priority Control.
#define B_PT0 1 // Timer 0 Interrupt Priority Control.
#define M_PT0 0x02 // Timer 0 Interrupt Priority Control.
#define B_PX0 0 // External Interrupt 0 Priority Control.
#define M_PX0 0x01 // External Interrupt 0 Priority Control.
// SFR Definition 12.3. EIE1: Extended Interrupt Enable 1
#define B_ET3 7 // Enable Timer 3 Interrupt.
#define M_ET3 0x80 // Enable Timer 3 Interrupt.
#define B_ECP1 6 // Enable Comparator1 (CP1) Interrupt.
#define M_ECP1 0x40 // Enable Comparator1 (CP1) Interrupt.
#define B_ECP0 5 // Enable Comparator0 (CP0) Interrupt.
#define M_ECP0 0x20 // Enable Comparator0 (CP0) Interrupt.
#define B_EPCA0 4 // Enable Programmable Counter Array (PCA0) Interrupt.
#define M_EPCA0 0x10 // Enable Programmable Counter Array (PCA0) Interrupt.
#define B_EADC0 3 // Enable ADC0 Conversion Complete Interrupt.
#define M_EADC0 0x08 // Enable ADC0 Conversion Complete Interrupt.
#define B_EWADC0 2 // Enable Window Comparison ADC0 Interrupt.
#define M_EWADC0 0x04 // Enable Window Comparison ADC0 Interrupt.
#define B_ERTC0A 1 // Enable SmaRTClock Alarm Interrupts.
#define M_ERTC0A 0x02 // Enable SmaRTClock Alarm Interrupts.
#define B_ESMB0 0 // Enable SMBus (SMB0) Interrupt.
#define M_ESMB0 0x01 // Enable SMBus (SMB0) Interrupt.
// SFR Definition 12.4. EIP1: Extended Interrupt Priority 1
#define B_PT3 7 // Timer 3 Interrupt Priority Control.
#define M_PT3 0x80 // Timer 3 Interrupt Priority Control.
#define B_PCP1 6 // Comparator1 (CP1) Interrupt Priority Control.
#define M_PCP1 0x40 // Comparator1 (CP1) Interrupt Priority Control.
#define B_PCP0 5 // Comparator0 (CP0) Interrupt Priority Control.
#define M_PCP0 0x20 // Comparator0 (CP0) Interrupt Priority Control.
#define B_PPCA0 4 // Programmable Counter Array (PCA0) Interrupt Priority Control.
#define M_PPCA0 0x10 // Programmable Counter Array (PCA0) Interrupt Priority Control.
#define B_PADC0 3 // ADC0 Conversion Complete Interrupt Priority Control.
#define M_PADC0 0x08 // ADC0 Conversion Complete Interrupt Priority Control.
#define B_PWADC0 2 // ADC0 Window Comparator Interrupt Priority Control.
#define M_PWADC0 0x04 // ADC0 Window Comparator Interrupt Priority Control.
#define B_PRTC0A 1 // SmaRTClock Alarm Interrupt Priority Control.
#define M_PRTC0A 0x02 // SmaRTClock Alarm Interrupt Priority Control.
#define B_PSMB0 0 // SMBus (SMB0) Interrupt Priority Control.
#define M_PSMB0 0x01 // SMBus (SMB0) Interrupt Priority Control.
// SFR Definition 12.5. EIE2: Extended Interrupt Enable 2
#define B_ESPI1 3 // Enable Serial Peripheral Interface (SPI1) Interrupt.
#define M_ESPI1 0x08 // Enable Serial Peripheral Interface (SPI1) Interrupt.
#define B_ERTC0F 2 // Enable SmaRTClock Oscillator Fail Interrupt.
#define M_ERTC0F 0x04 // Enable SmaRTClock Oscillator Fail Interrupt.
#define B_EMAT 1 // Enable Port Match Interrupts.
#define M_EMAT 0x02 // Enable Port Match Interrupts.
#define B_EWARN 0 // Enable VDD/DC+ Supply Monitor Early Warning Interrupt.
#define M_EWARN 0x01 // Enable VDD/DC+ Supply Monitor Early Warning Interrupt.
// SFR Definition 12.6. EIP2: Extended Interrupt Priority 2
#define B_PSPI1 3 // Serial Peripheral Interface (SPI1) Interrupt Pr iority Control.
#define M_PSPI1 0x08 // Serial Peripheral Interface (SPI1) Interrupt Pr iority Control.
#define B_PRTC0F 2 // SmaRTClock Oscillator Fail Interrupt Priority Control.
#define M_PRTC0F 0x04 // SmaRTClock Oscillator Fail Interrupt Priority Control.
#define B_PMAT 1 // Port Match Interrupt Priority Control.
#define M_PMAT 0x02 // Port Match Interrupt Priority Control.
#define B_PWARN 0 // VDD/DC+ Supply Monitor Early Warning Interrupt Priority Control.
#define M_PWARN 0x01 // VDD/DC+ Supply Monitor Early Warning Interrupt Priority Control.
// SFR Definition 12.7. IT01CF: INT0/ INT1 Configuration
#define B_IN1PL 7 // INT1 Polarity.
#define M_IN1PL 0x80 // INT1 Polarity.
#define BF_IN1SL 4 // INT1 Port Pin Se lection Bits.
#define BF_IN1SL_0 4 // INT1 Port Pin Se lection Bits.
#define BF_IN1SL_1 5 // INT1 Port Pin Se lection Bits.
#define BF_IN1SL_2 6 // INT1 Port Pin Se lection Bits.
#define M_IN1SL 0x70 // INT1 Port Pin Se lection Bits.
#define B_IN0PL 3 // INT0 Polarity.
#define M_IN0PL 0x08 // INT0 Polarity.
#define BF_IN0SL 0 // INT0 Port Pin Se lection Bits.
#define BF_IN0SL_0 0 // INT0 Port Pin Se lection Bits.
#define BF_IN0SL_1 1 // INT0 Port Pin Se lection Bits.
#define BF_IN0SL_2 2 // INT0 Port Pin Se lection Bits.
#define M_IN0SL 0x07 // INT0 Port Pin Se lection Bits.
// SFR Definition 13.1. PSCTL: Program Store R/W Control
#define B_SFLE 2 // Scratchpad Flash Memory Access Enable.
#define M_SFLE 0x04 // Scratchpad Flash Memory Access Enable.
#define B_PSEE 1 // Program Store Erase Enable.
#define M_PSEE 0x02 // Program Store Erase Enable.
#define B_PSWE 0 // Program Store Write Enable.
#define M_PSWE 0x01 // Program Store Write Enable.
// SFR Definition 13.3. FLSCL: Flash Scale
#define B_BYPASS 6 // Flash Read Timing One-Shot Bypass.
#define M_BYPASS 0x40 // Flash Read Timing One-Shot Bypass.
// SFR Definition 14.1. PMU0CF: Power Management Unit Configuration
#define B_SLEEP 7 // Sleep Mode Select Writing 1 places the
#define M_SLEEP 0x80 // Sleep Mode Select Writing 1 places the
#define B_SUSPEND 6 // Suspend Mode Select Writing 1 places the
#define M_SUSPEND 0x40 // Suspend Mode Select Writing 1 places the
#define B_CLEAR 5 // Wake-up Flag Clear Writing 1 clears all wake-up flags.
#define M_CLEAR 0x20 // Wake-up Flag Clear Writing 1 clears all wake-up flags.
#define B_RSTWK 4 // Reset Pin Wake-up Flag N/A Set to 1 if a glitch has
#define M_RSTWK 0x10 // Reset Pin Wake-up Flag N/A Set to 1 if a glitch has
#define B_RTCFWK 3 // SmaRTClock Oscillator
#define M_RTCFWK 0x08 // SmaRTClock Oscillator
#define B_RTCAWK 2 // SmaRTClock Alarm
#define M_RTCAWK 0x04 // SmaRTClock Alarm
#define B_PMATWK 1 // Port Match Wake-up
#define M_PMATWK 0x02 // Port Match Wake-up
#define B_CPT0WK 0 // Comparator0 Wake-up
#define M_CPT0WK 0x01 // Comparator0 Wake-up
// SFR Definition 14.2. PCON: Power Manageme nt Control Register
#define BF_GF 2 // General Purpose Flags Sets the logic value. Returns the logic value.
#define BF_GF_0 2 // General Purpose Flags Sets the logic value. Returns the logic value.
#define BF_GF_1 3 // General Purpose Flags Sets the logic value. Returns the logic value.
#define BF_GF_2 4 // General Purpose Flags Sets the logic value. Returns the logic value.
#define BF_GF_3 5 // General Purpose Flags Sets the logic value. Returns the logic value.
#define BF_GF_4 6 // General Purpose Flags Sets the logic value. Returns the logic value.
#define BF_GF_5 7 // General Purpose Flags Sets the logic value. Returns the logic value.
#define M_GF 0xFC // General Purpose Flags Sets the logic value. Returns the logic value.
#define B_STOP 1 // Stop Mode Select Writing 1 places the
#define M_STOP 0x02 // Stop Mode Select Writing 1 places the
#define B_IDLE 0 // Idle Mode Select Writing 1 places the
#define M_IDLE 0x01 // Idle Mode Select Writing 1 places the
// SFR Definition 15.1. CRC0CN: CRC0 Control
#define B_CRC0SEL 4 // CRC0 Polynomial Select Bit.
#define M_CRC0SEL 0x10 // CRC0 Polynomial Select Bit.
#define B_CRC0INIT 3 // CRC0 Result Init ialization Bit.
#define M_CRC0INIT 0x08 // CRC0 Result Init ialization Bit.
#define B_CRC0VAL 2 // CRC0 Set Value Initialization Bit.
#define M_CRC0VAL 0x04 // CRC0 Set Value Initialization Bit.
#define BF_CRC0PNT 0 // CRC0 Result Pointer.
#define BF_CRC0PNT_0 0 // CRC0 Result Pointer.
#define BF_CRC0PNT_1 1 // CRC0 Result Pointer.
#define M_CRC0PNT 0x03 // CRC0 Result Pointer.
// SFR Definition 15.4. CRC0AUTO: CRC0 Automatic Control
#define B_AUTOEN 7 // Automatic CRC Calc ulation Enable.
#define M_AUTOEN 0x80 // Automatic CRC Calc ulation Enable.
#define B_CRCDONE 6 // CRCDONE Automatic CRC Calculation Complete.
#define M_CRCDONE 0x40 // CRCDONE Automatic CRC Calculation Complete.
#define BF_CRC0ST 0 // Automatic CRC Calculation Starting Flash Sector.
#define BF_CRC0ST_0 0 // Automatic CRC Calculation Starting Flash Sector.
#define BF_CRC0ST_1 1 // Automatic CRC Calculation Starting Flash Sector.
#define BF_CRC0ST_2 2 // Automatic CRC Calculation Starting Flash Sector.
#define BF_CRC0ST_3 3 // Automatic CRC Calculation Starting Flash Sector.
#define BF_CRC0ST_4 4 // Automatic CRC Calculation Starting Flash Sector.
#define BF_CRC0ST_5 5 // Automatic CRC Calculation Starting Flash Sector.
#define M_CRC0ST 0x3F // Automatic CRC Calculation Starting Flash Sector.
// SFR Definition 15.5. CRC0CNT: CRC0 Automatic Flash Sector Count
#define BF_CRC0CNT 0 // Automatic CRC Calculation Flash Sector Count.
#define BF_CRC0CNT_0 0 // Automatic CRC Calculation Flash Sector Count.
#define BF_CRC0CNT_1 1 // Automatic CRC Calculation Flash Sector Count.
#define BF_CRC0CNT_2 2 // Automatic CRC Calculation Flash Sector Count.
#define BF_CRC0CNT_3 3 // Automatic CRC Calculation Flash Sector Count.
#define BF_CRC0CNT_4 4 // Automatic CRC Calculation Flash Sector Count.
#define BF_CRC0CNT_5 5 // Automatic CRC Calculation Flash Sector Count.
#define M_CRC0CNT 0x3F // Automatic CRC Calculation Flash Sector Count.
// SFR Definition 16.1. DC0CN: DC-DC Converter Control
#define BF_MINPW 6 // DC- DC Converter Minimum Pulse Width.
#define BF_MINPW_0 6 // DC- DC Converter Minimum Pulse Width.
#define BF_MINPW_1 7 // DC- DC Converter Minimum Pulse Width.
#define M_MINPW 0xC0 // DC- DC Converter Minimum Pulse Width.
#define B_SWSEL 5 // DC-DC Converter Switch Select.
#define M_SWSEL 0x20 // DC-DC Converter Switch Select.
#define B_SYNC 3 // ADC0 Synchronization Enable.
#define M_SYNC 0x08 // ADC0 Synchronization Enable.
#define BF_VSEL 0 // DC- DC Converter Output Voltage Select.
#define BF_VSEL_0 0 // DC- DC Converter Output Voltage Select.
#define BF_VSEL_1 1 // DC- DC Converter Output Voltage Select.
#define BF_VSEL_2 2 // DC- DC Converter Output Voltage Select.
#define M_VSEL 0x07 // DC- DC Converter Output Voltage Select.
// SFR Definition 16.2. DC0CF: DC-DC Conver ter Configuration
#define BF_DC0CF_CLKDIV 5 // DC- DC Clock Divider.
#define BF_DC0CF_CLKDIV_0 5 // DC- DC Clock Divider.
#define BF_DC0CF_CLKDIV_1 6 // DC- DC Clock Divider.
#define M_DC0CF_CLKDIV 0x60 // DC- DC Clock Divider.
#define B_CLKINV 3 // DC- DC Converter Clock Invert.
#define M_CLKINV 0x08 // DC- DC Converter Clock Invert.
#define B_ILIMIT 2 // Peak Current Limit Threshold.
#define M_ILIMIT 0x04 // Peak Current Limit Threshold.
#define B_VDDSLP 1 // VDD-DC+ Sleep Mode Connection.
#define M_VDDSLP 0x02 // VDD-DC+ Sleep Mode Connection.
#define B_DC0CF_CLKSEL 0 // DC- DC Converter Clock Source Select.
#define M_DC0CF_CLKSEL 0x01 // DC- DC Converter Clock Source Select.
// SFR Definition 17.1. REG0CN: Voltage Regulator Control
#define B_OSCBIAS 4 // Precision Oscillator Bias.
#define M_OSCBIAS 0x10 // Precision Oscillator Bias.
// SFR Definition 18.1. VDM0CN: VDD/DC+ Supply Monitor Control
#define B_VDMEN 7 // VDD/DC+ Supply Monitor Enable.
#define M_VDMEN 0x80 // VDD/DC+ Supply Monitor Enable.
#define B_VDDSTAT 6 // VDD/DC+ Supply Status.
#define M_VDDSTAT 0x40 // VDD/DC+ Supply Status.
#define B_VDDOK 5 // VDD/DC+ Supply Status (Early Warning).
#define M_VDDOK 0x20 // VDD/DC+ Supply Status (Early Warning).
// SFR Definition 18.2. RSTSRC: Reset Source
#define B_RTC0RE 7 // SmaRTClock Reset Enable
#define M_RTC0RE 0x80 // SmaRTClock Reset Enable
#define B_FERROR 6 // Flash Error Reset Flag. N/A Set to 1 if Flash
#define M_FERROR 0x40 // Flash Error Reset Flag. N/A Set to 1 if Flash
#define B_C0RSEF 5 // Comparator0 Reset Enable
#define M_C0RSEF 0x20 // Comparator0 Reset Enable
#define B_SWRSF 4 // Software Reset Force and
#define M_SWRSF 0x10 // Software Reset Force and
#define B_WDTRSF 3 // Watchdog Timer Reset Flag. N/A Set to 1 if Watchdog Timer
#define M_WDTRSF 0x08 // Watchdog Timer Reset Flag. N/A Set to 1 if Watchdog Timer
#define B_MCDRSF 2 // Missing Clock Detector
#define M_MCDRSF 0x04 // Missing Clock Detector
#define B_PORSF 1 // Power-On / Power-Fail
#define M_PORSF 0x02 // Power-On / Power-Fail
#define B_PINRSF 0 // HW Pin Reset Flag. N/A Set to 1 if RST pin caused
#define M_PINRSF 0x01 // HW Pin Reset Flag. N/A Set to 1 if RST pin caused
// SFR Definition 19.1. CLKSEL: Clock Select
#define B_CLKRDY 7 // System Clock Divider Clock Ready Flag.
#define M_CLKRDY 0x80 // System Clock Divider Clock Ready Flag.
#define BF_CLKDIV 4 // System Clock Divider Bits.
#define BF_CLKDIV_0 4 // System Clock Divider Bits.
#define BF_CLKDIV_1 5 // System Clock Divider Bits.
#define BF_CLKDIV_2 6 // System Clock Divider Bits.
#define M_CLKDIV 0x70 // System Clock Divider Bits.
#define BF_CLKSEL 0 // System Clock Select.
#define BF_CLKSEL_0 0 // System Clock Select.
#define BF_CLKSEL_1 1 // System Clock Select.
#define BF_CLKSEL_2 2 // System Clock Select.
#define M_CLKSEL 0x07 // System Clock Select.
// SFR Definition 19.2. OSCICN: Internal Oscillator Control
#define B_IOSCEN 7 // Internal Oscill ator Enable.
#define M_IOSCEN 0x80 // Internal Oscill ator Enable.
#define B_IFRDY 6 // Internal Oscillator Frequency Ready Flag.
#define M_IFRDY 0x40 // Internal Oscillator Frequency Ready Flag.
// SFR Definition 19.3. OSCICL: Internal Oscillator Calibration
#define B_SSE 7 // Spread Spectrum Enable.
#define M_SSE 0x80 // Spread Spectrum Enable.
#define BF_OSCICL 0 // Internal Oscillator Calibration.
#define BF_OSCICL_0 0 // Internal Oscillator Calibration.
#define BF_OSCICL_1 1 // Internal Oscillator Calibration.
#define BF_OSCICL_2 2 // Internal Oscillator Calibration.
#define BF_OSCICL_3 3 // Internal Oscillator Calibration.
#define BF_OSCICL_4 4 // Internal Oscillator Calibration.
#define BF_OSCICL_5 5 // Internal Oscillator Calibration.
#define BF_OSCICL_6 6 // Internal Oscillator Calibration.
#define M_OSCICL 0x7F // Internal Oscillator Calibration.
// SFR Definition 19.4. OSCXCN: External Oscillator Control
#define B_XCLKVLD 7 // External Oscillator Valid Flag.
#define M_XCLKVLD 0x80 // External Oscillator Valid Flag.
#define BF_XOSCMD 4 // External Oscillator Mode Bits.
#define BF_XOSCMD_0 4 // External Oscillator Mode Bits.
#define BF_XOSCMD_1 5 // External Oscillator Mode Bits.
#define BF_XOSCMD_2 6 // External Oscillator Mode Bits.
#define M_XOSCMD 0x70 // External Oscillator Mode Bits.
#define BF_XFCN 0 // External Oscillator Frequency Control Bits.
#define BF_XFCN_0 0 // External Oscillator Frequency Control Bits.
#define BF_XFCN_1 1 // External Oscillator Frequency Control Bits.
#define BF_XFCN_2 2 // External Oscillator Frequency Control Bits.
#define M_XFCN 0x07 // External Oscillator Frequency Control Bits.
// SFR Definition 20.2. RTC0ADR: SmaRTClock Address
#define B_RTC0ADR_BUSY 7 // SmaRTClock Interface Busy Indicator.
#define M_RTC0ADR_BUSY 0x80 // SmaRTClock Interface Busy Indicator.
#define B_AUTORD 6 // SmaRTClock Interface Autoread Enable.
#define M_AUTORD 0x40 // SmaRTClock Interface Autoread Enable.
#define B_SHORT 4 // Short Strobe Enable.
#define M_SHORT 0x10 // Short Strobe Enable.
#define BF_ADDR 0 // SmaRTClock Indirect Register Address.
#define BF_ADDR_0 0 // SmaRTClock Indirect Register Address.
#define BF_ADDR_1 1 // SmaRTClock Indirect Register Address.
#define BF_ADDR_2 2 // SmaRTClock Indirect Register Address.
#define BF_ADDR_3 3 // SmaRTClock Indirect Register Address.
#define M_ADDR 0x0F // SmaRTClock Indirect Register Address.
// Internal Register Definition 20.4. RTC0CN: SmaRTClock Control
#define B_RTC0EN 7 // SmaRTClock Enable.
#define M_RTC0EN 0x80 // SmaRTClock Enable.
#define B_MCLKEN 6 // Missing SmaRTClock Detector Enable.
#define M_MCLKEN 0x40 // Missing SmaRTClock Detector Enable.
#define B_OSCFAIL 5 // SmaRTClock Oscillator Fail Event Flag.
#define M_OSCFAIL 0x20 // SmaRTClock Oscillator Fail Event Flag.
#define B_RTC0TR 4 // SmaRTClock Timer Run Control.
#define M_RTC0TR 0x10 // SmaRTClock Timer Run Control.
#define B_RTC0AEN 3 // SmaRTClock Alarm Enable.
#define M_RTC0AEN 0x08 // SmaRTClock Alarm Enable.
#define B_ALRM 2 // SmaRTClock Alarm Event
#define M_ALRM 0x04 // SmaRTClock Alarm Event
#define B_RTC0SET 1 // SmaRTClock Timer Set.
#define M_RTC0SET 0x02 // SmaRTClock Timer Set.
#define B_RTC0CAP 0 // SmaRTClock Timer Capture.
#define M_RTC0CAP 0x01 // SmaRTClock Timer Capture.
// Internal Register Definition 20.5. RTC0XCN: SmaRTClock Oscillator Control
#define B_AGCEN 7 // SmaRTClock Oscillator Automatic Gain Control (AGC) Enable.
#define M_AGCEN 0x80 // SmaRTClock Oscillator Automatic Gain Control (AGC) Enable.
#define B_BIASX2 5 // SmaRTClock Oscillator Bias Double Enable.
#define M_BIASX2 0x20 // SmaRTClock Oscillator Bias Double Enable.
#define B_CLKVLD 4 // SmaRTClock Oscillator Crystal Valid Indicator.
#define M_CLKVLD 0x10 // SmaRTClock Oscillator Crystal Valid Indicator.
// Internal Register Definition 20.6. RTC0XCF: SmaRTClock Oscillator Configuration
#define B_AUTOSTP 7 // Automatic Load Capacitance Stepping Enable.
#define M_AUTOSTP 0x80 // Automatic Load Capacitance Stepping Enable.
#define B_LOADRDY 6 // Load Capacitance Ready Indicator.
#define M_LOADRDY 0x40 // Load Capacitance Ready Indicator.
#define BF_LOADCAP 0 // Load Capacitance Programmed Value.
#define BF_LOADCAP_0 0 // Load Capacitance Programmed Value.
#define BF_LOADCAP_1 1 // Load Capacitance Programmed Value.
#define BF_LOADCAP_2 2 // Load Capacitance Programmed Value.
#define BF_LOADCAP_3 3 // Load Capacitance Programmed Value.
#define M_LOADCAP 0x0F // Load Capacitance Programmed Value.
// SFR Definition 21.1. XBR0: Port I/O Crossbar Register 0
#define B_CP1AE 7 // Comparator1 Asynchronous Output Enable.
#define M_CP1AE 0x80 // Comparator1 Asynchronous Output Enable.
#define B_CP1E 6 // Comparator1 Output Enable.
#define M_CP1E 0x40 // Comparator1 Output Enable.
#define B_CP0AE 5 // Comparator0 Asynchronous Output Enable.
#define M_CP0AE 0x20 // Comparator0 Asynchronous Output Enable.
#define B_CP0E 4 // Comparator0 Output Enable.
#define M_CP0E 0x10 // Comparator0 Output Enable.
#define B_SYSCKE 3 // SYSCLK Output Enable.
#define M_SYSCKE 0x08 // SYSCLK Output Enable.
#define B_SMB0E 2 // SMBus I/O Enable.
#define M_SMB0E 0x04 // SMBus I/O Enable.
#define B_SPI0E 1 // SPI0 I/O Enable
#define M_SPI0E 0x02 // SPI0 I/O Enable
#define B_URT0E 0 // UART0 Output Enable.
#define M_URT0E 0x01 // UART0 Output Enable.
// SFR Definition 21.2. XBR1: Port I/O Crossbar Register 1
#define B_SPI1E 6 // SPI1 I/O Enable.
#define M_SPI1E 0x40 // SPI1 I/O Enable.
#define B_T1E 5 // Timer1 Input Enable.
#define M_T1E 0x20 // Timer1 Input Enable.
#define B_T0E 4 // Timer0 Input Enable.
#define M_T0E 0x10 // Timer0 Input Enable.
#define B_ECIE 3 // PCA0 External Counter Input (ECI) Enable.
#define M_ECIE 0x08 // PCA0 External Counter Input (ECI) Enable.
#define BF_PCA0ME 0 // PCA0 Module I/O Enable.
#define BF_PCA0ME_0 0 // PCA0 Module I/O Enable.
#define BF_PCA0ME_1 1 // PCA0 Module I/O Enable.
#define BF_PCA0ME_2 2 // PCA0 Module I/O Enable.
#define M_PCA0ME 0x07 // PCA0 Module I/O Enable.
// SFR Definition 21.3. XBR2: Port I/O Crossbar Register 2
#define B_WEAKPUD 7 // Port I/O Weak Pullup Disable.
#define M_WEAKPUD 0x80 // Port I/O Weak Pullup Disable.
#define B_XBARE 6 // Crossbar Enable.
#define M_XBARE 0x40 // Crossbar Enable.
// SFR Definition 22.1. SMB0CF: SMBus Clock/Configuration
#define B_ENSMB 7 // SMBus Enable.
#define M_ENSMB 0x80 // SMBus Enable.
#define B_INH 6 // SMBus Slave Inhibit.
#define M_INH 0x40 // SMBus Slave Inhibit.
#define B_BUSY 5 // SMBus Busy Indicator.
#define M_BUSY 0x20 // SMBus Busy Indicator.
#define B_EXTHOLD 4 // SMBus Setup and Hold Time Extension Enable.
#define M_EXTHOLD 0x10 // SMBus Setup and Hold Time Extension Enable.
#define B_SMBTOE 3 // SMBus SCL Timeout Detection Enable.
#define M_SMBTOE 0x08 // SMBus SCL Timeout Detection Enable.
#define B_SMBFTE 2 // SMBus Free Timeout Detection Enable.
#define M_SMBFTE 0x04 // SMBus Free Timeout Detection Enable.
#define BF_SMBCS 0 // SMBus Clock Source Selection.
#define BF_SMBCS_0 0 // SMBus Clock Source Selection.
#define BF_SMBCS_1 1 // SMBus Clock Source Selection.
#define M_SMBCS 0x03 // SMBus Clock Source Selection.
// SFR Definition 22.2. SMB0CN: SMBus Control
#define B_MASTER 7 // SMBus Master/Slave
#define M_MASTER 0x80 // SMBus Master/Slave
#define B_TXMODE 6 // SMBus Transmit Mode
#define M_TXMODE 0x40 // SMBus Transmit Mode
#define B_STA 5 // SMBus Start Flag. 0: No Start or repeated
#define M_STA 0x20 // SMBus Start Flag. 0: No Start or repeated
#define B_STO 4 // SMBus Stop Flag. 0: No Stop condition
#define M_STO 0x10 // SMBus Stop Flag. 0: No Stop condition
#define B_ACKRQ 3 // SMBus Acknowledge
#define M_ACKRQ 0x08 // SMBus Acknowledge
#define B_ARBLOST 2 // SMBus Arbitration Lost
#define M_ARBLOST 0x04 // SMBus Arbitration Lost
#define B_ACK 1 // SMBus Acknowledge. 0: NACK received.
#define M_ACK 0x02 // SMBus Acknowledge. 0: NACK received.
#define B_SI 0 // SMBus Interrupt Flag.
#define M_SI 0x01 // SMBus Interrupt Flag.
// SFR Definition 22.3. SMB0ADR: SMBus Slave Address
#define BF_SLV 1 // SMBus Hardware Slave Address.
#define BF_SLV_0 1 // SMBus Hardware Slave Address.
#define BF_SLV_1 2 // SMBus Hardware Slave Address.
#define BF_SLV_2 3 // SMBus Hardware Slave Address.
#define BF_SLV_3 4 // SMBus Hardware Slave Address.
#define BF_SLV_4 5 // SMBus Hardware Slave Address.
#define BF_SLV_5 6 // SMBus Hardware Slave Address.
#define BF_SLV_6 7 // SMBus Hardware Slave Address.
#define M_SLV 0xFE // SMBus Hardware Slave Address.
#define B_GC 0 // General Call Address Enable.
#define M_GC 0x01 // General Call Address Enable.
// SFR Definition 22.4. SMB0ADM: SMBus Slave Address Mask
#define BF_SLVM 1 // SMBus Slave Address Mask.
#define BF_SLVM_0 1 // SMBus Slave Address Mask.
#define BF_SLVM_1 2 // SMBus Slave Address Mask.
#define BF_SLVM_2 3 // SMBus Slave Address Mask.
#define BF_SLVM_3 4 // SMBus Slave Address Mask.
#define BF_SLVM_4 5 // SMBus Slave Address Mask.
#define BF_SLVM_5 6 // SMBus Slave Address Mask.
#define BF_SLVM_6 7 // SMBus Slave Address Mask.
#define M_SLVM 0xFE // SMBus Slave Address Mask.
#define B_EHACK 0 // Hardware Acknowledge Enable.
#define M_EHACK 0x01 // Hardware Acknowledge Enable.
// SFR Definition 23.1. SCON0: Serial Port 0 Control
#define B_S0MODE 7 // Serial Port 0 Operation Mode.
#define M_S0MODE 0x80 // Serial Port 0 Operation Mode.
#define B_MCE0 5 // Multiprocessor Communication Enable.
#define M_MCE0 0x20 // Multiprocessor Communication Enable.
#define B_REN0 4 // Serial Port 0 Operation Mode.
#define M_REN0 0x10 // Serial Port 0 Operation Mode.
#define B_TB80 3 // Ninth Transmission Bit.
#define M_TB80 0x08 // Ninth Transmission Bit.
#define B_RB80 2 // Ninth Receive Bit.
#define M_RB80 0x04 // Ninth Receive Bit.
#define B_TI0 1 // Transmit Interrupt Flag.
#define M_TI0 0x02 // Transmit Interrupt Flag.
#define B_RI0 0 // Receive Interrupt Flag.
#define M_RI0 0x01 // Receive Interrupt Flag.
// SFR Definition 24.1. SPI0CFG: SPI Configuration
#define B_SPIBSY0 7 // SPI Busy.
#define M_SPIBSY0 0x80 // SPI Busy.
#define B_MSTEN0 6 // Master Mode Enable.
#define M_MSTEN0 0x40 // Master Mode Enable.
#define B_CKPHA0 5 // SPI Clock Phase.
#define M_CKPHA0 0x20 // SPI Clock Phase.
#define B_CKPOL0 4 // SPI Clock Polarity.
#define M_CKPOL0 0x10 // SPI Clock Polarity.
#define B_SLVSEL0 3 // Slave Selected Flag.
#define M_SLVSEL0 0x08 // Slave Selected Flag.
#define B_NSSIN0 2 // NSS Instantaneous Pin Input.
#define M_NSSIN0 0x04 // NSS Instantaneous Pin Input.
#define B_SRMT0 1 // Shift Register Empty (valid in slave mode only).
#define M_SRMT0 0x02 // Shift Register Empty (valid in slave mode only).
#define B_RXBMT0 0 // Receive Buffer Empty (valid in slave mode only).
#define M_RXBMT0 0x01 // Receive Buffer Empty (valid in slave mode only).
// SFR Definition 24.1. SPI1CFG: SPI Configuration
#define B_SPIBSY1 7 // SPI Busy.
#define M_SPIBSY1 0x80 // SPI Busy.
#define B_MSTEN1 6 // Master Mode Enable.
#define M_MSTEN1 0x40 // Master Mode Enable.
#define B_CKPHA1 5 // SPI Clock Phase.
#define M_CKPHA1 0x20 // SPI Clock Phase.
#define B_CKPOL1 4 // SPI Clock Polarity.
#define M_CKPOL1 0x10 // SPI Clock Polarity.
#define B_SLVSEL1 3 // Slave Selected Flag.
#define M_SLVSEL1 0x08 // Slave Selected Flag.
#define B_NSSIN1 2 // NSS Instantaneous Pin Input.
#define M_NSSIN1 0x04 // NSS Instantaneous Pin Input.
#define B_SRMT1 1 // Shift Register Empty (valid in slave mode only).
#define M_SRMT1 0x02 // Shift Register Empty (valid in slave mode only).
#define B_RXBMT1 0 // Receive Buffer Empty (valid in slave mode only).
#define M_RXBMT1 0x01 // Receive Buffer Empty (valid in slave mode only).
// SFR Definition 24.2. SPI0CN: SPI Control
#define B_SPIF0 7 // SPIn Interrupt Flag.
#define M_SPIF0 0x80 // SPIn Interrupt Flag.
#define B_WCOL0 6 // Write Collision Flag.
#define M_WCOL0 0x40 // Write Collision Flag.
#define B_MODF0 5 // Mode Fault Flag.
#define M_MODF0 0x20 // Mode Fault Flag.
#define B_RXOVRN0 4 // Receive Overrun Flag (valid in slave mode only).
#define M_RXOVRN0 0x10 // Receive Overrun Flag (valid in slave mode only).
#define BF_NSS0MD 2 // Slave Select Mode.
#define BF_NSS0MD_0 2 // Slave Select Mode.
#define BF_NSS0MD_1 3 // Slave Select Mode.
#define M_NSS0MD 0x0C // Slave Select Mode.
#define B_TXBMT0 1 // Transmit Buffer Empty.
#define M_TXBMT0 0x02 // Transmit Buffer Empty.
#define B_SPI0EN 0 // SPIn Enable.
#define M_SPI0EN 0x01 // SPIn Enable.
// SFR Definition 24.2. SPI1CN: SPI Control
#define B_SPIF1 7 // SPIn Interrupt Flag.
#define M_SPIF1 0x80 // SPIn Interrupt Flag.
#define B_WCOL1 6 // Write Collision Flag.
#define M_WCOL1 0x40 // Write Collision Flag.
#define B_MODF1 5 // Mode Fault Flag.
#define M_MODF1 0x20 // Mode Fault Flag.
#define B_RXOVRN1 4 // Receive Overrun Flag (valid in slave mode only).
#define M_RXOVRN1 0x10 // Receive Overrun Flag (valid in slave mode only).
#define BF_NSS1MD 2 // Slave Select Mode.
#define BF_NSS1MD_0 2 // Slave Select Mode.
#define BF_NSS1MD_1 3 // Slave Select Mode.
#define M_NSS1MD 0x0C // Slave Select Mode.
#define B_TXBMT1 1 // Transmit Buffer Empty.
#define M_TXBMT1 0x02 // Transmit Buffer Empty.
#define B_SPI1EN 0 // SPIn Enable.
#define M_SPI1EN 0x01 // SPIn Enable.
// SFR Definition 25.1. CKCON: Clock Control
#define B_T3MH 7 // Timer 3 High Byte Clock Select.
#define M_T3MH 0x80 // Timer 3 High Byte Clock Select.
#define B_T3ML 6 // Timer 3 Low Byte Clock Select.
#define M_T3ML 0x40 // Timer 3 Low Byte Clock Select.
#define B_T2MH 5 // Timer 2 High Byte Clock Select.
#define M_T2MH 0x20 // Timer 2 High Byte Clock Select.
#define B_T2ML 4 // Timer 2 Low Byte Clock Select.
#define M_T2ML 0x10 // Timer 2 Low Byte Clock Select.
#define B_T1M 3 // Timer 1 Clock Select.
#define M_T1M 0x08 // Timer 1 Clock Select.
#define B_T0M 2 // Timer 0 Clock Select.
#define M_T0M 0x04 // Timer 0 Clock Select.
#define BF_SCA 0 // Timer 0/1 Prescale Bits.
#define BF_SCA_0 0 // Timer 0/1 Prescale Bits.
#define BF_SCA_1 1 // Timer 0/1 Prescale Bits.
#define M_SCA 0x03 // Timer 0/1 Prescale Bits.
// SFR Definition 25.2. TCON: Timer Control
#define B_TF1 7 // Timer 1 Overflow Flag.
#define M_TF1 0x80 // Timer 1 Overflow Flag.
#define B_TR1 6 // Timer 1 Run Control.
#define M_TR1 0x40 // Timer 1 Run Control.
#define B_TF0 5 // Timer 0 Overflow Flag.
#define M_TF0 0x20 // Timer 0 Overflow Flag.
#define B_TR0 4 // Timer 0 Run Control.
#define M_TR0 0x10 // Timer 0 Run Control.
#define B_IE1 3 // External Interrupt 1.
#define M_IE1 0x08 // External Interrupt 1.
#define B_IT1 2 // Interrupt 1 Type Select.
#define M_IT1 0x04 // Interrupt 1 Type Select.
#define B_IE0 1 // External Interrupt 0.
#define M_IE0 0x02 // External Interrupt 0.
#define B_IT0 0 // Interrupt 0 Type Select.
#define M_IT0 0x01 // Interrupt 0 Type Select.
// SFR Definition 25.3. TMOD: Timer Mode
#define B_GATE1 7 // Timer 1 Gate Control.
#define M_GATE1 0x80 // Timer 1 Gate Control.
#define BF_TMOD_T1M 4 // Timer 1 Mode Select.
#define BF_TMOD_T1M_0 4 // Timer 1 Mode Select.
#define BF_TMOD_T1M_1 5 // Timer 1 Mode Select.
#define M_TMOD_T1M 0x30 // Timer 1 Mode Select.
#define B_GATE0 3 // Timer 0 Gate Control.
#define M_GATE0 0x08 // Timer 0 Gate Control.
#define BF_TMOD_T0M 0 // Timer 0 Mode Select.
#define BF_TMOD_T0M_0 0 // Timer 0 Mode Select.
#define BF_TMOD_T0M_1 1 // Timer 0 Mode Select.
#define M_TMOD_T0M 0x03 // Timer 0 Mode Select.
// SFR Definition 25.8. TMR2CN: Timer 2 Control
#define B_TF2H 7 // Timer 2 High Byte Overflow Flag.
#define M_TF2H 0x80 // Timer 2 High Byte Overflow Flag.
#define B_TF2L 6 // Timer 2 Low Byte Overflow Flag.
#define M_TF2L 0x40 // Timer 2 Low Byte Overflow Flag.
#define B_TF2LEN 5 // Timer 2 Low Byte Interrupt Enable.
#define M_TF2LEN 0x20 // Timer 2 Low Byte Interrupt Enable.
#define B_TF2CEN 4 // Timer 2 Capture Enable.
#define M_TF2CEN 0x10 // Timer 2 Capture Enable.
#define B_T2SPLIT 3 // Timer 2 Split Mode Enable.
#define M_T2SPLIT 0x08 // Timer 2 Split Mode Enable.
#define B_TR2 2 // Timer 2 Run Control.
#define M_TR2 0x04 // Timer 2 Run Control.
#define BF_T2XCLK 0 // Timer 2 External Clock Select.
#define BF_T2XCLK_0 0 // Timer 2 External Clock Select.
#define BF_T2XCLK_1 1 // Timer 2 External Clock Select.
#define M_T2XCLK 0x03 // Timer 2 External Clock Select.
// SFR Definition 25.13. TMR3CN: Timer 3 Control
#define B_TF3H 7 // Timer 3 High Byte Overflow Flag.
#define M_TF3H 0x80 // Timer 3 High Byte Overflow Flag.
#define B_TF3L 6 // Timer 3 Low Byte Overflow Flag.
#define M_TF3L 0x40 // Timer 3 Low Byte Overflow Flag.
#define B_TF3LEN 5 // Timer 3 Low Byte Interrupt Enable.
#define M_TF3LEN 0x20 // Timer 3 Low Byte Interrupt Enable.
#define B_TF3CEN 4 // Timer 3 Comparator 1/External Oscillator Capture Enable.
#define M_TF3CEN 0x10 // Timer 3 Comparator 1/External Oscillator Capture Enable.
#define B_T3SPLIT 3 // Timer 3 Split Mode Enable.
#define M_T3SPLIT 0x08 // Timer 3 Split Mode Enable.
#define B_TR3 2 // Timer 3 Run Control.
#define M_TR3 0x04 // Timer 3 Run Control.
#define BF_T3XCLK 0 // Timer 3 External Clock Select.
#define BF_T3XCLK_0 0 // Timer 3 External Clock Select.
#define BF_T3XCLK_1 1 // Timer 3 External Clock Select.
#define M_T3XCLK 0x03 // Timer 3 External Clock Select.
// SFR Definition 26.1. PCA0CN: PCA Control
#define B_CF 7 // PCA Counter/Timer Overflow Flag.
#define M_CF 0x80 // PCA Counter/Timer Overflow Flag.
#define B_CR 6 // PCA Counter/Timer Run Control.
#define M_CR 0x40 // PCA Counter/Timer Run Control.
#define BF_CCF 0 // PCA Module n Capture/Compare Flag.
#define BF_CCF_0 0 // PCA Module n Capture/Compare Flag.
#define BF_CCF_1 1 // PCA Module n Capture/Compare Flag.
#define BF_CCF_2 2 // PCA Module n Capture/Compare Flag.
#define BF_CCF_3 3 // PCA Module n Capture/Compare Flag.
#define BF_CCF_4 4 // PCA Module n Capture/Compare Flag.
#define BF_CCF_5 5 // PCA Module n Capture/Compare Flag.
#define M_CCF 0x3F // PCA Module n Capture/Compare Flag.
// SFR Definition 26.2. PCA0MD: PCA Mode
#define B_CIDL 7 // PCA Counter/Timer Idle Control.
#define M_CIDL 0x80 // PCA Counter/Timer Idle Control.
#define B_WDTE 6 // Watchdog Timer Enable.
#define M_WDTE 0x40 // Watchdog Timer Enable.
#define B_WDLCK 5 // Watchdog Timer Lock.
#define M_WDLCK 0x20 // Watchdog Timer Lock.
#define BF_CPS 1 // PCA Counter/Timer Pulse Select.
#define BF_CPS_0 1 // PCA Counter/Timer Pulse Select.
#define BF_CPS_1 2 // PCA Counter/Timer Pulse Select.
#define BF_CPS_2 3 // PCA Counter/Timer Pulse Select.
#define M_CPS 0x0E // PCA Counter/Timer Pulse Select.
#define B_ECF 0 // PCA Counter/Timer Overflow Interrupt Enable.
#define M_ECF 0x01 // PCA Counter/Timer Overflow Interrupt Enable.
// SFR Definition 26.3. PCA0PWM: PCA PWM Configuration
#define B_ARSEL 7 // Auto-Reload Register Select.
#define M_ARSEL 0x80 // Auto-Reload Register Select.
#define B_ECOV 6 // Cycle Overflow Interrupt Enable.
#define M_ECOV 0x40 // Cycle Overflow Interrupt Enable.
#define B_COVF 5 // Cycle Overflow Flag.
#define M_COVF 0x20 // Cycle Overflow Flag.
#define BF_CLSEL 0 // Cycle Length Select.
#define BF_CLSEL_0 0 // Cycle Length Select.
#define BF_CLSEL_1 1 // Cycle Length Select.
#define M_CLSEL 0x03 // Cycle Length Select.
// SFR Definition 26.4. PCA0CPM0: PCA Capture/Compare Mode
#define B_ECOM0 6 // Comparator Function Enable.
#define M_ECOM0 0x40 // Comparator Function Enable.
#define B_CAPP0 5 // Capture Positive Function Enable.
#define M_CAPP0 0x20 // Capture Positive Function Enable.
#define B_CAPN0 4 // Capture Negative Function Enable.
#define M_CAPN0 0x10 // Capture Negative Function Enable.
#define B_MAT0 3 // Match Function Enable.
#define M_MAT0 0x08 // Match Function Enable.
#define B_TOG0 2 // Toggle Function Enable.
#define M_TOG0 0x04 // Toggle Function Enable.
#define B_PWM0 1 // Pulse Width Modulation Mode Enable.
#define M_PWM0 0x02 // Pulse Width Modulation Mode Enable.
#define B_ECCF0 0 // Capture/Compare Flag Interrupt Enable.
#define M_ECCF0 0x01 // Capture/Compare Flag Interrupt Enable.
// SFR Definition 26.4. PCA0CPM1: PCA Capture/Compare Mode
#define B_PWM161 7 // 16-bit Pulse Width Modulation Enable.
#define M_PWM161 0x80 // 16-bit Pulse Width Modulation Enable.
#define B_ECOM1 6 // Comparator Function Enable.
#define M_ECOM1 0x40 // Comparator Function Enable.
#define B_CAPP1 5 // Capture Positive Function Enable.
#define M_CAPP1 0x20 // Capture Positive Function Enable.
#define B_CAPN1 4 // Capture Negative Function Enable.
#define M_CAPN1 0x10 // Capture Negative Function Enable.
#define B_MAT1 3 // Match Function Enable.
#define M_MAT1 0x08 // Match Function Enable.
#define B_TOG1 2 // Toggle Function Enable.
#define M_TOG1 0x04 // Toggle Function Enable.
#define B_PWM1 1 // Pulse Width Modulation Mode Enable.
#define M_PWM1 0x02 // Pulse Width Modulation Mode Enable.
#define B_ECCF1 0 // Capture/Compare Flag Interrupt Enable.
#define M_ECCF1 0x01 // Capture/Compare Flag Interrupt Enable.
// SFR Definition 26.4. PCA0CPM2: PCA Capture/Compare Mode
#define B_PWM162 7 // 16-bit Pulse Width Modulation Enable.
#define M_PWM162 0x80 // 16-bit Pulse Width Modulation Enable.
#define B_ECOM2 6 // Comparator Function Enable.
#define M_ECOM2 0x40 // Comparator Function Enable.
#define B_CAPP2 5 // Capture Positive Function Enable.
#define M_CAPP2 0x20 // Capture Positive Function Enable.
#define B_CAPN2 4 // Capture Negative Function Enable.
#define M_CAPN2 0x10 // Capture Negative Function Enable.
#define B_MAT2 3 // Match Function Enable.
#define M_MAT2 0x08 // Match Function Enable.
#define B_TOG2 2 // Toggle Function Enable.
#define M_TOG2 0x04 // Toggle Function Enable.
#define B_PWM2 1 // Pulse Width Modulation Mode Enable.
#define M_PWM2 0x02 // Pulse Width Modulation Mode Enable.
#define B_ECCF2 0 // Capture/Compare Flag Interrupt Enable.
#define M_ECCF2 0x01 // Capture/Compare Flag Interrupt Enable.
// SFR Definition 26.4. PCA0CPM3: PCA Capture/Compare Mode
#define B_PWM163 7 // 16-bit Pulse Width Modulation Enable.
#define M_PWM163 0x80 // 16-bit Pulse Width Modulation Enable.
#define B_ECOM3 6 // Comparator Function Enable.
#define M_ECOM3 0x40 // Comparator Function Enable.
#define B_CAPP3 5 // Capture Positive Function Enable.
#define M_CAPP3 0x20 // Capture Positive Function Enable.
#define B_CAPN3 4 // Capture Negative Function Enable.
#define M_CAPN3 0x10 // Capture Negative Function Enable.
#define B_MAT3 3 // Match Function Enable.
#define M_MAT3 0x08 // Match Function Enable.
#define B_TOG3 2 // Toggle Function Enable.
#define M_TOG3 0x04 // Toggle Function Enable.
#define B_PWM3 1 // Pulse Width Modulation Mode Enable.
#define M_PWM3 0x02 // Pulse Width Modulation Mode Enable.
#define B_ECCF3 0 // Capture/Compare Flag Interrupt Enable.
#define M_ECCF3 0x01 // Capture/Compare Flag Interrupt Enable.
// SFR Definition 26.4. PCA0CPM4: PCA Capture/Compare Mode
#define B_PWM164 7 // 16-bit Pulse Width Modulation Enable.
#define M_PWM164 0x80 // 16-bit Pulse Width Modulation Enable.
#define B_ECOM4 6 // Comparator Function Enable.
#define M_ECOM4 0x40 // Comparator Function Enable.
#define B_CAPP4 5 // Capture Positive Function Enable.
#define M_CAPP4 0x20 // Capture Positive Function Enable.
#define B_CAPN4 4 // Capture Negative Function Enable.
#define M_CAPN4 0x10 // Capture Negative Function Enable.
#define B_MAT4 3 // Match Function Enable.
#define M_MAT4 0x08 // Match Function Enable.
#define B_TOG4 2 // Toggle Function Enable.
#define M_TOG4 0x04 // Toggle Function Enable.
#define B_PWM4 1 // Pulse Width Modulation Mode Enable.
#define M_PWM4 0x02 // Pulse Width Modulation Mode Enable.
#define B_ECCF4 0 // Capture/Compare Flag Interrupt Enable.
#define M_ECCF4 0x01 // Capture/Compare Flag Interrupt Enable.
// SFR Definition 26.4. PCA0CPM5: PCA Capture/Compare Mode
#define B_PWM165 7 // 16-bit Pulse Width Modulation Enable.
#define M_PWM165 0x80 // 16-bit Pulse Width Modulation Enable.
#define B_ECOM5 6 // Comparator Function Enable.
#define M_ECOM5 0x40 // Comparator Function Enable.
#define B_CAPP5 5 // Capture Positive Function Enable.
#define M_CAPP5 0x20 // Capture Positive Function Enable.
#define B_CAPN5 4 // Capture Negative Function Enable.
#define M_CAPN5 0x10 // Capture Negative Function Enable.
#define B_MAT5 3 // Match Function Enable.
#define M_MAT5 0x08 // Match Function Enable.
#define B_TOG5 2 // Toggle Function Enable.
#define M_TOG5 0x04 // Toggle Function Enable.
#define B_PWM5 1 // Pulse Width Modulation Mode Enable.
#define M_PWM5 0x02 // Pulse Width Modulation Mode Enable.
#define B_ECCF5 0 // Capture/Compare Flag Interrupt Enable.
#define M_ECCF5 0x01 // Capture/Compare Flag Interrupt Enable.
#endif /* C8051F930_DEFS_ADD_H_ */
spino_code/silabs_code/Si446x_CustomPacketTX/src/drivers/STARTUP.A51 0 → 100644
View file @ 083b3926
$NOMOD51
;------------------------------------------------------------------------------
; This file is part of the C51 Compiler package
; Copyright (c) 1988-2005 Keil Elektronik GmbH and Keil Software, Inc.
; Version 8.01
;
; *** <<< Use Configuration Wizard in Context Menu >>> ***
;------------------------------------------------------------------------------
; STARTUP.A51: This code is executed after processor reset.
;
; To translate this file use A51 with the following invocation:
;
; A51 STARTUP.A51
;
; To link the modified STARTUP.OBJ file to your application use the following
; Lx51 invocation:
;
; Lx51 your object file list, STARTUP.OBJ controls
;
;------------------------------------------------------------------------------
;
; User-defined <h> Power-On Initialization of Memory
;
; With the following EQU statements the initialization of memory
; at processor reset can be defined:
;
; <o> IDATALEN: IDATA memory size <0x0-0x100>
; <i> Note: The absolute start-address of IDATA memory is always 0
; <i> The IDATA space overlaps physically the DATA and BIT areas.
IDATALEN EQU 80H
;
; <o> XDATASTART: XDATA memory start address <0x0-0xFFFF>
; <i> The absolute start address of XDATA memory
XDATASTART EQU 0
;
; <o> XDATALEN: XDATA memory size <0x0-0xFFFF>
; <i> The length of XDATA memory in bytes.
XDATALEN EQU 0FFFH
;
; <o> PDATASTART: PDATA memory start address <0x0-0xFFFF>
; <i> The absolute start address of PDATA memory
PDATASTART EQU 0H
;
; <o> PDATALEN: PDATA memory size <0x0-0xFF>
; <i> The length of PDATA memory in bytes.
PDATALEN EQU 0H
;
;</h>
;------------------------------------------------------------------------------
;
;<h> Reentrant Stack Initialization
;
; The following EQU statements define the stack pointer for reentrant
; functions and initialized it:
;
; <h> Stack Space for reentrant functions in the SMALL model.
; <q> IBPSTACK: Enable SMALL model reentrant stack
; <i> Stack space for reentrant functions in the SMALL model.
IBPSTACK EQU 0 ; set to 1 if small reentrant is used.
; <o> IBPSTACKTOP: End address of SMALL model stack <0x0-0xFF>
; <i> Set the top of the stack to the highest location.
IBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1
; </h>
;
; <h> Stack Space for reentrant functions in the LARGE model.
; <q> XBPSTACK: Enable LARGE model reentrant stack
; <i> Stack space for reentrant functions in the LARGE model.
XBPSTACK EQU 0 ; set to 1 if large reentrant is used.
; <o> XBPSTACKTOP: End address of LARGE model stack <0x0-0xFFFF>
; <i> Set the top of the stack to the highest location.
XBPSTACKTOP EQU 0xFFFF +1 ; default 0FFFFH+1
; </h>
;
; <h> Stack Space for reentrant functions in the COMPACT model.
; <q> PBPSTACK: Enable COMPACT model reentrant stack
; <i> Stack space for reentrant functions in the COMPACT model.
PBPSTACK EQU 0 ; set to 1 if compact reentrant is used.
;
; <o> PBPSTACKTOP: End address of COMPACT model stack <0x0-0xFFFF>
; <i> Set the top of the stack to the highest location.
PBPSTACKTOP EQU 0xFF +1 ; default 0FFH+1
; </h>
;</h>
;------------------------------------------------------------------------------
;
; Memory Page for Using the Compact Model with 64 KByte xdata RAM
; <e>Compact Model Page Definition
;
; <i>Define the XDATA page used for PDATA variables.
; <i>PPAGE must conform with the PPAGE set in the linker invocation.
;
; Enable pdata memory page initalization
PPAGEENABLE EQU 0 ; set to 1 if pdata object are used.
;
; <o> PPAGE number <0x0-0xFF>
; <i> uppermost 256-byte address of the page used for PDATA variables.
PPAGE EQU 0
;
; <o> SFR address which supplies uppermost address byte <0x0-0xFF>
; <i> most 8051 variants use P2 as uppermost address byte
PPAGE_SFR DATA 0A0H
;
; </e>
;------------------------------------------------------------------------------
; Standard SFR Symbols
ACC DATA 0E0H
B DATA 0F0H
SP DATA 81H
DPL DATA 82H
DPH DATA 83H
PCA0MD DATA 0D9H
NAME ?C_STARTUP
?C_C51STARTUP SEGMENT CODE
?STACK SEGMENT IDATA
RSEG ?STACK
DS 1
EXTRN CODE (?C_START)
PUBLIC ?C_STARTUP
CSEG AT 0
?C_STARTUP: LJMP STARTUP1
RSEG ?C_C51STARTUP
STARTUP1:
;Disable the Watch Dog Timer
WDT_DISABLE: MOV PCA0MD, #0
IF IDATALEN <> 0
MOV R0,#IDATALEN - 1
CLR A
IDATALOOP: MOV @R0,A
DJNZ R0,IDATALOOP
ENDIF
IF XDATALEN <> 0
MOV DPTR,#XDATASTART
MOV R7,#LOW (XDATALEN)
IF (LOW (XDATALEN)) <> 0
MOV R6,#(HIGH (XDATALEN)) +1
ELSE
MOV R6,#HIGH (XDATALEN)
ENDIF
CLR A
XDATALOOP: MOVX @DPTR,A
INC DPTR
DJNZ R7,XDATALOOP
DJNZ R6,XDATALOOP
ENDIF
IF PPAGEENABLE <> 0
MOV PPAGE_SFR,#PPAGE
ENDIF
IF PDATALEN <> 0
MOV R0,#LOW (PDATASTART)
MOV R7,#LOW (PDATALEN)
CLR A
PDATALOOP: MOVX @R0,A
INC R0
DJNZ R7,PDATALOOP
ENDIF
IF IBPSTACK <> 0
EXTRN DATA (?C_IBP)
MOV ?C_IBP,#LOW IBPSTACKTOP
ENDIF
IF XBPSTACK <> 0
EXTRN DATA (?C_XBP)
MOV ?C_XBP,#HIGH XBPSTACKTOP
MOV ?C_XBP+1,#LOW XBPSTACKTOP
ENDIF
IF PBPSTACK <> 0
EXTRN DATA (?C_PBP)
MOV ?C_PBP,#LOW PBPSTACKTOP
ENDIF
MOV SP,#?STACK-1
; This code is required if you use L51_BANK.A51 with Banking Mode 4
;<h> Code Banking
; <q> Select Bank 0 for L51_BANK.A51 Mode 4
#if 0
; <i> Initialize bank mechanism to code bank 0 when using L51_BANK.A51 with Banking Mode 4.
EXTRN CODE (?B_SWITCH0)
CALL ?B_SWITCH0 ; init bank mechanism to code bank 0
#endif
;</h>
LJMP ?C_START
END
spino_code/silabs_code/Si446x_CustomPacketTX/src/drivers/ascii5x7.c 0 → 100644
View file @ 083b3926
/*! @file ascii5x7.c
* @brief ASCII character table for 5x7 pixels of characters.
*
* @b COPYRIGHT
* @n Silicon Laboratories Confidential
* @n Copyright 2012 Silicon Laboratories, Inc.
* @n http://www.silabs.com
*/
#include "..\bsp.h"
/*! ASCII character table for the LCD */
const SEGMENT_VARIABLE(ascii_table5x7[][5u], U8, SEG_CODE) =
{
{0x00, 0x00, 0x00, 0x00, 0x00},// (space)
{0x00, 0x00, 0x5F, 0x00, 0x00},// !
{0x00, 0x07, 0x00, 0x07, 0x00},// "
{0x14, 0x7F, 0x14, 0x7F, 0x14},// #
{0x24, 0x2A, 0x7F, 0x2A, 0x12},// $
{0x23, 0x13, 0x08, 0x64, 0x62},// %
{0x36, 0x49, 0x55, 0x22, 0x50},// &
{0x00, 0x05, 0x03, 0x00, 0x00},// '
{0x00, 0x1C, 0x22, 0x41, 0x00},// (
{0x00, 0x41, 0x22, 0x1C, 0x00},// )
{0x08, 0x2A, 0x1C, 0x2A, 0x08},// *
{0x08, 0x08, 0x3E, 0x08, 0x08},// +
{0x00, 0x50, 0x30, 0x00, 0x00},// ,
{0x08, 0x08, 0x08, 0x08, 0x08},// -
{0x00, 0x60, 0x60, 0x00, 0x00},// .
{0x20, 0x10, 0x08, 0x04, 0x02},// /
{0x3E, 0x51, 0x49, 0x45, 0x3E},// 0
{0x00, 0x42, 0x7F, 0x40, 0x00},// 1
{0x42, 0x61, 0x51, 0x49, 0x46},// 2
{0x21, 0x41, 0x45, 0x4B, 0x31},// 3
{0x18, 0x14, 0x12, 0x7F, 0x10},// 4
{0x27, 0x45, 0x45, 0x45, 0x39},// 5
{0x3C, 0x4A, 0x49, 0x49, 0x30},// 6
{0x01, 0x71, 0x09, 0x05, 0x03},// 7
{0x36, 0x49, 0x49, 0x49, 0x36},// 8
{0x06, 0x49, 0x49, 0x29, 0x1E},// 9
{0x00, 0x36, 0x36, 0x00, 0x00},// :
{0x00, 0x56, 0x36, 0x00, 0x00},// ;
{0x00, 0x08, 0x14, 0x22, 0x41},// <
{0x14, 0x14, 0x14, 0x14, 0x14},// =
{0x41, 0x22, 0x14, 0x08, 0x00},// >
{0x02, 0x01, 0x51, 0x09, 0x06},// ?
{0x32, 0x49, 0x79, 0x41, 0x3E},// @
{0x7E, 0x11, 0x11, 0x11, 0x7E},// A
{0x7F, 0x49, 0x49, 0x49, 0x36},// B
{0x3E, 0x41, 0x41, 0x41, 0x22},// C
{0x7F, 0x41, 0x41, 0x22, 0x1C},// D
{0x7F, 0x49, 0x49, 0x49, 0x41},// E
{0x7F, 0x09, 0x09, 0x01, 0x01},// F
{0x3E, 0x41, 0x41, 0x51, 0x32},// G
{0x7F, 0x08, 0x08, 0x08, 0x7F},// H
{0x00, 0x41, 0x7F, 0x41, 0x00},// I
{0x20, 0x40, 0x41, 0x3F, 0x01},// J
{0x7F, 0x08, 0x14, 0x22, 0x41},// K
{0x7F, 0x40, 0x40, 0x40, 0x40},// L
{0x7F, 0x02, 0x04, 0x02, 0x7F},// M
{0x7F, 0x04, 0x08, 0x10, 0x7F},// N
{0x3E, 0x41, 0x41, 0x41, 0x3E},// O
{0x7F, 0x09, 0x09, 0x09, 0x06},// P
{0x3E, 0x41, 0x51, 0x21, 0x5E},// Q
{0x7F, 0x09, 0x19, 0x29, 0x46},// R
{0x46, 0x49, 0x49, 0x49, 0x31},// S
{0x01, 0x01, 0x7F, 0x01, 0x01},// T
{0x3F, 0x40, 0x40, 0x40, 0x3F},// U
{0x1F, 0x20, 0x40, 0x20, 0x1F},// V
{0x7F, 0x20, 0x18, 0x20, 0x7F},// W
{0x63, 0x14, 0x08, 0x14, 0x63},// X
{0x03, 0x04, 0x78, 0x04, 0x03},// Y
{0x61, 0x51, 0x49, 0x45, 0x43},// Z
{0x00, 0x00, 0x7F, 0x41, 0x41},// [
{0x02, 0x04, 0x08, 0x10, 0x20},// "\"
{0x41, 0x41, 0x7F, 0x00, 0x00},// ]
{0x04, 0x02, 0x01, 0x02, 0x04},// ^
{0x40, 0x40, 0x40, 0x40, 0x40},// _
{0x00, 0x01, 0x02, 0x04, 0x00},// `
{0x20, 0x54, 0x54, 0x54, 0x78},// a
{0x7F, 0x48, 0x44, 0x44, 0x38},// b
{0x38, 0x44, 0x44, 0x44, 0x20},// c
{0x38, 0x44, 0x44, 0x48, 0x7F},// d
{0x38, 0x54, 0x54, 0x54, 0x18},// e
{0x08, 0x7E, 0x09, 0x01, 0x02},// f
{0x08, 0x14, 0x54, 0x54, 0x3C},// g
{0x7F, 0x08, 0x04, 0x04, 0x78},// h
{0x00, 0x44, 0x7D, 0x40, 0x00},// i
{0x20, 0x40, 0x44, 0x3D, 0x00},// j
{0x00, 0x7F, 0x10, 0x28, 0x44},// k
{0x00, 0x41, 0x7F, 0x40, 0x00},// l
{0x7C, 0x04, 0x18, 0x04, 0x78},// m
{0x7C, 0x08, 0x04, 0x04, 0x78},// n
{0x38, 0x44, 0x44, 0x44, 0x38},// o
{0x7C, 0x14, 0x14, 0x14, 0x08},// p
{0x08, 0x14, 0x14, 0x18, 0x7C},// q
{0x7C, 0x08, 0x04, 0x04, 0x08},// r
{0x48, 0x54, 0x54, 0x54, 0x20},// s
{0x04, 0x3F, 0x44, 0x40, 0x20},// t
{0x3C, 0x40, 0x40, 0x20, 0x7C},// u
{0x1C, 0x20, 0x40, 0x20, 0x1C},// v
{0x3C, 0x40, 0x30, 0x40, 0x3C},// w
{0x44, 0x28, 0x10, 0x28, 0x44},// x
{0x0C, 0x50, 0x50, 0x50, 0x3C},// y
{0x44, 0x64, 0x54, 0x4C, 0x44},// z
{0x00, 0x08, 0x36, 0x41, 0x00},// {
{0x00, 0x00, 0x7F, 0x00, 0x00},// |
{0x00, 0x41, 0x36, 0x08, 0x00},// }
{0x08, 0x08, 0x2A, 0x1C, 0x08},// ->
{0x08, 0x1C, 0x2A, 0x08, 0x08},// <-
{0x08, 0x04, 0x7E, 0x04, 0x08},// Up
{0x10, 0x20, 0x7E, 0x20, 0x10},// Dn
{0x08, 0x1C, 0x2A, 0x1C, 0x08},// <>
};
spino_code/silabs_code/Si446x_CustomPacketTX/src/drivers/ascii5x7.h 0 → 100644
View file @ 083b3926
/*! @file ascii5x7.h
* @brief <WRITE BRIEF DESCRIPTION OF THE FILE HERE>.
*
* @b COPYRIGHT
* @n Silicon Laboratories Confidential
* @n Copyright 2012 Silicon Laboratories, Inc.
* @n http://www.silabs.com
*/
#ifndef ASCII5X7_H_
#define ASCII5X7_H_
/*------------------------------------------------------------------------*/
/* Global definitions */
/*------------------------------------------------------------------------*/
/*------------------------------------------------------------------------*/
/* Global macros */
/*------------------------------------------------------------------------*/
/*------------------------------------------------------------------------*/
/* Global structure & enumeration definitions */
/*------------------------------------------------------------------------*/
/*------------------------------------------------------------------------*/
/* External variables */
/*------------------------------------------------------------------------*/
extern const SEGMENT_VARIABLE(ascii_table5x7[][5u], U8, SEG_CODE);
/*------------------------------------------------------------------------*/
/* Function prototypes */
/*------------------------------------------------------------------------*/
#endif /* ASCII5X7_H_ */
spino_code/silabs_code/Si446x_CustomPacketTX/src/drivers/cdd_common.h 0 → 100644
View file @ 083b3926
/*! @file control_IO.h
* @brief This file contains the common constants and interfaces used by the
* CDD drivers.
*
* @b COPYRIGHT
* @n Silicon Laboratories Confidential
* @n Copyright 2012 Silicon Laboratories, Inc.
* @n http://www.silabs.com
*/
#ifndef CDD_COMMON_H
#define CDD_COMMON_H
/*****************************************************************************
* Global Definitions & Macros
*****************************************************************************/
/*! Critical Section Macros */
#define ENTER_CRITICAL_SECTION (EA = 0)
#define EXIT_CRITICAL_SECTION (EA = 1)
/**
* @description Useful macro for avoiding compiler warnings related to unused
* function arguments or unused variables.
*/
#define UNUSED_VAR(x) do { if (x) {} } while(0)
/*****************************************************************************
* Global Enums & Typedefs
*****************************************************************************/
/*****************************************************************************
* Global Function Declarations
*****************************************************************************/
/*****************************************************************************
* Global Variables Declarations
*****************************************************************************/
#endif /* CDD_COMMON_H */
spino_code/silabs_code/Si446x_CustomPacketTX/src/drivers/compiler_defs.h 0 → 100644
View file @ 083b3926
/** \file compiler_defs.h
*
* \brief Register/bit definitions for cross-compiler projects on the C8051F93x/2x family.
*
* \b COPYRIGHT
* \n Portions of this file are copyright Maarten Brock
* \n http://sdcc.sourceforge.net
* \n Portions of this file are copyright 2010, Silicon Laboratories, Inc.
* \n http://www.silabs.com
*
*
* <b> GNU LGPL boilerplate: </b>
* \n This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
* \n This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
* \n You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
* \n In other words, you are welcome to use, share and improve this program.
* You are forbidden to forbid anyone else to use, share and improve
* what you give them. Help stamp out software-hoarding!
*
* <b> Program Description: </b>
* \note This header file should be included before including
* a device-specific header file such as C8051F300_defs.h.
*
* Macro definitions to accommodate 8051 compiler differences in specifying
* special function registers and other 8051-specific features such as NOP
* generation, and locating variables in memory-specific segments. The
* compilers are identified by their unique predefined macros. See also:
* http://predef.sourceforge.net/precomp.html
*
* SBIT and SFR define special bit and special function registers at the given
* address. SFR16 and SFR32 define sfr combinations at adjacent addresses in
* little-endian format. SFR16E and SFR32E define sfr combinations without
* prerequisite byte order or adjacency. None of these multi-byte sfr
* combinations will guarantee the order in which they are accessed when read
* or written.
*
* SFR16X and SFR32X for 16 bit and 32 bit xdata registers are not defined
* to avoid portability issues because of compiler endianness.
*
* Example:
* \code
* // my_mcu.c: main 'c' file for my mcu
* #include <compiler_defs.h> // this file
* #include <C8051xxxx_defs.h> // SFR definitions for specific MCU target
*
* SBIT (P0_1, 0x80, 1); // Port 0 pin 1
* SFR (P0, 0x80); // Port 0
* SFRX (CPUCS, 0xE600); // Cypress FX2 Control and Status register in
* // xdata memory at 0xE600
* SFR16 (TMR2, 0xCC); // Timer 2, lsb at 0xCC, msb at 0xCD
* SFR16E(TMR0, 0x8C8A); // Timer 0, lsb at 0x8A, msb at 0x8C
* SFR32 (MAC0ACC, 0x93); // SiLabs C8051F120 32 bits MAC0 Accumulator,
* // lsb at 0x93, msb at 0x96
* SFR32E(SUMR, 0xE5E4E3E2); // TI MSC1210 SUMR 32 bits Summation register,
* // lsb at 0xE2, msb at 0xE5
* \endcode
*
* <b>Target:</b> C8051xxxx
* \n <b>Tool chain:</b> Generic
* \n <b>Command Line:</b> None
*
* Release 2.3 - 27 MAY 2010 (DM)
* \n -Removed 'LOCATED_VARIABLE' pragma from Keil because it is not supported
* \n Release 2.2 - 06 APR 2010 (ES)
* \n -Removed 'PATHINCLUDE' pragma from Raisonance section
* \n Release 2.1 - 16 JUL 2009 (ES)
* \n -Added SEGMENT_POINTER macro definitions for SDCC, Keil, and Raisonance
* \n -Added LOCATED_VARIABLE_NO_INIT macro definitions for Raisonance
* \n Release 2.0 - 19 MAY 2009 (ES)
* \n -Added LOCATED_VARIABLE_NO_INIT macro definitions for SDCC and Keil
* \n Release 1.9 - 23 OCT 2008 (ES)
* \n -Updated Hi-Tech INTERRUPT and INTERRUPT_USING macro definitions
* \n -Added SFR16 macro defintion for Hi-Tech
* \n Release 1.8 - 31 JUL 2008 (ES)
* \n -Added INTERRUPT_USING and FUNCTION_USING macro's
* \n -Added macro's for IAR
* \n -Corrected Union definitions for Hi-Tech and added SFR16 macro defintion
* \n Release 1.7 - 11 SEP 2007 (BW)
* \n -Added support for Raisonance EVAL 03.03.42 and Tasking Eval 7.2r1
* \n Release 1.6 - 27 AUG 2007 (BW)
* \n -Updated copyright notice per agreement with Maartin Brock
* \n -Added SDCC 2.7.0 "compiler.h" bug fixes
* \n -Added memory segment defines (SEG_XDATA, for example)
* \n Release 1.5 - 24 AUG 2007 (BW)
* \n -Added support for NOP () macro
* \n -Added support for Hi-Tech ver 9.01
* \n Release 1.4 - 07 AUG 2007 (PKC)
* \n -Removed FID and fixed formatting.
* \n Release 1.3 - 30 SEP 2007 (TP)
* \n -Added INTERRUPT_PROTO_USING to properly support ISR context switching
* under SDCC.
* \n Release 1.2 - (BW)
* \n -Added support for U8,U16,U32,S8,S16,S32,UU16,UU32 data types
* \n Release 1.1 - (BW)
* \n -Added support for INTERRUPT, INTERRUPT_USING, INTERRUPT_PROTO,
* SEGMENT_VARIABLE, VARIABLE_SEGMENT_POINTER,
* SEGMENT_VARIABLE_SEGMENT_POINTER, and LOCATED_VARIABLE
* \n Release 1.0 - 29 SEP 2006 (PKC)
* \n -Initial revision
*/
//-----------------------------------------------------------------------------
// Header File Preprocessor Directive
//-----------------------------------------------------------------------------
#ifndef COMPILER_DEFS_H
#define COMPILER_DEFS_H
//-----------------------------------------------------------------------------
// Macro definitions
//-----------------------------------------------------------------------------
// SDCC - Small Device C Compiler
// http://sdcc.sourceforge.net
#if defined SDCC
# define SEG_GENERIC
# define SEG_FAR __xdata
# define SEG_DATA __data
# define SEG_NEAR __data
# define SEG_IDATA __idata
# define SEG_XDATA __xdata
# define SEG_PDATA __pdata
# define SEG_CODE __code
//# define SEG_BDATA __bdata
# define SBIT(name, addr, bit) __sbit __at(addr+bit) name
# define SFR(name, addr) __sfr __at(addr) name
# define SFRX(name, addr) xdata volatile unsigned char __at(addr) name
# define SFR16(name, addr) __sfr16 __at(((addr+1U)<<8) | addr) name
# define SFR16E(name, fulladdr) __sfr16 __at(fulladdr) name
# define SFR32(name, addr) __sfr32 __at(((addr+3UL)<<24) | ((addr+2UL)<<16) | ((addr+1UL)<<8) | addr) name
# define SFR32E(name, fulladdr) __sfr32 __at(fulladdr) name
#if (SDCC < 300)
# define INTERRUPT(name, vector) void name (void) interrupt (vector)
# define INTERRUPT_USING(name, vector, regnum) void name (void) interrupt (vector) using (regnum)
# define INTERRUPT_PROTO(name, vector) void name (void) interrupt (vector)
# define INTERRUPT_PROTO_USING(name, vector, regnum) void name (void) interrupt (vector) using (regnum)
# define FUNCTION_USING(name, return_value, parameter, regnum) return_value name (parameter) using (regnum)
# define FUNCTION_PROTO_USING(name, return_value, parameter, regnum) return_value name (parameter) using (regnum)
// Note: Parameter must be either 'void' or include a variable type and name. (Ex: char temp_variable)
# define SEGMENT_VARIABLE(name, vartype, locsegment) locsegment vartype name
# define VARIABLE_SEGMENT_POINTER(name, vartype, targsegment) targsegment vartype * name
# define SEGMENT_VARIABLE_SEGMENT_POINTER(name, vartype, targsegment, locsegment) targsegment vartype * locsegment name
# define SEGMENT_POINTER(name, vartype, locsegment) vartype * locsegment name
# define LOCATED_VARIABLE(name, vartype, locsegment, addr, init) locsegment at (addr) vartype name = init
# define LOCATED_VARIABLE_NO_INIT(name, vartype, locsegment, addr) locsegment at (addr) vartype name
# define LOCATED_VARIABLE_POST_INIT(name, vartype, locsegment, addr) locsegment at (addr) vartype name
#else //SDCC >= 300
# define INTERRUPT(name, vector) void name (void) __interrupt (vector)
# define INTERRUPT_USING(name, vector, regnum) void name (void) __interrupt (vector) using (regnum)
# define INTERRUPT_PROTO(name, vector) void name (void) __interrupt (vector)
# define INTERRUPT_PROTO_USING(name, vector, regnum) void name (void) __interrupt (vector) using (regnum)
# define FUNCTION_USING(name, return_value, parameter, regnum) return_value name (parameter) using (regnum)
# define FUNCTION_PROTO_USING(name, return_value, parameter, regnum) return_value name (parameter) using (regnum)
// Note: Parameter must be either 'void' or include a variable type and name. (Ex: char temp_variable)
# define SEGMENT_VARIABLE(name, vartype, locsegment) locsegment vartype name
# define VARIABLE_SEGMENT_POINTER(name, vartype, targsegment) targsegment vartype * name
# define SEGMENT_VARIABLE_SEGMENT_POINTER(name, vartype, targsegment, locsegment) targsegment vartype * locsegment name
# define SEGMENT_POINTER(name, vartype, locsegment) vartype * locsegment name
# define LOCATED_VARIABLE(name, vartype, locsegment, addr, init) locsegment __at (addr) vartype name = init
# define LOCATED_VARIABLE_NO_INIT(name, vartype, locsegment, addr) locsegment __at (addr) vartype name
# define LOCATED_VARIABLE_POST_INIT(name, vartype, locsegment, addr) locsegment __at (addr) vartype name
#endif //SDCC >= 300
// used with UU16
# define LSB 0
# define MSB 1
// used with UU32 (b0 is least-significant byte)
# define b0 0
# define b1 1
# define b2 2
# define b3 3
#if (SDCC < 300)
typedef bit BIT;
#else //SDCC >= 300
typedef __bit BIT;
#endif //SDCC >= 300
#define BITS(bitArray, bitPos) BIT bitArray ## bitPos
#define WRITE_TO_BIT_ARRAY(bitArray, byte) bitArray ## 0 = byte & 0x01; \
bitArray ## 1 = byte & 0x02; \
bitArray ## 2 = byte & 0x04; \
bitArray ## 3 = byte & 0x08; \
bitArray ## 4 = byte & 0x10; \
bitArray ## 5 = byte & 0x20; \
bitArray ## 6 = byte & 0x40; \
bitArray ## 7 = byte & 0x80;
#define READ_FROM_BIT_ARRAY(bitArray, byte) byte = (bitArray ## 0) | \
((bitArray ## 1) << 1) | \
((bitArray ## 2) << 2) | \
((bitArray ## 3) << 3) | \
((bitArray ## 4) << 4) | \
((bitArray ## 5) << 5) | \
((bitArray ## 6) << 6) | \
((bitArray ## 7) << 7);
typedef unsigned char U8;
typedef unsigned int U16;
typedef unsigned long U32;
typedef signed char S8;
typedef signed int S16;
typedef signed long S32;
typedef union UU16
{
U16 U16;
S16 S16;
U8 U8[2];
S8 S8[2];
} UU16;
typedef union UU32
{
U32 U32;
S32 S32;
UU16 UU16[2];
U16 U16[2];
S16 S16[2];
U8 U8[4];
S8 S8[4];
} UU32;
// NOP () macro support
#if (SDCC<300)
#define NOP() _asm NOP _endasm
#else //SDCC>= 300
#define NOP() __asm NOP __endasm
#endif //SDCC>= 300
//-----------------------------------------------------------------------------
// Raisonance (must be placed before Keil C51)
// http://www.raisonance.com
#elif defined __RC51__
//#error Raisonance C51 detected.
# define SEG_GENERIC generic //SEG_GENERIC only applies to pointers in Raisonance, not variables.
# define SEG_FAR xdata
# define SEG_DATA data
# define SEG_NEAR data
# define SEG_IDATA idata
# define SEG_XDATA xdata
# define SEG_PDATA pdata
# define SEG_CODE code
# define SEG_BDATA bdata
# define SBIT(name, addr, bit) at (addr+bit) sbit name
# define SFR(name, addr) sfr at addr name
# define SFR16(name, addr) sfr16 at addr name
# define SFR16E(name, fulladdr) /* not supported */
# define SFR32(name, fulladdr) /* not supported */
# define SFR32E(name, fulladdr) /* not supported */
# define INTERRUPT(name, vector) void name (void) interrupt vector
# define INTERRUPT_USING(name, vector, regnum) void name (void) interrupt vector using regnum
# define INTERRUPT_PROTO(name, vector) void name (void)
# define INTERRUPT_PROTO_USING(name, vector, regnum) void name (void)
# define FUNCTION_USING(name, return_value, parameter, regnum) return_value name (parameter) using regnum
# define FUNCTION_PROTO_USING(name, return_value, parameter, regnum) return_value name (parameter)
// Note: Parameter must be either 'void' or include a variable type and name. (Ex: char temp_variable)
# define SEGMENT_VARIABLE(name, vartype, locsegment) vartype locsegment name
# define VARIABLE_SEGMENT_POINTER(name, vartype, targsegment) vartype targsegment * name
# define SEGMENT_VARIABLE_SEGMENT_POINTER(name, vartype, targsegment, locsegment) vartype targsegment * locsegment name
# define SEGMENT_POINTER(name, vartype, locsegment) vartype * locsegment name
# define LOCATED_VARIABLE(name, vartype, locsegment, addr, init) at addr locsegment vartype name
# define LOCATED_VARIABLE_NO_INIT(name, vartype, locsegment, addr) at addr locsegment vartype name
// used with UU16
# define LSB 1
# define MSB 0
// used with UU32 (b0 is least-significant byte)
# define b0 3
# define b1 2
# define b2 1
# define b3 0
typedef bit BIT;
#define BITS(bitArray, bitPos) BIT bitArray ## bitPos
#define WRITE_TO_BIT_ARRAY(bitArray, byte) bitArray ## 0 = byte & 0x01; \
bitArray ## 1 = byte & 0x02; \
bitArray ## 2 = byte & 0x04; \
bitArray ## 3 = byte & 0x08; \
bitArray ## 4 = byte & 0x10; \
bitArray ## 5 = byte & 0x20; \
bitArray ## 6 = byte & 0x40; \
bitArray ## 7 = byte & 0x80;
#define READ_FROM_BIT_ARRAY(bitArray, byte) byte = (bitArray ## 0) | \
((bitArray ## 1) << 1) | \
((bitArray ## 2) << 2) | \
((bitArray ## 3) << 3) | \
((bitArray ## 4) << 4) | \
((bitArray ## 5) << 5) | \
((bitArray ## 6) << 6) | \
((bitArray ## 7) << 7);
typedef unsigned char U8;
typedef unsigned int U16;
typedef unsigned long U32;
typedef signed char S8;
typedef signed int S16;
typedef signed long S32;
typedef union UU16
{
U16 U16;
S16 S16;
U8 U8[2];
S8 S8[2];
} UU16;
typedef union UU32
{
U32 U32;
S32 S32;
UU16 UU16[2];
U16 U16[2];
S16 S16[2];
U8 U8[4];
S8 S8[4];
} UU32;
// NOP () macro support -- NOP is opcode 0x00
#define NOP() asm { 0x00 }
//-----------------------------------------------------------------------------
// Keil C51
// http://www.keil.com
#elif (defined __C51__) || (defined __CX51__)
//#error Keil C51 detected.
# define SEG_GENERIC
# define SEG_FAR xdata
# define SEG_DATA data
# define SEG_NEAR data
# define SEG_IDATA idata
# define SEG_XDATA xdata
# define SEG_PDATA pdata
# define SEG_CODE code
# define SEG_BDATA bdata
# define SBIT(name, addr, bit) sbit name = addr^bit
# define SFR(name, addr) sfr name = addr
# define SFR16(name, addr) sfr16 name = addr
# define SFR16E(name, fulladdr) /* not supported */
# define SFR32(name, fulladdr) /* not supported */
# define SFR32E(name, fulladdr) /* not supported */
# define INTERRUPT(name, vector) void name (void) interrupt vector
# define INTERRUPT_USING(name, vector, regnum) void name (void) interrupt vector using regnum
# define INTERRUPT_PROTO(name, vector) void name (void)
# define INTERRUPT_PROTO_USING(name, vector, regnum) void name (void)
# define FUNCTION_USING(name, return_value, parameter, regnum) return_value name (parameter) using regnum
# define FUNCTION_PROTO_USING(name, return_value, parameter, regnum) return_value name (parameter)
// Note: Parameter must be either 'void' or include a variable type and name. (Ex: char temp_variable)
# define SEGMENT_VARIABLE(name, vartype, locsegment) vartype locsegment name
# define VARIABLE_SEGMENT_POINTER(name, vartype, targsegment) vartype targsegment * name
# define SEGMENT_VARIABLE_SEGMENT_POINTER(name, vartype, targsegment, locsegment) vartype targsegment * locsegment name
# define SEGMENT_POINTER(name, vartype, locsegment) vartype * locsegment name
# define LOCATED_VARIABLE_NO_INIT(name, vartype, locsegment, addr) vartype locsegment name _at_ addr
// used with UU16
# define LSB 1
# define MSB 0
// used with UU32 (b0 is least-significant byte)
# define b0 3
# define b1 2
# define b2 1
# define b3 0
typedef bit BIT;
#define BITS(bitArray, bitPos) BIT bitArray ## bitPos
#define WRITE_TO_BIT_ARRAY(bitArray, byte) bitArray ## 0 = byte & 0x01; \
bitArray ## 1 = byte & 0x02; \
bitArray ## 2 = byte & 0x04; \
bitArray ## 3 = byte & 0x08; \
bitArray ## 4 = byte & 0x10; \
bitArray ## 5 = byte & 0x20; \
bitArray ## 6 = byte & 0x40; \
bitArray ## 7 = byte & 0x80;
#define READ_FROM_BIT_ARRAY(bitArray, byte) byte = (bitArray ## 0) | \
((bitArray ## 1) << 1) | \
((bitArray ## 2) << 2) | \
((bitArray ## 3) << 3) | \
((bitArray ## 4) << 4) | \
((bitArray ## 5) << 5) | \
((bitArray ## 6) << 6) | \
((bitArray ## 7) << 7);
typedef unsigned char U8;
typedef unsigned int U16;
typedef unsigned long U32;
typedef signed char S8;
typedef signed int S16;
typedef signed long S32;
typedef union UU16
{
U16 U16;
S16 S16;
U8 U8[2];
S8 S8[2];
} UU16;
typedef union UU32
{
U32 U32;
S32 S32;
UU16 UU16[2];
U16 U16[2];
S16 S16[2];
U8 U8[4];
S8 S8[4];
} UU32;
// NOP () macro support
extern void _nop_ (void);
#define NOP() _nop_()
//-----------------------------------------------------------------------------
// Hi-Tech 8051
// http://www.htsoft.com
#elif defined HI_TECH_C
# define SEG_GENERIC
# define SEG_FAR far
# define SEG_DATA data
# define SEG_NEAR near
# define SEG_IDATA idata
# define SEG_XDATA xdata
# define SEG_PDATA pdata
# define SEG_CODE code
# define SEG_BDATA bdata
# define SBIT(name, addr, thebit) static volatile bit name @ (addr + thebit)
# define SFR(name, addr) static volatile unsigned char name @ addr
# define SFR16(name, addr) static volatile unsigned int name @ addr
# define SFR16E(name, fulladdr) /* not supported */
# define SFR32(name, fulladdr) /* not supported */
# define SFR32E(name, fulladdr) /* not supported */
# define INTERRUPT(name, vector) void name (void) interrupt vector
# define INTERRUPT_PROTO(name, vector)
# define INTERRUPT_USING(name, vector, regnum) void name (void) interrupt vector using regnum
# define INTERRUPT_PROTO_USING(name, vector, regnum)
# define FUNCTION_USING(name, return_value, parameter, regnum) /* not supported */
# define FUNCTION_PROTO_USING(name, return_value, parameter, regnum) /* not supported */
// Note: Hi-Tech does not support functions using different register banks. Register
// banks can only be specified in interrupts. If a function is called from
// inside an interrupt, it will use the same register bank as the interrupt.
# define SEGMENT_VARIABLE(name, vartype, locsegment) locsegment vartype name
# define VARIABLE_SEGMENT_POINTER(name, vartype, targsegment) targsegment vartype * name
# define SEGMENT_VARIABLE_SEGMENT_POINTER(name, vartype, targsegment, locsegment) targsegment vartype * locsegment name
# define LOCATED_VARIABLE(name, vartype, locsegment, addr, init) locsegment vartype name @ addr
// used with UU16
# define LSB 0
# define MSB 1
// used with UU32 (b0 is least-significant byte)
# define b0 0
# define b1 1
# define b2 2
# define b3 3
typedef unsigned char U8;
typedef unsigned int U16;
typedef unsigned long U32;
typedef signed char S8;
typedef signed int S16;
typedef signed long S32;
typedef union UU16
{
U16 U16;
S16 S16;
U8 U8[2];
S8 S8[2];
} UU16;
typedef union UU32
{
U32 U32;
S32 S32;
UU16 UU16[2];
U16 U16[2];
S16 S16[2];
U8 U8[4];
S8 S8[4];
} UU32;
// NOP () macro support
#define NOP() asm(" nop ")
//-----------------------------------------------------------------------------
// Tasking / Altium
// http://www.altium.com/tasking
#elif defined _CC51
# define SEG_GENERIC
# define SEG_FAR _xdat
# define SEG_DATA _data
# define SEG_NEAR _data
# define SEG_IDATA _idat
# define SEG_XDATA _xdat
# define SEG_PDATA _pdat
# define SEG_CODE _rom
# define SEG_BDATA _bdat
# define SBIT(name, addr, bit) _sfrbit name _at(addr+bit)
# define SFR(name, addr) _sfrbyte name _at(addr)
# define SFRX(name, addr) _xdat volatile unsigned char name _at(addr)
#if _CC51 > 71
# define SFR16(name, addr) _sfrword _little name _at(addr)
#else
# define SFR16(name, addr) /* not supported */
#endif
# define SFR16E(name, fulladdr) /* not supported */
# define SFR32(name, fulladdr) /* not supported */
# define SFR32E(name, fulladdr) /* not supported */
# define INTERRUPT(name, vector) _interrupt (vector) void name (void)
# define INTERRUPT_USING(name, vector, regnum) _interrupt (vector) _using(regnum) void name (void)
# define INTERRUPT_PROTO(name, vector) _interrupt (vector) void name (void)
# define INTERRUPT_PROTO_USING(name, vector, regnum) _interrupt (vector) _using(regnum) void name (void)
// When calling FUNCTION_USING in Tasking, the function must be called from an interrupt or Main which
// is also using the same register bank. If not, the compiler will generate an error.
# define FUNCTION_USING(name, return_value, parameter, regnum) _using(regnum) return_value name (parameter)
# define FUNCTION_PROTO_USING(name, return_value, parameter, regnum) _using(regnum) return_value name (parameter)
// Note: Parameter must be either 'void' or include a variable type and name. (Ex: char temp_variable)
# define SEGMENT_VARIABLE(name, vartype, locsegment) vartype locsegment name
# define VARIABLE_SEGMENT_POINTER(name, vartype, targsegment) vartype targsegment * name
# define SEGMENT_VARIABLE_SEGMENT_POINTER(name, vartype, targsegment, locsegment) vartype targsegment * locsegment name
# define LOCATED_VARIABLE(name, vartype, locsegment, addr, init) vartype locsegment name _at( addr )
// used with UU16
# define LSB 1
# define MSB 0
// used with UU32 (b0 is least-significant byte)
# define b0 3
# define b1 2
# define b2 1
# define b3 0
typedef unsigned char U8;
typedef unsigned int U16;
typedef unsigned long U32;
typedef signed char S8;
typedef signed int S16;
typedef signed long S32;
typedef union UU16
{
U16 U16;
S16 S16;
U8 U8[2];
S8 S8[2];
} UU16;
typedef union UU32
{
U32 U32;
S32 S32;
UU16 UU16[2];
U16 U16[2];
S16 S16[2];
U8 U8[4];
S8 S8[4];
} UU32;
// NOP () macro support
extern void _nop (void);
#define NOP() _nop()
//-----------------------------------------------------------------------------
// IAR 8051
// http://www.iar.com
#elif defined __ICC8051__
#include <stdbool.h>
#include <intrinsics.h>
# define SBIT(name, addr, bit) __bit __no_init volatile bool name @ (addr+bit)
# define SFR(name, addr) __sfr __no_init volatile unsigned char name @ addr
# define SFRX(name, addr) __xdata __no_init volatile unsigned char name @ addr
# define SFR16(name, addr) __sfr __no_init volatile unsigned int name @ addr
# define SFR16E(name, fulladdr) /* not supported */
# define SFR32(name, fulladdr) /* not supported */
# define SFR32E(name, fulladdr) /* not supported */
# define SEG_GENERIC __generic
# define SEG_FAR __xdata
# define SEG_DATA __data
# define SEG_NEAR __data
# define SEG_IDATA __idata
# define SEG_XDATA __xdata
# define SEG_PDATA __pdata
# define SEG_CODE __code
# define SEG_BDATA __bdata
#define bit bool
# define _PPTOSTR_(x) #x
# define _PPARAM_(address) _PPTOSTR_(vector=address * 8 + 3)
# define _PPARAM2_(regbank) _PPTOSTR_(register_bank=regbank)
# define INTERRUPT(name, vector) _Pragma(_PPARAM_(vector)) __interrupt void name(void)
# define INTERRUPT_PROTO(name, vector) __interrupt void name(void)
# define INTERRUPT_USING(name, vector, regnum) _Pragma(_PPARAM2_(regnum)) _Pragma(_PPARAM_(vector)) __interrupt void name(void)
# define INTERRUPT_PROTO_USING(name, vector, regnum) __interrupt void name(void)
# define FUNCTION_USING(name, return_value, parameter, regnum) /* not supported */
# define FUNCTION_PROTO_USING(name, return_value, parameter, regnum) /* not supported */
// Note: IAR does not support functions using different register banks. Register
// banks can only be specified in interrupts. If a function is called from
// inside an interrupt, it will use the same register bank as the interrupt.
# define SEGMENT_VARIABLE(name, vartype, locsegment) locsegment vartype name
# define VARIABLE_SEGMENT_POINTER(name, vartype, targsegment) vartype targsegment * name
# define SEGMENT_VARIABLE_SEGMENT_POINTER(name, vartype, targsegment, locsegment) vartype targsegment * locsegment name
# define LOCATED_VARIABLE(name, vartype, locsegment, addr, init) locsegment __no_init vartype name @ addr
// used with UU16
# define LSB 0
# define MSB 1
// used with UU32 (b0 is least-significant byte)
# define b0 0
# define b1 1
# define b2 2
# define b3 3
typedef unsigned char U8;
typedef unsigned int U16;
typedef unsigned long U32;
typedef signed char S8;
typedef signed int S16;
typedef signed long S32;
typedef union UU16
{
U16 U16;
S16 S16;
U8 U8[2];
S8 S8[2];
} UU16;
typedef union UU32
{
U32 U32;
S32 S32;
UU16 UU16[2];
U16 U16[2];
S16 S16[2];
U8 U8[4];
S8 S8[4];
} UU32;
#define NOP() __no_operation();
//-----------------------------------------------------------------------------
// Crossware
// http://www.crossware.com
#elif defined _XC51_VER
# define SBIT(name, addr, bit) _sfrbit name = (addr+bit)
# define SFR(name, addr) _sfr name = addr
# define SFR16(name, addr) _sfrword name = addr
# define SFR16E(name, fulladdr) /* not supported */
# define SFR32(name, fulladdr) /* not supported */
# define SFR32E(name, fulladdr) /* not supported */
//-----------------------------------------------------------------------------
// Wickenhuser
// http://www.wickenhaeuser.de
#elif defined __UC__
# define SBIT(name, addr, bit) unsigned char bit name @ (addr+bit)
# define SFR(name, addr) near unsigned char name @ addr
# define SFR16(name, addr) /* not supported */
# define SFR16E(name, fulladdr) /* not supported */
# define SFR32(name, fulladdr) /* not supported */
# define SFR32E(name, fulladdr) /* not supported */
//-----------------------------------------------------------------------------
// Default
// Unknown compiler
#else
# warning unrecognized compiler
#define SEG_FAR
#define SEG_DATA
#define SEG_NEAR
#define SEG_IDATA
#define SEG_XDATA
#define SEG_PDATA
#define SEG_CODE
#define SEG_BDATA
#define SBIT(name, addr, bit) volatile unsigned char name
#define SFR(name, addr) volatile unsigned char name
#define SFRX(name, addr) volatile unsigned char name
#define SFR16(name, addr) volatile unsigned short name
#define SFR16E(name, fulladdr) volatile unsigned short name
#define SFR32(name, fulladdr) volatile unsigned long name
#define SFR32E(name, fulladdr) volatile unsigned long name
#define INTERRUPT(name, vector) void name (void)
#define INTERRUPT_USING(name, vector, regnum) void name (void)
#define INTERRUPT_PROTO(name, vector) void name (void)
#define INTERRUPT_PROTO_USING(name, vector, regnum) void name (void)
#define FUNCTION_USING(name, return_value, parameter, regnum) return_value name (parameter)
#define FUNCTION_PROTO_USING(name, return_value, parameter, regnum) return_value name (parameter)
// Note: Parameter must be either 'void' or include a variable type and name. (Ex: char temp_variable)
#define SEGMENT_VARIABLE(name, vartype, locsegment) vartype locsegment name
#define VARIABLE_SEGMENT_POINTER(name, vartype, targsegment) vartype targsegment * name
#define SEGMENT_VARIABLE_SEGMENT_POINTER(name, vartype, targsegment, locsegment) vartype targsegment * locsegment name
#define SEGMENT_POINTER(name, vartype, locsegment) vartype * locsegment name
#define LOCATED_VARIABLE(name, vartype, locsegment, addr, init) locsegment vartype name
#define LOCATED_VARIABLE_NO_INIT(name, vartype, locsegment, addr) locsegment vartype name
// used with UU16
#define LSB 0
#define MSB 1
// used with UU32 (b0 is least-significant byte)
#define b0 0
#define b1 1
#define b2 2
#define b3 3
typedef unsigned char U8;
typedef unsigned int U16;
typedef unsigned long U32;
typedef signed char S8;
typedef signed int S16;
typedef signed long S32;
typedef union UU16
{
U16 U16;
S16 S16;
U8 U8[2];
S8 S8[2];
} UU16;
typedef union UU32
{
U32 U32;
S32 S32;
UU16 UU16[2];
U16 U16[2];
S16 S16[2];
U8 U8[4];
S8 S8[4];
} UU32;
// NOP () macro support
extern void _nop (void);
#define NOP() _nop()
typedef unsigned char bit;
typedef bit BIT;
#define BITS(bitArray, bitPos) BIT bitArray ## bitPos
#define WRITE_TO_BIT_ARRAY(bitArray, byte) bitArray ## 0 = byte & 0x01; \
bitArray ## 1 = byte & 0x02; \
bitArray ## 2 = byte & 0x04; \
bitArray ## 3 = byte & 0x08; \
bitArray ## 4 = byte & 0x10; \
bitArray ## 5 = byte & 0x20; \
bitArray ## 6 = byte & 0x40; \
bitArray ## 7 = byte & 0x80;
#define READ_FROM_BIT_ARRAY(bitArray, byte) byte = (bitArray ## 0) | \
((bitArray ## 1) << 1) | \
((bitArray ## 2) << 2) | \
((bitArray ## 3) << 3) | \
((bitArray ## 4) << 4) | \
((bitArray ## 5) << 5) | \
((bitArray ## 6) << 6) | \
((bitArray ## 7) << 7);
#endif
//-----------------------------------------------------------------------------
// Compiler independent data type definitions
//-----------------------------------------------------------------------------
#ifndef FALSE
#define FALSE 0
#endif
#ifndef TRUE
#define TRUE !FALSE
#endif
#ifndef NULL
#define NULL ((void *) 0)
#endif
//-----------------------------------------------------------------------------
// Header File PreProcessor Directive
//-----------------------------------------------------------------------------
#endif // #define COMPILER_DEFS_H
//-----------------------------------------------------------------------------
// End Of File
//-----------------------------------------------------------------------------
spino_code/silabs_code/Si446x_CustomPacketTX/src/drivers/control_IO.c 0 → 100644
View file @ 083b3926
/*! @file control_IO.c
* @brief This file contains functions for controlling LEDs and PBs.
*
* @b COPYRIGHT
* @n Silicon Laboratories Confidential
* @n Copyright 2012 Silicon Laboratories, Inc.
* @n http://www.silabs.com
*/
#include "..\bsp.h"
/*------------------------------------------------------------------------*/
/* Global variables */
/*------------------------------------------------------------------------*/
/*------------------------------------------------------------------------*/
/* Local variables */
/*------------------------------------------------------------------------*/
#if (!(defined SILABS_PLATFORM_RFSTICK) && !(defined SILABS_PLATFORM_LCDBB))
volatile SEGMENT_VARIABLE(bDelay, U8, SEG_XDATA);
#endif
#if (defined SILABS_IO_WITH_EXTENDER)
typedef union {
U8 bCio_IoExtCommArrayCmd[bCio_IoExtAddrLength_c + bCio_IoExtCmdLength_c];
U8 bCio_IoExtCommArrayResp[bCio_IoExtAddrLength_c + bCio_IoExtRespLength_c];
} uIoExtCommArray;
/**< Data array for IO extender communication */
SEGMENT_VARIABLE(bCio_IoExtCommArray, uIoExtCommArray, SEG_DATA);
#else
/**< State holder of IO port*/
SEGMENT_VARIABLE(bCio_IoPortState, U8, SEG_DATA);
#endif
/*------------------------------------------------------------------------*/
/* Local macros */
/*------------------------------------------------------------------------*/
#if (!(defined SILABS_PLATFORM_RFSTICK) && !(defined SILABS_PLATFORM_LCDBB))
#define mCio_WaitIOSteadyState \
for (bDelay = 0u; bDelay < 0x01; bDelay++) ;
#if (defined SILABS_MCU_DC_EMIF_F930)
#define mCio_WaitIOSteadyState_long \
for (bDelay = 0u; bDelay < 0x3F; bDelay++) ;
#endif
#endif
/*------------------------------------------------------------------------*/
/* Function implementations */
/*------------------------------------------------------------------------*/
/*!
* This function is used to initialize specific IO port for LED & PB.
*
* @return None
*
* @note It has to be called from the initialization section.
*/
void vCio_InitIO(void)
{
#ifndef SILABS_IO_WITH_EXTENDER
#if ((defined SILABS_PLATFORM_RFSTICK) || (defined SILABS_PLATFORM_LCDBB))
bCio_IoPortState = (~M_BZ1); //Config all to '1', but buzzer
P2 = bCio_IoPortState;
#elif (defined SILABS_MCU_DC_EMIF_F930)
bCio_IoPortState = eHmi_NoLed_c;
P0 = (P0 & ~M_P0_IO);
#elif (defined SILABS_PLATFORM_WMB930)
bCio_IoPortState = (M_LED1) | (M_LED2) | (M_LED3) | (M_LED4);
#elif (defined SILABS_PLATFORM_WMB912)
bCio_IoPortState = (M_LED1);
#else
#error TO BE WRITTEN FOR OTHER PLARFORMS!
#endif
#endif
}
/*!
* This function is used to switch the selected LED on.
*
* @param[in] biLedNum Number of the LED to be switched on (1 ... 4).
*
* @return None
*/
void vCio_SetLed(U8 biLedNum)
{
#ifdef SILABS_IO_WITH_EXTENDER
*((U16*) bCio_IoExtCommArray.bCio_IoExtCommArrayCmd) = \
IOEXT_ADDR_CONTROL_SET_LED_STATE;
#endif
switch(biLedNum)
{
case 1:
#if (defined SILABS_IO_WITH_EXTENDER)
*(bCio_IoExtCommArray.bCio_IoExtCommArrayCmd + 2u) = eCio_Led1_c;
#else
LED1 = ILLUMINATE;
bCio_IoPortState &= (~M_LED1);
#endif
break;
case 2:
#if (defined SILABS_IO_WITH_EXTENDER)
*(bCio_IoExtCommArray.bCio_IoExtCommArrayCmd + 2u) = eCio_Led2_c;
#elif !(defined SILABS_PLATFORM_WMB912)
bCio_IoPortState &= (~M_LED2);
LED2 = ILLUMINATE;
#endif
break;
case 3:
#if (defined SILABS_IO_WITH_EXTENDER)
*(bCio_IoExtCommArray.bCio_IoExtCommArrayCmd + 2u) = eCio_Led3_c;
#elif !(defined SILABS_PLATFORM_WMB912)
bCio_IoPortState &= (~M_LED3);
LED3 = ILLUMINATE;
#endif
break;
case 4:
#if (defined SILABS_IO_WITH_EXTENDER)
*(bCio_IoExtCommArray.bCio_IoExtCommArrayCmd + 2u) = eCio_Led4_c;
#elif !(defined SILABS_PLATFORM_WMB912)
bCio_IoPortState &= (~M_LED4);
LED4 = ILLUMINATE;
#endif
break;
default:
break;
}
#ifdef SILABS_IO_WITH_EXTENDER
/* Request LED state change */
qSmbus_SMBusWrite(IOEXT_SMBUS_ADDR, \
bCio_IoExtAddrLength_c + bCio_IoExtCmdLength_c, \
bCio_IoExtCommArray.bCio_IoExtCommArrayCmd);
#endif
}
/*!
* This function is used to switch the selected LED off.
*
* @param[in] biLedNum Number of the LED to be switched off (1 ... 4).
*
* @return None
*/
void vCio_ClearLed(U8 biLedNum)
{
#ifdef SILABS_IO_WITH_EXTENDER
*((U16*) bCio_IoExtCommArray.bCio_IoExtCommArrayCmd) = \
IOEXT_ADDR_CONTROL_CLEAR_LED_STATE;
#endif
switch(biLedNum)
{
case 1:
#if (defined SILABS_IO_WITH_EXTENDER)
*(bCio_IoExtCommArray.bCio_IoExtCommArrayCmd + 2u) = eCio_Led1_c;
#else
LED1 = EXTINGUISH;
bCio_IoPortState |= M_LED1;
#endif
break;
case 2:
#if (defined SILABS_IO_WITH_EXTENDER)
*(bCio_IoExtCommArray.bCio_IoExtCommArrayCmd + 2u) = eCio_Led2_c;
#elif !(defined SILABS_PLATFORM_WMB912)
bCio_IoPortState |= M_LED2;
LED2 = EXTINGUISH;
#endif
break;
case 3:
#if (defined SILABS_IO_WITH_EXTENDER)
*(bCio_IoExtCommArray.bCio_IoExtCommArrayCmd + 2u) = eCio_Led3_c;
#elif !(defined SILABS_PLATFORM_WMB912)
bCio_IoPortState |= M_LED3;
LED3 = EXTINGUISH;
#endif
break;
case 4:
#if (defined SILABS_IO_WITH_EXTENDER)
*(bCio_IoExtCommArray.bCio_IoExtCommArrayCmd + 2u) = eCio_Led4_c;
#elif !(defined SILABS_PLATFORM_WMB912)
bCio_IoPortState |= M_LED4;
LED4 = EXTINGUISH;
#endif
break;
default:
break;
}
#ifdef SILABS_IO_WITH_EXTENDER
/* Request LED state change */
qSmbus_SMBusWrite(IOEXT_SMBUS_ADDR, \
bCio_IoExtAddrLength_c + bCio_IoExtCmdLength_c, \
bCio_IoExtCommArray.bCio_IoExtCommArrayCmd);
#endif
}
/**
* Function to toggle the given LED state.
*
* @param[in] biLedNum Number of the LED to be toggled off (1 ... 4).
*
* @return None.
*/
void vCio_ToggleLed(U8 biLedNum)
{
#ifdef SILABS_IO_WITH_EXTENDER
*((U16*) bCio_IoExtCommArray.bCio_IoExtCommArrayCmd) = \
IOEXT_ADDR_CONTROL_TOGGLE_LED_STATE;
#endif
switch(biLedNum)
{
case 1:
#if (defined SILABS_IO_WITH_EXTENDER)
*(bCio_IoExtCommArray.bCio_IoExtCommArrayCmd + 2u) = eCio_Led1_c;
#else
if (bCio_IoPortState & M_LED1)
vCio_SetLed(biLedNum);
else
vCio_ClearLed(biLedNum);
#endif
break;
case 2:
#if (defined SILABS_IO_WITH_EXTENDER)
*(bCio_IoExtCommArray.bCio_IoExtCommArrayCmd + 2u) = eCio_Led2_c;
#elif !(defined SILABS_PLATFORM_WMB912)
if (bCio_IoPortState & M_LED2)
vCio_SetLed(biLedNum);
else
vCio_ClearLed(biLedNum);
#endif
break;
case 3:
#if (defined SILABS_IO_WITH_EXTENDER)
*(bCio_IoExtCommArray.bCio_IoExtCommArrayCmd + 2u) = eCio_Led3_c;
#elif !(defined SILABS_PLATFORM_WMB912)
if (bCio_IoPortState & M_LED3)
vCio_SetLed(biLedNum);
else
vCio_ClearLed(biLedNum);
#endif
break;
case 4:
#if (defined SILABS_IO_WITH_EXTENDER)
*(bCio_IoExtCommArray.bCio_IoExtCommArrayCmd + 2u) = eCio_Led4_c;
#elif !(defined SILABS_PLATFORM_WMB912)
if (bCio_IoPortState & M_LED4)
vCio_SetLed(biLedNum);
else
vCio_ClearLed(biLedNum);
#endif
break;
default:
break;
}
#ifdef SILABS_IO_WITH_EXTENDER
/* Request LED state change */
qSmbus_SMBusWrite(IOEXT_SMBUS_ADDR, \
bCio_IoExtAddrLength_c + bCio_IoExtCmdLength_c, \
bCio_IoExtCommArray.bCio_IoExtCommArrayCmd);
#endif
}
/*!
* This function is used to read the status of the selected push-button.
*
* @param[in] biPbNum Number of the push-button to be switched on (1 ... 4).
*
* @return State of the selected PB.
*
* @note If SILABS_IO_WITH_EXTENDER defined the function implements a "cache"
* algorithm to eliminate the SMBus communication overhead. As the IOExt returns
* all PB states in one byte queries for each PB state is unnecessary. The SMBus
* fetch takes place only in case the PB state has been already read.
*/
BIT gCio_GetPB(U8 biPbNum)
{
#if (defined SILABS_IO_WITH_EXTENDER)
SEGMENT_VARIABLE(lutPB[SILABS_PLATFORM_COMPONENT_PB + 1u], U8, SEG_CODE) = \
{ 0x00, 0x01, 0x02, 0x04, 0x08, };
/* Store the fetched, not yet queried PB states */
static SEGMENT_VARIABLE(lPBState, U8, SEG_DATA) = 0x00;
if (!(lPBState & lutPB[biPbNum])) {
/* Fill SMBus data array: address */
*((U16*) bCio_IoExtCommArray.bCio_IoExtCommArrayCmd) = \
IOEXT_ADDR_REQUEST_GPIO_STATE;
/* Request PB state */
if (qSmbus_SMBusWrite(IOEXT_SMBUS_ADDR, \
bCio_IoExtAddrLength_c, \
bCio_IoExtCommArray.bCio_IoExtCommArrayCmd) == \
SMBUS_TRANSMISSION_OK) {
/* Read PB state */
if (qSmbus_SMBusRead(IOEXT_SMBUS_ADDR, \
bCio_IoExtRespLength_c, \
bCio_IoExtCommArray.bCio_IoExtCommArrayResp) == \
SMBUS_RX_FINISHED) {
lPBState = \
(bCio_IoExtCommArray.bCio_IoExtCommArrayResp[0u] << 4u) | 0x0F;
}
}
}
/* Check requested PB state */
if ((biPbNum) && (SILABS_PLATFORM_COMPONENT_PB >= biPbNum)) {
lPBState &= ~(lutPB[biPbNum]);
if ((lPBState >> 4u) & lutPB[biPbNum]) {
return TRUE;
}
}
return FALSE;
#elif ((defined SILABS_PLATFORM_RFSTICK) || (defined SILABS_PLATFORM_LCDBB))
BIT s;
//Disable Global interrupt
EA = 0;
switch(biPbNum)
{
case 1:
s = PB1;
break;
case 2:
s = PB2;
break;
case 3:
s = PB3;
break;
case 4:
s = PB4;
break;
default:
s = 1;
break;
}
//Enable Global interrupt
EA = 1;
//return with the value of the button
return s;
#else
BIT s;
//check whether the selected button was pressed or not
switch (biPbNum)
{
case 1:
//Disable Global interrupt
EA = 0;
//latch P2.0 to '1'
LED1 = 1;
#if (defined SILABS_MCU_DC_EMIF_F930)
//Discharge capacitor on Vref pin
mCio_WaitIOSteadyState_long;
#endif
//set Px.x to input
#if ((defined SILABS_MCU_DC_EMIF_F930) || (defined SILABS_PLATFORM_WMB))
P0MDOUT &= (~M_LED1);
#else
P2MDOUT &= (~M_LED1);
#endif
#if (defined SILABS_MCU_DC_EMIF_F930)
//Wait pin to be stabilized on EMIF F930
//HW contains delay due to capacitor on Vref pin
//(~10k pull-up resistor required)
mCio_WaitIOSteadyState_long;
#else
//Wait pin to be stabilized
mCio_WaitIOSteadyState;
#endif
//Store input value
s = LED1;
// if (P0 & M_LED1)
// s = 1;
// else
// s = 0;
//set P2.0 to output
#if ((defined SILABS_MCU_DC_EMIF_F930) || (defined SILABS_PLATFORM_WMB))
P0MDOUT |= M_LED1;
#else
P2MDOUT |= M_LED1;
#endif
//restore LED1
if ((bCio_IoPortState & M_LED1) == 0)
vCio_SetLed(1);
else
vCio_ClearLed(1);
//Enable Global interrupt
EA = 1;
//return with the value of the button
break;
#if !(defined SILABS_PLATFORM_WMB912)
case 2:
//Disable Global interrupt
EA = 0;
//latch P2.0 to '1'
LED2 = 1;
//set P2.0 to input
#if ((defined SILABS_MCU_DC_EMIF_F930) || (defined SILABS_PLATFORM_WMB))
P0MDOUT &= (~M_LED2);
#else
P2MDOUT &= (~M_LED2);
#endif
//Wait pin to be stabilized
mCio_WaitIOSteadyState;
//Store input value
s = LED2;
//set P2.0 to output
#if ((defined SILABS_MCU_DC_EMIF_F930) || (defined SILABS_PLATFORM_WMB))
P0MDOUT |= M_LED2;
#else
P2MDOUT |= M_LED2;
#endif
//restore LED2
if((bCio_IoPortState & M_LED2) == 0)
vCio_SetLed(2);
else
vCio_ClearLed(2);
//Enable Global interrupt
EA = 1;
//return with the value of the button
break;
case 3:
//Disable Global interrupt
EA = 0;
//latch P2.0 to '1'
LED3 = 1;
//set P2.0 to input
#if ((defined SILABS_MCU_DC_EMIF_F930) || (defined SILABS_PLATFORM_WMB))
P0MDOUT &= (~M_LED3);
#else
P2MDOUT &= (~M_LED3);
#endif
//Wait pin to be stabilized
mCio_WaitIOSteadyState;
//Store input value
s = LED3;
//set P2.0 to output
#if ((defined SILABS_MCU_DC_EMIF_F930) || (defined SILABS_PLATFORM_WMB))
P0MDOUT |= M_LED3;
#else
P2MDOUT |= M_LED3;
#endif
//restore LED3
if((bCio_IoPortState & M_LED3) == 0)
vCio_SetLed(3);
else
vCio_ClearLed(3);
//Enable Global interrupt
EA = 1;
//return with the value of the button
break;
case 4:
//Disable Global interrupt
EA = 0;
//latch P2.0 to '1'
LED4 = 1;
//set P2.0 to input
#if ((defined SILABS_MCU_DC_EMIF_F930) || (defined SILABS_PLATFORM_WMB))
P0MDOUT &= (~M_LED4);
#else
P2MDOUT &= (~M_LED4);
#endif
//Wait pin to be stabilized
mCio_WaitIOSteadyState;
//Store input value
s = LED4;
//set P2.0 to output
#if ((defined SILABS_MCU_DC_EMIF_F930) || (defined SILABS_PLATFORM_WMB))
P0MDOUT |= M_LED4;
#else
P2MDOUT |= M_LED4;
#endif
//restore LED4
if((bCio_IoPortState & M_LED4) == 0)
vCio_SetLed(4);
else
vCio_ClearLed(4);
//Enable Global interrupt
EA = 1;
//return with the value of the button
break;
#endif //#if !(defined SILABS_PLATFORM_WMB912)
default:
s = 1;
break;
}
return s;
#endif
}
spino_code/silabs_code/Si446x_CustomPacketTX/src/drivers/control_IO.h 0 → 100644
View file @ 083b3926
/*! @file control_IO.h
* @brief This file is the interface file for IO control routines.
*
* @b COPYRIGHT
* @n Silicon Laboratories Confidential
* @n Copyright 2012 Silicon Laboratories, Inc.
* @n http://www.silabs.com
*/
#ifndef CONTROL_IO_H
#define CONTROL_IO_H
/*------------------------------------------------------------------------*/
/* Function prototypes */
/*------------------------------------------------------------------------*/
#if (defined SILABS_IO_WITH_EXTENDER)
/* Address length of extended IOs in IO extender */
#define bCio_IoExtAddrLength_c 0x02
/* Data length of extended IOs in IO extender */
#define bCio_IoExtCmdLength_c 0x01
#define bCio_IoExtRespLength_c 0x01
/* SMBus address of the IO extender */
#define IOEXT_SMBUS_ADDR 0x50
/* Address of extended IOs in IO extender */
typedef enum
{
IOEXT_ADDR_REQUEST_GPIO_STATE = (0x8000 | 0x00),
IOEXT_ADDR_CONTROL_SET_LED_STATE = (0x8000 | 0x01),
IOEXT_ADDR_CONTROL_CLEAR_LED_STATE = (0x8000 | 0x02),
IOEXT_ADDR_CONTROL_TOGGLE_LED_STATE = (0x8000 | 0x03),
} eUDPBaseboardAddressSpace;
/*!
* @brief This enumeration contains definitions of push-buttons for IO extender.
*/
typedef enum _eHmi_PbStates
{
eCio_PbNo_c = 0x00,
eCio_Pb1_c = 0x01,
eCio_Pb2_c = 0x02,
eCio_Pb3_c = 0x04,
eCio_Pb4_c = 0x08,
} eCio_PbStates;
/*!
* @brief This enumeration contains definitions of LEDs for IO extender.
*/
typedef enum _eHmi_LedStates
{
eCio_LedNo_c = 0x00,
eCio_Led1_c = 0x01,
eCio_Led2_c = 0x02,
eCio_Led3_c = 0x04,
eCio_Led4_c = 0x08,
} eCio_LedStates;
#endif /* #if (defined SILABS_IO_WITH_EXTENDER) */
void vCio_InitIO(void);
void vCio_SetLed(U8 biLedNum);
void vCio_ClearLed(U8 biLedNum);
void vCio_ToggleLed(U8 biLedNum);
BIT gCio_GetPB(U8 biPbNum);
#endif
spino_code/silabs_code/Si446x_CustomPacketTX/src/drivers/dog_glcd.c 0 → 100644
View file @ 083b3926
/*! @file dog_glcd.c
* @brief This file contains functions to control the DOG LCD.
*
* @b COPYRIGHT
* @n Silicon Laboratories Confidential
* @n Copyright 2012 Silicon Laboratories, Inc.
* @n http://www.silabs.com
*/
#include "..\bsp.h"
#ifdef SILABS_LCD_DOG_GLCD
/*------------------------------------------------------------------------*/
/* Local Macros & Definitions */
/*------------------------------------------------------------------------*/
#define LCD_BACKLIGHT_IS_USED
/*------------------------------------------------------------------------*/
/* Global variables */
/*------------------------------------------------------------------------*/
SEGMENT_VARIABLE(fUnderline, BIT, SEG_DATA) = FALSE;
SEGMENT_VARIABLE(fInvert, BIT, SEG_DATA) = FALSE;
SEGMENT_VARIABLE(bLcd_CurrentLine, U8, SEG_IDATA);
SEGMENT_VARIABLE(bLcd_CurrentChPos, U8, SEG_IDATA);
SEGMENT_VARIABLE(bLcd_CurrentPage, U8, SEG_IDATA);
SEGMENT_VARIABLE(bLcd_CurrentColumn, U8, SEG_IDATA);
#ifdef LCD_DRIVER_EXTENDED_SUPPORT
SEGMENT_VARIABLE(LCDBuffer[bLcd_NumOfColumnsMax_c * 3u], U8, SEG_XDATA);
#endif
/*------------------------------------------------------------------------*/
/* Function implementations */
/*------------------------------------------------------------------------*/
#if !(defined SOFTTIMER_H_)
/*!
* This function is used to wait about 2ms.
*
* @return None.
*
* @note The delay depends on the clock of the MCU.
*/
void vLcd_Delay2ms(void)
{
volatile SEGMENT_VARIABLE(Delay, U32, SEG_DATA);
for (Delay = 0u; Delay < 0x9FFF; Delay++) ;
}
#define LcdDelay(ms) { vLcd_Delay2ms(); vLcd_Delay2ms(); vLcd_Delay2ms(); vLcd_Delay2ms(); vLcd_Delay2ms(); }
#else
/**
* Wait about ms x 10ms.
*
* @param[in] ms Delay (x 10ms).
*
* @note Blocks code execution until elapses.
*
*****************************************************************************/
void LcdDelay(U8 ms)
{
/* Add Software Timer Channel no. 2 for LCD delay purposes */
SoftTimer_Add(ms, SOFTTIMER_CH2);
while (SoftTimer_Elapsed(SOFTTIMER_CH2) == FALSE) ;
}
#endif
/*!
* This function is used to initialize the LCD for 3.3V operation voltage and SPI comm.
*
* @return None.
*
* @note It can be called only 40ms after the VDD is stabilized.
*/
BIT vLcd_InitLcd(void)
{
vSpi_SetNsel(eSpi_Nsel_LCD);
LCD_A0 = FALSE;
#ifdef SPI_DRIVER_EXTENDED_SUPPORT
if (gSpi_SpiLcdDisabled == TRUE)
{
#if !(defined SPI_PERIPHERALS_ALWAYS_ENABLED)
mSpi_EnableSpiLcd();
#endif
}
#endif
LCD_A0 = FALSE;
/* perform reset ~10ms */
LcdDelay(1u);
vSpi_ClearNsel(eSpi_Nsel_LCD);
mSpi_ReadWriteSpiLcd(0x40); // display start line 0
mSpi_ReadWriteSpiLcd(0xA1); // ADC reverse
mSpi_ReadWriteSpiLcd(0xC0); // normal COM0~COM63
mSpi_ReadWriteSpiLcd(0xA6); // display normal
mSpi_ReadWriteSpiLcd(0xA2); // set bias 1/9 (Duty 1/65)
mSpi_ReadWriteSpiLcd(0x2F); // booster, regulator and follower on
mSpi_ReadWriteSpiLcd(0xF8); // set internal booster to 4x
mSpi_ReadWriteSpiLcd(0x00);
mSpi_ReadWriteSpiLcd(0x23); // contrast set
mSpi_ReadWriteSpiLcd(0x81);
mSpi_ReadWriteSpiLcd(0x1F);
mSpi_ReadWriteSpiLcd(0xAC); // no indicator
mSpi_ReadWriteSpiLcd(0x00);
vSpi_SetNsel(eSpi_Nsel_LCD);
vLcd_LcdOff();
vLcd_LcdClearDisplay();
vLcd_LcdOn();
return TRUE;
}
/*!
* This function is used to turn on the LCD screen.
*
* @return None.
*/
void vLcd_LcdOn(void)
{
/* disable global interrupts */
ENTER_CRITICAL_SECTION;
vSpi_ClearNsel(eSpi_Nsel_LCD);
mSpi_ReadWriteSpiLcd(0xAF);
vSpi_SetNsel(eSpi_Nsel_LCD);
/* enable global interrupts */
EXIT_CRITICAL_SECTION;
}
/*!
* This function is used to turn off the LCD
* screen (the DDRAM content will be kept).
*
* @return None.
*/
void vLcd_LcdOff(void)
{
/* disable global interrupts */
ENTER_CRITICAL_SECTION;
vSpi_ClearNsel(eSpi_Nsel_LCD);
mSpi_ReadWriteSpiLcd(0xAE);
vSpi_SetNsel(eSpi_Nsel_LCD);
/* enable global interrupts */
EXIT_CRITICAL_SECTION;
}
/*!
* This function is used to set the page address (0...7).
*
* @param[in] bi_DataIn Page address: the LCD is separated to 8x8 rows
* and 8 row is called as a page, page0 is the top 8 rows.
*
* @return None.
*/
void vLcd_LcdSetPage(U8 bi_DataIn)
{
/* disable global interrupts */
ENTER_CRITICAL_SECTION;
vSpi_ClearNsel(eSpi_Nsel_LCD);
mSpi_ReadWriteSpiLcd(0xB0 | bi_DataIn);
vSpi_SetNsel(eSpi_Nsel_LCD);
/* enable global interrupts */
EXIT_CRITICAL_SECTION;
}
/*!
* This function is used to set the column address (0...131).
*
* @param[in] bi_DataIn Column address.
*
* @return None.
*/
void vLcd_LcdSetColumn(U8 bi_DataIn)
{
/* disable global interrupts */
ENTER_CRITICAL_SECTION;
vSpi_ClearNsel(eSpi_Nsel_LCD);
mSpi_ReadWriteSpiLcd(0x10 | ((bi_DataIn & 0xF0) >> 4));
mSpi_ReadWriteSpiLcd(0x00 | (bi_DataIn & 0x0F));
vSpi_SetNsel(eSpi_Nsel_LCD);
/* enable global interrupts */
EXIT_CRITICAL_SECTION;
}
/*!
* This function is used to clear the display (the content of the DDRAM).
*
* @return None.
*/
void vLcd_LcdClearDisplay(void)
{
SEGMENT_VARIABLE(lPage, U8, SEG_DATA);
for(lPage = 1u; lPage <= bLcd_NumOfLinesMax_c; lPage++) {
vLcd_LcdClearLine(lPage);
}
}
/**
* Fills the display (the content of the DDRAM!)
*
* @note
*
*****************************************************************************/
void LcdFillDisplay(void)
{
SEGMENT_VARIABLE(lPage, U8, SEG_XDATA);
SEGMENT_VARIABLE(col, U8, SEG_XDATA);
ENTER_CRITICAL_SECTION;
for (lPage = 1u; lPage <= bLcd_NumOfLinesMax_c; lPage++)
{
/* select the page */
vLcd_LcdSetPage(lPage - 1u);
/* set to the first column */
vLcd_LcdSetColumn(0u);
/* set A0 to 1 -> access to the DDRAM */
LCD_A0 = TRUE;
vSpi_ClearNsel(eSpi_Nsel_LCD);
for (col = 0u; col < bLcd_NumOfColumnsMax_c; col++)
{
/* clear the selected column */
mSpi_ReadWriteSpiLcd(0xFF);
}
LCD_A0 = FALSE;
vSpi_SetNsel(eSpi_Nsel_LCD);
}
EXIT_CRITICAL_SECTION;
}
/*!
* This function is used to clear one line on the LCD.
*
* @param[in] bi_DataIn Line address.
*
* @return None.
*/
void vLcd_LcdClearLine(U8 bi_Line)
{
SEGMENT_VARIABLE(lColumn, U8, SEG_DATA);
if ((bi_Line < bLcd_NumOfLinesMin_c) || (bi_Line > bLcd_NumOfLinesMax_c)) {
return;
}
//select the page
vLcd_LcdSetPage(bi_Line - 1);
//set to the first column
vLcd_LcdSetColumn(0);
/* disable global interrupts */
ENTER_CRITICAL_SECTION;
//set A0 to 1 -> access to the DDRAM
LCD_A0 = 1;
vSpi_ClearNsel(eSpi_Nsel_LCD);
for (lColumn = 0u; lColumn < bLcd_NumOfColumnsMax_c; lColumn++) {
//clear the selected column
mSpi_ReadWriteSpiLcd(0x00);
}
LCD_A0 = 0;
vSpi_SetNsel(eSpi_Nsel_LCD);
/* enable global interrupts */
EXIT_CRITICAL_SECTION;
}
/*!
* This function is used to write one complete line on the LCD.
*
* @param[in] bi_Line Line address.
* @param[in] pbi_Text Pointer to the text (char array).
*
* @return None.
*
* @note If the line is invalid, the function returns without any changes.
* @note The function doesn't set the bLcd_CurrentLine,
* bLcd_CurrentChPos variables.
*/
void vLcd_LcdWriteLine(U8 biLine, U8 * pbiText)
{
if ((biLine < bLcd_NumOfLinesMin_c) || (biLine > bLcd_NumOfLinesMax_c)) {
return;
}
vLcd_LcdClearLine(biLine);
bLcd_CurrentLine = biLine - 1u;
bLcd_CurrentColumn = 0u;
vLcd_LcdWrite(pbiText);
}
/**
* Sets the LCD text position.
*
* @param[in] line Line number.
*
* @param[in] ch_pos Character horizontal position.
*
* @return \b TRUE - operation was successful <br>
* \b FALSE - operation was ignored.
*
* @note
*
*****************************************************************************/
BIT gLcd_LcdSetCharCursor(U8 biLine, U8 biChPos)
{
/* set page address */
bLcd_CurrentLine = biLine;
vLcd_LcdSetPage(biLine);
/* set column address */
bLcd_CurrentColumn = biChPos * 6u;
vLcd_LcdSetColumn(bLcd_CurrentColumn);
return TRUE;
}
/**
* Write string to LCD at actual position.
*
* @param[in] pText String to be written.
*
* @note
*
*****************************************************************************/
void vLcd_LcdWrite(U8 * pbi_pText)
{
SEGMENT_VARIABLE(lTemp , U8, SEG_DATA);
SEGMENT_VARIABLE(lColumn, U8, SEG_DATA);
SEGMENT_VARIABLE(lChar , U8, SEG_DATA);
while (*pbi_pText)
{
/* Check Position */
if ((bLcd_CurrentColumn >= bLcd_NumOfColumnsMax_c) || \
(bLcd_CurrentLine >= bLcd_NumOfLinesMax_c)) {
bLcd_CurrentColumn = 0u;
if (++bLcd_CurrentLine >= bLcd_NumOfLinesMax_c) {
bLcd_CurrentLine = 0u;
}
}
gLcd_LcdSetCharCursor(bLcd_CurrentLine, bLcd_CurrentColumn / 6u);
if ((*pbi_pText > bLcd_Ascii5x7Max_c) || \
(*pbi_pText < bLcd_Ascii5x7Min_c)) {
lTemp = ' ' - bLcd_Ascii5x7Min_c;
} else {
lTemp = *pbi_pText - bLcd_Ascii5x7Min_c;
}
pbi_pText++;
/* write character */
LCD_A0 = TRUE; /* set A0 to 1 -> access to the DDRAM */
vSpi_ClearNsel(eSpi_Nsel_LCD);
for (lColumn = 0u; lColumn < 5u; lColumn++)
{
lChar = ascii_table5x7[lTemp][lColumn];
if (TRUE == fUnderline) { lChar |= 0x80; }
if (TRUE == fInvert) { lChar = ~lChar; }
mSpi_ReadWriteSpiLcd(lChar);
}
/* space between the characters */
lChar = 0x00;
if (TRUE == fUnderline) { lChar |= 0x80; }
if (TRUE == fInvert) { lChar = ~lChar; }
mSpi_ReadWriteSpiLcd(lChar);
LCD_A0 = FALSE;
vSpi_SetNsel(eSpi_Nsel_LCD);
/* Increment LCD Column position */
bLcd_CurrentColumn += 6u;
}
}
/**
* Write string to the center of the given line.
*
* @param[in] line Line number.
*
* @param[in] pText String to be written.
*
* @note
*
*****************************************************************************/
void vLcd_LcdWriteLineCenter(U8 bi_line, U8 * pbi_Text)
{
SEGMENT_VARIABLE(lIdx, U8, SEG_DATA) = 0u;
if ((bi_line < bLcd_NumOfLinesMin_c) || (bi_line > bLcd_NumOfLinesMax_c))
{
return;
}
/* Clear actual line */
vLcd_LcdClearLine(bi_line);
/* Count characters */
while (*(pbi_Text + lIdx))
{
lIdx++;
}
if (lIdx < bLcd_NumOfCharsMax_c)
{
//bLcd_CurrentColumn = ((bLcd_NumOfCharsMax_c - lIdx) / 2u) * 6u;
bLcd_CurrentColumn = ((bLcd_NumOfCharsMax_c - lIdx) * 6u) / 2u;
}
else
{
bLcd_CurrentColumn = 0u;
}
bLcd_CurrentLine = bi_line - 1u;
vLcd_LcdWrite(pbi_Text);
}
/**
* Turns on Underline during text write on LCD.
*
* @note
*
*****************************************************************************/
void vLcd_LcdSetUnderline()
{
fUnderline = TRUE;
}
/**
* Turns off Underline during text write on LCD.
*
* @note
*
*****************************************************************************/
void vLcd_LcdClearUnderline()
{
fUnderline = FALSE;
}
/**
* Sets invert attribute when writing text to LCD.
*
* @note
*
*****************************************************************************/
void vLcd_LcdSetInvert()
{
fInvert = TRUE;
}
/**
* Clears invert attribute when writing text to LCD.
*
* @note
*
*****************************************************************************/
void vLcd_LcdClearInvert()
{
fInvert = FALSE;
}
/*!
* This function is used to set the character position.
*
* @param[in] bi_Page Number of the pages (1...8) the LCD is divided to
* 8 pages. Page1 is the top page.
* @param[in] bi_Column Number of start column. Column1 is the left one.
*
* @return True if operation is successfull.
*
* @note If the position is invalid, the function returns without changing the
* registers.
* @note The function sets the bLcd_CurrentLine, bLcd_CurrentChPos variables.
*/
U8 bLcd_LcdSetPictureCursor(U8 bi_Page, U8 bi_Column)
{
//check whether the input parameters are correct
if ( ((bi_Page < bLcd_NumOfLinesMin_c) || \
(bi_Page > bLcd_NumOfLinesMax_c)) || \
((bi_Column < bLcd_NumOfColumnsMin_c) || \
(bi_Column > bLcd_NumOfColumnsMax_c)) ) {
return FALSE;
}
//set page address
vLcd_LcdSetPage(bi_Page-1);
//set column address
vLcd_LcdSetColumn( bi_Column-1 );
bLcd_CurrentPage = bi_Page;
bLcd_CurrentColumn = bi_Column;
return TRUE;
}
/*!
* This function is used to draw a picture on the LCD screen.
*
* @param[in] pi_Picture The address of the picture, the picture must be stored
* in the FLASH.
*
* @return None.
*
* @note bLcd_LcdSetPictureCursor(uint8 page, uint8 column) function has to be
* called before calling this function.
* @note The function sets the bLcd_CurrentPage and bLcd_CurrentColumn variable.
*/
void vLcd_LcdDrawPicture(const U8 * pi_Picture)
{
SEGMENT_VARIABLE(pages, U8, SEG_DATA);
SEGMENT_VARIABLE(page, U8, SEG_DATA);
SEGMENT_VARIABLE(col, U8, SEG_DATA);
SEGMENT_VARIABLE(ii, U8, SEG_DATA);
SEGMENT_VARIABLE(jj, U16, SEG_DATA);
// checks whether there are enough column for the picture or not
col = ((bLcd_NumOfColumnsMax_c - bLcd_CurrentColumn + 1) < \
pi_Picture[bLcd_PictureColumnNum_c]) ? \
(bLcd_NumOfColumnsMax_c - bLcd_CurrentColumn + 1) : \
pi_Picture[bLcd_PictureColumnNum_c];
// check whether there are enough pages for the picture or not
page = ((bLcd_NumOfLinesMax_c - bLcd_CurrentPage + 1) < \
pi_Picture[bLcd_PicturePageNum_c]) ? \
(bLcd_NumOfLinesMax_c - bLcd_CurrentPage + 1) : \
pi_Picture[bLcd_PicturePageNum_c];
// draw the picture
for (pages = 0u; pages < page; pages++) {
ENTER_CRITICAL_SECTION; // disable global interrupts
LCD_A0 = 1; //set A0 to 1 -> access to the DDRAM
vSpi_ClearNsel(eSpi_Nsel_LCD);
jj = bLcd_PictureAddressOffset_c + pages;
for (ii = 0u; ii < col; ii++) {
// write column data
mSpi_ReadWriteSpiLcd(pi_Picture[jj]);
jj += pi_Picture[bLcd_PicturePageNum_c];
}
LCD_A0 = 0;
vSpi_SetNsel(eSpi_Nsel_LCD);
EXIT_CRITICAL_SECTION; // enable global interrupts
//set next page
bLcd_LcdSetPictureCursor(++bLcd_CurrentPage, bLcd_CurrentColumn);
}
}
#ifdef LCD_DRIVER_EXTENDED_SUPPORT
void vLcd_LcdDrawVerticalLine(U8 Y1, U8 Y2, U8 X, U8 clr)
{
SEGMENT_VARIABLE(lTmp, U8, SEG_DATA) = 0u;
if (Y1 > Y2) {
return;
}
while (((Y1/8u) >= lTmp) && (clr)) {
bLcd_LcdSetPictureCursor(++lTmp, X + 1u);
/* Draw line within the same Page */
LCD_A0 = 1; //set A0 to 1 -> access to the DDRAM
LCD_NSEL = 0;
mSpi_ReadWriteSpiLcd(0x00);
LCD_A0 = 0; //set A0 to 1 -> access to the DDRAM
LCD_NSEL = 1;
}
do {
if ((Y2/8u) > (Y1/8u)) {
lTmp = (Y1/8u + 1u) * 8u - 1u;
} else {
lTmp = Y2;
}
bLcd_LcdSetPictureCursor((Y1/8u) + 1u, X + 1u);
/* Draw line within the same Page */
LCD_A0 = 1; //set A0 to 1 -> access to the DDRAM
LCD_NSEL = 0;
mSpi_ReadWriteSpiLcd((0xFF << (Y1%8u)) & (0xFF >> (7u - (lTmp%8u))));
LCD_A0 = 0; //set A0 to 1 -> access to the DDRAM
LCD_NSEL = 1;
if ((Y2/8u) == (Y1/8u)) {
return;
}
Y1 = (Y1/8u + 1u) * 8u;
} while(TRUE);
}
void vLcd_DrawClearLine(U8 line, U8 column)
{
SEGMENT_VARIABLE(ii, U16, SEG_DATA);
if (line >= (sizeof(LCDBuffer) / bLcd_NumOfColumnsMax_c)) {
return;
}
for (ii = (line * bLcd_NumOfColumnsMax_c) + column; \
ii < ((line + 1) * bLcd_NumOfColumnsMax_c); ii++) {
LCDBuffer[ii] = 0x00;
}
}
void vLcd_DrawText(U8 line, U8 col, U8 * pStr)
{
SEGMENT_VARIABLE(ii, U8, SEG_DATA);
SEGMENT_VARIABLE(lTemp, U8, SEG_DATA);
while (*pStr) {
/* Check Position */
if ((col >= bLcd_NumOfColumnsMax_c) || \
(line >= (sizeof(LCDBuffer) / bLcd_NumOfColumnsMax_c))) {
bLcd_CurrentColumn = 0u;
if (++line >= (sizeof(LCDBuffer) / bLcd_NumOfColumnsMax_c)) {
line = 0u;
}
}
if ((*pStr > bLcd_Ascii5x7Max_c) || \
(*pStr < bLcd_Ascii5x7Min_c)) {
lTemp = ' ' - bLcd_Ascii5x7Min_c;
} else {
lTemp = *pStr - bLcd_Ascii5x7Min_c;
}
pStr++;
for (ii = 0u; ii < 5u; ii++) {
LCDBuffer[(line * bLcd_NumOfColumnsMax_c) + col++] = \
ascii_table5x7[lTemp][ii];
}
col++;
}
}
void vLcd_DrawTextCenter(U8 line, U8 * pStr)
{
SEGMENT_VARIABLE(lCnt, U8, SEG_DATA) = 0u;
while (*(pStr + lCnt)) lCnt++;
if (lCnt > 22u)
return;
vLcd_DrawText(line, (bLcd_NumOfColumnsMax_c - (lCnt * 6u)) / 2u, pStr);
}
BIT gLcd_DrawMoveArea(U8 columnStart, U8 columnEnd, U8 dir)
{
SEGMENT_VARIABLE(lCnt, U16, SEG_DATA);
static SEGMENT_VARIABLE(lRow, U8, SEG_DATA) = 0u;
static SEGMENT_VARIABLE(lInvoke, U8, SEG_DATA) = 0u;
if (++lInvoke > LCD_INVOKE_COUNT) {
lInvoke = 0u;
if (dir) {
for (lCnt = columnStart; lCnt < sizeof(LCDBuffer); lCnt++) {
if (((lCnt % bLcd_NumOfColumnsMax_c) < columnStart) || \
((lCnt % bLcd_NumOfColumnsMax_c) > columnEnd)) {
continue;
}
if ((lCnt >= bLcd_NumOfColumnsMax_c) && (LCDBuffer[lCnt] & 0x01)) {
LCDBuffer[lCnt - bLcd_NumOfColumnsMax_c] |= 0x80;
}
LCDBuffer[lCnt] >>= 1u;
}
} else {
for (lCnt = sizeof(LCDBuffer); lCnt > columnStart; lCnt--) {
if ((((lCnt - 1u) % bLcd_NumOfColumnsMax_c) < columnStart) || \
(((lCnt - 1u) % bLcd_NumOfColumnsMax_c) > columnEnd)) {
continue;
}
if (((lCnt - 1u) < (sizeof(LCDBuffer) - bLcd_NumOfColumnsMax_c)) && \
(LCDBuffer[(lCnt - 1u)] & 0x80)) {
LCDBuffer[(lCnt - 1u) + bLcd_NumOfColumnsMax_c] |= 0x01;
}
LCDBuffer[(lCnt - 1u)] <<= 1u;
}
}
if (++lRow >= 8u) {
lRow = 0u;
return TRUE;
}
}
return FALSE;
}
BIT gLcd_DrawInsertLine(U8 column, U8 dir, U8 * pStr)
{
SEGMENT_VARIABLE(lCnt, U8, SEG_DATA) = 0u;
static SEGMENT_VARIABLE(lState, U8, SEG_DATA) = 0u;
switch (lState) {
case 0u:
while (*(pStr + lCnt)) lCnt++;
if (lCnt > (bLcd_NumOfColumnsMax_c - column) / 6u) {
lState = 0u;
return TRUE;
}
lState++;
break;
case 1u:
if (gLcd_DrawMoveArea(column, bLcd_NumOfColumnsMax_c, dir) == TRUE) {
lState++;
}
break;
case 2u:
vLcd_DrawText((dir) ? \
((sizeof(LCDBuffer) / bLcd_NumOfColumnsMax_c) - 1u) : 0u, column, pStr);
lState = 0u;
return TRUE;
break;
default:
lState = 0u;
break;
}
return FALSE;
}
void vLcd_DrawBuffer(void)
{
SEGMENT_VARIABLE(ii, U16, SEG_DATA);
for (ii = 0u; ii < sizeof(LCDBuffer); ii++) {
if ((ii % bLcd_NumOfColumnsMax_c) == 0u) {
LCD_A0 = 0;
LCD_NSEL = 1;
bLcd_LcdSetPictureCursor(bLcd_NumOfLinesMin_c + \
(ii / bLcd_NumOfColumnsMax_c), bLcd_NumOfColumnsMin_c);
LCD_A0 = 1; //set A0 to 1 -> access to the DDRAM
LCD_NSEL = 0;
}
mSpi_ReadWriteSpiLcd(LCDBuffer[ii]);
}
LCD_A0 = 0;
LCD_NSEL = 1;
}
U8 *pLcd_DrawGetBuffer()
{
return LCDBuffer;
}
#endif
#endif
spino_code/silabs_code/Si446x_CustomPacketTX/src/drivers/dog_glcd.h 0 → 100644
View file @ 083b3926
/*! @file dog_glcd.h
* @brief This file is the interface file for LCD routines.
*
* @b COPYRIGHT
* @n Silicon Laboratories Confidential
* @n Copyright 2012 Silicon Laboratories, Inc.
* @n http://www.silabs.com
*/
#ifndef DOG_GLCD_H
#define DOG_GLCD_H
/*------------------------------------------------------------------------*/
/* Global definitions */
/*------------------------------------------------------------------------*/
#define bLcd_NumOfLinesMin_c (1u)
#define bLcd_NumOfLinesMax_c (4u)
#define bLcd_NumOfCharsMin_c (1u)
#define bLcd_NumOfCharsMax_c (22u)
#define bLcd_NumOfColumnsMin_c (1u)
#define bLcd_NumOfColumnsMax_c (132u)
#define bLcd_PicturePageNum_c (0u)
#define bLcd_PictureColumnNum_c (1u)
#define bLcd_PictureAddressOffset_c (2u)
#define bLcd_Line1_c (1u)
#define bLcd_Line2_c (2u)
#define bLcd_Line3_c (3u)
#define bLcd_Line4_c (4u)
#define bLcd_Ascii5x7Min_c (0x20)
#define bLcd_Ascii5x7Max_c (0x82)
#ifdef LCD_DRIVER_EXTENDED_SUPPORT
#define LCD_INVOKE_COUNT (1u)
#endif
#if (defined SILABS_MCU_DC_EMIF_F930) || (defined SILABS_PLATFORM_WMB)
#define mSpi_ReadWriteSpiLcd(biDataIn) bSpi_ReadWriteSpi0(biDataIn)
#define mSpi_EnableSpiLcd(biDataIn) vSpi_EnableSpi0()
#define gSpi_SpiLcdDisabled gSpi_Spi0Disabled
#else
#define mSpi_ReadWriteSpiLcd(biDataIn) bSpi_ReadWriteSpi1(biDataIn)
#define mSpi_EnableSpiLcd(biDataIn) vSpi_EnableSpi1()
#define gSpi_SpiLcdDisabled gSpi_Spi1Disabled
#endif
/*------------------------------------------------------------------------*/
/* External variables */
/*------------------------------------------------------------------------*/
extern SEGMENT_VARIABLE(abLcd_LcdData[bLcd_NumOfCharsMax_c + 1], U8, SEG_XDATA);
/*------------------------------------------------------------------------*/
/* Function prototypes */
/*------------------------------------------------------------------------*/
BIT vLcd_InitLcd(void);
void vLcd_LcdOn(void);
void vLcd_LcdOff(void);
void vLcd_LcdSetPage(U8 bi_DataIn);
void vLcd_LcdSetColumn(U8 bi_DataIn);
void vLcd_LcdClearDisplay(void);
void LcdFillDisplay(void);
void vLcd_LcdClearLine(U8 bi_Line);
void vLcd_LcdWriteLine(U8 bi_Line, U8 * pbi_Text);
U8 bLcd_LcdSetPictureCursor(U8 page, U8 bi_Column);
void vLcd_LcdDrawPicture(const U8 * pi_Picture);
BIT gLcd_LcdSetCharCursor(U8 biLine, U8 biChPos);
void vLcd_LcdWrite(U8 * pbi_pText);
void vLcd_LcdWriteLineCenter(U8 bi_line, U8 * pbi_Text);
void vLcd_LcdSetUnderline();
void vLcd_LcdClearUnderline();
void vLcd_LcdSetInvert();
void vLcd_LcdClearInvert();
#ifdef LCD_DRIVER_EXTENDED_SUPPORT
void vLcd_LcdDrawVerticalLine(U8 Y1, U8 Y2, U8 X, U8 clr);
void vLcd_DrawClearLine(U8 line, U8 column);
void vLcd_DrawText(U8 line, U8 col, U8 * pStr);
void vLcd_DrawTextCenter(U8 line, U8 * pStr);
BIT gLcd_DrawMoveArea(U8 columnStart, U8 columnEnd, U8 dir);
BIT gLcd_DrawInsertLine(U8 column, U8 dir, U8 * pStr);
void vLcd_DrawBuffer(void);
U8 *pLcd_DrawGetBuffer(void);
#else
#define vLcd_DrawClearLine(line, column) do \
{ vLcd_LcdClearLine((line) + 1u); } while (0)
#define vLcd_DrawText(line, col, pStr) do \
{ gLcd_LcdSetCharCursor(line, (col) / 6u); \
vLcd_LcdWrite(pStr); } while(0)
#define vLcd_DrawTextCenter(line, pStr) do \
{ vLcd_LcdWriteLineCenter((line) + 1u, pStr); } while(0)
#define gLcd_DrawInsertLine(column, dir, pStr) TRUE // TODO
#define gLcd_DrawMoveArea(columnStart, columnEnd, dir) TRUE // TODO
#define vLcd_DrawBuffer() // TODO
#endif
#ifdef SI4313
#define LCD_MIN_LINE (1)
#define LCD_MAX_LINE (4)
#define LCD_MIN_CHAR (1)
#define LCD_MAX_CHAR (22)
#endif
#endif
spino_code/silabs_code/Si446x_CustomPacketTX/src/drivers/hmi.c 0 → 100644
View file @ 083b3926
/*! @file hmi.c
* @brief This file contains functions to manage behavior of basic human module interfaces (push-buttons, switches, LEDs).
*
* @b COPYRIGHT
* @n Silicon Laboratories Confidential
* @n Copyright 2012 Silicon Laboratories, Inc.
* @n http://www.silabs.com
*/
#include "..\bsp.h"
/*------------------------------------------------------------------------*/
/* Global variables */
/*------------------------------------------------------------------------*/
#ifdef SILABS_PLATFORM_COMPONENT_PB
SEGMENT_VARIABLE(rHmi_PbData, tHmi_PbData, SEG_XDATA) = { eHmi_PbStandBy_c, }; /**< Instance of push-button data structure */
SEGMENT_VARIABLE(aqHmi_PbStates[], eHmi_PbStates, SEG_XDATA)= {eHmi_PbNo_c, eHmi_Pb1_c, eHmi_Pb2_c, eHmi_Pb3_c, eHmi_Pb4_c}; /**< Array of instances of push-button definitions */
#endif
#ifdef SILABS_PLATFORM_COMPONENT_LED
SEGMENT_VARIABLE(arHmi_LedData[bHmi_NumOfLeds_c], tHmi_LedData, SEG_XDATA) = {{0,},}; /**< Array of instances of Led data structure */
#ifdef HMI_DRIVER_EXTENDED_SUPPORT
SEGMENT_VARIABLE(wHmi_LedMainCnt, U16, SEG_XDATA) = 0; /**< Main time counter of Led handler */
#endif
SEGMENT_VARIABLE(aqHmi_Leds[], eHmi_Leds, SEG_XDATA)= {eHmi_NoLed_c, eHmi_Led1_c, eHmi_Led2_c, eHmi_Led3_c, eHmi_Led4_c}; /**< Array of instances of Led definitions */
#endif
#ifdef SILABS_PLATFORM_COMPONENT_BUZZER
SEGMENT_VARIABLE(rHmi_BuzzData, tHmi_BuzzData, SEG_XDATA); /**< Instance of Buzzer data structure */
#ifdef HMI_DRIVER_EXTENDED_SUPPORT
SEGMENT_VARIABLE(wHmi_BuzzMainCnt, U16, SEG_XDATA) = 0; /**< Main time counter of Buzzer handler */
#endif
#endif
#ifdef SILABS_PLATFORM_COMPONENT_SWITCH
SEGMENT_VARIABLE(bHmi_SwStateHolder, U8, SEG_XDATA) = 0; /**< Holds the actual state of the switches */
#endif
/*------------------------------------------------------------------------*/
/* Function implementations */
/*------------------------------------------------------------------------*/
#ifdef SILABS_PLATFORM_COMPONENT_LED
/*!
* This function is used to initialize the Led handler.
*
* @return None.
*
* @note It has to be called from the initialization section.
*/
void vHmi_InitLedHandler(void)
{
/*! NOTE: Re-initialization of LED Handler supported by the extended HMI driver */
#ifdef HMI_DRIVER_EXTENDED_SUPPORT
SEGMENT_VARIABLE(bLedCnt, U8 , SEG_DATA);
for (bLedCnt = 1; bLedCnt <= bHmi_NumOfLeds_c; bLedCnt++)
{
arHmi_LedData[bLedCnt-1].gLedIsOn = FALSE;
arHmi_LedData[bLedCnt-1].qLedState = eHmi_LedOff_c;
arHmi_LedData[bLedCnt-1].wLedBlinkCnt = 0;
}
#endif
}
/*!
* This function is used to change state of selected Led.
*
* @param[in] qiLed Led to change its state.
* @param[in] qiLedState New state of qiLed.
*
* @return None.
*/
void vHmi_ChangeLedState(eHmi_Leds qiLed, eHmi_LedStates qiLedState)
{
arHmi_LedData[qiLed-1].qLedState = qiLedState;
}
#ifdef HMI_DRIVER_EXTENDED_SUPPORT
/*!
* This function is used to change state of all Leds.
*
* @param[in] qiLedState New state of all the Leds.
*
* @return None.
*/
void vHmi_ChangeAllLedState(eHmi_LedStates qiLedState)
{
SEGMENT_VARIABLE(bLedCnt, U8 , SEG_DATA);
for (bLedCnt = 1; bLedCnt <= bHmi_NumOfLeds_c; bLedCnt++)
{
arHmi_LedData[bLedCnt-1].qLedState = qiLedState;
}
}
/*!
* This function is used to force all Leds to off immediately.
*
* @return None.
*/
void vHmi_ClearAllLeds(void)
{
SEGMENT_VARIABLE(bLedCnt, U8 , SEG_DATA);
for (bLedCnt = 1; bLedCnt <= bHmi_NumOfLeds_c; bLedCnt++)
{
vCio_ClearLed(bLedCnt);
arHmi_LedData[bLedCnt-1].gLedIsOn = FALSE;
arHmi_LedData[bLedCnt-1].qLedState = eHmi_LedStdBy_c;
}
}
#endif
/*!
* This function is used to handle Led management.
*
* @return None.
*/
void vHmi_LedHandler(void)
{
#ifdef HMI_DRIVER_EXTENDED_SUPPORT
BIT bLedChngReq = FALSE;
#else
static
#endif
SEGMENT_VARIABLE(bLedCnt, U8 , SEG_DATA) = 0u;
#ifdef HMI_DRIVER_EXTENDED_SUPPORT
wHmi_LedMainCnt++;
for (bLedCnt = 1; bLedCnt <= bHmi_NumOfLeds_c; bLedCnt++)
#else
if (++bLedCnt > bHmi_NumOfLeds_c) bLedCnt = 1u;
#endif
{
switch (arHmi_LedData[bLedCnt-1].qLedState)
{
case eHmi_LedOff_c:
vCio_ClearLed(bLedCnt);
arHmi_LedData[bLedCnt-1].gLedIsOn = FALSE;
arHmi_LedData[bLedCnt-1].qLedState = eHmi_LedStdBy_c;
break;
case eHmi_LedOn_c:
vCio_SetLed(bLedCnt);
arHmi_LedData[bLedCnt-1].gLedIsOn = TRUE;
arHmi_LedData[bLedCnt-1].qLedState = eHmi_LedStdBy_c;
break;
case eHmi_LedStdBy_c:
break;
#ifdef HMI_DRIVER_EXTENDED_SUPPORT
case eHmi_LedToggle_c:
vCio_ToggleLed(bLedCnt);
arHmi_LedData[bLedCnt-1].gLedIsOn = \
!arHmi_LedData[bLedCnt-1].gLedIsOn;
arHmi_LedData[bLedCnt-1].qLedState = eHmi_LedStdBy_c;
break;
case eHmi_LedBlink2Hz_c:
if ((wHmi_LedMainCnt == wTmr_2HzCntMax_c) ||
(wHmi_LedMainCnt == wTmr_2HzCntMax_c + wTmr_1HzCntMax_c)
)
{
bLedChngReq = TRUE;
}
case eHmi_LedBlink1Hz_c:
if (wHmi_LedMainCnt == wTmr_1HzCntMax_c)
{
bLedChngReq = TRUE;
}
case eHmi_LedBlinkHalfHz_c:
if (wHmi_LedMainCnt == wTmr_0Hz5CntMax_c)
{
bLedChngReq = TRUE;
}
break;
#endif
case eHmi_LedBlinkOnce_c:
vCio_SetLed(bLedCnt);
arHmi_LedData[bLedCnt-1].gLedIsOn = TRUE;
arHmi_LedData[bLedCnt-1].wLedBlinkCnt = 0;
arHmi_LedData[bLedCnt-1].qLedState = eHmi_LedBlinkWait_c;
case eHmi_LedBlinkWait_c:
if ( arHmi_LedData[bLedCnt-1].wLedBlinkCnt++ > (wTmr_2HzCntMax_c / (2.0
#ifndef HMI_DRIVER_EXTENDED_SUPPORT
* 4u
#endif
)) )
{
arHmi_LedData[bLedCnt-1].qLedState = eHmi_LedOff_c;
}
break;
default:
break;
}
#ifdef HMI_DRIVER_EXTENDED_SUPPORT
if (bLedChngReq)
{
if (arHmi_LedData[bLedCnt-1].gLedIsOn)
{
vCio_ClearLed(bLedCnt);
arHmi_LedData[bLedCnt-1].gLedIsOn = FALSE;
}
else
{
vCio_SetLed(bLedCnt);
arHmi_LedData[bLedCnt-1].gLedIsOn = TRUE;
}
bLedChngReq = FALSE;
}
#endif
}
#ifdef HMI_DRIVER_EXTENDED_SUPPORT
if (wHmi_LedMainCnt == wTmr_0Hz5CntMax_c)
{
wHmi_LedMainCnt = 0;
}
#endif
}
#endif
#ifdef SILABS_PLATFORM_COMPONENT_PB
/*!
* This function is used to initialize push-button handler.
*
* @return None.
*
* @note It has to be called from the initialization section.
*/
void vHmi_InitPbHandler(void)
{
/*! NOTE: Re-initialization of LED Handler supported by the extended HMI driver */
#ifdef HMI_DRIVER_EXTENDED_SUPPORT
rHmi_PbData.qPbHandlerState = eHmi_PbStandBy_c;
rHmi_PbData.wPbPushTime = 0;
rHmi_PbData.bPbPushTrack = eHmi_PbNo_c;
rHmi_PbData.bPbPushTrackAct = eHmi_PbNo_c;
rHmi_PbData.bPbWaitTime = 0;
#endif
}
/*!
* This function is used to check if any of the push-buttons is pushed.
*
* @param[out] *boPbPushTrack Read value of pushed button.
* @param[out] *woPbPushTime Push time of pushed button.
*
* @return Pushed state of push-buttons.
*/
BIT gHmi_PbIsPushed(U8 *boPbPushTrack, U16 *woPbPushTime)
{
if (rHmi_PbData.qPbHandlerState == eHmi_PbPushed_c)
{
*boPbPushTrack = rHmi_PbData.bPbPushTrack;
*woPbPushTime = rHmi_PbData.wPbPushTime;
return TRUE;
}
else
{
*boPbPushTrack = eHmi_PbNo_c;
*woPbPushTime = 0;
return FALSE;
}
}
#ifdef HMI_DRIVER_EXTENDED_SUPPORT
/*!
* This function is used to check if there is unhandled push-buttons event.
*
* @return True if there is unhandled push-button event.
*/
BIT gHmi_IsPbUnHandled(void)
{
if (rHmi_PbData.bPbPushTrackLast > eHmi_PbNo_c)
{
return TRUE;
}
else
{
return FALSE;
}
}
/*!
* This function is used to read last pushed button(s), push track holder is erased if button(s) was already released.
*
* @param[out] *woPbPushTime Push time of pushed button.
* @return Push track holder of last pushed button(s).
*/
U8 bHmi_PbGetLastButton(U16 *woPbPushTime)
{
SEGMENT_VARIABLE(bPbPushTrackTemp, U8 , SEG_DATA) = rHmi_PbData.bPbPushTrackLast;
*woPbPushTime = rHmi_PbData.wPbPushTimeLast;
if (rHmi_PbData.bPbPushTrackLast > eHmi_PbNo_c)
{
rHmi_PbData.bPbPushTrackLast = eHmi_PbNo_c;
rHmi_PbData.wPbPushTimeLast = 0;
}
return bPbPushTrackTemp;
}
#endif
/*!
* This function is used to handle push-button management.
*
* @return None.
*/
void vHmi_PbHandler(void)
{
#ifdef HMI_DRIVER_EXTENDED_SUPPORT
static
#endif
SEGMENT_VARIABLE(bButtonCnt, U8 , SEG_DATA) = 0u;
SEGMENT_VARIABLE(bTemp, U8 , SEG_DATA);
#ifdef SILABS_PLATFORM_WMB
static SEGMENT_VARIABLE(lInvokeCnt, U8, SEG_XDATA) = 0u;
#endif
#ifdef HMI_DRIVER_EXTENDED_SUPPORT
if (rHmi_PbData.qPbHandlerState > eHmi_PbNoRun_c)
#endif
{
#ifdef SILABS_PLATFORM_WMB
if (++lInvokeCnt == 0u)
#endif
{
rHmi_PbData.bPbPushTrackAct = eHmi_PbNo_c;
for (bButtonCnt = 1; bButtonCnt <= bHmi_NumOfPbs_c; bButtonCnt++) // Store state of the buttons
{
bTemp = !gCio_GetPB(bButtonCnt);
rHmi_PbData.bPbPushTrackAct += bTemp<<(bButtonCnt-1);
}
}
switch (rHmi_PbData.qPbHandlerState)
{
case eHmi_PbStandByWaitAllReleased_c:
if (rHmi_PbData.bPbPushTrackAct == eHmi_PbNo_c)
{
rHmi_PbData.qPbHandlerState = eHmi_PbStandBy_c;
}
break;
case eHmi_PbStandBy_c:
if (rHmi_PbData.bPbPushTrackAct > eHmi_PbNo_c)
{
rHmi_PbData.qPbHandlerState = eHmi_PbStateChanged_c;
}
break;
case eHmi_PbStateChanged_c:
rHmi_PbData.wPbPushTime = 0;
rHmi_PbData.bPbPushTrack = rHmi_PbData.bPbPushTrackAct;
if (rHmi_PbData.bPbPushTrackAct == eHmi_PbNo_c)
{
rHmi_PbData.qPbHandlerState = eHmi_PbStandBy_c;
}
else
{
rHmi_PbData.qPbHandlerState = eHmi_PbDebounceWait_c;
}
break;
case eHmi_PbDebounceWait_c:
if (rHmi_PbData.bPbWaitTime++ > bHmi_PbDebounceWaitTime_c)
{
rHmi_PbData.bPbWaitTime = 0;
rHmi_PbData.wPbPushTime = 0;
rHmi_PbData.qPbHandlerState = eHmi_PbPushed_c;
}
break;
case eHmi_PbPushed_c:
/* If button released, or one released but more were pushed store the state*/
if (rHmi_PbData.bPbPushTrackAct < rHmi_PbData.bPbPushTrack)
{
rHmi_PbData.qPbHandlerState = eHmi_PbReleaseWait_c;
}
/* If one more button is pushed goto change state */
else if (rHmi_PbData.bPbPushTrackAct > rHmi_PbData.bPbPushTrack)
{
rHmi_PbData.qPbHandlerState = eHmi_PbStateChanged_c;
}
/* Increase counter if no change in button states */
else
{
rHmi_PbData.wPbPushTime++;
}
break;
case eHmi_PbReleaseWait_c:
if (rHmi_PbData.bPbWaitTime++ > bHmi_PbDebounceWaitTime_c)
{
rHmi_PbData.bPbWaitTime = 0;
rHmi_PbData.qPbHandlerState = eHmi_PbStandByWaitAllReleased_c;
rHmi_PbData.bPbPushTrackLast = rHmi_PbData.bPbPushTrack;
rHmi_PbData.wPbPushTimeLast = rHmi_PbData.wPbPushTime;
}
break;
}
}
}
#endif
#if ((defined SILABS_PLATFORM_COMPONENT_LED) && (defined SILABS_PLATFORM_COMPONENT_PB))
#ifdef HMI_DRIVER_EXTENDED_SUPPORT
/*!
* This function is used to show the actual state of the push-buttons on the Leds.
*
* @return None.
*/
void vHmi_ShowPbOnLeds(void)
{
SEGMENT_VARIABLE(boPbPushTrack, U8 , SEG_DATA);
SEGMENT_VARIABLE(woPbPushTime, U16 , SEG_DATA);
SEGMENT_VARIABLE(bPbLedCnt, U8 , SEG_DATA);
gHmi_PbIsPushed(&boPbPushTrack, &woPbPushTime);
for (bPbLedCnt = 1; bPbLedCnt <= 4; bPbLedCnt++)
{
if (boPbPushTrack & aqHmi_PbStates[bPbLedCnt])
{
vHmi_ChangeLedState(aqHmi_Leds[bPbLedCnt], eHmi_LedOn_c);
}
else
{
vHmi_ChangeLedState(aqHmi_Leds[bPbLedCnt], eHmi_LedOff_c);
}
}
}
#endif
#endif
#ifdef SILABS_PLATFORM_COMPONENT_SWITCH
/*!
* This function is used to handle switch state change.
*
* @return True if state of switches has changed.
*/
BIT gHmi_SwStateHandler(void)
{
SEGMENT_VARIABLE(bSwStateHolderAct, U8, SEG_DATA) = 0; /**< Holds the actual state of the switches */
bSwStateHolderAct |= (SW1_A) ? (eHmi_NoSw_c) : (eHmi_Sw1_A_c);
bSwStateHolderAct |= (SW1_B) ? (eHmi_NoSw_c) : (eHmi_Sw1_B_c);
bSwStateHolderAct |= (SW1_C) ? (eHmi_NoSw_c) : (eHmi_Sw1_C_c);
bSwStateHolderAct |= (SW1_D) ? (eHmi_NoSw_c) : (eHmi_Sw1_D_c);
if (bSwStateHolderAct == bHmi_SwStateHolder)
{
return FALSE;
}
else
{
bHmi_SwStateHolder = bSwStateHolderAct;
return TRUE;
}
}
U8 bHmi_GetSwState(void)
{
return bHmi_SwStateHolder;
}
#endif
#ifdef SILABS_PLATFORM_COMPONENT_BUZZER
/*!
* This function is used to initialize the buzzer operation.
*
* @return None.
*
* @note It has to be called from the initialization section.
*/
void vHmi_InitBuzzer(void)
{
// vPca_InitPcaTmr(bPca_PcaCps_000_c, FALSE, bPca_PwmClsel_01_c); //4kHz
// vPca_InitPcaTmr(bPca_PcaCps_000_c, FALSE, bPca_PwmClsel_00_c); //8kHz
// vPca_InitPcaTmr(bPca_PcaCps_000_c, FALSE, bPca_PwmClsel_10_c); //2kHz
vPca_InitPcaTmr(bPca_PcaCps_000_c, FALSE, bPca_PwmClsel_11_c); //1kHz
// mPca_EnablePcaTmrCofIt();
mPca_DisableAllInCpmN(0);
// mPca_EnablePwmN(0);
mPca_SelectAutoReloadReg();
// mPca_SetAutoReloadRegN(0, 0x0040); //90% @ 4kHz
// mPca_SetAutoReloadRegN(0, 0x0100); //50% @ 4kHz
mPca_SetAutoReloadRegN(0, 0x0400); //50% @ 1kHz
// mPca_SetAutoReloadRegN(0, 0x01BF); //10% @ 4kHz
mPca_EnablePcaTmr();
rHmi_BuzzData.gBuzzIsOn = FALSE;
rHmi_BuzzData.qBuzzState = eHmi_BuzzOff_c;
rHmi_BuzzData.wBuzzCnt = 0;
}
/*!
* This function is used to change the state the buzzer.
*
* @param[in] qiBuzzState New state of the buzzer.
*
* @return None.
*/
void vHmi_ChangeBuzzState(eHmi_BuzzStates qiBuzzState)
{
#ifdef HMI_DRIVER_EXTENDED_SUPPORT
if (rHmi_BuzzData.qBuzzNextState != qiBuzzState)
#endif
{
rHmi_BuzzData.qBuzzState = rHmi_BuzzData.qBuzzNextState = qiBuzzState;
}
}
/*!
* This function is used to handle buzzer management.
*
* @return None.
*/
void vHmi_BuzzHandler(void)
{
BIT bBuzzChngReq = FALSE;
#ifdef HMI_DRIVER_EXTENDED_SUPPORT
wHmi_BuzzMainCnt++;
#endif
switch (rHmi_BuzzData.qBuzzState)
{
case eHmi_BuzzOff_c:
mPca_DisablePwmN(0);
rHmi_BuzzData.gBuzzIsOn = FALSE;
rHmi_BuzzData.qBuzzState = eHmi_BuzzStdBy_c;
break;
#ifdef HMI_DRIVER_EXTENDED_SUPPORT
case eHmi_BuzzOn_c:
mPca_EnablePwmN(0);
rHmi_BuzzData.gBuzzIsOn = TRUE;
rHmi_BuzzData.qBuzzState = eHmi_BuzzStdBy_c;
break;
case eHmi_BuzzStdBy_c:
break;
case eHmi_Buzz2Hz_c:
if ((wHmi_BuzzMainCnt == wTmr_2HzCntMax_c) ||
(wHmi_BuzzMainCnt == wTmr_2HzCntMax_c + wTmr_1HzCntMax_c) ||
(wHmi_BuzzMainCnt == wTmr_2HzCntMax_c + wTmr_0Hz5CntMax_c) ||
(wHmi_BuzzMainCnt == wTmr_2HzCntMax_c + wTmr_0Hz5CntMax_c + wTmr_1HzCntMax_c)
)
{
rHmi_BuzzData.qBuzzState = eHmi_BuzzOnceAndCont_c;
}
case eHmi_Buzz1Hz_c:
if ((wHmi_BuzzMainCnt == wTmr_1HzCntMax_c) ||
(wHmi_BuzzMainCnt == wTmr_1HzCntMax_c + wTmr_0Hz5CntMax_c)
)
{
rHmi_BuzzData.qBuzzState = eHmi_BuzzOnceAndCont_c;
}
case eHmi_Buzz0Hz5_c:
if (wHmi_BuzzMainCnt == wTmr_0Hz5CntMax_c)
{
rHmi_BuzzData.qBuzzState = eHmi_BuzzOnceAndCont_c;
}
case eHmi_Buzz0Hz25_c:
if (wHmi_BuzzMainCnt == wTmr_0Hz25CntMax_c)
{
rHmi_BuzzData.qBuzzState = eHmi_BuzzOnceAndCont_c;
}
break;
case eHmi_BuzzOnceAndCont_c:
mPca_EnablePwmN(0);
mPca_SetAutoReloadRegN(0, 0x0100); //50% @ 4kHz
rHmi_BuzzData.gBuzzIsOn = TRUE;
rHmi_BuzzData.wBuzzCnt = 0;
rHmi_BuzzData.qBuzzState = eHmi_BuzzWait_c;
break;
#endif
case eHmi_BuzzOnce_c:
mPca_EnablePwmN(0);
//mPca_SetAutoReloadRegN(0, 0x0100); //50% @ 2kHz
mPca_SetAutoReloadRegN(0, 0x0400); //50% @ 1kHz
rHmi_BuzzData.gBuzzIsOn = TRUE;
rHmi_BuzzData.wBuzzCnt = 0;
rHmi_BuzzData.qBuzzNextState = eHmi_BuzzOff_c;
rHmi_BuzzData.qBuzzState = eHmi_BuzzWait_c;
case eHmi_BuzzWait_c:
if (rHmi_BuzzData.wBuzzCnt++ > (wTmr_8HzCntMax_c))
{
mPca_DisablePwmN(0);
rHmi_BuzzData.gBuzzIsOn = FALSE;
rHmi_BuzzData.qBuzzState = rHmi_BuzzData.qBuzzNextState;
}
break;
default:
break;
}
#ifdef HMI_DRIVER_EXTENDED_SUPPORT
if (wHmi_BuzzMainCnt == wTmr_0Hz25CntMax_c)
{
wHmi_BuzzMainCnt = 0;
}
#endif
}
#endif
spino_code/silabs_code/Si446x_CustomPacketTX/src/drivers/hmi.h 0 → 100644
View file @ 083b3926
/*! @file hmi.h
* @brief This file is the interface file for basic HMI functions.
*
* @b COPYRIGHT
* @n Silicon Laboratories Confidential
* @n Copyright 2012 Silicon Laboratories, Inc.
* @n http://www.silabs.com
*/
#ifndef HMI_H_
#define HMI_H_
/*------------------------------------------------------------------------*/
/* Global definitions */
/*------------------------------------------------------------------------*/
#ifdef SILABS_PLATFORM_COMPONENT_LED
/*!
* @brief This definition holds the maximum number of Leds.
*/
#define bHmi_NumOfLeds_c SILABS_PLATFORM_COMPONENT_LED
/*!
* @brief This definition holds the maximum of the main counter of the Leds.
*/
#define wHmi_LedMainCntMax_c wTim_HalfHzCntMax_c
#endif
#ifdef SILABS_PLATFORM_COMPONENT_PB
/*!
* @brief This definition holds the maximum number of switches.
*/
#define bHmi_NumOfPbs_c SILABS_PLATFORM_COMPONENT_PB
/*!
* @brief This definition holds steady-state wait time of push-buttons.
*/
#define bHmi_PbDebounceWaitTime_c 10
/*
* #define bHmi_PbMaxPushTrackFifo_c 10
*/
#endif
#ifdef SILABS_PLATFORM_COMPONENT_SWITCH
/*!
* @brief This definition holds the maximum number of switches.
*/
#define bHmi_NumOfSwitches_c SILABS_PLATFORM_COMPONENT_SWITCH
#endif
/*------------------------------------------------------------------------*/
/* Global structure & enumeration definitions */
/*------------------------------------------------------------------------*/
#ifdef SILABS_PLATFORM_COMPONENT_LED
/*!
* @brief This enumeration contains constant definitions for Leds.
*/
typedef enum _eHmi_Leds
{
eHmi_NoLed_c = 0x00, /**< No Led */
eHmi_Led1_c = 0x01, /**< Led1 */
eHmi_Led2_c = 0x02, /**< Led2 */
eHmi_Led3_c = 0x03, /**< Led3 */
eHmi_Led4_c = 0x04, /**< Led4 */
} eHmi_Leds;
/*!
* @brief This enumeration contains Led state definitions.
*/
typedef enum {
eHmi_LedOff_c = 0x00, /**< Led is in off state */
eHmi_LedStdBy_c = 0x01, /**< Led waits for state change */
eHmi_LedOn_c = 0x10, /**< Led is in on state */
eHmi_LedToggle_c ,
eHmi_LedBlink2Hz_c = 0x20, /**< Led blinks with 2Hz */
eHmi_LedBlink1Hz_c = 0x30, /**< Led blinks with 1Hz */
eHmi_LedBlinkHalfHz_c = 0x40, /**< Led blinks with 0.5Hz */
eHmi_LedBlinkOnce_c = 0x50, /**< Blinks led once */
eHmi_LedBlinkWait_c = 0x55, /**< Blinks led once */
} eHmi_LedStates;
/*!
* @brief This structure contains required data of a specific Led.
*/
typedef struct _tHmi_LedData
{
eHmi_LedStates qLedState; /**< Led state (on, off, blink) */
U16 wLedBlinkCnt; /**< Led blink counter */
U8 gLedIsOn; /**< Actual state of Led (lid or not) */
} tHmi_LedData;
#endif
#ifdef SILABS_PLATFORM_COMPONENT_PB
/*!
* @brief This enumeration contains states of push-button handler.
*/
typedef enum _eHmi_PbHandlerStates
{
eHmi_PbNoRun_c = 0x00, /**< Push-button handler not runs */
eHmi_PbStandBy_c = 0x10, /**< No button is pushed */
eHmi_PbStandByWaitAllReleased_c = 0x11, /**< Wait for release all buttons (if more were pushed) */
eHmi_PbStateChanged_c = 0x20, /**< Push-button state changed */
eHmi_PbDebounceWait_c = 0x25, /**< Push-button debounce state (push)*/
eHmi_PbPushed_c = 0x30, /**< Push-button pushed */
eHmi_PbReleaseWait_c = 0x40, /**< Push-button debounce state (release) */
} eHmi_PbHandlerStates;
/*!
* @brief This enumeration contains definitions of push-button push states.
*/
typedef enum {
eHmi_PbNo_c = 0x00,
eHmi_Pb1_c = 0x01,
eHmi_Pb2_c = 0x02,
eHmi_Pb3_c = 0x04,
eHmi_Pb4_c = 0x08,
} eHmi_PbStates;
/*!
* @brief This structure contains required data of the push-button handler.
*/
typedef struct _tHmi_PbData
{
eHmi_PbHandlerStates qPbHandlerState; /**< Push-button handler state */
U8 bPbPushTrack; /**< Push-button state */
U8 bPbPushTrackLast; /**< Push-button state of last pushed-released button*/
U8 bPbPushTrackAct; /**< Actual state of push-buttons */
U16 wPbPushTime; /**< Push-button state time holder */
U16 wPbPushTimeLast; /**< Push-button state time holder of last pushed-released button */
U8 bPbWaitTime; /**< Steady-state wait time holder */
} tHmi_PbData;
#endif
#ifdef SILABS_PLATFORM_COMPONENT_SWITCH
/*!
* @brief This enumeration contains constant definitions for switches.
*/
typedef enum _eHmi_Switches
{
eHmi_NoSw_c = 0x00, /**< No switch is set */
eHmi_Sw1_A_c = 0x01, /**< switch 1-A is set */
eHmi_Sw1_B_c = 0x02, /**< switch 1-B is set */
eHmi_Sw1_C_c = 0x04, /**< switch 1-C is set */
eHmi_Sw1_D_c = 0x08, /**< switch 1-D is set */
} eHmi_Switches;
#endif
#ifdef SILABS_PLATFORM_COMPONENT_BUZZER
/*!
* @brief This enumeration contains state definitions of the buzzer.
*/
typedef enum _eHmi_BuzzStates
{
eHmi_BuzzOff_c = 0x00, /**< Buzz is in off state */
eHmi_BuzzStdBy_c = 0x01, /**< Buzz waits for state change */
eHmi_BuzzOn_c = 0x10, /**< Buzz is in on state */
eHmi_Buzz2Hz_c = 0x20, /**< Buzz 2Hz */
eHmi_Buzz1Hz_c = 0x30, /**< Buzz 1Hz */
eHmi_Buzz0Hz5_c = 0x40, /**< Buzz 0.5Hz */
eHmi_Buzz0Hz25_c = 0x41, /**< Buzz 0.25Hz */
eHmi_BuzzOnce_c = 0x50, /**< Buzz once */
eHmi_BuzzOnceAndCont_c = 0x51, /**< Buzz once and continue buzzing*/
eHmi_BuzzWait_c = 0x55, /**< Waits for buzz once */
} eHmi_BuzzStates;
/*!
* @brief This structure contains required data of the Buzzer.
*/
typedef struct _tHmi_BuzzData
{
eHmi_BuzzStates qBuzzState; /**< Buzzer state (on, off, blink) */
eHmi_BuzzStates qBuzzNextState; /**< Buzzer next state (on, off, blink) */
U16 wBuzzCnt; /**< Buzzer counter */
U8 gBuzzIsOn; /**< Actual state of the buzzer (buzz or not) */
} tHmi_BuzzData;
#endif
/*------------------------------------------------------------------------*/
/* Function prototypes */
/*------------------------------------------------------------------------*/
#ifdef SILABS_PLATFORM_COMPONENT_LED
void vHmi_InitLedHandler(void);
void vHmi_ChangeLedState(eHmi_Leds qiLed, eHmi_LedStates qiLedState);
void vHmi_LedHandler(void);
#endif
#ifdef SILABS_PLATFORM_COMPONENT_PB
void vHmi_InitPbHandler(void);
BIT gHmi_PbIsPushed(U8 *boPbPushTrack, U16 *woPbPushTime);
U8 bHmi_PbGetLastButton(U16 *woPbPushTime);
void vHmi_PbHandler(void);
#endif
#ifdef SILABS_PLATFORM_COMPONENT_SWITCH
BIT gHmi_SwStateHandler(void);
U8 bHmi_GetSwState(void);
#endif
#ifdef SILABS_PLATFORM_COMPONENT_BUZZER
void vHmi_InitBuzzer(void);
void vHmi_ChangeBuzzState(eHmi_BuzzStates qiBuzzState);
void vHmi_BuzzHandler(void);
#endif
#ifdef HMI_DRIVER_EXTENDED_SUPPORT
#ifdef SILABS_PLATFORM_COMPONENT_LED
void vHmi_ChangeAllLedState(eHmi_LedStates qiLedState);
void vHmi_ClearAllLeds(void);
#endif
#ifdef SILABS_PLATFORM_COMPONENT_PB
BIT gHmi_IsPbUnHandled(void);
#endif
#if ((defined SILABS_PLATFORM_COMPONENT_LED) && (defined SILABS_PLATFORM_COMPONENT_PB))
void vHmi_ShowPbOnLeds(void);
#endif
#endif
#endif /* HMI_H_ */
spino_code/silabs_code/Si446x_CustomPacketTX/src/drivers/menu.c 0 → 100644
View file @ 083b3926
/*! @file menu.c
* @brief This file contains functions of the menu handler driver.
*
* @b COPYRIGHT
* @n Silicon Laboratories Confidential
* @n Copyright 2012 Silicon Laboratories, Inc.
* @n http://www.silabs.com
*/
#include "..\bsp.h"
/*------------------------------------------------------------------------*/
/* Global variables */
/*------------------------------------------------------------------------*/
/**< This instance of the structure holds information of menu states */
SEGMENT_VARIABLE(rMnu_MenuStateInfo, tMnu_MenuStateInfo, SEG_XDATA);
/*!
* @brief Pointer to an instance of the tMnu_MenuState structure, which is
* stored on the code space.
* @note It have to be implemented in the application menu files.
*/
SEGMENT_VARIABLE_SEGMENT_POINTER(parMnu_AppMenuState, tMnu_MenuState, \
SEG_CODE, SEG_XDATA);
/*------------------------------------------------------------------------*/
/* Function implementations */
/*------------------------------------------------------------------------*/
/*!
* This function is used to handle switch state change.
*
* @param[in] pariAppMenuState Pointer to the instance
* of the tMnu_MenuState structure.
*
* @return True if state of switches has changed.
*
* @note It has to be called from the initialization section.
*/
void vMnu_InitMenu(tMnu_MenuState *pariAppMenuState)
{
parMnu_AppMenuState = pariAppMenuState;
rMnu_MenuStateInfo.bMenuState = parMnu_AppMenuState[0].bMenuState;
rMnu_MenuStateInfo.bMenuNextState = parMnu_AppMenuState[0].bMenuState;
rMnu_MenuStateInfo.pMenuFunction = &(parMnu_AppMenuState[0].menuFunction);
}
/*!
* This function is used to manage menu states and
* the transitions from one state to an other.
*
* @return None.
*/
menuFuncRet_t vMnu_MenuHandler()
{
SEGMENT_VARIABLE(lFuncRet, menuFuncRet_t, SEG_DATA) = \
{ MENUCHANGE_NOCHANGE, FALSE };
if (rMnu_MenuStateInfo.pMenuFunction->pStateFunction) {
lFuncRet = rMnu_MenuStateInfo.pMenuFunction->pStateFunction();
}
return lFuncRet;
}
/*!
* This function is used to change the menu state.
*
* @param[in] biNewMenuState New menu state.
*
* @return None.
*/
void vMnu_MenuChangeState(U8 reqDir)
{
switch (reqDir) {
case MENUCHANGE_NEXT:
if (!sMenuIsLastElement(rMnu_MenuStateInfo.bMenuState)) {
rMnu_MenuStateInfo.bMenuState = \
sMenuNext(rMnu_MenuStateInfo.bMenuState);
rMnu_MenuStateInfo.pMenuFunction = \
sMenuGetStateFunction(rMnu_MenuStateInfo.bMenuState);
}
break;
case MENUCHANGE_BACK:
if (!sMenuIsFirstElement(rMnu_MenuStateInfo.bMenuState)) {
rMnu_MenuStateInfo.bMenuState = \
sMenuBack(rMnu_MenuStateInfo.bMenuState);
rMnu_MenuStateInfo.pMenuFunction = \
sMenuGetStateFunction(rMnu_MenuStateInfo.bMenuState);
}
break;
default:
break;
}
}
/*!
* This function is used to clear handler function of a menu state.
* It can be used if handler required only for first time and all the
* transitions can be managed by the menu handler.
*
* @return None.
*/
void vMnu_DeleteMenuFunction(void)
{
rMnu_MenuStateInfo.pMenuFunction->pStateFunction = NULL;
}
spino_code/silabs_code/Si446x_CustomPacketTX/src/drivers/menu.h 0 → 100644
View file @ 083b3926
/*! @file menu.h
* @brief Header file of menu handler driver.
*
* @b COPYRIGHT
* @n Silicon Laboratories Confidential
* @n Copyright 2012 Silicon Laboratories, Inc.
* @n http://www.silabs.com
*/
#ifndef MENU_H_
#define MENU_H_
/*------------------------------------------------------------------------*/
/* Global definitions */
/*------------------------------------------------------------------------*/
/*------------------------------------------------------------------------*/
/* Global structure & enumeration definitions */
/*------------------------------------------------------------------------*/
typedef enum {
MENUCHANGE_NOCHANGE,
MENUCHANGE_NEXT,
MENUCHANGE_BACK,
} menuChgReq_e;
typedef struct {
U8 chgReq;
U8 rfsReq;
U8 btnType;
} menuFuncRet_t;
typedef struct {
menuFuncRet_t (*pStateFunction)(void); /**< Handler function of the menu state */
U8 *(*pOutputFunction)(void); /**< Display function of the menu state */
} menuFunction_t;
/*!
* @brief This structure contains information of the menu state.
*/
typedef struct _tMnu_MenuState
{
U8 bMenuState; /**< Actual menu state */
U8 bMenuNextState; /**< Next menu state */
menuFunction_t menuFunction;
U8 menuHidden;
} tMnu_MenuState;
/*!
* @brief This structure contains operation
* information of the current and next menu state.
*/
typedef struct _tMnu_MenuStateInfo
{
U8 bMenuState; /**< Actual menu state */
U8 bMenuNextState; /**< Next menu state caused by input */
menuFunction_t *pMenuFunction; /**< Pointer to handler functions */
} tMnu_MenuStateInfo;
/*------------------------------------------------------------------------*/
/* Public variables */
/*------------------------------------------------------------------------*/
extern SEGMENT_VARIABLE(rMnu_MenuStateInfo, tMnu_MenuStateInfo, SEG_XDATA);
/*------------------------------------------------------------------------*/
/* Function prototypes */
/*------------------------------------------------------------------------*/
void vMnu_InitMenu(tMnu_MenuState *pariAppMenuState);
void vMnu_MenuChangeState(U8 biNewMenuState);
void vMnu_DeleteMenuFunction(void);
U8 bMnu_GetMenuState(void);
menuFuncRet_t vMnu_MenuHandler();
#endif /* MENU_H_ */
spino_code/silabs_code/Si446x_CustomPacketTX/src/drivers/pca.c 0 → 100644
View file @ 083b3926
/*! @file pca.c
* @brief This file contains the interface functions of the programmable counter array (PCA).
*
* @b COPYRIGHT
* @n Silicon Laboratories Confidential
* @n Copyright 2012 Silicon Laboratories, Inc.
* @n http://www.silabs.com
*/
#include "..\bsp.h"
#if !( (defined SILABS_MCU_F930) || (defined SILABS_MCU_F912) )
#error Check implementation for given MCU!
#endif
/*------------------------------------------------------------------------*/
/* Global variables */
/*------------------------------------------------------------------------*/
/*------------------------------------------------------------------------*/
/* Function implementations */
/*------------------------------------------------------------------------*/
/*!
* This function is used to start Timer 2 in the specified mode.
*
* @param[in] biPulseSelect Selects time-base source of PCA counter (use predefined constants: bPca_PcaCps_000_c etc.)
* @param[in] biPcaTmrItEnable Enables PCA timer IT if TRUE, disables it if FALSE
* @param[in] biCycleLengthSelect PWM-mode cycle length select (use predefined constants: bPca_PwmClsel_00_c etc.)
*
* @return None.
*/
void vPca_InitPcaTmr(U8 biPulseSelect, U8 biPcaTmrItEnable, U8 biCycleLengthSelect)
{
//setup timer
PCA0MD = M_CIDL | (biPulseSelect & M_CPS);
PCA0PWM = M_ARSEL | (biCycleLengthSelect & M_CLSEL);
//enable IT if needed
if(biPcaTmrItEnable)
{
mPca_EnablePcaTmrIt();
}
else
{
mPca_DisablePcaTmrIt();
}
}
spino_code/silabs_code/Si446x_CustomPacketTX/src/drivers/pca.h 0 → 100644
View file @ 083b3926
/*! @file pca.h
* @brief Header file of PCA routines and definitions.
*
* @b COPYRIGHT
* @n Silicon Laboratories Confidential
* @n Copyright 2012 Silicon Laboratories, Inc.
* @n http://www.silabs.com
*/
#ifndef PCA_H_
#define PCA_H_
/*------------------------------------------------------------------------*/
/* Global definitions */
/*------------------------------------------------------------------------*/
/** @name Time-base source
*
* Time-base source selection of PCA counter.
*/
//@{
#define bPca_PcaCps_000_c 0x00
#define bPca_PcaCps_001_c 0x01
#define bPca_PcaCps_010_c 0x02
#define bPca_PcaCps_011_c 0x03
#define bPca_PcaCps_100_c 0x04
#define bPca_PcaCps_101_c 0x05
//@}
/** @name Cycle length select
*
* Cycle length select definitions of PCA timer PWM configuration.
*/
//@{
#define bPca_PwmClsel_00_c 0x00
#define bPca_PwmClsel_01_c 0x01
#define bPca_PwmClsel_10_c 0x02
#define bPca_PwmClsel_11_c 0x03
//@}
/*------------------------------------------------------------------------*/
/* Global macros */
/*------------------------------------------------------------------------*/
/** @name PCA Timer macros
*
* Macro interfaces of PCA timer operations.
*/
//@{
#define mPca_EnablePcaTmr() CR = 1; CF = 0
#define mPca_StopPcaTmr() CR = 0; CF = 0
#define mPca_EnablePcaTmrIt() PCA0MD |= M_ECF; CF = 0
#define mPca_DisablePcaTmrIt() PCA0MD &= (~M_ECF); CF = 0
#define mPca_ClearPcaTmrIt() CF = 0
//@}
/** @name PCA Timer PWM macros
*
* Macro interfaces of PCA timer PWM configuration.
*/
//@{
#define mPca_EnablePcaTmrCofIt() PCA0PWM |= M_ECOV; PCA0PWM &= (~M_COVF)
#define mPca_DisablePcaTmrCofIt() PCA0PWM &= (~(M_ECOV | M_COVF))
#define mPca_ClearPcaTmrCofIt() PCA0PWM &= (~M_COVF)
#define mPca_SelectAutoReloadReg() PCA0PWM |= M_ARSEL
//@}
#define mPca_EnablePwm16N(biCpmNum) PCA0CPM ## biCpmNum |= (M_PWM16 ## biCpmNum)
#define mPca_DisablePwm16N(biCpmNum) PCA0CPM ## biCpmNum &= (~(M_PWM16 ## biCpmNum))
#define mPca_EnableEcomN(biCpmNum) PCA0CPM ## biCpmNum |= (M_ECOM ## biCpmNum)
#define mPca_DisableEcomN(biCpmNum) PCA0CPM ## biCpmNum &= (~(M_ECOM ## biCpmNum))
#define mPca_EnableCappN(biCpmNum) PCA0CPM ## biCpmNum |= (M_CAPP ## biCpmNum)
#define mPca_DisableCappN(biCpmNum) PCA0CPM ## biCpmNum &= (~(M_CAPP ## biCpmNum))
#define mPca_EnableCapnN(biCpmNum) PCA0CPM ## biCpmNum |= (M_CAPN ## biCpmNum)
#define mPca_DisableCapnN(biCpmNum) PCA0CPM ## biCpmNum &= (~(M_CAPN ## biCpmNum))
#define mPca_EnableMatN(biCpmNum) PCA0CPM ## biCpmNum |= (M_MAT ## biCpmNum)
#define mPca_DisableMatN(biCpmNum) PCA0CPM ## biCpmNum &= (~(M_MAT ## biCpmNum))
#define mPca_EnableTogN(biCpmNum) PCA0CPM ## biCpmNum |= (M_TOG ## biCpmNum)
#define mPca_DisableTogN(biCpmNum) PCA0CPM ## biCpmNum &= (~(M_TOG ## biCpmNum))
#define mPca_EnablePwmN(biCpmNum) PCA0CPM ## biCpmNum |= (M_PWM ## biCpmNum)
#define mPca_DisablePwmN(biCpmNum) PCA0CPM ## biCpmNum &= (~(M_PWM ## biCpmNum))
#define mPca_EnableEccfN(biCpmNum) PCA0CPM ## biCpmNum |= (M_ECCF ## biCpmNum)
#define mPca_DisableEccfN(biCpmNum) PCA0CPM ## biCpmNum &= (~(M_ECCF ## biCpmNum))
#define mPca_DisableAllInCpmN(biCpmNum) PCA0CPM ## biCpmNum = 0x00
#define mPca_SetAutoReloadRegN(biCpmNum, wiPca0Cp) PCA0CPL ## biCpmNum = (wiPca0Cp & 0x00FF); PCA0CPH ## biCpmNum = ((wiPca0Cp >> 8) & 0x00FF)
/*------------------------------------------------------------------------*/
/* Global structure & enumeration definitions */
/*------------------------------------------------------------------------*/
/*------------------------------------------------------------------------*/
/* Function prototypes */
/*------------------------------------------------------------------------*/
void vPca_InitPcaTmr(U8 biPulseSelect, U8 biPcaTmrItEnable, U8 biCycleLengthSelect);
#endif /* PCA_H_ */
spino_code/silabs_code/Si446x_CustomPacketTX/src/drivers/pictures.c 0 → 100644
View file @ 083b3926
/*! @file pictures.c
* @brief This file contains pictures to be shown on graphical LCD.
*
* @b COPYRIGHT
* @n Silicon Laboratories Confidential
* @n Copyright 2012 Silicon Laboratories, Inc.
* @n http://www.silabs.com
*/
#include "..\bsp.h"
/** NOTE: the picture description arrays are generated by Fntcvtr.exe
** The first element of the array should be number of the vertical pixels / 8.
** The second element of the array should be the number of horizontal pixels.
**/
/*
* INFO icon
horizontal size is 21 pixels.
vertical size is 8 pixels.
*/
const SEGMENT_VARIABLE(info21x8[], U8, SEG_CODE) = {
1,21,
'\xff',
'\x81',
'\xff',
'\x81',
'\xfb',
'\xf7',
'\xef',
'\xdf',
'\x81',
'\xff',
'\x81',
'\xf5',
'\xf5',
'\xfd',
'\xff',
'\xc3',
'\xbd',
'\xbd',
'\xbd',
'\xc3',
'\xff'
}; /* end of char *info21x8 */
/*
* RSSI icon
horizontal size is 23 pixels.
vertical size is 8 pixels.
*/
const SEGMENT_VARIABLE(rssi_icon[], U8, SEG_CODE) = {
1,23,
'\xff',
'\x81',
'\xed',
'\xed',
'\xed',
'\x93',
'\xff',
'\xdb',
'\xb5',
'\xb5',
'\xb5',
'\xcf',
'\xff',
'\xdb',
'\xb5',
'\xb5',
'\xb5',
'\xcf',
'\xff',
'\xbd',
'\x81',
'\xbd',
'\xff',
}; /* end of char *info21x8 */
/*
NO PACKET ICON
horizontal size is 11 pixels.
vertical size is 8 pixels.
*/
const SEGMENT_VARIABLE(no_packet11x8[], U8, SEG_CODE) = {
1,11,
'\x10',
'\x10',
'\x10',
'\x00',
'\x10',
'\x10',
'\x10',
'\x00',
'\x10',
'\x10',
'\x10'
};
/*
RSSI1 ICON
horizontal size is 2 pixels.
vertical size is 8 pixels.
*/
const SEGMENT_VARIABLE(rssi12x8[], U8, SEG_CODE) = {
1,2,
'\x40',
'\x40'
};
/*
RSSI2 ICON
horizontal size is 4 pixels.
vertical size is 8 pixels.
*/
const SEGMENT_VARIABLE(rssi24x8[], U8, SEG_CODE) = {
1,4,
'\x40',
'\x40',
'\x60',
'\x60'
};
/*
RSSI3 ICON
horizontal size is 6 pixels.
vertical size is 8 pixels.
*/
const SEGMENT_VARIABLE(rssi36x8[], U8, SEG_CODE) = {
1,6,
'\x40',
'\x40',
'\x60',
'\x60',
'\x70',
'\x70'
};
/*
RSSI4 ICON
horizontal size is 8 pixels.
vertical size is 8 pixels.
*/
const SEGMENT_VARIABLE(rssi48x8[], U8, SEG_CODE) = {
1,8,
'\x40',
'\x40',
'\x60',
'\x60',
'\x70',
'\x70',
'\x78',
'\x78'
};
/*
RSSI5 ICON
horizontal size is 10 pixels.
vertical size is 8 pixels.
*/
const SEGMENT_VARIABLE(rssi510x8[], U8, SEG_CODE) = {
1,10,
'\x40',
'\x40',
'\x60',
'\x60',
'\x70',
'\x70',
'\x78',
'\x78',
'\x7c',
'\x7c'
};
/*
RSSI6 ICON
horizontal size is 12 pixels.
vertical size is 8 pixels.
*/
const SEGMENT_VARIABLE(rssi612x8[], U8, SEG_CODE) = {
1,12,
'\x40',
'\x40',
'\x60',
'\x60',
'\x70',
'\x70',
'\x78',
'\x78',
'\x7c',
'\x7c',
'\x7e',
'\x7e'
};
/*
RSSI7 ICON
horizontal size is 14 pixels.
vertical size is 8 pixels.
*/
const SEGMENT_VARIABLE(rssi714x8[], U8, SEG_CODE) = {
1,14,
'\x40',
'\x40',
'\x60',
'\x60',
'\x70',
'\x70',
'\x78',
'\x78',
'\x7c',
'\x7c',
'\x7e',
'\x7e',
'\x7f',
'\x7f'
};
/*
ANTENNA ICON
horizontal size is 9 pixels.
vertical size is 8 pixels.
*/
const SEGMENT_VARIABLE(ant9x8[], U8, SEG_CODE) = {
1,9,
'\x01',
'\x02',
'\x04',
'\x7f',
'\x04',
'\x02',
'\x01',
'\x00',
'\x24'
};
/*
RSSI FULL ICON
horizontal size is 14 pixels.
vertical size is 8 pixels.
*/
const SEGMENT_VARIABLE(rssi_full_inverted14x8[], U8, SEG_CODE) = {
1,14,
'\x40',
'\x40',
'\x60',
'\x60',
'\x70',
'\x70',
'\x78',
'\x78',
'\x7c',
'\x7c',
'\x7e',
'\x7e',
'\x7f',
'\x7f'
};
/*
ANTANNA 1 ICON
horizontal size is 15 pixels.
vertical size is 8 pixels.
*/
const SEGMENT_VARIABLE(ant1_inverted15x8[], U8, SEG_CODE) = {
1,15,
'\x7f',
'\x7f',
'\x7d',
'\x7b',
'\x41',
'\x7b',
'\x7d',
'\x7f',
'\x7f',
'\x77',
'\x7b',
'\x41',
'\x7f',
'\x7f',
'\x7f'
};
/*
ANTANNA 2 ICON
horizontal size is 15 pixels.
vertical size is 8 pixels.
*/
const SEGMENT_VARIABLE(ant2_inverted15x8[], U8, SEG_CODE) = {
1,15,
'\x7f',
'\x7f',
'\x7d',
'\x7b',
'\x41',
'\x7b',
'\x7d',
'\x7f',
'\x7f',
'\x5b',
'\x4d',
'\x55',
'\x5b',
'\x7f',
'\x7f'
};
/*
OK ICON
horizontal size is 21 pixels.
vertical size is 8 pixels.
*/
const SEGMENT_VARIABLE(ok_inverted21x8[], U8, SEG_CODE) = {
1,21,
'\x00',
'\x00',
'\xff',
'\xff',
'\xc3',
'\xbd',
'\xbd',
'\xbd',
'\xc3',
'\xff',
'\xff',
'\x81',
'\xef',
'\xe7',
'\xdb',
'\xbd',
'\xff',
'\xff',
'\x00',
'\x00',
'\x00',
};
/*
RX ICON
horizontal size is 16 pixels.
vertical size is 8 pixels.
*/
const SEGMENT_VARIABLE(rx_inverted16x8[], U8, SEG_CODE) = {
1,16,
'\x7f',
'\x7f',
'\x7f',
'\x41',
'\x75',
'\x75',
'\x4b',
'\x7f',
'\x7f',
'\x5d',
'\x6b',
'\x77',
'\x6b',
'\x5d',
'\x7f',
'\x7f'
};
/*
START OFF ICON
horizontal size is 29 pixels.
vertical size is 8 pixels.
*/
const SEGMENT_VARIABLE(start_inverted29x8[], U8, SEG_CODE) = {
1,29,
'\xff',
'\xbb',
'\xb5',
'\xb5',
'\xb5',
'\xcd',
'\xff',
'\xfd',
'\xfd',
'\x81',
'\xfd',
'\xfd',
'\xff',
'\x83',
'\xed',
'\xed',
'\x83',
'\xff',
'\x81',
'\xed',
'\xed',
'\x93',
'\xff',
'\xfd',
'\xfd',
'\x81',
'\xfd',
'\xfd',
'\xff'
};
/*
STOP ICON
horizontal size is 24 pixels.
vertical size is 8 pixels.
*/
const SEGMENT_VARIABLE(stop_inverted24x8[], U8, SEG_CODE) = {
1,24,
'\xff',
'\xff',
'\xbb',
'\xb5',
'\xb5',
'\xb5',
'\xcd',
'\xff',
'\xfd',
'\xfd',
'\x81',
'\xfd',
'\xfd',
'\xff',
'\xc3',
'\xbd',
'\xbd',
'\xc3',
'\xff',
'\x81',
'\xed',
'\xed',
'\xf3',
'\xff'
};
/*
TX ICON
horizontal size is 16 pixels.
vertical size is 8 pixels.
*/
const SEGMENT_VARIABLE(tx_inverted16x8[], U8, SEG_CODE) = {
1,16,
'\x7f',
'\x7f',
'\x7d',
'\x7d',
'\x41',
'\x7d',
'\x7d',
'\x7f',
'\x7f',
'\x5d',
'\x6b',
'\x77',
'\x6b',
'\x5d',
'\x7f',
'\x7f'
};
/*
TX ON ICON
horizontal size is 32 pixels.
vertical size is 8 pixels.
*/
const SEGMENT_VARIABLE(txon_inverted32x8[], U8, SEG_CODE) = {
1,32,
'\xff',
'\xfd',
'\xfd',
'\x81',
'\xfd',
'\xfd',
'\xff',
'\xbd',
'\xdb',
'\xe7',
'\xe7',
'\xdb',
'\xbd',
'\xff',
'\xff',
'\xff',
'\xc3',
'\xbd',
'\xbd',
'\xbd',
'\xc3',
'\xff',
'\x81',
'\xfb',
'\xf7',
'\xef',
'\xdf',
'\x81',
'\xff',
'\x00',
'\x00',
'\x00',
};
/*
TX OFF ICON
horizontal size is 32 pixels.
vertical size is 8 pixels.
*/
const SEGMENT_VARIABLE(txoff_inverted32x8[], U8, SEG_CODE) = {
1,32,
'\xff',
'\xfd',
'\xfd',
'\x81',
'\xfd',
'\xfd',
'\xff',
'\xbd',
'\xdb',
'\xe7',
'\xe7',
'\xdb',
'\xbd',
'\xff',
'\xff',
'\xff',
'\xc3',
'\xbd',
'\xbd',
'\xbd',
'\xc3',
'\xff',
'\x81',
'\xf5',
'\xf5',
'\xfd',
'\xff',
'\x81',
'\xf5',
'\xf5',
'\xfd',
'\xff'
};
/*
CLEAR ICON
horizontal size is 29 pixels.
vertical size is 8 pixels.
*/
const SEGMENT_VARIABLE(clear_inverted29x8[], U8, SEG_CODE) = {
1,29,
'\xff',
'\xff',
'\xc3',
'\xbd',
'\xbd',
'\xbd',
'\xff',
'\x81',
'\xbf',
'\xbf',
'\xbf',
'\xff',
'\x81',
'\xad',
'\xad',
'\xbd',
'\xff',
'\x83',
'\xed',
'\xed',
'\xed',
'\x83',
'\xff',
'\x81',
'\xed',
'\xed',
'\x93',
'\xff',
'\xff'
};
/*
CLEAR ICON
horizontal size is 27 pixels.
vertical size is 8 pixels.
*/
const SEGMENT_VARIABLE(clear_inverted27x8[], U8, SEG_CODE) = {
1,27,
'\xff',
'\xc3',
'\xbd',
'\xbd',
'\xbd',
'\xff',
'\x81',
'\xbf',
'\xbf',
'\xbf',
'\xff',
'\x81',
'\xad',
'\xad',
'\xbd',
'\xff',
'\x83',
'\xed',
'\xed',
'\xed',
'\x83',
'\xff',
'\x81',
'\xed',
'\xed',
'\x93',
'\xff',
};
/*
SETTING ICON
horizontal size is 48 pixels.
vertical size is 8 pixels.
*/
const SEGMENT_VARIABLE(setting_inverted48x8[], U8, SEG_CODE) = {
1,48,
'\xff',
'\xff',
'\xbb',
'\xb5',
'\xb5',
'\xb5',
'\xcd',
'\xff',
'\x81',
'\xb5',
'\xb5',
'\xbd',
'\xff',
'\xfd',
'\xfd',
'\x81',
'\xfd',
'\xfd',
'\xff',
'\xfd',
'\xfd',
'\x81',
'\xfd',
'\xfd',
'\xff',
'\x81',
'\xff',
'\x81',
'\xfb',
'\xf7',
'\xef',
'\xdf',
'\x81',
'\xff',
'\xc3',
'\xbd',
'\xbd',
'\xad',
'\xcf',
'\xff',
'\xbb',
'\xb5',
'\xb5',
'\xb5',
'\xcd',
'\xff',
'\xff',
'\xff'
};
/*
SETTING ICON
horizontal size is 45 pixels.
vertical size is 8 pixels.
*/
const SEGMENT_VARIABLE(setting_inverted45x8[], U8, SEG_CODE) = {
1,45,
'\xff',
'\xbb',
'\xb5',
'\xb5',
'\xb5',
'\xcd',
'\xff',
'\x81',
'\xb5',
'\xb5',
'\xbd',
'\xff',
'\xfd',
'\xfd',
'\x81',
'\xfd',
'\xfd',
'\xff',
'\xfd',
'\xfd',
'\x81',
'\xfd',
'\xfd',
'\xff',
'\x81',
'\xff',
'\x81',
'\xfb',
'\xf7',
'\xef',
'\xdf',
'\x81',
'\xff',
'\xc3',
'\xbd',
'\xbd',
'\xad',
'\xcf',
'\xff',
'\xbb',
'\xb5',
'\xb5',
'\xb5',
'\xcd',
'\xff',
};
/*
MINUS ICON
horizontal size is 16 pixels.
vertical size is 8 pixels.
*/
const SEGMENT_VARIABLE(minus_inverted16x8[], U8, SEG_CODE) = {
1,16,
'\xff',
'\xff',
'\xff',
'\xff',
'\xff',
'\xe7',
'\xe7',
'\xe7',
'\xe7',
'\xe7',
'\xe7',
'\xff',
'\xff',
'\xff',
'\xff',
'\xff'
};
/*
PLUS ICON
horizontal size is 16 pixels.
vertical size is 8 pixels.
*/
const SEGMENT_VARIABLE(plus_inverted16x8[], U8, SEG_CODE) = {
1,16,
'\xff',
'\xff',
'\xff',
'\xff',
'\xff',
'\xe7',
'\xe7',
'\x81',
'\x81',
'\xe7',
'\xe7',
'\xff',
'\xff',
'\xff',
'\xff',
'\xff'
};
/*
UP_DOWN ICON
horizontal size is 16 pixels.
vertical size is 8 pixels.
*/
const SEGMENT_VARIABLE(up_down_inverted16x8[], U8, SEG_CODE) = {
1,16,
'\xff',
'\xff',
'\xf7',
'\xf3',
'\x81',
'\xf3',
'\xf7',
'\xff',
'\xff',
'\xef',
'\xcf',
'\x81',
'\xcf',
'\xef',
'\xff',
'\xff'
};
/*
GO ICON
horizontal size is 16 pixels.
vertical size is 8 pixels.
*/
const SEGMENT_VARIABLE(go_inverted16x8[], U8, SEG_CODE) = {
1,16,
'\xff',
'\xff',
'\xc3',
'\xbd',
'\xbd',
'\xad',
'\xcf',
'\xff',
'\xff',
'\xc3',
'\xbd',
'\xbd',
'\xbd',
'\xc3',
'\xff',
'\xff'
};
/*
Silabs LOGO
horizontal size is 66 pixels.
vertical size is 30 pixels.
*/
const SEGMENT_VARIABLE(silabs66x30[], U8, SEG_CODE) = {
4, 66,
'\x00','\x00','\x00','\x23',
'\x00','\x00','\x80','\x24',
'\x00','\x00','\x80','\x24',
'\x00','\xe0','\x81','\x18',
'\x00','\xf8','\x01','\x00',
'\x00','\xfc','\x07','\x00',
'\x00','\xfe','\x0f','\x00',
'\x00','\xff','\x8f','\x3f',
'\x80','\xff','\x1f','\x00',
'\x80','\xff','\x1f','\x00',
'\x80','\xff','\x11','\x00',
'\xc0','\xff','\x91','\x3f',
'\xe0','\xff','\x00','\x20',
'\xe0','\xff','\x00','\x20',
'\xf0','\x7c','\x00','\x20',
'\x70','\x70','\x00','\x00',
'\x30','\x70','\x00','\x00',
'\x38','\x70','\x80','\x3f',
'\x18','\x60','\x03','\x00',
'\x18','\x60','\x07','\x00',
'\x1c','\xe0','\x0f','\x00',
'\x0c','\xe0','\x0f','\x00',
'\x0c','\xe0','\x0f','\x1f',
'\x06','\xe0','\x8f','\x20',
'\x06','\xe0','\x8f','\x20',
'\x82','\xe1','\x8f','\x20',
'\xc2','\xe3','\x0f','\x00',
'\xf2','\xe7','\x0f','\x00',
'\xf2','\xe7','\x0f','\x1f',
'\xf3','\xe5','\x8f','\x20',
'\xfb','\xe5','\x8f','\x20',
'\xf9','\xe5','\x0f','\x1f',
'\xfd','\xe5','\x0f','\x00',
'\xfd','\xe4','\x0f','\x00',
'\xfe','\xe4','\x8f','\x3f',
'\xfe','\xe4','\x07','\x06',
'\xfe','\xfc','\x07','\x0c',
'\xfe','\xfc','\x83','\x3f',
'\xfe','\xfc','\x03','\x00',
'\xfe','\xfc','\x01','\x00',
'\xfe','\xf8','\x09','\x00',
'\xfe','\xf0','\x08','\x00',
'\xfe','\x60','\x08','\x00',
'\xfe','\x00','\x08','\x00',
'\xfe','\x00','\x08','\x00',
'\xfe','\x00','\x88','\x3f',
'\xfe','\x00','\x0c','\x20',
'\xfc','\x00','\x06','\x20',
'\xb8','\x00','\x06','\x20',
'\x90','\x01','\x03','\x00',
'\x80','\x01','\x01','\x3f',
'\x80','\x01','\x81','\x04',
'\x80','\xc3','\x81','\x04',
'\x80','\xe7','\x01','\x3f',
'\x80','\xe7','\x00','\x00',
'\xc0','\xff','\x00','\x00',
'\xe2','\x7f','\x80','\x3f',
'\xf2','\x3f','\x80','\x24',
'\xfe','\x3f','\x80','\x24',
'\xfe','\x0f','\x00','\x1b',
'\xfc','\x0f','\x00','\x00',
'\xf8','\x07','\x00','\x00',
'\xf0','\x01','\x00','\x23',
'\xc6','\x00','\x80','\x24',
'\x06','\x00','\x80','\x24',
'\x00','\x00','\x80','\x18'
};
spino_code/silabs_code/Si446x_CustomPacketTX/src/drivers/pictures.h 0 → 100644
View file @ 083b3926
/*! @file pictures.h
* @brief Header file of pictures definitions.
*
* @b COPYRIGHT
* @n Silicon Laboratories Confidential
* @n Copyright 2012 Silicon Laboratories, Inc.
* @n http://www.silabs.com
*/
#ifndef PICTURES_H_
#define PICTURES_H_
/*------------------------------------------------------------------------*/
/* Global variables */
/*------------------------------------------------------------------------*/
extern const SEGMENT_VARIABLE(info21x8[], U8, SEG_CODE);
extern const SEGMENT_VARIABLE(no_packet11x8[], U8, SEG_CODE);
extern const SEGMENT_VARIABLE(rssi12x8[], U8, SEG_CODE);
extern const SEGMENT_VARIABLE(rssi24x8[], U8, SEG_CODE);
extern const SEGMENT_VARIABLE(rssi36x8[], U8, SEG_CODE);
extern const SEGMENT_VARIABLE(rssi48x8[], U8, SEG_CODE);
extern const SEGMENT_VARIABLE(rssi510x8[], U8, SEG_CODE);
extern const SEGMENT_VARIABLE(rssi612x8[], U8, SEG_CODE);
extern const SEGMENT_VARIABLE(rssi714x8[], U8, SEG_CODE);
extern const SEGMENT_VARIABLE(ant9x8[], U8, SEG_CODE);
extern const SEGMENT_VARIABLE(rssi_full_inverted14x8[], U8, SEG_CODE);
extern const SEGMENT_VARIABLE(ant1_inverted15x8[], U8, SEG_CODE);
extern const SEGMENT_VARIABLE(ant2_inverted15x8[], U8, SEG_CODE);
extern const SEGMENT_VARIABLE(ok_inverted21x8[], U8, SEG_CODE);
extern const SEGMENT_VARIABLE(rx_inverted16x8[], U8, SEG_CODE);
extern const SEGMENT_VARIABLE(start_inverted29x8[], U8, SEG_CODE);
extern const SEGMENT_VARIABLE(stop_inverted24x8[], U8, SEG_CODE);
extern const SEGMENT_VARIABLE(tx_inverted16x8[], U8, SEG_CODE);
extern const SEGMENT_VARIABLE(txon_inverted32x8[], U8, SEG_CODE);
extern const SEGMENT_VARIABLE(txoff_inverted32x8[], U8, SEG_CODE);
extern const SEGMENT_VARIABLE(clear_inverted29x8[], U8, SEG_CODE);
extern const SEGMENT_VARIABLE(clear_inverted27x8[], U8, SEG_CODE);
extern const SEGMENT_VARIABLE(setting_inverted48x8[], U8, SEG_CODE);
extern const SEGMENT_VARIABLE(setting_inverted45x8[], U8, SEG_CODE);
extern const SEGMENT_VARIABLE(minus_inverted16x8[], U8, SEG_CODE);
extern const SEGMENT_VARIABLE(plus_inverted16x8[], U8, SEG_CODE);
extern const SEGMENT_VARIABLE(up_down_inverted16x8[], U8, SEG_CODE);
extern const SEGMENT_VARIABLE(go_inverted16x8[], U8, SEG_CODE);
extern const SEGMENT_VARIABLE(silabs66x30[], U8, SEG_CODE);
extern const SEGMENT_VARIABLE(rssi_icon[], U8, SEG_CODE);
/*------------------------------------------------------------------------*/
/* Global macros */
/*------------------------------------------------------------------------*/
/*------------------------------------------------------------------------*/
/* Global structure & enumeration definitions */
/*------------------------------------------------------------------------*/
/*------------------------------------------------------------------------*/
/* Function prototypes */
/*------------------------------------------------------------------------*/
#endif /* PICTURES_H_ */