spino_code/silabs_code/Si446x_CustomPacketTX/src/hardware_defs.h

+/*! @file hardware_defs.h
+ * @brief This file contains hardware specific definitions defined by the platform.
+ *
+ * @b COPYRIGHT
+ * @n Silicon Laboratories Confidential
+ * @n Copyright 2012 Silicon Laboratories, Inc.
+ * @n http://www.silabs.com
+ */
+
+#ifndef HARDWARE_DEFS_H
+#define HARDWARE_DEFS_H
+
+/*-------------------------------------------------------------*/
+/*						      Global definitions				                 */
+/*-------------------------------------------------------------*/
+
+#if (defined SILABS_PLATFORM_RFSTICK)
+
+/*!* LED state Type definition */
+typedef enum
+{
+  ILLUMINATE,
+  EXTINGUISH
+} eLEDStates;
+
+#define M_P0_UART_TX 0x10
+#define M_P0_UART_RX 0x20
+
+#define M_P0_I2C_SCL 0x40
+#define M_P0_I2C_SDA 0x80
+
+#define M_P0_RF_GPIO0 0x01
+#define M_P0_RF_GPIO1 0x02
+#define M_P0_RF_GPIO2 0x04
+#define M_P0_RF_GPIO3 0x08
+
+#define M_P1_SPI1_SCK  0x01
+#define M_P1_SPI1_MISO 0x02
+#define M_P1_SPI1_MOSI 0x04
+
+#define M_P1_RF_NSEL  0x08
+#define M_P1_RF_NIRQ  0x10
+#define M_P1_RF_PWRDN 0x20
+
+#define M_P0_PB1  0x01
+#define M_P0_PB2  0x02
+#define M_P0_PB3  0x04
+#define M_P0_PB4  0x08
+
+#define M_P2_LED1 0x01
+#define M_P2_LED2 0x02
+#define M_P2_LED3 0x04
+#define M_P2_LED4 0x08
+
+#define M_P2_SW1_A 0x20
+#define M_P2_SW1_B 0x40
+#define M_P1_SW1_C 0x80
+#define M_P1_SW1_D 0x40
+
+#define M_P2_BZ1  0x10
+#define M_P2_C2D  0x80
+
+#define NUMOF_PUSHBUTTONS 0x04
+
+/* Definition of pins that are used by basic HWs, be aware not to have same*/
+#define M_LED1 M_P2_LED1
+#define M_LED2 M_P2_LED2
+#define M_LED3 M_P2_LED3
+#define M_LED4 M_P2_LED4
+
+#define M_BZ1 M_P2_BZ1
+
+#define B_P0_UART_TX 4
+#define B_P0_UART_RX 5
+
+#define B_P0_RF_GPIO0 0
+#define B_P0_RF_GPIO1 1
+#define B_P0_RF_GPIO2 2
+#define B_P0_RF_GPIO3 3
+
+#define B_P1_SPI1_SCK  0
+#define B_P1_SPI1_MISO 1
+#define B_P1_SPI1_MOSI 2
+
+#define B_P1_RF_NSEL  3
+#define B_P1_RF_NIRQ  4
+#define B_P1_RF_PWRDN 5
+
+#define B_P0_PB1  0
+#define B_P0_PB2  1
+#define B_P0_PB3  2
+#define B_P0_PB4  3
+#define B_P2_LED1 0
+#define B_P2_LED2 1
+#define B_P2_LED3 2
+#define B_P2_LED4 3
+
+#define B_P2_SW1_A 5
+#define B_P2_SW1_B 6
+#define B_P1_SW1_C 7
+#define B_P1_SW1_D 6
+
+#define B_P2_BZ1  4
+#define B_P2_C2D  7
+
+SBIT(RF_GPIO0,   SFR_P0, B_P0_RF_GPIO0);
+SBIT(RF_GPIO1,   SFR_P0, B_P0_RF_GPIO1);
+SBIT(RF_GPIO2,   SFR_P0, B_P0_RF_GPIO2);
+SBIT(RF_GPIO3,   SFR_P0, B_P0_RF_GPIO3);
+
+SBIT(SPI1_SCK,   SFR_P1, B_P1_SPI1_SCK);
+SBIT(SPI1_MISO,  SFR_P1, B_P1_SPI1_MISO);
+SBIT(SPI1_MOSI,  SFR_P1, B_P1_SPI1_MOSI);
+
+SBIT(RF_NSEL,  SFR_P1, B_P1_RF_NSEL);
+SBIT(RF_IRQ,   SFR_P1, B_P1_RF_NIRQ);
+SBIT(RF_NIRQ,  SFR_P1, B_P1_RF_NIRQ);
+SBIT(RF_PWRDN, SFR_P1, B_P1_RF_PWRDN);
+
+SBIT(PB1,   SFR_P0, B_P0_PB1);
+SBIT(PB2,   SFR_P0, B_P0_PB2);
+SBIT(PB3,   SFR_P0, B_P0_PB3);
+SBIT(PB4,   SFR_P0, B_P0_PB4);
+SBIT(LED1,  SFR_P2, B_P2_LED1);
+SBIT(LED2,  SFR_P2, B_P2_LED2);
+SBIT(LED3,  SFR_P2, B_P2_LED3);
+SBIT(LED4,  SFR_P2, B_P2_LED4);
+
+SBIT(SW1_A, SFR_P2, B_P2_SW1_A);
+SBIT(SW1_B, SFR_P2, B_P2_SW1_B);
+SBIT(SW1_C, SFR_P1, B_P1_SW1_C);
+SBIT(SW1_D, SFR_P1, B_P1_SW1_D);
+
+SBIT(BZ1,   SFR_P2, B_P2_BZ1);
+
+#elif (defined SILABS_PLATFORM_LCDBB)
+
+/*!* LED state Type definition */
+typedef enum
+{
+  ILLUMINATE,
+  EXTINGUISH
+} eLEDStates;
+
+/*! Hardware related definitions */
+#define HW_NUMOF_LEDS             4u
+#define NUMOF_PUSHBUTTONS         4u
+
+/* UART related port mapping */
+#define B_P0_UART_TX 4
+#define B_P0_UART_RX 5
+
+#define M_P0_UART_TX (1 << B_P0_UART_TX )
+#define M_P0_UART_RX (1 << B_P0_UART_RX )
+
+/*
+ * TODO: Check HW what about SPI0 ?
+ */
+#if 0
+/* SPI0 related port mapping */
+#define B_P1_SPI0_SCK   5u
+#define B_P1_SPI0_MISO  6u
+#define B_P1_SPI0_MOSI  7u
+
+#define M_P1_SPI0_SCK   (1 << B_P1_SPI0_SCK )
+#define M_P1_SPI0_MISO  (1 << B_P1_SPI0_MISO)
+#define M_P1_SPI0_MOSI  (1 << B_P1_SPI0_MOSI)
+
+#define MASK_SPI0_MOSI     M_P1_SPI0_MOSI
+#define PIN_SPI0_MOSI      B_P1_SPI0_MOSI
+#define PORT_SPI0_MOSI                 P1
+#define PXMDOUT_SPI0_MOSI         P1MDOUT
+#define PXSKIP_SPI0_MOSI           P1SKIP
+
+#define MASK_SPI0_MISO     M_P1_SPI0_MISO
+#define PIN_SPI0_MISO      B_P1_SPI0_MISO
+#define PORT_SPI0_MISO                 P1
+#define PXMDOUT_SPI0_MISO         P1MDOUT
+#define PXSKIP_SPI0_MISO           P1SKIP
+
+#define MASK_SPI0_SCK       M_P1_SPI0_SCK
+#define PIN_SPI0_SCK        B_P1_SPI0_SCK
+#define PORT_SPI0_SCK                  P1
+#define PXMDOUT_SPI0_SCK          P1MDOUT
+#define PXSKIP_SPI0_SCK            P1SKIP
+#else
+#define SILABS_PLATFORM_DISABLE_SPI0
+#endif
+
+/* SPI1 related port mapping */
+#define B_P1_SPI1_SCK   0u
+#define B_P1_SPI1_MISO  1u
+#define B_P1_SPI1_MOSI  2u
+
+#define M_P1_SPI1_SCK   (1 << B_P1_SPI1_SCK )
+#define M_P1_SPI1_MISO  (1 << B_P1_SPI1_MISO)
+#define M_P1_SPI1_MOSI  (1 << B_P1_SPI1_MOSI)
+
+#define MASK_SPI1_MOSI     M_P1_SPI1_MOSI
+#define PIN_SPI1_MOSI      B_P1_SPI1_MOSI
+#define PORT_SPI1_MOSI                 P1
+#define PXMDOUT_SPI1_MOSI         P1MDOUT
+#define PXSKIP_SPI1_MOSI           P1SKIP
+
+#define MASK_SPI1_MISO     M_P1_SPI1_MISO
+#define PIN_SPI1_MISO      B_P1_SPI1_MISO
+#define PORT_SPI1_MISO                 P1
+#define PXMDOUT_SPI1_MISO         P1MDOUT
+#define PXSKIP_SPI1_MISO           P1SKIP
+
+#define MASK_SPI1_SCK       M_P1_SPI1_SCK
+#define PIN_SPI1_SCK        B_P1_SPI1_SCK
+#define PORT_SPI1_SCK                  P1
+#define PXMDOUT_SPI1_SCK          P1MDOUT
+#define PXSKIP_SPI1_SCK            P1SKIP
+
+/* LCD related port mapping */
+#define B_P1_LCD_NSEL   6u
+#define B_P1_LCD_A0     7u
+
+#define M_P1_LCD_NSEL   (1 << B_P1_LCD_NSEL)
+#define M_P1_LCD_A0     (1 << B_P1_LCD_A0)
+
+/* SMBus related port mapping */
+#define B_P0_I2C_SDA    6u
+#define B_P0_I2C_SCL    7u
+
+#define M_P0_I2C_SCL    (1 << B_P0_I2C_SDA)
+#define M_P0_I2C_SDA    (1 << B_P0_I2C_SCL)
+
+/* Push-Button related port mapping */
+#define B_P0_PB1        0u
+#define B_P0_PB2        1u
+#define B_P0_PB3        2u
+#define B_P0_PB4        3u
+
+/* LED related port mapping */
+#define B_P2_LED1       0u
+#define B_P2_LED2       1u
+#define B_P2_LED3       2u
+#define B_P2_LED4       3u
+
+#define M_P2_LED1       (1 << B_P2_LED1)
+#define M_P2_LED2       (1 << B_P2_LED2)
+#define M_P2_LED3       (1 << B_P2_LED3)
+#define M_P2_LED4       (1 << B_P2_LED4)
+
+#define M_LED1          M_P2_LED1
+#define M_LED2          M_P2_LED2
+#define M_LED3          M_P2_LED3
+#define M_LED4          M_P2_LED4
+
+/* Buzzer related port mapping */
+#define B_P2_BZ1        4u
+
+#define M_P2_BZ1        (1 << B_P2_BZ1)
+
+#define M_BZ1           M_P2_BZ1
+
+/* RF related port mapping */
+#define B_P1_RF_NSEL    3u
+#define B_P1_RF_NIRQ    4u
+#define B_P1_RF_PWRDN   5u
+
+#define M_P1_RF_NSEL    (1 << B_P1_RF_NSEL)
+#define M_P1_RF_NIRQ    (1 << B_P1_RF_NIRQ)
+#define M_P1_RF_PWRDN   (1 << B_P1_RF_PWRDN)
+
+#define B_P0_RF_GPIO0   0u
+#define B_P0_RF_GPIO1   1u
+#define B_P0_RF_GPIO2   2u
+#define B_P0_RF_GPIO3   3u
+
+#define M_P0_RF_GPIO0   (1 << B_P0_RF_GPIO0)
+#define M_P0_RF_GPIO1   (1 << B_P0_RF_GPIO1)
+#define M_P0_RF_GPIO2   (1 << B_P0_RF_GPIO2)
+#define M_P0_RF_GPIO3   (1 << B_P0_RF_GPIO3)
+
+
+#define PIN_MCU_MOSI      PIN_SPI1_MOSI
+#define PORT_MCU_MOSI     PORT_SPI1_MOSI
+#define PXMDOUT_MCU_MOSI  PXMDOUT_SPI1_MOSI
+
+#define PIN_MCU_MISO      PIN_SPI1_MISO
+#define PORT_MCU_MISO     PORT_SPI1_MISO
+#define PXMDOUT_MCU_MISO  PXMDOUT_SPI1_MISO
+
+#define PIN_MCU_SCK       PIN_SPI1_SCK
+#define PORT_MCU_SCK      PORT_SPI1_SCK
+#define PXMDOUT_MCU_SCK   PXMDOUT_SPI1_SCK
+
+#define PIN_MCU_NSEL        B_P1_RF_NSEL
+#define PORT_MCU_NSEL                 P1
+#define PXMDOUT_MCU_NSEL         P1MDOUT
+
+#define PIN_MCU_SDA         B_P0_I2C_SDA
+#define PORT_MCU_SDA                  P0
+#define PXMDOUT_MCU_SDA          P0MDOUT
+
+#define PIN_MCU_SCL         B_P0_I2C_SCL
+#define PORT_MCU_SCL                  P0
+#define PXMDOUT_MCU_SCL          P0MDOUT
+
+#define PIN_MCU_GPIO0      B_P0_RF_GPIO0
+#define PORT_MCU_GPIO0                P0
+#define PXMDOUT_MCU_GPIO0        P0MDOUT
+
+#define PIN_MCU_GPIO1      B_P0_RF_GPIO1
+#define PORT_MCU_GPIO1                P0
+#define PXMDOUT_MCU_GPIO1        P0MDOUT
+
+#define PIN_MCU_GPIO2      B_P0_RF_GPIO2
+#define PORT_MCU_GPIO2                P0
+#define PXMDOUT_MCU_GPIO2        P0MDOUT
+
+#define PIN_MCU_GPIO3      B_P0_RF_GPIO3
+#define PORT_MCU_GPIO3                P0
+#define PXMDOUT_MCU_GPIO3        P0MDOUT
+
+#define PIN_MCU_SDN        B_P1_RF_PWRDN
+#define PORT_MCU_SDN                  P1
+#define PXMDOUT_MCU_SDN          P1MDOUT
+
+#define PIN_MCU_NIRQ        B_P1_RF_NIRQ
+#define PORT_MCU_NIRQ                 P1
+#define PXMDOUT_MCU_NIRQ         P1MDOUT
+
+
+SBIT(RF_GPIO0,  SFR_P0, B_P0_RF_GPIO0);
+SBIT(RF_GPIO1,  SFR_P0, B_P0_RF_GPIO1);
+SBIT(RF_GPIO2,  SFR_P0, B_P0_RF_GPIO2);
+SBIT(RF_GPIO3,  SFR_P0, B_P0_RF_GPIO3);
+
+/* SMBus */
+SBIT(MCU_SDA,   SFR_P0, B_P0_I2C_SDA);
+SBIT(MCU_SCL,   SFR_P0, B_P0_I2C_SCL);
+
+/* LEDs */
+SBIT(LED1,      SFR_P2, B_P2_LED1);
+SBIT(LED2,      SFR_P2, B_P2_LED2);
+SBIT(LED3,      SFR_P2, B_P2_LED3);
+SBIT(LED4,      SFR_P2, B_P2_LED4);
+
+#if 0
+/* MCU SPI0 */
+SBIT(SPI0_SCK,  SFR_P1, B_P1_SPI1_SCK);
+SBIT(SPI0_MISO, SFR_P1, B_P1_SPI1_MISO);
+SBIT(SPI0_MOSI, SFR_P1, B_P1_SPI1_MOSI);
+#endif
+
+/* MCU SPI1 */
+SBIT(SPI1_SCK,  SFR_P1, B_P1_SPI1_SCK);
+SBIT(SPI1_MISO, SFR_P1, B_P1_SPI1_MISO);
+SBIT(SPI1_MOSI, SFR_P1, B_P1_SPI1_MOSI);
+
+/* RF related */
+SBIT(RF_NSEL,   SFR_P1, B_P1_RF_NSEL);
+SBIT(RF_IRQ,    SFR_P1, B_P1_RF_NIRQ);
+SBIT(RF_NIRQ,   SFR_P1, B_P1_RF_NIRQ);
+SBIT(RF_PWRDN,  SFR_P1, B_P1_RF_PWRDN);
+
+/* LCD related */
+SBIT(LCD_NSEL,  SFR_P1, B_P1_LCD_NSEL);
+SBIT(LCD_A0,    SFR_P1, B_P1_LCD_A0);
+
+SBIT(PB1,       SFR_P0, B_P0_PB1);
+SBIT(PB2,       SFR_P0, B_P0_PB2);
+SBIT(PB3,       SFR_P0, B_P0_PB3);
+SBIT(PB4,       SFR_P0, B_P0_PB4);
+
+/* Buzzer */
+SBIT(BZ1,       SFR_P2, B_P2_BZ1);
+
+#elif (defined SILABS_PLATFORM_WMB)
+
+/*!* LED state Type definition */
+typedef enum
+{
+  ILLUMINATE,
+  EXTINGUISH
+} eLEDStates;
+
+/*! Hardware related definitions */
+#if (defined SILABS_PLATFORM_WMB912)
+#define HW_NUMOF_LEDS             1u
+#define NUMOF_PUSHBUTTONS         1u
+#else
+#define HW_NUMOF_LEDS             4u
+#define NUMOF_PUSHBUTTONS         4u
+#endif
+
+#define M_P0_UART_TX 0x10
+#define M_P0_UART_RX 0x20
+
+#if (defined SILABS_PLATFORM_WMB912)
+#define B_P0_SPI0_SCK   6u
+//#define B_P1_SPI0_MISO  6u
+#define B_P0_SPI0_MOSI  3u
+
+#define M_P0_SPI0_SCK   (1 << B_P0_SPI0_SCK )
+//#define M_P1_SPI0_MISO  (1 << B_P1_SPI0_MISO)
+#define M_P0_SPI0_MOSI  (1 << B_P0_SPI0_MOSI)
+
+#define MASK_SPI0_MOSI     M_P0_SPI0_MOSI
+#define PIN_SPI0_MOSI      B_P0_SPI0_MOSI
+#define PORT_SPI0_MOSI                 P0
+#define PXMDOUT_SPI0_MOSI         P0MDOUT
+#define PXSKIP_SPI0_MOSI           P0SKIP
+
+#if 0
+#define MASK_SPI0_MISO     M_P1_SPI0_MISO
+#define PIN_SPI0_MISO      B_P1_SPI0_MISO
+#define PORT_SPI0_MISO                 P1
+#define PXMDOUT_SPI0_MISO         P1MDOUT
+#define PXSKIP_SPI0_MISO           P1SKIP
+#endif
+
+#define MASK_SPI0_SCK       M_P0_SPI0_SCK
+#define PIN_SPI0_SCK        B_P0_SPI0_SCK
+#define PORT_SPI0_SCK                  P0
+#define PXMDOUT_SPI0_SCK          P0MDOUT
+#define PXSKIP_SPI0_SCK            P0SKIP
+#else
+#define B_P1_SPI0_SCK   5u
+#define B_P1_SPI0_MISO  6u
+#define B_P1_SPI0_MOSI  7u
+
+#define M_P1_SPI0_SCK   (1 << B_P1_SPI0_SCK )
+#define M_P1_SPI0_MISO  (1 << B_P1_SPI0_MISO)
+#define M_P1_SPI0_MOSI  (1 << B_P1_SPI0_MOSI)
+
+#define MASK_SPI0_MOSI     M_P1_SPI0_MOSI
+#define PIN_SPI0_MOSI      B_P1_SPI0_MOSI
+#define PORT_SPI0_MOSI                 P1
+#define PXMDOUT_SPI0_MOSI         P1MDOUT
+#define PXSKIP_SPI0_MOSI           P1SKIP
+
+#define MASK_SPI0_MISO     M_P1_SPI0_MISO
+#define PIN_SPI0_MISO      B_P1_SPI0_MISO
+#define PORT_SPI0_MISO                 P1
+#define PXMDOUT_SPI0_MISO         P1MDOUT
+#define PXSKIP_SPI0_MISO           P1SKIP
+
+#define MASK_SPI0_SCK       M_P1_SPI0_SCK
+#define PIN_SPI0_SCK        B_P1_SPI0_SCK
+#define PORT_SPI0_SCK                  P1
+#define PXMDOUT_SPI0_SCK          P1MDOUT
+#define PXSKIP_SPI0_SCK            P1SKIP
+#endif
+
+#define B_P1_SPI1_SCK   0u
+#define B_P1_SPI1_MISO  1u
+#define B_P1_SPI1_MOSI  2u
+
+#define M_P1_SPI1_SCK   (1 << B_P1_SPI1_SCK )
+#define M_P1_SPI1_MISO  (1 << B_P1_SPI1_MISO)
+#define M_P1_SPI1_MOSI  (1 << B_P1_SPI1_MOSI)
+
+#define MASK_SPI1_MOSI     M_P1_SPI1_MOSI
+#define PIN_SPI1_MOSI      B_P1_SPI1_MOSI
+#define PORT_SPI1_MOSI                 P1
+#define PXMDOUT_SPI1_MOSI         P1MDOUT
+#define PXSKIP_SPI1_MOSI           P1SKIP
+
+#define MASK_SPI1_MISO     M_P1_SPI1_MISO
+#define PIN_SPI1_MISO      B_P1_SPI1_MISO
+#define PORT_SPI1_MISO                 P1
+#define PXMDOUT_SPI1_MISO         P1MDOUT
+#define PXSKIP_SPI1_MISO           P1SKIP
+
+#define MASK_SPI1_SCK       M_P1_SPI1_SCK
+#define PIN_SPI1_SCK        B_P1_SPI1_SCK
+#define PORT_SPI1_SCK                  P1
+#define PXMDOUT_SPI1_SCK          P1MDOUT
+#define PXSKIP_SPI1_SCK            P1SKIP
+
+#if (defined SILABS_PLATFORM_WMB912)
+  #define B_P0_LCD_NSEL   2u
+
+  #if ( (defined SILABS_WMCU_SI106x) || (defined SILABS_WMCU_SI108x) )
+    #define B_P1_LCD_A0     6u
+  #else
+    #define B_P0_LCD_A0     7u
+  #endif
+#else
+#define B_P2_LCD_NSEL   0u
+#define B_P0_LCD_A0     7u
+#endif
+
+#if (defined SILABS_PLATFORM_WMB912)
+  #define M_P0_LCD_NSEL   (1 << B_P0_LCD_NSEL)
+
+  #if ( (defined SILABS_WMCU_SI106x) || (defined SILABS_WMCU_SI108x) )
+    #define M_P1_LCD_A0     (1 << B_P1_LCD_A0)
+  #else
+    #define M_P0_LCD_A0     (1 << B_P0_LCD_A0)
+  #endif
+#else
+#define M_P2_LCD_NSEL   (1 << B_P2_LCD_NSEL)
+#define M_P0_LCD_A0     (1 << B_P0_LCD_A0)
+#endif
+
+#if (defined SILABS_PLATFORM_WMB912)
+#define B_P1_I2C_SDA    4u
+#define B_P1_I2C_SCL    5u
+
+#define M_P1_I2C_SCL    (1 << B_P1_I2C_SDA)
+#define M_P1_I2C_SDA    (1 << B_P1_I2C_SCL)
+#else
+#define B_P2_I2C_SDA    1u
+#define B_P2_I2C_SCL    2u
+
+#define M_P2_I2C_SCL    (1 << B_P2_I2C_SDA)
+#define M_P2_I2C_SDA    (1 << B_P2_I2C_SCL)
+#endif
+
+#define B_P0_PB1        0u
+#if !(defined SILABS_PLATFORM_WMB912)
+#define B_P0_PB2        6u
+#define B_P0_PB3        2u
+#define B_P0_PB4        3u
+#endif
+
+#define B_P0_LED1       0u
+#if !(defined SILABS_PLATFORM_WMB912)
+#define B_P0_LED2       6u
+#define B_P0_LED3       2u
+#define B_P0_LED4       3u
+#endif
+
+#define M_P0_LED1       (1 << B_P0_LED1)
+#if !(defined SILABS_PLATFORM_WMB912)
+#define M_P0_LED2       (1 << B_P0_LED2)
+#define M_P0_LED3       (1 << B_P0_LED3)
+#define M_P0_LED4       (1 << B_P0_LED4)
+#endif
+
+#define M_LED1          M_P0_LED1
+#if !(defined SILABS_PLATFORM_WMB912)
+#define M_LED2          M_P0_LED2
+#define M_LED3          M_P0_LED3
+#define M_LED4          M_P0_LED4
+
+#define B_P2_BZ1        6u
+#endif
+
+#if (defined SILABS_PLATFORM_WMB912)
+  #define B_P1_RF_NSEL    3u
+
+  #if ( (defined SILABS_WMCU_SI106x) || (defined SILABS_WMCU_SI108x) )
+    #define B_P0_RF_PWRDN   7u
+  #else
+    #define B_P1_RF_PWRDN   6u
+  #endif
+#else
+  #define B_P1_RF_NSEL    4u
+  #define B_P2_RF_PWRDN   3u
+#endif
+
+#define B_P0_RF_NIRQ    1u
+
+#define M_P1_RF_NSEL    (1 << B_P1_RF_NSEL)
+#if (defined SILABS_PLATFORM_WMB912)
+  #if ( (defined SILABS_WMCU_SI106x) || (defined SILABS_WMCU_SI108x) )
+    #define M_P0_RF_PWRDN   (1 << B_P0_RF_PWRDN)
+  #else
+    #define M_P1_RF_PWRDN   (1 << B_P1_RF_PWRDN)
+  #endif
+#else
+#define M_P2_RF_PWRDN   (1 << B_P2_RF_PWRDN)
+#endif
+#define M_P0_RF_NIRQ    (1 << B_P0_RF_NIRQ)
+
+/* In WMB RF_GPIO0 is not connected to the MCU by default,
+ * the input pin is interchangeable with the buzzer.
+ * It is defined here for consistency with DCP_Module.
+ */
+#if (defined SILABS_PLATFORM_WMB912)
+#define B_P0_RF_GPIO0   0u
+#define B_P0_RF_GPIO1   6u
+#define B_P0_RF_GPIO2   2u
+#define B_P0_RF_GPIO3   3u
+
+#define M_P0_RF_GPIO0   (1 << B_P0_RF_GPIO0)
+#define M_P0_RF_GPIO1   (1 << B_P0_RF_GPIO1)
+#define M_P0_RF_GPIO2   (1 << B_P0_RF_GPIO2)
+#define M_P0_RF_GPIO3   (1 << B_P0_RF_GPIO3)
+#else
+#define B_P2_RF_GPIO0   6u
+#define B_P1_RF_GPIO1   3u
+#define B_P2_RF_GPIO2   5u
+#define B_P2_RF_GPIO3   4u
+
+#define M_P2_RF_GPIO0   (1 << B_P2_RF_GPIO0)
+#define M_P1_RF_GPIO1   (1 << B_P1_RF_GPIO1)
+#define M_P2_RF_GPIO2   (1 << B_P2_RF_GPIO2)
+#define M_P2_RF_GPIO3   (1 << B_P2_RF_GPIO3)
+#endif
+
+#define PIN_MCU_MOSI      PIN_SPI1_MOSI
+#define PORT_MCU_MOSI     PORT_SPI1_MOSI
+#define PXMDOUT_MCU_MOSI  PXMDOUT_SPI1_MOSI
+
+#define PIN_MCU_MISO      PIN_SPI1_MISO
+#define PORT_MCU_MISO     PORT_SPI1_MISO
+#define PXMDOUT_MCU_MISO  PXMDOUT_SPI1_MISO
+
+#define PIN_MCU_SCK       PIN_SPI1_SCK
+#define PORT_MCU_SCK      PORT_SPI1_SCK
+#define PXMDOUT_MCU_SCK   PXMDOUT_SPI1_SCK
+
+#define PIN_MCU_NSEL        B_P1_RF_NSEL
+#define PORT_MCU_NSEL                 P1
+#define PXMDOUT_MCU_NSEL         P1MDOUT
+
+#if (defined SILABS_PLATFORM_WMB912)
+#define PIN_MCU_SDA         B_P1_I2C_SDA
+#define PORT_MCU_SDA                  P1
+#define PXMDOUT_MCU_SDA          P1MDOUT
+
+#define PIN_MCU_SCL         B_P1_I2C_SCL
+#define PORT_MCU_SCL                  P1
+#define PXMDOUT_MCU_SCL          P1MDOUT
+#else
+#define PIN_MCU_SDA         B_P2_I2C_SDA
+#define PORT_MCU_SDA                  P2
+#define PXMDOUT_MCU_SDA          P2MDOUT
+
+#define PIN_MCU_SCL         B_P2_I2C_SCL
+#define PORT_MCU_SCL                  P2
+#define PXMDOUT_MCU_SCL          P2MDOUT
+#endif
+
+/* In WMB RF_GPIO0 is not connected to the MCU by default,
+ * the input pin is interchangeable with the buzzer.
+ * It is defined here for consistency with DCP_Module.
+ */
+#if (defined SILABS_PLATFORM_WMB912)
+#define PIN_MCU_GPIO0      B_P0_RF_GPIO0
+#define PORT_MCU_GPIO0                P0
+#define PXMDOUT_MCU_GPIO0        P0MDOUT
+
+#define PIN_MCU_GPIO1      B_P0_RF_GPIO1
+#define PORT_MCU_GPIO1                P0
+#define PXMDOUT_MCU_GPIO1        P0MDOUT
+
+#define PIN_MCU_GPIO2      B_P0_RF_GPIO0
+#define PORT_MCU_GPIO2                P0
+#define PXMDOUT_MCU_GPIO2        P0MDOUT
+
+#define PIN_MCU_GPIO3      B_P0_RF_GPIO3
+#define PORT_MCU_GPIO3                P0
+#define PXMDOUT_MCU_GPIO3        P0MDOUT
+
+#if ( (defined SILABS_WMCU_SI106x) || (defined SILABS_WMCU_SI108x) )
+  #define PIN_MCU_SDN        B_P0_RF_PWRDN
+  #define PORT_MCU_SDN                  P0
+  #define PXMDOUT_MCU_SDN          P0MDOUT
+#else
+  #define PIN_MCU_SDN        B_P1_RF_PWRDN
+  #define PORT_MCU_SDN                  P1
+  #define PXMDOUT_MCU_SDN          P1MDOUT
+#endif
+
+#else
+#define PIN_MCU_GPIO0      B_P2_RF_GPIO0
+#define PORT_MCU_GPIO0                P2
+#define PXMDOUT_MCU_GPIO0        P2MDOUT
+
+#define PIN_MCU_GPIO1      B_P1_RF_GPIO1
+#define PORT_MCU_GPIO1                P1
+#define PXMDOUT_MCU_GPIO1        P1MDOUT
+
+#define PIN_MCU_GPIO2      B_P2_RF_GPIO2
+#define PORT_MCU_GPIO2                P2
+#define PXMDOUT_MCU_GPIO2        P2MDOUT
+
+#define PIN_MCU_GPIO3      B_P2_RF_GPIO3
+#define PORT_MCU_GPIO3                P2
+#define PXMDOUT_MCU_GPIO3        P2MDOUT
+
+#define PIN_MCU_SDN        B_P2_RF_PWRDN
+#define PORT_MCU_SDN                  P2
+#define PXMDOUT_MCU_SDN          P2MDOUT
+#endif
+
+#define PIN_MCU_NIRQ        B_P0_RF_NIRQ
+#define PORT_MCU_NIRQ                 P0
+#define PXMDOUT_MCU_NIRQ         P0MDOUT
+
+
+#if (defined SILABS_PLATFORM_WMB912)
+//SBIT(RF_GPIO0,  SFR_P0, B_P0_RF_GPIO0);
+SBIT(RF_GPIO1,  SFR_P0, B_P0_RF_GPIO1);
+SBIT(RF_GPIO2,  SFR_P0, B_P0_RF_GPIO2);
+SBIT(RF_GPIO3,  SFR_P0, B_P0_RF_GPIO3);
+#else
+//SBIT(RF_GPIO0,  SFR_P2, B_P2_RF_GPIO0);
+SBIT(RF_GPIO1,  SFR_P1, B_P1_RF_GPIO1);
+SBIT(RF_GPIO2,  SFR_P2, B_P2_RF_GPIO2);
+SBIT(RF_GPIO3,  SFR_P2, B_P2_RF_GPIO3);
+#endif
+
+/* SMBus */
+#if (defined SILABS_PLATFORM_WMB912)
+SBIT(MCU_SDA,   SFR_P1, B_P1_I2C_SDA);
+SBIT(MCU_SCL,   SFR_P1, B_P1_I2C_SCL);
+#else
+SBIT(MCU_SDA,   SFR_P2, B_P2_I2C_SDA);
+SBIT(MCU_SCL,   SFR_P2, B_P2_I2C_SCL);
+#endif
+
+/* LEDs */
+SBIT(LED1,      SFR_P0, B_P0_LED1);
+#if !(defined SILABS_PLATFORM_WMB912)
+SBIT(LED2,      SFR_P0, B_P0_LED2);
+SBIT(LED3,      SFR_P0, B_P0_LED3);
+SBIT(LED4,      SFR_P0, B_P0_LED4);
+#endif
+
+/* MCU SPI0 */
+#if (defined SILABS_PLATFORM_WMB912)
+SBIT(SPI0_SCK,  SFR_P0, B_P0_SPI0_SCK);
+//SBIT(SPI0_MISO, SFR_P1, B_P1_SPI1_MISO);
+SBIT(SPI0_MOSI, SFR_P0, B_P0_SPI0_MOSI);
+#else
+SBIT(SPI0_SCK,  SFR_P1, B_P1_SPI1_SCK);
+SBIT(SPI0_MISO, SFR_P1, B_P1_SPI1_MISO);
+SBIT(SPI0_MOSI, SFR_P1, B_P1_SPI1_MOSI);
+#endif
+
+/* MCU SPI1 */
+SBIT(SPI1_SCK,  SFR_P1, B_P1_SPI1_SCK);
+SBIT(SPI1_MISO, SFR_P1, B_P1_SPI1_MISO);
+SBIT(SPI1_MOSI, SFR_P1, B_P1_SPI1_MOSI);
+
+/* RF related */
+#if (defined SILABS_PLATFORM_WMB912)
+  #if ( (defined SILABS_WMCU_SI106x) || (defined SILABS_WMCU_SI108x) )
+    SBIT(RF_PWRDN,  SFR_P0, B_P0_RF_PWRDN);
+  #else
+    SBIT(RF_PWRDN,  SFR_P1, B_P1_RF_PWRDN);
+  #endif
+#else
+SBIT(RF_PWRDN,  SFR_P2, B_P2_RF_PWRDN);
+#endif
+SBIT(RF_NSEL,   SFR_P1, B_P1_RF_NSEL);
+SBIT(RF_IRQ,    SFR_P0, B_P0_RF_NIRQ);
+SBIT(RF_NIRQ,   SFR_P0, B_P0_RF_NIRQ);
+
+/* LCD related */
+#if (defined SILABS_PLATFORM_WMB912)
+  SBIT(LCD_NSEL,  SFR_P0, B_P0_LCD_NSEL);
+
+  #if ( (defined SILABS_WMCU_SI106x) || (defined SILABS_WMCU_SI108x) )
+    SBIT(LCD_A0,    SFR_P1, B_P1_LCD_A0);
+  #else
+    SBIT(LCD_A0,    SFR_P0, B_P0_LCD_A0);
+  #endif
+#else
+SBIT(LCD_NSEL,  SFR_P2, B_P2_LCD_NSEL);
+SBIT(LCD_A0,    SFR_P0, B_P0_LCD_A0);
+#endif
+
+SBIT(PB1,       SFR_P0, B_P0_PB1);
+#if !(defined SILABS_PLATFORM_WMB912)
+SBIT(PB2,       SFR_P0, B_P0_PB2);
+SBIT(PB3,       SFR_P0, B_P0_PB3);
+SBIT(PB4,       SFR_P0, B_P0_PB4);
+
+/* Buzzer */
+SBIT(BZ1,       SFR_P2, B_P2_BZ1);
+#endif
+
+#else
+#error Other platforms are not supported yet!
+#endif
+
+#endif //HARDWARE_DEFS_H

spino_code/silabs_code/Si446x_CustomPacketTX/src/platform_defs.h

+/*! @file platform_defs.h
+ * @brief This file contains platform specific definitions.
+ *
+ * @b COPYRIGHT
+ * @n Silicon Laboratories Confidential
+ * @n Copyright 2012 Silicon Laboratories, Inc.
+ * @n http://www.silabs.com
+ */
+
+#ifndef PLATFORM_DEFS_H_
+#define PLATFORM_DEFS_H_
+
+
+/*---------------------------------------------------------------------*/
+/*            Platform specific global definitions                     */
+/*---------------------------------------------------------------------*/
+
+#ifdef SILABS_PLATFORM_RFSTICK
+
+  #define SILABS_RFSTICK_4455HB
+  #define SILABS_MCU_F930
+
+  #ifdef SILABS_RFSTICK_4455HB
+    #define SILABS_RADIO_SI4455
+    #undef SILABS_RADIO_SI446X
+  #else
+    #error Check and define the type of your RFstick & radio.
+  #endif
+
+  #define SILABS_PLATFORM_COMPONENT_LED     4
+  #define SILABS_PLATFORM_COMPONENT_PB      4
+  #define SILABS_PLATFORM_COMPONENT_SWITCH  4
+  #define SILABS_PLATFORM_COMPONENT_BUZZER  1
+
+#elif (defined SILABS_PLATFORM_WMB930)
+  #define SILABS_PLATFORM_WMB
+  #define SILABS_RADIO_SI446X
+  #undef  SILABS_RADIO_SI4455
+  #define SILABS_MCU_F930
+  #define SILABS_LCD_DOG_GLCD
+
+  #define SILABS_PLATFORM_COMPONENT_LED     4
+  #define SILABS_PLATFORM_COMPONENT_PB      4
+//  #define SILABS_PLATFORM_COMPONENT_SWITCH  0
+  #define SILABS_PLATFORM_COMPONENT_BUZZER  1
+#elif (defined SILABS_PLATFORM_WMB912)
+  #define SILABS_PLATFORM_WMB
+  #define SILABS_RADIO_SI446X
+  #undef  SILABS_RADIO_SI4455
+  #define SILABS_IO_WITH_EXTENDER
+  #if (defined SILABS_WMCU_SI106x)
+  #define SILABS_MCU_F930
+  #else
+  #define SILABS_MCU_F912
+  #endif
+  #define SILABS_LCD_DOG_GLCD
+
+  #define SILABS_PLATFORM_COMPONENT_LED     4
+  #define SILABS_PLATFORM_COMPONENT_PB      4
+//  #define SILABS_PLATFORM_COMPONENT_SWITCH  0
+  #define SILABS_PLATFORM_COMPONENT_BUZZER  1
+#elif (defined SILABS_PLATFORM_LCDBB)
+  #define SILABS_RADIO_SI446X
+  #undef  SILABS_RADIO_SI4455
+  #define SILABS_MCU_F930
+  #define SILABS_LCD_DOG_GLCD
+
+  #define SILABS_PLATFORM_COMPONENT_LED     4
+  #define SILABS_PLATFORM_COMPONENT_PB      4
+//  #define SILABS_PLATFORM_COMPONENT_SWITCH  0
+  #define SILABS_PLATFORM_COMPONENT_BUZZER  1
+#else
+  #error Platform is undefined or unidentified platform is used!
+#endif
+
+#ifdef SILABS_MCU_F930
+  #include "drivers\c8051f930_defs.h"
+  #include "drivers\C8051F930_defs_add.h"
+#endif
+
+#ifdef SILABS_MCU_F912
+  #include "drivers\c8051f912_defs.h"
+  #include "drivers\C8051F910_defs_add.h"
+#endif
+
+#ifdef SILABS_MCU_F960
+  #include "drivers\c8051f960_defs.h"
+  #include "drivers\C8051F960_defs_add.h"
+#endif
+
+#endif /* PLATFORM_DEFS_H_ */

spino_code/silabs_code/radio_config_Si4464.h

+/*! @file radio_config.h
+ * @brief This file contains the automatically generated
+ * configurations.
+ *
+ * @n WDS GUI Version: 3.2.11.0
+ * @n Device: Si4464 Rev.: B1                                 
+ *
+ * @b COPYRIGHT
+ * @n Silicon Laboratories Confidential
+ * @n Copyright 2017 Silicon Laboratories, Inc.
+ * @n http://www.silabs.com
+ */
+
+#ifndef RADIO_CONFIG_H_
+#define RADIO_CONFIG_H_
+
+// USER DEFINED PARAMETERS
+// Define your own parameters here
+
+// INPUT DATA
+/*
+// Crys_freq(Hz): 26000000    Crys_tol(ppm): 20    IF_mode: 2    High_perf_Ch_Fil: 1    OSRtune: 0    Ch_Fil_Bw_AFC: 0    ANT_DIV: 0    PM_pattern: 0    
+// MOD_type: 3    Rsymb(sps): 10000    Fdev(Hz): 20000    RXBW(Hz): 150000    Manchester: 0    AFC_en: 0    Rsymb_error: 0.0    Chip-Version: 3    
+// RF Freq.(MHz): 433    API_TC: 29    fhst: 250000    inputBW: 0    BERT: 0    RAW_dout: 0    D_source: 0    Hi_pfm_div: 1    
+// 
+// # RX IF frequency is  -406250 Hz
+// # WB filter 3 (BW =  80.26 kHz);  NB-filter 3 (BW = 80.26 kHz)
+// 
+// Modulation index: 4
+*/
+
+
+// CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ                     26000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH               0x30
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP        0x03
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET       0xF000
+#define RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD					   {0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, \
+0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, \
+0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5, 0xC5}
+
+
+// CONFIGURATION COMMANDS
+
+/*
+// Command:                  RF_POWER_UP
+// Description:              Command to power-up the device and select the operational mode and functionality.
+*/
+#define RF_POWER_UP 0x02, 0x01, 0x00, 0x01, 0x8C, 0xBA, 0x80
+
+/*
+// Command:                  RF_GPIO_PIN_CFG
+// Description:              Configures the GPIO pins.
+*/
+#define RF_GPIO_PIN_CFG 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_XO_TUNE_2
+// Number of properties:     2
+// Group ID:                 0x00
+// Start ID:                 0x00
+// Default values:           0x40, 0x00, 
+// Descriptions:
+//   GLOBAL_XO_TUNE - Configure the internal capacitor frequency tuning bank for the crystal oscillator.
+//   GLOBAL_CLK_CFG - Clock configuration options.
+*/
+#define RF_GLOBAL_XO_TUNE_2 0x11, 0x00, 0x02, 0x00, 0x52, 0x00
+
+/*
+// Set properties:           RF_GLOBAL_CONFIG_1
+// Number of properties:     1
+// Group ID:                 0x00
+// Start ID:                 0x03
+// Default values:           0x20, 
+// Descriptions:
+//   GLOBAL_CONFIG - Global configuration settings.
+*/
+#define RF_GLOBAL_CONFIG_1 0x11, 0x00, 0x01, 0x03, 0x60
+
+/*
+// Set properties:           RF_INT_CTL_ENABLE_2
+// Number of properties:     2
+// Group ID:                 0x01
+// Start ID:                 0x00
+// Default values:           0x04, 0x00, 
+// Descriptions:
+//   INT_CTL_ENABLE - This property provides for global enabling of the three interrupt groups (Chip, Modem and Packet Handler) in order to generate HW interrupts at the NIRQ pin.
+//   INT_CTL_PH_ENABLE - Enable individual interrupt sources within the Packet Handler Interrupt Group to generate a HW interrupt on the NIRQ output pin.
+*/
+#define RF_INT_CTL_ENABLE_2 0x11, 0x01, 0x02, 0x00, 0x01, 0x20
+
+/*
+// Set properties:           RF_FRR_CTL_A_MODE_4
+// Number of properties:     4
+// Group ID:                 0x02
+// Start ID:                 0x00
+// Default values:           0x01, 0x02, 0x09, 0x00, 
+// Descriptions:
+//   FRR_CTL_A_MODE - Fast Response Register A Configuration.
+//   FRR_CTL_B_MODE - Fast Response Register B Configuration.
+//   FRR_CTL_C_MODE - Fast Response Register C Configuration.
+//   FRR_CTL_D_MODE - Fast Response Register D Configuration.
+*/
+#define RF_FRR_CTL_A_MODE_4 0x11, 0x02, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PREAMBLE_TX_LENGTH_9
+// Number of properties:     9
+// Group ID:                 0x10
+// Start ID:                 0x00
+// Default values:           0x08, 0x14, 0x00, 0x0F, 0x21, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PREAMBLE_TX_LENGTH - Configure length of TX Preamble.
+//   PREAMBLE_CONFIG_STD_1 - Configuration of reception of a packet with a Standard Preamble pattern.
+//   PREAMBLE_CONFIG_NSTD - Configuration of transmission/reception of a packet with a Non-Standard Preamble pattern.
+//   PREAMBLE_CONFIG_STD_2 - Configuration of timeout periods during reception of a packet with Standard Preamble pattern.
+//   PREAMBLE_CONFIG - General configuration bits for the Preamble field.
+//   PREAMBLE_PATTERN_31_24 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_23_16 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_15_8 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+//   PREAMBLE_PATTERN_7_0 - Configuration of the bit values describing a Non-Standard Preamble pattern.
+*/
+#define RF_PREAMBLE_TX_LENGTH_9 0x11, 0x10, 0x09, 0x00, 0x08, 0x14, 0x00, 0x0F, 0x31, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_SYNC_CONFIG_5
+// Number of properties:     5
+// Group ID:                 0x11
+// Start ID:                 0x00
+// Default values:           0x01, 0x2D, 0xD4, 0x2D, 0xD4, 
+// Descriptions:
+//   SYNC_CONFIG - Sync Word configuration bits.
+//   SYNC_BITS_31_24 - Sync word.
+//   SYNC_BITS_23_16 - Sync word.
+//   SYNC_BITS_15_8 - Sync word.
+//   SYNC_BITS_7_0 - Sync word.
+*/
+#define RF_SYNC_CONFIG_5 0x11, 0x11, 0x05, 0x00, 0x01, 0xB4, 0x2B, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_CRC_CONFIG_7
+// Number of properties:     7
+// Group ID:                 0x12
+// Start ID:                 0x00
+// Default values:           0x00, 0x01, 0x08, 0xFF, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   PKT_CRC_CONFIG - Select a CRC polynomial and seed.
+//   PKT_WHT_POLY_15_8 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_POLY_7_0 - 16-bit polynomial value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_15_8 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_SEED_7_0 - 16-bit seed value for the PN Generator (e.g., for Data Whitening)
+//   PKT_WHT_BIT_NUM - Selects which bit of the LFSR (used to generate the PN / data whitening sequence) is used as the output bit for data scrambling.
+//   PKT_CONFIG1 - General configuration bits for transmission or reception of a packet.
+*/
+#define RF_PKT_CRC_CONFIG_7 0x11, 0x12, 0x07, 0x00, 0x84, 0x01, 0x08, 0xFF, 0xFF, 0x00, 0x02
+
+/*
+// Set properties:           RF_PKT_LEN_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x08
+// Default values:           0x00, 0x00, 0x00, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_LEN - Configuration bits for reception of a variable length packet.
+//   PKT_LEN_FIELD_SOURCE - Field number containing the received packet length byte(s).
+//   PKT_LEN_ADJUST - Provides for adjustment/offset of the received packet length value (in order to accommodate a variety of methods of defining total packet length).
+//   PKT_TX_THRESHOLD - TX FIFO almost empty threshold.
+//   PKT_RX_THRESHOLD - RX FIFO Almost Full threshold.
+//   PKT_FIELD_1_LENGTH_12_8 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_LENGTH_7_0 - Unsigned 13-bit Field 1 length value.
+//   PKT_FIELD_1_CONFIG - General data processing and packet configuration bits for Field 1.
+//   PKT_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across Field 1.
+//   PKT_FIELD_2_LENGTH_12_8 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_LENGTH_7_0 - Unsigned 13-bit Field 2 length value.
+//   PKT_FIELD_2_CONFIG - General data processing and packet configuration bits for Field 2.
+*/
+#define RF_PKT_LEN_12 0x11, 0x12, 0x0C, 0x08, 0x00, 0x00, 0x00, 0x30, 0x30, 0x00, 0x30, 0x04, 0xA2, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_FIELD_2_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x14
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across Field 2.
+//   PKT_FIELD_3_LENGTH_12_8 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_LENGTH_7_0 - Unsigned 13-bit Field 3 length value.
+//   PKT_FIELD_3_CONFIG - General data processing and packet configuration bits for Field 3.
+//   PKT_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across Field 3.
+//   PKT_FIELD_4_LENGTH_12_8 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_LENGTH_7_0 - Unsigned 13-bit Field 4 length value.
+//   PKT_FIELD_4_CONFIG - General data processing and packet configuration bits for Field 4.
+//   PKT_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across Field 4.
+//   PKT_FIELD_5_LENGTH_12_8 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_LENGTH_7_0 - Unsigned 13-bit Field 5 length value.
+//   PKT_FIELD_5_CONFIG - General data processing and packet configuration bits for Field 5.
+*/
+#define RF_PKT_FIELD_2_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_FIELD_5_CRC_CONFIG_12
+// Number of properties:     12
+// Group ID:                 0x12
+// Start ID:                 0x20
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across Field 5.
+//   PKT_RX_FIELD_1_LENGTH_12_8 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_LENGTH_7_0 - Unsigned 13-bit RX Field 1 length value.
+//   PKT_RX_FIELD_1_CONFIG - General data processing and packet configuration bits for RX Field 1.
+//   PKT_RX_FIELD_1_CRC_CONFIG - Configuration of CRC control bits across RX Field 1.
+//   PKT_RX_FIELD_2_LENGTH_12_8 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_LENGTH_7_0 - Unsigned 13-bit RX Field 2 length value.
+//   PKT_RX_FIELD_2_CONFIG - General data processing and packet configuration bits for RX Field 2.
+//   PKT_RX_FIELD_2_CRC_CONFIG - Configuration of CRC control bits across RX Field 2.
+//   PKT_RX_FIELD_3_LENGTH_12_8 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_LENGTH_7_0 - Unsigned 13-bit RX Field 3 length value.
+//   PKT_RX_FIELD_3_CONFIG - General data processing and packet configuration bits for RX Field 3.
+*/
+#define RF_PKT_FIELD_5_CRC_CONFIG_12 0x11, 0x12, 0x0C, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_PKT_RX_FIELD_3_CRC_CONFIG_9
+// Number of properties:     9
+// Group ID:                 0x12
+// Start ID:                 0x2C
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   PKT_RX_FIELD_3_CRC_CONFIG - Configuration of CRC control bits across RX Field 3.
+//   PKT_RX_FIELD_4_LENGTH_12_8 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_LENGTH_7_0 - Unsigned 13-bit RX Field 4 length value.
+//   PKT_RX_FIELD_4_CONFIG - General data processing and packet configuration bits for RX Field 4.
+//   PKT_RX_FIELD_4_CRC_CONFIG - Configuration of CRC control bits across RX Field 4.
+//   PKT_RX_FIELD_5_LENGTH_12_8 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_LENGTH_7_0 - Unsigned 13-bit RX Field 5 length value.
+//   PKT_RX_FIELD_5_CONFIG - General data processing and packet configuration bits for RX Field 5.
+//   PKT_RX_FIELD_5_CRC_CONFIG - Configuration of CRC control bits across RX Field 5.
+*/
+#define RF_PKT_RX_FIELD_3_CRC_CONFIG_9 0x11, 0x12, 0x09, 0x2C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_MODEM_MOD_TYPE_12
+// Number of properties:     12
+// Group ID:                 0x20
+// Start ID:                 0x00
+// Default values:           0x02, 0x80, 0x07, 0x0F, 0x42, 0x40, 0x01, 0xC9, 0xC3, 0x80, 0x00, 0x06, 
+// Descriptions:
+//   MODEM_MOD_TYPE - Selects the type of modulation. In TX mode, additionally selects the source of the modulation.
+//   MODEM_MAP_CONTROL - Controls polarity and mapping of transmit and receive bits.
+//   MODEM_DSM_CTRL - Miscellaneous control bits for the Delta-Sigma Modulator (DSM) in the PLL Synthesizer.
+//   MODEM_DATA_RATE_2 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_1 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_DATA_RATE_0 - Unsigned 24-bit value used to determine the TX data rate
+//   MODEM_TX_NCO_MODE_3 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_2 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_1 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_TX_NCO_MODE_0 - TX Gaussian filter oversampling ratio and Byte 3 of unsigned 26-bit TX Numerically Controlled Oscillator (NCO) modulus.
+//   MODEM_FREQ_DEV_2 - 17-bit unsigned TX frequency deviation word.
+//   MODEM_FREQ_DEV_1 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_MOD_TYPE_12 0x11, 0x20, 0x0C, 0x00, 0x03, 0x00, 0x07, 0x06, 0x1A, 0x80, 0x05, 0x8C, 0xBA, 0x80, 0x00, 0x06
+
+/*
+// Set properties:           RF_MODEM_FREQ_DEV_0_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x0C
+// Default values:           0xD3, 
+// Descriptions:
+//   MODEM_FREQ_DEV_0 - 17-bit unsigned TX frequency deviation word.
+*/
+#define RF_MODEM_FREQ_DEV_0_1 0x11, 0x20, 0x01, 0x0C, 0x4D
+
+/*
+// Set properties:           RF_MODEM_TX_RAMP_DELAY_8
+// Number of properties:     8
+// Group ID:                 0x20
+// Start ID:                 0x18
+// Default values:           0x01, 0x00, 0x08, 0x03, 0xC0, 0x00, 0x10, 0x20, 
+// Descriptions:
+//   MODEM_TX_RAMP_DELAY - TX ramp-down delay setting.
+//   MODEM_MDM_CTRL - MDM control.
+//   MODEM_IF_CONTROL - Selects Fixed-IF, Scaled-IF, or Zero-IF mode of RX Modem operation.
+//   MODEM_IF_FREQ_2 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_1 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_IF_FREQ_0 - the IF frequency setting (an 18-bit signed number).
+//   MODEM_DECIMATION_CFG1 - Specifies three decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+//   MODEM_DECIMATION_CFG0 - Specifies miscellaneous parameters and decimator ratios for the Cascaded Integrator Comb (CIC) filter.
+*/
+#define RF_MODEM_TX_RAMP_DELAY_8 0x11, 0x20, 0x08, 0x18, 0x01, 0x80, 0x08, 0x03, 0x80, 0x00, 0x20, 0x20
+
+/*
+// Set properties:           RF_MODEM_BCR_OSR_1_9
+// Number of properties:     9
+// Group ID:                 0x20
+// Start ID:                 0x22
+// Default values:           0x00, 0x4B, 0x06, 0xD3, 0xA0, 0x06, 0xD3, 0x02, 0xC0, 
+// Descriptions:
+//   MODEM_BCR_OSR_1 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_OSR_0 - RX BCR/Slicer oversampling rate (12-bit unsigned number).
+//   MODEM_BCR_NCO_OFFSET_2 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_1 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_NCO_OFFSET_0 - RX BCR NCO offset value (an unsigned 22-bit number).
+//   MODEM_BCR_GAIN_1 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GAIN_0 - The unsigned 11-bit RX BCR loop gain value.
+//   MODEM_BCR_GEAR - RX BCR loop gear control.
+//   MODEM_BCR_MISC1 - Miscellaneous control bits for the RX BCR loop.
+*/
+#define RF_MODEM_BCR_OSR_1_9 0x11, 0x20, 0x09, 0x22, 0x01, 0x45, 0x01, 0x93, 0x4C, 0x00, 0xCA, 0x02, 0xC2
+
+/*
+// Set properties:           RF_MODEM_AFC_GEAR_7
+// Number of properties:     7
+// Group ID:                 0x20
+// Start ID:                 0x2C
+// Default values:           0x00, 0x23, 0x83, 0x69, 0x00, 0x40, 0xA0, 
+// Descriptions:
+//   MODEM_AFC_GEAR - RX AFC loop gear control.
+//   MODEM_AFC_WAIT - RX AFC loop wait time control.
+//   MODEM_AFC_GAIN_1 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_GAIN_0 - Sets the gain of the PLL-based AFC acquisition loop, and provides miscellaneous control bits for AFC functionality.
+//   MODEM_AFC_LIMITER_1 - Set the AFC limiter value.
+//   MODEM_AFC_LIMITER_0 - Set the AFC limiter value.
+//   MODEM_AFC_MISC - Specifies miscellaneous AFC control bits.
+*/
+#define RF_MODEM_AFC_GEAR_7 0x11, 0x20, 0x07, 0x2C, 0x04, 0x36, 0x80, 0x22, 0x0F, 0x50, 0x80
+
+/*
+// Set properties:           RF_MODEM_AGC_CONTROL_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x35
+// Default values:           0xE0, 
+// Descriptions:
+//   MODEM_AGC_CONTROL - Miscellaneous control bits for the Automatic Gain Control (AGC) function in the RX Chain.
+*/
+#define RF_MODEM_AGC_CONTROL_1 0x11, 0x20, 0x01, 0x35, 0xE2
+
+/*
+// Set properties:           RF_MODEM_AGC_WINDOW_SIZE_9
+// Number of properties:     9
+// Group ID:                 0x20
+// Start ID:                 0x38
+// Default values:           0x11, 0x10, 0x10, 0x0B, 0x1C, 0x40, 0x00, 0x00, 0x2B, 
+// Descriptions:
+//   MODEM_AGC_WINDOW_SIZE - Specifies the size of the measurement and settling windows for the AGC algorithm.
+//   MODEM_AGC_RFPD_DECAY - Sets the decay time of the RF peak detectors.
+//   MODEM_AGC_IFPD_DECAY - Sets the decay time of the IF peak detectors.
+//   MODEM_FSK4_GAIN1 - Specifies the gain factor of the secondary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_GAIN0 - Specifies the gain factor of the primary branch in 4(G)FSK ISI-suppression.
+//   MODEM_FSK4_TH1 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_TH0 - 16 bit 4(G)FSK slicer threshold.
+//   MODEM_FSK4_MAP - 4(G)FSK symbol mapping code.
+//   MODEM_OOK_PDTC - Configures the attack and decay times of the OOK Peak Detector.
+*/
+#define RF_MODEM_AGC_WINDOW_SIZE_9 0x11, 0x20, 0x09, 0x38, 0x11, 0x47, 0x47, 0x00, 0x1A, 0xFF, 0xFF, 0x00, 0x2A
+
+/*
+// Set properties:           RF_MODEM_OOK_CNT1_8
+// Number of properties:     8
+// Group ID:                 0x20
+// Start ID:                 0x42
+// Default values:           0xA4, 0x03, 0x56, 0x02, 0x00, 0xA3, 0x02, 0x80, 
+// Descriptions:
+//   MODEM_OOK_CNT1 - OOK control.
+//   MODEM_OOK_MISC - Selects the detector(s) used for demodulation of an OOK signal, or for demodulation of a (G)FSK signal when using the asynchronous demodulator.
+//   MODEM_RAW_SEARCH - Defines and controls the search period length for the Moving Average and Min-Max detectors.
+//   MODEM_RAW_CONTROL - Defines gain and enable controls for raw / nonstandard mode.
+//   MODEM_RAW_EYE_1 - 11 bit eye-open detector threshold.
+//   MODEM_RAW_EYE_0 - 11 bit eye-open detector threshold.
+//   MODEM_ANT_DIV_MODE - Antenna diversity mode settings.
+//   MODEM_ANT_DIV_CONTROL - Specifies controls for the Antenna Diversity algorithm.
+*/
+#define RF_MODEM_OOK_CNT1_8 0x11, 0x20, 0x08, 0x42, 0xA4, 0x02, 0xD6, 0x83, 0x00, 0xC8, 0x01, 0x80
+
+/*
+// Set properties:           RF_MODEM_RSSI_COMP_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x4E
+// Default values:           0x32, 
+// Descriptions:
+//   MODEM_RSSI_COMP - RSSI compensation value.
+*/
+#define RF_MODEM_RSSI_COMP_1 0x11, 0x20, 0x01, 0x4E, 0x40
+
+/*
+// Set properties:           RF_MODEM_CLKGEN_BAND_1
+// Number of properties:     1
+// Group ID:                 0x20
+// Start ID:                 0x51
+// Default values:           0x08, 
+// Descriptions:
+//   MODEM_CLKGEN_BAND - Select PLL Synthesizer output divider ratio as a function of frequency band.
+*/
+#define RF_MODEM_CLKGEN_BAND_1 0x11, 0x20, 0x01, 0x51, 0x0A
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x00
+// Default values:           0xFF, 0xBA, 0x0F, 0x51, 0xCF, 0xA9, 0xC9, 0xFC, 0x1B, 0x1E, 0x0F, 0x01, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE13_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE12_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE11_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE10_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE9_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE8_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE7_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE6_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE5_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE4_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE3_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE2_7_0 - Filter coefficients for the first set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12 0x11, 0x21, 0x0C, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x0C
+// Default values:           0xFC, 0xFD, 0x15, 0xFF, 0x00, 0x0F, 0xFF, 0xC4, 0x30, 0x7F, 0xF5, 0xB5, 
+// Descriptions:
+//   MODEM_CHFLT_RX1_CHFLT_COE1_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COE0_7_0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM0 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM1 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM2 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX1_CHFLT_COEM3 - Filter coefficients for the first set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE13_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE12_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE11_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE10_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE9_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE8_7_0 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12 0x11, 0x21, 0x0C, 0x0C, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00, 0xCC, 0xA1, 0x30, 0xA0, 0x21, 0xD1
+
+/*
+// Set properties:           RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12
+// Number of properties:     12
+// Group ID:                 0x21
+// Start ID:                 0x18
+// Default values:           0xB8, 0xDE, 0x05, 0x17, 0x16, 0x0C, 0x03, 0x00, 0x15, 0xFF, 0x00, 0x00, 
+// Descriptions:
+//   MODEM_CHFLT_RX2_CHFLT_COE7_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE6_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE5_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE4_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE3_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE2_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE1_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COE0_7_0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM0 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM1 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM2 - Filter coefficients for the second set of RX filter coefficients.
+//   MODEM_CHFLT_RX2_CHFLT_COEM3 - Filter coefficients for the second set of RX filter coefficients.
+*/
+#define RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12 0x11, 0x21, 0x0C, 0x18, 0xB9, 0xC9, 0xEA, 0x05, 0x12, 0x11, 0x0A, 0x04, 0x15, 0xFC, 0x03, 0x00
+
+/*
+// Set properties:           RF_PA_MODE_4
+// Number of properties:     4
+// Group ID:                 0x22
+// Start ID:                 0x00
+// Default values:           0x08, 0x7F, 0x00, 0x5D, 
+// Descriptions:
+//   PA_MODE - Selects the PA operating mode, and selects resolution of PA power adjustment (i.e., step size).
+//   PA_PWR_LVL - Configuration of PA output power level.
+//   PA_BIAS_CLKDUTY - Configuration of the PA Bias and duty cycle of the TX clock source.
+//   PA_TC - Configuration of PA ramping parameters.
+*/
+#define RF_PA_MODE_4 0x11, 0x22, 0x04, 0x00, 0x08, 0x7F, 0x00, 0x3D
+
+/*
+// Set properties:           RF_SYNTH_PFDCP_CPFF_7
+// Number of properties:     7
+// Group ID:                 0x23
+// Start ID:                 0x00
+// Default values:           0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03, 
+// Descriptions:
+//   SYNTH_PFDCP_CPFF - Feed forward charge pump current selection.
+//   SYNTH_PFDCP_CPINT - Integration charge pump current selection.
+//   SYNTH_VCO_KV - Gain scaling factors (Kv) for the VCO tuning varactors on both the integrated-path and feed forward path.
+//   SYNTH_LPFILT3 - Value of resistor R2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT2 - Value of capacitor C2 in feed-forward path of loop filter.
+//   SYNTH_LPFILT1 - Value of capacitors C1 and C3 in feed-forward path of loop filter.
+//   SYNTH_LPFILT0 - Bias current of the active amplifier in the feed-forward loop filter.
+*/
+#define RF_SYNTH_PFDCP_CPFF_7 0x11, 0x23, 0x07, 0x00, 0x2C, 0x0E, 0x0B, 0x04, 0x0C, 0x73, 0x03
+
+/*
+// Set properties:           RF_MATCH_VALUE_1_12
+// Number of properties:     12
+// Group ID:                 0x30
+// Start ID:                 0x00
+// Default values:           0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
+// Descriptions:
+//   MATCH_VALUE_1 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 1 value with the received Match 1 byte.
+//   MATCH_MASK_1 - Mask value to be logically AND-ed (bit-wise) with the Match 1 byte.
+//   MATCH_CTRL_1 - Enable for Packet Match functionality, and configuration of Match Byte 1.
+//   MATCH_VALUE_2 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 2 value with the received Match 2 byte.
+//   MATCH_MASK_2 - Mask value to be logically AND-ed (bit-wise) with the Match 2 byte.
+//   MATCH_CTRL_2 - Configuration of Match Byte 2.
+//   MATCH_VALUE_3 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 3 value with the received Match 3 byte.
+//   MATCH_MASK_3 - Mask value to be logically AND-ed (bit-wise) with the Match 3 byte.
+//   MATCH_CTRL_3 - Configuration of Match Byte 3.
+//   MATCH_VALUE_4 - Match value to be compared with the result of logically AND-ing (bit-wise) the Mask 4 value with the received Match 4 byte.
+//   MATCH_MASK_4 - Mask value to be logically AND-ed (bit-wise) with the Match 4 byte.
+//   MATCH_CTRL_4 - Configuration of Match Byte 4.
+*/
+#define RF_MATCH_VALUE_1_12 0x11, 0x30, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+
+/*
+// Set properties:           RF_FREQ_CONTROL_INTE_8
+// Number of properties:     8
+// Group ID:                 0x40
+// Start ID:                 0x00
+// Default values:           0x3C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x20, 0xFF, 
+// Descriptions:
+//   FREQ_CONTROL_INTE - Frac-N PLL Synthesizer integer divide number.
+//   FREQ_CONTROL_FRAC_2 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_1 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_FRAC_0 - Frac-N PLL fraction number.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_1 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_CHANNEL_STEP_SIZE_0 - EZ Frequency Programming channel step size.
+//   FREQ_CONTROL_W_SIZE - Set window gating period (in number of crystal reference clock cycles) for counting VCO frequency during calibration.
+//   FREQ_CONTROL_VCOCNT_RX_ADJ - Adjust target count for VCO calibration in RX mode.
+*/
+#define RF_FREQ_CONTROL_INTE_8 0x11, 0x40, 0x08, 0x00, 0x41, 0x0C, 0xEC, 0x4E, 0x4E, 0xC5, 0x20, 0xFE
+
+
+// AUTOMATICALLY GENERATED CODE! 
+// DO NOT EDIT/MODIFY BELOW THIS LINE!
+// --------------------------------------------
+
+#ifndef FIRMWARE_LOAD_COMPILE
+#define RADIO_CONFIGURATION_DATA_ARRAY { \
+        0x07, RF_POWER_UP, \
+        0x08, RF_GPIO_PIN_CFG, \
+        0x06, RF_GLOBAL_XO_TUNE_2, \
+        0x05, RF_GLOBAL_CONFIG_1, \
+        0x06, RF_INT_CTL_ENABLE_2, \
+        0x08, RF_FRR_CTL_A_MODE_4, \
+        0x0D, RF_PREAMBLE_TX_LENGTH_9, \
+        0x09, RF_SYNC_CONFIG_5, \
+        0x0B, RF_PKT_CRC_CONFIG_7, \
+        0x10, RF_PKT_LEN_12, \
+        0x10, RF_PKT_FIELD_2_CRC_CONFIG_12, \
+        0x10, RF_PKT_FIELD_5_CRC_CONFIG_12, \
+        0x0D, RF_PKT_RX_FIELD_3_CRC_CONFIG_9, \
+        0x10, RF_MODEM_MOD_TYPE_12, \
+        0x05, RF_MODEM_FREQ_DEV_0_1, \
+        0x0C, RF_MODEM_TX_RAMP_DELAY_8, \
+        0x0D, RF_MODEM_BCR_OSR_1_9, \
+        0x0B, RF_MODEM_AFC_GEAR_7, \
+        0x05, RF_MODEM_AGC_CONTROL_1, \
+        0x0D, RF_MODEM_AGC_WINDOW_SIZE_9, \
+        0x0C, RF_MODEM_OOK_CNT1_8, \
+        0x05, RF_MODEM_RSSI_COMP_1, \
+        0x05, RF_MODEM_CLKGEN_BAND_1, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE13_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX1_CHFLT_COE1_7_0_12, \
+        0x10, RF_MODEM_CHFLT_RX2_CHFLT_COE7_7_0_12, \
+        0x08, RF_PA_MODE_4, \
+        0x0B, RF_SYNTH_PFDCP_CPFF_7, \
+        0x10, RF_MATCH_VALUE_1_12, \
+        0x0C, RF_FREQ_CONTROL_INTE_8, \
+        0x00 \
+ }
+#else
+#define RADIO_CONFIGURATION_DATA_ARRAY { 0 }
+#endif
+
+// DEFAULT VALUES FOR CONFIGURATION PARAMETERS
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT                     30000000L
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT                    0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT               0x10
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT        0x01
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT       0x1000
+#define RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD_DEFAULT					   {0x42, 0x55, 0x54, 0x54, 0x4F, 0x4E, 0x31} // BUTTON1 
+
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_INCLUDED                      0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH_SIZE                          0x00
+#define RADIO_CONFIGURATION_DATA_RADIO_PATCH                               {  }
+
+#ifndef RADIO_CONFIGURATION_DATA_ARRAY
+#error "This property must be defined!"
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ
+#define RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ          RADIO_CONFIGURATION_DATA_RADIO_XO_FREQ_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER
+#define RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER         RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH
+#define RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH    RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP
+#define RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP   RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET
+#define RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET  RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET_DEFAULT 
+#endif
+
+#ifndef RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD
+#define RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD         RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD_DEFAULT 
+#endif
+
+#define RADIO_CONFIGURATION_DATA { \
+                            Radio_Configuration_Data_Array,                            \
+                            RADIO_CONFIGURATION_DATA_CHANNEL_NUMBER,                   \
+                            RADIO_CONFIGURATION_DATA_RADIO_PACKET_LENGTH,              \
+                            RADIO_CONFIGURATION_DATA_RADIO_STATE_AFTER_POWER_UP,       \
+                            RADIO_CONFIGURATION_DATA_RADIO_DELAY_CNT_AFTER_RESET,       \
+                            RADIO_CONFIGURATION_DATA_CUSTOM_PAYLOAD                   \
+                            }
+
+#endif /* RADIO_CONFIG_H_ */

spino_code/src/clock.c

+/*
+ * clock.c
+ *
+ *  Created on: 1 Jul 2018
+ *      Author: nats
+ */
+
+#include "stm32f10x.h"
+
+/**
+  * @brief  Sets System clock frequency to 65MHz and configure HCLK, PCLK2
+  *         and PCLK1 prescalers.
+  * @note   This function should be used only after reset.
+  * @param  None
+  * @retval None
+  */
+void SetSysClockTo65(void)
+{
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+
+  /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable Prefetch Buffer */
+    FLASH->ACR |= FLASH_ACR_PRFTBE;
+
+    /* Flash 2 wait state */
+    FLASH->ACR &= (uint32_t)((uint32_t)~FLASH_ACR_LATENCY);
+    FLASH->ACR |= (uint32_t)FLASH_ACR_LATENCY_2;
+
+
+    /* HCLK = SYSCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
+
+    /* PCLK2 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
+
+    /* PCLK1 = HCLK */
+    RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
+
+    /*  PLL configuration: PLLCLK = HSE * 5 = 65 MHz */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
+                                        RCC_CFGR_PLLMULL));
+    RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMULL5);
+
+    /* Enable PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Select PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
+
+    /* Wait till PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)0x08)
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+}

spino_code/src/datafifo.c

+/*
+ * datafifo.c
+ *
+ *  Created on: 1 Jul 2018
+ *      Author: nats
+ */
+
+#include "datafifo.h"
+#include "radio.h"
+
+packet *fifo[FIFOSIZE];
+
+uint16_t readp = 0;
+uint16_t writep = 0;
+
+uint8_t full = 0;
+uint8_t empty = 1;
+
+uint8_t add_packet(packet *p) {
+	if(full) {
+		return FIFOERROR;
+	} else {
+		fifo[writep] = p;
+		writep++;
+		check_full();
+		return FIFOOK;
+	}
+}
+
+uint8_t read_packet(packet *p) {
+	if(empty) {
+		return FIFOERROR;
+	} else {
+		p = fifo[readp];
+		readp++;
+		check_empty();
+		return FIFOOK;
+	}
+}
+
+uint8_t check_full() {
+	uint8_t wmask = writep & FIFOMASK;
+	uint8_t rmask = readp & FIFOMASK;
+
+	uint8_t overwbit = (writep & FIFOSIZE);
+	uint8_t overrbit = (readp & FIFOSIZE);
+
+	if((wmask == rmask-1) && (overwbit != overrbit)) {
+		full = 1;
+		return FULL;
+	} else {
+		full = 0;
+		return READY;
+	}
+}
+
+uint8_t check_empty() {
+	uint8_t wmask = writep & FIFOMASK;
+	uint8_t rmask = readp & FIFOMASK;
+
+	uint8_t overwbit = (writep & FIFOSIZE);
+	uint8_t overrbit = (readp & FIFOSIZE);
+
+	if(overwbit == overrbit) {
+		writep = writep & FIFOMASK;
+		readp = readp & FIFOMASK;
+	}
+
+	if((wmask-1 == rmask) && (overwbit == overrbit)) {
+		empty = 1;
+		return EMPTY;
+	} else {
+		empty = 0;
+		return READY;
+	}
+}
+
+void init_fifo() {
+	for(uint8_t i = 0; i < FIFOSIZE; i++) {
+		uint8_t *datap = fifo[i];
+		datap[0] = START_TX;
+	}
+}

spino_code/src/main.c

@@ -11,6 +11,9 @@
 
 #include "stm32f10x.h"
 #include "periph.h"
+#include "lmk61e2.h"
+#include "clock.h"
+#include "datafifo.h"
 			
 
 int main(void)
@@ -21,9 +24,58 @@ int main(void)
 	initI2C();
 
 	/* Init and start the TI clock */
+	uint8_t valid_conf = 1;
 
-	if(validPLL()) GPIO_ResetBits(LEDPORT, LED);
-	/* Switch to the external 13MHz clock */
+	if(validPLL(VNDRID_BY1, 0x10)) {
+		writeTIPLL(OUTDIV_BY1, 0x00); // Outdiv = 192;
+		if(!validPLL(OUTDIV_BY1, 0x00)) valid_conf = 0;
+		writeTIPLL(OUTDIV_BY0, 0xC0); // Outdiv = 192;
+		if(!validPLL(OUTDIV_BY0, 0xC0)) valid_conf = 0;
+
+		writeTIPLL(PLL_CTRL0, 0x04); // Remove Doubler
+		if(!validPLL(PLL_CTRL0, 0x04)) valid_conf = 0;
+
+		writeTIPLL(PLL_NDIV_BY1, 0x00); // Integer part = 99
+		if(!validPLL(PLL_NDIV_BY1, 0x00)) valid_conf = 0;
+		writeTIPLL(PLL_NDIV_BY0, 0x63); // Integer part = 99
+		if(!validPLL(PLL_NDIV_BY0, 0x63)) valid_conf = 0;
+
+		writeTIPLL(PLL_FRACNUM_BY2, 0x00); // Fractionnal numerator = 84
+		if(!validPLL(PLL_FRACNUM_BY2, 0x00)) valid_conf = 0;
+		writeTIPLL(PLL_FRACNUM_BY1, 0x00); // Fractionnal numerator = 84
+		if(!validPLL(PLL_FRACNUM_BY1, 0x00)) valid_conf = 0;
+		writeTIPLL(PLL_FRACNUM_BY0, 0x54); // Fractionnal numerator = 84
+		if(!validPLL(PLL_FRACNUM_BY0, 0x54)) valid_conf = 0;
+
+		writeTIPLL(PLL_FRACDEN_BY2, 0x00); //Fractionnal denumerator = 100
+		if(!validPLL(PLL_FRACDEN_BY2, 0x00)) valid_conf = 0;
+		writeTIPLL(PLL_FRACDEN_BY1, 0x00); //Fractionnal denumerator = 100
+		if(!validPLL(PLL_FRACDEN_BY1, 0x00)) valid_conf = 0;
+		writeTIPLL(PLL_FRACDEN_BY0, 0x64); //Fractionnal denumerator = 100
+		if(!validPLL(PLL_FRACDEN_BY0, 0x64)) valid_conf = 0;
+
+		writeTIPLL(DIFFCTL, 0x02); // LVDS Output
+		if(!validPLL(DIFFCTL, 0x02)) valid_conf = 0;
+	}
+
+	if(valid_conf) {
+		GPIO_SetBits(GPIOB, PLL_EN);
+		GPIO_ResetBits(GPIOA, LED);
+
+		/* Switch to the external 13MHz clock */
+		SetSysClockTo65();
+		SystemCoreClockUpdate();
+
+		/* Init UART and SPI */
+		// Init the SPI without dma for SI4461 configuration
+		initSPI(NODMA);
+		initsi4461();
+
+		// Init the SPI with DMA for communication
+		initfifo();
+
+		GPIO_SetBits(GPIOA, LED);
+	}
 
 
 	/* Start SI446x */

spino_code/src/periph.c

+#include "stm32f10x_dma.h"
+
 #include "periph.h"
 #include "lmk61e2.h"
 
+
 void initGPIO() {
 	RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE);
 	RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
 	RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE);
 
 	GPIO_InitTypeDef GPIO_InitStructure;
-	GPIO_InitStructure.GPIO_Pin = LED;
+	GPIO_InitStructure.GPIO_Pin = LED | SI_CS;
 	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
 	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
-	GPIO_Init(LEDPORT, &GPIO_InitStructure);
+	GPIO_Init(GPIOA, &GPIO_InitStructure);
 
 	/* Light Up led for test */
-	GPIO_SetBits(LEDPORT, LED);
+	GPIO_SetBits(GPIOA, LED);
+
+	/* Reset SI4461 */
+	GPIO_SetBits(GPIOA, SI_CS);
+
+	/* Keep the PLL down */
+	GPIO_PinRemapConfig(GPIO_Remap_SWJ_JTAGDisable, ENABLE);
+
+	GPIO_InitStructure.GPIO_Pin = PLL_EN | SI_SHDN;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
+	GPIO_Init(GPIOB, &GPIO_InitStructure);
+	GPIO_ResetBits(GPIOB, PLL_EN);
+
+
 }
 
 void initI2C() {
@@ -39,7 +56,7 @@ void initI2C() {
     I2C_AcknowledgeConfig(I2C1, ENABLE);
 }
 
-uint8_t validPLL() {
+uint8_t validPLL(uint8_t addr, uint8_t ref) {
 	uint8_t value = 0;
 
 	I2C_GenerateSTART(I2C1, ENABLE);
@@ -48,7 +65,7 @@ uint8_t validPLL() {
 	I2C_Send7bitAddress(I2C1, I2C_LMK_ADDR << 1, I2C_Direction_Transmitter);
 	while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED));
 
-	I2C_SendData(I2C1, VNDRID_BY1);
+	I2C_SendData(I2C1, addr);
 	while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_BYTE_TRANSMITTED));
 
 	I2C_GenerateSTART(I2C1, ENABLE);
@@ -63,12 +80,12 @@ uint8_t validPLL() {
 	I2C_GenerateSTOP(I2C1, ENABLE);
 	while(I2C_GetFlagStatus(I2C1, I2C_FLAG_STOPF));
 
-	if(value == 0x10) return 1;
+	if(value == ref) return 1;
 
 	return 0;
 }
 
-void configTIPLL() {
+void writeTIPLL(uint8_t addr, uint8_t value) {
 
 	I2C_GenerateSTART(I2C1, ENABLE);
 	while(!I2C_GetFlagStatus(I2C1, I2C_FLAG_SB));
@@ -76,5 +93,88 @@ void configTIPLL() {
 	I2C_Send7bitAddress(I2C1, I2C_LMK_ADDR << 1, I2C_Direction_Transmitter);
 	while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED));
 
+	I2C_SendData(I2C1, addr);
+	while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_BYTE_TRANSMITTED));
 
+	I2C_SendData(I2C1, value);
+	while(!I2C_CheckEvent(I2C1, I2C_EVENT_MASTER_BYTE_TRANSMITTED));
+
+	I2C_GenerateSTOP(I2C1, ENABLE);
+	while(I2C_GetFlagStatus(I2C1, I2C_FLAG_STOPF));
+}
+
+void initSPI(uint8_t withDMA) {
+	RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
+	RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
+
+	GPIO_InitTypeDef GPIO_InitStructure;
+	GPIO_InitStructure.GPIO_Pin = SCK | MOSI | MISO;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+	SPI_InitTypeDef SPI_InitStructure;
+
+	SPI_InitStructure.SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+	SPI_InitStructure.SPI_Mode = SPI_Mode_Master;
+	SPI_InitStructure.SPI_DataSize = SPI_DataSize_8b;
+	SPI_InitStructure.SPI_CPOL = SPI_CPOL_Low;
+	SPI_InitStructure.SPI_CPHA = SPI_CPHA_1Edge;
+	SPI_InitStructure.SPI_NSS = SPI_NSS_Soft;
+	SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_64;
+	SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB;
+	SPI_InitStructure.SPI_CRCPolynomial = 7;
+
+	if(withDMA == 1) {
+		DMA_InitTypeDef DMA_InitStructure;
+
+		/* Init DMA for SPI1 TX */
+		DMA_DeInit(DMA1_Channel3);
+
+		DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)(&SPI1->DR);
+		DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
+		DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+		DMA_InitStructure.DMA_BufferSize = 48;
+		DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
+		DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+		DMA_InitStructure.DMA_MemoryDataSize = DMA_PeripheralDataSize_Byte;
+		DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
+		DMA_InitStructure.DMA_Priority = DMA_Priority_High;
+		DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
+		DMA_Init(DMA1_Channel3, &DMA_InitStructure);
+	}
+
+	SPI_Init(SPI1, &SPI_InitStructure);
+	SPI_Cmd(SPI1, ENABLE);
+}
+
+/* Send the 48 bytes via DMA on SPI1 */
+void dmaSPISend(uint32_t addr) {
+	DMA1_Channel3->CMAR = addr;
+	DMA_Cmd(DMA1_Channel3, ENABLE);
+}
+
+void initUART() {
+	RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
+
+	GPIO_InitTypeDef GPIO_InitStructure;
+	GPIO_InitStructure.GPIO_Pin = UTX;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
+	GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
+	GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+	GPIO_InitStructure.GPIO_Pin = URX;
+	GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
+	GPIO_Init(GPIOA, &GPIO_InitStructure);
+
+	USART_InitTypeDef USART_InitStructure;
+    USART_InitStructure.USART_BaudRate = 115200;
+    USART_InitStructure.USART_WordLength = USART_WordLength_8b;
+    USART_InitStructure.USART_StopBits = USART_StopBits_1;
+    USART_InitStructure.USART_Parity = USART_Parity_No;
+    USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+    USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+
+    USART_Init(USART1, &USART_InitStructure);
+    USART_Cmd(USART1, ENABLE);
 }

spino_code/src/radio.c

+/*
+ * radio.c
+ *
+ *  Created on: 3 Jul 2018
+ *      Author: nats
+ */
+
+#include "stm32f10x.h"
+#include "datafifo.h"
+#include "radio.h"
+
+uint8_t beaconbuffer[48] = { 	0xDE, 0xAD, 0xBE, 0xEF, 0xBA, 0xDC, 0x0F, 0xFE, 0xBA, 0xDF, 0x00, 0xD0,
+								0xDE, 0xAD, 0xBE, 0xEF, 0xBA, 0xDC, 0x0F, 0xFE, 0xBA, 0xDF, 0x00, 0xD0,
+								0xDE, 0xAD, 0xBE, 0xEF, 0xBA, 0xDC, 0x0F, 0xFE, 0xBA, 0xDF, 0x00, 0xD0,
+								0xDE, 0xAD, 0xBE, 0xEF, 0xBA, 0xDC, 0x0F, 0xFE, 0xBA, 0xDF, 0x00, 0xD0 };
+
+void send_packet() {
+	uint8_t * p = 0;
+	if(read_packet(&p) == FIFOERROR) {
+		// Nothing to send in the FIFO
+		// We send the Toxic beacon
+		dmaSPISend(beaconbuffer);
+	} else {
+		dmaSPISend(p);
+	}
+}
+
+void si44_spisend(uint8_t data) {
+	SPI_I2S_SendData(SPI1, data);
+
+}
+
+void set_property(unsigned short property, unsigned char length) {
+    si44_spisend(SET_PROPERTY);
+    si44_spisend(property >> 8);
+    si44_spisend(length);
+    si44_spisend(property & 0xFF);
+}