top Project Status (01/28/2018 - 15:15:09)
Project File: valid_spi_pll.xise Parser Errors: No Errors
Module Name: main_fsm Implementation State: Mapped (Failed)
Target Device: xc6slx9-3tqg144
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment:  
  • Final Timing Score:
  
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateFri 26. Jan 19:29:30 2018
Post-Synthesis Simulation Model ReportOut of DateFri 26. Jan 19:29:31 2018
Post-Translate Simulation Model ReportOut of DateFri 26. Jan 19:29:31 2018
WebTalk ReportOut of DateSun 28. Jan 15:06:19 2018
WebTalk Log FileOut of DateSun 28. Jan 15:06:23 2018

Date Generated: 01/28/2018 - 15:15:09