| top Project Status (01/28/2018 - 15:15:09) | |||
| Project File: | valid_spi_pll.xise | Parser Errors: | No Errors |
| Module Name: | main_fsm | Implementation State: | Mapped (Failed) |
| Target Device: | xc6slx9-3tqg144 |
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| Product Version: | ISE 14.7 |
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| Design Goal: | Balanced |
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| Design Strategy: | Xilinx Default (unlocked) |
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| Environment: |
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| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | ||||||
| Translation Report | ||||||
| Map Report | ||||||
| Place and Route Report | ||||||
| CPLD Fitter Report (Text) | ||||||
| Power Report | ||||||
| Post-PAR Static Timing Report | ||||||
| Bitgen Report | ||||||
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| ISIM Simulator Log | Out of Date | Fri 26. Jan 19:29:30 2018 | |
| Post-Synthesis Simulation Model Report | Out of Date | Fri 26. Jan 19:29:31 2018 | |
| Post-Translate Simulation Model Report | Out of Date | Fri 26. Jan 19:29:31 2018 | |
| WebTalk Report | Out of Date | Sun 28. Jan 15:06:19 2018 | |
| WebTalk Log File | Out of Date | Sun 28. Jan 15:06:23 2018 | |