diff --git a/IP/LTC2271_ADCGetter/LTC2271_IP.sublime-workspace b/IP/LTC2271_ADCGetter/LTC2271_IP.sublime-workspace index b7439d86e7dc21bbc681c4e811e9625f38a8240e..507763f885fdf11d0ad789f17fc2d1aee2b7fe3a 100644 --- a/IP/LTC2271_ADCGetter/LTC2271_IP.sublime-workspace +++ b/IP/LTC2271_ADCGetter/LTC2271_IP.sublime-workspace @@ -151,6 +151,7 @@ "file_history": [ "/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi", + "/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/mz_petalinux_wrapper.hdf", "/home/nats/.qucs/dsn_lna/lna_dsn.sch", "/home/nats/project/vnav1_fpga_soft/fpga/valid_spi_pll/adc_data_ng.v", "/home/nats/.FreeCAD/Mod/A2plus/InitGui.py", diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/4c407e6cdd36e680/4c407e6cdd36e680.xci b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/4c407e6cdd36e680/4c407e6cdd36e680.xci new file mode 100644 index 0000000000000000000000000000000000000000..c4151d7413be6efe95805a9f09ef4cec12920e02 --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/4c407e6cdd36e680/4c407e6cdd36e680.xci @@ -0,0 +1,918 @@ + + + xilinx.com + ipcache + 4c407e6cdd36e680 + 0 + + + mz_petalinux_processing_system7_0_0 + + + 99999999 + 99999999 + 99999999 + 99999999 + 99999999 + mz_petalinux_processing_system7_0_0 + 666.666660 + 23.8095 + 23.8095 + 10.000000 + 10.158730 + 124.999999 + 10.000000 + 99.999999 + 10.000000 + 10.000000 + 10.000000 + 50 + 199.999998 + 199.999998 + 25.000000 + 10.000000 + 20.000000 + 200.000000 + 111.111110 + 111.111110 + 111.111110 + 111.111110 + 111.111110 + 111.111110 + 50 + 50.000000 + 60 + 60 + 111.111110 + 6:2:1 + 667 + 40 + 0xE0008000 + <Select> + 0 + <Select> + 0xE0008FFF + External + 0 + -1 + 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gpio[0]#qspi0_ss_b#qspi0_io[0]#qspi0_io[1]#qspi0_io[2]#qspi0_io[3]/HOLD_B#qspi0_sclk#reset#qspi_fbclk#gpio[9]#gpio[10]#gpio[11]#gpio[12]#gpio[13]#gpio[14]#gpio[15]#tx_clk#txd[0]#txd[1]#txd[2]#txd[3]#tx_ctl#rx_clk#rxd[0]#rxd[1]#rxd[2]#rxd[3]#rx_ctl#data[4]#dir#stp#nxt#data[0]#data[1]#data[2]#data[3]#clk#data[5]#data[6]#data[7]#clk#cmd#data[0]#data[1]#data[2]#data[3]#cd#gpio[47]#tx#rx#wp#gpio[51]#mdc#mdio + 0 + 99 + 12 + 0 + 12 + 0 + 10 + 12 + 0 + 12 + 1 + 1 + 11 + 1 + 1 + 11 + 1 + 0 + <Select> + <Select> + 0 + 1 + 1 + 11 + 1 + 11 + 1 + 0 + 1 + 1 + 11 + 1 + 11 + 1 + 0 + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + <Select> + 0 + 1 + 1 + 11 + 1 + 11 + 1 + 0 + 1 + 1 + 11 + 1 + 11 + 1 + 0 + 2 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0.406 + 0.396 + 0.340 + 0.346 + -0.021 + -0.002 + -0.071 + -0.082 + clg400 + IO PLL + 5 + 200 + part0 + 0 + <Select> + 0 + LVCMOS 3.3V + LVCMOS 1.8V + PRODUCTION + 1 + MIO 8 + 0 + <Select> + 1 + MIO 1 .. 6 + 0 + <Select> + 0xFCFFFFFF + IO PLL + 5 + 1 + 200 + MIO 1 .. 6 + 1 + MIO 46 + 0 + <Select> + 1 + MIO 50 + 1 + MIO 40 .. 45 + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0xE0100000 + 0xE0100FFF + 0xE0101000 + 0xE0101FFF + IO PLL + 40 + 25 + 1 + x4 + NA + NA + NA + NA + NA + NA + NA + IO PLL + 1 + 100 + 0 + 0xE0006000 + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0xE0006FFF + 0 + <Select> + 0xE0007000 + 1 + EMIO + 1 + EMIO + 1 + EMIO + 0xE0007FFF + 1 + EMIO + IO PLL + 50 + 166.666666 + 1 + 31 + 31 + 10 + 3 + 10 + 6 + 10 + 6 + 64 + 99 + 6 + 64 + 10 + 6 + 64 + 10 + 6 + 64 + 10 + 6 + External + 1 + 200 + 12 + 128 + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 0 + <Select> + 2 + 0 + 8 + <Select> + 0xE0104000 + CPU_1X + 1 + 111.111115 + CPU_1X + 1 + 111.111115 + CPU_1X + 1 + 111.111115 + 0xE0104fff + 1 + EMIO + 0xE0105000 + CPU_1X + 1 + 133.333333 + CPU_1X + 1 + 133.333333 + CPU_1X + 1 + 133.333333 + 0xE0105fff + 0 + <Select> + 50 + 0xE0000000 + 115200 + 0 + <Select> + 0xE0000FFF + 0 + <Select> + 0xE0001000 + 115200 + 0 + <Select> + 0xE0001FFF + 1 + MIO 48 .. 49 + IO PLL + 20 + 50 + 1 + 533.333328 + 0 + 0 + 3 + 8 + 0.294 + 0.298 + 0.338 + 0.334 + 32 Bit + 7 + 54.14 + 54.563 + 160 + 54.14 + 54.563 + 160 + 39.7 + 54.563 + 160 + 39.7 + 54.563 + 160 + 0 + 10 + 6 + 4096 MBits + 50.05 + 101.239 + 160 + 50.43 + 79.5025 + 160 + 50.10 + 60.536 + 160 + 50.01 + 71.7715 + 160 + -0.073 + -0.072 + 0.024 + 0.023 + 49.59 + 104.5365 + 160 + 51.74 + 70.676 + 160 + 50.32 + 59.1615 + 160 + 48.55 + 81.319 + 160 + 16 Bits + Disabled + 1 + 533.333333 + Normal (0-85) + DDR 3 + MT41K256M16 RE-125 + 15 + DDR3_1066F + 1 + 1 + 1 + 40.0 + 35.0 + 48.75 + 7 + 7 + 0 + NA + 0xE0102000 + 0xE0102fff + 1 + 60 + 1 + MIO 7 + MIO 28 .. 39 + 0xE0103000 + 0xE0103fff + 0 + 60 + 0 + <Select> + <Select> + 1 + Active Low + Share reset pin + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 3 + CPU_1X + 1 + 0 + 133.333333 + <Select> + None + zynq + em.avnet.com:microzed_7010:part0:1.1 + xc7z010 + clg400 + VERILOG + + MIXED + -1 + + TRUE + TRUE + 4c407e6cdd36e680 + IP_Unknown + 6 + TRUE + . + + . + 2017.4 + GLOBAL + + + + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/4c407e6cdd36e680/mz_petalinux_processing_system7_0_0.dcp b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/4c407e6cdd36e680/mz_petalinux_processing_system7_0_0.dcp new file mode 100644 index 0000000000000000000000000000000000000000..554f81ad5d6712650111497731785a33153368b2 Binary files /dev/null and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/4c407e6cdd36e680/mz_petalinux_processing_system7_0_0.dcp differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/4c407e6cdd36e680/mz_petalinux_processing_system7_0_0_sim_netlist.v b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/4c407e6cdd36e680/mz_petalinux_processing_system7_0_0_sim_netlist.v new file mode 100755 index 0000000000000000000000000000000000000000..0b04b8541340d7221b50730ad362f458a8bce096 --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/4c407e6cdd36e680/mz_petalinux_processing_system7_0_0_sim_netlist.v @@ -0,0 +1,5375 @@ +// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 +// Date : Sun Oct 20 22:43:57 2019 +// Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS +// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mz_petalinux_processing_system7_0_0_sim_netlist.v +// Design : mz_petalinux_processing_system7_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z010clg400-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "mz_petalinux_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2017.4" *) +(* NotValidForBitStream *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix + (I2C0_SDA_I, + I2C0_SDA_O, + I2C0_SDA_T, + I2C0_SCL_I, + I2C0_SCL_O, + I2C0_SCL_T, + SPI1_SCLK_I, + SPI1_SCLK_O, + SPI1_SCLK_T, + SPI1_MOSI_I, + SPI1_MOSI_O, + SPI1_MOSI_T, + SPI1_MISO_I, + SPI1_MISO_O, + SPI1_MISO_T, + SPI1_SS_I, + SPI1_SS_O, + SPI1_SS1_O, + SPI1_SS2_O, + SPI1_SS_T, + TTC0_WAVE0_OUT, + TTC0_WAVE1_OUT, + TTC0_WAVE2_OUT, + USB0_PORT_INDCTL, + USB0_VBUS_PWRSELECT, + USB0_VBUS_PWRFAULT, + M_AXI_GP0_ARVALID, + M_AXI_GP0_AWVALID, + M_AXI_GP0_BREADY, + M_AXI_GP0_RREADY, + M_AXI_GP0_WLAST, + M_AXI_GP0_WVALID, + M_AXI_GP0_ARID, + M_AXI_GP0_AWID, + M_AXI_GP0_WID, + M_AXI_GP0_ARBURST, + M_AXI_GP0_ARLOCK, + M_AXI_GP0_ARSIZE, + M_AXI_GP0_AWBURST, + M_AXI_GP0_AWLOCK, + M_AXI_GP0_AWSIZE, + M_AXI_GP0_ARPROT, + M_AXI_GP0_AWPROT, + M_AXI_GP0_ARADDR, + M_AXI_GP0_AWADDR, + M_AXI_GP0_WDATA, + M_AXI_GP0_ARCACHE, + M_AXI_GP0_ARLEN, + M_AXI_GP0_ARQOS, + M_AXI_GP0_AWCACHE, + M_AXI_GP0_AWLEN, + M_AXI_GP0_AWQOS, + M_AXI_GP0_WSTRB, + M_AXI_GP0_ACLK, + M_AXI_GP0_ARREADY, + M_AXI_GP0_AWREADY, + M_AXI_GP0_BVALID, + M_AXI_GP0_RLAST, + M_AXI_GP0_RVALID, + M_AXI_GP0_WREADY, + M_AXI_GP0_BID, + M_AXI_GP0_RID, + M_AXI_GP0_BRESP, + M_AXI_GP0_RRESP, + M_AXI_GP0_RDATA, + S_AXI_HP0_ARREADY, + S_AXI_HP0_AWREADY, + S_AXI_HP0_BVALID, + S_AXI_HP0_RLAST, + S_AXI_HP0_RVALID, + S_AXI_HP0_WREADY, + S_AXI_HP0_BRESP, + S_AXI_HP0_RRESP, + S_AXI_HP0_BID, + S_AXI_HP0_RID, + S_AXI_HP0_RDATA, + S_AXI_HP0_RCOUNT, + S_AXI_HP0_WCOUNT, + S_AXI_HP0_RACOUNT, + S_AXI_HP0_WACOUNT, + S_AXI_HP0_ACLK, + S_AXI_HP0_ARVALID, + S_AXI_HP0_AWVALID, + S_AXI_HP0_BREADY, + S_AXI_HP0_RDISSUECAP1_EN, + S_AXI_HP0_RREADY, + S_AXI_HP0_WLAST, + S_AXI_HP0_WRISSUECAP1_EN, + S_AXI_HP0_WVALID, + S_AXI_HP0_ARBURST, + S_AXI_HP0_ARLOCK, + S_AXI_HP0_ARSIZE, + S_AXI_HP0_AWBURST, + S_AXI_HP0_AWLOCK, + S_AXI_HP0_AWSIZE, + S_AXI_HP0_ARPROT, + S_AXI_HP0_AWPROT, + S_AXI_HP0_ARADDR, + S_AXI_HP0_AWADDR, + S_AXI_HP0_ARCACHE, + S_AXI_HP0_ARLEN, + S_AXI_HP0_ARQOS, + S_AXI_HP0_AWCACHE, + S_AXI_HP0_AWLEN, + S_AXI_HP0_AWQOS, + S_AXI_HP0_ARID, + S_AXI_HP0_AWID, + S_AXI_HP0_WID, + S_AXI_HP0_WDATA, + S_AXI_HP0_WSTRB, + IRQ_F2P, + FCLK_CLK0, + FCLK_RESET0_N, + MIO, + DDR_CAS_n, + DDR_CKE, + DDR_Clk_n, + DDR_Clk, + DDR_CS_n, + DDR_DRSTB, + DDR_ODT, + DDR_RAS_n, + DDR_WEB, + DDR_BankAddr, + DDR_Addr, + DDR_VRN, + DDR_VRP, + DDR_DM, + DDR_DQ, + DDR_DQS_n, + DDR_DQS, + PS_SRSTB, + PS_CLK, + PS_PORB); + (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_I" *) input I2C0_SDA_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_O" *) output I2C0_SDA_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SDA_T" *) output I2C0_SDA_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_I" *) input I2C0_SCL_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_O" *) output I2C0_SCL_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_T" *) output I2C0_SCL_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SCK_I" *) input SPI1_SCLK_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SCK_O" *) output SPI1_SCLK_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SCK_T" *) output SPI1_SCLK_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO0_I" *) input SPI1_MOSI_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO0_O" *) output SPI1_MOSI_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO0_T" *) output SPI1_MOSI_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO1_I" *) input SPI1_MISO_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO1_O" *) output SPI1_MISO_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO1_T" *) output SPI1_MISO_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS_I" *) input SPI1_SS_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS_O" *) output SPI1_SS_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS1_O" *) output SPI1_SS1_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS2_O" *) output SPI1_SS2_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS_T" *) output SPI1_SS_T; + output TTC0_WAVE0_OUT; + output TTC0_WAVE1_OUT; + output TTC0_WAVE2_OUT; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL" *) output [1:0]USB0_PORT_INDCTL; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT" *) output USB0_VBUS_PWRSELECT; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT" *) input USB0_VBUS_PWRFAULT; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID" *) output M_AXI_GP0_ARVALID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID" *) output M_AXI_GP0_AWVALID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY" *) output M_AXI_GP0_BREADY; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY" *) output M_AXI_GP0_RREADY; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST" *) output M_AXI_GP0_WLAST; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID" *) output M_AXI_GP0_WVALID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID" *) output [11:0]M_AXI_GP0_ARID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID" *) output [11:0]M_AXI_GP0_AWID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID" *) output [11:0]M_AXI_GP0_WID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST" *) output [1:0]M_AXI_GP0_ARBURST; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK" *) output [1:0]M_AXI_GP0_ARLOCK; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE" *) output [2:0]M_AXI_GP0_ARSIZE; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST" *) output [1:0]M_AXI_GP0_AWBURST; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK" *) output [1:0]M_AXI_GP0_AWLOCK; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE" *) output [2:0]M_AXI_GP0_AWSIZE; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT" *) output [2:0]M_AXI_GP0_ARPROT; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT" *) output [2:0]M_AXI_GP0_AWPROT; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR" *) output [31:0]M_AXI_GP0_ARADDR; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR" *) output [31:0]M_AXI_GP0_AWADDR; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA" *) output [31:0]M_AXI_GP0_WDATA; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE" *) output [3:0]M_AXI_GP0_ARCACHE; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN" *) output [3:0]M_AXI_GP0_ARLEN; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS" *) output [3:0]M_AXI_GP0_ARQOS; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE" *) output [3:0]M_AXI_GP0_AWCACHE; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN" *) output [3:0]M_AXI_GP0_AWLEN; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS" *) output [3:0]M_AXI_GP0_AWQOS; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB" *) output [3:0]M_AXI_GP0_WSTRB; + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 99999999, PHASE 0.000, CLK_DOMAIN mz_petalinux_processing_system7_0_0_FCLK_CLK0" *) input M_AXI_GP0_ACLK; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY" *) input M_AXI_GP0_ARREADY; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY" *) input M_AXI_GP0_AWREADY; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID" *) input M_AXI_GP0_BVALID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST" *) input M_AXI_GP0_RLAST; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID" *) input M_AXI_GP0_RVALID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY" *) input M_AXI_GP0_WREADY; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID" *) input [11:0]M_AXI_GP0_BID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID" *) input [11:0]M_AXI_GP0_RID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP" *) input [1:0]M_AXI_GP0_BRESP; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP" *) input [1:0]M_AXI_GP0_RRESP; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 99999999, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN mz_petalinux_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input [31:0]M_AXI_GP0_RDATA; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARREADY" *) output S_AXI_HP0_ARREADY; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWREADY" *) output S_AXI_HP0_AWREADY; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BVALID" *) output S_AXI_HP0_BVALID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RLAST" *) output S_AXI_HP0_RLAST; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RVALID" *) output S_AXI_HP0_RVALID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WREADY" *) output S_AXI_HP0_WREADY; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BRESP" *) output [1:0]S_AXI_HP0_BRESP; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RRESP" *) output [1:0]S_AXI_HP0_RRESP; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BID" *) output [5:0]S_AXI_HP0_BID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RID" *) output [5:0]S_AXI_HP0_RID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RDATA" *) output [63:0]S_AXI_HP0_RDATA; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RCOUNT" *) output [7:0]S_AXI_HP0_RCOUNT; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WCOUNT" *) output [7:0]S_AXI_HP0_WCOUNT; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RACOUNT" *) output [2:0]S_AXI_HP0_RACOUNT; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WACOUNT" *) output [5:0]S_AXI_HP0_WACOUNT; + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 S_AXI_HP0_ACLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI_HP0_ACLK, ASSOCIATED_BUSIF S_AXI_HP0, FREQ_HZ 99999999, PHASE 0.000, CLK_DOMAIN mz_petalinux_processing_system7_0_0_FCLK_CLK0" *) input S_AXI_HP0_ACLK; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARVALID" *) input S_AXI_HP0_ARVALID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWVALID" *) input S_AXI_HP0_AWVALID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BREADY" *) input S_AXI_HP0_BREADY; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RDISSUECAPEN" *) input S_AXI_HP0_RDISSUECAP1_EN; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RREADY" *) input S_AXI_HP0_RREADY; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WLAST" *) input S_AXI_HP0_WLAST; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WRISSUECAPEN" *) input S_AXI_HP0_WRISSUECAP1_EN; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WVALID" *) input S_AXI_HP0_WVALID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARBURST" *) input [1:0]S_AXI_HP0_ARBURST; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARLOCK" *) input [1:0]S_AXI_HP0_ARLOCK; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARSIZE" *) input [2:0]S_AXI_HP0_ARSIZE; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWBURST" *) input [1:0]S_AXI_HP0_AWBURST; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWLOCK" *) input [1:0]S_AXI_HP0_AWLOCK; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWSIZE" *) input [2:0]S_AXI_HP0_AWSIZE; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARPROT" *) input [2:0]S_AXI_HP0_ARPROT; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWPROT" *) input [2:0]S_AXI_HP0_AWPROT; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARADDR" *) input [31:0]S_AXI_HP0_ARADDR; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWADDR" *) input [31:0]S_AXI_HP0_AWADDR; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARCACHE" *) input [3:0]S_AXI_HP0_ARCACHE; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARLEN" *) input [3:0]S_AXI_HP0_ARLEN; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARQOS" *) input [3:0]S_AXI_HP0_ARQOS; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWCACHE" *) input [3:0]S_AXI_HP0_AWCACHE; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWLEN" *) input [3:0]S_AXI_HP0_AWLEN; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWQOS" *) input [3:0]S_AXI_HP0_AWQOS; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARID" *) input [5:0]S_AXI_HP0_ARID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWID" *) input [5:0]S_AXI_HP0_AWID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WID" *) input [5:0]S_AXI_HP0_WID; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WDATA" *) input [63:0]S_AXI_HP0_WDATA; + (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WSTRB" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI_HP0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 64, PROTOCOL AXI3, FREQ_HZ 99999999, ID_WIDTH 6, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, MAX_BURST_LENGTH 8, PHASE 0.000, CLK_DOMAIN mz_petalinux_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input [7:0]S_AXI_HP0_WSTRB; + (* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH:NULL, PortWidth 2" *) input [1:0]IRQ_F2P; + (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 99999999, PHASE 0.000, CLK_DOMAIN mz_petalinux_processing_system7_0_0_FCLK_CLK0" *) output FCLK_CLK0; + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW" *) output FCLK_RESET0_N; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CAS_N" *) inout DDR_CAS_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CKE" *) inout DDR_CKE; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_N" *) inout DDR_Clk_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CK_P" *) inout DDR_Clk; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR CS_N" *) inout DDR_CS_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RESET_N" *) inout DDR_DRSTB; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ODT" *) inout DDR_ODT; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR RAS_N" *) inout DDR_RAS_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR WE_N" *) inout DDR_WEB; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR BA" *) inout [2:0]DDR_BankAddr; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR ADDR" *) inout [14:0]DDR_Addr; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN" *) inout DDR_VRN; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP" *) inout DDR_VRP; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DM" *) inout [3:0]DDR_DM; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQ" *) inout [31:0]DDR_DQ; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_N" *) inout [3:0]DDR_DQS_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 DDR DQS_P" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11" *) inout [3:0]DDR_DQS; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB" *) inout PS_SRSTB; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK" *) inout PS_CLK; + (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false" *) inout PS_PORB; + + wire [14:0]DDR_Addr; + wire [2:0]DDR_BankAddr; + wire DDR_CAS_n; + wire DDR_CKE; + wire DDR_CS_n; + wire DDR_Clk; + wire DDR_Clk_n; + wire [3:0]DDR_DM; + wire [31:0]DDR_DQ; + wire [3:0]DDR_DQS; + wire [3:0]DDR_DQS_n; + wire DDR_DRSTB; + wire DDR_ODT; + wire DDR_RAS_n; + wire DDR_VRN; + wire DDR_VRP; + wire DDR_WEB; + wire FCLK_CLK0; + wire FCLK_RESET0_N; + wire I2C0_SCL_I; + wire I2C0_SCL_O; + wire I2C0_SCL_T; + wire I2C0_SDA_I; + wire I2C0_SDA_O; + wire I2C0_SDA_T; + wire [1:0]IRQ_F2P; + wire [53:0]MIO; + wire M_AXI_GP0_ACLK; + wire [31:0]M_AXI_GP0_ARADDR; + wire [1:0]M_AXI_GP0_ARBURST; + wire [3:0]M_AXI_GP0_ARCACHE; + wire [11:0]M_AXI_GP0_ARID; + wire [3:0]M_AXI_GP0_ARLEN; + wire [1:0]M_AXI_GP0_ARLOCK; + wire [2:0]M_AXI_GP0_ARPROT; + wire [3:0]M_AXI_GP0_ARQOS; + wire M_AXI_GP0_ARREADY; + wire [2:0]M_AXI_GP0_ARSIZE; + wire M_AXI_GP0_ARVALID; + wire [31:0]M_AXI_GP0_AWADDR; + wire [1:0]M_AXI_GP0_AWBURST; + wire [3:0]M_AXI_GP0_AWCACHE; + wire [11:0]M_AXI_GP0_AWID; + wire [3:0]M_AXI_GP0_AWLEN; + wire [1:0]M_AXI_GP0_AWLOCK; + wire [2:0]M_AXI_GP0_AWPROT; + wire [3:0]M_AXI_GP0_AWQOS; + wire M_AXI_GP0_AWREADY; + wire [2:0]M_AXI_GP0_AWSIZE; + wire M_AXI_GP0_AWVALID; + wire [11:0]M_AXI_GP0_BID; + wire M_AXI_GP0_BREADY; + wire [1:0]M_AXI_GP0_BRESP; + wire M_AXI_GP0_BVALID; + wire [31:0]M_AXI_GP0_RDATA; + wire [11:0]M_AXI_GP0_RID; + wire M_AXI_GP0_RLAST; + wire M_AXI_GP0_RREADY; + wire [1:0]M_AXI_GP0_RRESP; + wire M_AXI_GP0_RVALID; + wire [31:0]M_AXI_GP0_WDATA; + wire [11:0]M_AXI_GP0_WID; + wire M_AXI_GP0_WLAST; + wire M_AXI_GP0_WREADY; + wire [3:0]M_AXI_GP0_WSTRB; + wire M_AXI_GP0_WVALID; + wire PS_CLK; + wire PS_PORB; + wire PS_SRSTB; + wire SPI1_MISO_I; + wire SPI1_MISO_O; + wire SPI1_MISO_T; + wire SPI1_MOSI_I; + wire SPI1_MOSI_O; + wire SPI1_MOSI_T; + wire SPI1_SCLK_I; + wire SPI1_SCLK_O; + wire SPI1_SCLK_T; + wire SPI1_SS1_O; + wire SPI1_SS2_O; + wire SPI1_SS_I; + wire SPI1_SS_O; + wire SPI1_SS_T; + wire S_AXI_HP0_ACLK; + wire [31:0]S_AXI_HP0_ARADDR; + wire [1:0]S_AXI_HP0_ARBURST; + wire [3:0]S_AXI_HP0_ARCACHE; + wire [5:0]S_AXI_HP0_ARID; + wire [3:0]S_AXI_HP0_ARLEN; + wire [1:0]S_AXI_HP0_ARLOCK; + wire [2:0]S_AXI_HP0_ARPROT; + wire [3:0]S_AXI_HP0_ARQOS; + wire S_AXI_HP0_ARREADY; + wire [2:0]S_AXI_HP0_ARSIZE; + wire S_AXI_HP0_ARVALID; + wire [31:0]S_AXI_HP0_AWADDR; + wire [1:0]S_AXI_HP0_AWBURST; + wire [3:0]S_AXI_HP0_AWCACHE; + wire [5:0]S_AXI_HP0_AWID; + wire [3:0]S_AXI_HP0_AWLEN; + wire [1:0]S_AXI_HP0_AWLOCK; + wire [2:0]S_AXI_HP0_AWPROT; + wire [3:0]S_AXI_HP0_AWQOS; + wire S_AXI_HP0_AWREADY; + wire [2:0]S_AXI_HP0_AWSIZE; + wire S_AXI_HP0_AWVALID; + wire [5:0]S_AXI_HP0_BID; + wire S_AXI_HP0_BREADY; + wire [1:0]S_AXI_HP0_BRESP; + wire S_AXI_HP0_BVALID; + wire [2:0]S_AXI_HP0_RACOUNT; + wire [7:0]S_AXI_HP0_RCOUNT; + wire [63:0]S_AXI_HP0_RDATA; + wire S_AXI_HP0_RDISSUECAP1_EN; + wire [5:0]S_AXI_HP0_RID; + wire S_AXI_HP0_RLAST; + wire S_AXI_HP0_RREADY; + wire [1:0]S_AXI_HP0_RRESP; + wire S_AXI_HP0_RVALID; + wire [5:0]S_AXI_HP0_WACOUNT; + wire [7:0]S_AXI_HP0_WCOUNT; + wire [63:0]S_AXI_HP0_WDATA; + wire [5:0]S_AXI_HP0_WID; + wire S_AXI_HP0_WLAST; + wire S_AXI_HP0_WREADY; + wire S_AXI_HP0_WRISSUECAP1_EN; + wire [7:0]S_AXI_HP0_WSTRB; + wire S_AXI_HP0_WVALID; + wire TTC0_WAVE0_OUT; + wire TTC0_WAVE1_OUT; + wire TTC0_WAVE2_OUT; + wire [1:0]USB0_PORT_INDCTL; + wire USB0_VBUS_PWRFAULT; + wire USB0_VBUS_PWRSELECT; + wire NLW_inst_CAN0_PHY_TX_UNCONNECTED; + wire NLW_inst_CAN1_PHY_TX_UNCONNECTED; + wire NLW_inst_DMA0_DAVALID_UNCONNECTED; + wire NLW_inst_DMA0_DRREADY_UNCONNECTED; + wire NLW_inst_DMA0_RSTN_UNCONNECTED; + wire NLW_inst_DMA1_DAVALID_UNCONNECTED; + wire NLW_inst_DMA1_DRREADY_UNCONNECTED; + wire NLW_inst_DMA1_RSTN_UNCONNECTED; + wire NLW_inst_DMA2_DAVALID_UNCONNECTED; + wire NLW_inst_DMA2_DRREADY_UNCONNECTED; + wire NLW_inst_DMA2_RSTN_UNCONNECTED; + wire NLW_inst_DMA3_DAVALID_UNCONNECTED; + wire NLW_inst_DMA3_DRREADY_UNCONNECTED; + wire NLW_inst_DMA3_RSTN_UNCONNECTED; + wire NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED; + wire NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED; + wire NLW_inst_ENET0_MDIO_MDC_UNCONNECTED; + wire NLW_inst_ENET0_MDIO_O_UNCONNECTED; + wire NLW_inst_ENET0_MDIO_T_UNCONNECTED; + wire NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED; + wire NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED; + wire NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED; + wire NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED; + wire NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED; + wire NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED; + wire NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED; + wire NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED; + wire NLW_inst_ENET0_SOF_RX_UNCONNECTED; + wire NLW_inst_ENET0_SOF_TX_UNCONNECTED; + wire NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED; + wire NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED; + wire NLW_inst_ENET1_MDIO_MDC_UNCONNECTED; + wire NLW_inst_ENET1_MDIO_O_UNCONNECTED; + wire NLW_inst_ENET1_MDIO_T_UNCONNECTED; + wire NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED; + wire NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED; + wire NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED; + wire NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED; + wire NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED; + wire NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED; + wire NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED; + wire NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED; + wire NLW_inst_ENET1_SOF_RX_UNCONNECTED; + wire NLW_inst_ENET1_SOF_TX_UNCONNECTED; + wire NLW_inst_EVENT_EVENTO_UNCONNECTED; + wire NLW_inst_FCLK_CLK1_UNCONNECTED; + wire NLW_inst_FCLK_CLK2_UNCONNECTED; + wire NLW_inst_FCLK_CLK3_UNCONNECTED; + wire NLW_inst_FCLK_RESET1_N_UNCONNECTED; + wire NLW_inst_FCLK_RESET2_N_UNCONNECTED; + wire NLW_inst_FCLK_RESET3_N_UNCONNECTED; + wire NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED; + wire NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED; + wire NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED; + wire NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED; + wire NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED; + wire NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED; + wire NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED; + wire NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED; + wire NLW_inst_I2C1_SCL_O_UNCONNECTED; + wire NLW_inst_I2C1_SCL_T_UNCONNECTED; + wire NLW_inst_I2C1_SDA_O_UNCONNECTED; + wire NLW_inst_I2C1_SDA_T_UNCONNECTED; + wire NLW_inst_IRQ_P2F_CAN0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_CAN1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_CTI_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED; + wire NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED; + wire NLW_inst_IRQ_P2F_ENET0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_ENET1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_GPIO_UNCONNECTED; + wire NLW_inst_IRQ_P2F_I2C0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_I2C1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_QSPI_UNCONNECTED; + wire NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_SMC_UNCONNECTED; + wire NLW_inst_IRQ_P2F_SPI0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_SPI1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_UART0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_UART1_UNCONNECTED; + wire NLW_inst_IRQ_P2F_USB0_UNCONNECTED; + wire NLW_inst_IRQ_P2F_USB1_UNCONNECTED; + wire NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED; + wire NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED; + wire NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED; + wire NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED; + wire NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED; + wire NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED; + wire NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED; + wire NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED; + wire NLW_inst_PJTAG_TDO_UNCONNECTED; + wire NLW_inst_SDIO0_BUSPOW_UNCONNECTED; + wire NLW_inst_SDIO0_CLK_UNCONNECTED; + wire NLW_inst_SDIO0_CMD_O_UNCONNECTED; + wire NLW_inst_SDIO0_CMD_T_UNCONNECTED; + wire NLW_inst_SDIO0_LED_UNCONNECTED; + wire NLW_inst_SDIO1_BUSPOW_UNCONNECTED; + wire NLW_inst_SDIO1_CLK_UNCONNECTED; + wire NLW_inst_SDIO1_CMD_O_UNCONNECTED; + wire NLW_inst_SDIO1_CMD_T_UNCONNECTED; + wire NLW_inst_SDIO1_LED_UNCONNECTED; + wire NLW_inst_SPI0_MISO_O_UNCONNECTED; + wire NLW_inst_SPI0_MISO_T_UNCONNECTED; + wire NLW_inst_SPI0_MOSI_O_UNCONNECTED; + wire NLW_inst_SPI0_MOSI_T_UNCONNECTED; + wire NLW_inst_SPI0_SCLK_O_UNCONNECTED; + wire NLW_inst_SPI0_SCLK_T_UNCONNECTED; + wire NLW_inst_SPI0_SS1_O_UNCONNECTED; + wire NLW_inst_SPI0_SS2_O_UNCONNECTED; + wire NLW_inst_SPI0_SS_O_UNCONNECTED; + wire NLW_inst_SPI0_SS_T_UNCONNECTED; + wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED; + wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED; + wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED; + wire NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED; + wire NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED; + wire NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED; + wire NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED; + wire NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED; + wire NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED; + wire NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED; + wire NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED; + wire NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED; + wire NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED; + wire NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED; + wire NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED; + wire NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED; + wire NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED; + wire NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED; + wire NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED; + wire NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED; + wire NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED; + wire NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED; + wire NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED; + wire NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED; + wire NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED; + wire NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED; + wire NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED; + wire NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED; + wire NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED; + wire NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED; + wire NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED; + wire NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED; + wire NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED; + wire NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED; + wire NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED; + wire NLW_inst_TRACE_CLK_OUT_UNCONNECTED; + wire NLW_inst_TRACE_CTL_UNCONNECTED; + wire NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED; + wire NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED; + wire NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED; + wire NLW_inst_UART0_DTRN_UNCONNECTED; + wire NLW_inst_UART0_RTSN_UNCONNECTED; + wire NLW_inst_UART0_TX_UNCONNECTED; + wire NLW_inst_UART1_DTRN_UNCONNECTED; + wire NLW_inst_UART1_RTSN_UNCONNECTED; + wire NLW_inst_UART1_TX_UNCONNECTED; + wire NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED; + wire NLW_inst_WDT_RST_OUT_UNCONNECTED; + wire [1:0]NLW_inst_DMA0_DATYPE_UNCONNECTED; + wire [1:0]NLW_inst_DMA1_DATYPE_UNCONNECTED; + wire [1:0]NLW_inst_DMA2_DATYPE_UNCONNECTED; + wire [1:0]NLW_inst_DMA3_DATYPE_UNCONNECTED; + wire [7:0]NLW_inst_ENET0_GMII_TXD_UNCONNECTED; + wire [7:0]NLW_inst_ENET1_GMII_TXD_UNCONNECTED; + wire [1:0]NLW_inst_EVENT_STANDBYWFE_UNCONNECTED; + wire [1:0]NLW_inst_EVENT_STANDBYWFI_UNCONNECTED; + wire [31:0]NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED; + wire [63:0]NLW_inst_GPIO_O_UNCONNECTED; + wire [63:0]NLW_inst_GPIO_T_UNCONNECTED; + wire [31:0]NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED; + wire [1:0]NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED; + wire [3:0]NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED; + wire [11:0]NLW_inst_M_AXI_GP1_ARID_UNCONNECTED; + wire [3:0]NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED; + wire [1:0]NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED; + wire [2:0]NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED; + wire [3:0]NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED; + wire [2:0]NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED; + wire [31:0]NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED; + wire [1:0]NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED; + wire [3:0]NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED; + wire [11:0]NLW_inst_M_AXI_GP1_AWID_UNCONNECTED; + wire [3:0]NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED; + wire [1:0]NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED; + wire [2:0]NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED; + wire [3:0]NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED; + wire [2:0]NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED; + wire [31:0]NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED; + wire [11:0]NLW_inst_M_AXI_GP1_WID_UNCONNECTED; + wire [3:0]NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED; + wire [2:0]NLW_inst_SDIO0_BUSVOLT_UNCONNECTED; + wire [3:0]NLW_inst_SDIO0_DATA_O_UNCONNECTED; + wire [3:0]NLW_inst_SDIO0_DATA_T_UNCONNECTED; + wire [2:0]NLW_inst_SDIO1_BUSVOLT_UNCONNECTED; + wire [3:0]NLW_inst_SDIO1_DATA_O_UNCONNECTED; + wire [3:0]NLW_inst_SDIO1_DATA_T_UNCONNECTED; + wire [2:0]NLW_inst_S_AXI_ACP_BID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED; + wire [63:0]NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED; + wire [2:0]NLW_inst_S_AXI_ACP_RID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_GP0_BID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED; + wire [31:0]NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_GP0_RID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_GP1_BID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED; + wire [31:0]NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_GP1_RID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP1_BID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED; + wire [2:0]NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED; + wire [7:0]NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED; + wire [63:0]NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP1_RID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED; + wire [7:0]NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP2_BID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED; + wire [2:0]NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED; + wire [7:0]NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED; + wire [63:0]NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP2_RID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED; + wire [7:0]NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP3_BID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED; + wire [2:0]NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED; + wire [7:0]NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED; + wire [63:0]NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP3_RID_UNCONNECTED; + wire [1:0]NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED; + wire [5:0]NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED; + wire [7:0]NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED; + wire [1:0]NLW_inst_TRACE_DATA_UNCONNECTED; + wire [1:0]NLW_inst_USB1_PORT_INDCTL_UNCONNECTED; + + (* C_DM_WIDTH = "4" *) + (* C_DQS_WIDTH = "4" *) + (* C_DQ_WIDTH = "32" *) + (* C_EMIO_GPIO_WIDTH = "64" *) + (* C_EN_EMIO_ENET0 = "0" *) + (* C_EN_EMIO_ENET1 = "0" *) + (* C_EN_EMIO_PJTAG = "0" *) + (* C_EN_EMIO_TRACE = "0" *) + (* C_FCLK_CLK0_BUF = "TRUE" *) + (* C_FCLK_CLK1_BUF = "FALSE" *) + (* C_FCLK_CLK2_BUF = "FALSE" *) + (* C_FCLK_CLK3_BUF = "FALSE" *) + (* C_GP0_EN_MODIFIABLE_TXN = "1" *) + (* C_GP1_EN_MODIFIABLE_TXN = "1" *) + (* C_INCLUDE_ACP_TRANS_CHECK = "0" *) + (* C_INCLUDE_TRACE_BUFFER = "0" *) + (* C_IRQ_F2P_MODE = "DIRECT" *) + (* C_MIO_PRIMITIVE = "54" *) + (* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) + (* C_M_AXI_GP0_ID_WIDTH = "12" *) + (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *) + (* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) + (* C_M_AXI_GP1_ID_WIDTH = "12" *) + (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *) + (* C_NUM_F2P_INTR_INPUTS = "2" *) + (* C_PACKAGE_NAME = "clg400" *) + (* C_PS7_SI_REV = "PRODUCTION" *) + (* C_S_AXI_ACP_ARUSER_VAL = "31" *) + (* C_S_AXI_ACP_AWUSER_VAL = "31" *) + (* C_S_AXI_ACP_ID_WIDTH = "3" *) + (* C_S_AXI_GP0_ID_WIDTH = "6" *) + (* C_S_AXI_GP1_ID_WIDTH = "6" *) + (* C_S_AXI_HP0_DATA_WIDTH = "64" *) + (* C_S_AXI_HP0_ID_WIDTH = "6" *) + (* C_S_AXI_HP1_DATA_WIDTH = "64" *) + (* C_S_AXI_HP1_ID_WIDTH = "6" *) + (* C_S_AXI_HP2_DATA_WIDTH = "64" *) + (* C_S_AXI_HP2_ID_WIDTH = "6" *) + (* C_S_AXI_HP3_DATA_WIDTH = "64" *) + (* C_S_AXI_HP3_ID_WIDTH = "6" *) + (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) + (* C_TRACE_BUFFER_FIFO_SIZE = "128" *) + (* C_TRACE_INTERNAL_WIDTH = "2" *) + (* C_TRACE_PIPELINE_WIDTH = "8" *) + (* C_USE_AXI_NONSECURE = "0" *) + (* C_USE_DEFAULT_ACP_USER_VAL = "0" *) + (* C_USE_M_AXI_GP0 = "1" *) + (* C_USE_M_AXI_GP1 = "0" *) + (* C_USE_S_AXI_ACP = "0" *) + (* C_USE_S_AXI_GP0 = "0" *) + (* C_USE_S_AXI_GP1 = "0" *) + (* C_USE_S_AXI_HP0 = "1" *) + (* C_USE_S_AXI_HP1 = "0" *) + (* C_USE_S_AXI_HP2 = "0" *) + (* C_USE_S_AXI_HP3 = "0" *) + (* HW_HANDOFF = "mz_petalinux_processing_system7_0_0.hwdef" *) + (* POWER = "/>" *) + (* USE_TRACE_DATA_EDGE_DETECTOR = "0" *) + decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 inst + (.CAN0_PHY_RX(1'b0), + .CAN0_PHY_TX(NLW_inst_CAN0_PHY_TX_UNCONNECTED), + .CAN1_PHY_RX(1'b0), + .CAN1_PHY_TX(NLW_inst_CAN1_PHY_TX_UNCONNECTED), + .Core0_nFIQ(1'b0), + .Core0_nIRQ(1'b0), + .Core1_nFIQ(1'b0), + .Core1_nIRQ(1'b0), + .DDR_ARB({1'b0,1'b0,1'b0,1'b0}), + .DDR_Addr(DDR_Addr), + .DDR_BankAddr(DDR_BankAddr), + .DDR_CAS_n(DDR_CAS_n), + .DDR_CKE(DDR_CKE), + .DDR_CS_n(DDR_CS_n), + .DDR_Clk(DDR_Clk), + .DDR_Clk_n(DDR_Clk_n), + .DDR_DM(DDR_DM), + .DDR_DQ(DDR_DQ), + .DDR_DQS(DDR_DQS), + .DDR_DQS_n(DDR_DQS_n), + .DDR_DRSTB(DDR_DRSTB), + .DDR_ODT(DDR_ODT), + .DDR_RAS_n(DDR_RAS_n), + .DDR_VRN(DDR_VRN), + .DDR_VRP(DDR_VRP), + .DDR_WEB(DDR_WEB), + .DMA0_ACLK(1'b0), + .DMA0_DAREADY(1'b0), + .DMA0_DATYPE(NLW_inst_DMA0_DATYPE_UNCONNECTED[1:0]), + .DMA0_DAVALID(NLW_inst_DMA0_DAVALID_UNCONNECTED), + .DMA0_DRLAST(1'b0), + .DMA0_DRREADY(NLW_inst_DMA0_DRREADY_UNCONNECTED), + .DMA0_DRTYPE({1'b0,1'b0}), + .DMA0_DRVALID(1'b0), + .DMA0_RSTN(NLW_inst_DMA0_RSTN_UNCONNECTED), + .DMA1_ACLK(1'b0), + .DMA1_DAREADY(1'b0), + .DMA1_DATYPE(NLW_inst_DMA1_DATYPE_UNCONNECTED[1:0]), + .DMA1_DAVALID(NLW_inst_DMA1_DAVALID_UNCONNECTED), + .DMA1_DRLAST(1'b0), + .DMA1_DRREADY(NLW_inst_DMA1_DRREADY_UNCONNECTED), + .DMA1_DRTYPE({1'b0,1'b0}), + .DMA1_DRVALID(1'b0), + .DMA1_RSTN(NLW_inst_DMA1_RSTN_UNCONNECTED), + .DMA2_ACLK(1'b0), + .DMA2_DAREADY(1'b0), + .DMA2_DATYPE(NLW_inst_DMA2_DATYPE_UNCONNECTED[1:0]), + .DMA2_DAVALID(NLW_inst_DMA2_DAVALID_UNCONNECTED), + .DMA2_DRLAST(1'b0), + .DMA2_DRREADY(NLW_inst_DMA2_DRREADY_UNCONNECTED), + .DMA2_DRTYPE({1'b0,1'b0}), + .DMA2_DRVALID(1'b0), + .DMA2_RSTN(NLW_inst_DMA2_RSTN_UNCONNECTED), + .DMA3_ACLK(1'b0), + .DMA3_DAREADY(1'b0), + .DMA3_DATYPE(NLW_inst_DMA3_DATYPE_UNCONNECTED[1:0]), + .DMA3_DAVALID(NLW_inst_DMA3_DAVALID_UNCONNECTED), + .DMA3_DRLAST(1'b0), + .DMA3_DRREADY(NLW_inst_DMA3_DRREADY_UNCONNECTED), + .DMA3_DRTYPE({1'b0,1'b0}), + .DMA3_DRVALID(1'b0), + .DMA3_RSTN(NLW_inst_DMA3_RSTN_UNCONNECTED), + .ENET0_EXT_INTIN(1'b0), + .ENET0_GMII_COL(1'b0), + .ENET0_GMII_CRS(1'b0), + .ENET0_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .ENET0_GMII_RX_CLK(1'b0), + .ENET0_GMII_RX_DV(1'b0), + .ENET0_GMII_RX_ER(1'b0), + .ENET0_GMII_TXD(NLW_inst_ENET0_GMII_TXD_UNCONNECTED[7:0]), + .ENET0_GMII_TX_CLK(1'b0), + .ENET0_GMII_TX_EN(NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED), + .ENET0_GMII_TX_ER(NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED), + .ENET0_MDIO_I(1'b0), + .ENET0_MDIO_MDC(NLW_inst_ENET0_MDIO_MDC_UNCONNECTED), + .ENET0_MDIO_O(NLW_inst_ENET0_MDIO_O_UNCONNECTED), + .ENET0_MDIO_T(NLW_inst_ENET0_MDIO_T_UNCONNECTED), + .ENET0_PTP_DELAY_REQ_RX(NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED), + .ENET0_PTP_DELAY_REQ_TX(NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED), + .ENET0_PTP_PDELAY_REQ_RX(NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED), + .ENET0_PTP_PDELAY_REQ_TX(NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED), + .ENET0_PTP_PDELAY_RESP_RX(NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED), + .ENET0_PTP_PDELAY_RESP_TX(NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED), + .ENET0_PTP_SYNC_FRAME_RX(NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED), + .ENET0_PTP_SYNC_FRAME_TX(NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED), + .ENET0_SOF_RX(NLW_inst_ENET0_SOF_RX_UNCONNECTED), + .ENET0_SOF_TX(NLW_inst_ENET0_SOF_TX_UNCONNECTED), + .ENET1_EXT_INTIN(1'b0), + .ENET1_GMII_COL(1'b0), + .ENET1_GMII_CRS(1'b0), + .ENET1_GMII_RXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .ENET1_GMII_RX_CLK(1'b0), + .ENET1_GMII_RX_DV(1'b0), + .ENET1_GMII_RX_ER(1'b0), + .ENET1_GMII_TXD(NLW_inst_ENET1_GMII_TXD_UNCONNECTED[7:0]), + .ENET1_GMII_TX_CLK(1'b0), + .ENET1_GMII_TX_EN(NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED), + .ENET1_GMII_TX_ER(NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED), + .ENET1_MDIO_I(1'b0), + .ENET1_MDIO_MDC(NLW_inst_ENET1_MDIO_MDC_UNCONNECTED), + .ENET1_MDIO_O(NLW_inst_ENET1_MDIO_O_UNCONNECTED), + .ENET1_MDIO_T(NLW_inst_ENET1_MDIO_T_UNCONNECTED), + .ENET1_PTP_DELAY_REQ_RX(NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED), + .ENET1_PTP_DELAY_REQ_TX(NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED), + .ENET1_PTP_PDELAY_REQ_RX(NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED), + .ENET1_PTP_PDELAY_REQ_TX(NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED), + .ENET1_PTP_PDELAY_RESP_RX(NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED), + .ENET1_PTP_PDELAY_RESP_TX(NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED), + .ENET1_PTP_SYNC_FRAME_RX(NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED), + .ENET1_PTP_SYNC_FRAME_TX(NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED), + .ENET1_SOF_RX(NLW_inst_ENET1_SOF_RX_UNCONNECTED), + .ENET1_SOF_TX(NLW_inst_ENET1_SOF_TX_UNCONNECTED), + .EVENT_EVENTI(1'b0), + .EVENT_EVENTO(NLW_inst_EVENT_EVENTO_UNCONNECTED), + .EVENT_STANDBYWFE(NLW_inst_EVENT_STANDBYWFE_UNCONNECTED[1:0]), + .EVENT_STANDBYWFI(NLW_inst_EVENT_STANDBYWFI_UNCONNECTED[1:0]), + .FCLK_CLK0(FCLK_CLK0), + .FCLK_CLK1(NLW_inst_FCLK_CLK1_UNCONNECTED), + .FCLK_CLK2(NLW_inst_FCLK_CLK2_UNCONNECTED), + .FCLK_CLK3(NLW_inst_FCLK_CLK3_UNCONNECTED), + .FCLK_CLKTRIG0_N(1'b0), + .FCLK_CLKTRIG1_N(1'b0), + .FCLK_CLKTRIG2_N(1'b0), + .FCLK_CLKTRIG3_N(1'b0), + .FCLK_RESET0_N(FCLK_RESET0_N), + .FCLK_RESET1_N(NLW_inst_FCLK_RESET1_N_UNCONNECTED), + .FCLK_RESET2_N(NLW_inst_FCLK_RESET2_N_UNCONNECTED), + .FCLK_RESET3_N(NLW_inst_FCLK_RESET3_N_UNCONNECTED), + .FPGA_IDLE_N(1'b0), + .FTMD_TRACEIN_ATID({1'b0,1'b0,1'b0,1'b0}), + .FTMD_TRACEIN_CLK(1'b0), + .FTMD_TRACEIN_DATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .FTMD_TRACEIN_VALID(1'b0), + .FTMT_F2P_DEBUG({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .FTMT_F2P_TRIGACK_0(NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED), + .FTMT_F2P_TRIGACK_1(NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED), + .FTMT_F2P_TRIGACK_2(NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED), + .FTMT_F2P_TRIGACK_3(NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED), + .FTMT_F2P_TRIG_0(1'b0), + .FTMT_F2P_TRIG_1(1'b0), + .FTMT_F2P_TRIG_2(1'b0), + .FTMT_F2P_TRIG_3(1'b0), + .FTMT_P2F_DEBUG(NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED[31:0]), + .FTMT_P2F_TRIGACK_0(1'b0), + .FTMT_P2F_TRIGACK_1(1'b0), + .FTMT_P2F_TRIGACK_2(1'b0), + .FTMT_P2F_TRIGACK_3(1'b0), + .FTMT_P2F_TRIG_0(NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED), + .FTMT_P2F_TRIG_1(NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED), + .FTMT_P2F_TRIG_2(NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED), + .FTMT_P2F_TRIG_3(NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED), + .GPIO_I({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .GPIO_O(NLW_inst_GPIO_O_UNCONNECTED[63:0]), + .GPIO_T(NLW_inst_GPIO_T_UNCONNECTED[63:0]), + .I2C0_SCL_I(I2C0_SCL_I), + .I2C0_SCL_O(I2C0_SCL_O), + .I2C0_SCL_T(I2C0_SCL_T), + .I2C0_SDA_I(I2C0_SDA_I), + .I2C0_SDA_O(I2C0_SDA_O), + .I2C0_SDA_T(I2C0_SDA_T), + .I2C1_SCL_I(1'b0), + .I2C1_SCL_O(NLW_inst_I2C1_SCL_O_UNCONNECTED), + .I2C1_SCL_T(NLW_inst_I2C1_SCL_T_UNCONNECTED), + .I2C1_SDA_I(1'b0), + .I2C1_SDA_O(NLW_inst_I2C1_SDA_O_UNCONNECTED), + .I2C1_SDA_T(NLW_inst_I2C1_SDA_T_UNCONNECTED), + .IRQ_F2P(IRQ_F2P), + .IRQ_P2F_CAN0(NLW_inst_IRQ_P2F_CAN0_UNCONNECTED), + .IRQ_P2F_CAN1(NLW_inst_IRQ_P2F_CAN1_UNCONNECTED), + .IRQ_P2F_CTI(NLW_inst_IRQ_P2F_CTI_UNCONNECTED), + .IRQ_P2F_DMAC0(NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED), + .IRQ_P2F_DMAC1(NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED), + .IRQ_P2F_DMAC2(NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED), + .IRQ_P2F_DMAC3(NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED), + .IRQ_P2F_DMAC4(NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED), + .IRQ_P2F_DMAC5(NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED), + .IRQ_P2F_DMAC6(NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED), + .IRQ_P2F_DMAC7(NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED), + .IRQ_P2F_DMAC_ABORT(NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED), + .IRQ_P2F_ENET0(NLW_inst_IRQ_P2F_ENET0_UNCONNECTED), + .IRQ_P2F_ENET1(NLW_inst_IRQ_P2F_ENET1_UNCONNECTED), + .IRQ_P2F_ENET_WAKE0(NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED), + .IRQ_P2F_ENET_WAKE1(NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED), + .IRQ_P2F_GPIO(NLW_inst_IRQ_P2F_GPIO_UNCONNECTED), + .IRQ_P2F_I2C0(NLW_inst_IRQ_P2F_I2C0_UNCONNECTED), + .IRQ_P2F_I2C1(NLW_inst_IRQ_P2F_I2C1_UNCONNECTED), + .IRQ_P2F_QSPI(NLW_inst_IRQ_P2F_QSPI_UNCONNECTED), + .IRQ_P2F_SDIO0(NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED), + .IRQ_P2F_SDIO1(NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED), + .IRQ_P2F_SMC(NLW_inst_IRQ_P2F_SMC_UNCONNECTED), + .IRQ_P2F_SPI0(NLW_inst_IRQ_P2F_SPI0_UNCONNECTED), + .IRQ_P2F_SPI1(NLW_inst_IRQ_P2F_SPI1_UNCONNECTED), + .IRQ_P2F_UART0(NLW_inst_IRQ_P2F_UART0_UNCONNECTED), + .IRQ_P2F_UART1(NLW_inst_IRQ_P2F_UART1_UNCONNECTED), + .IRQ_P2F_USB0(NLW_inst_IRQ_P2F_USB0_UNCONNECTED), + .IRQ_P2F_USB1(NLW_inst_IRQ_P2F_USB1_UNCONNECTED), + .MIO(MIO), + .M_AXI_GP0_ACLK(M_AXI_GP0_ACLK), + .M_AXI_GP0_ARADDR(M_AXI_GP0_ARADDR), + .M_AXI_GP0_ARBURST(M_AXI_GP0_ARBURST), + .M_AXI_GP0_ARCACHE(M_AXI_GP0_ARCACHE), + .M_AXI_GP0_ARESETN(NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED), + .M_AXI_GP0_ARID(M_AXI_GP0_ARID), + .M_AXI_GP0_ARLEN(M_AXI_GP0_ARLEN), + .M_AXI_GP0_ARLOCK(M_AXI_GP0_ARLOCK), + .M_AXI_GP0_ARPROT(M_AXI_GP0_ARPROT), + .M_AXI_GP0_ARQOS(M_AXI_GP0_ARQOS), + .M_AXI_GP0_ARREADY(M_AXI_GP0_ARREADY), + .M_AXI_GP0_ARSIZE(M_AXI_GP0_ARSIZE), + .M_AXI_GP0_ARVALID(M_AXI_GP0_ARVALID), + .M_AXI_GP0_AWADDR(M_AXI_GP0_AWADDR), + .M_AXI_GP0_AWBURST(M_AXI_GP0_AWBURST), + .M_AXI_GP0_AWCACHE(M_AXI_GP0_AWCACHE), + .M_AXI_GP0_AWID(M_AXI_GP0_AWID), + .M_AXI_GP0_AWLEN(M_AXI_GP0_AWLEN), + .M_AXI_GP0_AWLOCK(M_AXI_GP0_AWLOCK), + .M_AXI_GP0_AWPROT(M_AXI_GP0_AWPROT), + .M_AXI_GP0_AWQOS(M_AXI_GP0_AWQOS), + .M_AXI_GP0_AWREADY(M_AXI_GP0_AWREADY), + .M_AXI_GP0_AWSIZE(M_AXI_GP0_AWSIZE), + .M_AXI_GP0_AWVALID(M_AXI_GP0_AWVALID), + .M_AXI_GP0_BID(M_AXI_GP0_BID), + .M_AXI_GP0_BREADY(M_AXI_GP0_BREADY), + .M_AXI_GP0_BRESP(M_AXI_GP0_BRESP), + .M_AXI_GP0_BVALID(M_AXI_GP0_BVALID), + .M_AXI_GP0_RDATA(M_AXI_GP0_RDATA), + .M_AXI_GP0_RID(M_AXI_GP0_RID), + .M_AXI_GP0_RLAST(M_AXI_GP0_RLAST), + .M_AXI_GP0_RREADY(M_AXI_GP0_RREADY), + .M_AXI_GP0_RRESP(M_AXI_GP0_RRESP), + .M_AXI_GP0_RVALID(M_AXI_GP0_RVALID), + .M_AXI_GP0_WDATA(M_AXI_GP0_WDATA), + .M_AXI_GP0_WID(M_AXI_GP0_WID), + .M_AXI_GP0_WLAST(M_AXI_GP0_WLAST), + .M_AXI_GP0_WREADY(M_AXI_GP0_WREADY), + .M_AXI_GP0_WSTRB(M_AXI_GP0_WSTRB), + .M_AXI_GP0_WVALID(M_AXI_GP0_WVALID), + .M_AXI_GP1_ACLK(1'b0), + .M_AXI_GP1_ARADDR(NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED[31:0]), + .M_AXI_GP1_ARBURST(NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED[1:0]), + .M_AXI_GP1_ARCACHE(NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED[3:0]), + .M_AXI_GP1_ARESETN(NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED), + .M_AXI_GP1_ARID(NLW_inst_M_AXI_GP1_ARID_UNCONNECTED[11:0]), + .M_AXI_GP1_ARLEN(NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED[3:0]), + .M_AXI_GP1_ARLOCK(NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED[1:0]), + .M_AXI_GP1_ARPROT(NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED[2:0]), + .M_AXI_GP1_ARQOS(NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED[3:0]), + .M_AXI_GP1_ARREADY(1'b0), + .M_AXI_GP1_ARSIZE(NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED[2:0]), + .M_AXI_GP1_ARVALID(NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED), + .M_AXI_GP1_AWADDR(NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED[31:0]), + .M_AXI_GP1_AWBURST(NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED[1:0]), + .M_AXI_GP1_AWCACHE(NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED[3:0]), + .M_AXI_GP1_AWID(NLW_inst_M_AXI_GP1_AWID_UNCONNECTED[11:0]), + .M_AXI_GP1_AWLEN(NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED[3:0]), + .M_AXI_GP1_AWLOCK(NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED[1:0]), + .M_AXI_GP1_AWPROT(NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED[2:0]), + .M_AXI_GP1_AWQOS(NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED[3:0]), + .M_AXI_GP1_AWREADY(1'b0), + .M_AXI_GP1_AWSIZE(NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED[2:0]), + .M_AXI_GP1_AWVALID(NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED), + .M_AXI_GP1_BID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .M_AXI_GP1_BREADY(NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED), + .M_AXI_GP1_BRESP({1'b0,1'b0}), + .M_AXI_GP1_BVALID(1'b0), + .M_AXI_GP1_RDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .M_AXI_GP1_RID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .M_AXI_GP1_RLAST(1'b0), + .M_AXI_GP1_RREADY(NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED), + .M_AXI_GP1_RRESP({1'b0,1'b0}), + .M_AXI_GP1_RVALID(1'b0), + .M_AXI_GP1_WDATA(NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED[31:0]), + .M_AXI_GP1_WID(NLW_inst_M_AXI_GP1_WID_UNCONNECTED[11:0]), + .M_AXI_GP1_WLAST(NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED), + .M_AXI_GP1_WREADY(1'b0), + .M_AXI_GP1_WSTRB(NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED[3:0]), + .M_AXI_GP1_WVALID(NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED), + .PJTAG_TCK(1'b0), + .PJTAG_TDI(1'b0), + .PJTAG_TDO(NLW_inst_PJTAG_TDO_UNCONNECTED), + .PJTAG_TMS(1'b0), + .PS_CLK(PS_CLK), + .PS_PORB(PS_PORB), + .PS_SRSTB(PS_SRSTB), + .SDIO0_BUSPOW(NLW_inst_SDIO0_BUSPOW_UNCONNECTED), + .SDIO0_BUSVOLT(NLW_inst_SDIO0_BUSVOLT_UNCONNECTED[2:0]), + .SDIO0_CDN(1'b0), + .SDIO0_CLK(NLW_inst_SDIO0_CLK_UNCONNECTED), + .SDIO0_CLK_FB(1'b0), + .SDIO0_CMD_I(1'b0), + .SDIO0_CMD_O(NLW_inst_SDIO0_CMD_O_UNCONNECTED), + .SDIO0_CMD_T(NLW_inst_SDIO0_CMD_T_UNCONNECTED), + .SDIO0_DATA_I({1'b0,1'b0,1'b0,1'b0}), + .SDIO0_DATA_O(NLW_inst_SDIO0_DATA_O_UNCONNECTED[3:0]), + .SDIO0_DATA_T(NLW_inst_SDIO0_DATA_T_UNCONNECTED[3:0]), + .SDIO0_LED(NLW_inst_SDIO0_LED_UNCONNECTED), + .SDIO0_WP(1'b0), + .SDIO1_BUSPOW(NLW_inst_SDIO1_BUSPOW_UNCONNECTED), + .SDIO1_BUSVOLT(NLW_inst_SDIO1_BUSVOLT_UNCONNECTED[2:0]), + .SDIO1_CDN(1'b0), + .SDIO1_CLK(NLW_inst_SDIO1_CLK_UNCONNECTED), + .SDIO1_CLK_FB(1'b0), + .SDIO1_CMD_I(1'b0), + .SDIO1_CMD_O(NLW_inst_SDIO1_CMD_O_UNCONNECTED), + .SDIO1_CMD_T(NLW_inst_SDIO1_CMD_T_UNCONNECTED), + .SDIO1_DATA_I({1'b0,1'b0,1'b0,1'b0}), + .SDIO1_DATA_O(NLW_inst_SDIO1_DATA_O_UNCONNECTED[3:0]), + .SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]), + .SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED), + .SDIO1_WP(1'b0), + .SPI0_MISO_I(1'b0), + .SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED), + .SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED), + .SPI0_MOSI_I(1'b0), + .SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED), + .SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED), + .SPI0_SCLK_I(1'b0), + .SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED), + .SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED), + .SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED), + .SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED), + .SPI0_SS_I(1'b0), + .SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED), + .SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED), + .SPI1_MISO_I(SPI1_MISO_I), + .SPI1_MISO_O(SPI1_MISO_O), + .SPI1_MISO_T(SPI1_MISO_T), + .SPI1_MOSI_I(SPI1_MOSI_I), + .SPI1_MOSI_O(SPI1_MOSI_O), + .SPI1_MOSI_T(SPI1_MOSI_T), + .SPI1_SCLK_I(SPI1_SCLK_I), + .SPI1_SCLK_O(SPI1_SCLK_O), + .SPI1_SCLK_T(SPI1_SCLK_T), + .SPI1_SS1_O(SPI1_SS1_O), + .SPI1_SS2_O(SPI1_SS2_O), + .SPI1_SS_I(SPI1_SS_I), + .SPI1_SS_O(SPI1_SS_O), + .SPI1_SS_T(SPI1_SS_T), + .SRAM_INTIN(1'b0), + .S_AXI_ACP_ACLK(1'b0), + .S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARBURST({1'b0,1'b0}), + .S_AXI_ACP_ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARESETN(NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED), + .S_AXI_ACP_ARID({1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARLOCK({1'b0,1'b0}), + .S_AXI_ACP_ARPROT({1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARREADY(NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED), + .S_AXI_ACP_ARSIZE({1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARUSER({1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_ARVALID(1'b0), + .S_AXI_ACP_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWBURST({1'b0,1'b0}), + .S_AXI_ACP_AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWID({1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWLOCK({1'b0,1'b0}), + .S_AXI_ACP_AWPROT({1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWREADY(NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED), + .S_AXI_ACP_AWSIZE({1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWUSER({1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_AWVALID(1'b0), + .S_AXI_ACP_BID(NLW_inst_S_AXI_ACP_BID_UNCONNECTED[2:0]), + .S_AXI_ACP_BREADY(1'b0), + .S_AXI_ACP_BRESP(NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED[1:0]), + .S_AXI_ACP_BVALID(NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED), + .S_AXI_ACP_RDATA(NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED[63:0]), + .S_AXI_ACP_RID(NLW_inst_S_AXI_ACP_RID_UNCONNECTED[2:0]), + .S_AXI_ACP_RLAST(NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED), + .S_AXI_ACP_RREADY(1'b0), + .S_AXI_ACP_RRESP(NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED[1:0]), + .S_AXI_ACP_RVALID(NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED), + .S_AXI_ACP_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_WID({1'b0,1'b0,1'b0}), + .S_AXI_ACP_WLAST(1'b0), + .S_AXI_ACP_WREADY(NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED), + .S_AXI_ACP_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_ACP_WVALID(1'b0), + .S_AXI_GP0_ACLK(1'b0), + .S_AXI_GP0_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_ARBURST({1'b0,1'b0}), + .S_AXI_GP0_ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_ARESETN(NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED), + .S_AXI_GP0_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_ARLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_ARLOCK({1'b0,1'b0}), + .S_AXI_GP0_ARPROT({1'b0,1'b0,1'b0}), + .S_AXI_GP0_ARQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_ARREADY(NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED), + .S_AXI_GP0_ARSIZE({1'b0,1'b0,1'b0}), + .S_AXI_GP0_ARVALID(1'b0), + .S_AXI_GP0_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_AWBURST({1'b0,1'b0}), + .S_AXI_GP0_AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_AWLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_AWLOCK({1'b0,1'b0}), + .S_AXI_GP0_AWPROT({1'b0,1'b0,1'b0}), + .S_AXI_GP0_AWQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_AWREADY(NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED), + .S_AXI_GP0_AWSIZE({1'b0,1'b0,1'b0}), + .S_AXI_GP0_AWVALID(1'b0), + .S_AXI_GP0_BID(NLW_inst_S_AXI_GP0_BID_UNCONNECTED[5:0]), + .S_AXI_GP0_BREADY(1'b0), + .S_AXI_GP0_BRESP(NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED[1:0]), + .S_AXI_GP0_BVALID(NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED), + .S_AXI_GP0_RDATA(NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED[31:0]), + .S_AXI_GP0_RID(NLW_inst_S_AXI_GP0_RID_UNCONNECTED[5:0]), + .S_AXI_GP0_RLAST(NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED), + .S_AXI_GP0_RREADY(1'b0), + .S_AXI_GP0_RRESP(NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED[1:0]), + .S_AXI_GP0_RVALID(NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED), + .S_AXI_GP0_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_WLAST(1'b0), + .S_AXI_GP0_WREADY(NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED), + .S_AXI_GP0_WSTRB({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP0_WVALID(1'b0), + .S_AXI_GP1_ACLK(1'b0), + .S_AXI_GP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_ARBURST({1'b0,1'b0}), + .S_AXI_GP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_ARESETN(NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED), + .S_AXI_GP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_ARLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_ARLOCK({1'b0,1'b0}), + .S_AXI_GP1_ARPROT({1'b0,1'b0,1'b0}), + .S_AXI_GP1_ARQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_ARREADY(NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED), + .S_AXI_GP1_ARSIZE({1'b0,1'b0,1'b0}), + .S_AXI_GP1_ARVALID(1'b0), + .S_AXI_GP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_AWBURST({1'b0,1'b0}), + .S_AXI_GP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_AWLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_AWLOCK({1'b0,1'b0}), + .S_AXI_GP1_AWPROT({1'b0,1'b0,1'b0}), + .S_AXI_GP1_AWQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_AWREADY(NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED), + .S_AXI_GP1_AWSIZE({1'b0,1'b0,1'b0}), + .S_AXI_GP1_AWVALID(1'b0), + .S_AXI_GP1_BID(NLW_inst_S_AXI_GP1_BID_UNCONNECTED[5:0]), + .S_AXI_GP1_BREADY(1'b0), + .S_AXI_GP1_BRESP(NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED[1:0]), + .S_AXI_GP1_BVALID(NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED), + .S_AXI_GP1_RDATA(NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED[31:0]), + .S_AXI_GP1_RID(NLW_inst_S_AXI_GP1_RID_UNCONNECTED[5:0]), + .S_AXI_GP1_RLAST(NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED), + .S_AXI_GP1_RREADY(1'b0), + .S_AXI_GP1_RRESP(NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED[1:0]), + .S_AXI_GP1_RVALID(NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED), + .S_AXI_GP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_WLAST(1'b0), + .S_AXI_GP1_WREADY(NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED), + .S_AXI_GP1_WSTRB({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_GP1_WVALID(1'b0), + .S_AXI_HP0_ACLK(S_AXI_HP0_ACLK), + .S_AXI_HP0_ARADDR(S_AXI_HP0_ARADDR), + .S_AXI_HP0_ARBURST(S_AXI_HP0_ARBURST), + .S_AXI_HP0_ARCACHE(S_AXI_HP0_ARCACHE), + .S_AXI_HP0_ARESETN(NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED), + .S_AXI_HP0_ARID(S_AXI_HP0_ARID), + .S_AXI_HP0_ARLEN(S_AXI_HP0_ARLEN), + .S_AXI_HP0_ARLOCK(S_AXI_HP0_ARLOCK), + .S_AXI_HP0_ARPROT(S_AXI_HP0_ARPROT), + .S_AXI_HP0_ARQOS(S_AXI_HP0_ARQOS), + .S_AXI_HP0_ARREADY(S_AXI_HP0_ARREADY), + .S_AXI_HP0_ARSIZE(S_AXI_HP0_ARSIZE), + .S_AXI_HP0_ARVALID(S_AXI_HP0_ARVALID), + .S_AXI_HP0_AWADDR(S_AXI_HP0_AWADDR), + .S_AXI_HP0_AWBURST(S_AXI_HP0_AWBURST), + .S_AXI_HP0_AWCACHE(S_AXI_HP0_AWCACHE), + .S_AXI_HP0_AWID(S_AXI_HP0_AWID), + .S_AXI_HP0_AWLEN(S_AXI_HP0_AWLEN), + .S_AXI_HP0_AWLOCK(S_AXI_HP0_AWLOCK), + .S_AXI_HP0_AWPROT(S_AXI_HP0_AWPROT), + .S_AXI_HP0_AWQOS(S_AXI_HP0_AWQOS), + .S_AXI_HP0_AWREADY(S_AXI_HP0_AWREADY), + .S_AXI_HP0_AWSIZE(S_AXI_HP0_AWSIZE), + .S_AXI_HP0_AWVALID(S_AXI_HP0_AWVALID), + .S_AXI_HP0_BID(S_AXI_HP0_BID), + .S_AXI_HP0_BREADY(S_AXI_HP0_BREADY), + .S_AXI_HP0_BRESP(S_AXI_HP0_BRESP), + .S_AXI_HP0_BVALID(S_AXI_HP0_BVALID), + .S_AXI_HP0_RACOUNT(S_AXI_HP0_RACOUNT), + .S_AXI_HP0_RCOUNT(S_AXI_HP0_RCOUNT), + .S_AXI_HP0_RDATA(S_AXI_HP0_RDATA), + .S_AXI_HP0_RDISSUECAP1_EN(S_AXI_HP0_RDISSUECAP1_EN), + .S_AXI_HP0_RID(S_AXI_HP0_RID), + .S_AXI_HP0_RLAST(S_AXI_HP0_RLAST), + .S_AXI_HP0_RREADY(S_AXI_HP0_RREADY), + .S_AXI_HP0_RRESP(S_AXI_HP0_RRESP), + .S_AXI_HP0_RVALID(S_AXI_HP0_RVALID), + .S_AXI_HP0_WACOUNT(S_AXI_HP0_WACOUNT), + .S_AXI_HP0_WCOUNT(S_AXI_HP0_WCOUNT), + .S_AXI_HP0_WDATA(S_AXI_HP0_WDATA), + .S_AXI_HP0_WID(S_AXI_HP0_WID), + .S_AXI_HP0_WLAST(S_AXI_HP0_WLAST), + .S_AXI_HP0_WREADY(S_AXI_HP0_WREADY), + .S_AXI_HP0_WRISSUECAP1_EN(S_AXI_HP0_WRISSUECAP1_EN), + .S_AXI_HP0_WSTRB(S_AXI_HP0_WSTRB), + .S_AXI_HP0_WVALID(S_AXI_HP0_WVALID), + .S_AXI_HP1_ACLK(1'b0), + .S_AXI_HP1_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_ARBURST({1'b0,1'b0}), + .S_AXI_HP1_ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_ARESETN(NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED), + .S_AXI_HP1_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_ARLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_ARLOCK({1'b0,1'b0}), + .S_AXI_HP1_ARPROT({1'b0,1'b0,1'b0}), + .S_AXI_HP1_ARQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_ARREADY(NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED), + .S_AXI_HP1_ARSIZE({1'b0,1'b0,1'b0}), + .S_AXI_HP1_ARVALID(1'b0), + .S_AXI_HP1_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_AWBURST({1'b0,1'b0}), + .S_AXI_HP1_AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_AWLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_AWLOCK({1'b0,1'b0}), + .S_AXI_HP1_AWPROT({1'b0,1'b0,1'b0}), + .S_AXI_HP1_AWQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_AWREADY(NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED), + .S_AXI_HP1_AWSIZE({1'b0,1'b0,1'b0}), + .S_AXI_HP1_AWVALID(1'b0), + .S_AXI_HP1_BID(NLW_inst_S_AXI_HP1_BID_UNCONNECTED[5:0]), + .S_AXI_HP1_BREADY(1'b0), + .S_AXI_HP1_BRESP(NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED[1:0]), + .S_AXI_HP1_BVALID(NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED), + .S_AXI_HP1_RACOUNT(NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED[2:0]), + .S_AXI_HP1_RCOUNT(NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED[7:0]), + .S_AXI_HP1_RDATA(NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED[63:0]), + .S_AXI_HP1_RDISSUECAP1_EN(1'b0), + .S_AXI_HP1_RID(NLW_inst_S_AXI_HP1_RID_UNCONNECTED[5:0]), + .S_AXI_HP1_RLAST(NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED), + .S_AXI_HP1_RREADY(1'b0), + .S_AXI_HP1_RRESP(NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED[1:0]), + .S_AXI_HP1_RVALID(NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED), + .S_AXI_HP1_WACOUNT(NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED[5:0]), + .S_AXI_HP1_WCOUNT(NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED[7:0]), + .S_AXI_HP1_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_WLAST(1'b0), + .S_AXI_HP1_WREADY(NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED), + .S_AXI_HP1_WRISSUECAP1_EN(1'b0), + .S_AXI_HP1_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP1_WVALID(1'b0), + .S_AXI_HP2_ACLK(1'b0), + .S_AXI_HP2_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_ARBURST({1'b0,1'b0}), + .S_AXI_HP2_ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_ARESETN(NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED), + .S_AXI_HP2_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_ARLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_ARLOCK({1'b0,1'b0}), + .S_AXI_HP2_ARPROT({1'b0,1'b0,1'b0}), + .S_AXI_HP2_ARQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_ARREADY(NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED), + .S_AXI_HP2_ARSIZE({1'b0,1'b0,1'b0}), + .S_AXI_HP2_ARVALID(1'b0), + .S_AXI_HP2_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_AWBURST({1'b0,1'b0}), + .S_AXI_HP2_AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_AWLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_AWLOCK({1'b0,1'b0}), + .S_AXI_HP2_AWPROT({1'b0,1'b0,1'b0}), + .S_AXI_HP2_AWQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_AWREADY(NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED), + .S_AXI_HP2_AWSIZE({1'b0,1'b0,1'b0}), + .S_AXI_HP2_AWVALID(1'b0), + .S_AXI_HP2_BID(NLW_inst_S_AXI_HP2_BID_UNCONNECTED[5:0]), + .S_AXI_HP2_BREADY(1'b0), + .S_AXI_HP2_BRESP(NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED[1:0]), + .S_AXI_HP2_BVALID(NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED), + .S_AXI_HP2_RACOUNT(NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED[2:0]), + .S_AXI_HP2_RCOUNT(NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED[7:0]), + .S_AXI_HP2_RDATA(NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED[63:0]), + .S_AXI_HP2_RDISSUECAP1_EN(1'b0), + .S_AXI_HP2_RID(NLW_inst_S_AXI_HP2_RID_UNCONNECTED[5:0]), + .S_AXI_HP2_RLAST(NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED), + .S_AXI_HP2_RREADY(1'b0), + .S_AXI_HP2_RRESP(NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED[1:0]), + .S_AXI_HP2_RVALID(NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED), + .S_AXI_HP2_WACOUNT(NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED[5:0]), + .S_AXI_HP2_WCOUNT(NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED[7:0]), + .S_AXI_HP2_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_WLAST(1'b0), + .S_AXI_HP2_WREADY(NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED), + .S_AXI_HP2_WRISSUECAP1_EN(1'b0), + .S_AXI_HP2_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP2_WVALID(1'b0), + .S_AXI_HP3_ACLK(1'b0), + .S_AXI_HP3_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_ARBURST({1'b0,1'b0}), + .S_AXI_HP3_ARCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_ARESETN(NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED), + .S_AXI_HP3_ARID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_ARLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_ARLOCK({1'b0,1'b0}), + .S_AXI_HP3_ARPROT({1'b0,1'b0,1'b0}), + .S_AXI_HP3_ARQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_ARREADY(NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED), + .S_AXI_HP3_ARSIZE({1'b0,1'b0,1'b0}), + .S_AXI_HP3_ARVALID(1'b0), + .S_AXI_HP3_AWADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_AWBURST({1'b0,1'b0}), + .S_AXI_HP3_AWCACHE({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_AWID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_AWLEN({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_AWLOCK({1'b0,1'b0}), + .S_AXI_HP3_AWPROT({1'b0,1'b0,1'b0}), + .S_AXI_HP3_AWQOS({1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_AWREADY(NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED), + .S_AXI_HP3_AWSIZE({1'b0,1'b0,1'b0}), + .S_AXI_HP3_AWVALID(1'b0), + .S_AXI_HP3_BID(NLW_inst_S_AXI_HP3_BID_UNCONNECTED[5:0]), + .S_AXI_HP3_BREADY(1'b0), + .S_AXI_HP3_BRESP(NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED[1:0]), + .S_AXI_HP3_BVALID(NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED), + .S_AXI_HP3_RACOUNT(NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED[2:0]), + .S_AXI_HP3_RCOUNT(NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED[7:0]), + .S_AXI_HP3_RDATA(NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED[63:0]), + .S_AXI_HP3_RDISSUECAP1_EN(1'b0), + .S_AXI_HP3_RID(NLW_inst_S_AXI_HP3_RID_UNCONNECTED[5:0]), + .S_AXI_HP3_RLAST(NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED), + .S_AXI_HP3_RREADY(1'b0), + .S_AXI_HP3_RRESP(NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED[1:0]), + .S_AXI_HP3_RVALID(NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED), + .S_AXI_HP3_WACOUNT(NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED[5:0]), + .S_AXI_HP3_WCOUNT(NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED[7:0]), + .S_AXI_HP3_WDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_WID({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_WLAST(1'b0), + .S_AXI_HP3_WREADY(NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED), + .S_AXI_HP3_WRISSUECAP1_EN(1'b0), + .S_AXI_HP3_WSTRB({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .S_AXI_HP3_WVALID(1'b0), + .TRACE_CLK(1'b0), + .TRACE_CLK_OUT(NLW_inst_TRACE_CLK_OUT_UNCONNECTED), + .TRACE_CTL(NLW_inst_TRACE_CTL_UNCONNECTED), + .TRACE_DATA(NLW_inst_TRACE_DATA_UNCONNECTED[1:0]), + .TTC0_CLK0_IN(1'b0), + .TTC0_CLK1_IN(1'b0), + .TTC0_CLK2_IN(1'b0), + .TTC0_WAVE0_OUT(TTC0_WAVE0_OUT), + .TTC0_WAVE1_OUT(TTC0_WAVE1_OUT), + .TTC0_WAVE2_OUT(TTC0_WAVE2_OUT), + .TTC1_CLK0_IN(1'b0), + .TTC1_CLK1_IN(1'b0), + .TTC1_CLK2_IN(1'b0), + .TTC1_WAVE0_OUT(NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED), + .TTC1_WAVE1_OUT(NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED), + .TTC1_WAVE2_OUT(NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED), + .UART0_CTSN(1'b0), + .UART0_DCDN(1'b0), + .UART0_DSRN(1'b0), + .UART0_DTRN(NLW_inst_UART0_DTRN_UNCONNECTED), + .UART0_RIN(1'b0), + .UART0_RTSN(NLW_inst_UART0_RTSN_UNCONNECTED), + .UART0_RX(1'b1), + .UART0_TX(NLW_inst_UART0_TX_UNCONNECTED), + .UART1_CTSN(1'b0), + .UART1_DCDN(1'b0), + .UART1_DSRN(1'b0), + .UART1_DTRN(NLW_inst_UART1_DTRN_UNCONNECTED), + .UART1_RIN(1'b0), + .UART1_RTSN(NLW_inst_UART1_RTSN_UNCONNECTED), + .UART1_RX(1'b1), + .UART1_TX(NLW_inst_UART1_TX_UNCONNECTED), + .USB0_PORT_INDCTL(USB0_PORT_INDCTL), + .USB0_VBUS_PWRFAULT(USB0_VBUS_PWRFAULT), + .USB0_VBUS_PWRSELECT(USB0_VBUS_PWRSELECT), + .USB1_PORT_INDCTL(NLW_inst_USB1_PORT_INDCTL_UNCONNECTED[1:0]), + .USB1_VBUS_PWRFAULT(1'b0), + .USB1_VBUS_PWRSELECT(NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED), + .WDT_CLK_IN(1'b0), + .WDT_RST_OUT(NLW_inst_WDT_RST_OUT_UNCONNECTED)); +endmodule + +(* C_DM_WIDTH = "4" *) (* C_DQS_WIDTH = "4" *) (* C_DQ_WIDTH = "32" *) +(* C_EMIO_GPIO_WIDTH = "64" *) (* C_EN_EMIO_ENET0 = "0" *) (* C_EN_EMIO_ENET1 = "0" *) +(* C_EN_EMIO_PJTAG = "0" *) (* C_EN_EMIO_TRACE = "0" *) (* C_FCLK_CLK0_BUF = "TRUE" *) +(* C_FCLK_CLK1_BUF = "FALSE" *) (* C_FCLK_CLK2_BUF = "FALSE" *) (* C_FCLK_CLK3_BUF = "FALSE" *) +(* C_GP0_EN_MODIFIABLE_TXN = "1" *) (* C_GP1_EN_MODIFIABLE_TXN = "1" *) (* C_INCLUDE_ACP_TRANS_CHECK = "0" *) +(* C_INCLUDE_TRACE_BUFFER = "0" *) (* C_IRQ_F2P_MODE = "DIRECT" *) (* C_MIO_PRIMITIVE = "54" *) +(* C_M_AXI_GP0_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP0_ID_WIDTH = "12" *) (* C_M_AXI_GP0_THREAD_ID_WIDTH = "12" *) +(* C_M_AXI_GP1_ENABLE_STATIC_REMAP = "0" *) (* C_M_AXI_GP1_ID_WIDTH = "12" *) (* C_M_AXI_GP1_THREAD_ID_WIDTH = "12" *) +(* C_NUM_F2P_INTR_INPUTS = "2" *) (* C_PACKAGE_NAME = "clg400" *) (* C_PS7_SI_REV = "PRODUCTION" *) +(* C_S_AXI_ACP_ARUSER_VAL = "31" *) (* C_S_AXI_ACP_AWUSER_VAL = "31" *) (* C_S_AXI_ACP_ID_WIDTH = "3" *) +(* C_S_AXI_GP0_ID_WIDTH = "6" *) (* C_S_AXI_GP1_ID_WIDTH = "6" *) (* C_S_AXI_HP0_DATA_WIDTH = "64" *) +(* C_S_AXI_HP0_ID_WIDTH = "6" *) (* C_S_AXI_HP1_DATA_WIDTH = "64" *) (* C_S_AXI_HP1_ID_WIDTH = "6" *) +(* C_S_AXI_HP2_DATA_WIDTH = "64" *) (* C_S_AXI_HP2_ID_WIDTH = "6" *) (* C_S_AXI_HP3_DATA_WIDTH = "64" *) +(* C_S_AXI_HP3_ID_WIDTH = "6" *) (* C_TRACE_BUFFER_CLOCK_DELAY = "12" *) (* C_TRACE_BUFFER_FIFO_SIZE = "128" *) +(* C_TRACE_INTERNAL_WIDTH = "2" *) (* C_TRACE_PIPELINE_WIDTH = "8" *) (* C_USE_AXI_NONSECURE = "0" *) +(* C_USE_DEFAULT_ACP_USER_VAL = "0" *) (* C_USE_M_AXI_GP0 = "1" *) (* C_USE_M_AXI_GP1 = "0" *) +(* C_USE_S_AXI_ACP = "0" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *) +(* C_USE_S_AXI_HP0 = "1" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *) +(* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "mz_petalinux_processing_system7_0_0.hwdef" *) (* POWER = "/>" *) +(* USE_TRACE_DATA_EDGE_DETECTOR = "0" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 + (CAN0_PHY_TX, + CAN0_PHY_RX, + CAN1_PHY_TX, + CAN1_PHY_RX, + ENET0_GMII_TX_EN, + ENET0_GMII_TX_ER, + ENET0_MDIO_MDC, + ENET0_MDIO_O, + ENET0_MDIO_T, + ENET0_PTP_DELAY_REQ_RX, + ENET0_PTP_DELAY_REQ_TX, + ENET0_PTP_PDELAY_REQ_RX, + ENET0_PTP_PDELAY_REQ_TX, + ENET0_PTP_PDELAY_RESP_RX, + ENET0_PTP_PDELAY_RESP_TX, + ENET0_PTP_SYNC_FRAME_RX, + ENET0_PTP_SYNC_FRAME_TX, + ENET0_SOF_RX, + ENET0_SOF_TX, + ENET0_GMII_TXD, + ENET0_GMII_COL, + ENET0_GMII_CRS, + ENET0_GMII_RX_CLK, + ENET0_GMII_RX_DV, + ENET0_GMII_RX_ER, + ENET0_GMII_TX_CLK, + ENET0_MDIO_I, + ENET0_EXT_INTIN, + ENET0_GMII_RXD, + ENET1_GMII_TX_EN, + ENET1_GMII_TX_ER, + ENET1_MDIO_MDC, + ENET1_MDIO_O, + ENET1_MDIO_T, + ENET1_PTP_DELAY_REQ_RX, + ENET1_PTP_DELAY_REQ_TX, + ENET1_PTP_PDELAY_REQ_RX, + ENET1_PTP_PDELAY_REQ_TX, + ENET1_PTP_PDELAY_RESP_RX, + ENET1_PTP_PDELAY_RESP_TX, + ENET1_PTP_SYNC_FRAME_RX, + ENET1_PTP_SYNC_FRAME_TX, + ENET1_SOF_RX, + ENET1_SOF_TX, + ENET1_GMII_TXD, + ENET1_GMII_COL, + ENET1_GMII_CRS, + ENET1_GMII_RX_CLK, + ENET1_GMII_RX_DV, + ENET1_GMII_RX_ER, + ENET1_GMII_TX_CLK, + ENET1_MDIO_I, + ENET1_EXT_INTIN, + ENET1_GMII_RXD, + GPIO_I, + GPIO_O, + GPIO_T, + I2C0_SDA_I, + I2C0_SDA_O, + I2C0_SDA_T, + I2C0_SCL_I, + I2C0_SCL_O, + I2C0_SCL_T, + I2C1_SDA_I, + I2C1_SDA_O, + I2C1_SDA_T, + I2C1_SCL_I, + I2C1_SCL_O, + I2C1_SCL_T, + PJTAG_TCK, + PJTAG_TMS, + PJTAG_TDI, + PJTAG_TDO, + SDIO0_CLK, + SDIO0_CLK_FB, + SDIO0_CMD_O, + SDIO0_CMD_I, + SDIO0_CMD_T, + SDIO0_DATA_I, + SDIO0_DATA_O, + SDIO0_DATA_T, + SDIO0_LED, + SDIO0_CDN, + SDIO0_WP, + SDIO0_BUSPOW, + SDIO0_BUSVOLT, + SDIO1_CLK, + SDIO1_CLK_FB, + SDIO1_CMD_O, + SDIO1_CMD_I, + SDIO1_CMD_T, + SDIO1_DATA_I, + SDIO1_DATA_O, + SDIO1_DATA_T, + SDIO1_LED, + SDIO1_CDN, + SDIO1_WP, + SDIO1_BUSPOW, + SDIO1_BUSVOLT, + SPI0_SCLK_I, + SPI0_SCLK_O, + SPI0_SCLK_T, + SPI0_MOSI_I, + SPI0_MOSI_O, + SPI0_MOSI_T, + SPI0_MISO_I, + SPI0_MISO_O, + SPI0_MISO_T, + SPI0_SS_I, + SPI0_SS_O, + SPI0_SS1_O, + SPI0_SS2_O, + SPI0_SS_T, + SPI1_SCLK_I, + SPI1_SCLK_O, + SPI1_SCLK_T, + SPI1_MOSI_I, + SPI1_MOSI_O, + SPI1_MOSI_T, + SPI1_MISO_I, + SPI1_MISO_O, + SPI1_MISO_T, + SPI1_SS_I, + SPI1_SS_O, + SPI1_SS1_O, + SPI1_SS2_O, + SPI1_SS_T, + UART0_DTRN, + UART0_RTSN, + UART0_TX, + UART0_CTSN, + UART0_DCDN, + UART0_DSRN, + UART0_RIN, + UART0_RX, + UART1_DTRN, + UART1_RTSN, + UART1_TX, + UART1_CTSN, + UART1_DCDN, + UART1_DSRN, + UART1_RIN, + UART1_RX, + TTC0_WAVE0_OUT, + TTC0_WAVE1_OUT, + TTC0_WAVE2_OUT, + TTC0_CLK0_IN, + TTC0_CLK1_IN, + TTC0_CLK2_IN, + TTC1_WAVE0_OUT, + TTC1_WAVE1_OUT, + TTC1_WAVE2_OUT, + TTC1_CLK0_IN, + TTC1_CLK1_IN, + TTC1_CLK2_IN, + WDT_CLK_IN, + WDT_RST_OUT, + TRACE_CLK, + TRACE_CTL, + TRACE_DATA, + TRACE_CLK_OUT, + USB0_PORT_INDCTL, + USB0_VBUS_PWRSELECT, + USB0_VBUS_PWRFAULT, + USB1_PORT_INDCTL, + USB1_VBUS_PWRSELECT, + USB1_VBUS_PWRFAULT, + SRAM_INTIN, + M_AXI_GP0_ARESETN, + M_AXI_GP0_ARVALID, + M_AXI_GP0_AWVALID, + M_AXI_GP0_BREADY, + M_AXI_GP0_RREADY, + M_AXI_GP0_WLAST, + M_AXI_GP0_WVALID, + M_AXI_GP0_ARID, + M_AXI_GP0_AWID, + M_AXI_GP0_WID, + M_AXI_GP0_ARBURST, + M_AXI_GP0_ARLOCK, + M_AXI_GP0_ARSIZE, + M_AXI_GP0_AWBURST, + M_AXI_GP0_AWLOCK, + M_AXI_GP0_AWSIZE, + M_AXI_GP0_ARPROT, + M_AXI_GP0_AWPROT, + M_AXI_GP0_ARADDR, + M_AXI_GP0_AWADDR, + M_AXI_GP0_WDATA, + M_AXI_GP0_ARCACHE, + M_AXI_GP0_ARLEN, + M_AXI_GP0_ARQOS, + M_AXI_GP0_AWCACHE, + M_AXI_GP0_AWLEN, + M_AXI_GP0_AWQOS, + M_AXI_GP0_WSTRB, + M_AXI_GP0_ACLK, + M_AXI_GP0_ARREADY, + M_AXI_GP0_AWREADY, + M_AXI_GP0_BVALID, + M_AXI_GP0_RLAST, + M_AXI_GP0_RVALID, + M_AXI_GP0_WREADY, + M_AXI_GP0_BID, + M_AXI_GP0_RID, + M_AXI_GP0_BRESP, + M_AXI_GP0_RRESP, + M_AXI_GP0_RDATA, + M_AXI_GP1_ARESETN, + M_AXI_GP1_ARVALID, + M_AXI_GP1_AWVALID, + M_AXI_GP1_BREADY, + M_AXI_GP1_RREADY, + M_AXI_GP1_WLAST, + M_AXI_GP1_WVALID, + M_AXI_GP1_ARID, + M_AXI_GP1_AWID, + M_AXI_GP1_WID, + M_AXI_GP1_ARBURST, + M_AXI_GP1_ARLOCK, + M_AXI_GP1_ARSIZE, + M_AXI_GP1_AWBURST, + M_AXI_GP1_AWLOCK, + M_AXI_GP1_AWSIZE, + M_AXI_GP1_ARPROT, + M_AXI_GP1_AWPROT, + M_AXI_GP1_ARADDR, + M_AXI_GP1_AWADDR, + M_AXI_GP1_WDATA, + M_AXI_GP1_ARCACHE, + M_AXI_GP1_ARLEN, + M_AXI_GP1_ARQOS, + M_AXI_GP1_AWCACHE, + M_AXI_GP1_AWLEN, + M_AXI_GP1_AWQOS, + M_AXI_GP1_WSTRB, + M_AXI_GP1_ACLK, + M_AXI_GP1_ARREADY, + M_AXI_GP1_AWREADY, + M_AXI_GP1_BVALID, + M_AXI_GP1_RLAST, + M_AXI_GP1_RVALID, + M_AXI_GP1_WREADY, + M_AXI_GP1_BID, + M_AXI_GP1_RID, + M_AXI_GP1_BRESP, + M_AXI_GP1_RRESP, + M_AXI_GP1_RDATA, + S_AXI_GP0_ARESETN, + S_AXI_GP0_ARREADY, + S_AXI_GP0_AWREADY, + S_AXI_GP0_BVALID, + S_AXI_GP0_RLAST, + S_AXI_GP0_RVALID, + S_AXI_GP0_WREADY, + S_AXI_GP0_BRESP, + S_AXI_GP0_RRESP, + S_AXI_GP0_RDATA, + S_AXI_GP0_BID, + S_AXI_GP0_RID, + S_AXI_GP0_ACLK, + S_AXI_GP0_ARVALID, + S_AXI_GP0_AWVALID, + S_AXI_GP0_BREADY, + S_AXI_GP0_RREADY, + S_AXI_GP0_WLAST, + S_AXI_GP0_WVALID, + S_AXI_GP0_ARBURST, + S_AXI_GP0_ARLOCK, + S_AXI_GP0_ARSIZE, + S_AXI_GP0_AWBURST, + S_AXI_GP0_AWLOCK, + S_AXI_GP0_AWSIZE, + S_AXI_GP0_ARPROT, + S_AXI_GP0_AWPROT, + S_AXI_GP0_ARADDR, + S_AXI_GP0_AWADDR, + S_AXI_GP0_WDATA, + S_AXI_GP0_ARCACHE, + S_AXI_GP0_ARLEN, + S_AXI_GP0_ARQOS, + S_AXI_GP0_AWCACHE, + S_AXI_GP0_AWLEN, + S_AXI_GP0_AWQOS, + S_AXI_GP0_WSTRB, + S_AXI_GP0_ARID, + S_AXI_GP0_AWID, + S_AXI_GP0_WID, + S_AXI_GP1_ARESETN, + S_AXI_GP1_ARREADY, + S_AXI_GP1_AWREADY, + S_AXI_GP1_BVALID, + S_AXI_GP1_RLAST, + S_AXI_GP1_RVALID, + S_AXI_GP1_WREADY, + S_AXI_GP1_BRESP, + S_AXI_GP1_RRESP, + S_AXI_GP1_RDATA, + S_AXI_GP1_BID, + S_AXI_GP1_RID, + S_AXI_GP1_ACLK, + S_AXI_GP1_ARVALID, + S_AXI_GP1_AWVALID, + S_AXI_GP1_BREADY, + S_AXI_GP1_RREADY, + S_AXI_GP1_WLAST, + S_AXI_GP1_WVALID, + S_AXI_GP1_ARBURST, + S_AXI_GP1_ARLOCK, + S_AXI_GP1_ARSIZE, + S_AXI_GP1_AWBURST, + S_AXI_GP1_AWLOCK, + S_AXI_GP1_AWSIZE, + S_AXI_GP1_ARPROT, + S_AXI_GP1_AWPROT, + S_AXI_GP1_ARADDR, + S_AXI_GP1_AWADDR, + S_AXI_GP1_WDATA, + S_AXI_GP1_ARCACHE, + S_AXI_GP1_ARLEN, + S_AXI_GP1_ARQOS, + S_AXI_GP1_AWCACHE, + S_AXI_GP1_AWLEN, + S_AXI_GP1_AWQOS, + S_AXI_GP1_WSTRB, + S_AXI_GP1_ARID, + S_AXI_GP1_AWID, + S_AXI_GP1_WID, + S_AXI_ACP_ARESETN, + S_AXI_ACP_ARREADY, + S_AXI_ACP_AWREADY, + S_AXI_ACP_BVALID, + S_AXI_ACP_RLAST, + S_AXI_ACP_RVALID, + S_AXI_ACP_WREADY, + S_AXI_ACP_BRESP, + S_AXI_ACP_RRESP, + S_AXI_ACP_BID, + S_AXI_ACP_RID, + S_AXI_ACP_RDATA, + S_AXI_ACP_ACLK, + S_AXI_ACP_ARVALID, + S_AXI_ACP_AWVALID, + S_AXI_ACP_BREADY, + S_AXI_ACP_RREADY, + S_AXI_ACP_WLAST, + S_AXI_ACP_WVALID, + S_AXI_ACP_ARID, + S_AXI_ACP_ARPROT, + S_AXI_ACP_AWID, + S_AXI_ACP_AWPROT, + S_AXI_ACP_WID, + S_AXI_ACP_ARADDR, + S_AXI_ACP_AWADDR, + S_AXI_ACP_ARCACHE, + S_AXI_ACP_ARLEN, + S_AXI_ACP_ARQOS, + S_AXI_ACP_AWCACHE, + S_AXI_ACP_AWLEN, + S_AXI_ACP_AWQOS, + S_AXI_ACP_ARBURST, + S_AXI_ACP_ARLOCK, + S_AXI_ACP_ARSIZE, + S_AXI_ACP_AWBURST, + S_AXI_ACP_AWLOCK, + S_AXI_ACP_AWSIZE, + S_AXI_ACP_ARUSER, + S_AXI_ACP_AWUSER, + S_AXI_ACP_WDATA, + S_AXI_ACP_WSTRB, + S_AXI_HP0_ARESETN, + S_AXI_HP0_ARREADY, + S_AXI_HP0_AWREADY, + S_AXI_HP0_BVALID, + S_AXI_HP0_RLAST, + S_AXI_HP0_RVALID, + S_AXI_HP0_WREADY, + S_AXI_HP0_BRESP, + S_AXI_HP0_RRESP, + S_AXI_HP0_BID, + S_AXI_HP0_RID, + S_AXI_HP0_RDATA, + S_AXI_HP0_RCOUNT, + S_AXI_HP0_WCOUNT, + S_AXI_HP0_RACOUNT, + S_AXI_HP0_WACOUNT, + S_AXI_HP0_ACLK, + S_AXI_HP0_ARVALID, + S_AXI_HP0_AWVALID, + S_AXI_HP0_BREADY, + S_AXI_HP0_RDISSUECAP1_EN, + S_AXI_HP0_RREADY, + S_AXI_HP0_WLAST, + S_AXI_HP0_WRISSUECAP1_EN, + S_AXI_HP0_WVALID, + S_AXI_HP0_ARBURST, + S_AXI_HP0_ARLOCK, + S_AXI_HP0_ARSIZE, + S_AXI_HP0_AWBURST, + S_AXI_HP0_AWLOCK, + S_AXI_HP0_AWSIZE, + S_AXI_HP0_ARPROT, + S_AXI_HP0_AWPROT, + S_AXI_HP0_ARADDR, + S_AXI_HP0_AWADDR, + S_AXI_HP0_ARCACHE, + S_AXI_HP0_ARLEN, + S_AXI_HP0_ARQOS, + S_AXI_HP0_AWCACHE, + S_AXI_HP0_AWLEN, + S_AXI_HP0_AWQOS, + S_AXI_HP0_ARID, + S_AXI_HP0_AWID, + S_AXI_HP0_WID, + S_AXI_HP0_WDATA, + S_AXI_HP0_WSTRB, + S_AXI_HP1_ARESETN, + S_AXI_HP1_ARREADY, + S_AXI_HP1_AWREADY, + S_AXI_HP1_BVALID, + S_AXI_HP1_RLAST, + S_AXI_HP1_RVALID, + S_AXI_HP1_WREADY, + S_AXI_HP1_BRESP, + S_AXI_HP1_RRESP, + S_AXI_HP1_BID, + S_AXI_HP1_RID, + S_AXI_HP1_RDATA, + S_AXI_HP1_RCOUNT, + S_AXI_HP1_WCOUNT, + S_AXI_HP1_RACOUNT, + S_AXI_HP1_WACOUNT, + S_AXI_HP1_ACLK, + S_AXI_HP1_ARVALID, + S_AXI_HP1_AWVALID, + S_AXI_HP1_BREADY, + S_AXI_HP1_RDISSUECAP1_EN, + S_AXI_HP1_RREADY, + S_AXI_HP1_WLAST, + S_AXI_HP1_WRISSUECAP1_EN, + S_AXI_HP1_WVALID, + S_AXI_HP1_ARBURST, + S_AXI_HP1_ARLOCK, + S_AXI_HP1_ARSIZE, + S_AXI_HP1_AWBURST, + S_AXI_HP1_AWLOCK, + S_AXI_HP1_AWSIZE, + S_AXI_HP1_ARPROT, + S_AXI_HP1_AWPROT, + S_AXI_HP1_ARADDR, + S_AXI_HP1_AWADDR, + S_AXI_HP1_ARCACHE, + S_AXI_HP1_ARLEN, + S_AXI_HP1_ARQOS, + S_AXI_HP1_AWCACHE, + S_AXI_HP1_AWLEN, + S_AXI_HP1_AWQOS, + S_AXI_HP1_ARID, + S_AXI_HP1_AWID, + S_AXI_HP1_WID, + S_AXI_HP1_WDATA, + S_AXI_HP1_WSTRB, + S_AXI_HP2_ARESETN, + S_AXI_HP2_ARREADY, + S_AXI_HP2_AWREADY, + S_AXI_HP2_BVALID, + S_AXI_HP2_RLAST, + S_AXI_HP2_RVALID, + S_AXI_HP2_WREADY, + S_AXI_HP2_BRESP, + S_AXI_HP2_RRESP, + S_AXI_HP2_BID, + S_AXI_HP2_RID, + S_AXI_HP2_RDATA, + S_AXI_HP2_RCOUNT, + S_AXI_HP2_WCOUNT, + S_AXI_HP2_RACOUNT, + S_AXI_HP2_WACOUNT, + S_AXI_HP2_ACLK, + S_AXI_HP2_ARVALID, + S_AXI_HP2_AWVALID, + S_AXI_HP2_BREADY, + S_AXI_HP2_RDISSUECAP1_EN, + S_AXI_HP2_RREADY, + S_AXI_HP2_WLAST, + S_AXI_HP2_WRISSUECAP1_EN, + S_AXI_HP2_WVALID, + S_AXI_HP2_ARBURST, + S_AXI_HP2_ARLOCK, + S_AXI_HP2_ARSIZE, + S_AXI_HP2_AWBURST, + S_AXI_HP2_AWLOCK, + S_AXI_HP2_AWSIZE, + S_AXI_HP2_ARPROT, + S_AXI_HP2_AWPROT, + S_AXI_HP2_ARADDR, + S_AXI_HP2_AWADDR, + S_AXI_HP2_ARCACHE, + S_AXI_HP2_ARLEN, + S_AXI_HP2_ARQOS, + S_AXI_HP2_AWCACHE, + S_AXI_HP2_AWLEN, + S_AXI_HP2_AWQOS, + S_AXI_HP2_ARID, + S_AXI_HP2_AWID, + S_AXI_HP2_WID, + S_AXI_HP2_WDATA, + S_AXI_HP2_WSTRB, + S_AXI_HP3_ARESETN, + S_AXI_HP3_ARREADY, + S_AXI_HP3_AWREADY, + S_AXI_HP3_BVALID, + S_AXI_HP3_RLAST, + S_AXI_HP3_RVALID, + S_AXI_HP3_WREADY, + S_AXI_HP3_BRESP, + S_AXI_HP3_RRESP, + S_AXI_HP3_BID, + S_AXI_HP3_RID, + S_AXI_HP3_RDATA, + S_AXI_HP3_RCOUNT, + S_AXI_HP3_WCOUNT, + S_AXI_HP3_RACOUNT, + S_AXI_HP3_WACOUNT, + S_AXI_HP3_ACLK, + S_AXI_HP3_ARVALID, + S_AXI_HP3_AWVALID, + S_AXI_HP3_BREADY, + S_AXI_HP3_RDISSUECAP1_EN, + S_AXI_HP3_RREADY, + S_AXI_HP3_WLAST, + S_AXI_HP3_WRISSUECAP1_EN, + S_AXI_HP3_WVALID, + S_AXI_HP3_ARBURST, + S_AXI_HP3_ARLOCK, + S_AXI_HP3_ARSIZE, + S_AXI_HP3_AWBURST, + S_AXI_HP3_AWLOCK, + S_AXI_HP3_AWSIZE, + S_AXI_HP3_ARPROT, + S_AXI_HP3_AWPROT, + S_AXI_HP3_ARADDR, + S_AXI_HP3_AWADDR, + S_AXI_HP3_ARCACHE, + S_AXI_HP3_ARLEN, + S_AXI_HP3_ARQOS, + S_AXI_HP3_AWCACHE, + S_AXI_HP3_AWLEN, + S_AXI_HP3_AWQOS, + S_AXI_HP3_ARID, + S_AXI_HP3_AWID, + S_AXI_HP3_WID, + S_AXI_HP3_WDATA, + S_AXI_HP3_WSTRB, + IRQ_P2F_DMAC_ABORT, + IRQ_P2F_DMAC0, + IRQ_P2F_DMAC1, + IRQ_P2F_DMAC2, + IRQ_P2F_DMAC3, + IRQ_P2F_DMAC4, + IRQ_P2F_DMAC5, + IRQ_P2F_DMAC6, + IRQ_P2F_DMAC7, + IRQ_P2F_SMC, + IRQ_P2F_QSPI, + IRQ_P2F_CTI, + IRQ_P2F_GPIO, + IRQ_P2F_USB0, + IRQ_P2F_ENET0, + IRQ_P2F_ENET_WAKE0, + IRQ_P2F_SDIO0, + IRQ_P2F_I2C0, + IRQ_P2F_SPI0, + IRQ_P2F_UART0, + IRQ_P2F_CAN0, + IRQ_P2F_USB1, + IRQ_P2F_ENET1, + IRQ_P2F_ENET_WAKE1, + IRQ_P2F_SDIO1, + IRQ_P2F_I2C1, + IRQ_P2F_SPI1, + IRQ_P2F_UART1, + IRQ_P2F_CAN1, + IRQ_F2P, + Core0_nFIQ, + Core0_nIRQ, + Core1_nFIQ, + Core1_nIRQ, + DMA0_DATYPE, + DMA0_DAVALID, + DMA0_DRREADY, + DMA0_RSTN, + DMA1_DATYPE, + DMA1_DAVALID, + DMA1_DRREADY, + DMA1_RSTN, + DMA2_DATYPE, + DMA2_DAVALID, + DMA2_DRREADY, + DMA2_RSTN, + DMA3_DATYPE, + DMA3_DAVALID, + DMA3_DRREADY, + DMA3_RSTN, + DMA0_ACLK, + DMA0_DAREADY, + DMA0_DRLAST, + DMA0_DRVALID, + DMA1_ACLK, + DMA1_DAREADY, + DMA1_DRLAST, + DMA1_DRVALID, + DMA2_ACLK, + DMA2_DAREADY, + DMA2_DRLAST, + DMA2_DRVALID, + DMA3_ACLK, + DMA3_DAREADY, + DMA3_DRLAST, + DMA3_DRVALID, + DMA0_DRTYPE, + DMA1_DRTYPE, + DMA2_DRTYPE, + DMA3_DRTYPE, + FCLK_CLK3, + FCLK_CLK2, + FCLK_CLK1, + FCLK_CLK0, + FCLK_CLKTRIG3_N, + FCLK_CLKTRIG2_N, + FCLK_CLKTRIG1_N, + FCLK_CLKTRIG0_N, + FCLK_RESET3_N, + FCLK_RESET2_N, + FCLK_RESET1_N, + FCLK_RESET0_N, + FTMD_TRACEIN_DATA, + FTMD_TRACEIN_VALID, + FTMD_TRACEIN_CLK, + FTMD_TRACEIN_ATID, + FTMT_F2P_TRIG_0, + FTMT_F2P_TRIGACK_0, + FTMT_F2P_TRIG_1, + FTMT_F2P_TRIGACK_1, + FTMT_F2P_TRIG_2, + FTMT_F2P_TRIGACK_2, + FTMT_F2P_TRIG_3, + FTMT_F2P_TRIGACK_3, + FTMT_F2P_DEBUG, + FTMT_P2F_TRIGACK_0, + FTMT_P2F_TRIG_0, + FTMT_P2F_TRIGACK_1, + FTMT_P2F_TRIG_1, + FTMT_P2F_TRIGACK_2, + FTMT_P2F_TRIG_2, + FTMT_P2F_TRIGACK_3, + FTMT_P2F_TRIG_3, + FTMT_P2F_DEBUG, + FPGA_IDLE_N, + EVENT_EVENTO, + EVENT_STANDBYWFE, + EVENT_STANDBYWFI, + EVENT_EVENTI, + DDR_ARB, + MIO, + DDR_CAS_n, + DDR_CKE, + DDR_Clk_n, + DDR_Clk, + DDR_CS_n, + DDR_DRSTB, + DDR_ODT, + DDR_RAS_n, + DDR_WEB, + DDR_BankAddr, + DDR_Addr, + DDR_VRN, + DDR_VRP, + DDR_DM, + DDR_DQ, + DDR_DQS_n, + DDR_DQS, + PS_SRSTB, + PS_CLK, + PS_PORB); + output CAN0_PHY_TX; + input CAN0_PHY_RX; + output CAN1_PHY_TX; + input CAN1_PHY_RX; + output ENET0_GMII_TX_EN; + output ENET0_GMII_TX_ER; + output ENET0_MDIO_MDC; + output ENET0_MDIO_O; + output ENET0_MDIO_T; + output ENET0_PTP_DELAY_REQ_RX; + output ENET0_PTP_DELAY_REQ_TX; + output ENET0_PTP_PDELAY_REQ_RX; + output ENET0_PTP_PDELAY_REQ_TX; + output ENET0_PTP_PDELAY_RESP_RX; + output ENET0_PTP_PDELAY_RESP_TX; + output ENET0_PTP_SYNC_FRAME_RX; + output ENET0_PTP_SYNC_FRAME_TX; + output ENET0_SOF_RX; + output ENET0_SOF_TX; + output [7:0]ENET0_GMII_TXD; + input ENET0_GMII_COL; + input ENET0_GMII_CRS; + input ENET0_GMII_RX_CLK; + input ENET0_GMII_RX_DV; + input ENET0_GMII_RX_ER; + input ENET0_GMII_TX_CLK; + input ENET0_MDIO_I; + input ENET0_EXT_INTIN; + input [7:0]ENET0_GMII_RXD; + output ENET1_GMII_TX_EN; + output ENET1_GMII_TX_ER; + output ENET1_MDIO_MDC; + output ENET1_MDIO_O; + output ENET1_MDIO_T; + output ENET1_PTP_DELAY_REQ_RX; + output ENET1_PTP_DELAY_REQ_TX; + output ENET1_PTP_PDELAY_REQ_RX; + output ENET1_PTP_PDELAY_REQ_TX; + output ENET1_PTP_PDELAY_RESP_RX; + output ENET1_PTP_PDELAY_RESP_TX; + output ENET1_PTP_SYNC_FRAME_RX; + output ENET1_PTP_SYNC_FRAME_TX; + output ENET1_SOF_RX; + output ENET1_SOF_TX; + output [7:0]ENET1_GMII_TXD; + input ENET1_GMII_COL; + input ENET1_GMII_CRS; + input ENET1_GMII_RX_CLK; + input ENET1_GMII_RX_DV; + input ENET1_GMII_RX_ER; + input ENET1_GMII_TX_CLK; + input ENET1_MDIO_I; + input ENET1_EXT_INTIN; + input [7:0]ENET1_GMII_RXD; + input [63:0]GPIO_I; + output [63:0]GPIO_O; + output [63:0]GPIO_T; + input I2C0_SDA_I; + output I2C0_SDA_O; + output I2C0_SDA_T; + input I2C0_SCL_I; + output I2C0_SCL_O; + output I2C0_SCL_T; + input I2C1_SDA_I; + output I2C1_SDA_O; + output I2C1_SDA_T; + input I2C1_SCL_I; + output I2C1_SCL_O; + output I2C1_SCL_T; + input PJTAG_TCK; + input PJTAG_TMS; + input PJTAG_TDI; + output PJTAG_TDO; + output SDIO0_CLK; + input SDIO0_CLK_FB; + output SDIO0_CMD_O; + input SDIO0_CMD_I; + output SDIO0_CMD_T; + input [3:0]SDIO0_DATA_I; + output [3:0]SDIO0_DATA_O; + output [3:0]SDIO0_DATA_T; + output SDIO0_LED; + input SDIO0_CDN; + input SDIO0_WP; + output SDIO0_BUSPOW; + output [2:0]SDIO0_BUSVOLT; + output SDIO1_CLK; + input SDIO1_CLK_FB; + output SDIO1_CMD_O; + input SDIO1_CMD_I; + output SDIO1_CMD_T; + input [3:0]SDIO1_DATA_I; + output [3:0]SDIO1_DATA_O; + output [3:0]SDIO1_DATA_T; + output SDIO1_LED; + input SDIO1_CDN; + input SDIO1_WP; + output SDIO1_BUSPOW; + output [2:0]SDIO1_BUSVOLT; + input SPI0_SCLK_I; + output SPI0_SCLK_O; + output SPI0_SCLK_T; + input SPI0_MOSI_I; + output SPI0_MOSI_O; + output SPI0_MOSI_T; + input SPI0_MISO_I; + output SPI0_MISO_O; + output SPI0_MISO_T; + input SPI0_SS_I; + output SPI0_SS_O; + output SPI0_SS1_O; + output SPI0_SS2_O; + output SPI0_SS_T; + input SPI1_SCLK_I; + output SPI1_SCLK_O; + output SPI1_SCLK_T; + input SPI1_MOSI_I; + output SPI1_MOSI_O; + output SPI1_MOSI_T; + input SPI1_MISO_I; + output SPI1_MISO_O; + output SPI1_MISO_T; + input SPI1_SS_I; + output SPI1_SS_O; + output SPI1_SS1_O; + output SPI1_SS2_O; + output SPI1_SS_T; + output UART0_DTRN; + output UART0_RTSN; + output UART0_TX; + input UART0_CTSN; + input UART0_DCDN; + input UART0_DSRN; + input UART0_RIN; + input UART0_RX; + output UART1_DTRN; + output UART1_RTSN; + output UART1_TX; + input UART1_CTSN; + input UART1_DCDN; + input UART1_DSRN; + input UART1_RIN; + input UART1_RX; + output TTC0_WAVE0_OUT; + output TTC0_WAVE1_OUT; + output TTC0_WAVE2_OUT; + input TTC0_CLK0_IN; + input TTC0_CLK1_IN; + input TTC0_CLK2_IN; + output TTC1_WAVE0_OUT; + output TTC1_WAVE1_OUT; + output TTC1_WAVE2_OUT; + input TTC1_CLK0_IN; + input TTC1_CLK1_IN; + input TTC1_CLK2_IN; + input WDT_CLK_IN; + output WDT_RST_OUT; + input TRACE_CLK; + output TRACE_CTL; + output [1:0]TRACE_DATA; + output TRACE_CLK_OUT; + output [1:0]USB0_PORT_INDCTL; + output USB0_VBUS_PWRSELECT; + input USB0_VBUS_PWRFAULT; + output [1:0]USB1_PORT_INDCTL; + output USB1_VBUS_PWRSELECT; + input USB1_VBUS_PWRFAULT; + input SRAM_INTIN; + output M_AXI_GP0_ARESETN; + output M_AXI_GP0_ARVALID; + output M_AXI_GP0_AWVALID; + output M_AXI_GP0_BREADY; + output M_AXI_GP0_RREADY; + output M_AXI_GP0_WLAST; + output M_AXI_GP0_WVALID; + output [11:0]M_AXI_GP0_ARID; + output [11:0]M_AXI_GP0_AWID; + output [11:0]M_AXI_GP0_WID; + output [1:0]M_AXI_GP0_ARBURST; + output [1:0]M_AXI_GP0_ARLOCK; + output [2:0]M_AXI_GP0_ARSIZE; + output [1:0]M_AXI_GP0_AWBURST; + output [1:0]M_AXI_GP0_AWLOCK; + output [2:0]M_AXI_GP0_AWSIZE; + output [2:0]M_AXI_GP0_ARPROT; + output [2:0]M_AXI_GP0_AWPROT; + output [31:0]M_AXI_GP0_ARADDR; + output [31:0]M_AXI_GP0_AWADDR; + output [31:0]M_AXI_GP0_WDATA; + output [3:0]M_AXI_GP0_ARCACHE; + output [3:0]M_AXI_GP0_ARLEN; + output [3:0]M_AXI_GP0_ARQOS; + output [3:0]M_AXI_GP0_AWCACHE; + output [3:0]M_AXI_GP0_AWLEN; + output [3:0]M_AXI_GP0_AWQOS; + output [3:0]M_AXI_GP0_WSTRB; + input M_AXI_GP0_ACLK; + input M_AXI_GP0_ARREADY; + input M_AXI_GP0_AWREADY; + input M_AXI_GP0_BVALID; + input M_AXI_GP0_RLAST; + input M_AXI_GP0_RVALID; + input M_AXI_GP0_WREADY; + input [11:0]M_AXI_GP0_BID; + input [11:0]M_AXI_GP0_RID; + input [1:0]M_AXI_GP0_BRESP; + input [1:0]M_AXI_GP0_RRESP; + input [31:0]M_AXI_GP0_RDATA; + output M_AXI_GP1_ARESETN; + output M_AXI_GP1_ARVALID; + output M_AXI_GP1_AWVALID; + output M_AXI_GP1_BREADY; + output M_AXI_GP1_RREADY; + output M_AXI_GP1_WLAST; + output M_AXI_GP1_WVALID; + output [11:0]M_AXI_GP1_ARID; + output [11:0]M_AXI_GP1_AWID; + output [11:0]M_AXI_GP1_WID; + output [1:0]M_AXI_GP1_ARBURST; + output [1:0]M_AXI_GP1_ARLOCK; + output [2:0]M_AXI_GP1_ARSIZE; + output [1:0]M_AXI_GP1_AWBURST; + output [1:0]M_AXI_GP1_AWLOCK; + output [2:0]M_AXI_GP1_AWSIZE; + output [2:0]M_AXI_GP1_ARPROT; + output [2:0]M_AXI_GP1_AWPROT; + output [31:0]M_AXI_GP1_ARADDR; + output [31:0]M_AXI_GP1_AWADDR; + output [31:0]M_AXI_GP1_WDATA; + output [3:0]M_AXI_GP1_ARCACHE; + output [3:0]M_AXI_GP1_ARLEN; + output [3:0]M_AXI_GP1_ARQOS; + output [3:0]M_AXI_GP1_AWCACHE; + output [3:0]M_AXI_GP1_AWLEN; + output [3:0]M_AXI_GP1_AWQOS; + output [3:0]M_AXI_GP1_WSTRB; + input M_AXI_GP1_ACLK; + input M_AXI_GP1_ARREADY; + input M_AXI_GP1_AWREADY; + input M_AXI_GP1_BVALID; + input M_AXI_GP1_RLAST; + input M_AXI_GP1_RVALID; + input M_AXI_GP1_WREADY; + input [11:0]M_AXI_GP1_BID; + input [11:0]M_AXI_GP1_RID; + input [1:0]M_AXI_GP1_BRESP; + input [1:0]M_AXI_GP1_RRESP; + input [31:0]M_AXI_GP1_RDATA; + output S_AXI_GP0_ARESETN; + output S_AXI_GP0_ARREADY; + output S_AXI_GP0_AWREADY; + output S_AXI_GP0_BVALID; + output S_AXI_GP0_RLAST; + output S_AXI_GP0_RVALID; + output S_AXI_GP0_WREADY; + output [1:0]S_AXI_GP0_BRESP; + output [1:0]S_AXI_GP0_RRESP; + output [31:0]S_AXI_GP0_RDATA; + output [5:0]S_AXI_GP0_BID; + output [5:0]S_AXI_GP0_RID; + input S_AXI_GP0_ACLK; + input S_AXI_GP0_ARVALID; + input S_AXI_GP0_AWVALID; + input S_AXI_GP0_BREADY; + input S_AXI_GP0_RREADY; + input S_AXI_GP0_WLAST; + input S_AXI_GP0_WVALID; + input [1:0]S_AXI_GP0_ARBURST; + input [1:0]S_AXI_GP0_ARLOCK; + input [2:0]S_AXI_GP0_ARSIZE; + input [1:0]S_AXI_GP0_AWBURST; + input [1:0]S_AXI_GP0_AWLOCK; + input [2:0]S_AXI_GP0_AWSIZE; + input [2:0]S_AXI_GP0_ARPROT; + input [2:0]S_AXI_GP0_AWPROT; + input [31:0]S_AXI_GP0_ARADDR; + input [31:0]S_AXI_GP0_AWADDR; + input [31:0]S_AXI_GP0_WDATA; + input [3:0]S_AXI_GP0_ARCACHE; + input [3:0]S_AXI_GP0_ARLEN; + input [3:0]S_AXI_GP0_ARQOS; + input [3:0]S_AXI_GP0_AWCACHE; + input [3:0]S_AXI_GP0_AWLEN; + input [3:0]S_AXI_GP0_AWQOS; + input [3:0]S_AXI_GP0_WSTRB; + input [5:0]S_AXI_GP0_ARID; + input [5:0]S_AXI_GP0_AWID; + input [5:0]S_AXI_GP0_WID; + output S_AXI_GP1_ARESETN; + output S_AXI_GP1_ARREADY; + output S_AXI_GP1_AWREADY; + output S_AXI_GP1_BVALID; + output S_AXI_GP1_RLAST; + output S_AXI_GP1_RVALID; + output S_AXI_GP1_WREADY; + output [1:0]S_AXI_GP1_BRESP; + output [1:0]S_AXI_GP1_RRESP; + output [31:0]S_AXI_GP1_RDATA; + output [5:0]S_AXI_GP1_BID; + output [5:0]S_AXI_GP1_RID; + input S_AXI_GP1_ACLK; + input S_AXI_GP1_ARVALID; + input S_AXI_GP1_AWVALID; + input S_AXI_GP1_BREADY; + input S_AXI_GP1_RREADY; + input S_AXI_GP1_WLAST; + input S_AXI_GP1_WVALID; + input [1:0]S_AXI_GP1_ARBURST; + input [1:0]S_AXI_GP1_ARLOCK; + input [2:0]S_AXI_GP1_ARSIZE; + input [1:0]S_AXI_GP1_AWBURST; + input [1:0]S_AXI_GP1_AWLOCK; + input [2:0]S_AXI_GP1_AWSIZE; + input [2:0]S_AXI_GP1_ARPROT; + input [2:0]S_AXI_GP1_AWPROT; + input [31:0]S_AXI_GP1_ARADDR; + input [31:0]S_AXI_GP1_AWADDR; + input [31:0]S_AXI_GP1_WDATA; + input [3:0]S_AXI_GP1_ARCACHE; + input [3:0]S_AXI_GP1_ARLEN; + input [3:0]S_AXI_GP1_ARQOS; + input [3:0]S_AXI_GP1_AWCACHE; + input [3:0]S_AXI_GP1_AWLEN; + input [3:0]S_AXI_GP1_AWQOS; + input [3:0]S_AXI_GP1_WSTRB; + input [5:0]S_AXI_GP1_ARID; + input [5:0]S_AXI_GP1_AWID; + input [5:0]S_AXI_GP1_WID; + output S_AXI_ACP_ARESETN; + output S_AXI_ACP_ARREADY; + output S_AXI_ACP_AWREADY; + output S_AXI_ACP_BVALID; + output S_AXI_ACP_RLAST; + output S_AXI_ACP_RVALID; + output S_AXI_ACP_WREADY; + output [1:0]S_AXI_ACP_BRESP; + output [1:0]S_AXI_ACP_RRESP; + output [2:0]S_AXI_ACP_BID; + output [2:0]S_AXI_ACP_RID; + output [63:0]S_AXI_ACP_RDATA; + input S_AXI_ACP_ACLK; + input S_AXI_ACP_ARVALID; + input S_AXI_ACP_AWVALID; + input S_AXI_ACP_BREADY; + input S_AXI_ACP_RREADY; + input S_AXI_ACP_WLAST; + input S_AXI_ACP_WVALID; + input [2:0]S_AXI_ACP_ARID; + input [2:0]S_AXI_ACP_ARPROT; + input [2:0]S_AXI_ACP_AWID; + input [2:0]S_AXI_ACP_AWPROT; + input [2:0]S_AXI_ACP_WID; + input [31:0]S_AXI_ACP_ARADDR; + input [31:0]S_AXI_ACP_AWADDR; + input [3:0]S_AXI_ACP_ARCACHE; + input [3:0]S_AXI_ACP_ARLEN; + input [3:0]S_AXI_ACP_ARQOS; + input [3:0]S_AXI_ACP_AWCACHE; + input [3:0]S_AXI_ACP_AWLEN; + input [3:0]S_AXI_ACP_AWQOS; + input [1:0]S_AXI_ACP_ARBURST; + input [1:0]S_AXI_ACP_ARLOCK; + input [2:0]S_AXI_ACP_ARSIZE; + input [1:0]S_AXI_ACP_AWBURST; + input [1:0]S_AXI_ACP_AWLOCK; + input [2:0]S_AXI_ACP_AWSIZE; + input [4:0]S_AXI_ACP_ARUSER; + input [4:0]S_AXI_ACP_AWUSER; + input [63:0]S_AXI_ACP_WDATA; + input [7:0]S_AXI_ACP_WSTRB; + output S_AXI_HP0_ARESETN; + output S_AXI_HP0_ARREADY; + output S_AXI_HP0_AWREADY; + output S_AXI_HP0_BVALID; + output S_AXI_HP0_RLAST; + output S_AXI_HP0_RVALID; + output S_AXI_HP0_WREADY; + output [1:0]S_AXI_HP0_BRESP; + output [1:0]S_AXI_HP0_RRESP; + output [5:0]S_AXI_HP0_BID; + output [5:0]S_AXI_HP0_RID; + output [63:0]S_AXI_HP0_RDATA; + output [7:0]S_AXI_HP0_RCOUNT; + output [7:0]S_AXI_HP0_WCOUNT; + output [2:0]S_AXI_HP0_RACOUNT; + output [5:0]S_AXI_HP0_WACOUNT; + input S_AXI_HP0_ACLK; + input S_AXI_HP0_ARVALID; + input S_AXI_HP0_AWVALID; + input S_AXI_HP0_BREADY; + input S_AXI_HP0_RDISSUECAP1_EN; + input S_AXI_HP0_RREADY; + input S_AXI_HP0_WLAST; + input S_AXI_HP0_WRISSUECAP1_EN; + input S_AXI_HP0_WVALID; + input [1:0]S_AXI_HP0_ARBURST; + input [1:0]S_AXI_HP0_ARLOCK; + input [2:0]S_AXI_HP0_ARSIZE; + input [1:0]S_AXI_HP0_AWBURST; + input [1:0]S_AXI_HP0_AWLOCK; + input [2:0]S_AXI_HP0_AWSIZE; + input [2:0]S_AXI_HP0_ARPROT; + input [2:0]S_AXI_HP0_AWPROT; + input [31:0]S_AXI_HP0_ARADDR; + input [31:0]S_AXI_HP0_AWADDR; + input [3:0]S_AXI_HP0_ARCACHE; + input [3:0]S_AXI_HP0_ARLEN; + input [3:0]S_AXI_HP0_ARQOS; + input [3:0]S_AXI_HP0_AWCACHE; + input [3:0]S_AXI_HP0_AWLEN; + input [3:0]S_AXI_HP0_AWQOS; + input [5:0]S_AXI_HP0_ARID; + input [5:0]S_AXI_HP0_AWID; + input [5:0]S_AXI_HP0_WID; + input [63:0]S_AXI_HP0_WDATA; + input [7:0]S_AXI_HP0_WSTRB; + output S_AXI_HP1_ARESETN; + output S_AXI_HP1_ARREADY; + output S_AXI_HP1_AWREADY; + output S_AXI_HP1_BVALID; + output S_AXI_HP1_RLAST; + output S_AXI_HP1_RVALID; + output S_AXI_HP1_WREADY; + output [1:0]S_AXI_HP1_BRESP; + output [1:0]S_AXI_HP1_RRESP; + output [5:0]S_AXI_HP1_BID; + output [5:0]S_AXI_HP1_RID; + output [63:0]S_AXI_HP1_RDATA; + output [7:0]S_AXI_HP1_RCOUNT; + output [7:0]S_AXI_HP1_WCOUNT; + output [2:0]S_AXI_HP1_RACOUNT; + output [5:0]S_AXI_HP1_WACOUNT; + input S_AXI_HP1_ACLK; + input S_AXI_HP1_ARVALID; + input S_AXI_HP1_AWVALID; + input S_AXI_HP1_BREADY; + input S_AXI_HP1_RDISSUECAP1_EN; + input S_AXI_HP1_RREADY; + input S_AXI_HP1_WLAST; + input S_AXI_HP1_WRISSUECAP1_EN; + input S_AXI_HP1_WVALID; + input [1:0]S_AXI_HP1_ARBURST; + input [1:0]S_AXI_HP1_ARLOCK; + input [2:0]S_AXI_HP1_ARSIZE; + input [1:0]S_AXI_HP1_AWBURST; + input [1:0]S_AXI_HP1_AWLOCK; + input [2:0]S_AXI_HP1_AWSIZE; + input [2:0]S_AXI_HP1_ARPROT; + input [2:0]S_AXI_HP1_AWPROT; + input [31:0]S_AXI_HP1_ARADDR; + input [31:0]S_AXI_HP1_AWADDR; + input [3:0]S_AXI_HP1_ARCACHE; + input [3:0]S_AXI_HP1_ARLEN; + input [3:0]S_AXI_HP1_ARQOS; + input [3:0]S_AXI_HP1_AWCACHE; + input [3:0]S_AXI_HP1_AWLEN; + input [3:0]S_AXI_HP1_AWQOS; + input [5:0]S_AXI_HP1_ARID; + input [5:0]S_AXI_HP1_AWID; + input [5:0]S_AXI_HP1_WID; + input [63:0]S_AXI_HP1_WDATA; + input [7:0]S_AXI_HP1_WSTRB; + output S_AXI_HP2_ARESETN; + output S_AXI_HP2_ARREADY; + output S_AXI_HP2_AWREADY; + output S_AXI_HP2_BVALID; + output S_AXI_HP2_RLAST; + output S_AXI_HP2_RVALID; + output S_AXI_HP2_WREADY; + output [1:0]S_AXI_HP2_BRESP; + output [1:0]S_AXI_HP2_RRESP; + output [5:0]S_AXI_HP2_BID; + output [5:0]S_AXI_HP2_RID; + output [63:0]S_AXI_HP2_RDATA; + output [7:0]S_AXI_HP2_RCOUNT; + output [7:0]S_AXI_HP2_WCOUNT; + output [2:0]S_AXI_HP2_RACOUNT; + output [5:0]S_AXI_HP2_WACOUNT; + input S_AXI_HP2_ACLK; + input S_AXI_HP2_ARVALID; + input S_AXI_HP2_AWVALID; + input S_AXI_HP2_BREADY; + input S_AXI_HP2_RDISSUECAP1_EN; + input S_AXI_HP2_RREADY; + input S_AXI_HP2_WLAST; + input S_AXI_HP2_WRISSUECAP1_EN; + input S_AXI_HP2_WVALID; + input [1:0]S_AXI_HP2_ARBURST; + input [1:0]S_AXI_HP2_ARLOCK; + input [2:0]S_AXI_HP2_ARSIZE; + input [1:0]S_AXI_HP2_AWBURST; + input [1:0]S_AXI_HP2_AWLOCK; + input [2:0]S_AXI_HP2_AWSIZE; + input [2:0]S_AXI_HP2_ARPROT; + input [2:0]S_AXI_HP2_AWPROT; + input [31:0]S_AXI_HP2_ARADDR; + input [31:0]S_AXI_HP2_AWADDR; + input [3:0]S_AXI_HP2_ARCACHE; + input [3:0]S_AXI_HP2_ARLEN; + input [3:0]S_AXI_HP2_ARQOS; + input [3:0]S_AXI_HP2_AWCACHE; + input [3:0]S_AXI_HP2_AWLEN; + input [3:0]S_AXI_HP2_AWQOS; + input [5:0]S_AXI_HP2_ARID; + input [5:0]S_AXI_HP2_AWID; + input [5:0]S_AXI_HP2_WID; + input [63:0]S_AXI_HP2_WDATA; + input [7:0]S_AXI_HP2_WSTRB; + output S_AXI_HP3_ARESETN; + output S_AXI_HP3_ARREADY; + output S_AXI_HP3_AWREADY; + output S_AXI_HP3_BVALID; + output S_AXI_HP3_RLAST; + output S_AXI_HP3_RVALID; + output S_AXI_HP3_WREADY; + output [1:0]S_AXI_HP3_BRESP; + output [1:0]S_AXI_HP3_RRESP; + output [5:0]S_AXI_HP3_BID; + output [5:0]S_AXI_HP3_RID; + output [63:0]S_AXI_HP3_RDATA; + output [7:0]S_AXI_HP3_RCOUNT; + output [7:0]S_AXI_HP3_WCOUNT; + output [2:0]S_AXI_HP3_RACOUNT; + output [5:0]S_AXI_HP3_WACOUNT; + input S_AXI_HP3_ACLK; + input S_AXI_HP3_ARVALID; + input S_AXI_HP3_AWVALID; + input S_AXI_HP3_BREADY; + input S_AXI_HP3_RDISSUECAP1_EN; + input S_AXI_HP3_RREADY; + input S_AXI_HP3_WLAST; + input S_AXI_HP3_WRISSUECAP1_EN; + input S_AXI_HP3_WVALID; + input [1:0]S_AXI_HP3_ARBURST; + input [1:0]S_AXI_HP3_ARLOCK; + input [2:0]S_AXI_HP3_ARSIZE; + input [1:0]S_AXI_HP3_AWBURST; + input [1:0]S_AXI_HP3_AWLOCK; + input [2:0]S_AXI_HP3_AWSIZE; + input [2:0]S_AXI_HP3_ARPROT; + input [2:0]S_AXI_HP3_AWPROT; + input [31:0]S_AXI_HP3_ARADDR; + input [31:0]S_AXI_HP3_AWADDR; + input [3:0]S_AXI_HP3_ARCACHE; + input [3:0]S_AXI_HP3_ARLEN; + input [3:0]S_AXI_HP3_ARQOS; + input [3:0]S_AXI_HP3_AWCACHE; + input [3:0]S_AXI_HP3_AWLEN; + input [3:0]S_AXI_HP3_AWQOS; + input [5:0]S_AXI_HP3_ARID; + input [5:0]S_AXI_HP3_AWID; + input [5:0]S_AXI_HP3_WID; + input [63:0]S_AXI_HP3_WDATA; + input [7:0]S_AXI_HP3_WSTRB; + output IRQ_P2F_DMAC_ABORT; + output IRQ_P2F_DMAC0; + output IRQ_P2F_DMAC1; + output IRQ_P2F_DMAC2; + output IRQ_P2F_DMAC3; + output IRQ_P2F_DMAC4; + output IRQ_P2F_DMAC5; + output IRQ_P2F_DMAC6; + output IRQ_P2F_DMAC7; + output IRQ_P2F_SMC; + output IRQ_P2F_QSPI; + output IRQ_P2F_CTI; + output IRQ_P2F_GPIO; + output IRQ_P2F_USB0; + output IRQ_P2F_ENET0; + output IRQ_P2F_ENET_WAKE0; + output IRQ_P2F_SDIO0; + output IRQ_P2F_I2C0; + output IRQ_P2F_SPI0; + output IRQ_P2F_UART0; + output IRQ_P2F_CAN0; + output IRQ_P2F_USB1; + output IRQ_P2F_ENET1; + output IRQ_P2F_ENET_WAKE1; + output IRQ_P2F_SDIO1; + output IRQ_P2F_I2C1; + output IRQ_P2F_SPI1; + output IRQ_P2F_UART1; + output IRQ_P2F_CAN1; + input [1:0]IRQ_F2P; + input Core0_nFIQ; + input Core0_nIRQ; + input Core1_nFIQ; + input Core1_nIRQ; + output [1:0]DMA0_DATYPE; + output DMA0_DAVALID; + output DMA0_DRREADY; + output DMA0_RSTN; + output [1:0]DMA1_DATYPE; + output DMA1_DAVALID; + output DMA1_DRREADY; + output DMA1_RSTN; + output [1:0]DMA2_DATYPE; + output DMA2_DAVALID; + output DMA2_DRREADY; + output DMA2_RSTN; + output [1:0]DMA3_DATYPE; + output DMA3_DAVALID; + output DMA3_DRREADY; + output DMA3_RSTN; + input DMA0_ACLK; + input DMA0_DAREADY; + input DMA0_DRLAST; + input DMA0_DRVALID; + input DMA1_ACLK; + input DMA1_DAREADY; + input DMA1_DRLAST; + input DMA1_DRVALID; + input DMA2_ACLK; + input DMA2_DAREADY; + input DMA2_DRLAST; + input DMA2_DRVALID; + input DMA3_ACLK; + input DMA3_DAREADY; + input DMA3_DRLAST; + input DMA3_DRVALID; + input [1:0]DMA0_DRTYPE; + input [1:0]DMA1_DRTYPE; + input [1:0]DMA2_DRTYPE; + input [1:0]DMA3_DRTYPE; + output FCLK_CLK3; + output FCLK_CLK2; + output FCLK_CLK1; + output FCLK_CLK0; + input FCLK_CLKTRIG3_N; + input FCLK_CLKTRIG2_N; + input FCLK_CLKTRIG1_N; + input FCLK_CLKTRIG0_N; + output FCLK_RESET3_N; + output FCLK_RESET2_N; + output FCLK_RESET1_N; + output FCLK_RESET0_N; + input [31:0]FTMD_TRACEIN_DATA; + input FTMD_TRACEIN_VALID; + input FTMD_TRACEIN_CLK; + input [3:0]FTMD_TRACEIN_ATID; + input FTMT_F2P_TRIG_0; + output FTMT_F2P_TRIGACK_0; + input FTMT_F2P_TRIG_1; + output FTMT_F2P_TRIGACK_1; + input FTMT_F2P_TRIG_2; + output FTMT_F2P_TRIGACK_2; + input FTMT_F2P_TRIG_3; + output FTMT_F2P_TRIGACK_3; + input [31:0]FTMT_F2P_DEBUG; + input FTMT_P2F_TRIGACK_0; + output FTMT_P2F_TRIG_0; + input FTMT_P2F_TRIGACK_1; + output FTMT_P2F_TRIG_1; + input FTMT_P2F_TRIGACK_2; + output FTMT_P2F_TRIG_2; + input FTMT_P2F_TRIGACK_3; + output FTMT_P2F_TRIG_3; + output [31:0]FTMT_P2F_DEBUG; + input FPGA_IDLE_N; + output EVENT_EVENTO; + output [1:0]EVENT_STANDBYWFE; + output [1:0]EVENT_STANDBYWFI; + input EVENT_EVENTI; + input [3:0]DDR_ARB; + inout [53:0]MIO; + inout DDR_CAS_n; + inout DDR_CKE; + inout DDR_Clk_n; + inout DDR_Clk; + inout DDR_CS_n; + inout DDR_DRSTB; + inout DDR_ODT; + inout DDR_RAS_n; + inout DDR_WEB; + inout [2:0]DDR_BankAddr; + inout [14:0]DDR_Addr; + inout DDR_VRN; + inout DDR_VRP; + inout [3:0]DDR_DM; + inout [31:0]DDR_DQ; + inout [3:0]DDR_DQS_n; + inout [3:0]DDR_DQS; + inout PS_SRSTB; + inout PS_CLK; + inout PS_PORB; + + wire \ ; + wire \ ; + wire CAN0_PHY_RX; + wire CAN0_PHY_TX; + wire CAN1_PHY_RX; + wire CAN1_PHY_TX; + wire Core0_nFIQ; + wire Core0_nIRQ; + wire Core1_nFIQ; + wire Core1_nIRQ; + wire [3:0]DDR_ARB; + wire [14:0]DDR_Addr; + wire [2:0]DDR_BankAddr; + wire DDR_CAS_n; + wire DDR_CKE; + wire DDR_CS_n; + wire DDR_Clk; + wire DDR_Clk_n; + wire [3:0]DDR_DM; + wire [31:0]DDR_DQ; + wire [3:0]DDR_DQS; + wire [3:0]DDR_DQS_n; + wire DDR_DRSTB; + wire DDR_ODT; + wire DDR_RAS_n; + wire DDR_VRN; + wire DDR_VRP; + wire DDR_WEB; + wire DMA0_ACLK; + wire DMA0_DAREADY; + wire [1:0]DMA0_DATYPE; + wire DMA0_DAVALID; + wire DMA0_DRLAST; + wire DMA0_DRREADY; + wire [1:0]DMA0_DRTYPE; + wire DMA0_DRVALID; + wire DMA0_RSTN; + wire DMA1_ACLK; + wire DMA1_DAREADY; + wire [1:0]DMA1_DATYPE; + wire DMA1_DAVALID; + wire DMA1_DRLAST; + wire DMA1_DRREADY; + wire [1:0]DMA1_DRTYPE; + wire DMA1_DRVALID; + wire DMA1_RSTN; + wire DMA2_ACLK; + wire DMA2_DAREADY; + wire [1:0]DMA2_DATYPE; + wire DMA2_DAVALID; + wire DMA2_DRLAST; + wire DMA2_DRREADY; + wire [1:0]DMA2_DRTYPE; + wire DMA2_DRVALID; + wire DMA2_RSTN; + wire DMA3_ACLK; + wire DMA3_DAREADY; + wire [1:0]DMA3_DATYPE; + wire DMA3_DAVALID; + wire DMA3_DRLAST; + wire DMA3_DRREADY; + wire [1:0]DMA3_DRTYPE; + wire DMA3_DRVALID; + wire DMA3_RSTN; + wire ENET0_EXT_INTIN; + wire ENET0_GMII_RX_CLK; + wire ENET0_GMII_TX_CLK; + wire ENET0_MDIO_I; + wire ENET0_MDIO_MDC; + wire ENET0_MDIO_O; + wire ENET0_MDIO_T; + wire ENET0_MDIO_T_n; + wire ENET0_PTP_DELAY_REQ_RX; + wire ENET0_PTP_DELAY_REQ_TX; + wire ENET0_PTP_PDELAY_REQ_RX; + wire ENET0_PTP_PDELAY_REQ_TX; + wire ENET0_PTP_PDELAY_RESP_RX; + wire ENET0_PTP_PDELAY_RESP_TX; + wire ENET0_PTP_SYNC_FRAME_RX; + wire ENET0_PTP_SYNC_FRAME_TX; + wire ENET0_SOF_RX; + wire ENET0_SOF_TX; + wire ENET1_EXT_INTIN; + wire ENET1_GMII_RX_CLK; + wire ENET1_GMII_TX_CLK; + wire ENET1_MDIO_I; + wire ENET1_MDIO_MDC; + wire ENET1_MDIO_O; + wire ENET1_MDIO_T; + wire ENET1_MDIO_T_n; + wire ENET1_PTP_DELAY_REQ_RX; + wire ENET1_PTP_DELAY_REQ_TX; + wire ENET1_PTP_PDELAY_REQ_RX; + wire ENET1_PTP_PDELAY_REQ_TX; + wire ENET1_PTP_PDELAY_RESP_RX; + wire ENET1_PTP_PDELAY_RESP_TX; + wire ENET1_PTP_SYNC_FRAME_RX; + wire ENET1_PTP_SYNC_FRAME_TX; + wire ENET1_SOF_RX; + wire ENET1_SOF_TX; + wire EVENT_EVENTI; + wire EVENT_EVENTO; + wire [1:0]EVENT_STANDBYWFE; + wire [1:0]EVENT_STANDBYWFI; + wire FCLK_CLK0; + wire FCLK_CLK1; + wire FCLK_CLK2; + wire FCLK_CLK3; + wire [0:0]FCLK_CLK_unbuffered; + wire FCLK_RESET0_N; + wire FCLK_RESET1_N; + wire FCLK_RESET2_N; + wire FCLK_RESET3_N; + wire FPGA_IDLE_N; + wire FTMD_TRACEIN_CLK; + wire [31:0]FTMT_F2P_DEBUG; + wire FTMT_F2P_TRIGACK_0; + wire FTMT_F2P_TRIGACK_1; + wire FTMT_F2P_TRIGACK_2; + wire FTMT_F2P_TRIGACK_3; + wire FTMT_F2P_TRIG_0; + wire FTMT_F2P_TRIG_1; + wire FTMT_F2P_TRIG_2; + wire FTMT_F2P_TRIG_3; + wire [31:0]FTMT_P2F_DEBUG; + wire FTMT_P2F_TRIGACK_0; + wire FTMT_P2F_TRIGACK_1; + wire FTMT_P2F_TRIGACK_2; + wire FTMT_P2F_TRIGACK_3; + wire FTMT_P2F_TRIG_0; + wire FTMT_P2F_TRIG_1; + wire FTMT_P2F_TRIG_2; + wire FTMT_P2F_TRIG_3; + wire [63:0]GPIO_I; + wire [63:0]GPIO_O; + wire [63:0]GPIO_T; + wire I2C0_SCL_I; + wire I2C0_SCL_O; + wire I2C0_SCL_T; + wire I2C0_SCL_T_n; + wire I2C0_SDA_I; + wire I2C0_SDA_O; + wire I2C0_SDA_T; + wire I2C0_SDA_T_n; + wire I2C1_SCL_I; + wire I2C1_SCL_O; + wire I2C1_SCL_T; + wire I2C1_SCL_T_n; + wire I2C1_SDA_I; + wire I2C1_SDA_O; + wire I2C1_SDA_T; + wire I2C1_SDA_T_n; + wire [1:0]IRQ_F2P; + wire IRQ_P2F_CAN0; + wire IRQ_P2F_CAN1; + wire IRQ_P2F_CTI; + wire IRQ_P2F_DMAC0; + wire IRQ_P2F_DMAC1; + wire IRQ_P2F_DMAC2; + wire IRQ_P2F_DMAC3; + wire IRQ_P2F_DMAC4; + wire IRQ_P2F_DMAC5; + wire IRQ_P2F_DMAC6; + wire IRQ_P2F_DMAC7; + wire IRQ_P2F_DMAC_ABORT; + wire IRQ_P2F_ENET0; + wire IRQ_P2F_ENET1; + wire IRQ_P2F_ENET_WAKE0; + wire IRQ_P2F_ENET_WAKE1; + wire IRQ_P2F_GPIO; + wire IRQ_P2F_I2C0; + wire IRQ_P2F_I2C1; + wire IRQ_P2F_QSPI; + wire IRQ_P2F_SDIO0; + wire IRQ_P2F_SDIO1; + wire IRQ_P2F_SMC; + wire IRQ_P2F_SPI0; + wire IRQ_P2F_SPI1; + wire IRQ_P2F_UART0; + wire IRQ_P2F_UART1; + wire IRQ_P2F_USB0; + wire IRQ_P2F_USB1; + wire [53:0]MIO; + wire M_AXI_GP0_ACLK; + wire [31:0]M_AXI_GP0_ARADDR; + wire [1:0]M_AXI_GP0_ARBURST; + wire [3:0]\^M_AXI_GP0_ARCACHE ; + wire M_AXI_GP0_ARESETN; + wire [11:0]M_AXI_GP0_ARID; + wire [3:0]M_AXI_GP0_ARLEN; + wire [1:0]M_AXI_GP0_ARLOCK; + wire [2:0]M_AXI_GP0_ARPROT; + wire [3:0]M_AXI_GP0_ARQOS; + wire M_AXI_GP0_ARREADY; + wire [1:0]\^M_AXI_GP0_ARSIZE ; + wire M_AXI_GP0_ARVALID; + wire [31:0]M_AXI_GP0_AWADDR; + wire [1:0]M_AXI_GP0_AWBURST; + wire [3:0]\^M_AXI_GP0_AWCACHE ; + wire [11:0]M_AXI_GP0_AWID; + wire [3:0]M_AXI_GP0_AWLEN; + wire [1:0]M_AXI_GP0_AWLOCK; + wire [2:0]M_AXI_GP0_AWPROT; + wire [3:0]M_AXI_GP0_AWQOS; + wire M_AXI_GP0_AWREADY; + wire [1:0]\^M_AXI_GP0_AWSIZE ; + wire M_AXI_GP0_AWVALID; + wire [11:0]M_AXI_GP0_BID; + wire M_AXI_GP0_BREADY; + wire [1:0]M_AXI_GP0_BRESP; + wire M_AXI_GP0_BVALID; + wire [31:0]M_AXI_GP0_RDATA; + wire [11:0]M_AXI_GP0_RID; + wire M_AXI_GP0_RLAST; + wire M_AXI_GP0_RREADY; + wire [1:0]M_AXI_GP0_RRESP; + wire M_AXI_GP0_RVALID; + wire [31:0]M_AXI_GP0_WDATA; + wire [11:0]M_AXI_GP0_WID; + wire M_AXI_GP0_WLAST; + wire M_AXI_GP0_WREADY; + wire [3:0]M_AXI_GP0_WSTRB; + wire M_AXI_GP0_WVALID; + wire M_AXI_GP1_ACLK; + wire [31:0]M_AXI_GP1_ARADDR; + wire [1:0]M_AXI_GP1_ARBURST; + wire [3:0]\^M_AXI_GP1_ARCACHE ; + wire M_AXI_GP1_ARESETN; + wire [11:0]M_AXI_GP1_ARID; + wire [3:0]M_AXI_GP1_ARLEN; + wire [1:0]M_AXI_GP1_ARLOCK; + wire [2:0]M_AXI_GP1_ARPROT; + wire [3:0]M_AXI_GP1_ARQOS; + wire M_AXI_GP1_ARREADY; + wire [1:0]\^M_AXI_GP1_ARSIZE ; + wire M_AXI_GP1_ARVALID; + wire [31:0]M_AXI_GP1_AWADDR; + wire [1:0]M_AXI_GP1_AWBURST; + wire [3:0]\^M_AXI_GP1_AWCACHE ; + wire [11:0]M_AXI_GP1_AWID; + wire [3:0]M_AXI_GP1_AWLEN; + wire [1:0]M_AXI_GP1_AWLOCK; + wire [2:0]M_AXI_GP1_AWPROT; + wire [3:0]M_AXI_GP1_AWQOS; + wire M_AXI_GP1_AWREADY; + wire [1:0]\^M_AXI_GP1_AWSIZE ; + wire M_AXI_GP1_AWVALID; + wire [11:0]M_AXI_GP1_BID; + wire M_AXI_GP1_BREADY; + wire [1:0]M_AXI_GP1_BRESP; + wire M_AXI_GP1_BVALID; + wire [31:0]M_AXI_GP1_RDATA; + wire [11:0]M_AXI_GP1_RID; + wire M_AXI_GP1_RLAST; + wire M_AXI_GP1_RREADY; + wire [1:0]M_AXI_GP1_RRESP; + wire M_AXI_GP1_RVALID; + wire [31:0]M_AXI_GP1_WDATA; + wire [11:0]M_AXI_GP1_WID; + wire M_AXI_GP1_WLAST; + wire M_AXI_GP1_WREADY; + wire [3:0]M_AXI_GP1_WSTRB; + wire M_AXI_GP1_WVALID; + wire PJTAG_TCK; + wire PJTAG_TDI; + wire PJTAG_TMS; + wire PS_CLK; + wire PS_PORB; + wire PS_SRSTB; + wire SDIO0_BUSPOW; + wire [2:0]SDIO0_BUSVOLT; + wire SDIO0_CDN; + wire SDIO0_CLK; + wire SDIO0_CLK_FB; + wire SDIO0_CMD_I; + wire SDIO0_CMD_O; + wire SDIO0_CMD_T; + wire SDIO0_CMD_T_n; + wire [3:0]SDIO0_DATA_I; + wire [3:0]SDIO0_DATA_O; + wire [3:0]SDIO0_DATA_T; + wire [3:0]SDIO0_DATA_T_n; + wire SDIO0_LED; + wire SDIO0_WP; + wire SDIO1_BUSPOW; + wire [2:0]SDIO1_BUSVOLT; + wire SDIO1_CDN; + wire SDIO1_CLK; + wire SDIO1_CLK_FB; + wire SDIO1_CMD_I; + wire SDIO1_CMD_O; + wire SDIO1_CMD_T; + wire SDIO1_CMD_T_n; + wire [3:0]SDIO1_DATA_I; + wire [3:0]SDIO1_DATA_O; + wire [3:0]SDIO1_DATA_T; + wire [3:0]SDIO1_DATA_T_n; + wire SDIO1_LED; + wire SDIO1_WP; + wire SPI0_MISO_I; + wire SPI0_MISO_O; + wire SPI0_MISO_T; + wire SPI0_MISO_T_n; + wire SPI0_MOSI_I; + wire SPI0_MOSI_O; + wire SPI0_MOSI_T; + wire SPI0_MOSI_T_n; + wire SPI0_SCLK_I; + wire SPI0_SCLK_O; + wire SPI0_SCLK_T; + wire SPI0_SCLK_T_n; + wire SPI0_SS1_O; + wire SPI0_SS2_O; + wire SPI0_SS_I; + wire SPI0_SS_O; + wire SPI0_SS_T; + wire SPI0_SS_T_n; + wire SPI1_MISO_I; + wire SPI1_MISO_O; + wire SPI1_MISO_T; + wire SPI1_MISO_T_n; + wire SPI1_MOSI_I; + wire SPI1_MOSI_O; + wire SPI1_MOSI_T; + wire SPI1_MOSI_T_n; + wire SPI1_SCLK_I; + wire SPI1_SCLK_O; + wire SPI1_SCLK_T; + wire SPI1_SCLK_T_n; + wire SPI1_SS1_O; + wire SPI1_SS2_O; + wire SPI1_SS_I; + wire SPI1_SS_O; + wire SPI1_SS_T; + wire SPI1_SS_T_n; + wire SRAM_INTIN; + wire S_AXI_ACP_ACLK; + wire [31:0]S_AXI_ACP_ARADDR; + wire [1:0]S_AXI_ACP_ARBURST; + wire [3:0]S_AXI_ACP_ARCACHE; + wire S_AXI_ACP_ARESETN; + wire [2:0]S_AXI_ACP_ARID; + wire [3:0]S_AXI_ACP_ARLEN; + wire [1:0]S_AXI_ACP_ARLOCK; + wire [2:0]S_AXI_ACP_ARPROT; + wire [3:0]S_AXI_ACP_ARQOS; + wire S_AXI_ACP_ARREADY; + wire [2:0]S_AXI_ACP_ARSIZE; + wire [4:0]S_AXI_ACP_ARUSER; + wire S_AXI_ACP_ARVALID; + wire [31:0]S_AXI_ACP_AWADDR; + wire [1:0]S_AXI_ACP_AWBURST; + wire [3:0]S_AXI_ACP_AWCACHE; + wire [2:0]S_AXI_ACP_AWID; + wire [3:0]S_AXI_ACP_AWLEN; + wire [1:0]S_AXI_ACP_AWLOCK; + wire [2:0]S_AXI_ACP_AWPROT; + wire [3:0]S_AXI_ACP_AWQOS; + wire S_AXI_ACP_AWREADY; + wire [2:0]S_AXI_ACP_AWSIZE; + wire [4:0]S_AXI_ACP_AWUSER; + wire S_AXI_ACP_AWVALID; + wire [2:0]S_AXI_ACP_BID; + wire S_AXI_ACP_BREADY; + wire [1:0]S_AXI_ACP_BRESP; + wire S_AXI_ACP_BVALID; + wire [63:0]S_AXI_ACP_RDATA; + wire [2:0]S_AXI_ACP_RID; + wire S_AXI_ACP_RLAST; + wire S_AXI_ACP_RREADY; + wire [1:0]S_AXI_ACP_RRESP; + wire S_AXI_ACP_RVALID; + wire [63:0]S_AXI_ACP_WDATA; + wire [2:0]S_AXI_ACP_WID; + wire S_AXI_ACP_WLAST; + wire S_AXI_ACP_WREADY; + wire [7:0]S_AXI_ACP_WSTRB; + wire S_AXI_ACP_WVALID; + wire S_AXI_GP0_ACLK; + wire [31:0]S_AXI_GP0_ARADDR; + wire [1:0]S_AXI_GP0_ARBURST; + wire [3:0]S_AXI_GP0_ARCACHE; + wire S_AXI_GP0_ARESETN; + wire [5:0]S_AXI_GP0_ARID; + wire [3:0]S_AXI_GP0_ARLEN; + wire [1:0]S_AXI_GP0_ARLOCK; + wire [2:0]S_AXI_GP0_ARPROT; + wire [3:0]S_AXI_GP0_ARQOS; + wire S_AXI_GP0_ARREADY; + wire [2:0]S_AXI_GP0_ARSIZE; + wire S_AXI_GP0_ARVALID; + wire [31:0]S_AXI_GP0_AWADDR; + wire [1:0]S_AXI_GP0_AWBURST; + wire [3:0]S_AXI_GP0_AWCACHE; + wire [5:0]S_AXI_GP0_AWID; + wire [3:0]S_AXI_GP0_AWLEN; + wire [1:0]S_AXI_GP0_AWLOCK; + wire [2:0]S_AXI_GP0_AWPROT; + wire [3:0]S_AXI_GP0_AWQOS; + wire S_AXI_GP0_AWREADY; + wire [2:0]S_AXI_GP0_AWSIZE; + wire S_AXI_GP0_AWVALID; + wire [5:0]S_AXI_GP0_BID; + wire S_AXI_GP0_BREADY; + wire [1:0]S_AXI_GP0_BRESP; + wire S_AXI_GP0_BVALID; + wire [31:0]S_AXI_GP0_RDATA; + wire [5:0]S_AXI_GP0_RID; + wire S_AXI_GP0_RLAST; + wire S_AXI_GP0_RREADY; + wire [1:0]S_AXI_GP0_RRESP; + wire S_AXI_GP0_RVALID; + wire [31:0]S_AXI_GP0_WDATA; + wire [5:0]S_AXI_GP0_WID; + wire S_AXI_GP0_WLAST; + wire S_AXI_GP0_WREADY; + wire [3:0]S_AXI_GP0_WSTRB; + wire S_AXI_GP0_WVALID; + wire S_AXI_GP1_ACLK; + wire [31:0]S_AXI_GP1_ARADDR; + wire [1:0]S_AXI_GP1_ARBURST; + wire [3:0]S_AXI_GP1_ARCACHE; + wire S_AXI_GP1_ARESETN; + wire [5:0]S_AXI_GP1_ARID; + wire [3:0]S_AXI_GP1_ARLEN; + wire [1:0]S_AXI_GP1_ARLOCK; + wire [2:0]S_AXI_GP1_ARPROT; + wire [3:0]S_AXI_GP1_ARQOS; + wire S_AXI_GP1_ARREADY; + wire [2:0]S_AXI_GP1_ARSIZE; + wire S_AXI_GP1_ARVALID; + wire [31:0]S_AXI_GP1_AWADDR; + wire [1:0]S_AXI_GP1_AWBURST; + wire [3:0]S_AXI_GP1_AWCACHE; + wire [5:0]S_AXI_GP1_AWID; + wire [3:0]S_AXI_GP1_AWLEN; + wire [1:0]S_AXI_GP1_AWLOCK; + wire [2:0]S_AXI_GP1_AWPROT; + wire [3:0]S_AXI_GP1_AWQOS; + wire S_AXI_GP1_AWREADY; + wire [2:0]S_AXI_GP1_AWSIZE; + wire S_AXI_GP1_AWVALID; + wire [5:0]S_AXI_GP1_BID; + wire S_AXI_GP1_BREADY; + wire [1:0]S_AXI_GP1_BRESP; + wire S_AXI_GP1_BVALID; + wire [31:0]S_AXI_GP1_RDATA; + wire [5:0]S_AXI_GP1_RID; + wire S_AXI_GP1_RLAST; + wire S_AXI_GP1_RREADY; + wire [1:0]S_AXI_GP1_RRESP; + wire S_AXI_GP1_RVALID; + wire [31:0]S_AXI_GP1_WDATA; + wire [5:0]S_AXI_GP1_WID; + wire S_AXI_GP1_WLAST; + wire S_AXI_GP1_WREADY; + wire [3:0]S_AXI_GP1_WSTRB; + wire S_AXI_GP1_WVALID; + wire S_AXI_HP0_ACLK; + wire [31:0]S_AXI_HP0_ARADDR; + wire [1:0]S_AXI_HP0_ARBURST; + wire [3:0]S_AXI_HP0_ARCACHE; + wire S_AXI_HP0_ARESETN; + wire [5:0]S_AXI_HP0_ARID; + wire [3:0]S_AXI_HP0_ARLEN; + wire [1:0]S_AXI_HP0_ARLOCK; + wire [2:0]S_AXI_HP0_ARPROT; + wire [3:0]S_AXI_HP0_ARQOS; + wire S_AXI_HP0_ARREADY; + wire [2:0]S_AXI_HP0_ARSIZE; + wire S_AXI_HP0_ARVALID; + wire [31:0]S_AXI_HP0_AWADDR; + wire [1:0]S_AXI_HP0_AWBURST; + wire [3:0]S_AXI_HP0_AWCACHE; + wire [5:0]S_AXI_HP0_AWID; + wire [3:0]S_AXI_HP0_AWLEN; + wire [1:0]S_AXI_HP0_AWLOCK; + wire [2:0]S_AXI_HP0_AWPROT; + wire [3:0]S_AXI_HP0_AWQOS; + wire S_AXI_HP0_AWREADY; + wire [2:0]S_AXI_HP0_AWSIZE; + wire S_AXI_HP0_AWVALID; + wire [5:0]S_AXI_HP0_BID; + wire S_AXI_HP0_BREADY; + wire [1:0]S_AXI_HP0_BRESP; + wire S_AXI_HP0_BVALID; + wire [2:0]S_AXI_HP0_RACOUNT; + wire [7:0]S_AXI_HP0_RCOUNT; + wire [63:0]S_AXI_HP0_RDATA; + wire S_AXI_HP0_RDISSUECAP1_EN; + wire [5:0]S_AXI_HP0_RID; + wire S_AXI_HP0_RLAST; + wire S_AXI_HP0_RREADY; + wire [1:0]S_AXI_HP0_RRESP; + wire S_AXI_HP0_RVALID; + wire [5:0]S_AXI_HP0_WACOUNT; + wire [7:0]S_AXI_HP0_WCOUNT; + wire [63:0]S_AXI_HP0_WDATA; + wire [5:0]S_AXI_HP0_WID; + wire S_AXI_HP0_WLAST; + wire S_AXI_HP0_WREADY; + wire S_AXI_HP0_WRISSUECAP1_EN; + wire [7:0]S_AXI_HP0_WSTRB; + wire S_AXI_HP0_WVALID; + wire S_AXI_HP1_ACLK; + wire [31:0]S_AXI_HP1_ARADDR; + wire [1:0]S_AXI_HP1_ARBURST; + wire [3:0]S_AXI_HP1_ARCACHE; + wire S_AXI_HP1_ARESETN; + wire [5:0]S_AXI_HP1_ARID; + wire [3:0]S_AXI_HP1_ARLEN; + wire [1:0]S_AXI_HP1_ARLOCK; + wire [2:0]S_AXI_HP1_ARPROT; + wire [3:0]S_AXI_HP1_ARQOS; + wire S_AXI_HP1_ARREADY; + wire [2:0]S_AXI_HP1_ARSIZE; + wire S_AXI_HP1_ARVALID; + wire [31:0]S_AXI_HP1_AWADDR; + wire [1:0]S_AXI_HP1_AWBURST; + wire [3:0]S_AXI_HP1_AWCACHE; + wire [5:0]S_AXI_HP1_AWID; + wire [3:0]S_AXI_HP1_AWLEN; + wire [1:0]S_AXI_HP1_AWLOCK; + wire [2:0]S_AXI_HP1_AWPROT; + wire [3:0]S_AXI_HP1_AWQOS; + wire S_AXI_HP1_AWREADY; + wire [2:0]S_AXI_HP1_AWSIZE; + wire S_AXI_HP1_AWVALID; + wire [5:0]S_AXI_HP1_BID; + wire S_AXI_HP1_BREADY; + wire [1:0]S_AXI_HP1_BRESP; + wire S_AXI_HP1_BVALID; + wire [2:0]S_AXI_HP1_RACOUNT; + wire [7:0]S_AXI_HP1_RCOUNT; + wire [63:0]S_AXI_HP1_RDATA; + wire S_AXI_HP1_RDISSUECAP1_EN; + wire [5:0]S_AXI_HP1_RID; + wire S_AXI_HP1_RLAST; + wire S_AXI_HP1_RREADY; + wire [1:0]S_AXI_HP1_RRESP; + wire S_AXI_HP1_RVALID; + wire [5:0]S_AXI_HP1_WACOUNT; + wire [7:0]S_AXI_HP1_WCOUNT; + wire [63:0]S_AXI_HP1_WDATA; + wire [5:0]S_AXI_HP1_WID; + wire S_AXI_HP1_WLAST; + wire S_AXI_HP1_WREADY; + wire S_AXI_HP1_WRISSUECAP1_EN; + wire [7:0]S_AXI_HP1_WSTRB; + wire S_AXI_HP1_WVALID; + wire S_AXI_HP2_ACLK; + wire [31:0]S_AXI_HP2_ARADDR; + wire [1:0]S_AXI_HP2_ARBURST; + wire [3:0]S_AXI_HP2_ARCACHE; + wire S_AXI_HP2_ARESETN; + wire [5:0]S_AXI_HP2_ARID; + wire [3:0]S_AXI_HP2_ARLEN; + wire [1:0]S_AXI_HP2_ARLOCK; + wire [2:0]S_AXI_HP2_ARPROT; + wire [3:0]S_AXI_HP2_ARQOS; + wire S_AXI_HP2_ARREADY; + wire [2:0]S_AXI_HP2_ARSIZE; + wire S_AXI_HP2_ARVALID; + wire [31:0]S_AXI_HP2_AWADDR; + wire [1:0]S_AXI_HP2_AWBURST; + wire [3:0]S_AXI_HP2_AWCACHE; + wire [5:0]S_AXI_HP2_AWID; + wire [3:0]S_AXI_HP2_AWLEN; + wire [1:0]S_AXI_HP2_AWLOCK; + wire [2:0]S_AXI_HP2_AWPROT; + wire [3:0]S_AXI_HP2_AWQOS; + wire S_AXI_HP2_AWREADY; + wire [2:0]S_AXI_HP2_AWSIZE; + wire S_AXI_HP2_AWVALID; + wire [5:0]S_AXI_HP2_BID; + wire S_AXI_HP2_BREADY; + wire [1:0]S_AXI_HP2_BRESP; + wire S_AXI_HP2_BVALID; + wire [2:0]S_AXI_HP2_RACOUNT; + wire [7:0]S_AXI_HP2_RCOUNT; + wire [63:0]S_AXI_HP2_RDATA; + wire S_AXI_HP2_RDISSUECAP1_EN; + wire [5:0]S_AXI_HP2_RID; + wire S_AXI_HP2_RLAST; + wire S_AXI_HP2_RREADY; + wire [1:0]S_AXI_HP2_RRESP; + wire S_AXI_HP2_RVALID; + wire [5:0]S_AXI_HP2_WACOUNT; + wire [7:0]S_AXI_HP2_WCOUNT; + wire [63:0]S_AXI_HP2_WDATA; + wire [5:0]S_AXI_HP2_WID; + wire S_AXI_HP2_WLAST; + wire S_AXI_HP2_WREADY; + wire S_AXI_HP2_WRISSUECAP1_EN; + wire [7:0]S_AXI_HP2_WSTRB; + wire S_AXI_HP2_WVALID; + wire S_AXI_HP3_ACLK; + wire [31:0]S_AXI_HP3_ARADDR; + wire [1:0]S_AXI_HP3_ARBURST; + wire [3:0]S_AXI_HP3_ARCACHE; + wire S_AXI_HP3_ARESETN; + wire [5:0]S_AXI_HP3_ARID; + wire [3:0]S_AXI_HP3_ARLEN; + wire [1:0]S_AXI_HP3_ARLOCK; + wire [2:0]S_AXI_HP3_ARPROT; + wire [3:0]S_AXI_HP3_ARQOS; + wire S_AXI_HP3_ARREADY; + wire [2:0]S_AXI_HP3_ARSIZE; + wire S_AXI_HP3_ARVALID; + wire [31:0]S_AXI_HP3_AWADDR; + wire [1:0]S_AXI_HP3_AWBURST; + wire [3:0]S_AXI_HP3_AWCACHE; + wire [5:0]S_AXI_HP3_AWID; + wire [3:0]S_AXI_HP3_AWLEN; + wire [1:0]S_AXI_HP3_AWLOCK; + wire [2:0]S_AXI_HP3_AWPROT; + wire [3:0]S_AXI_HP3_AWQOS; + wire S_AXI_HP3_AWREADY; + wire [2:0]S_AXI_HP3_AWSIZE; + wire S_AXI_HP3_AWVALID; + wire [5:0]S_AXI_HP3_BID; + wire S_AXI_HP3_BREADY; + wire [1:0]S_AXI_HP3_BRESP; + wire S_AXI_HP3_BVALID; + wire [2:0]S_AXI_HP3_RACOUNT; + wire [7:0]S_AXI_HP3_RCOUNT; + wire [63:0]S_AXI_HP3_RDATA; + wire S_AXI_HP3_RDISSUECAP1_EN; + wire [5:0]S_AXI_HP3_RID; + wire S_AXI_HP3_RLAST; + wire S_AXI_HP3_RREADY; + wire [1:0]S_AXI_HP3_RRESP; + wire S_AXI_HP3_RVALID; + wire [5:0]S_AXI_HP3_WACOUNT; + wire [7:0]S_AXI_HP3_WCOUNT; + wire [63:0]S_AXI_HP3_WDATA; + wire [5:0]S_AXI_HP3_WID; + wire S_AXI_HP3_WLAST; + wire S_AXI_HP3_WREADY; + wire S_AXI_HP3_WRISSUECAP1_EN; + wire [7:0]S_AXI_HP3_WSTRB; + wire S_AXI_HP3_WVALID; + wire TRACE_CLK; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[0] ; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[1] ; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[2] ; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[3] ; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[4] ; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[5] ; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[6] ; + (* RTL_KEEP = "true" *) wire \TRACE_CTL_PIPE[7] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[0] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[1] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[2] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[3] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[4] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[5] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[6] ; + (* RTL_KEEP = "true" *) wire [1:0]\TRACE_DATA_PIPE[7] ; + wire TTC0_CLK0_IN; + wire TTC0_CLK1_IN; + wire TTC0_CLK2_IN; + wire TTC0_WAVE0_OUT; + wire TTC0_WAVE1_OUT; + wire TTC0_WAVE2_OUT; + wire TTC1_CLK0_IN; + wire TTC1_CLK1_IN; + wire TTC1_CLK2_IN; + wire TTC1_WAVE0_OUT; + wire TTC1_WAVE1_OUT; + wire TTC1_WAVE2_OUT; + wire UART0_CTSN; + wire UART0_DCDN; + wire UART0_DSRN; + wire UART0_DTRN; + wire UART0_RIN; + wire UART0_RTSN; + wire UART0_RX; + wire UART0_TX; + wire UART1_CTSN; + wire UART1_DCDN; + wire UART1_DSRN; + wire UART1_DTRN; + wire UART1_RIN; + wire UART1_RTSN; + wire UART1_RX; + wire UART1_TX; + wire [1:0]USB0_PORT_INDCTL; + wire USB0_VBUS_PWRFAULT; + wire USB0_VBUS_PWRSELECT; + wire [1:0]USB1_PORT_INDCTL; + wire USB1_VBUS_PWRFAULT; + wire USB1_VBUS_PWRSELECT; + wire WDT_CLK_IN; + wire WDT_RST_OUT; + wire [14:0]buffered_DDR_Addr; + wire [2:0]buffered_DDR_BankAddr; + wire buffered_DDR_CAS_n; + wire buffered_DDR_CKE; + wire buffered_DDR_CS_n; + wire buffered_DDR_Clk; + wire buffered_DDR_Clk_n; + wire [3:0]buffered_DDR_DM; + wire [31:0]buffered_DDR_DQ; + wire [3:0]buffered_DDR_DQS; + wire [3:0]buffered_DDR_DQS_n; + wire buffered_DDR_DRSTB; + wire buffered_DDR_ODT; + wire buffered_DDR_RAS_n; + wire buffered_DDR_VRN; + wire buffered_DDR_VRP; + wire buffered_DDR_WEB; + wire [53:0]buffered_MIO; + wire buffered_PS_CLK; + wire buffered_PS_PORB; + wire buffered_PS_SRSTB; + wire [63:0]gpio_out_t_n; + wire NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED; + wire NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED; + wire NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED; + wire NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED; + wire NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED; + wire NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED; + wire NLW_PS7_i_EMIOTRACECTL_UNCONNECTED; + wire [7:0]NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED; + wire [7:0]NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED; + wire [31:0]NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED; + wire [1:1]NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED; + wire [1:1]NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED; + wire [1:1]NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED; + wire [1:1]NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED; + + assign ENET0_GMII_TXD[7] = \ ; + assign ENET0_GMII_TXD[6] = \ ; + assign ENET0_GMII_TXD[5] = \ ; + assign ENET0_GMII_TXD[4] = \ ; + assign ENET0_GMII_TXD[3] = \ ; + assign ENET0_GMII_TXD[2] = \ ; + assign ENET0_GMII_TXD[1] = \ ; + assign ENET0_GMII_TXD[0] = \ ; + assign ENET0_GMII_TX_EN = \ ; + assign ENET0_GMII_TX_ER = \ ; + assign ENET1_GMII_TXD[7] = \ ; + assign ENET1_GMII_TXD[6] = \ ; + assign ENET1_GMII_TXD[5] = \ ; + assign ENET1_GMII_TXD[4] = \ ; + assign ENET1_GMII_TXD[3] = \ ; + assign ENET1_GMII_TXD[2] = \ ; + assign ENET1_GMII_TXD[1] = \ ; + assign ENET1_GMII_TXD[0] = \ ; + assign ENET1_GMII_TX_EN = \ ; + assign ENET1_GMII_TX_ER = \ ; + assign M_AXI_GP0_ARCACHE[3:2] = \^M_AXI_GP0_ARCACHE [3:2]; + assign M_AXI_GP0_ARCACHE[1] = \ ; + assign M_AXI_GP0_ARCACHE[0] = \^M_AXI_GP0_ARCACHE [0]; + assign M_AXI_GP0_ARSIZE[2] = \ ; + assign M_AXI_GP0_ARSIZE[1:0] = \^M_AXI_GP0_ARSIZE [1:0]; + assign M_AXI_GP0_AWCACHE[3:2] = \^M_AXI_GP0_AWCACHE [3:2]; + assign M_AXI_GP0_AWCACHE[1] = \ ; + assign M_AXI_GP0_AWCACHE[0] = \^M_AXI_GP0_AWCACHE [0]; + assign M_AXI_GP0_AWSIZE[2] = \ ; + assign M_AXI_GP0_AWSIZE[1:0] = \^M_AXI_GP0_AWSIZE [1:0]; + assign M_AXI_GP1_ARCACHE[3:2] = \^M_AXI_GP1_ARCACHE [3:2]; + assign M_AXI_GP1_ARCACHE[1] = \ ; + assign M_AXI_GP1_ARCACHE[0] = \^M_AXI_GP1_ARCACHE [0]; + assign M_AXI_GP1_ARSIZE[2] = \ ; + assign M_AXI_GP1_ARSIZE[1:0] = \^M_AXI_GP1_ARSIZE [1:0]; + assign M_AXI_GP1_AWCACHE[3:2] = \^M_AXI_GP1_AWCACHE [3:2]; + assign M_AXI_GP1_AWCACHE[1] = \ ; + assign M_AXI_GP1_AWCACHE[0] = \^M_AXI_GP1_AWCACHE [0]; + assign M_AXI_GP1_AWSIZE[2] = \ ; + assign M_AXI_GP1_AWSIZE[1:0] = \^M_AXI_GP1_AWSIZE [1:0]; + assign PJTAG_TDO = \ ; + assign TRACE_CLK_OUT = \ ; + assign TRACE_CTL = \TRACE_CTL_PIPE[0] ; + assign TRACE_DATA[1:0] = \TRACE_DATA_PIPE[0] ; + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_CAS_n_BIBUF + (.IO(buffered_DDR_CAS_n), + .PAD(DDR_CAS_n)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_CKE_BIBUF + (.IO(buffered_DDR_CKE), + .PAD(DDR_CKE)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_CS_n_BIBUF + (.IO(buffered_DDR_CS_n), + .PAD(DDR_CS_n)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_Clk_BIBUF + (.IO(buffered_DDR_Clk), + .PAD(DDR_Clk)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_Clk_n_BIBUF + (.IO(buffered_DDR_Clk_n), + .PAD(DDR_Clk_n)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_DRSTB_BIBUF + (.IO(buffered_DDR_DRSTB), + .PAD(DDR_DRSTB)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_ODT_BIBUF + (.IO(buffered_DDR_ODT), + .PAD(DDR_ODT)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_RAS_n_BIBUF + (.IO(buffered_DDR_RAS_n), + .PAD(DDR_RAS_n)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_VRN_BIBUF + (.IO(buffered_DDR_VRN), + .PAD(DDR_VRN)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_VRP_BIBUF + (.IO(buffered_DDR_VRP), + .PAD(DDR_VRP)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF DDR_WEB_BIBUF + (.IO(buffered_DDR_WEB), + .PAD(DDR_WEB)); + LUT1 #( + .INIT(2'h1)) + ENET0_MDIO_T_INST_0 + (.I0(ENET0_MDIO_T_n), + .O(ENET0_MDIO_T)); + LUT1 #( + .INIT(2'h1)) + ENET1_MDIO_T_INST_0 + (.I0(ENET1_MDIO_T_n), + .O(ENET1_MDIO_T)); + GND GND + (.G(\ )); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[0]_INST_0 + (.I0(gpio_out_t_n[0]), + .O(GPIO_T[0])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[10]_INST_0 + (.I0(gpio_out_t_n[10]), + .O(GPIO_T[10])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[11]_INST_0 + (.I0(gpio_out_t_n[11]), + .O(GPIO_T[11])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[12]_INST_0 + (.I0(gpio_out_t_n[12]), + .O(GPIO_T[12])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[13]_INST_0 + (.I0(gpio_out_t_n[13]), + .O(GPIO_T[13])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[14]_INST_0 + (.I0(gpio_out_t_n[14]), + .O(GPIO_T[14])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[15]_INST_0 + (.I0(gpio_out_t_n[15]), + .O(GPIO_T[15])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[16]_INST_0 + (.I0(gpio_out_t_n[16]), + .O(GPIO_T[16])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[17]_INST_0 + (.I0(gpio_out_t_n[17]), + .O(GPIO_T[17])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[18]_INST_0 + (.I0(gpio_out_t_n[18]), + .O(GPIO_T[18])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[19]_INST_0 + (.I0(gpio_out_t_n[19]), + .O(GPIO_T[19])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[1]_INST_0 + (.I0(gpio_out_t_n[1]), + .O(GPIO_T[1])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[20]_INST_0 + (.I0(gpio_out_t_n[20]), + .O(GPIO_T[20])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[21]_INST_0 + (.I0(gpio_out_t_n[21]), + .O(GPIO_T[21])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[22]_INST_0 + (.I0(gpio_out_t_n[22]), + .O(GPIO_T[22])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[23]_INST_0 + (.I0(gpio_out_t_n[23]), + .O(GPIO_T[23])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[24]_INST_0 + (.I0(gpio_out_t_n[24]), + .O(GPIO_T[24])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[25]_INST_0 + (.I0(gpio_out_t_n[25]), + .O(GPIO_T[25])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[26]_INST_0 + (.I0(gpio_out_t_n[26]), + .O(GPIO_T[26])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[27]_INST_0 + (.I0(gpio_out_t_n[27]), + .O(GPIO_T[27])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[28]_INST_0 + (.I0(gpio_out_t_n[28]), + .O(GPIO_T[28])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[29]_INST_0 + (.I0(gpio_out_t_n[29]), + .O(GPIO_T[29])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[2]_INST_0 + (.I0(gpio_out_t_n[2]), + .O(GPIO_T[2])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[30]_INST_0 + (.I0(gpio_out_t_n[30]), + .O(GPIO_T[30])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[31]_INST_0 + (.I0(gpio_out_t_n[31]), + .O(GPIO_T[31])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[32]_INST_0 + (.I0(gpio_out_t_n[32]), + .O(GPIO_T[32])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[33]_INST_0 + (.I0(gpio_out_t_n[33]), + .O(GPIO_T[33])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[34]_INST_0 + (.I0(gpio_out_t_n[34]), + .O(GPIO_T[34])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[35]_INST_0 + (.I0(gpio_out_t_n[35]), + .O(GPIO_T[35])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[36]_INST_0 + (.I0(gpio_out_t_n[36]), + .O(GPIO_T[36])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[37]_INST_0 + (.I0(gpio_out_t_n[37]), + .O(GPIO_T[37])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[38]_INST_0 + (.I0(gpio_out_t_n[38]), + .O(GPIO_T[38])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[39]_INST_0 + (.I0(gpio_out_t_n[39]), + .O(GPIO_T[39])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[3]_INST_0 + (.I0(gpio_out_t_n[3]), + .O(GPIO_T[3])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[40]_INST_0 + (.I0(gpio_out_t_n[40]), + .O(GPIO_T[40])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[41]_INST_0 + (.I0(gpio_out_t_n[41]), + .O(GPIO_T[41])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[42]_INST_0 + (.I0(gpio_out_t_n[42]), + .O(GPIO_T[42])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[43]_INST_0 + (.I0(gpio_out_t_n[43]), + .O(GPIO_T[43])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[44]_INST_0 + (.I0(gpio_out_t_n[44]), + .O(GPIO_T[44])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[45]_INST_0 + (.I0(gpio_out_t_n[45]), + .O(GPIO_T[45])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[46]_INST_0 + (.I0(gpio_out_t_n[46]), + .O(GPIO_T[46])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[47]_INST_0 + (.I0(gpio_out_t_n[47]), + .O(GPIO_T[47])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[48]_INST_0 + (.I0(gpio_out_t_n[48]), + .O(GPIO_T[48])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[49]_INST_0 + (.I0(gpio_out_t_n[49]), + .O(GPIO_T[49])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[4]_INST_0 + (.I0(gpio_out_t_n[4]), + .O(GPIO_T[4])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[50]_INST_0 + (.I0(gpio_out_t_n[50]), + .O(GPIO_T[50])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[51]_INST_0 + (.I0(gpio_out_t_n[51]), + .O(GPIO_T[51])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[52]_INST_0 + (.I0(gpio_out_t_n[52]), + .O(GPIO_T[52])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[53]_INST_0 + (.I0(gpio_out_t_n[53]), + .O(GPIO_T[53])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[54]_INST_0 + (.I0(gpio_out_t_n[54]), + .O(GPIO_T[54])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[55]_INST_0 + (.I0(gpio_out_t_n[55]), + .O(GPIO_T[55])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[56]_INST_0 + (.I0(gpio_out_t_n[56]), + .O(GPIO_T[56])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[57]_INST_0 + (.I0(gpio_out_t_n[57]), + .O(GPIO_T[57])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[58]_INST_0 + (.I0(gpio_out_t_n[58]), + .O(GPIO_T[58])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[59]_INST_0 + (.I0(gpio_out_t_n[59]), + .O(GPIO_T[59])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[5]_INST_0 + (.I0(gpio_out_t_n[5]), + .O(GPIO_T[5])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[60]_INST_0 + (.I0(gpio_out_t_n[60]), + .O(GPIO_T[60])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[61]_INST_0 + (.I0(gpio_out_t_n[61]), + .O(GPIO_T[61])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[62]_INST_0 + (.I0(gpio_out_t_n[62]), + .O(GPIO_T[62])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[63]_INST_0 + (.I0(gpio_out_t_n[63]), + .O(GPIO_T[63])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[6]_INST_0 + (.I0(gpio_out_t_n[6]), + .O(GPIO_T[6])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[7]_INST_0 + (.I0(gpio_out_t_n[7]), + .O(GPIO_T[7])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[8]_INST_0 + (.I0(gpio_out_t_n[8]), + .O(GPIO_T[8])); + LUT1 #( + .INIT(2'h1)) + \GPIO_T[9]_INST_0 + (.I0(gpio_out_t_n[9]), + .O(GPIO_T[9])); + LUT1 #( + .INIT(2'h1)) + I2C0_SCL_T_INST_0 + (.I0(I2C0_SCL_T_n), + .O(I2C0_SCL_T)); + LUT1 #( + .INIT(2'h1)) + I2C0_SDA_T_INST_0 + (.I0(I2C0_SDA_T_n), + .O(I2C0_SDA_T)); + LUT1 #( + .INIT(2'h1)) + I2C1_SCL_T_INST_0 + (.I0(I2C1_SCL_T_n), + .O(I2C1_SCL_T)); + LUT1 #( + .INIT(2'h1)) + I2C1_SDA_T_INST_0 + (.I0(I2C1_SDA_T_n), + .O(I2C1_SDA_T)); + (* BOX_TYPE = "PRIMITIVE" *) + PS7 PS7_i + (.DDRA(buffered_DDR_Addr), + .DDRARB(DDR_ARB), + .DDRBA(buffered_DDR_BankAddr), + .DDRCASB(buffered_DDR_CAS_n), + .DDRCKE(buffered_DDR_CKE), + .DDRCKN(buffered_DDR_Clk_n), + .DDRCKP(buffered_DDR_Clk), + .DDRCSB(buffered_DDR_CS_n), + .DDRDM(buffered_DDR_DM), + .DDRDQ(buffered_DDR_DQ), + .DDRDQSN(buffered_DDR_DQS_n), + .DDRDQSP(buffered_DDR_DQS), + .DDRDRSTB(buffered_DDR_DRSTB), + .DDRODT(buffered_DDR_ODT), + .DDRRASB(buffered_DDR_RAS_n), + .DDRVRN(buffered_DDR_VRN), + .DDRVRP(buffered_DDR_VRP), + .DDRWEB(buffered_DDR_WEB), + .DMA0ACLK(DMA0_ACLK), + .DMA0DAREADY(DMA0_DAREADY), + .DMA0DATYPE(DMA0_DATYPE), + .DMA0DAVALID(DMA0_DAVALID), + .DMA0DRLAST(DMA0_DRLAST), + .DMA0DRREADY(DMA0_DRREADY), + .DMA0DRTYPE(DMA0_DRTYPE), + .DMA0DRVALID(DMA0_DRVALID), + .DMA0RSTN(DMA0_RSTN), + .DMA1ACLK(DMA1_ACLK), + .DMA1DAREADY(DMA1_DAREADY), + .DMA1DATYPE(DMA1_DATYPE), + .DMA1DAVALID(DMA1_DAVALID), + .DMA1DRLAST(DMA1_DRLAST), + .DMA1DRREADY(DMA1_DRREADY), + .DMA1DRTYPE(DMA1_DRTYPE), + .DMA1DRVALID(DMA1_DRVALID), + .DMA1RSTN(DMA1_RSTN), + .DMA2ACLK(DMA2_ACLK), + .DMA2DAREADY(DMA2_DAREADY), + .DMA2DATYPE(DMA2_DATYPE), + .DMA2DAVALID(DMA2_DAVALID), + .DMA2DRLAST(DMA2_DRLAST), + .DMA2DRREADY(DMA2_DRREADY), + .DMA2DRTYPE(DMA2_DRTYPE), + .DMA2DRVALID(DMA2_DRVALID), + .DMA2RSTN(DMA2_RSTN), + .DMA3ACLK(DMA3_ACLK), + .DMA3DAREADY(DMA3_DAREADY), + .DMA3DATYPE(DMA3_DATYPE), + .DMA3DAVALID(DMA3_DAVALID), + .DMA3DRLAST(DMA3_DRLAST), + .DMA3DRREADY(DMA3_DRREADY), + .DMA3DRTYPE(DMA3_DRTYPE), + .DMA3DRVALID(DMA3_DRVALID), + .DMA3RSTN(DMA3_RSTN), + .EMIOCAN0PHYRX(CAN0_PHY_RX), + .EMIOCAN0PHYTX(CAN0_PHY_TX), + .EMIOCAN1PHYRX(CAN1_PHY_RX), + .EMIOCAN1PHYTX(CAN1_PHY_TX), + .EMIOENET0EXTINTIN(ENET0_EXT_INTIN), + .EMIOENET0GMIICOL(1'b0), + .EMIOENET0GMIICRS(1'b0), + .EMIOENET0GMIIRXCLK(ENET0_GMII_RX_CLK), + .EMIOENET0GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .EMIOENET0GMIIRXDV(1'b0), + .EMIOENET0GMIIRXER(1'b0), + .EMIOENET0GMIITXCLK(ENET0_GMII_TX_CLK), + .EMIOENET0GMIITXD(NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED[7:0]), + .EMIOENET0GMIITXEN(NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED), + .EMIOENET0GMIITXER(NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED), + .EMIOENET0MDIOI(ENET0_MDIO_I), + .EMIOENET0MDIOMDC(ENET0_MDIO_MDC), + .EMIOENET0MDIOO(ENET0_MDIO_O), + .EMIOENET0MDIOTN(ENET0_MDIO_T_n), + .EMIOENET0PTPDELAYREQRX(ENET0_PTP_DELAY_REQ_RX), + .EMIOENET0PTPDELAYREQTX(ENET0_PTP_DELAY_REQ_TX), + .EMIOENET0PTPPDELAYREQRX(ENET0_PTP_PDELAY_REQ_RX), + .EMIOENET0PTPPDELAYREQTX(ENET0_PTP_PDELAY_REQ_TX), + .EMIOENET0PTPPDELAYRESPRX(ENET0_PTP_PDELAY_RESP_RX), + .EMIOENET0PTPPDELAYRESPTX(ENET0_PTP_PDELAY_RESP_TX), + .EMIOENET0PTPSYNCFRAMERX(ENET0_PTP_SYNC_FRAME_RX), + .EMIOENET0PTPSYNCFRAMETX(ENET0_PTP_SYNC_FRAME_TX), + .EMIOENET0SOFRX(ENET0_SOF_RX), + .EMIOENET0SOFTX(ENET0_SOF_TX), + .EMIOENET1EXTINTIN(ENET1_EXT_INTIN), + .EMIOENET1GMIICOL(1'b0), + .EMIOENET1GMIICRS(1'b0), + .EMIOENET1GMIIRXCLK(ENET1_GMII_RX_CLK), + .EMIOENET1GMIIRXD({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .EMIOENET1GMIIRXDV(1'b0), + .EMIOENET1GMIIRXER(1'b0), + .EMIOENET1GMIITXCLK(ENET1_GMII_TX_CLK), + .EMIOENET1GMIITXD(NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED[7:0]), + .EMIOENET1GMIITXEN(NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED), + .EMIOENET1GMIITXER(NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED), + .EMIOENET1MDIOI(ENET1_MDIO_I), + .EMIOENET1MDIOMDC(ENET1_MDIO_MDC), + .EMIOENET1MDIOO(ENET1_MDIO_O), + .EMIOENET1MDIOTN(ENET1_MDIO_T_n), + .EMIOENET1PTPDELAYREQRX(ENET1_PTP_DELAY_REQ_RX), + .EMIOENET1PTPDELAYREQTX(ENET1_PTP_DELAY_REQ_TX), + .EMIOENET1PTPPDELAYREQRX(ENET1_PTP_PDELAY_REQ_RX), + .EMIOENET1PTPPDELAYREQTX(ENET1_PTP_PDELAY_REQ_TX), + .EMIOENET1PTPPDELAYRESPRX(ENET1_PTP_PDELAY_RESP_RX), + .EMIOENET1PTPPDELAYRESPTX(ENET1_PTP_PDELAY_RESP_TX), + .EMIOENET1PTPSYNCFRAMERX(ENET1_PTP_SYNC_FRAME_RX), + .EMIOENET1PTPSYNCFRAMETX(ENET1_PTP_SYNC_FRAME_TX), + .EMIOENET1SOFRX(ENET1_SOF_RX), + .EMIOENET1SOFTX(ENET1_SOF_TX), + .EMIOGPIOI(GPIO_I), + .EMIOGPIOO(GPIO_O), + .EMIOGPIOTN(gpio_out_t_n), + .EMIOI2C0SCLI(I2C0_SCL_I), + .EMIOI2C0SCLO(I2C0_SCL_O), + .EMIOI2C0SCLTN(I2C0_SCL_T_n), + .EMIOI2C0SDAI(I2C0_SDA_I), + .EMIOI2C0SDAO(I2C0_SDA_O), + .EMIOI2C0SDATN(I2C0_SDA_T_n), + .EMIOI2C1SCLI(I2C1_SCL_I), + .EMIOI2C1SCLO(I2C1_SCL_O), + .EMIOI2C1SCLTN(I2C1_SCL_T_n), + .EMIOI2C1SDAI(I2C1_SDA_I), + .EMIOI2C1SDAO(I2C1_SDA_O), + .EMIOI2C1SDATN(I2C1_SDA_T_n), + .EMIOPJTAGTCK(PJTAG_TCK), + .EMIOPJTAGTDI(PJTAG_TDI), + .EMIOPJTAGTDO(NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED), + .EMIOPJTAGTDTN(NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED), + .EMIOPJTAGTMS(PJTAG_TMS), + .EMIOSDIO0BUSPOW(SDIO0_BUSPOW), + .EMIOSDIO0BUSVOLT(SDIO0_BUSVOLT), + .EMIOSDIO0CDN(SDIO0_CDN), + .EMIOSDIO0CLK(SDIO0_CLK), + .EMIOSDIO0CLKFB(SDIO0_CLK_FB), + .EMIOSDIO0CMDI(SDIO0_CMD_I), + .EMIOSDIO0CMDO(SDIO0_CMD_O), + .EMIOSDIO0CMDTN(SDIO0_CMD_T_n), + .EMIOSDIO0DATAI(SDIO0_DATA_I), + .EMIOSDIO0DATAO(SDIO0_DATA_O), + .EMIOSDIO0DATATN(SDIO0_DATA_T_n), + .EMIOSDIO0LED(SDIO0_LED), + .EMIOSDIO0WP(SDIO0_WP), + .EMIOSDIO1BUSPOW(SDIO1_BUSPOW), + .EMIOSDIO1BUSVOLT(SDIO1_BUSVOLT), + .EMIOSDIO1CDN(SDIO1_CDN), + .EMIOSDIO1CLK(SDIO1_CLK), + .EMIOSDIO1CLKFB(SDIO1_CLK_FB), + .EMIOSDIO1CMDI(SDIO1_CMD_I), + .EMIOSDIO1CMDO(SDIO1_CMD_O), + .EMIOSDIO1CMDTN(SDIO1_CMD_T_n), + .EMIOSDIO1DATAI(SDIO1_DATA_I), + .EMIOSDIO1DATAO(SDIO1_DATA_O), + .EMIOSDIO1DATATN(SDIO1_DATA_T_n), + .EMIOSDIO1LED(SDIO1_LED), + .EMIOSDIO1WP(SDIO1_WP), + .EMIOSPI0MI(SPI0_MISO_I), + .EMIOSPI0MO(SPI0_MOSI_O), + .EMIOSPI0MOTN(SPI0_MOSI_T_n), + .EMIOSPI0SCLKI(SPI0_SCLK_I), + .EMIOSPI0SCLKO(SPI0_SCLK_O), + .EMIOSPI0SCLKTN(SPI0_SCLK_T_n), + .EMIOSPI0SI(SPI0_MOSI_I), + .EMIOSPI0SO(SPI0_MISO_O), + .EMIOSPI0SSIN(SPI0_SS_I), + .EMIOSPI0SSNTN(SPI0_SS_T_n), + .EMIOSPI0SSON({SPI0_SS2_O,SPI0_SS1_O,SPI0_SS_O}), + .EMIOSPI0STN(SPI0_MISO_T_n), + .EMIOSPI1MI(SPI1_MISO_I), + .EMIOSPI1MO(SPI1_MOSI_O), + .EMIOSPI1MOTN(SPI1_MOSI_T_n), + .EMIOSPI1SCLKI(SPI1_SCLK_I), + .EMIOSPI1SCLKO(SPI1_SCLK_O), + .EMIOSPI1SCLKTN(SPI1_SCLK_T_n), + .EMIOSPI1SI(SPI1_MOSI_I), + .EMIOSPI1SO(SPI1_MISO_O), + .EMIOSPI1SSIN(SPI1_SS_I), + .EMIOSPI1SSNTN(SPI1_SS_T_n), + .EMIOSPI1SSON({SPI1_SS2_O,SPI1_SS1_O,SPI1_SS_O}), + .EMIOSPI1STN(SPI1_MISO_T_n), + .EMIOSRAMINTIN(SRAM_INTIN), + .EMIOTRACECLK(TRACE_CLK), + .EMIOTRACECTL(NLW_PS7_i_EMIOTRACECTL_UNCONNECTED), + .EMIOTRACEDATA(NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED[31:0]), + .EMIOTTC0CLKI({TTC0_CLK2_IN,TTC0_CLK1_IN,TTC0_CLK0_IN}), + .EMIOTTC0WAVEO({TTC0_WAVE2_OUT,TTC0_WAVE1_OUT,TTC0_WAVE0_OUT}), + .EMIOTTC1CLKI({TTC1_CLK2_IN,TTC1_CLK1_IN,TTC1_CLK0_IN}), + .EMIOTTC1WAVEO({TTC1_WAVE2_OUT,TTC1_WAVE1_OUT,TTC1_WAVE0_OUT}), + .EMIOUART0CTSN(UART0_CTSN), + .EMIOUART0DCDN(UART0_DCDN), + .EMIOUART0DSRN(UART0_DSRN), + .EMIOUART0DTRN(UART0_DTRN), + .EMIOUART0RIN(UART0_RIN), + .EMIOUART0RTSN(UART0_RTSN), + .EMIOUART0RX(UART0_RX), + .EMIOUART0TX(UART0_TX), + .EMIOUART1CTSN(UART1_CTSN), + .EMIOUART1DCDN(UART1_DCDN), + .EMIOUART1DSRN(UART1_DSRN), + .EMIOUART1DTRN(UART1_DTRN), + .EMIOUART1RIN(UART1_RIN), + .EMIOUART1RTSN(UART1_RTSN), + .EMIOUART1RX(UART1_RX), + .EMIOUART1TX(UART1_TX), + .EMIOUSB0PORTINDCTL(USB0_PORT_INDCTL), + .EMIOUSB0VBUSPWRFAULT(USB0_VBUS_PWRFAULT), + .EMIOUSB0VBUSPWRSELECT(USB0_VBUS_PWRSELECT), + .EMIOUSB1PORTINDCTL(USB1_PORT_INDCTL), + .EMIOUSB1VBUSPWRFAULT(USB1_VBUS_PWRFAULT), + .EMIOUSB1VBUSPWRSELECT(USB1_VBUS_PWRSELECT), + .EMIOWDTCLKI(WDT_CLK_IN), + .EMIOWDTRSTO(WDT_RST_OUT), + .EVENTEVENTI(EVENT_EVENTI), + .EVENTEVENTO(EVENT_EVENTO), + .EVENTSTANDBYWFE(EVENT_STANDBYWFE), + .EVENTSTANDBYWFI(EVENT_STANDBYWFI), + .FCLKCLK({FCLK_CLK3,FCLK_CLK2,FCLK_CLK1,FCLK_CLK_unbuffered}), + .FCLKCLKTRIGN({1'b0,1'b0,1'b0,1'b0}), + .FCLKRESETN({FCLK_RESET3_N,FCLK_RESET2_N,FCLK_RESET1_N,FCLK_RESET0_N}), + .FPGAIDLEN(FPGA_IDLE_N), + .FTMDTRACEINATID({1'b0,1'b0,1'b0,1'b0}), + .FTMDTRACEINCLOCK(FTMD_TRACEIN_CLK), + .FTMDTRACEINDATA({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .FTMDTRACEINVALID(1'b0), + .FTMTF2PDEBUG(FTMT_F2P_DEBUG), + .FTMTF2PTRIG({FTMT_F2P_TRIG_3,FTMT_F2P_TRIG_2,FTMT_F2P_TRIG_1,FTMT_F2P_TRIG_0}), + .FTMTF2PTRIGACK({FTMT_F2P_TRIGACK_3,FTMT_F2P_TRIGACK_2,FTMT_F2P_TRIGACK_1,FTMT_F2P_TRIGACK_0}), + .FTMTP2FDEBUG(FTMT_P2F_DEBUG), + .FTMTP2FTRIG({FTMT_P2F_TRIG_3,FTMT_P2F_TRIG_2,FTMT_P2F_TRIG_1,FTMT_P2F_TRIG_0}), + .FTMTP2FTRIGACK({FTMT_P2F_TRIGACK_3,FTMT_P2F_TRIGACK_2,FTMT_P2F_TRIGACK_1,FTMT_P2F_TRIGACK_0}), + .IRQF2P({Core1_nFIQ,Core0_nFIQ,Core1_nIRQ,Core0_nIRQ,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,IRQ_F2P}), + .IRQP2F({IRQ_P2F_DMAC_ABORT,IRQ_P2F_DMAC7,IRQ_P2F_DMAC6,IRQ_P2F_DMAC5,IRQ_P2F_DMAC4,IRQ_P2F_DMAC3,IRQ_P2F_DMAC2,IRQ_P2F_DMAC1,IRQ_P2F_DMAC0,IRQ_P2F_SMC,IRQ_P2F_QSPI,IRQ_P2F_CTI,IRQ_P2F_GPIO,IRQ_P2F_USB0,IRQ_P2F_ENET0,IRQ_P2F_ENET_WAKE0,IRQ_P2F_SDIO0,IRQ_P2F_I2C0,IRQ_P2F_SPI0,IRQ_P2F_UART0,IRQ_P2F_CAN0,IRQ_P2F_USB1,IRQ_P2F_ENET1,IRQ_P2F_ENET_WAKE1,IRQ_P2F_SDIO1,IRQ_P2F_I2C1,IRQ_P2F_SPI1,IRQ_P2F_UART1,IRQ_P2F_CAN1}), + .MAXIGP0ACLK(M_AXI_GP0_ACLK), + .MAXIGP0ARADDR(M_AXI_GP0_ARADDR), + .MAXIGP0ARBURST(M_AXI_GP0_ARBURST), + .MAXIGP0ARCACHE(\^M_AXI_GP0_ARCACHE ), + .MAXIGP0ARESETN(M_AXI_GP0_ARESETN), + .MAXIGP0ARID(M_AXI_GP0_ARID), + .MAXIGP0ARLEN(M_AXI_GP0_ARLEN), + .MAXIGP0ARLOCK(M_AXI_GP0_ARLOCK), + .MAXIGP0ARPROT(M_AXI_GP0_ARPROT), + .MAXIGP0ARQOS(M_AXI_GP0_ARQOS), + .MAXIGP0ARREADY(M_AXI_GP0_ARREADY), + .MAXIGP0ARSIZE(\^M_AXI_GP0_ARSIZE ), + .MAXIGP0ARVALID(M_AXI_GP0_ARVALID), + .MAXIGP0AWADDR(M_AXI_GP0_AWADDR), + .MAXIGP0AWBURST(M_AXI_GP0_AWBURST), + .MAXIGP0AWCACHE(\^M_AXI_GP0_AWCACHE ), + .MAXIGP0AWID(M_AXI_GP0_AWID), + .MAXIGP0AWLEN(M_AXI_GP0_AWLEN), + .MAXIGP0AWLOCK(M_AXI_GP0_AWLOCK), + .MAXIGP0AWPROT(M_AXI_GP0_AWPROT), + .MAXIGP0AWQOS(M_AXI_GP0_AWQOS), + .MAXIGP0AWREADY(M_AXI_GP0_AWREADY), + .MAXIGP0AWSIZE(\^M_AXI_GP0_AWSIZE ), + .MAXIGP0AWVALID(M_AXI_GP0_AWVALID), + .MAXIGP0BID(M_AXI_GP0_BID), + .MAXIGP0BREADY(M_AXI_GP0_BREADY), + .MAXIGP0BRESP(M_AXI_GP0_BRESP), + .MAXIGP0BVALID(M_AXI_GP0_BVALID), + .MAXIGP0RDATA(M_AXI_GP0_RDATA), + .MAXIGP0RID(M_AXI_GP0_RID), + .MAXIGP0RLAST(M_AXI_GP0_RLAST), + .MAXIGP0RREADY(M_AXI_GP0_RREADY), + .MAXIGP0RRESP(M_AXI_GP0_RRESP), + .MAXIGP0RVALID(M_AXI_GP0_RVALID), + .MAXIGP0WDATA(M_AXI_GP0_WDATA), + .MAXIGP0WID(M_AXI_GP0_WID), + .MAXIGP0WLAST(M_AXI_GP0_WLAST), + .MAXIGP0WREADY(M_AXI_GP0_WREADY), + .MAXIGP0WSTRB(M_AXI_GP0_WSTRB), + .MAXIGP0WVALID(M_AXI_GP0_WVALID), + .MAXIGP1ACLK(M_AXI_GP1_ACLK), + .MAXIGP1ARADDR(M_AXI_GP1_ARADDR), + .MAXIGP1ARBURST(M_AXI_GP1_ARBURST), + .MAXIGP1ARCACHE(\^M_AXI_GP1_ARCACHE ), + .MAXIGP1ARESETN(M_AXI_GP1_ARESETN), + .MAXIGP1ARID(M_AXI_GP1_ARID), + .MAXIGP1ARLEN(M_AXI_GP1_ARLEN), + .MAXIGP1ARLOCK(M_AXI_GP1_ARLOCK), + .MAXIGP1ARPROT(M_AXI_GP1_ARPROT), + .MAXIGP1ARQOS(M_AXI_GP1_ARQOS), + .MAXIGP1ARREADY(M_AXI_GP1_ARREADY), + .MAXIGP1ARSIZE(\^M_AXI_GP1_ARSIZE ), + .MAXIGP1ARVALID(M_AXI_GP1_ARVALID), + .MAXIGP1AWADDR(M_AXI_GP1_AWADDR), + .MAXIGP1AWBURST(M_AXI_GP1_AWBURST), + .MAXIGP1AWCACHE(\^M_AXI_GP1_AWCACHE ), + .MAXIGP1AWID(M_AXI_GP1_AWID), + .MAXIGP1AWLEN(M_AXI_GP1_AWLEN), + .MAXIGP1AWLOCK(M_AXI_GP1_AWLOCK), + .MAXIGP1AWPROT(M_AXI_GP1_AWPROT), + .MAXIGP1AWQOS(M_AXI_GP1_AWQOS), + .MAXIGP1AWREADY(M_AXI_GP1_AWREADY), + .MAXIGP1AWSIZE(\^M_AXI_GP1_AWSIZE ), + .MAXIGP1AWVALID(M_AXI_GP1_AWVALID), + .MAXIGP1BID(M_AXI_GP1_BID), + .MAXIGP1BREADY(M_AXI_GP1_BREADY), + .MAXIGP1BRESP(M_AXI_GP1_BRESP), + .MAXIGP1BVALID(M_AXI_GP1_BVALID), + .MAXIGP1RDATA(M_AXI_GP1_RDATA), + .MAXIGP1RID(M_AXI_GP1_RID), + .MAXIGP1RLAST(M_AXI_GP1_RLAST), + .MAXIGP1RREADY(M_AXI_GP1_RREADY), + .MAXIGP1RRESP(M_AXI_GP1_RRESP), + .MAXIGP1RVALID(M_AXI_GP1_RVALID), + .MAXIGP1WDATA(M_AXI_GP1_WDATA), + .MAXIGP1WID(M_AXI_GP1_WID), + .MAXIGP1WLAST(M_AXI_GP1_WLAST), + .MAXIGP1WREADY(M_AXI_GP1_WREADY), + .MAXIGP1WSTRB(M_AXI_GP1_WSTRB), + .MAXIGP1WVALID(M_AXI_GP1_WVALID), + .MIO(buffered_MIO), + .PSCLK(buffered_PS_CLK), + .PSPORB(buffered_PS_PORB), + .PSSRSTB(buffered_PS_SRSTB), + .SAXIACPACLK(S_AXI_ACP_ACLK), + .SAXIACPARADDR(S_AXI_ACP_ARADDR), + .SAXIACPARBURST(S_AXI_ACP_ARBURST), + .SAXIACPARCACHE(S_AXI_ACP_ARCACHE), + .SAXIACPARESETN(S_AXI_ACP_ARESETN), + .SAXIACPARID(S_AXI_ACP_ARID), + .SAXIACPARLEN(S_AXI_ACP_ARLEN), + .SAXIACPARLOCK(S_AXI_ACP_ARLOCK), + .SAXIACPARPROT(S_AXI_ACP_ARPROT), + .SAXIACPARQOS(S_AXI_ACP_ARQOS), + .SAXIACPARREADY(S_AXI_ACP_ARREADY), + .SAXIACPARSIZE(S_AXI_ACP_ARSIZE[1:0]), + .SAXIACPARUSER(S_AXI_ACP_ARUSER), + .SAXIACPARVALID(S_AXI_ACP_ARVALID), + .SAXIACPAWADDR(S_AXI_ACP_AWADDR), + .SAXIACPAWBURST(S_AXI_ACP_AWBURST), + .SAXIACPAWCACHE(S_AXI_ACP_AWCACHE), + .SAXIACPAWID(S_AXI_ACP_AWID), + .SAXIACPAWLEN(S_AXI_ACP_AWLEN), + .SAXIACPAWLOCK(S_AXI_ACP_AWLOCK), + .SAXIACPAWPROT(S_AXI_ACP_AWPROT), + .SAXIACPAWQOS(S_AXI_ACP_AWQOS), + .SAXIACPAWREADY(S_AXI_ACP_AWREADY), + .SAXIACPAWSIZE(S_AXI_ACP_AWSIZE[1:0]), + .SAXIACPAWUSER(S_AXI_ACP_AWUSER), + .SAXIACPAWVALID(S_AXI_ACP_AWVALID), + .SAXIACPBID(S_AXI_ACP_BID), + .SAXIACPBREADY(S_AXI_ACP_BREADY), + .SAXIACPBRESP(S_AXI_ACP_BRESP), + .SAXIACPBVALID(S_AXI_ACP_BVALID), + .SAXIACPRDATA(S_AXI_ACP_RDATA), + .SAXIACPRID(S_AXI_ACP_RID), + .SAXIACPRLAST(S_AXI_ACP_RLAST), + .SAXIACPRREADY(S_AXI_ACP_RREADY), + .SAXIACPRRESP(S_AXI_ACP_RRESP), + .SAXIACPRVALID(S_AXI_ACP_RVALID), + .SAXIACPWDATA(S_AXI_ACP_WDATA), + .SAXIACPWID(S_AXI_ACP_WID), + .SAXIACPWLAST(S_AXI_ACP_WLAST), + .SAXIACPWREADY(S_AXI_ACP_WREADY), + .SAXIACPWSTRB(S_AXI_ACP_WSTRB), + .SAXIACPWVALID(S_AXI_ACP_WVALID), + .SAXIGP0ACLK(S_AXI_GP0_ACLK), + .SAXIGP0ARADDR(S_AXI_GP0_ARADDR), + .SAXIGP0ARBURST(S_AXI_GP0_ARBURST), + .SAXIGP0ARCACHE(S_AXI_GP0_ARCACHE), + .SAXIGP0ARESETN(S_AXI_GP0_ARESETN), + .SAXIGP0ARID(S_AXI_GP0_ARID), + .SAXIGP0ARLEN(S_AXI_GP0_ARLEN), + .SAXIGP0ARLOCK(S_AXI_GP0_ARLOCK), + .SAXIGP0ARPROT(S_AXI_GP0_ARPROT), + .SAXIGP0ARQOS(S_AXI_GP0_ARQOS), + .SAXIGP0ARREADY(S_AXI_GP0_ARREADY), + .SAXIGP0ARSIZE(S_AXI_GP0_ARSIZE[1:0]), + .SAXIGP0ARVALID(S_AXI_GP0_ARVALID), + .SAXIGP0AWADDR(S_AXI_GP0_AWADDR), + .SAXIGP0AWBURST(S_AXI_GP0_AWBURST), + .SAXIGP0AWCACHE(S_AXI_GP0_AWCACHE), + .SAXIGP0AWID(S_AXI_GP0_AWID), + .SAXIGP0AWLEN(S_AXI_GP0_AWLEN), + .SAXIGP0AWLOCK(S_AXI_GP0_AWLOCK), + .SAXIGP0AWPROT(S_AXI_GP0_AWPROT), + .SAXIGP0AWQOS(S_AXI_GP0_AWQOS), + .SAXIGP0AWREADY(S_AXI_GP0_AWREADY), + .SAXIGP0AWSIZE(S_AXI_GP0_AWSIZE[1:0]), + .SAXIGP0AWVALID(S_AXI_GP0_AWVALID), + .SAXIGP0BID(S_AXI_GP0_BID), + .SAXIGP0BREADY(S_AXI_GP0_BREADY), + .SAXIGP0BRESP(S_AXI_GP0_BRESP), + .SAXIGP0BVALID(S_AXI_GP0_BVALID), + .SAXIGP0RDATA(S_AXI_GP0_RDATA), + .SAXIGP0RID(S_AXI_GP0_RID), + .SAXIGP0RLAST(S_AXI_GP0_RLAST), + .SAXIGP0RREADY(S_AXI_GP0_RREADY), + .SAXIGP0RRESP(S_AXI_GP0_RRESP), + .SAXIGP0RVALID(S_AXI_GP0_RVALID), + .SAXIGP0WDATA(S_AXI_GP0_WDATA), + .SAXIGP0WID(S_AXI_GP0_WID), + .SAXIGP0WLAST(S_AXI_GP0_WLAST), + .SAXIGP0WREADY(S_AXI_GP0_WREADY), + .SAXIGP0WSTRB(S_AXI_GP0_WSTRB), + .SAXIGP0WVALID(S_AXI_GP0_WVALID), + .SAXIGP1ACLK(S_AXI_GP1_ACLK), + .SAXIGP1ARADDR(S_AXI_GP1_ARADDR), + .SAXIGP1ARBURST(S_AXI_GP1_ARBURST), + .SAXIGP1ARCACHE(S_AXI_GP1_ARCACHE), + .SAXIGP1ARESETN(S_AXI_GP1_ARESETN), + .SAXIGP1ARID(S_AXI_GP1_ARID), + .SAXIGP1ARLEN(S_AXI_GP1_ARLEN), + .SAXIGP1ARLOCK(S_AXI_GP1_ARLOCK), + .SAXIGP1ARPROT(S_AXI_GP1_ARPROT), + .SAXIGP1ARQOS(S_AXI_GP1_ARQOS), + .SAXIGP1ARREADY(S_AXI_GP1_ARREADY), + .SAXIGP1ARSIZE(S_AXI_GP1_ARSIZE[1:0]), + .SAXIGP1ARVALID(S_AXI_GP1_ARVALID), + .SAXIGP1AWADDR(S_AXI_GP1_AWADDR), + .SAXIGP1AWBURST(S_AXI_GP1_AWBURST), + .SAXIGP1AWCACHE(S_AXI_GP1_AWCACHE), + .SAXIGP1AWID(S_AXI_GP1_AWID), + .SAXIGP1AWLEN(S_AXI_GP1_AWLEN), + .SAXIGP1AWLOCK(S_AXI_GP1_AWLOCK), + .SAXIGP1AWPROT(S_AXI_GP1_AWPROT), + .SAXIGP1AWQOS(S_AXI_GP1_AWQOS), + .SAXIGP1AWREADY(S_AXI_GP1_AWREADY), + .SAXIGP1AWSIZE(S_AXI_GP1_AWSIZE[1:0]), + .SAXIGP1AWVALID(S_AXI_GP1_AWVALID), + .SAXIGP1BID(S_AXI_GP1_BID), + .SAXIGP1BREADY(S_AXI_GP1_BREADY), + .SAXIGP1BRESP(S_AXI_GP1_BRESP), + .SAXIGP1BVALID(S_AXI_GP1_BVALID), + .SAXIGP1RDATA(S_AXI_GP1_RDATA), + .SAXIGP1RID(S_AXI_GP1_RID), + .SAXIGP1RLAST(S_AXI_GP1_RLAST), + .SAXIGP1RREADY(S_AXI_GP1_RREADY), + .SAXIGP1RRESP(S_AXI_GP1_RRESP), + .SAXIGP1RVALID(S_AXI_GP1_RVALID), + .SAXIGP1WDATA(S_AXI_GP1_WDATA), + .SAXIGP1WID(S_AXI_GP1_WID), + .SAXIGP1WLAST(S_AXI_GP1_WLAST), + .SAXIGP1WREADY(S_AXI_GP1_WREADY), + .SAXIGP1WSTRB(S_AXI_GP1_WSTRB), + .SAXIGP1WVALID(S_AXI_GP1_WVALID), + .SAXIHP0ACLK(S_AXI_HP0_ACLK), + .SAXIHP0ARADDR(S_AXI_HP0_ARADDR), + .SAXIHP0ARBURST(S_AXI_HP0_ARBURST), + .SAXIHP0ARCACHE(S_AXI_HP0_ARCACHE), + .SAXIHP0ARESETN(S_AXI_HP0_ARESETN), + .SAXIHP0ARID(S_AXI_HP0_ARID), + .SAXIHP0ARLEN(S_AXI_HP0_ARLEN), + .SAXIHP0ARLOCK(S_AXI_HP0_ARLOCK), + .SAXIHP0ARPROT(S_AXI_HP0_ARPROT), + .SAXIHP0ARQOS(S_AXI_HP0_ARQOS), + .SAXIHP0ARREADY(S_AXI_HP0_ARREADY), + .SAXIHP0ARSIZE(S_AXI_HP0_ARSIZE[1:0]), + .SAXIHP0ARVALID(S_AXI_HP0_ARVALID), + .SAXIHP0AWADDR(S_AXI_HP0_AWADDR), + .SAXIHP0AWBURST(S_AXI_HP0_AWBURST), + .SAXIHP0AWCACHE(S_AXI_HP0_AWCACHE), + .SAXIHP0AWID(S_AXI_HP0_AWID), + .SAXIHP0AWLEN(S_AXI_HP0_AWLEN), + .SAXIHP0AWLOCK(S_AXI_HP0_AWLOCK), + .SAXIHP0AWPROT(S_AXI_HP0_AWPROT), + .SAXIHP0AWQOS(S_AXI_HP0_AWQOS), + .SAXIHP0AWREADY(S_AXI_HP0_AWREADY), + .SAXIHP0AWSIZE(S_AXI_HP0_AWSIZE[1:0]), + .SAXIHP0AWVALID(S_AXI_HP0_AWVALID), + .SAXIHP0BID(S_AXI_HP0_BID), + .SAXIHP0BREADY(S_AXI_HP0_BREADY), + .SAXIHP0BRESP(S_AXI_HP0_BRESP), + .SAXIHP0BVALID(S_AXI_HP0_BVALID), + .SAXIHP0RACOUNT(S_AXI_HP0_RACOUNT), + .SAXIHP0RCOUNT(S_AXI_HP0_RCOUNT), + .SAXIHP0RDATA(S_AXI_HP0_RDATA), + .SAXIHP0RDISSUECAP1EN(S_AXI_HP0_RDISSUECAP1_EN), + .SAXIHP0RID(S_AXI_HP0_RID), + .SAXIHP0RLAST(S_AXI_HP0_RLAST), + .SAXIHP0RREADY(S_AXI_HP0_RREADY), + .SAXIHP0RRESP(S_AXI_HP0_RRESP), + .SAXIHP0RVALID(S_AXI_HP0_RVALID), + .SAXIHP0WACOUNT(S_AXI_HP0_WACOUNT), + .SAXIHP0WCOUNT(S_AXI_HP0_WCOUNT), + .SAXIHP0WDATA(S_AXI_HP0_WDATA), + .SAXIHP0WID(S_AXI_HP0_WID), + .SAXIHP0WLAST(S_AXI_HP0_WLAST), + .SAXIHP0WREADY(S_AXI_HP0_WREADY), + .SAXIHP0WRISSUECAP1EN(S_AXI_HP0_WRISSUECAP1_EN), + .SAXIHP0WSTRB(S_AXI_HP0_WSTRB), + .SAXIHP0WVALID(S_AXI_HP0_WVALID), + .SAXIHP1ACLK(S_AXI_HP1_ACLK), + .SAXIHP1ARADDR(S_AXI_HP1_ARADDR), + .SAXIHP1ARBURST(S_AXI_HP1_ARBURST), + .SAXIHP1ARCACHE(S_AXI_HP1_ARCACHE), + .SAXIHP1ARESETN(S_AXI_HP1_ARESETN), + .SAXIHP1ARID(S_AXI_HP1_ARID), + .SAXIHP1ARLEN(S_AXI_HP1_ARLEN), + .SAXIHP1ARLOCK(S_AXI_HP1_ARLOCK), + .SAXIHP1ARPROT(S_AXI_HP1_ARPROT), + .SAXIHP1ARQOS(S_AXI_HP1_ARQOS), + .SAXIHP1ARREADY(S_AXI_HP1_ARREADY), + .SAXIHP1ARSIZE(S_AXI_HP1_ARSIZE[1:0]), + .SAXIHP1ARVALID(S_AXI_HP1_ARVALID), + .SAXIHP1AWADDR(S_AXI_HP1_AWADDR), + .SAXIHP1AWBURST(S_AXI_HP1_AWBURST), + .SAXIHP1AWCACHE(S_AXI_HP1_AWCACHE), + .SAXIHP1AWID(S_AXI_HP1_AWID), + .SAXIHP1AWLEN(S_AXI_HP1_AWLEN), + .SAXIHP1AWLOCK(S_AXI_HP1_AWLOCK), + .SAXIHP1AWPROT(S_AXI_HP1_AWPROT), + .SAXIHP1AWQOS(S_AXI_HP1_AWQOS), + .SAXIHP1AWREADY(S_AXI_HP1_AWREADY), + .SAXIHP1AWSIZE(S_AXI_HP1_AWSIZE[1:0]), + .SAXIHP1AWVALID(S_AXI_HP1_AWVALID), + .SAXIHP1BID(S_AXI_HP1_BID), + .SAXIHP1BREADY(S_AXI_HP1_BREADY), + .SAXIHP1BRESP(S_AXI_HP1_BRESP), + .SAXIHP1BVALID(S_AXI_HP1_BVALID), + .SAXIHP1RACOUNT(S_AXI_HP1_RACOUNT), + .SAXIHP1RCOUNT(S_AXI_HP1_RCOUNT), + .SAXIHP1RDATA(S_AXI_HP1_RDATA), + .SAXIHP1RDISSUECAP1EN(S_AXI_HP1_RDISSUECAP1_EN), + .SAXIHP1RID(S_AXI_HP1_RID), + .SAXIHP1RLAST(S_AXI_HP1_RLAST), + .SAXIHP1RREADY(S_AXI_HP1_RREADY), + .SAXIHP1RRESP(S_AXI_HP1_RRESP), + .SAXIHP1RVALID(S_AXI_HP1_RVALID), + .SAXIHP1WACOUNT(S_AXI_HP1_WACOUNT), + .SAXIHP1WCOUNT(S_AXI_HP1_WCOUNT), + .SAXIHP1WDATA(S_AXI_HP1_WDATA), + .SAXIHP1WID(S_AXI_HP1_WID), + .SAXIHP1WLAST(S_AXI_HP1_WLAST), + .SAXIHP1WREADY(S_AXI_HP1_WREADY), + .SAXIHP1WRISSUECAP1EN(S_AXI_HP1_WRISSUECAP1_EN), + .SAXIHP1WSTRB(S_AXI_HP1_WSTRB), + .SAXIHP1WVALID(S_AXI_HP1_WVALID), + .SAXIHP2ACLK(S_AXI_HP2_ACLK), + .SAXIHP2ARADDR(S_AXI_HP2_ARADDR), + .SAXIHP2ARBURST(S_AXI_HP2_ARBURST), + .SAXIHP2ARCACHE(S_AXI_HP2_ARCACHE), + .SAXIHP2ARESETN(S_AXI_HP2_ARESETN), + .SAXIHP2ARID(S_AXI_HP2_ARID), + .SAXIHP2ARLEN(S_AXI_HP2_ARLEN), + .SAXIHP2ARLOCK(S_AXI_HP2_ARLOCK), + .SAXIHP2ARPROT(S_AXI_HP2_ARPROT), + .SAXIHP2ARQOS(S_AXI_HP2_ARQOS), + .SAXIHP2ARREADY(S_AXI_HP2_ARREADY), + .SAXIHP2ARSIZE(S_AXI_HP2_ARSIZE[1:0]), + .SAXIHP2ARVALID(S_AXI_HP2_ARVALID), + .SAXIHP2AWADDR(S_AXI_HP2_AWADDR), + .SAXIHP2AWBURST(S_AXI_HP2_AWBURST), + .SAXIHP2AWCACHE(S_AXI_HP2_AWCACHE), + .SAXIHP2AWID(S_AXI_HP2_AWID), + .SAXIHP2AWLEN(S_AXI_HP2_AWLEN), + .SAXIHP2AWLOCK(S_AXI_HP2_AWLOCK), + .SAXIHP2AWPROT(S_AXI_HP2_AWPROT), + .SAXIHP2AWQOS(S_AXI_HP2_AWQOS), + .SAXIHP2AWREADY(S_AXI_HP2_AWREADY), + .SAXIHP2AWSIZE(S_AXI_HP2_AWSIZE[1:0]), + .SAXIHP2AWVALID(S_AXI_HP2_AWVALID), + .SAXIHP2BID(S_AXI_HP2_BID), + .SAXIHP2BREADY(S_AXI_HP2_BREADY), + .SAXIHP2BRESP(S_AXI_HP2_BRESP), + .SAXIHP2BVALID(S_AXI_HP2_BVALID), + .SAXIHP2RACOUNT(S_AXI_HP2_RACOUNT), + .SAXIHP2RCOUNT(S_AXI_HP2_RCOUNT), + .SAXIHP2RDATA(S_AXI_HP2_RDATA), + .SAXIHP2RDISSUECAP1EN(S_AXI_HP2_RDISSUECAP1_EN), + .SAXIHP2RID(S_AXI_HP2_RID), + .SAXIHP2RLAST(S_AXI_HP2_RLAST), + .SAXIHP2RREADY(S_AXI_HP2_RREADY), + .SAXIHP2RRESP(S_AXI_HP2_RRESP), + .SAXIHP2RVALID(S_AXI_HP2_RVALID), + .SAXIHP2WACOUNT(S_AXI_HP2_WACOUNT), + .SAXIHP2WCOUNT(S_AXI_HP2_WCOUNT), + .SAXIHP2WDATA(S_AXI_HP2_WDATA), + .SAXIHP2WID(S_AXI_HP2_WID), + .SAXIHP2WLAST(S_AXI_HP2_WLAST), + .SAXIHP2WREADY(S_AXI_HP2_WREADY), + .SAXIHP2WRISSUECAP1EN(S_AXI_HP2_WRISSUECAP1_EN), + .SAXIHP2WSTRB(S_AXI_HP2_WSTRB), + .SAXIHP2WVALID(S_AXI_HP2_WVALID), + .SAXIHP3ACLK(S_AXI_HP3_ACLK), + .SAXIHP3ARADDR(S_AXI_HP3_ARADDR), + .SAXIHP3ARBURST(S_AXI_HP3_ARBURST), + .SAXIHP3ARCACHE(S_AXI_HP3_ARCACHE), + .SAXIHP3ARESETN(S_AXI_HP3_ARESETN), + .SAXIHP3ARID(S_AXI_HP3_ARID), + .SAXIHP3ARLEN(S_AXI_HP3_ARLEN), + .SAXIHP3ARLOCK(S_AXI_HP3_ARLOCK), + .SAXIHP3ARPROT(S_AXI_HP3_ARPROT), + .SAXIHP3ARQOS(S_AXI_HP3_ARQOS), + .SAXIHP3ARREADY(S_AXI_HP3_ARREADY), + .SAXIHP3ARSIZE(S_AXI_HP3_ARSIZE[1:0]), + .SAXIHP3ARVALID(S_AXI_HP3_ARVALID), + .SAXIHP3AWADDR(S_AXI_HP3_AWADDR), + .SAXIHP3AWBURST(S_AXI_HP3_AWBURST), + .SAXIHP3AWCACHE(S_AXI_HP3_AWCACHE), + .SAXIHP3AWID(S_AXI_HP3_AWID), + .SAXIHP3AWLEN(S_AXI_HP3_AWLEN), + .SAXIHP3AWLOCK(S_AXI_HP3_AWLOCK), + .SAXIHP3AWPROT(S_AXI_HP3_AWPROT), + .SAXIHP3AWQOS(S_AXI_HP3_AWQOS), + .SAXIHP3AWREADY(S_AXI_HP3_AWREADY), + .SAXIHP3AWSIZE(S_AXI_HP3_AWSIZE[1:0]), + .SAXIHP3AWVALID(S_AXI_HP3_AWVALID), + .SAXIHP3BID(S_AXI_HP3_BID), + .SAXIHP3BREADY(S_AXI_HP3_BREADY), + .SAXIHP3BRESP(S_AXI_HP3_BRESP), + .SAXIHP3BVALID(S_AXI_HP3_BVALID), + .SAXIHP3RACOUNT(S_AXI_HP3_RACOUNT), + .SAXIHP3RCOUNT(S_AXI_HP3_RCOUNT), + .SAXIHP3RDATA(S_AXI_HP3_RDATA), + .SAXIHP3RDISSUECAP1EN(S_AXI_HP3_RDISSUECAP1_EN), + .SAXIHP3RID(S_AXI_HP3_RID), + .SAXIHP3RLAST(S_AXI_HP3_RLAST), + .SAXIHP3RREADY(S_AXI_HP3_RREADY), + .SAXIHP3RRESP(S_AXI_HP3_RRESP), + .SAXIHP3RVALID(S_AXI_HP3_RVALID), + .SAXIHP3WACOUNT(S_AXI_HP3_WACOUNT), + .SAXIHP3WCOUNT(S_AXI_HP3_WCOUNT), + .SAXIHP3WDATA(S_AXI_HP3_WDATA), + .SAXIHP3WID(S_AXI_HP3_WID), + .SAXIHP3WLAST(S_AXI_HP3_WLAST), + .SAXIHP3WREADY(S_AXI_HP3_WREADY), + .SAXIHP3WRISSUECAP1EN(S_AXI_HP3_WRISSUECAP1_EN), + .SAXIHP3WSTRB(S_AXI_HP3_WSTRB), + .SAXIHP3WVALID(S_AXI_HP3_WVALID)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF PS_CLK_BIBUF + (.IO(buffered_PS_CLK), + .PAD(PS_CLK)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF PS_PORB_BIBUF + (.IO(buffered_PS_PORB), + .PAD(PS_PORB)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF PS_SRSTB_BIBUF + (.IO(buffered_PS_SRSTB), + .PAD(PS_SRSTB)); + LUT1 #( + .INIT(2'h1)) + SDIO0_CMD_T_INST_0 + (.I0(SDIO0_CMD_T_n), + .O(SDIO0_CMD_T)); + LUT1 #( + .INIT(2'h1)) + \SDIO0_DATA_T[0]_INST_0 + (.I0(SDIO0_DATA_T_n[0]), + .O(SDIO0_DATA_T[0])); + LUT1 #( + .INIT(2'h1)) + \SDIO0_DATA_T[1]_INST_0 + (.I0(SDIO0_DATA_T_n[1]), + .O(SDIO0_DATA_T[1])); + LUT1 #( + .INIT(2'h1)) + \SDIO0_DATA_T[2]_INST_0 + (.I0(SDIO0_DATA_T_n[2]), + .O(SDIO0_DATA_T[2])); + LUT1 #( + .INIT(2'h1)) + \SDIO0_DATA_T[3]_INST_0 + (.I0(SDIO0_DATA_T_n[3]), + .O(SDIO0_DATA_T[3])); + LUT1 #( + .INIT(2'h1)) + SDIO1_CMD_T_INST_0 + (.I0(SDIO1_CMD_T_n), + .O(SDIO1_CMD_T)); + LUT1 #( + .INIT(2'h1)) + \SDIO1_DATA_T[0]_INST_0 + (.I0(SDIO1_DATA_T_n[0]), + .O(SDIO1_DATA_T[0])); + LUT1 #( + .INIT(2'h1)) + \SDIO1_DATA_T[1]_INST_0 + (.I0(SDIO1_DATA_T_n[1]), + .O(SDIO1_DATA_T[1])); + LUT1 #( + .INIT(2'h1)) + \SDIO1_DATA_T[2]_INST_0 + (.I0(SDIO1_DATA_T_n[2]), + .O(SDIO1_DATA_T[2])); + LUT1 #( + .INIT(2'h1)) + \SDIO1_DATA_T[3]_INST_0 + (.I0(SDIO1_DATA_T_n[3]), + .O(SDIO1_DATA_T[3])); + LUT1 #( + .INIT(2'h1)) + SPI0_MISO_T_INST_0 + (.I0(SPI0_MISO_T_n), + .O(SPI0_MISO_T)); + LUT1 #( + .INIT(2'h1)) + SPI0_MOSI_T_INST_0 + (.I0(SPI0_MOSI_T_n), + .O(SPI0_MOSI_T)); + LUT1 #( + .INIT(2'h1)) + SPI0_SCLK_T_INST_0 + (.I0(SPI0_SCLK_T_n), + .O(SPI0_SCLK_T)); + LUT1 #( + .INIT(2'h1)) + SPI0_SS_T_INST_0 + (.I0(SPI0_SS_T_n), + .O(SPI0_SS_T)); + LUT1 #( + .INIT(2'h1)) + SPI1_MISO_T_INST_0 + (.I0(SPI1_MISO_T_n), + .O(SPI1_MISO_T)); + LUT1 #( + .INIT(2'h1)) + SPI1_MOSI_T_INST_0 + (.I0(SPI1_MOSI_T_n), + .O(SPI1_MOSI_T)); + LUT1 #( + .INIT(2'h1)) + SPI1_SCLK_T_INST_0 + (.I0(SPI1_SCLK_T_n), + .O(SPI1_SCLK_T)); + LUT1 #( + .INIT(2'h1)) + SPI1_SS_T_INST_0 + (.I0(SPI1_SS_T_n), + .O(SPI1_SS_T)); + VCC VCC + (.P(\ )); + (* BOX_TYPE = "PRIMITIVE" *) + BUFG \buffer_fclk_clk_0.FCLK_CLK_0_BUFG + (.I(FCLK_CLK_unbuffered), + .O(FCLK_CLK0)); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[0].MIO_BIBUF + (.IO(buffered_MIO[0]), + .PAD(MIO[0])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[10].MIO_BIBUF + (.IO(buffered_MIO[10]), + .PAD(MIO[10])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[11].MIO_BIBUF + (.IO(buffered_MIO[11]), + .PAD(MIO[11])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[12].MIO_BIBUF + (.IO(buffered_MIO[12]), + .PAD(MIO[12])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[13].MIO_BIBUF + (.IO(buffered_MIO[13]), + .PAD(MIO[13])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[14].MIO_BIBUF + (.IO(buffered_MIO[14]), + .PAD(MIO[14])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[15].MIO_BIBUF + (.IO(buffered_MIO[15]), + .PAD(MIO[15])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[16].MIO_BIBUF + (.IO(buffered_MIO[16]), + .PAD(MIO[16])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[17].MIO_BIBUF + (.IO(buffered_MIO[17]), + .PAD(MIO[17])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[18].MIO_BIBUF + (.IO(buffered_MIO[18]), + .PAD(MIO[18])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[19].MIO_BIBUF + (.IO(buffered_MIO[19]), + .PAD(MIO[19])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[1].MIO_BIBUF + (.IO(buffered_MIO[1]), + .PAD(MIO[1])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[20].MIO_BIBUF + (.IO(buffered_MIO[20]), + .PAD(MIO[20])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[21].MIO_BIBUF + (.IO(buffered_MIO[21]), + .PAD(MIO[21])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[22].MIO_BIBUF + (.IO(buffered_MIO[22]), + .PAD(MIO[22])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[23].MIO_BIBUF + (.IO(buffered_MIO[23]), + .PAD(MIO[23])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[24].MIO_BIBUF + (.IO(buffered_MIO[24]), + .PAD(MIO[24])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[25].MIO_BIBUF + (.IO(buffered_MIO[25]), + .PAD(MIO[25])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[26].MIO_BIBUF + (.IO(buffered_MIO[26]), + .PAD(MIO[26])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[27].MIO_BIBUF + (.IO(buffered_MIO[27]), + .PAD(MIO[27])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[28].MIO_BIBUF + (.IO(buffered_MIO[28]), + .PAD(MIO[28])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[29].MIO_BIBUF + (.IO(buffered_MIO[29]), + .PAD(MIO[29])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[2].MIO_BIBUF + (.IO(buffered_MIO[2]), + .PAD(MIO[2])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[30].MIO_BIBUF + (.IO(buffered_MIO[30]), + .PAD(MIO[30])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[31].MIO_BIBUF + (.IO(buffered_MIO[31]), + .PAD(MIO[31])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[32].MIO_BIBUF + (.IO(buffered_MIO[32]), + .PAD(MIO[32])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[33].MIO_BIBUF + (.IO(buffered_MIO[33]), + .PAD(MIO[33])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[34].MIO_BIBUF + (.IO(buffered_MIO[34]), + .PAD(MIO[34])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[35].MIO_BIBUF + (.IO(buffered_MIO[35]), + .PAD(MIO[35])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[36].MIO_BIBUF + (.IO(buffered_MIO[36]), + .PAD(MIO[36])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[37].MIO_BIBUF + (.IO(buffered_MIO[37]), + .PAD(MIO[37])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[38].MIO_BIBUF + (.IO(buffered_MIO[38]), + .PAD(MIO[38])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[39].MIO_BIBUF + (.IO(buffered_MIO[39]), + .PAD(MIO[39])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[3].MIO_BIBUF + (.IO(buffered_MIO[3]), + .PAD(MIO[3])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[40].MIO_BIBUF + (.IO(buffered_MIO[40]), + .PAD(MIO[40])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[41].MIO_BIBUF + (.IO(buffered_MIO[41]), + .PAD(MIO[41])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[42].MIO_BIBUF + (.IO(buffered_MIO[42]), + .PAD(MIO[42])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[43].MIO_BIBUF + (.IO(buffered_MIO[43]), + .PAD(MIO[43])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[44].MIO_BIBUF + (.IO(buffered_MIO[44]), + .PAD(MIO[44])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[45].MIO_BIBUF + (.IO(buffered_MIO[45]), + .PAD(MIO[45])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[46].MIO_BIBUF + (.IO(buffered_MIO[46]), + .PAD(MIO[46])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[47].MIO_BIBUF + (.IO(buffered_MIO[47]), + .PAD(MIO[47])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[48].MIO_BIBUF + (.IO(buffered_MIO[48]), + .PAD(MIO[48])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[49].MIO_BIBUF + (.IO(buffered_MIO[49]), + .PAD(MIO[49])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[4].MIO_BIBUF + (.IO(buffered_MIO[4]), + .PAD(MIO[4])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[50].MIO_BIBUF + (.IO(buffered_MIO[50]), + .PAD(MIO[50])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[51].MIO_BIBUF + (.IO(buffered_MIO[51]), + .PAD(MIO[51])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[52].MIO_BIBUF + (.IO(buffered_MIO[52]), + .PAD(MIO[52])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[53].MIO_BIBUF + (.IO(buffered_MIO[53]), + .PAD(MIO[53])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[5].MIO_BIBUF + (.IO(buffered_MIO[5]), + .PAD(MIO[5])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[6].MIO_BIBUF + (.IO(buffered_MIO[6]), + .PAD(MIO[6])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[7].MIO_BIBUF + (.IO(buffered_MIO[7]), + .PAD(MIO[7])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[8].MIO_BIBUF + (.IO(buffered_MIO[8]), + .PAD(MIO[8])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk13[9].MIO_BIBUF + (.IO(buffered_MIO[9]), + .PAD(MIO[9])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk14[0].DDR_BankAddr_BIBUF + (.IO(buffered_DDR_BankAddr[0]), + .PAD(DDR_BankAddr[0])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk14[1].DDR_BankAddr_BIBUF + (.IO(buffered_DDR_BankAddr[1]), + .PAD(DDR_BankAddr[1])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk14[2].DDR_BankAddr_BIBUF + (.IO(buffered_DDR_BankAddr[2]), + .PAD(DDR_BankAddr[2])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[0].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[0]), + .PAD(DDR_Addr[0])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[10].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[10]), + .PAD(DDR_Addr[10])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[11].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[11]), + .PAD(DDR_Addr[11])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[12].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[12]), + .PAD(DDR_Addr[12])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[13].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[13]), + .PAD(DDR_Addr[13])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[14].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[14]), + .PAD(DDR_Addr[14])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[1].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[1]), + .PAD(DDR_Addr[1])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[2].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[2]), + .PAD(DDR_Addr[2])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[3].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[3]), + .PAD(DDR_Addr[3])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[4].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[4]), + .PAD(DDR_Addr[4])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[5].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[5]), + .PAD(DDR_Addr[5])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[6].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[6]), + .PAD(DDR_Addr[6])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[7].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[7]), + .PAD(DDR_Addr[7])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[8].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[8]), + .PAD(DDR_Addr[8])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk15[9].DDR_Addr_BIBUF + (.IO(buffered_DDR_Addr[9]), + .PAD(DDR_Addr[9])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk16[0].DDR_DM_BIBUF + (.IO(buffered_DDR_DM[0]), + .PAD(DDR_DM[0])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk16[1].DDR_DM_BIBUF + (.IO(buffered_DDR_DM[1]), + .PAD(DDR_DM[1])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk16[2].DDR_DM_BIBUF + (.IO(buffered_DDR_DM[2]), + .PAD(DDR_DM[2])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk16[3].DDR_DM_BIBUF + (.IO(buffered_DDR_DM[3]), + .PAD(DDR_DM[3])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[0].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[0]), + .PAD(DDR_DQ[0])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[10].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[10]), + .PAD(DDR_DQ[10])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[11].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[11]), + .PAD(DDR_DQ[11])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[12].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[12]), + .PAD(DDR_DQ[12])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[13].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[13]), + .PAD(DDR_DQ[13])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[14].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[14]), + .PAD(DDR_DQ[14])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[15].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[15]), + .PAD(DDR_DQ[15])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[16].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[16]), + .PAD(DDR_DQ[16])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[17].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[17]), + .PAD(DDR_DQ[17])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[18].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[18]), + .PAD(DDR_DQ[18])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[19].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[19]), + .PAD(DDR_DQ[19])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[1].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[1]), + .PAD(DDR_DQ[1])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[20].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[20]), + .PAD(DDR_DQ[20])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[21].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[21]), + .PAD(DDR_DQ[21])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[22].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[22]), + .PAD(DDR_DQ[22])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[23].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[23]), + .PAD(DDR_DQ[23])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[24].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[24]), + .PAD(DDR_DQ[24])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[25].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[25]), + .PAD(DDR_DQ[25])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[26].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[26]), + .PAD(DDR_DQ[26])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[27].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[27]), + .PAD(DDR_DQ[27])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[28].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[28]), + .PAD(DDR_DQ[28])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[29].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[29]), + .PAD(DDR_DQ[29])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[2].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[2]), + .PAD(DDR_DQ[2])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[30].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[30]), + .PAD(DDR_DQ[30])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[31].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[31]), + .PAD(DDR_DQ[31])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[3].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[3]), + .PAD(DDR_DQ[3])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[4].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[4]), + .PAD(DDR_DQ[4])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[5].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[5]), + .PAD(DDR_DQ[5])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[6].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[6]), + .PAD(DDR_DQ[6])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[7].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[7]), + .PAD(DDR_DQ[7])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[8].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[8]), + .PAD(DDR_DQ[8])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk17[9].DDR_DQ_BIBUF + (.IO(buffered_DDR_DQ[9]), + .PAD(DDR_DQ[9])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk18[0].DDR_DQS_n_BIBUF + (.IO(buffered_DDR_DQS_n[0]), + .PAD(DDR_DQS_n[0])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk18[1].DDR_DQS_n_BIBUF + (.IO(buffered_DDR_DQS_n[1]), + .PAD(DDR_DQS_n[1])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk18[2].DDR_DQS_n_BIBUF + (.IO(buffered_DDR_DQS_n[2]), + .PAD(DDR_DQS_n[2])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk18[3].DDR_DQS_n_BIBUF + (.IO(buffered_DDR_DQS_n[3]), + .PAD(DDR_DQS_n[3])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk19[0].DDR_DQS_BIBUF + (.IO(buffered_DDR_DQS[0]), + .PAD(DDR_DQS[0])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk19[1].DDR_DQS_BIBUF + (.IO(buffered_DDR_DQS[1]), + .PAD(DDR_DQS[1])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk19[2].DDR_DQS_BIBUF + (.IO(buffered_DDR_DQS[2]), + .PAD(DDR_DQS[2])); + (* BOX_TYPE = "PRIMITIVE" *) + BIBUF \genblk19[3].DDR_DQS_BIBUF + (.IO(buffered_DDR_DQS[3]), + .PAD(DDR_DQS[3])); + LUT1 #( + .INIT(2'h2)) + i_0 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[0] )); + LUT1 #( + .INIT(2'h2)) + i_1 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[0] [1])); + LUT1 #( + .INIT(2'h2)) + i_10 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[7] [1])); + LUT1 #( + .INIT(2'h2)) + i_11 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[7] [0])); + LUT1 #( + .INIT(2'h2)) + i_12 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[6] [1])); + LUT1 #( + .INIT(2'h2)) + i_13 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[6] [0])); + LUT1 #( + .INIT(2'h2)) + i_14 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[5] [1])); + LUT1 #( + .INIT(2'h2)) + i_15 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[5] [0])); + LUT1 #( + .INIT(2'h2)) + i_16 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[4] [1])); + LUT1 #( + .INIT(2'h2)) + i_17 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[4] [0])); + LUT1 #( + .INIT(2'h2)) + i_18 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[3] [1])); + LUT1 #( + .INIT(2'h2)) + i_19 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[3] [0])); + LUT1 #( + .INIT(2'h2)) + i_2 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[0] [0])); + LUT1 #( + .INIT(2'h2)) + i_20 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[2] [1])); + LUT1 #( + .INIT(2'h2)) + i_21 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[2] [0])); + LUT1 #( + .INIT(2'h2)) + i_22 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[1] [1])); + LUT1 #( + .INIT(2'h2)) + i_23 + (.I0(1'b0), + .O(\TRACE_DATA_PIPE[1] [0])); + LUT1 #( + .INIT(2'h2)) + i_3 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[7] )); + LUT1 #( + .INIT(2'h2)) + i_4 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[6] )); + LUT1 #( + .INIT(2'h2)) + i_5 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[5] )); + LUT1 #( + .INIT(2'h2)) + i_6 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[4] )); + LUT1 #( + .INIT(2'h2)) + i_7 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[3] )); + LUT1 #( + .INIT(2'h2)) + i_8 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[2] )); + LUT1 #( + .INIT(2'h2)) + i_9 + (.I0(1'b0), + .O(\TRACE_CTL_PIPE[1] )); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/4c407e6cdd36e680/mz_petalinux_processing_system7_0_0_sim_netlist.vhdl b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/4c407e6cdd36e680/mz_petalinux_processing_system7_0_0_sim_netlist.vhdl new file mode 100755 index 0000000000000000000000000000000000000000..73ba2a302ec5341f2dbee3f1003227a44697c2c0 --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/4c407e6cdd36e680/mz_petalinux_processing_system7_0_0_sim_netlist.vhdl @@ -0,0 +1,4712 @@ +-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 +-- Date : Sun Oct 20 22:43:57 2019 +-- Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS +-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mz_petalinux_processing_system7_0_0_sim_netlist.vhdl +-- Design : mz_petalinux_processing_system7_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z010clg400-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is + port ( + CAN0_PHY_TX : out STD_LOGIC; + CAN0_PHY_RX : in STD_LOGIC; + CAN1_PHY_TX : out STD_LOGIC; + CAN1_PHY_RX : in STD_LOGIC; + ENET0_GMII_TX_EN : out STD_LOGIC; + ENET0_GMII_TX_ER : out STD_LOGIC; + ENET0_MDIO_MDC : out STD_LOGIC; + ENET0_MDIO_O : out STD_LOGIC; + ENET0_MDIO_T : out STD_LOGIC; + ENET0_PTP_DELAY_REQ_RX : out STD_LOGIC; + ENET0_PTP_DELAY_REQ_TX : out STD_LOGIC; + ENET0_PTP_PDELAY_REQ_RX : out STD_LOGIC; + ENET0_PTP_PDELAY_REQ_TX : out STD_LOGIC; + ENET0_PTP_PDELAY_RESP_RX : out STD_LOGIC; + ENET0_PTP_PDELAY_RESP_TX : out STD_LOGIC; + ENET0_PTP_SYNC_FRAME_RX : out STD_LOGIC; + ENET0_PTP_SYNC_FRAME_TX : out STD_LOGIC; + ENET0_SOF_RX : out STD_LOGIC; + ENET0_SOF_TX : out STD_LOGIC; + ENET0_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 ); + ENET0_GMII_COL : in STD_LOGIC; + ENET0_GMII_CRS : in STD_LOGIC; + ENET0_GMII_RX_CLK : in STD_LOGIC; + ENET0_GMII_RX_DV : in STD_LOGIC; + ENET0_GMII_RX_ER : in STD_LOGIC; + ENET0_GMII_TX_CLK : in STD_LOGIC; + ENET0_MDIO_I : in STD_LOGIC; + ENET0_EXT_INTIN : in STD_LOGIC; + ENET0_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 ); + ENET1_GMII_TX_EN : out STD_LOGIC; + ENET1_GMII_TX_ER : out STD_LOGIC; + ENET1_MDIO_MDC : out STD_LOGIC; + ENET1_MDIO_O : out STD_LOGIC; + ENET1_MDIO_T : out STD_LOGIC; + ENET1_PTP_DELAY_REQ_RX : out STD_LOGIC; + ENET1_PTP_DELAY_REQ_TX : out STD_LOGIC; + ENET1_PTP_PDELAY_REQ_RX : out STD_LOGIC; + ENET1_PTP_PDELAY_REQ_TX : out STD_LOGIC; + ENET1_PTP_PDELAY_RESP_RX : out STD_LOGIC; + ENET1_PTP_PDELAY_RESP_TX : out STD_LOGIC; + ENET1_PTP_SYNC_FRAME_RX : out STD_LOGIC; + ENET1_PTP_SYNC_FRAME_TX : out STD_LOGIC; + ENET1_SOF_RX : out STD_LOGIC; + ENET1_SOF_TX : out STD_LOGIC; + ENET1_GMII_TXD : out STD_LOGIC_VECTOR ( 7 downto 0 ); + ENET1_GMII_COL : in STD_LOGIC; + ENET1_GMII_CRS : in STD_LOGIC; + ENET1_GMII_RX_CLK : in STD_LOGIC; + ENET1_GMII_RX_DV : in STD_LOGIC; + ENET1_GMII_RX_ER : in STD_LOGIC; + ENET1_GMII_TX_CLK : in STD_LOGIC; + ENET1_MDIO_I : in STD_LOGIC; + ENET1_EXT_INTIN : in STD_LOGIC; + ENET1_GMII_RXD : in STD_LOGIC_VECTOR ( 7 downto 0 ); + GPIO_I : in STD_LOGIC_VECTOR ( 63 downto 0 ); + GPIO_O : out STD_LOGIC_VECTOR ( 63 downto 0 ); + GPIO_T : out STD_LOGIC_VECTOR ( 63 downto 0 ); + I2C0_SDA_I : in STD_LOGIC; + I2C0_SDA_O : out STD_LOGIC; + I2C0_SDA_T : out STD_LOGIC; + I2C0_SCL_I : in STD_LOGIC; + I2C0_SCL_O : out STD_LOGIC; + I2C0_SCL_T : out STD_LOGIC; + I2C1_SDA_I : in STD_LOGIC; + I2C1_SDA_O : out STD_LOGIC; + I2C1_SDA_T : out STD_LOGIC; + I2C1_SCL_I : in STD_LOGIC; + I2C1_SCL_O : out STD_LOGIC; + I2C1_SCL_T : out STD_LOGIC; + PJTAG_TCK : in STD_LOGIC; + PJTAG_TMS : in STD_LOGIC; + PJTAG_TDI : in STD_LOGIC; + PJTAG_TDO : out STD_LOGIC; + SDIO0_CLK : out STD_LOGIC; + SDIO0_CLK_FB : in STD_LOGIC; + SDIO0_CMD_O : out STD_LOGIC; + SDIO0_CMD_I : in STD_LOGIC; + SDIO0_CMD_T : out STD_LOGIC; + SDIO0_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 ); + SDIO0_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 ); + SDIO0_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 ); + SDIO0_LED : out STD_LOGIC; + SDIO0_CDN : in STD_LOGIC; + SDIO0_WP : in STD_LOGIC; + SDIO0_BUSPOW : out STD_LOGIC; + SDIO0_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + SDIO1_CLK : out STD_LOGIC; + SDIO1_CLK_FB : in STD_LOGIC; + SDIO1_CMD_O : out STD_LOGIC; + SDIO1_CMD_I : in STD_LOGIC; + SDIO1_CMD_T : out STD_LOGIC; + SDIO1_DATA_I : in STD_LOGIC_VECTOR ( 3 downto 0 ); + SDIO1_DATA_O : out STD_LOGIC_VECTOR ( 3 downto 0 ); + SDIO1_DATA_T : out STD_LOGIC_VECTOR ( 3 downto 0 ); + SDIO1_LED : out STD_LOGIC; + SDIO1_CDN : in STD_LOGIC; + SDIO1_WP : in STD_LOGIC; + SDIO1_BUSPOW : out STD_LOGIC; + SDIO1_BUSVOLT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + SPI0_SCLK_I : in STD_LOGIC; + SPI0_SCLK_O : out STD_LOGIC; + SPI0_SCLK_T : out STD_LOGIC; + SPI0_MOSI_I : in STD_LOGIC; + SPI0_MOSI_O : out STD_LOGIC; + SPI0_MOSI_T : out STD_LOGIC; + SPI0_MISO_I : in STD_LOGIC; + SPI0_MISO_O : out STD_LOGIC; + SPI0_MISO_T : out STD_LOGIC; + SPI0_SS_I : in STD_LOGIC; + SPI0_SS_O : out STD_LOGIC; + SPI0_SS1_O : out STD_LOGIC; + SPI0_SS2_O : out STD_LOGIC; + SPI0_SS_T : out STD_LOGIC; + SPI1_SCLK_I : in STD_LOGIC; + SPI1_SCLK_O : out STD_LOGIC; + SPI1_SCLK_T : out STD_LOGIC; + SPI1_MOSI_I : in STD_LOGIC; + SPI1_MOSI_O : out STD_LOGIC; + SPI1_MOSI_T : out STD_LOGIC; + SPI1_MISO_I : in STD_LOGIC; + SPI1_MISO_O : out STD_LOGIC; + SPI1_MISO_T : out STD_LOGIC; + SPI1_SS_I : in STD_LOGIC; + SPI1_SS_O : out STD_LOGIC; + SPI1_SS1_O : out STD_LOGIC; + SPI1_SS2_O : out STD_LOGIC; + SPI1_SS_T : out STD_LOGIC; + UART0_DTRN : out STD_LOGIC; + UART0_RTSN : out STD_LOGIC; + UART0_TX : out STD_LOGIC; + UART0_CTSN : in STD_LOGIC; + UART0_DCDN : in STD_LOGIC; + UART0_DSRN : in STD_LOGIC; + UART0_RIN : in STD_LOGIC; + UART0_RX : in STD_LOGIC; + UART1_DTRN : out STD_LOGIC; + UART1_RTSN : out STD_LOGIC; + UART1_TX : out STD_LOGIC; + UART1_CTSN : in STD_LOGIC; + UART1_DCDN : in STD_LOGIC; + UART1_DSRN : in STD_LOGIC; + UART1_RIN : in STD_LOGIC; + UART1_RX : in STD_LOGIC; + TTC0_WAVE0_OUT : out STD_LOGIC; + TTC0_WAVE1_OUT : out STD_LOGIC; + TTC0_WAVE2_OUT : out STD_LOGIC; + TTC0_CLK0_IN : in STD_LOGIC; + TTC0_CLK1_IN : in STD_LOGIC; + TTC0_CLK2_IN : in STD_LOGIC; + TTC1_WAVE0_OUT : out STD_LOGIC; + TTC1_WAVE1_OUT : out STD_LOGIC; + TTC1_WAVE2_OUT : out STD_LOGIC; + TTC1_CLK0_IN : in STD_LOGIC; + TTC1_CLK1_IN : in STD_LOGIC; + TTC1_CLK2_IN : in STD_LOGIC; + WDT_CLK_IN : in STD_LOGIC; + WDT_RST_OUT : out STD_LOGIC; + TRACE_CLK : in STD_LOGIC; + TRACE_CTL : out STD_LOGIC; + TRACE_DATA : out STD_LOGIC_VECTOR ( 1 downto 0 ); + TRACE_CLK_OUT : out STD_LOGIC; + USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); + USB0_VBUS_PWRSELECT : out STD_LOGIC; + USB0_VBUS_PWRFAULT : in STD_LOGIC; + USB1_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); + USB1_VBUS_PWRSELECT : out STD_LOGIC; + USB1_VBUS_PWRFAULT : in STD_LOGIC; + SRAM_INTIN : in STD_LOGIC; + M_AXI_GP0_ARESETN : out STD_LOGIC; + M_AXI_GP0_ARVALID : out STD_LOGIC; + M_AXI_GP0_AWVALID : out STD_LOGIC; + M_AXI_GP0_BREADY : out STD_LOGIC; + M_AXI_GP0_RREADY : out STD_LOGIC; + M_AXI_GP0_WLAST : out STD_LOGIC; + M_AXI_GP0_WVALID : out STD_LOGIC; + M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_ACLK : in STD_LOGIC; + M_AXI_GP0_ARREADY : in STD_LOGIC; + M_AXI_GP0_AWREADY : in STD_LOGIC; + M_AXI_GP0_BVALID : in STD_LOGIC; + M_AXI_GP0_RLAST : in STD_LOGIC; + M_AXI_GP0_RVALID : in STD_LOGIC; + M_AXI_GP0_WREADY : in STD_LOGIC; + M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP1_ARESETN : out STD_LOGIC; + M_AXI_GP1_ARVALID : out STD_LOGIC; + M_AXI_GP1_AWVALID : out STD_LOGIC; + M_AXI_GP1_BREADY : out STD_LOGIC; + M_AXI_GP1_RREADY : out STD_LOGIC; + M_AXI_GP1_WLAST : out STD_LOGIC; + M_AXI_GP1_WVALID : out STD_LOGIC; + M_AXI_GP1_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP1_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP1_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP1_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP1_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP1_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP1_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP1_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP1_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP1_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP1_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP1_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP1_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP1_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP1_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP1_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP1_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP1_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP1_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP1_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP1_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP1_ACLK : in STD_LOGIC; + M_AXI_GP1_ARREADY : in STD_LOGIC; + M_AXI_GP1_AWREADY : in STD_LOGIC; + M_AXI_GP1_BVALID : in STD_LOGIC; + M_AXI_GP1_RLAST : in STD_LOGIC; + M_AXI_GP1_RVALID : in STD_LOGIC; + M_AXI_GP1_WREADY : in STD_LOGIC; + M_AXI_GP1_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP1_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP1_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP1_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP1_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_GP0_ARESETN : out STD_LOGIC; + S_AXI_GP0_ARREADY : out STD_LOGIC; + S_AXI_GP0_AWREADY : out STD_LOGIC; + S_AXI_GP0_BVALID : out STD_LOGIC; + S_AXI_GP0_RLAST : out STD_LOGIC; + S_AXI_GP0_RVALID : out STD_LOGIC; + S_AXI_GP0_WREADY : out STD_LOGIC; + S_AXI_GP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP0_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_GP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_GP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_GP0_ACLK : in STD_LOGIC; + S_AXI_GP0_ARVALID : in STD_LOGIC; + S_AXI_GP0_AWVALID : in STD_LOGIC; + S_AXI_GP0_BREADY : in STD_LOGIC; + S_AXI_GP0_RREADY : in STD_LOGIC; + S_AXI_GP0_WLAST : in STD_LOGIC; + S_AXI_GP0_WVALID : in STD_LOGIC; + S_AXI_GP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_GP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_GP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_GP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_GP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_GP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_GP0_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_GP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP0_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_GP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_GP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_GP1_ARESETN : out STD_LOGIC; + S_AXI_GP1_ARREADY : out STD_LOGIC; + S_AXI_GP1_AWREADY : out STD_LOGIC; + S_AXI_GP1_BVALID : out STD_LOGIC; + S_AXI_GP1_RLAST : out STD_LOGIC; + S_AXI_GP1_RVALID : out STD_LOGIC; + S_AXI_GP1_WREADY : out STD_LOGIC; + S_AXI_GP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP1_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_GP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_GP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_GP1_ACLK : in STD_LOGIC; + S_AXI_GP1_ARVALID : in STD_LOGIC; + S_AXI_GP1_AWVALID : in STD_LOGIC; + S_AXI_GP1_BREADY : in STD_LOGIC; + S_AXI_GP1_RREADY : in STD_LOGIC; + S_AXI_GP1_WLAST : in STD_LOGIC; + S_AXI_GP1_WVALID : in STD_LOGIC; + S_AXI_GP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_GP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_GP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_GP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_GP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_GP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_GP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_GP1_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_GP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP1_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_GP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_GP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_GP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_ACP_ARESETN : out STD_LOGIC; + S_AXI_ACP_ARREADY : out STD_LOGIC; + S_AXI_ACP_AWREADY : out STD_LOGIC; + S_AXI_ACP_BVALID : out STD_LOGIC; + S_AXI_ACP_RLAST : out STD_LOGIC; + S_AXI_ACP_RVALID : out STD_LOGIC; + S_AXI_ACP_WREADY : out STD_LOGIC; + S_AXI_ACP_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_BID : out STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_RID : out STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_ACP_ACLK : in STD_LOGIC; + S_AXI_ACP_ARVALID : in STD_LOGIC; + S_AXI_ACP_AWVALID : in STD_LOGIC; + S_AXI_ACP_BREADY : in STD_LOGIC; + S_AXI_ACP_RREADY : in STD_LOGIC; + S_AXI_ACP_WLAST : in STD_LOGIC; + S_AXI_ACP_WVALID : in STD_LOGIC; + S_AXI_ACP_ARID : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_AWID : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_WID : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_ACP_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_ACP_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_ACP_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_ACP_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_ACP_ARUSER : in STD_LOGIC_VECTOR ( 4 downto 0 ); + S_AXI_ACP_AWUSER : in STD_LOGIC_VECTOR ( 4 downto 0 ); + S_AXI_ACP_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_ACP_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP0_ARESETN : out STD_LOGIC; + S_AXI_HP0_ARREADY : out STD_LOGIC; + S_AXI_HP0_AWREADY : out STD_LOGIC; + S_AXI_HP0_BVALID : out STD_LOGIC; + S_AXI_HP0_RLAST : out STD_LOGIC; + S_AXI_HP0_RVALID : out STD_LOGIC; + S_AXI_HP0_WREADY : out STD_LOGIC; + S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_ACLK : in STD_LOGIC; + S_AXI_HP0_ARVALID : in STD_LOGIC; + S_AXI_HP0_AWVALID : in STD_LOGIC; + S_AXI_HP0_BREADY : in STD_LOGIC; + S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC; + S_AXI_HP0_RREADY : in STD_LOGIC; + S_AXI_HP0_WLAST : in STD_LOGIC; + S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC; + S_AXI_HP0_WVALID : in STD_LOGIC; + S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP1_ARESETN : out STD_LOGIC; + S_AXI_HP1_ARREADY : out STD_LOGIC; + S_AXI_HP1_AWREADY : out STD_LOGIC; + S_AXI_HP1_BVALID : out STD_LOGIC; + S_AXI_HP1_RLAST : out STD_LOGIC; + S_AXI_HP1_RVALID : out STD_LOGIC; + S_AXI_HP1_WREADY : out STD_LOGIC; + S_AXI_HP1_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP1_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP1_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP1_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP1_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_HP1_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP1_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP1_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP1_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP1_ACLK : in STD_LOGIC; + S_AXI_HP1_ARVALID : in STD_LOGIC; + S_AXI_HP1_AWVALID : in STD_LOGIC; + S_AXI_HP1_BREADY : in STD_LOGIC; + S_AXI_HP1_RDISSUECAP1_EN : in STD_LOGIC; + S_AXI_HP1_RREADY : in STD_LOGIC; + S_AXI_HP1_WLAST : in STD_LOGIC; + S_AXI_HP1_WRISSUECAP1_EN : in STD_LOGIC; + S_AXI_HP1_WVALID : in STD_LOGIC; + S_AXI_HP1_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP1_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP1_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP1_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP1_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP1_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP1_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP1_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP1_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_HP1_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_HP1_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP1_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP1_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP1_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP1_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP1_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP1_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP1_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP1_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP1_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_HP1_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP2_ARESETN : out STD_LOGIC; + S_AXI_HP2_ARREADY : out STD_LOGIC; + S_AXI_HP2_AWREADY : out STD_LOGIC; + S_AXI_HP2_BVALID : out STD_LOGIC; + S_AXI_HP2_RLAST : out STD_LOGIC; + S_AXI_HP2_RVALID : out STD_LOGIC; + S_AXI_HP2_WREADY : out STD_LOGIC; + S_AXI_HP2_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP2_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP2_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP2_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP2_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_HP2_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP2_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP2_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP2_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP2_ACLK : in STD_LOGIC; + S_AXI_HP2_ARVALID : in STD_LOGIC; + S_AXI_HP2_AWVALID : in STD_LOGIC; + S_AXI_HP2_BREADY : in STD_LOGIC; + S_AXI_HP2_RDISSUECAP1_EN : in STD_LOGIC; + S_AXI_HP2_RREADY : in STD_LOGIC; + S_AXI_HP2_WLAST : in STD_LOGIC; + S_AXI_HP2_WRISSUECAP1_EN : in STD_LOGIC; + S_AXI_HP2_WVALID : in STD_LOGIC; + S_AXI_HP2_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP2_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP2_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP2_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP2_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP2_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP2_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP2_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP2_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_HP2_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_HP2_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP2_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP2_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP2_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP2_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP2_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP2_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP2_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP2_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP2_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_HP2_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP3_ARESETN : out STD_LOGIC; + S_AXI_HP3_ARREADY : out STD_LOGIC; + S_AXI_HP3_AWREADY : out STD_LOGIC; + S_AXI_HP3_BVALID : out STD_LOGIC; + S_AXI_HP3_RLAST : out STD_LOGIC; + S_AXI_HP3_RVALID : out STD_LOGIC; + S_AXI_HP3_WREADY : out STD_LOGIC; + S_AXI_HP3_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP3_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP3_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP3_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP3_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_HP3_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP3_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP3_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP3_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP3_ACLK : in STD_LOGIC; + S_AXI_HP3_ARVALID : in STD_LOGIC; + S_AXI_HP3_AWVALID : in STD_LOGIC; + S_AXI_HP3_BREADY : in STD_LOGIC; + S_AXI_HP3_RDISSUECAP1_EN : in STD_LOGIC; + S_AXI_HP3_RREADY : in STD_LOGIC; + S_AXI_HP3_WLAST : in STD_LOGIC; + S_AXI_HP3_WRISSUECAP1_EN : in STD_LOGIC; + S_AXI_HP3_WVALID : in STD_LOGIC; + S_AXI_HP3_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP3_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP3_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP3_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP3_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP3_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP3_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP3_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP3_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_HP3_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_HP3_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP3_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP3_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP3_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP3_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP3_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP3_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP3_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP3_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP3_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_HP3_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); + IRQ_P2F_DMAC_ABORT : out STD_LOGIC; + IRQ_P2F_DMAC0 : out STD_LOGIC; + IRQ_P2F_DMAC1 : out STD_LOGIC; + IRQ_P2F_DMAC2 : out STD_LOGIC; + IRQ_P2F_DMAC3 : out STD_LOGIC; + IRQ_P2F_DMAC4 : out STD_LOGIC; + IRQ_P2F_DMAC5 : out STD_LOGIC; + IRQ_P2F_DMAC6 : out STD_LOGIC; + IRQ_P2F_DMAC7 : out STD_LOGIC; + IRQ_P2F_SMC : out STD_LOGIC; + IRQ_P2F_QSPI : out STD_LOGIC; + IRQ_P2F_CTI : out STD_LOGIC; + IRQ_P2F_GPIO : out STD_LOGIC; + IRQ_P2F_USB0 : out STD_LOGIC; + IRQ_P2F_ENET0 : out STD_LOGIC; + IRQ_P2F_ENET_WAKE0 : out STD_LOGIC; + IRQ_P2F_SDIO0 : out STD_LOGIC; + IRQ_P2F_I2C0 : out STD_LOGIC; + IRQ_P2F_SPI0 : out STD_LOGIC; + IRQ_P2F_UART0 : out STD_LOGIC; + IRQ_P2F_CAN0 : out STD_LOGIC; + IRQ_P2F_USB1 : out STD_LOGIC; + IRQ_P2F_ENET1 : out STD_LOGIC; + IRQ_P2F_ENET_WAKE1 : out STD_LOGIC; + IRQ_P2F_SDIO1 : out STD_LOGIC; + IRQ_P2F_I2C1 : out STD_LOGIC; + IRQ_P2F_SPI1 : out STD_LOGIC; + IRQ_P2F_UART1 : out STD_LOGIC; + IRQ_P2F_CAN1 : out STD_LOGIC; + IRQ_F2P : in STD_LOGIC_VECTOR ( 1 downto 0 ); + Core0_nFIQ : in STD_LOGIC; + Core0_nIRQ : in STD_LOGIC; + Core1_nFIQ : in STD_LOGIC; + Core1_nIRQ : in STD_LOGIC; + DMA0_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); + DMA0_DAVALID : out STD_LOGIC; + DMA0_DRREADY : out STD_LOGIC; + DMA0_RSTN : out STD_LOGIC; + DMA1_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); + DMA1_DAVALID : out STD_LOGIC; + DMA1_DRREADY : out STD_LOGIC; + DMA1_RSTN : out STD_LOGIC; + DMA2_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); + DMA2_DAVALID : out STD_LOGIC; + DMA2_DRREADY : out STD_LOGIC; + DMA2_RSTN : out STD_LOGIC; + DMA3_DATYPE : out STD_LOGIC_VECTOR ( 1 downto 0 ); + DMA3_DAVALID : out STD_LOGIC; + DMA3_DRREADY : out STD_LOGIC; + DMA3_RSTN : out STD_LOGIC; + DMA0_ACLK : in STD_LOGIC; + DMA0_DAREADY : in STD_LOGIC; + DMA0_DRLAST : in STD_LOGIC; + DMA0_DRVALID : in STD_LOGIC; + DMA1_ACLK : in STD_LOGIC; + DMA1_DAREADY : in STD_LOGIC; + DMA1_DRLAST : in STD_LOGIC; + DMA1_DRVALID : in STD_LOGIC; + DMA2_ACLK : in STD_LOGIC; + DMA2_DAREADY : in STD_LOGIC; + DMA2_DRLAST : in STD_LOGIC; + DMA2_DRVALID : in STD_LOGIC; + DMA3_ACLK : in STD_LOGIC; + DMA3_DAREADY : in STD_LOGIC; + DMA3_DRLAST : in STD_LOGIC; + DMA3_DRVALID : in STD_LOGIC; + DMA0_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); + DMA1_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); + DMA2_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); + DMA3_DRTYPE : in STD_LOGIC_VECTOR ( 1 downto 0 ); + FCLK_CLK3 : out STD_LOGIC; + FCLK_CLK2 : out STD_LOGIC; + FCLK_CLK1 : out STD_LOGIC; + FCLK_CLK0 : out STD_LOGIC; + FCLK_CLKTRIG3_N : in STD_LOGIC; + FCLK_CLKTRIG2_N : in STD_LOGIC; + FCLK_CLKTRIG1_N : in STD_LOGIC; + FCLK_CLKTRIG0_N : in STD_LOGIC; + FCLK_RESET3_N : out STD_LOGIC; + FCLK_RESET2_N : out STD_LOGIC; + FCLK_RESET1_N : out STD_LOGIC; + FCLK_RESET0_N : out STD_LOGIC; + FTMD_TRACEIN_DATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + FTMD_TRACEIN_VALID : in STD_LOGIC; + FTMD_TRACEIN_CLK : in STD_LOGIC; + FTMD_TRACEIN_ATID : in STD_LOGIC_VECTOR ( 3 downto 0 ); + FTMT_F2P_TRIG_0 : in STD_LOGIC; + FTMT_F2P_TRIGACK_0 : out STD_LOGIC; + FTMT_F2P_TRIG_1 : in STD_LOGIC; + FTMT_F2P_TRIGACK_1 : out STD_LOGIC; + FTMT_F2P_TRIG_2 : in STD_LOGIC; + FTMT_F2P_TRIGACK_2 : out STD_LOGIC; + FTMT_F2P_TRIG_3 : in STD_LOGIC; + FTMT_F2P_TRIGACK_3 : out STD_LOGIC; + FTMT_F2P_DEBUG : in STD_LOGIC_VECTOR ( 31 downto 0 ); + FTMT_P2F_TRIGACK_0 : in STD_LOGIC; + FTMT_P2F_TRIG_0 : out STD_LOGIC; + FTMT_P2F_TRIGACK_1 : in STD_LOGIC; + FTMT_P2F_TRIG_1 : out STD_LOGIC; + FTMT_P2F_TRIGACK_2 : in STD_LOGIC; + FTMT_P2F_TRIG_2 : out STD_LOGIC; + FTMT_P2F_TRIGACK_3 : in STD_LOGIC; + FTMT_P2F_TRIG_3 : out STD_LOGIC; + FTMT_P2F_DEBUG : out STD_LOGIC_VECTOR ( 31 downto 0 ); + FPGA_IDLE_N : in STD_LOGIC; + EVENT_EVENTO : out STD_LOGIC; + EVENT_STANDBYWFE : out STD_LOGIC_VECTOR ( 1 downto 0 ); + EVENT_STANDBYWFI : out STD_LOGIC_VECTOR ( 1 downto 0 ); + EVENT_EVENTI : in STD_LOGIC; + DDR_ARB : in STD_LOGIC_VECTOR ( 3 downto 0 ); + MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); + DDR_CAS_n : inout STD_LOGIC; + DDR_CKE : inout STD_LOGIC; + DDR_Clk_n : inout STD_LOGIC; + DDR_Clk : inout STD_LOGIC; + DDR_CS_n : inout STD_LOGIC; + DDR_DRSTB : inout STD_LOGIC; + DDR_ODT : inout STD_LOGIC; + DDR_RAS_n : inout STD_LOGIC; + DDR_WEB : inout STD_LOGIC; + DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); + DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); + DDR_VRN : inout STD_LOGIC; + DDR_VRP : inout STD_LOGIC; + DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); + DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + PS_SRSTB : inout STD_LOGIC; + PS_CLK : inout STD_LOGIC; + PS_PORB : inout STD_LOGIC + ); + attribute C_DM_WIDTH : integer; + attribute C_DM_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4; + attribute C_DQS_WIDTH : integer; + attribute C_DQS_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 4; + attribute C_DQ_WIDTH : integer; + attribute C_DQ_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 32; + attribute C_EMIO_GPIO_WIDTH : integer; + attribute C_EMIO_GPIO_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; + attribute C_EN_EMIO_ENET0 : integer; + attribute C_EN_EMIO_ENET0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_EN_EMIO_ENET1 : integer; + attribute C_EN_EMIO_ENET1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_EN_EMIO_PJTAG : integer; + attribute C_EN_EMIO_PJTAG of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_EN_EMIO_TRACE : integer; + attribute C_EN_EMIO_TRACE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_FCLK_CLK0_BUF : string; + attribute C_FCLK_CLK0_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "TRUE"; + attribute C_FCLK_CLK1_BUF : string; + attribute C_FCLK_CLK1_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE"; + attribute C_FCLK_CLK2_BUF : string; + attribute C_FCLK_CLK2_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE"; + attribute C_FCLK_CLK3_BUF : string; + attribute C_FCLK_CLK3_BUF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "FALSE"; + attribute C_GP0_EN_MODIFIABLE_TXN : integer; + attribute C_GP0_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; + attribute C_GP1_EN_MODIFIABLE_TXN : integer; + attribute C_GP1_EN_MODIFIABLE_TXN of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; + attribute C_INCLUDE_ACP_TRANS_CHECK : integer; + attribute C_INCLUDE_ACP_TRANS_CHECK of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_INCLUDE_TRACE_BUFFER : integer; + attribute C_INCLUDE_TRACE_BUFFER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_IRQ_F2P_MODE : string; + attribute C_IRQ_F2P_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "DIRECT"; + attribute C_MIO_PRIMITIVE : integer; + attribute C_MIO_PRIMITIVE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 54; + attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer; + attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_M_AXI_GP0_ID_WIDTH : integer; + attribute C_M_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; + attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer; + attribute C_M_AXI_GP0_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; + attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer; + attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_M_AXI_GP1_ID_WIDTH : integer; + attribute C_M_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; + attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer; + attribute C_M_AXI_GP1_THREAD_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; + attribute C_NUM_F2P_INTR_INPUTS : integer; + attribute C_NUM_F2P_INTR_INPUTS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 2; + attribute C_PACKAGE_NAME : string; + attribute C_PACKAGE_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "clg400"; + attribute C_PS7_SI_REV : string; + attribute C_PS7_SI_REV of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "PRODUCTION"; + attribute C_S_AXI_ACP_ARUSER_VAL : integer; + attribute C_S_AXI_ACP_ARUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31; + attribute C_S_AXI_ACP_AWUSER_VAL : integer; + attribute C_S_AXI_ACP_AWUSER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 31; + attribute C_S_AXI_ACP_ID_WIDTH : integer; + attribute C_S_AXI_ACP_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 3; + attribute C_S_AXI_GP0_ID_WIDTH : integer; + attribute C_S_AXI_GP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; + attribute C_S_AXI_GP1_ID_WIDTH : integer; + attribute C_S_AXI_GP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; + attribute C_S_AXI_HP0_DATA_WIDTH : integer; + attribute C_S_AXI_HP0_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; + attribute C_S_AXI_HP0_ID_WIDTH : integer; + attribute C_S_AXI_HP0_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; + attribute C_S_AXI_HP1_DATA_WIDTH : integer; + attribute C_S_AXI_HP1_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; + attribute C_S_AXI_HP1_ID_WIDTH : integer; + attribute C_S_AXI_HP1_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; + attribute C_S_AXI_HP2_DATA_WIDTH : integer; + attribute C_S_AXI_HP2_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; + attribute C_S_AXI_HP2_ID_WIDTH : integer; + attribute C_S_AXI_HP2_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; + attribute C_S_AXI_HP3_DATA_WIDTH : integer; + attribute C_S_AXI_HP3_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 64; + attribute C_S_AXI_HP3_ID_WIDTH : integer; + attribute C_S_AXI_HP3_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 6; + attribute C_TRACE_BUFFER_CLOCK_DELAY : integer; + attribute C_TRACE_BUFFER_CLOCK_DELAY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 12; + attribute C_TRACE_BUFFER_FIFO_SIZE : integer; + attribute C_TRACE_BUFFER_FIFO_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 128; + attribute C_TRACE_INTERNAL_WIDTH : integer; + attribute C_TRACE_INTERNAL_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 2; + attribute C_TRACE_PIPELINE_WIDTH : integer; + attribute C_TRACE_PIPELINE_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 8; + attribute C_USE_AXI_NONSECURE : integer; + attribute C_USE_AXI_NONSECURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_USE_DEFAULT_ACP_USER_VAL : integer; + attribute C_USE_DEFAULT_ACP_USER_VAL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_USE_M_AXI_GP0 : integer; + attribute C_USE_M_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; + attribute C_USE_M_AXI_GP1 : integer; + attribute C_USE_M_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_USE_S_AXI_ACP : integer; + attribute C_USE_S_AXI_ACP of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_USE_S_AXI_GP0 : integer; + attribute C_USE_S_AXI_GP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_USE_S_AXI_GP1 : integer; + attribute C_USE_S_AXI_GP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_USE_S_AXI_HP0 : integer; + attribute C_USE_S_AXI_HP0 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 1; + attribute C_USE_S_AXI_HP1 : integer; + attribute C_USE_S_AXI_HP1 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_USE_S_AXI_HP2 : integer; + attribute C_USE_S_AXI_HP2 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; + attribute C_USE_S_AXI_HP3 : integer; + attribute C_USE_S_AXI_HP3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; + attribute HW_HANDOFF : string; + attribute HW_HANDOFF of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "mz_petalinux_processing_system7_0_0.hwdef"; + attribute POWER : string; + attribute POWER of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is "/>"; + attribute USE_TRACE_DATA_EDGE_DETECTOR : integer; + attribute USE_TRACE_DATA_EDGE_DETECTOR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 : entity is 0; +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 is + signal \\ : STD_LOGIC; + signal \\ : STD_LOGIC; + signal ENET0_MDIO_T_n : STD_LOGIC; + signal ENET1_MDIO_T_n : STD_LOGIC; + signal FCLK_CLK_unbuffered : STD_LOGIC_VECTOR ( 0 to 0 ); + signal I2C0_SCL_T_n : STD_LOGIC; + signal I2C0_SDA_T_n : STD_LOGIC; + signal I2C1_SCL_T_n : STD_LOGIC; + signal I2C1_SDA_T_n : STD_LOGIC; + signal \^m_axi_gp0_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \^m_axi_gp0_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^m_axi_gp0_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \^m_axi_gp0_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^m_axi_gp1_arcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \^m_axi_gp1_arsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal \^m_axi_gp1_awcache\ : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal \^m_axi_gp1_awsize\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal SDIO0_CMD_T_n : STD_LOGIC; + signal SDIO0_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal SDIO1_CMD_T_n : STD_LOGIC; + signal SDIO1_DATA_T_n : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal SPI0_MISO_T_n : STD_LOGIC; + signal SPI0_MOSI_T_n : STD_LOGIC; + signal SPI0_SCLK_T_n : STD_LOGIC; + signal SPI0_SS_T_n : STD_LOGIC; + signal SPI1_MISO_T_n : STD_LOGIC; + signal SPI1_MOSI_T_n : STD_LOGIC; + signal SPI1_SCLK_T_n : STD_LOGIC; + signal SPI1_SS_T_n : STD_LOGIC; + signal \TRACE_CTL_PIPE[0]\ : STD_LOGIC; + attribute RTL_KEEP : string; + attribute RTL_KEEP of \TRACE_CTL_PIPE[0]\ : signal is "true"; + signal \TRACE_CTL_PIPE[1]\ : STD_LOGIC; + attribute RTL_KEEP of \TRACE_CTL_PIPE[1]\ : signal is "true"; + signal \TRACE_CTL_PIPE[2]\ : STD_LOGIC; + attribute RTL_KEEP of \TRACE_CTL_PIPE[2]\ : signal is "true"; + signal \TRACE_CTL_PIPE[3]\ : STD_LOGIC; + attribute RTL_KEEP of \TRACE_CTL_PIPE[3]\ : signal is "true"; + signal \TRACE_CTL_PIPE[4]\ : STD_LOGIC; + attribute RTL_KEEP of \TRACE_CTL_PIPE[4]\ : signal is "true"; + signal \TRACE_CTL_PIPE[5]\ : STD_LOGIC; + attribute RTL_KEEP of \TRACE_CTL_PIPE[5]\ : signal is "true"; + signal \TRACE_CTL_PIPE[6]\ : STD_LOGIC; + attribute RTL_KEEP of \TRACE_CTL_PIPE[6]\ : signal is "true"; + signal \TRACE_CTL_PIPE[7]\ : STD_LOGIC; + attribute RTL_KEEP of \TRACE_CTL_PIPE[7]\ : signal is "true"; + signal \TRACE_DATA_PIPE[0]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute RTL_KEEP of \TRACE_DATA_PIPE[0]\ : signal is "true"; + signal \TRACE_DATA_PIPE[1]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute RTL_KEEP of \TRACE_DATA_PIPE[1]\ : signal is "true"; + signal \TRACE_DATA_PIPE[2]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute RTL_KEEP of \TRACE_DATA_PIPE[2]\ : signal is "true"; + signal \TRACE_DATA_PIPE[3]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute RTL_KEEP of \TRACE_DATA_PIPE[3]\ : signal is "true"; + signal \TRACE_DATA_PIPE[4]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute RTL_KEEP of \TRACE_DATA_PIPE[4]\ : signal is "true"; + signal \TRACE_DATA_PIPE[5]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute RTL_KEEP of \TRACE_DATA_PIPE[5]\ : signal is "true"; + signal \TRACE_DATA_PIPE[6]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute RTL_KEEP of \TRACE_DATA_PIPE[6]\ : signal is "true"; + signal \TRACE_DATA_PIPE[7]\ : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute RTL_KEEP of \TRACE_DATA_PIPE[7]\ : signal is "true"; + signal buffered_DDR_Addr : STD_LOGIC_VECTOR ( 14 downto 0 ); + signal buffered_DDR_BankAddr : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal buffered_DDR_CAS_n : STD_LOGIC; + signal buffered_DDR_CKE : STD_LOGIC; + signal buffered_DDR_CS_n : STD_LOGIC; + signal buffered_DDR_Clk : STD_LOGIC; + signal buffered_DDR_Clk_n : STD_LOGIC; + signal buffered_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal buffered_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal buffered_DDR_DQS : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal buffered_DDR_DQS_n : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal buffered_DDR_DRSTB : STD_LOGIC; + signal buffered_DDR_ODT : STD_LOGIC; + signal buffered_DDR_RAS_n : STD_LOGIC; + signal buffered_DDR_VRN : STD_LOGIC; + signal buffered_DDR_VRP : STD_LOGIC; + signal buffered_DDR_WEB : STD_LOGIC; + signal buffered_MIO : STD_LOGIC_VECTOR ( 53 downto 0 ); + signal buffered_PS_CLK : STD_LOGIC; + signal buffered_PS_PORB : STD_LOGIC; + signal buffered_PS_SRSTB : STD_LOGIC; + signal gpio_out_t_n : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED : STD_LOGIC; + signal NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED : STD_LOGIC; + signal NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED : STD_LOGIC; + signal NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED : STD_LOGIC; + signal NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED : STD_LOGIC; + signal NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED : STD_LOGIC; + signal NLW_PS7_i_EMIOTRACECTL_UNCONNECTED : STD_LOGIC; + signal NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); + signal NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); + signal NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); + signal NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 ); + attribute BOX_TYPE : string; + attribute BOX_TYPE of DDR_CAS_n_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of DDR_CKE_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of DDR_CS_n_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of DDR_Clk_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of DDR_Clk_n_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of DDR_DRSTB_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of DDR_ODT_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of DDR_RAS_n_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of DDR_VRN_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of DDR_VRP_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of DDR_WEB_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of PS7_i : label is "PRIMITIVE"; + attribute BOX_TYPE of PS_CLK_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of PS_PORB_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of PS_SRSTB_BIBUF : label is "PRIMITIVE"; + attribute BOX_TYPE of \buffer_fclk_clk_0.FCLK_CLK_0_BUFG\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[0].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[10].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[11].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[12].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[13].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[14].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[15].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[16].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[17].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[18].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[19].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[1].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[20].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[21].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[22].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[23].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[24].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[25].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[26].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[27].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[28].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[29].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[2].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[30].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[31].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[32].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[33].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[34].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[35].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[36].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[37].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[38].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[39].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[3].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[40].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[41].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[42].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[43].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[44].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[45].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[46].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[47].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[48].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[49].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[4].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[50].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[51].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[52].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[53].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[5].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[6].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[7].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[8].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk13[9].MIO_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk14[0].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk14[1].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk14[2].DDR_BankAddr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[0].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[10].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[11].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[12].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[13].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[14].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[1].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[2].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[3].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[4].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[5].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[6].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[7].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[8].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk15[9].DDR_Addr_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk16[0].DDR_DM_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk16[1].DDR_DM_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk16[2].DDR_DM_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk16[3].DDR_DM_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[0].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[10].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[11].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[12].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[13].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[14].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[15].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[16].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[17].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[18].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[19].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[1].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[20].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[21].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[22].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[23].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[24].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[25].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[26].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[27].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[28].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[29].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[2].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[30].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[31].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[3].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[4].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[5].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[6].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[7].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[8].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk17[9].DDR_DQ_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk18[0].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk18[1].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk18[2].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk18[3].DDR_DQS_n_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk19[0].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk19[1].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk19[2].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; + attribute BOX_TYPE of \genblk19[3].DDR_DQS_BIBUF\ : label is "PRIMITIVE"; +begin + ENET0_GMII_TXD(7) <= \\; + ENET0_GMII_TXD(6) <= \\; + ENET0_GMII_TXD(5) <= \\; + ENET0_GMII_TXD(4) <= \\; + ENET0_GMII_TXD(3) <= \\; + ENET0_GMII_TXD(2) <= \\; + ENET0_GMII_TXD(1) <= \\; + ENET0_GMII_TXD(0) <= \\; + ENET0_GMII_TX_EN <= \\; + ENET0_GMII_TX_ER <= \\; + ENET1_GMII_TXD(7) <= \\; + ENET1_GMII_TXD(6) <= \\; + ENET1_GMII_TXD(5) <= \\; + ENET1_GMII_TXD(4) <= \\; + ENET1_GMII_TXD(3) <= \\; + ENET1_GMII_TXD(2) <= \\; + ENET1_GMII_TXD(1) <= \\; + ENET1_GMII_TXD(0) <= \\; + ENET1_GMII_TX_EN <= \\; + ENET1_GMII_TX_ER <= \\; + M_AXI_GP0_ARCACHE(3 downto 2) <= \^m_axi_gp0_arcache\(3 downto 2); + M_AXI_GP0_ARCACHE(1) <= \\; + M_AXI_GP0_ARCACHE(0) <= \^m_axi_gp0_arcache\(0); + M_AXI_GP0_ARSIZE(2) <= \\; + M_AXI_GP0_ARSIZE(1 downto 0) <= \^m_axi_gp0_arsize\(1 downto 0); + M_AXI_GP0_AWCACHE(3 downto 2) <= \^m_axi_gp0_awcache\(3 downto 2); + M_AXI_GP0_AWCACHE(1) <= \\; + M_AXI_GP0_AWCACHE(0) <= \^m_axi_gp0_awcache\(0); + M_AXI_GP0_AWSIZE(2) <= \\; + M_AXI_GP0_AWSIZE(1 downto 0) <= \^m_axi_gp0_awsize\(1 downto 0); + M_AXI_GP1_ARCACHE(3 downto 2) <= \^m_axi_gp1_arcache\(3 downto 2); + M_AXI_GP1_ARCACHE(1) <= \\; + M_AXI_GP1_ARCACHE(0) <= \^m_axi_gp1_arcache\(0); + M_AXI_GP1_ARSIZE(2) <= \\; + M_AXI_GP1_ARSIZE(1 downto 0) <= \^m_axi_gp1_arsize\(1 downto 0); + M_AXI_GP1_AWCACHE(3 downto 2) <= \^m_axi_gp1_awcache\(3 downto 2); + M_AXI_GP1_AWCACHE(1) <= \\; + M_AXI_GP1_AWCACHE(0) <= \^m_axi_gp1_awcache\(0); + M_AXI_GP1_AWSIZE(2) <= \\; + M_AXI_GP1_AWSIZE(1 downto 0) <= \^m_axi_gp1_awsize\(1 downto 0); + PJTAG_TDO <= \\; + TRACE_CLK_OUT <= \\; + TRACE_CTL <= \TRACE_CTL_PIPE[0]\; + TRACE_DATA(1 downto 0) <= \TRACE_DATA_PIPE[0]\(1 downto 0); +DDR_CAS_n_BIBUF: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_CAS_n, + PAD => DDR_CAS_n + ); +DDR_CKE_BIBUF: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_CKE, + PAD => DDR_CKE + ); +DDR_CS_n_BIBUF: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_CS_n, + PAD => DDR_CS_n + ); +DDR_Clk_BIBUF: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Clk, + PAD => DDR_Clk + ); +DDR_Clk_n_BIBUF: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Clk_n, + PAD => DDR_Clk_n + ); +DDR_DRSTB_BIBUF: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DRSTB, + PAD => DDR_DRSTB + ); +DDR_ODT_BIBUF: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_ODT, + PAD => DDR_ODT + ); +DDR_RAS_n_BIBUF: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_RAS_n, + PAD => DDR_RAS_n + ); +DDR_VRN_BIBUF: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_VRN, + PAD => DDR_VRN + ); +DDR_VRP_BIBUF: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_VRP, + PAD => DDR_VRP + ); +DDR_WEB_BIBUF: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_WEB, + PAD => DDR_WEB + ); +ENET0_MDIO_T_INST_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => ENET0_MDIO_T_n, + O => ENET0_MDIO_T + ); +ENET1_MDIO_T_INST_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => ENET1_MDIO_T_n, + O => ENET1_MDIO_T + ); +GND: unisim.vcomponents.GND + port map ( + G => \\ + ); +\GPIO_T[0]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(0), + O => GPIO_T(0) + ); +\GPIO_T[10]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(10), + O => GPIO_T(10) + ); +\GPIO_T[11]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(11), + O => GPIO_T(11) + ); +\GPIO_T[12]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(12), + O => GPIO_T(12) + ); +\GPIO_T[13]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(13), + O => GPIO_T(13) + ); +\GPIO_T[14]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(14), + O => GPIO_T(14) + ); +\GPIO_T[15]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(15), + O => GPIO_T(15) + ); +\GPIO_T[16]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(16), + O => GPIO_T(16) + ); +\GPIO_T[17]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(17), + O => GPIO_T(17) + ); +\GPIO_T[18]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(18), + O => GPIO_T(18) + ); +\GPIO_T[19]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(19), + O => GPIO_T(19) + ); +\GPIO_T[1]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(1), + O => GPIO_T(1) + ); +\GPIO_T[20]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(20), + O => GPIO_T(20) + ); +\GPIO_T[21]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(21), + O => GPIO_T(21) + ); +\GPIO_T[22]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(22), + O => GPIO_T(22) + ); +\GPIO_T[23]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(23), + O => GPIO_T(23) + ); +\GPIO_T[24]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(24), + O => GPIO_T(24) + ); +\GPIO_T[25]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(25), + O => GPIO_T(25) + ); +\GPIO_T[26]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(26), + O => GPIO_T(26) + ); +\GPIO_T[27]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(27), + O => GPIO_T(27) + ); +\GPIO_T[28]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(28), + O => GPIO_T(28) + ); +\GPIO_T[29]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(29), + O => GPIO_T(29) + ); +\GPIO_T[2]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(2), + O => GPIO_T(2) + ); +\GPIO_T[30]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(30), + O => GPIO_T(30) + ); +\GPIO_T[31]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(31), + O => GPIO_T(31) + ); +\GPIO_T[32]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(32), + O => GPIO_T(32) + ); +\GPIO_T[33]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(33), + O => GPIO_T(33) + ); +\GPIO_T[34]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(34), + O => GPIO_T(34) + ); +\GPIO_T[35]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(35), + O => GPIO_T(35) + ); +\GPIO_T[36]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(36), + O => GPIO_T(36) + ); +\GPIO_T[37]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(37), + O => GPIO_T(37) + ); +\GPIO_T[38]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(38), + O => GPIO_T(38) + ); +\GPIO_T[39]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(39), + O => GPIO_T(39) + ); +\GPIO_T[3]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(3), + O => GPIO_T(3) + ); +\GPIO_T[40]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(40), + O => GPIO_T(40) + ); +\GPIO_T[41]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(41), + O => GPIO_T(41) + ); +\GPIO_T[42]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(42), + O => GPIO_T(42) + ); +\GPIO_T[43]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(43), + O => GPIO_T(43) + ); +\GPIO_T[44]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(44), + O => GPIO_T(44) + ); +\GPIO_T[45]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(45), + O => GPIO_T(45) + ); +\GPIO_T[46]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(46), + O => GPIO_T(46) + ); +\GPIO_T[47]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(47), + O => GPIO_T(47) + ); +\GPIO_T[48]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(48), + O => GPIO_T(48) + ); +\GPIO_T[49]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(49), + O => GPIO_T(49) + ); +\GPIO_T[4]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(4), + O => GPIO_T(4) + ); +\GPIO_T[50]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(50), + O => GPIO_T(50) + ); +\GPIO_T[51]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(51), + O => GPIO_T(51) + ); +\GPIO_T[52]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(52), + O => GPIO_T(52) + ); +\GPIO_T[53]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(53), + O => GPIO_T(53) + ); +\GPIO_T[54]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(54), + O => GPIO_T(54) + ); +\GPIO_T[55]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(55), + O => GPIO_T(55) + ); +\GPIO_T[56]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(56), + O => GPIO_T(56) + ); +\GPIO_T[57]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(57), + O => GPIO_T(57) + ); +\GPIO_T[58]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(58), + O => GPIO_T(58) + ); +\GPIO_T[59]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(59), + O => GPIO_T(59) + ); +\GPIO_T[5]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(5), + O => GPIO_T(5) + ); +\GPIO_T[60]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(60), + O => GPIO_T(60) + ); +\GPIO_T[61]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(61), + O => GPIO_T(61) + ); +\GPIO_T[62]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(62), + O => GPIO_T(62) + ); +\GPIO_T[63]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(63), + O => GPIO_T(63) + ); +\GPIO_T[6]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(6), + O => GPIO_T(6) + ); +\GPIO_T[7]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(7), + O => GPIO_T(7) + ); +\GPIO_T[8]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(8), + O => GPIO_T(8) + ); +\GPIO_T[9]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => gpio_out_t_n(9), + O => GPIO_T(9) + ); +I2C0_SCL_T_INST_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => I2C0_SCL_T_n, + O => I2C0_SCL_T + ); +I2C0_SDA_T_INST_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => I2C0_SDA_T_n, + O => I2C0_SDA_T + ); +I2C1_SCL_T_INST_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => I2C1_SCL_T_n, + O => I2C1_SCL_T + ); +I2C1_SDA_T_INST_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => I2C1_SDA_T_n, + O => I2C1_SDA_T + ); +PS7_i: unisim.vcomponents.PS7 + port map ( + DDRA(14 downto 0) => buffered_DDR_Addr(14 downto 0), + DDRARB(3 downto 0) => DDR_ARB(3 downto 0), + DDRBA(2 downto 0) => buffered_DDR_BankAddr(2 downto 0), + DDRCASB => buffered_DDR_CAS_n, + DDRCKE => buffered_DDR_CKE, + DDRCKN => buffered_DDR_Clk_n, + DDRCKP => buffered_DDR_Clk, + DDRCSB => buffered_DDR_CS_n, + DDRDM(3 downto 0) => buffered_DDR_DM(3 downto 0), + DDRDQ(31 downto 0) => buffered_DDR_DQ(31 downto 0), + DDRDQSN(3 downto 0) => buffered_DDR_DQS_n(3 downto 0), + DDRDQSP(3 downto 0) => buffered_DDR_DQS(3 downto 0), + DDRDRSTB => buffered_DDR_DRSTB, + DDRODT => buffered_DDR_ODT, + DDRRASB => buffered_DDR_RAS_n, + DDRVRN => buffered_DDR_VRN, + DDRVRP => buffered_DDR_VRP, + DDRWEB => buffered_DDR_WEB, + DMA0ACLK => DMA0_ACLK, + DMA0DAREADY => DMA0_DAREADY, + DMA0DATYPE(1 downto 0) => DMA0_DATYPE(1 downto 0), + DMA0DAVALID => DMA0_DAVALID, + DMA0DRLAST => DMA0_DRLAST, + DMA0DRREADY => DMA0_DRREADY, + DMA0DRTYPE(1 downto 0) => DMA0_DRTYPE(1 downto 0), + DMA0DRVALID => DMA0_DRVALID, + DMA0RSTN => DMA0_RSTN, + DMA1ACLK => DMA1_ACLK, + DMA1DAREADY => DMA1_DAREADY, + DMA1DATYPE(1 downto 0) => DMA1_DATYPE(1 downto 0), + DMA1DAVALID => DMA1_DAVALID, + DMA1DRLAST => DMA1_DRLAST, + DMA1DRREADY => DMA1_DRREADY, + DMA1DRTYPE(1 downto 0) => DMA1_DRTYPE(1 downto 0), + DMA1DRVALID => DMA1_DRVALID, + DMA1RSTN => DMA1_RSTN, + DMA2ACLK => DMA2_ACLK, + DMA2DAREADY => DMA2_DAREADY, + DMA2DATYPE(1 downto 0) => DMA2_DATYPE(1 downto 0), + DMA2DAVALID => DMA2_DAVALID, + DMA2DRLAST => DMA2_DRLAST, + DMA2DRREADY => DMA2_DRREADY, + DMA2DRTYPE(1 downto 0) => DMA2_DRTYPE(1 downto 0), + DMA2DRVALID => DMA2_DRVALID, + DMA2RSTN => DMA2_RSTN, + DMA3ACLK => DMA3_ACLK, + DMA3DAREADY => DMA3_DAREADY, + DMA3DATYPE(1 downto 0) => DMA3_DATYPE(1 downto 0), + DMA3DAVALID => DMA3_DAVALID, + DMA3DRLAST => DMA3_DRLAST, + DMA3DRREADY => DMA3_DRREADY, + DMA3DRTYPE(1 downto 0) => DMA3_DRTYPE(1 downto 0), + DMA3DRVALID => DMA3_DRVALID, + DMA3RSTN => DMA3_RSTN, + EMIOCAN0PHYRX => CAN0_PHY_RX, + EMIOCAN0PHYTX => CAN0_PHY_TX, + EMIOCAN1PHYRX => CAN1_PHY_RX, + EMIOCAN1PHYTX => CAN1_PHY_TX, + EMIOENET0EXTINTIN => ENET0_EXT_INTIN, + EMIOENET0GMIICOL => '0', + EMIOENET0GMIICRS => '0', + EMIOENET0GMIIRXCLK => ENET0_GMII_RX_CLK, + EMIOENET0GMIIRXD(7 downto 0) => B"00000000", + EMIOENET0GMIIRXDV => '0', + EMIOENET0GMIIRXER => '0', + EMIOENET0GMIITXCLK => ENET0_GMII_TX_CLK, + EMIOENET0GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET0GMIITXD_UNCONNECTED(7 downto 0), + EMIOENET0GMIITXEN => NLW_PS7_i_EMIOENET0GMIITXEN_UNCONNECTED, + EMIOENET0GMIITXER => NLW_PS7_i_EMIOENET0GMIITXER_UNCONNECTED, + EMIOENET0MDIOI => ENET0_MDIO_I, + EMIOENET0MDIOMDC => ENET0_MDIO_MDC, + EMIOENET0MDIOO => ENET0_MDIO_O, + EMIOENET0MDIOTN => ENET0_MDIO_T_n, + EMIOENET0PTPDELAYREQRX => ENET0_PTP_DELAY_REQ_RX, + EMIOENET0PTPDELAYREQTX => ENET0_PTP_DELAY_REQ_TX, + EMIOENET0PTPPDELAYREQRX => ENET0_PTP_PDELAY_REQ_RX, + EMIOENET0PTPPDELAYREQTX => ENET0_PTP_PDELAY_REQ_TX, + EMIOENET0PTPPDELAYRESPRX => ENET0_PTP_PDELAY_RESP_RX, + EMIOENET0PTPPDELAYRESPTX => ENET0_PTP_PDELAY_RESP_TX, + EMIOENET0PTPSYNCFRAMERX => ENET0_PTP_SYNC_FRAME_RX, + EMIOENET0PTPSYNCFRAMETX => ENET0_PTP_SYNC_FRAME_TX, + EMIOENET0SOFRX => ENET0_SOF_RX, + EMIOENET0SOFTX => ENET0_SOF_TX, + EMIOENET1EXTINTIN => ENET1_EXT_INTIN, + EMIOENET1GMIICOL => '0', + EMIOENET1GMIICRS => '0', + EMIOENET1GMIIRXCLK => ENET1_GMII_RX_CLK, + EMIOENET1GMIIRXD(7 downto 0) => B"00000000", + EMIOENET1GMIIRXDV => '0', + EMIOENET1GMIIRXER => '0', + EMIOENET1GMIITXCLK => ENET1_GMII_TX_CLK, + EMIOENET1GMIITXD(7 downto 0) => NLW_PS7_i_EMIOENET1GMIITXD_UNCONNECTED(7 downto 0), + EMIOENET1GMIITXEN => NLW_PS7_i_EMIOENET1GMIITXEN_UNCONNECTED, + EMIOENET1GMIITXER => NLW_PS7_i_EMIOENET1GMIITXER_UNCONNECTED, + EMIOENET1MDIOI => ENET1_MDIO_I, + EMIOENET1MDIOMDC => ENET1_MDIO_MDC, + EMIOENET1MDIOO => ENET1_MDIO_O, + EMIOENET1MDIOTN => ENET1_MDIO_T_n, + EMIOENET1PTPDELAYREQRX => ENET1_PTP_DELAY_REQ_RX, + EMIOENET1PTPDELAYREQTX => ENET1_PTP_DELAY_REQ_TX, + EMIOENET1PTPPDELAYREQRX => ENET1_PTP_PDELAY_REQ_RX, + EMIOENET1PTPPDELAYREQTX => ENET1_PTP_PDELAY_REQ_TX, + EMIOENET1PTPPDELAYRESPRX => ENET1_PTP_PDELAY_RESP_RX, + EMIOENET1PTPPDELAYRESPTX => ENET1_PTP_PDELAY_RESP_TX, + EMIOENET1PTPSYNCFRAMERX => ENET1_PTP_SYNC_FRAME_RX, + EMIOENET1PTPSYNCFRAMETX => ENET1_PTP_SYNC_FRAME_TX, + EMIOENET1SOFRX => ENET1_SOF_RX, + EMIOENET1SOFTX => ENET1_SOF_TX, + EMIOGPIOI(63 downto 0) => GPIO_I(63 downto 0), + EMIOGPIOO(63 downto 0) => GPIO_O(63 downto 0), + EMIOGPIOTN(63 downto 0) => gpio_out_t_n(63 downto 0), + EMIOI2C0SCLI => I2C0_SCL_I, + EMIOI2C0SCLO => I2C0_SCL_O, + EMIOI2C0SCLTN => I2C0_SCL_T_n, + EMIOI2C0SDAI => I2C0_SDA_I, + EMIOI2C0SDAO => I2C0_SDA_O, + EMIOI2C0SDATN => I2C0_SDA_T_n, + EMIOI2C1SCLI => I2C1_SCL_I, + EMIOI2C1SCLO => I2C1_SCL_O, + EMIOI2C1SCLTN => I2C1_SCL_T_n, + EMIOI2C1SDAI => I2C1_SDA_I, + EMIOI2C1SDAO => I2C1_SDA_O, + EMIOI2C1SDATN => I2C1_SDA_T_n, + EMIOPJTAGTCK => PJTAG_TCK, + EMIOPJTAGTDI => PJTAG_TDI, + EMIOPJTAGTDO => NLW_PS7_i_EMIOPJTAGTDO_UNCONNECTED, + EMIOPJTAGTDTN => NLW_PS7_i_EMIOPJTAGTDTN_UNCONNECTED, + EMIOPJTAGTMS => PJTAG_TMS, + EMIOSDIO0BUSPOW => SDIO0_BUSPOW, + EMIOSDIO0BUSVOLT(2 downto 0) => SDIO0_BUSVOLT(2 downto 0), + EMIOSDIO0CDN => SDIO0_CDN, + EMIOSDIO0CLK => SDIO0_CLK, + EMIOSDIO0CLKFB => SDIO0_CLK_FB, + EMIOSDIO0CMDI => SDIO0_CMD_I, + EMIOSDIO0CMDO => SDIO0_CMD_O, + EMIOSDIO0CMDTN => SDIO0_CMD_T_n, + EMIOSDIO0DATAI(3 downto 0) => SDIO0_DATA_I(3 downto 0), + EMIOSDIO0DATAO(3 downto 0) => SDIO0_DATA_O(3 downto 0), + EMIOSDIO0DATATN(3 downto 0) => SDIO0_DATA_T_n(3 downto 0), + EMIOSDIO0LED => SDIO0_LED, + EMIOSDIO0WP => SDIO0_WP, + EMIOSDIO1BUSPOW => SDIO1_BUSPOW, + EMIOSDIO1BUSVOLT(2 downto 0) => SDIO1_BUSVOLT(2 downto 0), + EMIOSDIO1CDN => SDIO1_CDN, + EMIOSDIO1CLK => SDIO1_CLK, + EMIOSDIO1CLKFB => SDIO1_CLK_FB, + EMIOSDIO1CMDI => SDIO1_CMD_I, + EMIOSDIO1CMDO => SDIO1_CMD_O, + EMIOSDIO1CMDTN => SDIO1_CMD_T_n, + EMIOSDIO1DATAI(3 downto 0) => SDIO1_DATA_I(3 downto 0), + EMIOSDIO1DATAO(3 downto 0) => SDIO1_DATA_O(3 downto 0), + EMIOSDIO1DATATN(3 downto 0) => SDIO1_DATA_T_n(3 downto 0), + EMIOSDIO1LED => SDIO1_LED, + EMIOSDIO1WP => SDIO1_WP, + EMIOSPI0MI => SPI0_MISO_I, + EMIOSPI0MO => SPI0_MOSI_O, + EMIOSPI0MOTN => SPI0_MOSI_T_n, + EMIOSPI0SCLKI => SPI0_SCLK_I, + EMIOSPI0SCLKO => SPI0_SCLK_O, + EMIOSPI0SCLKTN => SPI0_SCLK_T_n, + EMIOSPI0SI => SPI0_MOSI_I, + EMIOSPI0SO => SPI0_MISO_O, + EMIOSPI0SSIN => SPI0_SS_I, + EMIOSPI0SSNTN => SPI0_SS_T_n, + EMIOSPI0SSON(2) => SPI0_SS2_O, + EMIOSPI0SSON(1) => SPI0_SS1_O, + EMIOSPI0SSON(0) => SPI0_SS_O, + EMIOSPI0STN => SPI0_MISO_T_n, + EMIOSPI1MI => SPI1_MISO_I, + EMIOSPI1MO => SPI1_MOSI_O, + EMIOSPI1MOTN => SPI1_MOSI_T_n, + EMIOSPI1SCLKI => SPI1_SCLK_I, + EMIOSPI1SCLKO => SPI1_SCLK_O, + EMIOSPI1SCLKTN => SPI1_SCLK_T_n, + EMIOSPI1SI => SPI1_MOSI_I, + EMIOSPI1SO => SPI1_MISO_O, + EMIOSPI1SSIN => SPI1_SS_I, + EMIOSPI1SSNTN => SPI1_SS_T_n, + EMIOSPI1SSON(2) => SPI1_SS2_O, + EMIOSPI1SSON(1) => SPI1_SS1_O, + EMIOSPI1SSON(0) => SPI1_SS_O, + EMIOSPI1STN => SPI1_MISO_T_n, + EMIOSRAMINTIN => SRAM_INTIN, + EMIOTRACECLK => TRACE_CLK, + EMIOTRACECTL => NLW_PS7_i_EMIOTRACECTL_UNCONNECTED, + EMIOTRACEDATA(31 downto 0) => NLW_PS7_i_EMIOTRACEDATA_UNCONNECTED(31 downto 0), + EMIOTTC0CLKI(2) => TTC0_CLK2_IN, + EMIOTTC0CLKI(1) => TTC0_CLK1_IN, + EMIOTTC0CLKI(0) => TTC0_CLK0_IN, + EMIOTTC0WAVEO(2) => TTC0_WAVE2_OUT, + EMIOTTC0WAVEO(1) => TTC0_WAVE1_OUT, + EMIOTTC0WAVEO(0) => TTC0_WAVE0_OUT, + EMIOTTC1CLKI(2) => TTC1_CLK2_IN, + EMIOTTC1CLKI(1) => TTC1_CLK1_IN, + EMIOTTC1CLKI(0) => TTC1_CLK0_IN, + EMIOTTC1WAVEO(2) => TTC1_WAVE2_OUT, + EMIOTTC1WAVEO(1) => TTC1_WAVE1_OUT, + EMIOTTC1WAVEO(0) => TTC1_WAVE0_OUT, + EMIOUART0CTSN => UART0_CTSN, + EMIOUART0DCDN => UART0_DCDN, + EMIOUART0DSRN => UART0_DSRN, + EMIOUART0DTRN => UART0_DTRN, + EMIOUART0RIN => UART0_RIN, + EMIOUART0RTSN => UART0_RTSN, + EMIOUART0RX => UART0_RX, + EMIOUART0TX => UART0_TX, + EMIOUART1CTSN => UART1_CTSN, + EMIOUART1DCDN => UART1_DCDN, + EMIOUART1DSRN => UART1_DSRN, + EMIOUART1DTRN => UART1_DTRN, + EMIOUART1RIN => UART1_RIN, + EMIOUART1RTSN => UART1_RTSN, + EMIOUART1RX => UART1_RX, + EMIOUART1TX => UART1_TX, + EMIOUSB0PORTINDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0), + EMIOUSB0VBUSPWRFAULT => USB0_VBUS_PWRFAULT, + EMIOUSB0VBUSPWRSELECT => USB0_VBUS_PWRSELECT, + EMIOUSB1PORTINDCTL(1 downto 0) => USB1_PORT_INDCTL(1 downto 0), + EMIOUSB1VBUSPWRFAULT => USB1_VBUS_PWRFAULT, + EMIOUSB1VBUSPWRSELECT => USB1_VBUS_PWRSELECT, + EMIOWDTCLKI => WDT_CLK_IN, + EMIOWDTRSTO => WDT_RST_OUT, + EVENTEVENTI => EVENT_EVENTI, + EVENTEVENTO => EVENT_EVENTO, + EVENTSTANDBYWFE(1 downto 0) => EVENT_STANDBYWFE(1 downto 0), + EVENTSTANDBYWFI(1 downto 0) => EVENT_STANDBYWFI(1 downto 0), + FCLKCLK(3) => FCLK_CLK3, + FCLKCLK(2) => FCLK_CLK2, + FCLKCLK(1) => FCLK_CLK1, + FCLKCLK(0) => FCLK_CLK_unbuffered(0), + FCLKCLKTRIGN(3 downto 0) => B"0000", + FCLKRESETN(3) => FCLK_RESET3_N, + FCLKRESETN(2) => FCLK_RESET2_N, + FCLKRESETN(1) => FCLK_RESET1_N, + FCLKRESETN(0) => FCLK_RESET0_N, + FPGAIDLEN => FPGA_IDLE_N, + FTMDTRACEINATID(3 downto 0) => B"0000", + FTMDTRACEINCLOCK => FTMD_TRACEIN_CLK, + FTMDTRACEINDATA(31 downto 0) => B"00000000000000000000000000000000", + FTMDTRACEINVALID => '0', + FTMTF2PDEBUG(31 downto 0) => FTMT_F2P_DEBUG(31 downto 0), + FTMTF2PTRIG(3) => FTMT_F2P_TRIG_3, + FTMTF2PTRIG(2) => FTMT_F2P_TRIG_2, + FTMTF2PTRIG(1) => FTMT_F2P_TRIG_1, + FTMTF2PTRIG(0) => FTMT_F2P_TRIG_0, + FTMTF2PTRIGACK(3) => FTMT_F2P_TRIGACK_3, + FTMTF2PTRIGACK(2) => FTMT_F2P_TRIGACK_2, + FTMTF2PTRIGACK(1) => FTMT_F2P_TRIGACK_1, + FTMTF2PTRIGACK(0) => FTMT_F2P_TRIGACK_0, + FTMTP2FDEBUG(31 downto 0) => FTMT_P2F_DEBUG(31 downto 0), + FTMTP2FTRIG(3) => FTMT_P2F_TRIG_3, + FTMTP2FTRIG(2) => FTMT_P2F_TRIG_2, + FTMTP2FTRIG(1) => FTMT_P2F_TRIG_1, + FTMTP2FTRIG(0) => FTMT_P2F_TRIG_0, + FTMTP2FTRIGACK(3) => FTMT_P2F_TRIGACK_3, + FTMTP2FTRIGACK(2) => FTMT_P2F_TRIGACK_2, + FTMTP2FTRIGACK(1) => FTMT_P2F_TRIGACK_1, + FTMTP2FTRIGACK(0) => FTMT_P2F_TRIGACK_0, + IRQF2P(19) => Core1_nFIQ, + IRQF2P(18) => Core0_nFIQ, + IRQF2P(17) => Core1_nIRQ, + IRQF2P(16) => Core0_nIRQ, + IRQF2P(15 downto 2) => B"00000000000000", + IRQF2P(1 downto 0) => IRQ_F2P(1 downto 0), + IRQP2F(28) => IRQ_P2F_DMAC_ABORT, + IRQP2F(27) => IRQ_P2F_DMAC7, + IRQP2F(26) => IRQ_P2F_DMAC6, + IRQP2F(25) => IRQ_P2F_DMAC5, + IRQP2F(24) => IRQ_P2F_DMAC4, + IRQP2F(23) => IRQ_P2F_DMAC3, + IRQP2F(22) => IRQ_P2F_DMAC2, + IRQP2F(21) => IRQ_P2F_DMAC1, + IRQP2F(20) => IRQ_P2F_DMAC0, + IRQP2F(19) => IRQ_P2F_SMC, + IRQP2F(18) => IRQ_P2F_QSPI, + IRQP2F(17) => IRQ_P2F_CTI, + IRQP2F(16) => IRQ_P2F_GPIO, + IRQP2F(15) => IRQ_P2F_USB0, + IRQP2F(14) => IRQ_P2F_ENET0, + IRQP2F(13) => IRQ_P2F_ENET_WAKE0, + IRQP2F(12) => IRQ_P2F_SDIO0, + IRQP2F(11) => IRQ_P2F_I2C0, + IRQP2F(10) => IRQ_P2F_SPI0, + IRQP2F(9) => IRQ_P2F_UART0, + IRQP2F(8) => IRQ_P2F_CAN0, + IRQP2F(7) => IRQ_P2F_USB1, + IRQP2F(6) => IRQ_P2F_ENET1, + IRQP2F(5) => IRQ_P2F_ENET_WAKE1, + IRQP2F(4) => IRQ_P2F_SDIO1, + IRQP2F(3) => IRQ_P2F_I2C1, + IRQP2F(2) => IRQ_P2F_SPI1, + IRQP2F(1) => IRQ_P2F_UART1, + IRQP2F(0) => IRQ_P2F_CAN1, + MAXIGP0ACLK => M_AXI_GP0_ACLK, + MAXIGP0ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0), + MAXIGP0ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0), + MAXIGP0ARCACHE(3 downto 2) => \^m_axi_gp0_arcache\(3 downto 2), + MAXIGP0ARCACHE(1) => NLW_PS7_i_MAXIGP0ARCACHE_UNCONNECTED(1), + MAXIGP0ARCACHE(0) => \^m_axi_gp0_arcache\(0), + MAXIGP0ARESETN => M_AXI_GP0_ARESETN, + MAXIGP0ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0), + MAXIGP0ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0), + MAXIGP0ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0), + MAXIGP0ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0), + MAXIGP0ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0), + MAXIGP0ARREADY => M_AXI_GP0_ARREADY, + MAXIGP0ARSIZE(1 downto 0) => \^m_axi_gp0_arsize\(1 downto 0), + MAXIGP0ARVALID => M_AXI_GP0_ARVALID, + MAXIGP0AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0), + MAXIGP0AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0), + MAXIGP0AWCACHE(3 downto 2) => \^m_axi_gp0_awcache\(3 downto 2), + MAXIGP0AWCACHE(1) => NLW_PS7_i_MAXIGP0AWCACHE_UNCONNECTED(1), + MAXIGP0AWCACHE(0) => \^m_axi_gp0_awcache\(0), + MAXIGP0AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0), + MAXIGP0AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0), + MAXIGP0AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0), + MAXIGP0AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0), + MAXIGP0AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0), + MAXIGP0AWREADY => M_AXI_GP0_AWREADY, + MAXIGP0AWSIZE(1 downto 0) => \^m_axi_gp0_awsize\(1 downto 0), + MAXIGP0AWVALID => M_AXI_GP0_AWVALID, + MAXIGP0BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0), + MAXIGP0BREADY => M_AXI_GP0_BREADY, + MAXIGP0BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0), + MAXIGP0BVALID => M_AXI_GP0_BVALID, + MAXIGP0RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0), + MAXIGP0RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0), + MAXIGP0RLAST => M_AXI_GP0_RLAST, + MAXIGP0RREADY => M_AXI_GP0_RREADY, + MAXIGP0RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0), + MAXIGP0RVALID => M_AXI_GP0_RVALID, + MAXIGP0WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0), + MAXIGP0WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0), + MAXIGP0WLAST => M_AXI_GP0_WLAST, + MAXIGP0WREADY => M_AXI_GP0_WREADY, + MAXIGP0WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0), + MAXIGP0WVALID => M_AXI_GP0_WVALID, + MAXIGP1ACLK => M_AXI_GP1_ACLK, + MAXIGP1ARADDR(31 downto 0) => M_AXI_GP1_ARADDR(31 downto 0), + MAXIGP1ARBURST(1 downto 0) => M_AXI_GP1_ARBURST(1 downto 0), + MAXIGP1ARCACHE(3 downto 2) => \^m_axi_gp1_arcache\(3 downto 2), + MAXIGP1ARCACHE(1) => NLW_PS7_i_MAXIGP1ARCACHE_UNCONNECTED(1), + MAXIGP1ARCACHE(0) => \^m_axi_gp1_arcache\(0), + MAXIGP1ARESETN => M_AXI_GP1_ARESETN, + MAXIGP1ARID(11 downto 0) => M_AXI_GP1_ARID(11 downto 0), + MAXIGP1ARLEN(3 downto 0) => M_AXI_GP1_ARLEN(3 downto 0), + MAXIGP1ARLOCK(1 downto 0) => M_AXI_GP1_ARLOCK(1 downto 0), + MAXIGP1ARPROT(2 downto 0) => M_AXI_GP1_ARPROT(2 downto 0), + MAXIGP1ARQOS(3 downto 0) => M_AXI_GP1_ARQOS(3 downto 0), + MAXIGP1ARREADY => M_AXI_GP1_ARREADY, + MAXIGP1ARSIZE(1 downto 0) => \^m_axi_gp1_arsize\(1 downto 0), + MAXIGP1ARVALID => M_AXI_GP1_ARVALID, + MAXIGP1AWADDR(31 downto 0) => M_AXI_GP1_AWADDR(31 downto 0), + MAXIGP1AWBURST(1 downto 0) => M_AXI_GP1_AWBURST(1 downto 0), + MAXIGP1AWCACHE(3 downto 2) => \^m_axi_gp1_awcache\(3 downto 2), + MAXIGP1AWCACHE(1) => NLW_PS7_i_MAXIGP1AWCACHE_UNCONNECTED(1), + MAXIGP1AWCACHE(0) => \^m_axi_gp1_awcache\(0), + MAXIGP1AWID(11 downto 0) => M_AXI_GP1_AWID(11 downto 0), + MAXIGP1AWLEN(3 downto 0) => M_AXI_GP1_AWLEN(3 downto 0), + MAXIGP1AWLOCK(1 downto 0) => M_AXI_GP1_AWLOCK(1 downto 0), + MAXIGP1AWPROT(2 downto 0) => M_AXI_GP1_AWPROT(2 downto 0), + MAXIGP1AWQOS(3 downto 0) => M_AXI_GP1_AWQOS(3 downto 0), + MAXIGP1AWREADY => M_AXI_GP1_AWREADY, + MAXIGP1AWSIZE(1 downto 0) => \^m_axi_gp1_awsize\(1 downto 0), + MAXIGP1AWVALID => M_AXI_GP1_AWVALID, + MAXIGP1BID(11 downto 0) => M_AXI_GP1_BID(11 downto 0), + MAXIGP1BREADY => M_AXI_GP1_BREADY, + MAXIGP1BRESP(1 downto 0) => M_AXI_GP1_BRESP(1 downto 0), + MAXIGP1BVALID => M_AXI_GP1_BVALID, + MAXIGP1RDATA(31 downto 0) => M_AXI_GP1_RDATA(31 downto 0), + MAXIGP1RID(11 downto 0) => M_AXI_GP1_RID(11 downto 0), + MAXIGP1RLAST => M_AXI_GP1_RLAST, + MAXIGP1RREADY => M_AXI_GP1_RREADY, + MAXIGP1RRESP(1 downto 0) => M_AXI_GP1_RRESP(1 downto 0), + MAXIGP1RVALID => M_AXI_GP1_RVALID, + MAXIGP1WDATA(31 downto 0) => M_AXI_GP1_WDATA(31 downto 0), + MAXIGP1WID(11 downto 0) => M_AXI_GP1_WID(11 downto 0), + MAXIGP1WLAST => M_AXI_GP1_WLAST, + MAXIGP1WREADY => M_AXI_GP1_WREADY, + MAXIGP1WSTRB(3 downto 0) => M_AXI_GP1_WSTRB(3 downto 0), + MAXIGP1WVALID => M_AXI_GP1_WVALID, + MIO(53 downto 0) => buffered_MIO(53 downto 0), + PSCLK => buffered_PS_CLK, + PSPORB => buffered_PS_PORB, + PSSRSTB => buffered_PS_SRSTB, + SAXIACPACLK => S_AXI_ACP_ACLK, + SAXIACPARADDR(31 downto 0) => S_AXI_ACP_ARADDR(31 downto 0), + SAXIACPARBURST(1 downto 0) => S_AXI_ACP_ARBURST(1 downto 0), + SAXIACPARCACHE(3 downto 0) => S_AXI_ACP_ARCACHE(3 downto 0), + SAXIACPARESETN => S_AXI_ACP_ARESETN, + SAXIACPARID(2 downto 0) => S_AXI_ACP_ARID(2 downto 0), + SAXIACPARLEN(3 downto 0) => S_AXI_ACP_ARLEN(3 downto 0), + SAXIACPARLOCK(1 downto 0) => S_AXI_ACP_ARLOCK(1 downto 0), + SAXIACPARPROT(2 downto 0) => S_AXI_ACP_ARPROT(2 downto 0), + SAXIACPARQOS(3 downto 0) => S_AXI_ACP_ARQOS(3 downto 0), + SAXIACPARREADY => S_AXI_ACP_ARREADY, + SAXIACPARSIZE(1 downto 0) => S_AXI_ACP_ARSIZE(1 downto 0), + SAXIACPARUSER(4 downto 0) => S_AXI_ACP_ARUSER(4 downto 0), + SAXIACPARVALID => S_AXI_ACP_ARVALID, + SAXIACPAWADDR(31 downto 0) => S_AXI_ACP_AWADDR(31 downto 0), + SAXIACPAWBURST(1 downto 0) => S_AXI_ACP_AWBURST(1 downto 0), + SAXIACPAWCACHE(3 downto 0) => S_AXI_ACP_AWCACHE(3 downto 0), + SAXIACPAWID(2 downto 0) => S_AXI_ACP_AWID(2 downto 0), + SAXIACPAWLEN(3 downto 0) => S_AXI_ACP_AWLEN(3 downto 0), + SAXIACPAWLOCK(1 downto 0) => S_AXI_ACP_AWLOCK(1 downto 0), + SAXIACPAWPROT(2 downto 0) => S_AXI_ACP_AWPROT(2 downto 0), + SAXIACPAWQOS(3 downto 0) => S_AXI_ACP_AWQOS(3 downto 0), + SAXIACPAWREADY => S_AXI_ACP_AWREADY, + SAXIACPAWSIZE(1 downto 0) => S_AXI_ACP_AWSIZE(1 downto 0), + SAXIACPAWUSER(4 downto 0) => S_AXI_ACP_AWUSER(4 downto 0), + SAXIACPAWVALID => S_AXI_ACP_AWVALID, + SAXIACPBID(2 downto 0) => S_AXI_ACP_BID(2 downto 0), + SAXIACPBREADY => S_AXI_ACP_BREADY, + SAXIACPBRESP(1 downto 0) => S_AXI_ACP_BRESP(1 downto 0), + SAXIACPBVALID => S_AXI_ACP_BVALID, + SAXIACPRDATA(63 downto 0) => S_AXI_ACP_RDATA(63 downto 0), + SAXIACPRID(2 downto 0) => S_AXI_ACP_RID(2 downto 0), + SAXIACPRLAST => S_AXI_ACP_RLAST, + SAXIACPRREADY => S_AXI_ACP_RREADY, + SAXIACPRRESP(1 downto 0) => S_AXI_ACP_RRESP(1 downto 0), + SAXIACPRVALID => S_AXI_ACP_RVALID, + SAXIACPWDATA(63 downto 0) => S_AXI_ACP_WDATA(63 downto 0), + SAXIACPWID(2 downto 0) => S_AXI_ACP_WID(2 downto 0), + SAXIACPWLAST => S_AXI_ACP_WLAST, + SAXIACPWREADY => S_AXI_ACP_WREADY, + SAXIACPWSTRB(7 downto 0) => S_AXI_ACP_WSTRB(7 downto 0), + SAXIACPWVALID => S_AXI_ACP_WVALID, + SAXIGP0ACLK => S_AXI_GP0_ACLK, + SAXIGP0ARADDR(31 downto 0) => S_AXI_GP0_ARADDR(31 downto 0), + SAXIGP0ARBURST(1 downto 0) => S_AXI_GP0_ARBURST(1 downto 0), + SAXIGP0ARCACHE(3 downto 0) => S_AXI_GP0_ARCACHE(3 downto 0), + SAXIGP0ARESETN => S_AXI_GP0_ARESETN, + SAXIGP0ARID(5 downto 0) => S_AXI_GP0_ARID(5 downto 0), + SAXIGP0ARLEN(3 downto 0) => S_AXI_GP0_ARLEN(3 downto 0), + SAXIGP0ARLOCK(1 downto 0) => S_AXI_GP0_ARLOCK(1 downto 0), + SAXIGP0ARPROT(2 downto 0) => S_AXI_GP0_ARPROT(2 downto 0), + SAXIGP0ARQOS(3 downto 0) => S_AXI_GP0_ARQOS(3 downto 0), + SAXIGP0ARREADY => S_AXI_GP0_ARREADY, + SAXIGP0ARSIZE(1 downto 0) => S_AXI_GP0_ARSIZE(1 downto 0), + SAXIGP0ARVALID => S_AXI_GP0_ARVALID, + SAXIGP0AWADDR(31 downto 0) => S_AXI_GP0_AWADDR(31 downto 0), + SAXIGP0AWBURST(1 downto 0) => S_AXI_GP0_AWBURST(1 downto 0), + SAXIGP0AWCACHE(3 downto 0) => S_AXI_GP0_AWCACHE(3 downto 0), + SAXIGP0AWID(5 downto 0) => S_AXI_GP0_AWID(5 downto 0), + SAXIGP0AWLEN(3 downto 0) => S_AXI_GP0_AWLEN(3 downto 0), + SAXIGP0AWLOCK(1 downto 0) => S_AXI_GP0_AWLOCK(1 downto 0), + SAXIGP0AWPROT(2 downto 0) => S_AXI_GP0_AWPROT(2 downto 0), + SAXIGP0AWQOS(3 downto 0) => S_AXI_GP0_AWQOS(3 downto 0), + SAXIGP0AWREADY => S_AXI_GP0_AWREADY, + SAXIGP0AWSIZE(1 downto 0) => S_AXI_GP0_AWSIZE(1 downto 0), + SAXIGP0AWVALID => S_AXI_GP0_AWVALID, + SAXIGP0BID(5 downto 0) => S_AXI_GP0_BID(5 downto 0), + SAXIGP0BREADY => S_AXI_GP0_BREADY, + SAXIGP0BRESP(1 downto 0) => S_AXI_GP0_BRESP(1 downto 0), + SAXIGP0BVALID => S_AXI_GP0_BVALID, + SAXIGP0RDATA(31 downto 0) => S_AXI_GP0_RDATA(31 downto 0), + SAXIGP0RID(5 downto 0) => S_AXI_GP0_RID(5 downto 0), + SAXIGP0RLAST => S_AXI_GP0_RLAST, + SAXIGP0RREADY => S_AXI_GP0_RREADY, + SAXIGP0RRESP(1 downto 0) => S_AXI_GP0_RRESP(1 downto 0), + SAXIGP0RVALID => S_AXI_GP0_RVALID, + SAXIGP0WDATA(31 downto 0) => S_AXI_GP0_WDATA(31 downto 0), + SAXIGP0WID(5 downto 0) => S_AXI_GP0_WID(5 downto 0), + SAXIGP0WLAST => S_AXI_GP0_WLAST, + SAXIGP0WREADY => S_AXI_GP0_WREADY, + SAXIGP0WSTRB(3 downto 0) => S_AXI_GP0_WSTRB(3 downto 0), + SAXIGP0WVALID => S_AXI_GP0_WVALID, + SAXIGP1ACLK => S_AXI_GP1_ACLK, + SAXIGP1ARADDR(31 downto 0) => S_AXI_GP1_ARADDR(31 downto 0), + SAXIGP1ARBURST(1 downto 0) => S_AXI_GP1_ARBURST(1 downto 0), + SAXIGP1ARCACHE(3 downto 0) => S_AXI_GP1_ARCACHE(3 downto 0), + SAXIGP1ARESETN => S_AXI_GP1_ARESETN, + SAXIGP1ARID(5 downto 0) => S_AXI_GP1_ARID(5 downto 0), + SAXIGP1ARLEN(3 downto 0) => S_AXI_GP1_ARLEN(3 downto 0), + SAXIGP1ARLOCK(1 downto 0) => S_AXI_GP1_ARLOCK(1 downto 0), + SAXIGP1ARPROT(2 downto 0) => S_AXI_GP1_ARPROT(2 downto 0), + SAXIGP1ARQOS(3 downto 0) => S_AXI_GP1_ARQOS(3 downto 0), + SAXIGP1ARREADY => S_AXI_GP1_ARREADY, + SAXIGP1ARSIZE(1 downto 0) => S_AXI_GP1_ARSIZE(1 downto 0), + SAXIGP1ARVALID => S_AXI_GP1_ARVALID, + SAXIGP1AWADDR(31 downto 0) => S_AXI_GP1_AWADDR(31 downto 0), + SAXIGP1AWBURST(1 downto 0) => S_AXI_GP1_AWBURST(1 downto 0), + SAXIGP1AWCACHE(3 downto 0) => S_AXI_GP1_AWCACHE(3 downto 0), + SAXIGP1AWID(5 downto 0) => S_AXI_GP1_AWID(5 downto 0), + SAXIGP1AWLEN(3 downto 0) => S_AXI_GP1_AWLEN(3 downto 0), + SAXIGP1AWLOCK(1 downto 0) => S_AXI_GP1_AWLOCK(1 downto 0), + SAXIGP1AWPROT(2 downto 0) => S_AXI_GP1_AWPROT(2 downto 0), + SAXIGP1AWQOS(3 downto 0) => S_AXI_GP1_AWQOS(3 downto 0), + SAXIGP1AWREADY => S_AXI_GP1_AWREADY, + SAXIGP1AWSIZE(1 downto 0) => S_AXI_GP1_AWSIZE(1 downto 0), + SAXIGP1AWVALID => S_AXI_GP1_AWVALID, + SAXIGP1BID(5 downto 0) => S_AXI_GP1_BID(5 downto 0), + SAXIGP1BREADY => S_AXI_GP1_BREADY, + SAXIGP1BRESP(1 downto 0) => S_AXI_GP1_BRESP(1 downto 0), + SAXIGP1BVALID => S_AXI_GP1_BVALID, + SAXIGP1RDATA(31 downto 0) => S_AXI_GP1_RDATA(31 downto 0), + SAXIGP1RID(5 downto 0) => S_AXI_GP1_RID(5 downto 0), + SAXIGP1RLAST => S_AXI_GP1_RLAST, + SAXIGP1RREADY => S_AXI_GP1_RREADY, + SAXIGP1RRESP(1 downto 0) => S_AXI_GP1_RRESP(1 downto 0), + SAXIGP1RVALID => S_AXI_GP1_RVALID, + SAXIGP1WDATA(31 downto 0) => S_AXI_GP1_WDATA(31 downto 0), + SAXIGP1WID(5 downto 0) => S_AXI_GP1_WID(5 downto 0), + SAXIGP1WLAST => S_AXI_GP1_WLAST, + SAXIGP1WREADY => S_AXI_GP1_WREADY, + SAXIGP1WSTRB(3 downto 0) => S_AXI_GP1_WSTRB(3 downto 0), + SAXIGP1WVALID => S_AXI_GP1_WVALID, + SAXIHP0ACLK => S_AXI_HP0_ACLK, + SAXIHP0ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0), + SAXIHP0ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0), + SAXIHP0ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0), + SAXIHP0ARESETN => S_AXI_HP0_ARESETN, + SAXIHP0ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0), + SAXIHP0ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0), + SAXIHP0ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0), + SAXIHP0ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0), + SAXIHP0ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0), + SAXIHP0ARREADY => S_AXI_HP0_ARREADY, + SAXIHP0ARSIZE(1 downto 0) => S_AXI_HP0_ARSIZE(1 downto 0), + SAXIHP0ARVALID => S_AXI_HP0_ARVALID, + SAXIHP0AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0), + SAXIHP0AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0), + SAXIHP0AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0), + SAXIHP0AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0), + SAXIHP0AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0), + SAXIHP0AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0), + SAXIHP0AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0), + SAXIHP0AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0), + SAXIHP0AWREADY => S_AXI_HP0_AWREADY, + SAXIHP0AWSIZE(1 downto 0) => S_AXI_HP0_AWSIZE(1 downto 0), + SAXIHP0AWVALID => S_AXI_HP0_AWVALID, + SAXIHP0BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0), + SAXIHP0BREADY => S_AXI_HP0_BREADY, + SAXIHP0BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0), + SAXIHP0BVALID => S_AXI_HP0_BVALID, + SAXIHP0RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0), + SAXIHP0RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0), + SAXIHP0RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0), + SAXIHP0RDISSUECAP1EN => S_AXI_HP0_RDISSUECAP1_EN, + SAXIHP0RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0), + SAXIHP0RLAST => S_AXI_HP0_RLAST, + SAXIHP0RREADY => S_AXI_HP0_RREADY, + SAXIHP0RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0), + SAXIHP0RVALID => S_AXI_HP0_RVALID, + SAXIHP0WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0), + SAXIHP0WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0), + SAXIHP0WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0), + SAXIHP0WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0), + SAXIHP0WLAST => S_AXI_HP0_WLAST, + SAXIHP0WREADY => S_AXI_HP0_WREADY, + SAXIHP0WRISSUECAP1EN => S_AXI_HP0_WRISSUECAP1_EN, + SAXIHP0WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0), + SAXIHP0WVALID => S_AXI_HP0_WVALID, + SAXIHP1ACLK => S_AXI_HP1_ACLK, + SAXIHP1ARADDR(31 downto 0) => S_AXI_HP1_ARADDR(31 downto 0), + SAXIHP1ARBURST(1 downto 0) => S_AXI_HP1_ARBURST(1 downto 0), + SAXIHP1ARCACHE(3 downto 0) => S_AXI_HP1_ARCACHE(3 downto 0), + SAXIHP1ARESETN => S_AXI_HP1_ARESETN, + SAXIHP1ARID(5 downto 0) => S_AXI_HP1_ARID(5 downto 0), + SAXIHP1ARLEN(3 downto 0) => S_AXI_HP1_ARLEN(3 downto 0), + SAXIHP1ARLOCK(1 downto 0) => S_AXI_HP1_ARLOCK(1 downto 0), + SAXIHP1ARPROT(2 downto 0) => S_AXI_HP1_ARPROT(2 downto 0), + SAXIHP1ARQOS(3 downto 0) => S_AXI_HP1_ARQOS(3 downto 0), + SAXIHP1ARREADY => S_AXI_HP1_ARREADY, + SAXIHP1ARSIZE(1 downto 0) => S_AXI_HP1_ARSIZE(1 downto 0), + SAXIHP1ARVALID => S_AXI_HP1_ARVALID, + SAXIHP1AWADDR(31 downto 0) => S_AXI_HP1_AWADDR(31 downto 0), + SAXIHP1AWBURST(1 downto 0) => S_AXI_HP1_AWBURST(1 downto 0), + SAXIHP1AWCACHE(3 downto 0) => S_AXI_HP1_AWCACHE(3 downto 0), + SAXIHP1AWID(5 downto 0) => S_AXI_HP1_AWID(5 downto 0), + SAXIHP1AWLEN(3 downto 0) => S_AXI_HP1_AWLEN(3 downto 0), + SAXIHP1AWLOCK(1 downto 0) => S_AXI_HP1_AWLOCK(1 downto 0), + SAXIHP1AWPROT(2 downto 0) => S_AXI_HP1_AWPROT(2 downto 0), + SAXIHP1AWQOS(3 downto 0) => S_AXI_HP1_AWQOS(3 downto 0), + SAXIHP1AWREADY => S_AXI_HP1_AWREADY, + SAXIHP1AWSIZE(1 downto 0) => S_AXI_HP1_AWSIZE(1 downto 0), + SAXIHP1AWVALID => S_AXI_HP1_AWVALID, + SAXIHP1BID(5 downto 0) => S_AXI_HP1_BID(5 downto 0), + SAXIHP1BREADY => S_AXI_HP1_BREADY, + SAXIHP1BRESP(1 downto 0) => S_AXI_HP1_BRESP(1 downto 0), + SAXIHP1BVALID => S_AXI_HP1_BVALID, + SAXIHP1RACOUNT(2 downto 0) => S_AXI_HP1_RACOUNT(2 downto 0), + SAXIHP1RCOUNT(7 downto 0) => S_AXI_HP1_RCOUNT(7 downto 0), + SAXIHP1RDATA(63 downto 0) => S_AXI_HP1_RDATA(63 downto 0), + SAXIHP1RDISSUECAP1EN => S_AXI_HP1_RDISSUECAP1_EN, + SAXIHP1RID(5 downto 0) => S_AXI_HP1_RID(5 downto 0), + SAXIHP1RLAST => S_AXI_HP1_RLAST, + SAXIHP1RREADY => S_AXI_HP1_RREADY, + SAXIHP1RRESP(1 downto 0) => S_AXI_HP1_RRESP(1 downto 0), + SAXIHP1RVALID => S_AXI_HP1_RVALID, + SAXIHP1WACOUNT(5 downto 0) => S_AXI_HP1_WACOUNT(5 downto 0), + SAXIHP1WCOUNT(7 downto 0) => S_AXI_HP1_WCOUNT(7 downto 0), + SAXIHP1WDATA(63 downto 0) => S_AXI_HP1_WDATA(63 downto 0), + SAXIHP1WID(5 downto 0) => S_AXI_HP1_WID(5 downto 0), + SAXIHP1WLAST => S_AXI_HP1_WLAST, + SAXIHP1WREADY => S_AXI_HP1_WREADY, + SAXIHP1WRISSUECAP1EN => S_AXI_HP1_WRISSUECAP1_EN, + SAXIHP1WSTRB(7 downto 0) => S_AXI_HP1_WSTRB(7 downto 0), + SAXIHP1WVALID => S_AXI_HP1_WVALID, + SAXIHP2ACLK => S_AXI_HP2_ACLK, + SAXIHP2ARADDR(31 downto 0) => S_AXI_HP2_ARADDR(31 downto 0), + SAXIHP2ARBURST(1 downto 0) => S_AXI_HP2_ARBURST(1 downto 0), + SAXIHP2ARCACHE(3 downto 0) => S_AXI_HP2_ARCACHE(3 downto 0), + SAXIHP2ARESETN => S_AXI_HP2_ARESETN, + SAXIHP2ARID(5 downto 0) => S_AXI_HP2_ARID(5 downto 0), + SAXIHP2ARLEN(3 downto 0) => S_AXI_HP2_ARLEN(3 downto 0), + SAXIHP2ARLOCK(1 downto 0) => S_AXI_HP2_ARLOCK(1 downto 0), + SAXIHP2ARPROT(2 downto 0) => S_AXI_HP2_ARPROT(2 downto 0), + SAXIHP2ARQOS(3 downto 0) => S_AXI_HP2_ARQOS(3 downto 0), + SAXIHP2ARREADY => S_AXI_HP2_ARREADY, + SAXIHP2ARSIZE(1 downto 0) => S_AXI_HP2_ARSIZE(1 downto 0), + SAXIHP2ARVALID => S_AXI_HP2_ARVALID, + SAXIHP2AWADDR(31 downto 0) => S_AXI_HP2_AWADDR(31 downto 0), + SAXIHP2AWBURST(1 downto 0) => S_AXI_HP2_AWBURST(1 downto 0), + SAXIHP2AWCACHE(3 downto 0) => S_AXI_HP2_AWCACHE(3 downto 0), + SAXIHP2AWID(5 downto 0) => S_AXI_HP2_AWID(5 downto 0), + SAXIHP2AWLEN(3 downto 0) => S_AXI_HP2_AWLEN(3 downto 0), + SAXIHP2AWLOCK(1 downto 0) => S_AXI_HP2_AWLOCK(1 downto 0), + SAXIHP2AWPROT(2 downto 0) => S_AXI_HP2_AWPROT(2 downto 0), + SAXIHP2AWQOS(3 downto 0) => S_AXI_HP2_AWQOS(3 downto 0), + SAXIHP2AWREADY => S_AXI_HP2_AWREADY, + SAXIHP2AWSIZE(1 downto 0) => S_AXI_HP2_AWSIZE(1 downto 0), + SAXIHP2AWVALID => S_AXI_HP2_AWVALID, + SAXIHP2BID(5 downto 0) => S_AXI_HP2_BID(5 downto 0), + SAXIHP2BREADY => S_AXI_HP2_BREADY, + SAXIHP2BRESP(1 downto 0) => S_AXI_HP2_BRESP(1 downto 0), + SAXIHP2BVALID => S_AXI_HP2_BVALID, + SAXIHP2RACOUNT(2 downto 0) => S_AXI_HP2_RACOUNT(2 downto 0), + SAXIHP2RCOUNT(7 downto 0) => S_AXI_HP2_RCOUNT(7 downto 0), + SAXIHP2RDATA(63 downto 0) => S_AXI_HP2_RDATA(63 downto 0), + SAXIHP2RDISSUECAP1EN => S_AXI_HP2_RDISSUECAP1_EN, + SAXIHP2RID(5 downto 0) => S_AXI_HP2_RID(5 downto 0), + SAXIHP2RLAST => S_AXI_HP2_RLAST, + SAXIHP2RREADY => S_AXI_HP2_RREADY, + SAXIHP2RRESP(1 downto 0) => S_AXI_HP2_RRESP(1 downto 0), + SAXIHP2RVALID => S_AXI_HP2_RVALID, + SAXIHP2WACOUNT(5 downto 0) => S_AXI_HP2_WACOUNT(5 downto 0), + SAXIHP2WCOUNT(7 downto 0) => S_AXI_HP2_WCOUNT(7 downto 0), + SAXIHP2WDATA(63 downto 0) => S_AXI_HP2_WDATA(63 downto 0), + SAXIHP2WID(5 downto 0) => S_AXI_HP2_WID(5 downto 0), + SAXIHP2WLAST => S_AXI_HP2_WLAST, + SAXIHP2WREADY => S_AXI_HP2_WREADY, + SAXIHP2WRISSUECAP1EN => S_AXI_HP2_WRISSUECAP1_EN, + SAXIHP2WSTRB(7 downto 0) => S_AXI_HP2_WSTRB(7 downto 0), + SAXIHP2WVALID => S_AXI_HP2_WVALID, + SAXIHP3ACLK => S_AXI_HP3_ACLK, + SAXIHP3ARADDR(31 downto 0) => S_AXI_HP3_ARADDR(31 downto 0), + SAXIHP3ARBURST(1 downto 0) => S_AXI_HP3_ARBURST(1 downto 0), + SAXIHP3ARCACHE(3 downto 0) => S_AXI_HP3_ARCACHE(3 downto 0), + SAXIHP3ARESETN => S_AXI_HP3_ARESETN, + SAXIHP3ARID(5 downto 0) => S_AXI_HP3_ARID(5 downto 0), + SAXIHP3ARLEN(3 downto 0) => S_AXI_HP3_ARLEN(3 downto 0), + SAXIHP3ARLOCK(1 downto 0) => S_AXI_HP3_ARLOCK(1 downto 0), + SAXIHP3ARPROT(2 downto 0) => S_AXI_HP3_ARPROT(2 downto 0), + SAXIHP3ARQOS(3 downto 0) => S_AXI_HP3_ARQOS(3 downto 0), + SAXIHP3ARREADY => S_AXI_HP3_ARREADY, + SAXIHP3ARSIZE(1 downto 0) => S_AXI_HP3_ARSIZE(1 downto 0), + SAXIHP3ARVALID => S_AXI_HP3_ARVALID, + SAXIHP3AWADDR(31 downto 0) => S_AXI_HP3_AWADDR(31 downto 0), + SAXIHP3AWBURST(1 downto 0) => S_AXI_HP3_AWBURST(1 downto 0), + SAXIHP3AWCACHE(3 downto 0) => S_AXI_HP3_AWCACHE(3 downto 0), + SAXIHP3AWID(5 downto 0) => S_AXI_HP3_AWID(5 downto 0), + SAXIHP3AWLEN(3 downto 0) => S_AXI_HP3_AWLEN(3 downto 0), + SAXIHP3AWLOCK(1 downto 0) => S_AXI_HP3_AWLOCK(1 downto 0), + SAXIHP3AWPROT(2 downto 0) => S_AXI_HP3_AWPROT(2 downto 0), + SAXIHP3AWQOS(3 downto 0) => S_AXI_HP3_AWQOS(3 downto 0), + SAXIHP3AWREADY => S_AXI_HP3_AWREADY, + SAXIHP3AWSIZE(1 downto 0) => S_AXI_HP3_AWSIZE(1 downto 0), + SAXIHP3AWVALID => S_AXI_HP3_AWVALID, + SAXIHP3BID(5 downto 0) => S_AXI_HP3_BID(5 downto 0), + SAXIHP3BREADY => S_AXI_HP3_BREADY, + SAXIHP3BRESP(1 downto 0) => S_AXI_HP3_BRESP(1 downto 0), + SAXIHP3BVALID => S_AXI_HP3_BVALID, + SAXIHP3RACOUNT(2 downto 0) => S_AXI_HP3_RACOUNT(2 downto 0), + SAXIHP3RCOUNT(7 downto 0) => S_AXI_HP3_RCOUNT(7 downto 0), + SAXIHP3RDATA(63 downto 0) => S_AXI_HP3_RDATA(63 downto 0), + SAXIHP3RDISSUECAP1EN => S_AXI_HP3_RDISSUECAP1_EN, + SAXIHP3RID(5 downto 0) => S_AXI_HP3_RID(5 downto 0), + SAXIHP3RLAST => S_AXI_HP3_RLAST, + SAXIHP3RREADY => S_AXI_HP3_RREADY, + SAXIHP3RRESP(1 downto 0) => S_AXI_HP3_RRESP(1 downto 0), + SAXIHP3RVALID => S_AXI_HP3_RVALID, + SAXIHP3WACOUNT(5 downto 0) => S_AXI_HP3_WACOUNT(5 downto 0), + SAXIHP3WCOUNT(7 downto 0) => S_AXI_HP3_WCOUNT(7 downto 0), + SAXIHP3WDATA(63 downto 0) => S_AXI_HP3_WDATA(63 downto 0), + SAXIHP3WID(5 downto 0) => S_AXI_HP3_WID(5 downto 0), + SAXIHP3WLAST => S_AXI_HP3_WLAST, + SAXIHP3WREADY => S_AXI_HP3_WREADY, + SAXIHP3WRISSUECAP1EN => S_AXI_HP3_WRISSUECAP1_EN, + SAXIHP3WSTRB(7 downto 0) => S_AXI_HP3_WSTRB(7 downto 0), + SAXIHP3WVALID => S_AXI_HP3_WVALID + ); +PS_CLK_BIBUF: unisim.vcomponents.BIBUF + port map ( + IO => buffered_PS_CLK, + PAD => PS_CLK + ); +PS_PORB_BIBUF: unisim.vcomponents.BIBUF + port map ( + IO => buffered_PS_PORB, + PAD => PS_PORB + ); +PS_SRSTB_BIBUF: unisim.vcomponents.BIBUF + port map ( + IO => buffered_PS_SRSTB, + PAD => PS_SRSTB + ); +SDIO0_CMD_T_INST_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => SDIO0_CMD_T_n, + O => SDIO0_CMD_T + ); +\SDIO0_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => SDIO0_DATA_T_n(0), + O => SDIO0_DATA_T(0) + ); +\SDIO0_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => SDIO0_DATA_T_n(1), + O => SDIO0_DATA_T(1) + ); +\SDIO0_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => SDIO0_DATA_T_n(2), + O => SDIO0_DATA_T(2) + ); +\SDIO0_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => SDIO0_DATA_T_n(3), + O => SDIO0_DATA_T(3) + ); +SDIO1_CMD_T_INST_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => SDIO1_CMD_T_n, + O => SDIO1_CMD_T + ); +\SDIO1_DATA_T[0]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => SDIO1_DATA_T_n(0), + O => SDIO1_DATA_T(0) + ); +\SDIO1_DATA_T[1]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => SDIO1_DATA_T_n(1), + O => SDIO1_DATA_T(1) + ); +\SDIO1_DATA_T[2]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => SDIO1_DATA_T_n(2), + O => SDIO1_DATA_T(2) + ); +\SDIO1_DATA_T[3]_INST_0\: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => SDIO1_DATA_T_n(3), + O => SDIO1_DATA_T(3) + ); +SPI0_MISO_T_INST_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => SPI0_MISO_T_n, + O => SPI0_MISO_T + ); +SPI0_MOSI_T_INST_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => SPI0_MOSI_T_n, + O => SPI0_MOSI_T + ); +SPI0_SCLK_T_INST_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => SPI0_SCLK_T_n, + O => SPI0_SCLK_T + ); +SPI0_SS_T_INST_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => SPI0_SS_T_n, + O => SPI0_SS_T + ); +SPI1_MISO_T_INST_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => SPI1_MISO_T_n, + O => SPI1_MISO_T + ); +SPI1_MOSI_T_INST_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => SPI1_MOSI_T_n, + O => SPI1_MOSI_T + ); +SPI1_SCLK_T_INST_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => SPI1_SCLK_T_n, + O => SPI1_SCLK_T + ); +SPI1_SS_T_INST_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"1" + ) + port map ( + I0 => SPI1_SS_T_n, + O => SPI1_SS_T + ); +VCC: unisim.vcomponents.VCC + port map ( + P => \\ + ); +\buffer_fclk_clk_0.FCLK_CLK_0_BUFG\: unisim.vcomponents.BUFG + port map ( + I => FCLK_CLK_unbuffered(0), + O => FCLK_CLK0 + ); +\genblk13[0].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(0), + PAD => MIO(0) + ); +\genblk13[10].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(10), + PAD => MIO(10) + ); +\genblk13[11].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(11), + PAD => MIO(11) + ); +\genblk13[12].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(12), + PAD => MIO(12) + ); +\genblk13[13].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(13), + PAD => MIO(13) + ); +\genblk13[14].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(14), + PAD => MIO(14) + ); +\genblk13[15].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(15), + PAD => MIO(15) + ); +\genblk13[16].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(16), + PAD => MIO(16) + ); +\genblk13[17].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(17), + PAD => MIO(17) + ); +\genblk13[18].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(18), + PAD => MIO(18) + ); +\genblk13[19].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(19), + PAD => MIO(19) + ); +\genblk13[1].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(1), + PAD => MIO(1) + ); +\genblk13[20].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(20), + PAD => MIO(20) + ); +\genblk13[21].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(21), + PAD => MIO(21) + ); +\genblk13[22].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(22), + PAD => MIO(22) + ); +\genblk13[23].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(23), + PAD => MIO(23) + ); +\genblk13[24].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(24), + PAD => MIO(24) + ); +\genblk13[25].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(25), + PAD => MIO(25) + ); +\genblk13[26].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(26), + PAD => MIO(26) + ); +\genblk13[27].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(27), + PAD => MIO(27) + ); +\genblk13[28].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(28), + PAD => MIO(28) + ); +\genblk13[29].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(29), + PAD => MIO(29) + ); +\genblk13[2].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(2), + PAD => MIO(2) + ); +\genblk13[30].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(30), + PAD => MIO(30) + ); +\genblk13[31].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(31), + PAD => MIO(31) + ); +\genblk13[32].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(32), + PAD => MIO(32) + ); +\genblk13[33].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(33), + PAD => MIO(33) + ); +\genblk13[34].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(34), + PAD => MIO(34) + ); +\genblk13[35].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(35), + PAD => MIO(35) + ); +\genblk13[36].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(36), + PAD => MIO(36) + ); +\genblk13[37].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(37), + PAD => MIO(37) + ); +\genblk13[38].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(38), + PAD => MIO(38) + ); +\genblk13[39].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(39), + PAD => MIO(39) + ); +\genblk13[3].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(3), + PAD => MIO(3) + ); +\genblk13[40].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(40), + PAD => MIO(40) + ); +\genblk13[41].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(41), + PAD => MIO(41) + ); +\genblk13[42].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(42), + PAD => MIO(42) + ); +\genblk13[43].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(43), + PAD => MIO(43) + ); +\genblk13[44].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(44), + PAD => MIO(44) + ); +\genblk13[45].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(45), + PAD => MIO(45) + ); +\genblk13[46].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(46), + PAD => MIO(46) + ); +\genblk13[47].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(47), + PAD => MIO(47) + ); +\genblk13[48].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(48), + PAD => MIO(48) + ); +\genblk13[49].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(49), + PAD => MIO(49) + ); +\genblk13[4].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(4), + PAD => MIO(4) + ); +\genblk13[50].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(50), + PAD => MIO(50) + ); +\genblk13[51].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(51), + PAD => MIO(51) + ); +\genblk13[52].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(52), + PAD => MIO(52) + ); +\genblk13[53].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(53), + PAD => MIO(53) + ); +\genblk13[5].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(5), + PAD => MIO(5) + ); +\genblk13[6].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(6), + PAD => MIO(6) + ); +\genblk13[7].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(7), + PAD => MIO(7) + ); +\genblk13[8].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(8), + PAD => MIO(8) + ); +\genblk13[9].MIO_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_MIO(9), + PAD => MIO(9) + ); +\genblk14[0].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_BankAddr(0), + PAD => DDR_BankAddr(0) + ); +\genblk14[1].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_BankAddr(1), + PAD => DDR_BankAddr(1) + ); +\genblk14[2].DDR_BankAddr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_BankAddr(2), + PAD => DDR_BankAddr(2) + ); +\genblk15[0].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Addr(0), + PAD => DDR_Addr(0) + ); +\genblk15[10].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Addr(10), + PAD => DDR_Addr(10) + ); +\genblk15[11].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Addr(11), + PAD => DDR_Addr(11) + ); +\genblk15[12].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Addr(12), + PAD => DDR_Addr(12) + ); +\genblk15[13].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Addr(13), + PAD => DDR_Addr(13) + ); +\genblk15[14].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Addr(14), + PAD => DDR_Addr(14) + ); +\genblk15[1].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Addr(1), + PAD => DDR_Addr(1) + ); +\genblk15[2].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Addr(2), + PAD => DDR_Addr(2) + ); +\genblk15[3].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Addr(3), + PAD => DDR_Addr(3) + ); +\genblk15[4].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Addr(4), + PAD => DDR_Addr(4) + ); +\genblk15[5].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Addr(5), + PAD => DDR_Addr(5) + ); +\genblk15[6].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Addr(6), + PAD => DDR_Addr(6) + ); +\genblk15[7].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Addr(7), + PAD => DDR_Addr(7) + ); +\genblk15[8].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Addr(8), + PAD => DDR_Addr(8) + ); +\genblk15[9].DDR_Addr_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_Addr(9), + PAD => DDR_Addr(9) + ); +\genblk16[0].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DM(0), + PAD => DDR_DM(0) + ); +\genblk16[1].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DM(1), + PAD => DDR_DM(1) + ); +\genblk16[2].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DM(2), + PAD => DDR_DM(2) + ); +\genblk16[3].DDR_DM_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DM(3), + PAD => DDR_DM(3) + ); +\genblk17[0].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(0), + PAD => DDR_DQ(0) + ); +\genblk17[10].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(10), + PAD => DDR_DQ(10) + ); +\genblk17[11].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(11), + PAD => DDR_DQ(11) + ); +\genblk17[12].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(12), + PAD => DDR_DQ(12) + ); +\genblk17[13].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(13), + PAD => DDR_DQ(13) + ); +\genblk17[14].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(14), + PAD => DDR_DQ(14) + ); +\genblk17[15].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(15), + PAD => DDR_DQ(15) + ); +\genblk17[16].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(16), + PAD => DDR_DQ(16) + ); +\genblk17[17].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(17), + PAD => DDR_DQ(17) + ); +\genblk17[18].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(18), + PAD => DDR_DQ(18) + ); +\genblk17[19].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(19), + PAD => DDR_DQ(19) + ); +\genblk17[1].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(1), + PAD => DDR_DQ(1) + ); +\genblk17[20].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(20), + PAD => DDR_DQ(20) + ); +\genblk17[21].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(21), + PAD => DDR_DQ(21) + ); +\genblk17[22].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(22), + PAD => DDR_DQ(22) + ); +\genblk17[23].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(23), + PAD => DDR_DQ(23) + ); +\genblk17[24].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(24), + PAD => DDR_DQ(24) + ); +\genblk17[25].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(25), + PAD => DDR_DQ(25) + ); +\genblk17[26].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(26), + PAD => DDR_DQ(26) + ); +\genblk17[27].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(27), + PAD => DDR_DQ(27) + ); +\genblk17[28].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(28), + PAD => DDR_DQ(28) + ); +\genblk17[29].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(29), + PAD => DDR_DQ(29) + ); +\genblk17[2].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(2), + PAD => DDR_DQ(2) + ); +\genblk17[30].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(30), + PAD => DDR_DQ(30) + ); +\genblk17[31].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(31), + PAD => DDR_DQ(31) + ); +\genblk17[3].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(3), + PAD => DDR_DQ(3) + ); +\genblk17[4].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(4), + PAD => DDR_DQ(4) + ); +\genblk17[5].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(5), + PAD => DDR_DQ(5) + ); +\genblk17[6].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(6), + PAD => DDR_DQ(6) + ); +\genblk17[7].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(7), + PAD => DDR_DQ(7) + ); +\genblk17[8].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(8), + PAD => DDR_DQ(8) + ); +\genblk17[9].DDR_DQ_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQ(9), + PAD => DDR_DQ(9) + ); +\genblk18[0].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQS_n(0), + PAD => DDR_DQS_n(0) + ); +\genblk18[1].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQS_n(1), + PAD => DDR_DQS_n(1) + ); +\genblk18[2].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQS_n(2), + PAD => DDR_DQS_n(2) + ); +\genblk18[3].DDR_DQS_n_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQS_n(3), + PAD => DDR_DQS_n(3) + ); +\genblk19[0].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQS(0), + PAD => DDR_DQS(0) + ); +\genblk19[1].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQS(1), + PAD => DDR_DQS(1) + ); +\genblk19[2].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQS(2), + PAD => DDR_DQS(2) + ); +\genblk19[3].DDR_DQS_BIBUF\: unisim.vcomponents.BIBUF + port map ( + IO => buffered_DDR_DQS(3), + PAD => DDR_DQS(3) + ); +i_0: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_CTL_PIPE[0]\ + ); +i_1: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[0]\(1) + ); +i_10: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[7]\(1) + ); +i_11: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[7]\(0) + ); +i_12: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[6]\(1) + ); +i_13: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[6]\(0) + ); +i_14: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[5]\(1) + ); +i_15: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[5]\(0) + ); +i_16: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[4]\(1) + ); +i_17: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[4]\(0) + ); +i_18: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[3]\(1) + ); +i_19: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[3]\(0) + ); +i_2: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[0]\(0) + ); +i_20: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[2]\(1) + ); +i_21: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[2]\(0) + ); +i_22: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[1]\(1) + ); +i_23: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_DATA_PIPE[1]\(0) + ); +i_3: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_CTL_PIPE[7]\ + ); +i_4: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_CTL_PIPE[6]\ + ); +i_5: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_CTL_PIPE[5]\ + ); +i_6: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_CTL_PIPE[4]\ + ); +i_7: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_CTL_PIPE[3]\ + ); +i_8: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_CTL_PIPE[2]\ + ); +i_9: unisim.vcomponents.LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => '0', + O => \TRACE_CTL_PIPE[1]\ + ); +end STRUCTURE; +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + port ( + I2C0_SDA_I : in STD_LOGIC; + I2C0_SDA_O : out STD_LOGIC; + I2C0_SDA_T : out STD_LOGIC; + I2C0_SCL_I : in STD_LOGIC; + I2C0_SCL_O : out STD_LOGIC; + I2C0_SCL_T : out STD_LOGIC; + SPI1_SCLK_I : in STD_LOGIC; + SPI1_SCLK_O : out STD_LOGIC; + SPI1_SCLK_T : out STD_LOGIC; + SPI1_MOSI_I : in STD_LOGIC; + SPI1_MOSI_O : out STD_LOGIC; + SPI1_MOSI_T : out STD_LOGIC; + SPI1_MISO_I : in STD_LOGIC; + SPI1_MISO_O : out STD_LOGIC; + SPI1_MISO_T : out STD_LOGIC; + SPI1_SS_I : in STD_LOGIC; + SPI1_SS_O : out STD_LOGIC; + SPI1_SS1_O : out STD_LOGIC; + SPI1_SS2_O : out STD_LOGIC; + SPI1_SS_T : out STD_LOGIC; + TTC0_WAVE0_OUT : out STD_LOGIC; + TTC0_WAVE1_OUT : out STD_LOGIC; + TTC0_WAVE2_OUT : out STD_LOGIC; + USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); + USB0_VBUS_PWRSELECT : out STD_LOGIC; + USB0_VBUS_PWRFAULT : in STD_LOGIC; + M_AXI_GP0_ARVALID : out STD_LOGIC; + M_AXI_GP0_AWVALID : out STD_LOGIC; + M_AXI_GP0_BREADY : out STD_LOGIC; + M_AXI_GP0_RREADY : out STD_LOGIC; + M_AXI_GP0_WLAST : out STD_LOGIC; + M_AXI_GP0_WVALID : out STD_LOGIC; + M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_ACLK : in STD_LOGIC; + M_AXI_GP0_ARREADY : in STD_LOGIC; + M_AXI_GP0_AWREADY : in STD_LOGIC; + M_AXI_GP0_BVALID : in STD_LOGIC; + M_AXI_GP0_RLAST : in STD_LOGIC; + M_AXI_GP0_RVALID : in STD_LOGIC; + M_AXI_GP0_WREADY : in STD_LOGIC; + M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_HP0_ARREADY : out STD_LOGIC; + S_AXI_HP0_AWREADY : out STD_LOGIC; + S_AXI_HP0_BVALID : out STD_LOGIC; + S_AXI_HP0_RLAST : out STD_LOGIC; + S_AXI_HP0_RVALID : out STD_LOGIC; + S_AXI_HP0_WREADY : out STD_LOGIC; + S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_ACLK : in STD_LOGIC; + S_AXI_HP0_ARVALID : in STD_LOGIC; + S_AXI_HP0_AWVALID : in STD_LOGIC; + S_AXI_HP0_BREADY : in STD_LOGIC; + S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC; + S_AXI_HP0_RREADY : in STD_LOGIC; + S_AXI_HP0_WLAST : in STD_LOGIC; + S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC; + S_AXI_HP0_WVALID : in STD_LOGIC; + S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); + IRQ_F2P : in STD_LOGIC_VECTOR ( 1 downto 0 ); + FCLK_CLK0 : out STD_LOGIC; + FCLK_RESET0_N : out STD_LOGIC; + MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); + DDR_CAS_n : inout STD_LOGIC; + DDR_CKE : inout STD_LOGIC; + DDR_Clk_n : inout STD_LOGIC; + DDR_Clk : inout STD_LOGIC; + DDR_CS_n : inout STD_LOGIC; + DDR_DRSTB : inout STD_LOGIC; + DDR_ODT : inout STD_LOGIC; + DDR_RAS_n : inout STD_LOGIC; + DDR_WEB : inout STD_LOGIC; + DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); + DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); + DDR_VRN : inout STD_LOGIC; + DDR_VRP : inout STD_LOGIC; + DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); + DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + PS_SRSTB : inout STD_LOGIC; + PS_CLK : inout STD_LOGIC; + PS_PORB : inout STD_LOGIC + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "mz_petalinux_processing_system7_0_0,processing_system7_v5_5_processing_system7,{}"; + attribute DowngradeIPIdentifiedWarnings : string; + attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; + attribute X_CORE_INFO : string; + attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "processing_system7_v5_5_processing_system7,Vivado 2017.4"; +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + signal NLW_inst_CAN0_PHY_TX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_CAN1_PHY_TX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_DMA0_DAVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_DMA0_DRREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_DMA0_RSTN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_DMA1_DAVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_DMA1_DRREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_DMA1_RSTN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_DMA2_DAVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_DMA2_DRREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_DMA2_RSTN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_DMA3_DAVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_DMA3_DRREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_DMA3_RSTN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET0_MDIO_MDC_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET0_MDIO_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET0_MDIO_T_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET0_SOF_RX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET0_SOF_TX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET1_MDIO_MDC_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET1_MDIO_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET1_MDIO_T_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET1_SOF_RX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_ENET1_SOF_TX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_EVENT_EVENTO_UNCONNECTED : STD_LOGIC; + signal NLW_inst_FCLK_CLK1_UNCONNECTED : STD_LOGIC; + signal NLW_inst_FCLK_CLK2_UNCONNECTED : STD_LOGIC; + signal NLW_inst_FCLK_CLK3_UNCONNECTED : STD_LOGIC; + signal NLW_inst_FCLK_RESET1_N_UNCONNECTED : STD_LOGIC; + signal NLW_inst_FCLK_RESET2_N_UNCONNECTED : STD_LOGIC; + signal NLW_inst_FCLK_RESET3_N_UNCONNECTED : STD_LOGIC; + signal NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED : STD_LOGIC; + signal NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED : STD_LOGIC; + signal NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED : STD_LOGIC; + signal NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED : STD_LOGIC; + signal NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED : STD_LOGIC; + signal NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED : STD_LOGIC; + signal NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED : STD_LOGIC; + signal NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED : STD_LOGIC; + signal NLW_inst_I2C1_SCL_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_I2C1_SCL_T_UNCONNECTED : STD_LOGIC; + signal NLW_inst_I2C1_SDA_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_I2C1_SDA_T_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_CAN0_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_CAN1_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_CTI_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_ENET0_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_ENET1_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_GPIO_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_I2C0_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_I2C1_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_QSPI_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_SMC_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_SPI0_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_SPI1_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_UART0_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_UART1_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_USB0_UNCONNECTED : STD_LOGIC; + signal NLW_inst_IRQ_P2F_USB1_UNCONNECTED : STD_LOGIC; + signal NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED : STD_LOGIC; + signal NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_PJTAG_TDO_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SDIO0_BUSPOW_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SDIO0_CLK_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SDIO0_CMD_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SDIO0_CMD_T_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SDIO0_LED_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SDIO1_BUSPOW_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SDIO1_CLK_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED : STD_LOGIC; + signal NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED : STD_LOGIC; + signal NLW_inst_TRACE_CLK_OUT_UNCONNECTED : STD_LOGIC; + signal NLW_inst_TRACE_CTL_UNCONNECTED : STD_LOGIC; + signal NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED : STD_LOGIC; + signal NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED : STD_LOGIC; + signal NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED : STD_LOGIC; + signal NLW_inst_UART0_DTRN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_UART0_RTSN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_UART0_TX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_UART1_DTRN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_UART1_RTSN_UNCONNECTED : STD_LOGIC; + signal NLW_inst_UART1_TX_UNCONNECTED : STD_LOGIC; + signal NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC; + signal NLW_inst_WDT_RST_OUT_UNCONNECTED : STD_LOGIC; + signal NLW_inst_DMA0_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_DMA1_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_DMA2_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_DMA3_DATYPE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_ENET0_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_inst_ENET1_GMII_TXD_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_inst_EVENT_STANDBYWFE_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_EVENT_STANDBYWFI_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_inst_GPIO_O_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal NLW_inst_GPIO_T_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_M_AXI_GP1_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_M_AXI_GP1_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_inst_M_AXI_GP1_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 ); + signal NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_SDIO0_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_SDIO0_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_SDIO0_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_SDIO1_BUSVOLT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_SDIO1_DATA_O_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_SDIO1_DATA_T_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal NLW_inst_S_AXI_ACP_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal NLW_inst_S_AXI_ACP_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_S_AXI_GP0_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_inst_S_AXI_GP0_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_S_AXI_GP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 ); + signal NLW_inst_S_AXI_GP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_S_AXI_HP1_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal NLW_inst_S_AXI_HP1_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_inst_S_AXI_HP2_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal NLW_inst_S_AXI_HP2_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_inst_S_AXI_HP3_BID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 ); + signal NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 63 downto 0 ); + signal NLW_inst_S_AXI_HP3_RID_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 ); + signal NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NLW_inst_TRACE_DATA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + signal NLW_inst_USB1_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 ); + attribute C_DM_WIDTH : integer; + attribute C_DM_WIDTH of inst : label is 4; + attribute C_DQS_WIDTH : integer; + attribute C_DQS_WIDTH of inst : label is 4; + attribute C_DQ_WIDTH : integer; + attribute C_DQ_WIDTH of inst : label is 32; + attribute C_EMIO_GPIO_WIDTH : integer; + attribute C_EMIO_GPIO_WIDTH of inst : label is 64; + attribute C_EN_EMIO_ENET0 : integer; + attribute C_EN_EMIO_ENET0 of inst : label is 0; + attribute C_EN_EMIO_ENET1 : integer; + attribute C_EN_EMIO_ENET1 of inst : label is 0; + attribute C_EN_EMIO_PJTAG : integer; + attribute C_EN_EMIO_PJTAG of inst : label is 0; + attribute C_EN_EMIO_TRACE : integer; + attribute C_EN_EMIO_TRACE of inst : label is 0; + attribute C_FCLK_CLK0_BUF : string; + attribute C_FCLK_CLK0_BUF of inst : label is "TRUE"; + attribute C_FCLK_CLK1_BUF : string; + attribute C_FCLK_CLK1_BUF of inst : label is "FALSE"; + attribute C_FCLK_CLK2_BUF : string; + attribute C_FCLK_CLK2_BUF of inst : label is "FALSE"; + attribute C_FCLK_CLK3_BUF : string; + attribute C_FCLK_CLK3_BUF of inst : label is "FALSE"; + attribute C_GP0_EN_MODIFIABLE_TXN : integer; + attribute C_GP0_EN_MODIFIABLE_TXN of inst : label is 1; + attribute C_GP1_EN_MODIFIABLE_TXN : integer; + attribute C_GP1_EN_MODIFIABLE_TXN of inst : label is 1; + attribute C_INCLUDE_ACP_TRANS_CHECK : integer; + attribute C_INCLUDE_ACP_TRANS_CHECK of inst : label is 0; + attribute C_INCLUDE_TRACE_BUFFER : integer; + attribute C_INCLUDE_TRACE_BUFFER of inst : label is 0; + attribute C_IRQ_F2P_MODE : string; + attribute C_IRQ_F2P_MODE of inst : label is "DIRECT"; + attribute C_MIO_PRIMITIVE : integer; + attribute C_MIO_PRIMITIVE of inst : label is 54; + attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP : integer; + attribute C_M_AXI_GP0_ENABLE_STATIC_REMAP of inst : label is 0; + attribute C_M_AXI_GP0_ID_WIDTH : integer; + attribute C_M_AXI_GP0_ID_WIDTH of inst : label is 12; + attribute C_M_AXI_GP0_THREAD_ID_WIDTH : integer; + attribute C_M_AXI_GP0_THREAD_ID_WIDTH of inst : label is 12; + attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP : integer; + attribute C_M_AXI_GP1_ENABLE_STATIC_REMAP of inst : label is 0; + attribute C_M_AXI_GP1_ID_WIDTH : integer; + attribute C_M_AXI_GP1_ID_WIDTH of inst : label is 12; + attribute C_M_AXI_GP1_THREAD_ID_WIDTH : integer; + attribute C_M_AXI_GP1_THREAD_ID_WIDTH of inst : label is 12; + attribute C_NUM_F2P_INTR_INPUTS : integer; + attribute C_NUM_F2P_INTR_INPUTS of inst : label is 2; + attribute C_PACKAGE_NAME : string; + attribute C_PACKAGE_NAME of inst : label is "clg400"; + attribute C_PS7_SI_REV : string; + attribute C_PS7_SI_REV of inst : label is "PRODUCTION"; + attribute C_S_AXI_ACP_ARUSER_VAL : integer; + attribute C_S_AXI_ACP_ARUSER_VAL of inst : label is 31; + attribute C_S_AXI_ACP_AWUSER_VAL : integer; + attribute C_S_AXI_ACP_AWUSER_VAL of inst : label is 31; + attribute C_S_AXI_ACP_ID_WIDTH : integer; + attribute C_S_AXI_ACP_ID_WIDTH of inst : label is 3; + attribute C_S_AXI_GP0_ID_WIDTH : integer; + attribute C_S_AXI_GP0_ID_WIDTH of inst : label is 6; + attribute C_S_AXI_GP1_ID_WIDTH : integer; + attribute C_S_AXI_GP1_ID_WIDTH of inst : label is 6; + attribute C_S_AXI_HP0_DATA_WIDTH : integer; + attribute C_S_AXI_HP0_DATA_WIDTH of inst : label is 64; + attribute C_S_AXI_HP0_ID_WIDTH : integer; + attribute C_S_AXI_HP0_ID_WIDTH of inst : label is 6; + attribute C_S_AXI_HP1_DATA_WIDTH : integer; + attribute C_S_AXI_HP1_DATA_WIDTH of inst : label is 64; + attribute C_S_AXI_HP1_ID_WIDTH : integer; + attribute C_S_AXI_HP1_ID_WIDTH of inst : label is 6; + attribute C_S_AXI_HP2_DATA_WIDTH : integer; + attribute C_S_AXI_HP2_DATA_WIDTH of inst : label is 64; + attribute C_S_AXI_HP2_ID_WIDTH : integer; + attribute C_S_AXI_HP2_ID_WIDTH of inst : label is 6; + attribute C_S_AXI_HP3_DATA_WIDTH : integer; + attribute C_S_AXI_HP3_DATA_WIDTH of inst : label is 64; + attribute C_S_AXI_HP3_ID_WIDTH : integer; + attribute C_S_AXI_HP3_ID_WIDTH of inst : label is 6; + attribute C_TRACE_BUFFER_CLOCK_DELAY : integer; + attribute C_TRACE_BUFFER_CLOCK_DELAY of inst : label is 12; + attribute C_TRACE_BUFFER_FIFO_SIZE : integer; + attribute C_TRACE_BUFFER_FIFO_SIZE of inst : label is 128; + attribute C_TRACE_INTERNAL_WIDTH : integer; + attribute C_TRACE_INTERNAL_WIDTH of inst : label is 2; + attribute C_TRACE_PIPELINE_WIDTH : integer; + attribute C_TRACE_PIPELINE_WIDTH of inst : label is 8; + attribute C_USE_AXI_NONSECURE : integer; + attribute C_USE_AXI_NONSECURE of inst : label is 0; + attribute C_USE_DEFAULT_ACP_USER_VAL : integer; + attribute C_USE_DEFAULT_ACP_USER_VAL of inst : label is 0; + attribute C_USE_M_AXI_GP0 : integer; + attribute C_USE_M_AXI_GP0 of inst : label is 1; + attribute C_USE_M_AXI_GP1 : integer; + attribute C_USE_M_AXI_GP1 of inst : label is 0; + attribute C_USE_S_AXI_ACP : integer; + attribute C_USE_S_AXI_ACP of inst : label is 0; + attribute C_USE_S_AXI_GP0 : integer; + attribute C_USE_S_AXI_GP0 of inst : label is 0; + attribute C_USE_S_AXI_GP1 : integer; + attribute C_USE_S_AXI_GP1 of inst : label is 0; + attribute C_USE_S_AXI_HP0 : integer; + attribute C_USE_S_AXI_HP0 of inst : label is 1; + attribute C_USE_S_AXI_HP1 : integer; + attribute C_USE_S_AXI_HP1 of inst : label is 0; + attribute C_USE_S_AXI_HP2 : integer; + attribute C_USE_S_AXI_HP2 of inst : label is 0; + attribute C_USE_S_AXI_HP3 : integer; + attribute C_USE_S_AXI_HP3 of inst : label is 0; + attribute HW_HANDOFF : string; + attribute HW_HANDOFF of inst : label is "mz_petalinux_processing_system7_0_0.hwdef"; + attribute POWER : string; + attribute POWER of inst : label is "/>"; + attribute USE_TRACE_DATA_EDGE_DETECTOR : integer; + attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0; + attribute X_INTERFACE_INFO : string; + attribute X_INTERFACE_INFO of DDR_CAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CAS_N"; + attribute X_INTERFACE_INFO of DDR_CKE : signal is "xilinx.com:interface:ddrx:1.0 DDR CKE"; + attribute X_INTERFACE_INFO of DDR_CS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CS_N"; + attribute X_INTERFACE_INFO of DDR_Clk : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_P"; + attribute X_INTERFACE_INFO of DDR_Clk_n : signal is "xilinx.com:interface:ddrx:1.0 DDR CK_N"; + attribute X_INTERFACE_INFO of DDR_DRSTB : signal is "xilinx.com:interface:ddrx:1.0 DDR RESET_N"; + attribute X_INTERFACE_INFO of DDR_ODT : signal is "xilinx.com:interface:ddrx:1.0 DDR ODT"; + attribute X_INTERFACE_INFO of DDR_RAS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR RAS_N"; + attribute X_INTERFACE_INFO of DDR_VRN : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRN"; + attribute X_INTERFACE_INFO of DDR_VRP : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO DDR_VRP"; + attribute X_INTERFACE_INFO of DDR_WEB : signal is "xilinx.com:interface:ddrx:1.0 DDR WE_N"; + attribute X_INTERFACE_INFO of FCLK_CLK0 : signal is "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK"; + attribute X_INTERFACE_PARAMETER : string; + attribute X_INTERFACE_PARAMETER of FCLK_CLK0 : signal is "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 99999999, PHASE 0.000, CLK_DOMAIN mz_petalinux_processing_system7_0_0_FCLK_CLK0"; + attribute X_INTERFACE_INFO of FCLK_RESET0_N : signal is "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST"; + attribute X_INTERFACE_PARAMETER of FCLK_RESET0_N : signal is "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW"; + attribute X_INTERFACE_INFO of I2C0_SCL_I : signal is "xilinx.com:interface:iic:1.0 IIC_0 SCL_I"; + attribute X_INTERFACE_INFO of I2C0_SCL_O : signal is "xilinx.com:interface:iic:1.0 IIC_0 SCL_O"; + attribute X_INTERFACE_INFO of I2C0_SCL_T : signal is "xilinx.com:interface:iic:1.0 IIC_0 SCL_T"; + attribute X_INTERFACE_INFO of I2C0_SDA_I : signal is "xilinx.com:interface:iic:1.0 IIC_0 SDA_I"; + attribute X_INTERFACE_INFO of I2C0_SDA_O : signal is "xilinx.com:interface:iic:1.0 IIC_0 SDA_O"; + attribute X_INTERFACE_INFO of I2C0_SDA_T : signal is "xilinx.com:interface:iic:1.0 IIC_0 SDA_T"; + attribute X_INTERFACE_INFO of M_AXI_GP0_ACLK : signal is "xilinx.com:signal:clock:1.0 M_AXI_GP0_ACLK CLK"; + attribute X_INTERFACE_PARAMETER of M_AXI_GP0_ACLK : signal is "XIL_INTERFACENAME M_AXI_GP0_ACLK, ASSOCIATED_BUSIF M_AXI_GP0, FREQ_HZ 99999999, PHASE 0.000, CLK_DOMAIN mz_petalinux_processing_system7_0_0_FCLK_CLK0"; + attribute X_INTERFACE_INFO of M_AXI_GP0_ARREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARREADY"; + attribute X_INTERFACE_INFO of M_AXI_GP0_ARVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARVALID"; + attribute X_INTERFACE_INFO of M_AXI_GP0_AWREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWREADY"; + attribute X_INTERFACE_INFO of M_AXI_GP0_AWVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWVALID"; + attribute X_INTERFACE_INFO of M_AXI_GP0_BREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BREADY"; + attribute X_INTERFACE_INFO of M_AXI_GP0_BVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BVALID"; + attribute X_INTERFACE_INFO of M_AXI_GP0_RLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RLAST"; + attribute X_INTERFACE_INFO of M_AXI_GP0_RREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RREADY"; + attribute X_INTERFACE_INFO of M_AXI_GP0_RVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RVALID"; + attribute X_INTERFACE_INFO of M_AXI_GP0_WLAST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WLAST"; + attribute X_INTERFACE_INFO of M_AXI_GP0_WREADY : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WREADY"; + attribute X_INTERFACE_INFO of M_AXI_GP0_WVALID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WVALID"; + attribute X_INTERFACE_INFO of PS_CLK : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_CLK"; + attribute X_INTERFACE_INFO of PS_PORB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB"; + attribute X_INTERFACE_PARAMETER of PS_PORB : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false"; + attribute X_INTERFACE_INFO of PS_SRSTB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB"; + attribute X_INTERFACE_INFO of SPI1_MISO_I : signal is "xilinx.com:interface:spi:1.0 SPI_1 IO1_I"; + attribute X_INTERFACE_INFO of SPI1_MISO_O : signal is "xilinx.com:interface:spi:1.0 SPI_1 IO1_O"; + attribute X_INTERFACE_INFO of SPI1_MISO_T : signal is "xilinx.com:interface:spi:1.0 SPI_1 IO1_T"; + attribute X_INTERFACE_INFO of SPI1_MOSI_I : signal is "xilinx.com:interface:spi:1.0 SPI_1 IO0_I"; + attribute X_INTERFACE_INFO of SPI1_MOSI_O : signal is "xilinx.com:interface:spi:1.0 SPI_1 IO0_O"; + attribute X_INTERFACE_INFO of SPI1_MOSI_T : signal is "xilinx.com:interface:spi:1.0 SPI_1 IO0_T"; + attribute X_INTERFACE_INFO of SPI1_SCLK_I : signal is "xilinx.com:interface:spi:1.0 SPI_1 SCK_I"; + attribute X_INTERFACE_INFO of SPI1_SCLK_O : signal is "xilinx.com:interface:spi:1.0 SPI_1 SCK_O"; + attribute X_INTERFACE_INFO of SPI1_SCLK_T : signal is "xilinx.com:interface:spi:1.0 SPI_1 SCK_T"; + attribute X_INTERFACE_INFO of SPI1_SS1_O : signal is "xilinx.com:interface:spi:1.0 SPI_1 SS1_O"; + attribute X_INTERFACE_INFO of SPI1_SS2_O : signal is "xilinx.com:interface:spi:1.0 SPI_1 SS2_O"; + attribute X_INTERFACE_INFO of SPI1_SS_I : signal is "xilinx.com:interface:spi:1.0 SPI_1 SS_I"; + attribute X_INTERFACE_INFO of SPI1_SS_O : signal is "xilinx.com:interface:spi:1.0 SPI_1 SS_O"; + attribute X_INTERFACE_INFO of SPI1_SS_T : signal is "xilinx.com:interface:spi:1.0 SPI_1 SS_T"; + attribute X_INTERFACE_INFO of S_AXI_HP0_ACLK : signal is "xilinx.com:signal:clock:1.0 S_AXI_HP0_ACLK CLK"; + attribute X_INTERFACE_PARAMETER of S_AXI_HP0_ACLK : signal is "XIL_INTERFACENAME S_AXI_HP0_ACLK, ASSOCIATED_BUSIF S_AXI_HP0, FREQ_HZ 99999999, PHASE 0.000, CLK_DOMAIN mz_petalinux_processing_system7_0_0_FCLK_CLK0"; + attribute X_INTERFACE_INFO of S_AXI_HP0_ARREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARREADY"; + attribute X_INTERFACE_INFO of S_AXI_HP0_ARVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARVALID"; + attribute X_INTERFACE_INFO of S_AXI_HP0_AWREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWREADY"; + attribute X_INTERFACE_INFO of S_AXI_HP0_AWVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWVALID"; + attribute X_INTERFACE_INFO of S_AXI_HP0_BREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BREADY"; + attribute X_INTERFACE_INFO of S_AXI_HP0_BVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BVALID"; + attribute X_INTERFACE_INFO of S_AXI_HP0_RDISSUECAP1_EN : signal is "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RDISSUECAPEN"; + attribute X_INTERFACE_INFO of S_AXI_HP0_RLAST : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RLAST"; + attribute X_INTERFACE_INFO of S_AXI_HP0_RREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RREADY"; + attribute X_INTERFACE_INFO of S_AXI_HP0_RVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RVALID"; + attribute X_INTERFACE_INFO of S_AXI_HP0_WLAST : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WLAST"; + attribute X_INTERFACE_INFO of S_AXI_HP0_WREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WREADY"; + attribute X_INTERFACE_INFO of S_AXI_HP0_WRISSUECAP1_EN : signal is "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WRISSUECAPEN"; + attribute X_INTERFACE_INFO of S_AXI_HP0_WVALID : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WVALID"; + attribute X_INTERFACE_INFO of USB0_VBUS_PWRFAULT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRFAULT"; + attribute X_INTERFACE_INFO of USB0_VBUS_PWRSELECT : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 VBUS_PWRSELECT"; + attribute X_INTERFACE_INFO of DDR_Addr : signal is "xilinx.com:interface:ddrx:1.0 DDR ADDR"; + attribute X_INTERFACE_INFO of DDR_BankAddr : signal is "xilinx.com:interface:ddrx:1.0 DDR BA"; + attribute X_INTERFACE_INFO of DDR_DM : signal is "xilinx.com:interface:ddrx:1.0 DDR DM"; + attribute X_INTERFACE_INFO of DDR_DQ : signal is "xilinx.com:interface:ddrx:1.0 DDR DQ"; + attribute X_INTERFACE_INFO of DDR_DQS : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_P"; + attribute X_INTERFACE_PARAMETER of DDR_DQS : signal is "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11"; + attribute X_INTERFACE_INFO of DDR_DQS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N"; + attribute X_INTERFACE_INFO of IRQ_F2P : signal is "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT"; + attribute X_INTERFACE_PARAMETER of IRQ_F2P : signal is "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH:NULL, PortWidth 2"; + attribute X_INTERFACE_INFO of MIO : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO"; + attribute X_INTERFACE_INFO of M_AXI_GP0_ARADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR"; + attribute X_INTERFACE_INFO of M_AXI_GP0_ARBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST"; + attribute X_INTERFACE_INFO of M_AXI_GP0_ARCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARCACHE"; + attribute X_INTERFACE_INFO of M_AXI_GP0_ARID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARID"; + attribute X_INTERFACE_INFO of M_AXI_GP0_ARLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLEN"; + attribute X_INTERFACE_INFO of M_AXI_GP0_ARLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARLOCK"; + attribute X_INTERFACE_INFO of M_AXI_GP0_ARPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARPROT"; + attribute X_INTERFACE_INFO of M_AXI_GP0_ARQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARQOS"; + attribute X_INTERFACE_INFO of M_AXI_GP0_ARSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARSIZE"; + attribute X_INTERFACE_INFO of M_AXI_GP0_AWADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWADDR"; + attribute X_INTERFACE_INFO of M_AXI_GP0_AWBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWBURST"; + attribute X_INTERFACE_INFO of M_AXI_GP0_AWCACHE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWCACHE"; + attribute X_INTERFACE_INFO of M_AXI_GP0_AWID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWID"; + attribute X_INTERFACE_INFO of M_AXI_GP0_AWLEN : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLEN"; + attribute X_INTERFACE_INFO of M_AXI_GP0_AWLOCK : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWLOCK"; + attribute X_INTERFACE_INFO of M_AXI_GP0_AWPROT : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWPROT"; + attribute X_INTERFACE_INFO of M_AXI_GP0_AWQOS : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWQOS"; + attribute X_INTERFACE_INFO of M_AXI_GP0_AWSIZE : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 AWSIZE"; + attribute X_INTERFACE_INFO of M_AXI_GP0_BID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BID"; + attribute X_INTERFACE_INFO of M_AXI_GP0_BRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 BRESP"; + attribute X_INTERFACE_INFO of M_AXI_GP0_RDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RDATA"; + attribute X_INTERFACE_PARAMETER of M_AXI_GP0_RDATA : signal is "XIL_INTERFACENAME M_AXI_GP0, SUPPORTS_NARROW_BURST 0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 99999999, ID_WIDTH 12, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN mz_petalinux_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 4, NUM_WRITE_THREADS 4, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; + attribute X_INTERFACE_INFO of M_AXI_GP0_RID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RID"; + attribute X_INTERFACE_INFO of M_AXI_GP0_RRESP : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 RRESP"; + attribute X_INTERFACE_INFO of M_AXI_GP0_WDATA : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WDATA"; + attribute X_INTERFACE_INFO of M_AXI_GP0_WID : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WID"; + attribute X_INTERFACE_INFO of M_AXI_GP0_WSTRB : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 WSTRB"; + attribute X_INTERFACE_INFO of S_AXI_HP0_ARADDR : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARADDR"; + attribute X_INTERFACE_INFO of S_AXI_HP0_ARBURST : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARBURST"; + attribute X_INTERFACE_INFO of S_AXI_HP0_ARCACHE : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARCACHE"; + attribute X_INTERFACE_INFO of S_AXI_HP0_ARID : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARID"; + attribute X_INTERFACE_INFO of S_AXI_HP0_ARLEN : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARLEN"; + attribute X_INTERFACE_INFO of S_AXI_HP0_ARLOCK : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARLOCK"; + attribute X_INTERFACE_INFO of S_AXI_HP0_ARPROT : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARPROT"; + attribute X_INTERFACE_INFO of S_AXI_HP0_ARQOS : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARQOS"; + attribute X_INTERFACE_INFO of S_AXI_HP0_ARSIZE : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARSIZE"; + attribute X_INTERFACE_INFO of S_AXI_HP0_AWADDR : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWADDR"; + attribute X_INTERFACE_INFO of S_AXI_HP0_AWBURST : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWBURST"; + attribute X_INTERFACE_INFO of S_AXI_HP0_AWCACHE : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWCACHE"; + attribute X_INTERFACE_INFO of S_AXI_HP0_AWID : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWID"; + attribute X_INTERFACE_INFO of S_AXI_HP0_AWLEN : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWLEN"; + attribute X_INTERFACE_INFO of S_AXI_HP0_AWLOCK : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWLOCK"; + attribute X_INTERFACE_INFO of S_AXI_HP0_AWPROT : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWPROT"; + attribute X_INTERFACE_INFO of S_AXI_HP0_AWQOS : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWQOS"; + attribute X_INTERFACE_INFO of S_AXI_HP0_AWSIZE : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 AWSIZE"; + attribute X_INTERFACE_INFO of S_AXI_HP0_BID : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BID"; + attribute X_INTERFACE_INFO of S_AXI_HP0_BRESP : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 BRESP"; + attribute X_INTERFACE_INFO of S_AXI_HP0_RACOUNT : signal is "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RACOUNT"; + attribute X_INTERFACE_INFO of S_AXI_HP0_RCOUNT : signal is "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL RCOUNT"; + attribute X_INTERFACE_INFO of S_AXI_HP0_RDATA : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RDATA"; + attribute X_INTERFACE_INFO of S_AXI_HP0_RID : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RID"; + attribute X_INTERFACE_INFO of S_AXI_HP0_RRESP : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 RRESP"; + attribute X_INTERFACE_INFO of S_AXI_HP0_WACOUNT : signal is "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WACOUNT"; + attribute X_INTERFACE_INFO of S_AXI_HP0_WCOUNT : signal is "xilinx.com:display_processing_system7:hpstatusctrl:1.0 S_AXI_HP0_FIFO_CTRL WCOUNT"; + attribute X_INTERFACE_INFO of S_AXI_HP0_WDATA : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WDATA"; + attribute X_INTERFACE_INFO of S_AXI_HP0_WID : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WID"; + attribute X_INTERFACE_INFO of S_AXI_HP0_WSTRB : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WSTRB"; + attribute X_INTERFACE_PARAMETER of S_AXI_HP0_WSTRB : signal is "XIL_INTERFACENAME S_AXI_HP0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 64, PROTOCOL AXI3, FREQ_HZ 99999999, ID_WIDTH 6, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, MAX_BURST_LENGTH 8, PHASE 0.000, CLK_DOMAIN mz_petalinux_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0"; + attribute X_INTERFACE_INFO of USB0_PORT_INDCTL : signal is "xilinx.com:display_processing_system7:usbctrl:1.0 USBIND_0 PORT_INDCTL"; +begin +inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_processing_system7_v5_5_processing_system7 + port map ( + CAN0_PHY_RX => '0', + CAN0_PHY_TX => NLW_inst_CAN0_PHY_TX_UNCONNECTED, + CAN1_PHY_RX => '0', + CAN1_PHY_TX => NLW_inst_CAN1_PHY_TX_UNCONNECTED, + Core0_nFIQ => '0', + Core0_nIRQ => '0', + Core1_nFIQ => '0', + Core1_nIRQ => '0', + DDR_ARB(3 downto 0) => B"0000", + DDR_Addr(14 downto 0) => DDR_Addr(14 downto 0), + DDR_BankAddr(2 downto 0) => DDR_BankAddr(2 downto 0), + DDR_CAS_n => DDR_CAS_n, + DDR_CKE => DDR_CKE, + DDR_CS_n => DDR_CS_n, + DDR_Clk => DDR_Clk, + DDR_Clk_n => DDR_Clk_n, + DDR_DM(3 downto 0) => DDR_DM(3 downto 0), + DDR_DQ(31 downto 0) => DDR_DQ(31 downto 0), + DDR_DQS(3 downto 0) => DDR_DQS(3 downto 0), + DDR_DQS_n(3 downto 0) => DDR_DQS_n(3 downto 0), + DDR_DRSTB => DDR_DRSTB, + DDR_ODT => DDR_ODT, + DDR_RAS_n => DDR_RAS_n, + DDR_VRN => DDR_VRN, + DDR_VRP => DDR_VRP, + DDR_WEB => DDR_WEB, + DMA0_ACLK => '0', + DMA0_DAREADY => '0', + DMA0_DATYPE(1 downto 0) => NLW_inst_DMA0_DATYPE_UNCONNECTED(1 downto 0), + DMA0_DAVALID => NLW_inst_DMA0_DAVALID_UNCONNECTED, + DMA0_DRLAST => '0', + DMA0_DRREADY => NLW_inst_DMA0_DRREADY_UNCONNECTED, + DMA0_DRTYPE(1 downto 0) => B"00", + DMA0_DRVALID => '0', + DMA0_RSTN => NLW_inst_DMA0_RSTN_UNCONNECTED, + DMA1_ACLK => '0', + DMA1_DAREADY => '0', + DMA1_DATYPE(1 downto 0) => NLW_inst_DMA1_DATYPE_UNCONNECTED(1 downto 0), + DMA1_DAVALID => NLW_inst_DMA1_DAVALID_UNCONNECTED, + DMA1_DRLAST => '0', + DMA1_DRREADY => NLW_inst_DMA1_DRREADY_UNCONNECTED, + DMA1_DRTYPE(1 downto 0) => B"00", + DMA1_DRVALID => '0', + DMA1_RSTN => NLW_inst_DMA1_RSTN_UNCONNECTED, + DMA2_ACLK => '0', + DMA2_DAREADY => '0', + DMA2_DATYPE(1 downto 0) => NLW_inst_DMA2_DATYPE_UNCONNECTED(1 downto 0), + DMA2_DAVALID => NLW_inst_DMA2_DAVALID_UNCONNECTED, + DMA2_DRLAST => '0', + DMA2_DRREADY => NLW_inst_DMA2_DRREADY_UNCONNECTED, + DMA2_DRTYPE(1 downto 0) => B"00", + DMA2_DRVALID => '0', + DMA2_RSTN => NLW_inst_DMA2_RSTN_UNCONNECTED, + DMA3_ACLK => '0', + DMA3_DAREADY => '0', + DMA3_DATYPE(1 downto 0) => NLW_inst_DMA3_DATYPE_UNCONNECTED(1 downto 0), + DMA3_DAVALID => NLW_inst_DMA3_DAVALID_UNCONNECTED, + DMA3_DRLAST => '0', + DMA3_DRREADY => NLW_inst_DMA3_DRREADY_UNCONNECTED, + DMA3_DRTYPE(1 downto 0) => B"00", + DMA3_DRVALID => '0', + DMA3_RSTN => NLW_inst_DMA3_RSTN_UNCONNECTED, + ENET0_EXT_INTIN => '0', + ENET0_GMII_COL => '0', + ENET0_GMII_CRS => '0', + ENET0_GMII_RXD(7 downto 0) => B"00000000", + ENET0_GMII_RX_CLK => '0', + ENET0_GMII_RX_DV => '0', + ENET0_GMII_RX_ER => '0', + ENET0_GMII_TXD(7 downto 0) => NLW_inst_ENET0_GMII_TXD_UNCONNECTED(7 downto 0), + ENET0_GMII_TX_CLK => '0', + ENET0_GMII_TX_EN => NLW_inst_ENET0_GMII_TX_EN_UNCONNECTED, + ENET0_GMII_TX_ER => NLW_inst_ENET0_GMII_TX_ER_UNCONNECTED, + ENET0_MDIO_I => '0', + ENET0_MDIO_MDC => NLW_inst_ENET0_MDIO_MDC_UNCONNECTED, + ENET0_MDIO_O => NLW_inst_ENET0_MDIO_O_UNCONNECTED, + ENET0_MDIO_T => NLW_inst_ENET0_MDIO_T_UNCONNECTED, + ENET0_PTP_DELAY_REQ_RX => NLW_inst_ENET0_PTP_DELAY_REQ_RX_UNCONNECTED, + ENET0_PTP_DELAY_REQ_TX => NLW_inst_ENET0_PTP_DELAY_REQ_TX_UNCONNECTED, + ENET0_PTP_PDELAY_REQ_RX => NLW_inst_ENET0_PTP_PDELAY_REQ_RX_UNCONNECTED, + ENET0_PTP_PDELAY_REQ_TX => NLW_inst_ENET0_PTP_PDELAY_REQ_TX_UNCONNECTED, + ENET0_PTP_PDELAY_RESP_RX => NLW_inst_ENET0_PTP_PDELAY_RESP_RX_UNCONNECTED, + ENET0_PTP_PDELAY_RESP_TX => NLW_inst_ENET0_PTP_PDELAY_RESP_TX_UNCONNECTED, + ENET0_PTP_SYNC_FRAME_RX => NLW_inst_ENET0_PTP_SYNC_FRAME_RX_UNCONNECTED, + ENET0_PTP_SYNC_FRAME_TX => NLW_inst_ENET0_PTP_SYNC_FRAME_TX_UNCONNECTED, + ENET0_SOF_RX => NLW_inst_ENET0_SOF_RX_UNCONNECTED, + ENET0_SOF_TX => NLW_inst_ENET0_SOF_TX_UNCONNECTED, + ENET1_EXT_INTIN => '0', + ENET1_GMII_COL => '0', + ENET1_GMII_CRS => '0', + ENET1_GMII_RXD(7 downto 0) => B"00000000", + ENET1_GMII_RX_CLK => '0', + ENET1_GMII_RX_DV => '0', + ENET1_GMII_RX_ER => '0', + ENET1_GMII_TXD(7 downto 0) => NLW_inst_ENET1_GMII_TXD_UNCONNECTED(7 downto 0), + ENET1_GMII_TX_CLK => '0', + ENET1_GMII_TX_EN => NLW_inst_ENET1_GMII_TX_EN_UNCONNECTED, + ENET1_GMII_TX_ER => NLW_inst_ENET1_GMII_TX_ER_UNCONNECTED, + ENET1_MDIO_I => '0', + ENET1_MDIO_MDC => NLW_inst_ENET1_MDIO_MDC_UNCONNECTED, + ENET1_MDIO_O => NLW_inst_ENET1_MDIO_O_UNCONNECTED, + ENET1_MDIO_T => NLW_inst_ENET1_MDIO_T_UNCONNECTED, + ENET1_PTP_DELAY_REQ_RX => NLW_inst_ENET1_PTP_DELAY_REQ_RX_UNCONNECTED, + ENET1_PTP_DELAY_REQ_TX => NLW_inst_ENET1_PTP_DELAY_REQ_TX_UNCONNECTED, + ENET1_PTP_PDELAY_REQ_RX => NLW_inst_ENET1_PTP_PDELAY_REQ_RX_UNCONNECTED, + ENET1_PTP_PDELAY_REQ_TX => NLW_inst_ENET1_PTP_PDELAY_REQ_TX_UNCONNECTED, + ENET1_PTP_PDELAY_RESP_RX => NLW_inst_ENET1_PTP_PDELAY_RESP_RX_UNCONNECTED, + ENET1_PTP_PDELAY_RESP_TX => NLW_inst_ENET1_PTP_PDELAY_RESP_TX_UNCONNECTED, + ENET1_PTP_SYNC_FRAME_RX => NLW_inst_ENET1_PTP_SYNC_FRAME_RX_UNCONNECTED, + ENET1_PTP_SYNC_FRAME_TX => NLW_inst_ENET1_PTP_SYNC_FRAME_TX_UNCONNECTED, + ENET1_SOF_RX => NLW_inst_ENET1_SOF_RX_UNCONNECTED, + ENET1_SOF_TX => NLW_inst_ENET1_SOF_TX_UNCONNECTED, + EVENT_EVENTI => '0', + EVENT_EVENTO => NLW_inst_EVENT_EVENTO_UNCONNECTED, + EVENT_STANDBYWFE(1 downto 0) => NLW_inst_EVENT_STANDBYWFE_UNCONNECTED(1 downto 0), + EVENT_STANDBYWFI(1 downto 0) => NLW_inst_EVENT_STANDBYWFI_UNCONNECTED(1 downto 0), + FCLK_CLK0 => FCLK_CLK0, + FCLK_CLK1 => NLW_inst_FCLK_CLK1_UNCONNECTED, + FCLK_CLK2 => NLW_inst_FCLK_CLK2_UNCONNECTED, + FCLK_CLK3 => NLW_inst_FCLK_CLK3_UNCONNECTED, + FCLK_CLKTRIG0_N => '0', + FCLK_CLKTRIG1_N => '0', + FCLK_CLKTRIG2_N => '0', + FCLK_CLKTRIG3_N => '0', + FCLK_RESET0_N => FCLK_RESET0_N, + FCLK_RESET1_N => NLW_inst_FCLK_RESET1_N_UNCONNECTED, + FCLK_RESET2_N => NLW_inst_FCLK_RESET2_N_UNCONNECTED, + FCLK_RESET3_N => NLW_inst_FCLK_RESET3_N_UNCONNECTED, + FPGA_IDLE_N => '0', + FTMD_TRACEIN_ATID(3 downto 0) => B"0000", + FTMD_TRACEIN_CLK => '0', + FTMD_TRACEIN_DATA(31 downto 0) => B"00000000000000000000000000000000", + FTMD_TRACEIN_VALID => '0', + FTMT_F2P_DEBUG(31 downto 0) => B"00000000000000000000000000000000", + FTMT_F2P_TRIGACK_0 => NLW_inst_FTMT_F2P_TRIGACK_0_UNCONNECTED, + FTMT_F2P_TRIGACK_1 => NLW_inst_FTMT_F2P_TRIGACK_1_UNCONNECTED, + FTMT_F2P_TRIGACK_2 => NLW_inst_FTMT_F2P_TRIGACK_2_UNCONNECTED, + FTMT_F2P_TRIGACK_3 => NLW_inst_FTMT_F2P_TRIGACK_3_UNCONNECTED, + FTMT_F2P_TRIG_0 => '0', + FTMT_F2P_TRIG_1 => '0', + FTMT_F2P_TRIG_2 => '0', + FTMT_F2P_TRIG_3 => '0', + FTMT_P2F_DEBUG(31 downto 0) => NLW_inst_FTMT_P2F_DEBUG_UNCONNECTED(31 downto 0), + FTMT_P2F_TRIGACK_0 => '0', + FTMT_P2F_TRIGACK_1 => '0', + FTMT_P2F_TRIGACK_2 => '0', + FTMT_P2F_TRIGACK_3 => '0', + FTMT_P2F_TRIG_0 => NLW_inst_FTMT_P2F_TRIG_0_UNCONNECTED, + FTMT_P2F_TRIG_1 => NLW_inst_FTMT_P2F_TRIG_1_UNCONNECTED, + FTMT_P2F_TRIG_2 => NLW_inst_FTMT_P2F_TRIG_2_UNCONNECTED, + FTMT_P2F_TRIG_3 => NLW_inst_FTMT_P2F_TRIG_3_UNCONNECTED, + GPIO_I(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + GPIO_O(63 downto 0) => NLW_inst_GPIO_O_UNCONNECTED(63 downto 0), + GPIO_T(63 downto 0) => NLW_inst_GPIO_T_UNCONNECTED(63 downto 0), + I2C0_SCL_I => I2C0_SCL_I, + I2C0_SCL_O => I2C0_SCL_O, + I2C0_SCL_T => I2C0_SCL_T, + I2C0_SDA_I => I2C0_SDA_I, + I2C0_SDA_O => I2C0_SDA_O, + I2C0_SDA_T => I2C0_SDA_T, + I2C1_SCL_I => '0', + I2C1_SCL_O => NLW_inst_I2C1_SCL_O_UNCONNECTED, + I2C1_SCL_T => NLW_inst_I2C1_SCL_T_UNCONNECTED, + I2C1_SDA_I => '0', + I2C1_SDA_O => NLW_inst_I2C1_SDA_O_UNCONNECTED, + I2C1_SDA_T => NLW_inst_I2C1_SDA_T_UNCONNECTED, + IRQ_F2P(1 downto 0) => IRQ_F2P(1 downto 0), + IRQ_P2F_CAN0 => NLW_inst_IRQ_P2F_CAN0_UNCONNECTED, + IRQ_P2F_CAN1 => NLW_inst_IRQ_P2F_CAN1_UNCONNECTED, + IRQ_P2F_CTI => NLW_inst_IRQ_P2F_CTI_UNCONNECTED, + IRQ_P2F_DMAC0 => NLW_inst_IRQ_P2F_DMAC0_UNCONNECTED, + IRQ_P2F_DMAC1 => NLW_inst_IRQ_P2F_DMAC1_UNCONNECTED, + IRQ_P2F_DMAC2 => NLW_inst_IRQ_P2F_DMAC2_UNCONNECTED, + IRQ_P2F_DMAC3 => NLW_inst_IRQ_P2F_DMAC3_UNCONNECTED, + IRQ_P2F_DMAC4 => NLW_inst_IRQ_P2F_DMAC4_UNCONNECTED, + IRQ_P2F_DMAC5 => NLW_inst_IRQ_P2F_DMAC5_UNCONNECTED, + IRQ_P2F_DMAC6 => NLW_inst_IRQ_P2F_DMAC6_UNCONNECTED, + IRQ_P2F_DMAC7 => NLW_inst_IRQ_P2F_DMAC7_UNCONNECTED, + IRQ_P2F_DMAC_ABORT => NLW_inst_IRQ_P2F_DMAC_ABORT_UNCONNECTED, + IRQ_P2F_ENET0 => NLW_inst_IRQ_P2F_ENET0_UNCONNECTED, + IRQ_P2F_ENET1 => NLW_inst_IRQ_P2F_ENET1_UNCONNECTED, + IRQ_P2F_ENET_WAKE0 => NLW_inst_IRQ_P2F_ENET_WAKE0_UNCONNECTED, + IRQ_P2F_ENET_WAKE1 => NLW_inst_IRQ_P2F_ENET_WAKE1_UNCONNECTED, + IRQ_P2F_GPIO => NLW_inst_IRQ_P2F_GPIO_UNCONNECTED, + IRQ_P2F_I2C0 => NLW_inst_IRQ_P2F_I2C0_UNCONNECTED, + IRQ_P2F_I2C1 => NLW_inst_IRQ_P2F_I2C1_UNCONNECTED, + IRQ_P2F_QSPI => NLW_inst_IRQ_P2F_QSPI_UNCONNECTED, + IRQ_P2F_SDIO0 => NLW_inst_IRQ_P2F_SDIO0_UNCONNECTED, + IRQ_P2F_SDIO1 => NLW_inst_IRQ_P2F_SDIO1_UNCONNECTED, + IRQ_P2F_SMC => NLW_inst_IRQ_P2F_SMC_UNCONNECTED, + IRQ_P2F_SPI0 => NLW_inst_IRQ_P2F_SPI0_UNCONNECTED, + IRQ_P2F_SPI1 => NLW_inst_IRQ_P2F_SPI1_UNCONNECTED, + IRQ_P2F_UART0 => NLW_inst_IRQ_P2F_UART0_UNCONNECTED, + IRQ_P2F_UART1 => NLW_inst_IRQ_P2F_UART1_UNCONNECTED, + IRQ_P2F_USB0 => NLW_inst_IRQ_P2F_USB0_UNCONNECTED, + IRQ_P2F_USB1 => NLW_inst_IRQ_P2F_USB1_UNCONNECTED, + MIO(53 downto 0) => MIO(53 downto 0), + M_AXI_GP0_ACLK => M_AXI_GP0_ACLK, + M_AXI_GP0_ARADDR(31 downto 0) => M_AXI_GP0_ARADDR(31 downto 0), + M_AXI_GP0_ARBURST(1 downto 0) => M_AXI_GP0_ARBURST(1 downto 0), + M_AXI_GP0_ARCACHE(3 downto 0) => M_AXI_GP0_ARCACHE(3 downto 0), + M_AXI_GP0_ARESETN => NLW_inst_M_AXI_GP0_ARESETN_UNCONNECTED, + M_AXI_GP0_ARID(11 downto 0) => M_AXI_GP0_ARID(11 downto 0), + M_AXI_GP0_ARLEN(3 downto 0) => M_AXI_GP0_ARLEN(3 downto 0), + M_AXI_GP0_ARLOCK(1 downto 0) => M_AXI_GP0_ARLOCK(1 downto 0), + M_AXI_GP0_ARPROT(2 downto 0) => M_AXI_GP0_ARPROT(2 downto 0), + M_AXI_GP0_ARQOS(3 downto 0) => M_AXI_GP0_ARQOS(3 downto 0), + M_AXI_GP0_ARREADY => M_AXI_GP0_ARREADY, + M_AXI_GP0_ARSIZE(2 downto 0) => M_AXI_GP0_ARSIZE(2 downto 0), + M_AXI_GP0_ARVALID => M_AXI_GP0_ARVALID, + M_AXI_GP0_AWADDR(31 downto 0) => M_AXI_GP0_AWADDR(31 downto 0), + M_AXI_GP0_AWBURST(1 downto 0) => M_AXI_GP0_AWBURST(1 downto 0), + M_AXI_GP0_AWCACHE(3 downto 0) => M_AXI_GP0_AWCACHE(3 downto 0), + M_AXI_GP0_AWID(11 downto 0) => M_AXI_GP0_AWID(11 downto 0), + M_AXI_GP0_AWLEN(3 downto 0) => M_AXI_GP0_AWLEN(3 downto 0), + M_AXI_GP0_AWLOCK(1 downto 0) => M_AXI_GP0_AWLOCK(1 downto 0), + M_AXI_GP0_AWPROT(2 downto 0) => M_AXI_GP0_AWPROT(2 downto 0), + M_AXI_GP0_AWQOS(3 downto 0) => M_AXI_GP0_AWQOS(3 downto 0), + M_AXI_GP0_AWREADY => M_AXI_GP0_AWREADY, + M_AXI_GP0_AWSIZE(2 downto 0) => M_AXI_GP0_AWSIZE(2 downto 0), + M_AXI_GP0_AWVALID => M_AXI_GP0_AWVALID, + M_AXI_GP0_BID(11 downto 0) => M_AXI_GP0_BID(11 downto 0), + M_AXI_GP0_BREADY => M_AXI_GP0_BREADY, + M_AXI_GP0_BRESP(1 downto 0) => M_AXI_GP0_BRESP(1 downto 0), + M_AXI_GP0_BVALID => M_AXI_GP0_BVALID, + M_AXI_GP0_RDATA(31 downto 0) => M_AXI_GP0_RDATA(31 downto 0), + M_AXI_GP0_RID(11 downto 0) => M_AXI_GP0_RID(11 downto 0), + M_AXI_GP0_RLAST => M_AXI_GP0_RLAST, + M_AXI_GP0_RREADY => M_AXI_GP0_RREADY, + M_AXI_GP0_RRESP(1 downto 0) => M_AXI_GP0_RRESP(1 downto 0), + M_AXI_GP0_RVALID => M_AXI_GP0_RVALID, + M_AXI_GP0_WDATA(31 downto 0) => M_AXI_GP0_WDATA(31 downto 0), + M_AXI_GP0_WID(11 downto 0) => M_AXI_GP0_WID(11 downto 0), + M_AXI_GP0_WLAST => M_AXI_GP0_WLAST, + M_AXI_GP0_WREADY => M_AXI_GP0_WREADY, + M_AXI_GP0_WSTRB(3 downto 0) => M_AXI_GP0_WSTRB(3 downto 0), + M_AXI_GP0_WVALID => M_AXI_GP0_WVALID, + M_AXI_GP1_ACLK => '0', + M_AXI_GP1_ARADDR(31 downto 0) => NLW_inst_M_AXI_GP1_ARADDR_UNCONNECTED(31 downto 0), + M_AXI_GP1_ARBURST(1 downto 0) => NLW_inst_M_AXI_GP1_ARBURST_UNCONNECTED(1 downto 0), + M_AXI_GP1_ARCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_ARCACHE_UNCONNECTED(3 downto 0), + M_AXI_GP1_ARESETN => NLW_inst_M_AXI_GP1_ARESETN_UNCONNECTED, + M_AXI_GP1_ARID(11 downto 0) => NLW_inst_M_AXI_GP1_ARID_UNCONNECTED(11 downto 0), + M_AXI_GP1_ARLEN(3 downto 0) => NLW_inst_M_AXI_GP1_ARLEN_UNCONNECTED(3 downto 0), + M_AXI_GP1_ARLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_ARLOCK_UNCONNECTED(1 downto 0), + M_AXI_GP1_ARPROT(2 downto 0) => NLW_inst_M_AXI_GP1_ARPROT_UNCONNECTED(2 downto 0), + M_AXI_GP1_ARQOS(3 downto 0) => NLW_inst_M_AXI_GP1_ARQOS_UNCONNECTED(3 downto 0), + M_AXI_GP1_ARREADY => '0', + M_AXI_GP1_ARSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_ARSIZE_UNCONNECTED(2 downto 0), + M_AXI_GP1_ARVALID => NLW_inst_M_AXI_GP1_ARVALID_UNCONNECTED, + M_AXI_GP1_AWADDR(31 downto 0) => NLW_inst_M_AXI_GP1_AWADDR_UNCONNECTED(31 downto 0), + M_AXI_GP1_AWBURST(1 downto 0) => NLW_inst_M_AXI_GP1_AWBURST_UNCONNECTED(1 downto 0), + M_AXI_GP1_AWCACHE(3 downto 0) => NLW_inst_M_AXI_GP1_AWCACHE_UNCONNECTED(3 downto 0), + M_AXI_GP1_AWID(11 downto 0) => NLW_inst_M_AXI_GP1_AWID_UNCONNECTED(11 downto 0), + M_AXI_GP1_AWLEN(3 downto 0) => NLW_inst_M_AXI_GP1_AWLEN_UNCONNECTED(3 downto 0), + M_AXI_GP1_AWLOCK(1 downto 0) => NLW_inst_M_AXI_GP1_AWLOCK_UNCONNECTED(1 downto 0), + M_AXI_GP1_AWPROT(2 downto 0) => NLW_inst_M_AXI_GP1_AWPROT_UNCONNECTED(2 downto 0), + M_AXI_GP1_AWQOS(3 downto 0) => NLW_inst_M_AXI_GP1_AWQOS_UNCONNECTED(3 downto 0), + M_AXI_GP1_AWREADY => '0', + M_AXI_GP1_AWSIZE(2 downto 0) => NLW_inst_M_AXI_GP1_AWSIZE_UNCONNECTED(2 downto 0), + M_AXI_GP1_AWVALID => NLW_inst_M_AXI_GP1_AWVALID_UNCONNECTED, + M_AXI_GP1_BID(11 downto 0) => B"000000000000", + M_AXI_GP1_BREADY => NLW_inst_M_AXI_GP1_BREADY_UNCONNECTED, + M_AXI_GP1_BRESP(1 downto 0) => B"00", + M_AXI_GP1_BVALID => '0', + M_AXI_GP1_RDATA(31 downto 0) => B"00000000000000000000000000000000", + M_AXI_GP1_RID(11 downto 0) => B"000000000000", + M_AXI_GP1_RLAST => '0', + M_AXI_GP1_RREADY => NLW_inst_M_AXI_GP1_RREADY_UNCONNECTED, + M_AXI_GP1_RRESP(1 downto 0) => B"00", + M_AXI_GP1_RVALID => '0', + M_AXI_GP1_WDATA(31 downto 0) => NLW_inst_M_AXI_GP1_WDATA_UNCONNECTED(31 downto 0), + M_AXI_GP1_WID(11 downto 0) => NLW_inst_M_AXI_GP1_WID_UNCONNECTED(11 downto 0), + M_AXI_GP1_WLAST => NLW_inst_M_AXI_GP1_WLAST_UNCONNECTED, + M_AXI_GP1_WREADY => '0', + M_AXI_GP1_WSTRB(3 downto 0) => NLW_inst_M_AXI_GP1_WSTRB_UNCONNECTED(3 downto 0), + M_AXI_GP1_WVALID => NLW_inst_M_AXI_GP1_WVALID_UNCONNECTED, + PJTAG_TCK => '0', + PJTAG_TDI => '0', + PJTAG_TDO => NLW_inst_PJTAG_TDO_UNCONNECTED, + PJTAG_TMS => '0', + PS_CLK => PS_CLK, + PS_PORB => PS_PORB, + PS_SRSTB => PS_SRSTB, + SDIO0_BUSPOW => NLW_inst_SDIO0_BUSPOW_UNCONNECTED, + SDIO0_BUSVOLT(2 downto 0) => NLW_inst_SDIO0_BUSVOLT_UNCONNECTED(2 downto 0), + SDIO0_CDN => '0', + SDIO0_CLK => NLW_inst_SDIO0_CLK_UNCONNECTED, + SDIO0_CLK_FB => '0', + SDIO0_CMD_I => '0', + SDIO0_CMD_O => NLW_inst_SDIO0_CMD_O_UNCONNECTED, + SDIO0_CMD_T => NLW_inst_SDIO0_CMD_T_UNCONNECTED, + SDIO0_DATA_I(3 downto 0) => B"0000", + SDIO0_DATA_O(3 downto 0) => NLW_inst_SDIO0_DATA_O_UNCONNECTED(3 downto 0), + SDIO0_DATA_T(3 downto 0) => NLW_inst_SDIO0_DATA_T_UNCONNECTED(3 downto 0), + SDIO0_LED => NLW_inst_SDIO0_LED_UNCONNECTED, + SDIO0_WP => '0', + SDIO1_BUSPOW => NLW_inst_SDIO1_BUSPOW_UNCONNECTED, + SDIO1_BUSVOLT(2 downto 0) => NLW_inst_SDIO1_BUSVOLT_UNCONNECTED(2 downto 0), + SDIO1_CDN => '0', + SDIO1_CLK => NLW_inst_SDIO1_CLK_UNCONNECTED, + SDIO1_CLK_FB => '0', + SDIO1_CMD_I => '0', + SDIO1_CMD_O => NLW_inst_SDIO1_CMD_O_UNCONNECTED, + SDIO1_CMD_T => NLW_inst_SDIO1_CMD_T_UNCONNECTED, + SDIO1_DATA_I(3 downto 0) => B"0000", + SDIO1_DATA_O(3 downto 0) => NLW_inst_SDIO1_DATA_O_UNCONNECTED(3 downto 0), + SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0), + SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED, + SDIO1_WP => '0', + SPI0_MISO_I => '0', + SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED, + SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED, + SPI0_MOSI_I => '0', + SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED, + SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED, + SPI0_SCLK_I => '0', + SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED, + SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED, + SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED, + SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED, + SPI0_SS_I => '0', + SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED, + SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED, + SPI1_MISO_I => SPI1_MISO_I, + SPI1_MISO_O => SPI1_MISO_O, + SPI1_MISO_T => SPI1_MISO_T, + SPI1_MOSI_I => SPI1_MOSI_I, + SPI1_MOSI_O => SPI1_MOSI_O, + SPI1_MOSI_T => SPI1_MOSI_T, + SPI1_SCLK_I => SPI1_SCLK_I, + SPI1_SCLK_O => SPI1_SCLK_O, + SPI1_SCLK_T => SPI1_SCLK_T, + SPI1_SS1_O => SPI1_SS1_O, + SPI1_SS2_O => SPI1_SS2_O, + SPI1_SS_I => SPI1_SS_I, + SPI1_SS_O => SPI1_SS_O, + SPI1_SS_T => SPI1_SS_T, + SRAM_INTIN => '0', + S_AXI_ACP_ACLK => '0', + S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000", + S_AXI_ACP_ARBURST(1 downto 0) => B"00", + S_AXI_ACP_ARCACHE(3 downto 0) => B"0000", + S_AXI_ACP_ARESETN => NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED, + S_AXI_ACP_ARID(2 downto 0) => B"000", + S_AXI_ACP_ARLEN(3 downto 0) => B"0000", + S_AXI_ACP_ARLOCK(1 downto 0) => B"00", + S_AXI_ACP_ARPROT(2 downto 0) => B"000", + S_AXI_ACP_ARQOS(3 downto 0) => B"0000", + S_AXI_ACP_ARREADY => NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED, + S_AXI_ACP_ARSIZE(2 downto 0) => B"000", + S_AXI_ACP_ARUSER(4 downto 0) => B"00000", + S_AXI_ACP_ARVALID => '0', + S_AXI_ACP_AWADDR(31 downto 0) => B"00000000000000000000000000000000", + S_AXI_ACP_AWBURST(1 downto 0) => B"00", + S_AXI_ACP_AWCACHE(3 downto 0) => B"0000", + S_AXI_ACP_AWID(2 downto 0) => B"000", + S_AXI_ACP_AWLEN(3 downto 0) => B"0000", + S_AXI_ACP_AWLOCK(1 downto 0) => B"00", + S_AXI_ACP_AWPROT(2 downto 0) => B"000", + S_AXI_ACP_AWQOS(3 downto 0) => B"0000", + S_AXI_ACP_AWREADY => NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED, + S_AXI_ACP_AWSIZE(2 downto 0) => B"000", + S_AXI_ACP_AWUSER(4 downto 0) => B"00000", + S_AXI_ACP_AWVALID => '0', + S_AXI_ACP_BID(2 downto 0) => NLW_inst_S_AXI_ACP_BID_UNCONNECTED(2 downto 0), + S_AXI_ACP_BREADY => '0', + S_AXI_ACP_BRESP(1 downto 0) => NLW_inst_S_AXI_ACP_BRESP_UNCONNECTED(1 downto 0), + S_AXI_ACP_BVALID => NLW_inst_S_AXI_ACP_BVALID_UNCONNECTED, + S_AXI_ACP_RDATA(63 downto 0) => NLW_inst_S_AXI_ACP_RDATA_UNCONNECTED(63 downto 0), + S_AXI_ACP_RID(2 downto 0) => NLW_inst_S_AXI_ACP_RID_UNCONNECTED(2 downto 0), + S_AXI_ACP_RLAST => NLW_inst_S_AXI_ACP_RLAST_UNCONNECTED, + S_AXI_ACP_RREADY => '0', + S_AXI_ACP_RRESP(1 downto 0) => NLW_inst_S_AXI_ACP_RRESP_UNCONNECTED(1 downto 0), + S_AXI_ACP_RVALID => NLW_inst_S_AXI_ACP_RVALID_UNCONNECTED, + S_AXI_ACP_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + S_AXI_ACP_WID(2 downto 0) => B"000", + S_AXI_ACP_WLAST => '0', + S_AXI_ACP_WREADY => NLW_inst_S_AXI_ACP_WREADY_UNCONNECTED, + S_AXI_ACP_WSTRB(7 downto 0) => B"00000000", + S_AXI_ACP_WVALID => '0', + S_AXI_GP0_ACLK => '0', + S_AXI_GP0_ARADDR(31 downto 0) => B"00000000000000000000000000000000", + S_AXI_GP0_ARBURST(1 downto 0) => B"00", + S_AXI_GP0_ARCACHE(3 downto 0) => B"0000", + S_AXI_GP0_ARESETN => NLW_inst_S_AXI_GP0_ARESETN_UNCONNECTED, + S_AXI_GP0_ARID(5 downto 0) => B"000000", + S_AXI_GP0_ARLEN(3 downto 0) => B"0000", + S_AXI_GP0_ARLOCK(1 downto 0) => B"00", + S_AXI_GP0_ARPROT(2 downto 0) => B"000", + S_AXI_GP0_ARQOS(3 downto 0) => B"0000", + S_AXI_GP0_ARREADY => NLW_inst_S_AXI_GP0_ARREADY_UNCONNECTED, + S_AXI_GP0_ARSIZE(2 downto 0) => B"000", + S_AXI_GP0_ARVALID => '0', + S_AXI_GP0_AWADDR(31 downto 0) => B"00000000000000000000000000000000", + S_AXI_GP0_AWBURST(1 downto 0) => B"00", + S_AXI_GP0_AWCACHE(3 downto 0) => B"0000", + S_AXI_GP0_AWID(5 downto 0) => B"000000", + S_AXI_GP0_AWLEN(3 downto 0) => B"0000", + S_AXI_GP0_AWLOCK(1 downto 0) => B"00", + S_AXI_GP0_AWPROT(2 downto 0) => B"000", + S_AXI_GP0_AWQOS(3 downto 0) => B"0000", + S_AXI_GP0_AWREADY => NLW_inst_S_AXI_GP0_AWREADY_UNCONNECTED, + S_AXI_GP0_AWSIZE(2 downto 0) => B"000", + S_AXI_GP0_AWVALID => '0', + S_AXI_GP0_BID(5 downto 0) => NLW_inst_S_AXI_GP0_BID_UNCONNECTED(5 downto 0), + S_AXI_GP0_BREADY => '0', + S_AXI_GP0_BRESP(1 downto 0) => NLW_inst_S_AXI_GP0_BRESP_UNCONNECTED(1 downto 0), + S_AXI_GP0_BVALID => NLW_inst_S_AXI_GP0_BVALID_UNCONNECTED, + S_AXI_GP0_RDATA(31 downto 0) => NLW_inst_S_AXI_GP0_RDATA_UNCONNECTED(31 downto 0), + S_AXI_GP0_RID(5 downto 0) => NLW_inst_S_AXI_GP0_RID_UNCONNECTED(5 downto 0), + S_AXI_GP0_RLAST => NLW_inst_S_AXI_GP0_RLAST_UNCONNECTED, + S_AXI_GP0_RREADY => '0', + S_AXI_GP0_RRESP(1 downto 0) => NLW_inst_S_AXI_GP0_RRESP_UNCONNECTED(1 downto 0), + S_AXI_GP0_RVALID => NLW_inst_S_AXI_GP0_RVALID_UNCONNECTED, + S_AXI_GP0_WDATA(31 downto 0) => B"00000000000000000000000000000000", + S_AXI_GP0_WID(5 downto 0) => B"000000", + S_AXI_GP0_WLAST => '0', + S_AXI_GP0_WREADY => NLW_inst_S_AXI_GP0_WREADY_UNCONNECTED, + S_AXI_GP0_WSTRB(3 downto 0) => B"0000", + S_AXI_GP0_WVALID => '0', + S_AXI_GP1_ACLK => '0', + S_AXI_GP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000", + S_AXI_GP1_ARBURST(1 downto 0) => B"00", + S_AXI_GP1_ARCACHE(3 downto 0) => B"0000", + S_AXI_GP1_ARESETN => NLW_inst_S_AXI_GP1_ARESETN_UNCONNECTED, + S_AXI_GP1_ARID(5 downto 0) => B"000000", + S_AXI_GP1_ARLEN(3 downto 0) => B"0000", + S_AXI_GP1_ARLOCK(1 downto 0) => B"00", + S_AXI_GP1_ARPROT(2 downto 0) => B"000", + S_AXI_GP1_ARQOS(3 downto 0) => B"0000", + S_AXI_GP1_ARREADY => NLW_inst_S_AXI_GP1_ARREADY_UNCONNECTED, + S_AXI_GP1_ARSIZE(2 downto 0) => B"000", + S_AXI_GP1_ARVALID => '0', + S_AXI_GP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000", + S_AXI_GP1_AWBURST(1 downto 0) => B"00", + S_AXI_GP1_AWCACHE(3 downto 0) => B"0000", + S_AXI_GP1_AWID(5 downto 0) => B"000000", + S_AXI_GP1_AWLEN(3 downto 0) => B"0000", + S_AXI_GP1_AWLOCK(1 downto 0) => B"00", + S_AXI_GP1_AWPROT(2 downto 0) => B"000", + S_AXI_GP1_AWQOS(3 downto 0) => B"0000", + S_AXI_GP1_AWREADY => NLW_inst_S_AXI_GP1_AWREADY_UNCONNECTED, + S_AXI_GP1_AWSIZE(2 downto 0) => B"000", + S_AXI_GP1_AWVALID => '0', + S_AXI_GP1_BID(5 downto 0) => NLW_inst_S_AXI_GP1_BID_UNCONNECTED(5 downto 0), + S_AXI_GP1_BREADY => '0', + S_AXI_GP1_BRESP(1 downto 0) => NLW_inst_S_AXI_GP1_BRESP_UNCONNECTED(1 downto 0), + S_AXI_GP1_BVALID => NLW_inst_S_AXI_GP1_BVALID_UNCONNECTED, + S_AXI_GP1_RDATA(31 downto 0) => NLW_inst_S_AXI_GP1_RDATA_UNCONNECTED(31 downto 0), + S_AXI_GP1_RID(5 downto 0) => NLW_inst_S_AXI_GP1_RID_UNCONNECTED(5 downto 0), + S_AXI_GP1_RLAST => NLW_inst_S_AXI_GP1_RLAST_UNCONNECTED, + S_AXI_GP1_RREADY => '0', + S_AXI_GP1_RRESP(1 downto 0) => NLW_inst_S_AXI_GP1_RRESP_UNCONNECTED(1 downto 0), + S_AXI_GP1_RVALID => NLW_inst_S_AXI_GP1_RVALID_UNCONNECTED, + S_AXI_GP1_WDATA(31 downto 0) => B"00000000000000000000000000000000", + S_AXI_GP1_WID(5 downto 0) => B"000000", + S_AXI_GP1_WLAST => '0', + S_AXI_GP1_WREADY => NLW_inst_S_AXI_GP1_WREADY_UNCONNECTED, + S_AXI_GP1_WSTRB(3 downto 0) => B"0000", + S_AXI_GP1_WVALID => '0', + S_AXI_HP0_ACLK => S_AXI_HP0_ACLK, + S_AXI_HP0_ARADDR(31 downto 0) => S_AXI_HP0_ARADDR(31 downto 0), + S_AXI_HP0_ARBURST(1 downto 0) => S_AXI_HP0_ARBURST(1 downto 0), + S_AXI_HP0_ARCACHE(3 downto 0) => S_AXI_HP0_ARCACHE(3 downto 0), + S_AXI_HP0_ARESETN => NLW_inst_S_AXI_HP0_ARESETN_UNCONNECTED, + S_AXI_HP0_ARID(5 downto 0) => S_AXI_HP0_ARID(5 downto 0), + S_AXI_HP0_ARLEN(3 downto 0) => S_AXI_HP0_ARLEN(3 downto 0), + S_AXI_HP0_ARLOCK(1 downto 0) => S_AXI_HP0_ARLOCK(1 downto 0), + S_AXI_HP0_ARPROT(2 downto 0) => S_AXI_HP0_ARPROT(2 downto 0), + S_AXI_HP0_ARQOS(3 downto 0) => S_AXI_HP0_ARQOS(3 downto 0), + S_AXI_HP0_ARREADY => S_AXI_HP0_ARREADY, + S_AXI_HP0_ARSIZE(2 downto 0) => S_AXI_HP0_ARSIZE(2 downto 0), + S_AXI_HP0_ARVALID => S_AXI_HP0_ARVALID, + S_AXI_HP0_AWADDR(31 downto 0) => S_AXI_HP0_AWADDR(31 downto 0), + S_AXI_HP0_AWBURST(1 downto 0) => S_AXI_HP0_AWBURST(1 downto 0), + S_AXI_HP0_AWCACHE(3 downto 0) => S_AXI_HP0_AWCACHE(3 downto 0), + S_AXI_HP0_AWID(5 downto 0) => S_AXI_HP0_AWID(5 downto 0), + S_AXI_HP0_AWLEN(3 downto 0) => S_AXI_HP0_AWLEN(3 downto 0), + S_AXI_HP0_AWLOCK(1 downto 0) => S_AXI_HP0_AWLOCK(1 downto 0), + S_AXI_HP0_AWPROT(2 downto 0) => S_AXI_HP0_AWPROT(2 downto 0), + S_AXI_HP0_AWQOS(3 downto 0) => S_AXI_HP0_AWQOS(3 downto 0), + S_AXI_HP0_AWREADY => S_AXI_HP0_AWREADY, + S_AXI_HP0_AWSIZE(2 downto 0) => S_AXI_HP0_AWSIZE(2 downto 0), + S_AXI_HP0_AWVALID => S_AXI_HP0_AWVALID, + S_AXI_HP0_BID(5 downto 0) => S_AXI_HP0_BID(5 downto 0), + S_AXI_HP0_BREADY => S_AXI_HP0_BREADY, + S_AXI_HP0_BRESP(1 downto 0) => S_AXI_HP0_BRESP(1 downto 0), + S_AXI_HP0_BVALID => S_AXI_HP0_BVALID, + S_AXI_HP0_RACOUNT(2 downto 0) => S_AXI_HP0_RACOUNT(2 downto 0), + S_AXI_HP0_RCOUNT(7 downto 0) => S_AXI_HP0_RCOUNT(7 downto 0), + S_AXI_HP0_RDATA(63 downto 0) => S_AXI_HP0_RDATA(63 downto 0), + S_AXI_HP0_RDISSUECAP1_EN => S_AXI_HP0_RDISSUECAP1_EN, + S_AXI_HP0_RID(5 downto 0) => S_AXI_HP0_RID(5 downto 0), + S_AXI_HP0_RLAST => S_AXI_HP0_RLAST, + S_AXI_HP0_RREADY => S_AXI_HP0_RREADY, + S_AXI_HP0_RRESP(1 downto 0) => S_AXI_HP0_RRESP(1 downto 0), + S_AXI_HP0_RVALID => S_AXI_HP0_RVALID, + S_AXI_HP0_WACOUNT(5 downto 0) => S_AXI_HP0_WACOUNT(5 downto 0), + S_AXI_HP0_WCOUNT(7 downto 0) => S_AXI_HP0_WCOUNT(7 downto 0), + S_AXI_HP0_WDATA(63 downto 0) => S_AXI_HP0_WDATA(63 downto 0), + S_AXI_HP0_WID(5 downto 0) => S_AXI_HP0_WID(5 downto 0), + S_AXI_HP0_WLAST => S_AXI_HP0_WLAST, + S_AXI_HP0_WREADY => S_AXI_HP0_WREADY, + S_AXI_HP0_WRISSUECAP1_EN => S_AXI_HP0_WRISSUECAP1_EN, + S_AXI_HP0_WSTRB(7 downto 0) => S_AXI_HP0_WSTRB(7 downto 0), + S_AXI_HP0_WVALID => S_AXI_HP0_WVALID, + S_AXI_HP1_ACLK => '0', + S_AXI_HP1_ARADDR(31 downto 0) => B"00000000000000000000000000000000", + S_AXI_HP1_ARBURST(1 downto 0) => B"00", + S_AXI_HP1_ARCACHE(3 downto 0) => B"0000", + S_AXI_HP1_ARESETN => NLW_inst_S_AXI_HP1_ARESETN_UNCONNECTED, + S_AXI_HP1_ARID(5 downto 0) => B"000000", + S_AXI_HP1_ARLEN(3 downto 0) => B"0000", + S_AXI_HP1_ARLOCK(1 downto 0) => B"00", + S_AXI_HP1_ARPROT(2 downto 0) => B"000", + S_AXI_HP1_ARQOS(3 downto 0) => B"0000", + S_AXI_HP1_ARREADY => NLW_inst_S_AXI_HP1_ARREADY_UNCONNECTED, + S_AXI_HP1_ARSIZE(2 downto 0) => B"000", + S_AXI_HP1_ARVALID => '0', + S_AXI_HP1_AWADDR(31 downto 0) => B"00000000000000000000000000000000", + S_AXI_HP1_AWBURST(1 downto 0) => B"00", + S_AXI_HP1_AWCACHE(3 downto 0) => B"0000", + S_AXI_HP1_AWID(5 downto 0) => B"000000", + S_AXI_HP1_AWLEN(3 downto 0) => B"0000", + S_AXI_HP1_AWLOCK(1 downto 0) => B"00", + S_AXI_HP1_AWPROT(2 downto 0) => B"000", + S_AXI_HP1_AWQOS(3 downto 0) => B"0000", + S_AXI_HP1_AWREADY => NLW_inst_S_AXI_HP1_AWREADY_UNCONNECTED, + S_AXI_HP1_AWSIZE(2 downto 0) => B"000", + S_AXI_HP1_AWVALID => '0', + S_AXI_HP1_BID(5 downto 0) => NLW_inst_S_AXI_HP1_BID_UNCONNECTED(5 downto 0), + S_AXI_HP1_BREADY => '0', + S_AXI_HP1_BRESP(1 downto 0) => NLW_inst_S_AXI_HP1_BRESP_UNCONNECTED(1 downto 0), + S_AXI_HP1_BVALID => NLW_inst_S_AXI_HP1_BVALID_UNCONNECTED, + S_AXI_HP1_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP1_RACOUNT_UNCONNECTED(2 downto 0), + S_AXI_HP1_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_RCOUNT_UNCONNECTED(7 downto 0), + S_AXI_HP1_RDATA(63 downto 0) => NLW_inst_S_AXI_HP1_RDATA_UNCONNECTED(63 downto 0), + S_AXI_HP1_RDISSUECAP1_EN => '0', + S_AXI_HP1_RID(5 downto 0) => NLW_inst_S_AXI_HP1_RID_UNCONNECTED(5 downto 0), + S_AXI_HP1_RLAST => NLW_inst_S_AXI_HP1_RLAST_UNCONNECTED, + S_AXI_HP1_RREADY => '0', + S_AXI_HP1_RRESP(1 downto 0) => NLW_inst_S_AXI_HP1_RRESP_UNCONNECTED(1 downto 0), + S_AXI_HP1_RVALID => NLW_inst_S_AXI_HP1_RVALID_UNCONNECTED, + S_AXI_HP1_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP1_WACOUNT_UNCONNECTED(5 downto 0), + S_AXI_HP1_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP1_WCOUNT_UNCONNECTED(7 downto 0), + S_AXI_HP1_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + S_AXI_HP1_WID(5 downto 0) => B"000000", + S_AXI_HP1_WLAST => '0', + S_AXI_HP1_WREADY => NLW_inst_S_AXI_HP1_WREADY_UNCONNECTED, + S_AXI_HP1_WRISSUECAP1_EN => '0', + S_AXI_HP1_WSTRB(7 downto 0) => B"00000000", + S_AXI_HP1_WVALID => '0', + S_AXI_HP2_ACLK => '0', + S_AXI_HP2_ARADDR(31 downto 0) => B"00000000000000000000000000000000", + S_AXI_HP2_ARBURST(1 downto 0) => B"00", + S_AXI_HP2_ARCACHE(3 downto 0) => B"0000", + S_AXI_HP2_ARESETN => NLW_inst_S_AXI_HP2_ARESETN_UNCONNECTED, + S_AXI_HP2_ARID(5 downto 0) => B"000000", + S_AXI_HP2_ARLEN(3 downto 0) => B"0000", + S_AXI_HP2_ARLOCK(1 downto 0) => B"00", + S_AXI_HP2_ARPROT(2 downto 0) => B"000", + S_AXI_HP2_ARQOS(3 downto 0) => B"0000", + S_AXI_HP2_ARREADY => NLW_inst_S_AXI_HP2_ARREADY_UNCONNECTED, + S_AXI_HP2_ARSIZE(2 downto 0) => B"000", + S_AXI_HP2_ARVALID => '0', + S_AXI_HP2_AWADDR(31 downto 0) => B"00000000000000000000000000000000", + S_AXI_HP2_AWBURST(1 downto 0) => B"00", + S_AXI_HP2_AWCACHE(3 downto 0) => B"0000", + S_AXI_HP2_AWID(5 downto 0) => B"000000", + S_AXI_HP2_AWLEN(3 downto 0) => B"0000", + S_AXI_HP2_AWLOCK(1 downto 0) => B"00", + S_AXI_HP2_AWPROT(2 downto 0) => B"000", + S_AXI_HP2_AWQOS(3 downto 0) => B"0000", + S_AXI_HP2_AWREADY => NLW_inst_S_AXI_HP2_AWREADY_UNCONNECTED, + S_AXI_HP2_AWSIZE(2 downto 0) => B"000", + S_AXI_HP2_AWVALID => '0', + S_AXI_HP2_BID(5 downto 0) => NLW_inst_S_AXI_HP2_BID_UNCONNECTED(5 downto 0), + S_AXI_HP2_BREADY => '0', + S_AXI_HP2_BRESP(1 downto 0) => NLW_inst_S_AXI_HP2_BRESP_UNCONNECTED(1 downto 0), + S_AXI_HP2_BVALID => NLW_inst_S_AXI_HP2_BVALID_UNCONNECTED, + S_AXI_HP2_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP2_RACOUNT_UNCONNECTED(2 downto 0), + S_AXI_HP2_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_RCOUNT_UNCONNECTED(7 downto 0), + S_AXI_HP2_RDATA(63 downto 0) => NLW_inst_S_AXI_HP2_RDATA_UNCONNECTED(63 downto 0), + S_AXI_HP2_RDISSUECAP1_EN => '0', + S_AXI_HP2_RID(5 downto 0) => NLW_inst_S_AXI_HP2_RID_UNCONNECTED(5 downto 0), + S_AXI_HP2_RLAST => NLW_inst_S_AXI_HP2_RLAST_UNCONNECTED, + S_AXI_HP2_RREADY => '0', + S_AXI_HP2_RRESP(1 downto 0) => NLW_inst_S_AXI_HP2_RRESP_UNCONNECTED(1 downto 0), + S_AXI_HP2_RVALID => NLW_inst_S_AXI_HP2_RVALID_UNCONNECTED, + S_AXI_HP2_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP2_WACOUNT_UNCONNECTED(5 downto 0), + S_AXI_HP2_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP2_WCOUNT_UNCONNECTED(7 downto 0), + S_AXI_HP2_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + S_AXI_HP2_WID(5 downto 0) => B"000000", + S_AXI_HP2_WLAST => '0', + S_AXI_HP2_WREADY => NLW_inst_S_AXI_HP2_WREADY_UNCONNECTED, + S_AXI_HP2_WRISSUECAP1_EN => '0', + S_AXI_HP2_WSTRB(7 downto 0) => B"00000000", + S_AXI_HP2_WVALID => '0', + S_AXI_HP3_ACLK => '0', + S_AXI_HP3_ARADDR(31 downto 0) => B"00000000000000000000000000000000", + S_AXI_HP3_ARBURST(1 downto 0) => B"00", + S_AXI_HP3_ARCACHE(3 downto 0) => B"0000", + S_AXI_HP3_ARESETN => NLW_inst_S_AXI_HP3_ARESETN_UNCONNECTED, + S_AXI_HP3_ARID(5 downto 0) => B"000000", + S_AXI_HP3_ARLEN(3 downto 0) => B"0000", + S_AXI_HP3_ARLOCK(1 downto 0) => B"00", + S_AXI_HP3_ARPROT(2 downto 0) => B"000", + S_AXI_HP3_ARQOS(3 downto 0) => B"0000", + S_AXI_HP3_ARREADY => NLW_inst_S_AXI_HP3_ARREADY_UNCONNECTED, + S_AXI_HP3_ARSIZE(2 downto 0) => B"000", + S_AXI_HP3_ARVALID => '0', + S_AXI_HP3_AWADDR(31 downto 0) => B"00000000000000000000000000000000", + S_AXI_HP3_AWBURST(1 downto 0) => B"00", + S_AXI_HP3_AWCACHE(3 downto 0) => B"0000", + S_AXI_HP3_AWID(5 downto 0) => B"000000", + S_AXI_HP3_AWLEN(3 downto 0) => B"0000", + S_AXI_HP3_AWLOCK(1 downto 0) => B"00", + S_AXI_HP3_AWPROT(2 downto 0) => B"000", + S_AXI_HP3_AWQOS(3 downto 0) => B"0000", + S_AXI_HP3_AWREADY => NLW_inst_S_AXI_HP3_AWREADY_UNCONNECTED, + S_AXI_HP3_AWSIZE(2 downto 0) => B"000", + S_AXI_HP3_AWVALID => '0', + S_AXI_HP3_BID(5 downto 0) => NLW_inst_S_AXI_HP3_BID_UNCONNECTED(5 downto 0), + S_AXI_HP3_BREADY => '0', + S_AXI_HP3_BRESP(1 downto 0) => NLW_inst_S_AXI_HP3_BRESP_UNCONNECTED(1 downto 0), + S_AXI_HP3_BVALID => NLW_inst_S_AXI_HP3_BVALID_UNCONNECTED, + S_AXI_HP3_RACOUNT(2 downto 0) => NLW_inst_S_AXI_HP3_RACOUNT_UNCONNECTED(2 downto 0), + S_AXI_HP3_RCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_RCOUNT_UNCONNECTED(7 downto 0), + S_AXI_HP3_RDATA(63 downto 0) => NLW_inst_S_AXI_HP3_RDATA_UNCONNECTED(63 downto 0), + S_AXI_HP3_RDISSUECAP1_EN => '0', + S_AXI_HP3_RID(5 downto 0) => NLW_inst_S_AXI_HP3_RID_UNCONNECTED(5 downto 0), + S_AXI_HP3_RLAST => NLW_inst_S_AXI_HP3_RLAST_UNCONNECTED, + S_AXI_HP3_RREADY => '0', + S_AXI_HP3_RRESP(1 downto 0) => NLW_inst_S_AXI_HP3_RRESP_UNCONNECTED(1 downto 0), + S_AXI_HP3_RVALID => NLW_inst_S_AXI_HP3_RVALID_UNCONNECTED, + S_AXI_HP3_WACOUNT(5 downto 0) => NLW_inst_S_AXI_HP3_WACOUNT_UNCONNECTED(5 downto 0), + S_AXI_HP3_WCOUNT(7 downto 0) => NLW_inst_S_AXI_HP3_WCOUNT_UNCONNECTED(7 downto 0), + S_AXI_HP3_WDATA(63 downto 0) => B"0000000000000000000000000000000000000000000000000000000000000000", + S_AXI_HP3_WID(5 downto 0) => B"000000", + S_AXI_HP3_WLAST => '0', + S_AXI_HP3_WREADY => NLW_inst_S_AXI_HP3_WREADY_UNCONNECTED, + S_AXI_HP3_WRISSUECAP1_EN => '0', + S_AXI_HP3_WSTRB(7 downto 0) => B"00000000", + S_AXI_HP3_WVALID => '0', + TRACE_CLK => '0', + TRACE_CLK_OUT => NLW_inst_TRACE_CLK_OUT_UNCONNECTED, + TRACE_CTL => NLW_inst_TRACE_CTL_UNCONNECTED, + TRACE_DATA(1 downto 0) => NLW_inst_TRACE_DATA_UNCONNECTED(1 downto 0), + TTC0_CLK0_IN => '0', + TTC0_CLK1_IN => '0', + TTC0_CLK2_IN => '0', + TTC0_WAVE0_OUT => TTC0_WAVE0_OUT, + TTC0_WAVE1_OUT => TTC0_WAVE1_OUT, + TTC0_WAVE2_OUT => TTC0_WAVE2_OUT, + TTC1_CLK0_IN => '0', + TTC1_CLK1_IN => '0', + TTC1_CLK2_IN => '0', + TTC1_WAVE0_OUT => NLW_inst_TTC1_WAVE0_OUT_UNCONNECTED, + TTC1_WAVE1_OUT => NLW_inst_TTC1_WAVE1_OUT_UNCONNECTED, + TTC1_WAVE2_OUT => NLW_inst_TTC1_WAVE2_OUT_UNCONNECTED, + UART0_CTSN => '0', + UART0_DCDN => '0', + UART0_DSRN => '0', + UART0_DTRN => NLW_inst_UART0_DTRN_UNCONNECTED, + UART0_RIN => '0', + UART0_RTSN => NLW_inst_UART0_RTSN_UNCONNECTED, + UART0_RX => '1', + UART0_TX => NLW_inst_UART0_TX_UNCONNECTED, + UART1_CTSN => '0', + UART1_DCDN => '0', + UART1_DSRN => '0', + UART1_DTRN => NLW_inst_UART1_DTRN_UNCONNECTED, + UART1_RIN => '0', + UART1_RTSN => NLW_inst_UART1_RTSN_UNCONNECTED, + UART1_RX => '1', + UART1_TX => NLW_inst_UART1_TX_UNCONNECTED, + USB0_PORT_INDCTL(1 downto 0) => USB0_PORT_INDCTL(1 downto 0), + USB0_VBUS_PWRFAULT => USB0_VBUS_PWRFAULT, + USB0_VBUS_PWRSELECT => USB0_VBUS_PWRSELECT, + USB1_PORT_INDCTL(1 downto 0) => NLW_inst_USB1_PORT_INDCTL_UNCONNECTED(1 downto 0), + USB1_VBUS_PWRFAULT => '0', + USB1_VBUS_PWRSELECT => NLW_inst_USB1_VBUS_PWRSELECT_UNCONNECTED, + WDT_CLK_IN => '0', + WDT_RST_OUT => NLW_inst_WDT_RST_OUT_UNCONNECTED + ); +end STRUCTURE; diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/4c407e6cdd36e680/mz_petalinux_processing_system7_0_0_stub.v b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/4c407e6cdd36e680/mz_petalinux_processing_system7_0_0_stub.v new file mode 100755 index 0000000000000000000000000000000000000000..8d91a47029ff040a402656b474847bea212d0e88 --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/4c407e6cdd36e680/mz_petalinux_processing_system7_0_0_stub.v @@ -0,0 +1,177 @@ +// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 +// Date : Sun Oct 20 22:43:57 2019 +// Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mz_petalinux_processing_system7_0_0_stub.v +// Design : mz_petalinux_processing_system7_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z010clg400-1 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2017.4" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(I2C0_SDA_I, I2C0_SDA_O, I2C0_SDA_T, I2C0_SCL_I, + I2C0_SCL_O, I2C0_SCL_T, SPI1_SCLK_I, SPI1_SCLK_O, SPI1_SCLK_T, SPI1_MOSI_I, SPI1_MOSI_O, + SPI1_MOSI_T, SPI1_MISO_I, SPI1_MISO_O, SPI1_MISO_T, SPI1_SS_I, SPI1_SS_O, SPI1_SS1_O, + SPI1_SS2_O, SPI1_SS_T, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, USB0_PORT_INDCTL, + USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, + M_AXI_GP0_BREADY, M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, + M_AXI_GP0_AWID, M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, + M_AXI_GP0_AWBURST, M_AXI_GP0_AWLOCK, M_AXI_GP0_AWSIZE, M_AXI_GP0_ARPROT, + M_AXI_GP0_AWPROT, M_AXI_GP0_ARADDR, M_AXI_GP0_AWADDR, M_AXI_GP0_WDATA, M_AXI_GP0_ARCACHE, + M_AXI_GP0_ARLEN, M_AXI_GP0_ARQOS, M_AXI_GP0_AWCACHE, M_AXI_GP0_AWLEN, M_AXI_GP0_AWQOS, + M_AXI_GP0_WSTRB, M_AXI_GP0_ACLK, M_AXI_GP0_ARREADY, M_AXI_GP0_AWREADY, M_AXI_GP0_BVALID, + M_AXI_GP0_RLAST, M_AXI_GP0_RVALID, M_AXI_GP0_WREADY, M_AXI_GP0_BID, M_AXI_GP0_RID, + M_AXI_GP0_BRESP, M_AXI_GP0_RRESP, M_AXI_GP0_RDATA, S_AXI_HP0_ARREADY, S_AXI_HP0_AWREADY, + S_AXI_HP0_BVALID, S_AXI_HP0_RLAST, S_AXI_HP0_RVALID, S_AXI_HP0_WREADY, S_AXI_HP0_BRESP, + S_AXI_HP0_RRESP, S_AXI_HP0_BID, S_AXI_HP0_RID, S_AXI_HP0_RDATA, S_AXI_HP0_RCOUNT, + S_AXI_HP0_WCOUNT, S_AXI_HP0_RACOUNT, S_AXI_HP0_WACOUNT, S_AXI_HP0_ACLK, + S_AXI_HP0_ARVALID, S_AXI_HP0_AWVALID, S_AXI_HP0_BREADY, S_AXI_HP0_RDISSUECAP1_EN, + S_AXI_HP0_RREADY, S_AXI_HP0_WLAST, S_AXI_HP0_WRISSUECAP1_EN, S_AXI_HP0_WVALID, + S_AXI_HP0_ARBURST, S_AXI_HP0_ARLOCK, S_AXI_HP0_ARSIZE, S_AXI_HP0_AWBURST, + S_AXI_HP0_AWLOCK, S_AXI_HP0_AWSIZE, S_AXI_HP0_ARPROT, S_AXI_HP0_AWPROT, S_AXI_HP0_ARADDR, + S_AXI_HP0_AWADDR, S_AXI_HP0_ARCACHE, S_AXI_HP0_ARLEN, S_AXI_HP0_ARQOS, S_AXI_HP0_AWCACHE, + S_AXI_HP0_AWLEN, S_AXI_HP0_AWQOS, S_AXI_HP0_ARID, S_AXI_HP0_AWID, S_AXI_HP0_WID, + S_AXI_HP0_WDATA, S_AXI_HP0_WSTRB, IRQ_F2P, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, + DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, + DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB) +/* synthesis syn_black_box black_box_pad_pin="I2C0_SDA_I,I2C0_SDA_O,I2C0_SDA_T,I2C0_SCL_I,I2C0_SCL_O,I2C0_SCL_T,SPI1_SCLK_I,SPI1_SCLK_O,SPI1_SCLK_T,SPI1_MOSI_I,SPI1_MOSI_O,SPI1_MOSI_T,SPI1_MISO_I,SPI1_MISO_O,SPI1_MISO_T,SPI1_SS_I,SPI1_SS_O,SPI1_SS1_O,SPI1_SS2_O,SPI1_SS_T,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],S_AXI_HP0_ARREADY,S_AXI_HP0_AWREADY,S_AXI_HP0_BVALID,S_AXI_HP0_RLAST,S_AXI_HP0_RVALID,S_AXI_HP0_WREADY,S_AXI_HP0_BRESP[1:0],S_AXI_HP0_RRESP[1:0],S_AXI_HP0_BID[5:0],S_AXI_HP0_RID[5:0],S_AXI_HP0_RDATA[63:0],S_AXI_HP0_RCOUNT[7:0],S_AXI_HP0_WCOUNT[7:0],S_AXI_HP0_RACOUNT[2:0],S_AXI_HP0_WACOUNT[5:0],S_AXI_HP0_ACLK,S_AXI_HP0_ARVALID,S_AXI_HP0_AWVALID,S_AXI_HP0_BREADY,S_AXI_HP0_RDISSUECAP1_EN,S_AXI_HP0_RREADY,S_AXI_HP0_WLAST,S_AXI_HP0_WRISSUECAP1_EN,S_AXI_HP0_WVALID,S_AXI_HP0_ARBURST[1:0],S_AXI_HP0_ARLOCK[1:0],S_AXI_HP0_ARSIZE[2:0],S_AXI_HP0_AWBURST[1:0],S_AXI_HP0_AWLOCK[1:0],S_AXI_HP0_AWSIZE[2:0],S_AXI_HP0_ARPROT[2:0],S_AXI_HP0_AWPROT[2:0],S_AXI_HP0_ARADDR[31:0],S_AXI_HP0_AWADDR[31:0],S_AXI_HP0_ARCACHE[3:0],S_AXI_HP0_ARLEN[3:0],S_AXI_HP0_ARQOS[3:0],S_AXI_HP0_AWCACHE[3:0],S_AXI_HP0_AWLEN[3:0],S_AXI_HP0_AWQOS[3:0],S_AXI_HP0_ARID[5:0],S_AXI_HP0_AWID[5:0],S_AXI_HP0_WID[5:0],S_AXI_HP0_WDATA[63:0],S_AXI_HP0_WSTRB[7:0],IRQ_F2P[1:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */; + input I2C0_SDA_I; + output I2C0_SDA_O; + output I2C0_SDA_T; + input I2C0_SCL_I; + output I2C0_SCL_O; + output I2C0_SCL_T; + input SPI1_SCLK_I; + output SPI1_SCLK_O; + output SPI1_SCLK_T; + input SPI1_MOSI_I; + output SPI1_MOSI_O; + output SPI1_MOSI_T; + input SPI1_MISO_I; + output SPI1_MISO_O; + output SPI1_MISO_T; + input SPI1_SS_I; + output SPI1_SS_O; + output SPI1_SS1_O; + output SPI1_SS2_O; + output SPI1_SS_T; + output TTC0_WAVE0_OUT; + output TTC0_WAVE1_OUT; + output TTC0_WAVE2_OUT; + output [1:0]USB0_PORT_INDCTL; + output USB0_VBUS_PWRSELECT; + input USB0_VBUS_PWRFAULT; + output M_AXI_GP0_ARVALID; + output M_AXI_GP0_AWVALID; + output M_AXI_GP0_BREADY; + output M_AXI_GP0_RREADY; + output M_AXI_GP0_WLAST; + output M_AXI_GP0_WVALID; + output [11:0]M_AXI_GP0_ARID; + output [11:0]M_AXI_GP0_AWID; + output [11:0]M_AXI_GP0_WID; + output [1:0]M_AXI_GP0_ARBURST; + output [1:0]M_AXI_GP0_ARLOCK; + output [2:0]M_AXI_GP0_ARSIZE; + output [1:0]M_AXI_GP0_AWBURST; + output [1:0]M_AXI_GP0_AWLOCK; + output [2:0]M_AXI_GP0_AWSIZE; + output [2:0]M_AXI_GP0_ARPROT; + output [2:0]M_AXI_GP0_AWPROT; + output [31:0]M_AXI_GP0_ARADDR; + output [31:0]M_AXI_GP0_AWADDR; + output [31:0]M_AXI_GP0_WDATA; + output [3:0]M_AXI_GP0_ARCACHE; + output [3:0]M_AXI_GP0_ARLEN; + output [3:0]M_AXI_GP0_ARQOS; + output [3:0]M_AXI_GP0_AWCACHE; + output [3:0]M_AXI_GP0_AWLEN; + output [3:0]M_AXI_GP0_AWQOS; + output [3:0]M_AXI_GP0_WSTRB; + input M_AXI_GP0_ACLK; + input M_AXI_GP0_ARREADY; + input M_AXI_GP0_AWREADY; + input M_AXI_GP0_BVALID; + input M_AXI_GP0_RLAST; + input M_AXI_GP0_RVALID; + input M_AXI_GP0_WREADY; + input [11:0]M_AXI_GP0_BID; + input [11:0]M_AXI_GP0_RID; + input [1:0]M_AXI_GP0_BRESP; + input [1:0]M_AXI_GP0_RRESP; + input [31:0]M_AXI_GP0_RDATA; + output S_AXI_HP0_ARREADY; + output S_AXI_HP0_AWREADY; + output S_AXI_HP0_BVALID; + output S_AXI_HP0_RLAST; + output S_AXI_HP0_RVALID; + output S_AXI_HP0_WREADY; + output [1:0]S_AXI_HP0_BRESP; + output [1:0]S_AXI_HP0_RRESP; + output [5:0]S_AXI_HP0_BID; + output [5:0]S_AXI_HP0_RID; + output [63:0]S_AXI_HP0_RDATA; + output [7:0]S_AXI_HP0_RCOUNT; + output [7:0]S_AXI_HP0_WCOUNT; + output [2:0]S_AXI_HP0_RACOUNT; + output [5:0]S_AXI_HP0_WACOUNT; + input S_AXI_HP0_ACLK; + input S_AXI_HP0_ARVALID; + input S_AXI_HP0_AWVALID; + input S_AXI_HP0_BREADY; + input S_AXI_HP0_RDISSUECAP1_EN; + input S_AXI_HP0_RREADY; + input S_AXI_HP0_WLAST; + input S_AXI_HP0_WRISSUECAP1_EN; + input S_AXI_HP0_WVALID; + input [1:0]S_AXI_HP0_ARBURST; + input [1:0]S_AXI_HP0_ARLOCK; + input [2:0]S_AXI_HP0_ARSIZE; + input [1:0]S_AXI_HP0_AWBURST; + input [1:0]S_AXI_HP0_AWLOCK; + input [2:0]S_AXI_HP0_AWSIZE; + input [2:0]S_AXI_HP0_ARPROT; + input [2:0]S_AXI_HP0_AWPROT; + input [31:0]S_AXI_HP0_ARADDR; + input [31:0]S_AXI_HP0_AWADDR; + input [3:0]S_AXI_HP0_ARCACHE; + input [3:0]S_AXI_HP0_ARLEN; + input [3:0]S_AXI_HP0_ARQOS; + input [3:0]S_AXI_HP0_AWCACHE; + input [3:0]S_AXI_HP0_AWLEN; + input [3:0]S_AXI_HP0_AWQOS; + input [5:0]S_AXI_HP0_ARID; + input [5:0]S_AXI_HP0_AWID; + input [5:0]S_AXI_HP0_WID; + input [63:0]S_AXI_HP0_WDATA; + input [7:0]S_AXI_HP0_WSTRB; + input [1:0]IRQ_F2P; + output FCLK_CLK0; + output FCLK_RESET0_N; + inout [53:0]MIO; + inout DDR_CAS_n; + inout DDR_CKE; + inout DDR_Clk_n; + inout DDR_Clk; + inout DDR_CS_n; + inout DDR_DRSTB; + inout DDR_ODT; + inout DDR_RAS_n; + inout DDR_WEB; + inout [2:0]DDR_BankAddr; + inout [14:0]DDR_Addr; + inout DDR_VRN; + inout DDR_VRP; + inout [3:0]DDR_DM; + inout [31:0]DDR_DQ; + inout [3:0]DDR_DQS_n; + inout [3:0]DDR_DQS; + inout PS_SRSTB; + inout PS_CLK; + inout PS_PORB; +endmodule diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/4c407e6cdd36e680/mz_petalinux_processing_system7_0_0_stub.vhdl b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/4c407e6cdd36e680/mz_petalinux_processing_system7_0_0_stub.vhdl new file mode 100755 index 0000000000000000000000000000000000000000..1ad831f11c0e665c24e0947781bf56367bec8df0 --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/4c407e6cdd36e680/mz_petalinux_processing_system7_0_0_stub.vhdl @@ -0,0 +1,163 @@ +-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 +-- Date : Sun Oct 20 22:43:57 2019 +-- Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mz_petalinux_processing_system7_0_0_stub.vhdl +-- Design : mz_petalinux_processing_system7_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z010clg400-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + I2C0_SDA_I : in STD_LOGIC; + I2C0_SDA_O : out STD_LOGIC; + I2C0_SDA_T : out STD_LOGIC; + I2C0_SCL_I : in STD_LOGIC; + I2C0_SCL_O : out STD_LOGIC; + I2C0_SCL_T : out STD_LOGIC; + SPI1_SCLK_I : in STD_LOGIC; + SPI1_SCLK_O : out STD_LOGIC; + SPI1_SCLK_T : out STD_LOGIC; + SPI1_MOSI_I : in STD_LOGIC; + SPI1_MOSI_O : out STD_LOGIC; + SPI1_MOSI_T : out STD_LOGIC; + SPI1_MISO_I : in STD_LOGIC; + SPI1_MISO_O : out STD_LOGIC; + SPI1_MISO_T : out STD_LOGIC; + SPI1_SS_I : in STD_LOGIC; + SPI1_SS_O : out STD_LOGIC; + SPI1_SS1_O : out STD_LOGIC; + SPI1_SS2_O : out STD_LOGIC; + SPI1_SS_T : out STD_LOGIC; + TTC0_WAVE0_OUT : out STD_LOGIC; + TTC0_WAVE1_OUT : out STD_LOGIC; + TTC0_WAVE2_OUT : out STD_LOGIC; + USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 ); + USB0_VBUS_PWRSELECT : out STD_LOGIC; + USB0_VBUS_PWRFAULT : in STD_LOGIC; + M_AXI_GP0_ARVALID : out STD_LOGIC; + M_AXI_GP0_AWVALID : out STD_LOGIC; + M_AXI_GP0_BREADY : out STD_LOGIC; + M_AXI_GP0_RREADY : out STD_LOGIC; + M_AXI_GP0_WLAST : out STD_LOGIC; + M_AXI_GP0_WVALID : out STD_LOGIC; + M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 ); + M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 ); + M_AXI_GP0_ACLK : in STD_LOGIC; + M_AXI_GP0_ARREADY : in STD_LOGIC; + M_AXI_GP0_AWREADY : in STD_LOGIC; + M_AXI_GP0_BVALID : in STD_LOGIC; + M_AXI_GP0_RLAST : in STD_LOGIC; + M_AXI_GP0_RVALID : in STD_LOGIC; + M_AXI_GP0_WREADY : in STD_LOGIC; + M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 ); + M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 ); + M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_HP0_ARREADY : out STD_LOGIC; + S_AXI_HP0_AWREADY : out STD_LOGIC; + S_AXI_HP0_BVALID : out STD_LOGIC; + S_AXI_HP0_RLAST : out STD_LOGIC; + S_AXI_HP0_RVALID : out STD_LOGIC; + S_AXI_HP0_WREADY : out STD_LOGIC; + S_AXI_HP0_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_BID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_RID : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_RDATA : out STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_HP0_RCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP0_WCOUNT : out STD_LOGIC_VECTOR ( 7 downto 0 ); + S_AXI_HP0_RACOUNT : out STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_WACOUNT : out STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_ACLK : in STD_LOGIC; + S_AXI_HP0_ARVALID : in STD_LOGIC; + S_AXI_HP0_AWVALID : in STD_LOGIC; + S_AXI_HP0_BREADY : in STD_LOGIC; + S_AXI_HP0_RDISSUECAP1_EN : in STD_LOGIC; + S_AXI_HP0_RREADY : in STD_LOGIC; + S_AXI_HP0_WLAST : in STD_LOGIC; + S_AXI_HP0_WRISSUECAP1_EN : in STD_LOGIC; + S_AXI_HP0_WVALID : in STD_LOGIC; + S_AXI_HP0_ARBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_ARLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_ARSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_AWBURST : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_AWLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 ); + S_AXI_HP0_AWSIZE : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_ARPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_AWPROT : in STD_LOGIC_VECTOR ( 2 downto 0 ); + S_AXI_HP0_ARADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_HP0_AWADDR : in STD_LOGIC_VECTOR ( 31 downto 0 ); + S_AXI_HP0_ARCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_ARLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_ARQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_AWCACHE : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_AWLEN : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_AWQOS : in STD_LOGIC_VECTOR ( 3 downto 0 ); + S_AXI_HP0_ARID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_AWID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_WID : in STD_LOGIC_VECTOR ( 5 downto 0 ); + S_AXI_HP0_WDATA : in STD_LOGIC_VECTOR ( 63 downto 0 ); + S_AXI_HP0_WSTRB : in STD_LOGIC_VECTOR ( 7 downto 0 ); + IRQ_F2P : in STD_LOGIC_VECTOR ( 1 downto 0 ); + FCLK_CLK0 : out STD_LOGIC; + FCLK_RESET0_N : out STD_LOGIC; + MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 ); + DDR_CAS_n : inout STD_LOGIC; + DDR_CKE : inout STD_LOGIC; + DDR_Clk_n : inout STD_LOGIC; + DDR_Clk : inout STD_LOGIC; + DDR_CS_n : inout STD_LOGIC; + DDR_DRSTB : inout STD_LOGIC; + DDR_ODT : inout STD_LOGIC; + DDR_RAS_n : inout STD_LOGIC; + DDR_WEB : inout STD_LOGIC; + DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 ); + DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 ); + DDR_VRN : inout STD_LOGIC; + DDR_VRP : inout STD_LOGIC; + DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 ); + DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 ); + PS_SRSTB : inout STD_LOGIC; + PS_CLK : inout STD_LOGIC; + PS_PORB : inout STD_LOGIC + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "I2C0_SDA_I,I2C0_SDA_O,I2C0_SDA_T,I2C0_SCL_I,I2C0_SCL_O,I2C0_SCL_T,SPI1_SCLK_I,SPI1_SCLK_O,SPI1_SCLK_T,SPI1_MOSI_I,SPI1_MOSI_O,SPI1_MOSI_T,SPI1_MISO_I,SPI1_MISO_O,SPI1_MISO_T,SPI1_SS_I,SPI1_SS_O,SPI1_SS1_O,SPI1_SS2_O,SPI1_SS_T,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],S_AXI_HP0_ARREADY,S_AXI_HP0_AWREADY,S_AXI_HP0_BVALID,S_AXI_HP0_RLAST,S_AXI_HP0_RVALID,S_AXI_HP0_WREADY,S_AXI_HP0_BRESP[1:0],S_AXI_HP0_RRESP[1:0],S_AXI_HP0_BID[5:0],S_AXI_HP0_RID[5:0],S_AXI_HP0_RDATA[63:0],S_AXI_HP0_RCOUNT[7:0],S_AXI_HP0_WCOUNT[7:0],S_AXI_HP0_RACOUNT[2:0],S_AXI_HP0_WACOUNT[5:0],S_AXI_HP0_ACLK,S_AXI_HP0_ARVALID,S_AXI_HP0_AWVALID,S_AXI_HP0_BREADY,S_AXI_HP0_RDISSUECAP1_EN,S_AXI_HP0_RREADY,S_AXI_HP0_WLAST,S_AXI_HP0_WRISSUECAP1_EN,S_AXI_HP0_WVALID,S_AXI_HP0_ARBURST[1:0],S_AXI_HP0_ARLOCK[1:0],S_AXI_HP0_ARSIZE[2:0],S_AXI_HP0_AWBURST[1:0],S_AXI_HP0_AWLOCK[1:0],S_AXI_HP0_AWSIZE[2:0],S_AXI_HP0_ARPROT[2:0],S_AXI_HP0_AWPROT[2:0],S_AXI_HP0_ARADDR[31:0],S_AXI_HP0_AWADDR[31:0],S_AXI_HP0_ARCACHE[3:0],S_AXI_HP0_ARLEN[3:0],S_AXI_HP0_ARQOS[3:0],S_AXI_HP0_AWCACHE[3:0],S_AXI_HP0_AWLEN[3:0],S_AXI_HP0_AWQOS[3:0],S_AXI_HP0_ARID[5:0],S_AXI_HP0_AWID[5:0],S_AXI_HP0_WID[5:0],S_AXI_HP0_WDATA[63:0],S_AXI_HP0_WSTRB[7:0],IRQ_F2P[1:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2017.4"; +begin +end; diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/83ee55342075f3ed/stats.txt b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/83ee55342075f3ed/stats.txt index d17db17cbf79201bf7c9abe6293ae8f66eca9866..823cd4ab231572680edab64f514cc2604ceead3e 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/83ee55342075f3ed/stats.txt +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/83ee55342075f3ed/stats.txt @@ -1,2 +1,2 @@ -NumberHits:2 -Timestamp: Thu Oct 17 23:16:13 UTC 2019 +NumberHits:9 +Timestamp: Sun Oct 20 20:43:00 UTC 2019 diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/91bfb491f461c2e6/91bfb491f461c2e6.xci b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/91bfb491f461c2e6/91bfb491f461c2e6.xci new file mode 100644 index 0000000000000000000000000000000000000000..ef6855d6440905e11208e8cb4b9a117823958de5 --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/91bfb491f461c2e6/91bfb491f461c2e6.xci @@ -0,0 +1,39 @@ + + + xilinx.com + ipcache + 91bfb491f461c2e6 + 0 + + + mz_petalinux_xlconstant_0_0 + + + 1 + 1 + mz_petalinux_xlconstant_0_0 + zynq + em.avnet.com:microzed_7010:part0:1.1 + xc7z010 + clg400 + VERILOG + + MIXED + -1 + + TRUE + TRUE + 2ab741f6 + 91bfb491f461c2e6 + IP_Unknown + 3 + TRUE + . + + . + 2017.4 + GLOBAL + + + + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/91bfb491f461c2e6/mz_petalinux_xlconstant_0_0.dcp b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/91bfb491f461c2e6/mz_petalinux_xlconstant_0_0.dcp new file mode 100644 index 0000000000000000000000000000000000000000..70b97ab9df6746f94bb8f84370153a0a2a8f867a Binary files /dev/null and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/91bfb491f461c2e6/mz_petalinux_xlconstant_0_0.dcp differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/91bfb491f461c2e6/mz_petalinux_xlconstant_0_0_sim_netlist.v b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/91bfb491f461c2e6/mz_petalinux_xlconstant_0_0_sim_netlist.v new file mode 100755 index 0000000000000000000000000000000000000000..65cc3491fa7a703d3a6f44b9cf6b614f3a84f931 --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/91bfb491f461c2e6/mz_petalinux_xlconstant_0_0_sim_netlist.v @@ -0,0 +1,96 @@ +// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 +// Date : Sun Oct 20 15:59:59 2019 +// Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS +// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mz_petalinux_xlconstant_0_0_sim_netlist.v +// Design : mz_petalinux_xlconstant_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z010clg400-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "mz_petalinux_xlconstant_0_0,xlconstant_v1_1_3_xlconstant,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "xlconstant_v1_1_3_xlconstant,Vivado 2017.4" *) +(* NotValidForBitStream *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix + (dout); + output [0:0]dout; + + wire \ ; + + assign dout[0] = \ ; + VCC VCC + (.P(\ )); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/91bfb491f461c2e6/mz_petalinux_xlconstant_0_0_sim_netlist.vhdl b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/91bfb491f461c2e6/mz_petalinux_xlconstant_0_0_sim_netlist.vhdl new file mode 100755 index 0000000000000000000000000000000000000000..34eea8011a815e587b4023d654f77c3fce4bae98 --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/91bfb491f461c2e6/mz_petalinux_xlconstant_0_0_sim_netlist.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 +-- Date : Sun Oct 20 15:59:59 2019 +-- Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS +-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mz_petalinux_xlconstant_0_0_sim_netlist.vhdl +-- Design : mz_petalinux_xlconstant_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z010clg400-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + port ( + dout : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "mz_petalinux_xlconstant_0_0,xlconstant_v1_1_3_xlconstant,{}"; + attribute DowngradeIPIdentifiedWarnings : string; + attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; + attribute X_CORE_INFO : string; + attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "xlconstant_v1_1_3_xlconstant,Vivado 2017.4"; +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + signal \\ : STD_LOGIC; +begin + dout(0) <= \\; +VCC: unisim.vcomponents.VCC + port map ( + P => \\ + ); +end STRUCTURE; diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/91bfb491f461c2e6/mz_petalinux_xlconstant_0_0_stub.v b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/91bfb491f461c2e6/mz_petalinux_xlconstant_0_0_stub.v new file mode 100755 index 0000000000000000000000000000000000000000..c66cbb81fb7d88068e87f5651dcd27ff8203e630 --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/91bfb491f461c2e6/mz_petalinux_xlconstant_0_0_stub.v @@ -0,0 +1,20 @@ +// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 +// Date : Sun Oct 20 15:59:59 2019 +// Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mz_petalinux_xlconstant_0_0_stub.v +// Design : mz_petalinux_xlconstant_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z010clg400-1 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "xlconstant_v1_1_3_xlconstant,Vivado 2017.4" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(dout) +/* synthesis syn_black_box black_box_pad_pin="dout[0:0]" */; + output [0:0]dout; +endmodule diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/91bfb491f461c2e6/mz_petalinux_xlconstant_0_0_stub.vhdl b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/91bfb491f461c2e6/mz_petalinux_xlconstant_0_0_stub.vhdl new file mode 100755 index 0000000000000000000000000000000000000000..97619d35a1bf9bc1b1df1310655db5737d0a154e --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/91bfb491f461c2e6/mz_petalinux_xlconstant_0_0_stub.vhdl @@ -0,0 +1,30 @@ +-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 +-- Date : Sun Oct 20 15:59:59 2019 +-- Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mz_petalinux_xlconstant_0_0_stub.vhdl +-- Design : mz_petalinux_xlconstant_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z010clg400-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + dout : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "dout[0:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "xlconstant_v1_1_3_xlconstant,Vivado 2017.4"; +begin +end; diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/ceb18d6554abefb1/ceb18d6554abefb1.xci b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/ceb18d6554abefb1/ceb18d6554abefb1.xci new file mode 100644 index 0000000000000000000000000000000000000000..57f3216925aa55e22343b1421e8ac5830c787b4c --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/ceb18d6554abefb1/ceb18d6554abefb1.xci @@ -0,0 +1,39 @@ + + + xilinx.com + ipcache + ceb18d6554abefb1 + 0 + + + mz_petalinux_xlconstant_0_0 + + + 0 + 1 + mz_petalinux_xlconstant_0_0 + zynq + em.avnet.com:microzed_7010:part0:1.1 + xc7z010 + clg400 + VERILOG + + MIXED + -1 + + TRUE + TRUE + 2ab741f6 + ceb18d6554abefb1 + IP_Unknown + 3 + TRUE + . + + . + 2017.4 + GLOBAL + + + + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/ceb18d6554abefb1/mz_petalinux_xlconstant_0_0.dcp b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/ceb18d6554abefb1/mz_petalinux_xlconstant_0_0.dcp new file mode 100644 index 0000000000000000000000000000000000000000..4becc99523d779a7b977abc27f71fbc6cf51dac5 Binary files /dev/null and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/ceb18d6554abefb1/mz_petalinux_xlconstant_0_0.dcp differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/ceb18d6554abefb1/mz_petalinux_xlconstant_0_0_sim_netlist.v b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/ceb18d6554abefb1/mz_petalinux_xlconstant_0_0_sim_netlist.v new file mode 100755 index 0000000000000000000000000000000000000000..b0fb262a1ae5446f8a6562a0092ac1cb39e88bbd --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/ceb18d6554abefb1/mz_petalinux_xlconstant_0_0_sim_netlist.v @@ -0,0 +1,96 @@ +// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 +// Date : Sun Oct 20 15:52:45 2019 +// Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS +// Command : write_verilog -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mz_petalinux_xlconstant_0_0_sim_netlist.v +// Design : mz_petalinux_xlconstant_0_0 +// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified +// or synthesized. This netlist cannot be used for SDF annotated simulation. +// Device : xc7z010clg400-1 +// -------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CHECK_LICENSE_TYPE = "mz_petalinux_xlconstant_0_0,xlconstant_v1_1_3_xlconstant,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "xlconstant_v1_1_3_xlconstant,Vivado 2017.4" *) +(* NotValidForBitStream *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix + (dout); + output [0:0]dout; + + wire \ ; + + assign dout[0] = \ ; + GND GND + (.G(\ )); +endmodule +`ifndef GLBL +`define GLBL +`timescale 1 ps / 1 ps + +module glbl (); + + parameter ROC_WIDTH = 100000; + parameter TOC_WIDTH = 0; + +//-------- STARTUP Globals -------------- + wire GSR; + wire GTS; + wire GWE; + wire PRLD; + tri1 p_up_tmp; + tri (weak1, strong0) PLL_LOCKG = p_up_tmp; + + wire PROGB_GLBL; + wire CCLKO_GLBL; + wire FCSBO_GLBL; + wire [3:0] DO_GLBL; + wire [3:0] DI_GLBL; + + reg GSR_int; + reg GTS_int; + reg PRLD_int; + +//-------- JTAG Globals -------------- + wire JTAG_TDO_GLBL; + wire JTAG_TCK_GLBL; + wire JTAG_TDI_GLBL; + wire JTAG_TMS_GLBL; + wire JTAG_TRST_GLBL; + + reg JTAG_CAPTURE_GLBL; + reg JTAG_RESET_GLBL; + reg JTAG_SHIFT_GLBL; + reg JTAG_UPDATE_GLBL; + reg JTAG_RUNTEST_GLBL; + + reg JTAG_SEL1_GLBL = 0; + reg JTAG_SEL2_GLBL = 0 ; + reg JTAG_SEL3_GLBL = 0; + reg JTAG_SEL4_GLBL = 0; + + reg JTAG_USER_TDO1_GLBL = 1'bz; + reg JTAG_USER_TDO2_GLBL = 1'bz; + reg JTAG_USER_TDO3_GLBL = 1'bz; + reg JTAG_USER_TDO4_GLBL = 1'bz; + + assign (strong1, weak0) GSR = GSR_int; + assign (strong1, weak0) GTS = GTS_int; + assign (weak1, weak0) PRLD = PRLD_int; + + initial begin + GSR_int = 1'b1; + PRLD_int = 1'b1; + #(ROC_WIDTH) + GSR_int = 1'b0; + PRLD_int = 1'b0; + end + + initial begin + GTS_int = 1'b1; + #(TOC_WIDTH) + GTS_int = 1'b0; + end + +endmodule +`endif diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/ceb18d6554abefb1/mz_petalinux_xlconstant_0_0_sim_netlist.vhdl b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/ceb18d6554abefb1/mz_petalinux_xlconstant_0_0_sim_netlist.vhdl new file mode 100755 index 0000000000000000000000000000000000000000..c98b4b4602d5e723a0b946c85062b596966af7b8 --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/ceb18d6554abefb1/mz_petalinux_xlconstant_0_0_sim_netlist.vhdl @@ -0,0 +1,39 @@ +-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 +-- Date : Sun Oct 20 15:52:45 2019 +-- Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS +-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mz_petalinux_xlconstant_0_0_sim_netlist.vhdl +-- Design : mz_petalinux_xlconstant_0_0 +-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or +-- synthesized. This netlist cannot be used for SDF annotated simulation. +-- Device : xc7z010clg400-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + port ( + dout : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + attribute NotValidForBitStream : boolean; + attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true; + attribute CHECK_LICENSE_TYPE : string; + attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "mz_petalinux_xlconstant_0_0,xlconstant_v1_1_3_xlconstant,{}"; + attribute DowngradeIPIdentifiedWarnings : string; + attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes"; + attribute X_CORE_INFO : string; + attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "xlconstant_v1_1_3_xlconstant,Vivado 2017.4"; +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + signal \\ : STD_LOGIC; +begin + dout(0) <= \\; +GND: unisim.vcomponents.GND + port map ( + G => \\ + ); +end STRUCTURE; diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/ceb18d6554abefb1/mz_petalinux_xlconstant_0_0_stub.v b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/ceb18d6554abefb1/mz_petalinux_xlconstant_0_0_stub.v new file mode 100755 index 0000000000000000000000000000000000000000..fc3881eb62079626e81905b58e1c332bd3e65dfd --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/ceb18d6554abefb1/mz_petalinux_xlconstant_0_0_stub.v @@ -0,0 +1,20 @@ +// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +// -------------------------------------------------------------------------------- +// Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 +// Date : Sun Oct 20 15:52:45 2019 +// Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS +// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mz_petalinux_xlconstant_0_0_stub.v +// Design : mz_petalinux_xlconstant_0_0 +// Purpose : Stub declaration of top-level module interface +// Device : xc7z010clg400-1 +// -------------------------------------------------------------------------------- + +// This empty module with port declaration file causes synthesis tools to infer a black box for IP. +// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion. +// Please paste the declaration into a Verilog source file or add the file as an additional source. +(* X_CORE_INFO = "xlconstant_v1_1_3_xlconstant,Vivado 2017.4" *) +module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(dout) +/* synthesis syn_black_box black_box_pad_pin="dout[0:0]" */; + output [0:0]dout; +endmodule diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/ceb18d6554abefb1/mz_petalinux_xlconstant_0_0_stub.vhdl b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/ceb18d6554abefb1/mz_petalinux_xlconstant_0_0_stub.vhdl new file mode 100755 index 0000000000000000000000000000000000000000..2b4113e49e6401cb41e1cc6dabe6ac05b411b585 --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip/2017.4/ceb18d6554abefb1/mz_petalinux_xlconstant_0_0_stub.vhdl @@ -0,0 +1,30 @@ +-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. +-- -------------------------------------------------------------------------------- +-- Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 +-- Date : Sun Oct 20 15:52:45 2019 +-- Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS +-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix +-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ mz_petalinux_xlconstant_0_0_stub.vhdl +-- Design : mz_petalinux_xlconstant_0_0 +-- Purpose : Stub declaration of top-level module interface +-- Device : xc7z010clg400-1 +-- -------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is + Port ( + dout : out STD_LOGIC_VECTOR ( 0 to 0 ) + ); + +end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix; + +architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is +attribute syn_black_box : boolean; +attribute black_box_pad_pin : string; +attribute syn_black_box of stub : architecture is true; +attribute black_box_pad_pin of stub : architecture is "dout[0:0]"; +attribute X_CORE_INFO : string; +attribute X_CORE_INFO of stub : architecture is "xlconstant_v1_1_3_xlconstant,Vivado 2017.4"; +begin +end; diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/wt/gui_handlers.wdf b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/wt/gui_handlers.wdf index 92b63a3955d7d9b0b7a97e294fe0617042244a5a..9740b8f55b2f3afd32421c506266b28894744ada 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/wt/gui_handlers.wdf +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/wt/gui_handlers.wdf @@ -3,15 +3,15 @@ version:1 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:616273747261637473656172636861626c6570616e656c5f73686f775f736561726368:31:00:00 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6d6f64655f636f756e7465727c42617463684d6f6465:2 -6d6f64655f636f756e7465727c4755494d6f6465:587 +6d6f64655f636f756e7465727c4755494d6f6465:589 eof: diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/wt/synthesis.wdf b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/wt/synthesis.wdf index 0b972ad54ca1c8ab8e29c435a1dc4b704022ae61..48a03a361d176b8dbd36f65f006481dfd409dd84 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/wt/synthesis.wdf +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/wt/synthesis.wdf @@ -33,7 +33,7 @@ version:1 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 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065544ac9abb5b92ee57d44bb6d86c81653f2de5..7cf74be347be5553ad213f39fadeb906d82f5f01 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/wt/webtalk_pa.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/wt/webtalk_pa.xml @@ -3,10 +3,10 @@ - +
- +
@@ -24,15 +24,17 @@ This means code written to parse this file will need to be revisited each subseq - - + + + + - + - + @@ -40,43 +42,44 @@ This means code written to parse this file will need to be revisited each subseq - + - - + + - + - + - + - + - - + + + - + - + - - + + - - + + @@ -90,12 +93,13 @@ This means code written to parse this file will need to be revisited each subseq - - + + - + + @@ -103,27 +107,27 @@ This means code written to parse this file will need to be revisited each subseq - - + + - - + + - - + + - + - + @@ -133,29 +137,30 @@ This means code written to parse this file will need to be revisited each subseq - + - + - + - - + + - + - + - - + + + - + @@ -168,7 +173,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -183,38 +188,39 @@ This means code written to parse this file will need to be revisited each subseq - + - + + - - - - + + + + - + - - - + + + - + - +
diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_64.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_64.xml new file mode 100644 index 0000000000000000000000000000000000000000..b0229b13db2b3eaa944c21ce4d356f905123b2ff --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_64.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_65.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_65.xml new file mode 100644 index 0000000000000000000000000000000000000000..f1c2b0ab4e5a1bb08cf495809611a61f60115c6e --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_65.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_66.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_66.xml new file mode 100644 index 0000000000000000000000000000000000000000..3ad209782c9758c3940b798b00925c0359d3b3a9 --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_66.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_67.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_67.xml new file mode 100644 index 0000000000000000000000000000000000000000..ce318f76d0e1536359a4d0ad4c83c38aea744f21 --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_67.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_68.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_68.xml new file mode 100644 index 0000000000000000000000000000000000000000..ce318f76d0e1536359a4d0ad4c83c38aea744f21 --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_68.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_69.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_69.xml new file mode 100644 index 0000000000000000000000000000000000000000..3ad209782c9758c3940b798b00925c0359d3b3a9 --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_69.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_70.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_70.xml new file mode 100644 index 0000000000000000000000000000000000000000..f1c2b0ab4e5a1bb08cf495809611a61f60115c6e --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_70.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_71.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_71.xml new file mode 100644 index 0000000000000000000000000000000000000000..3ad209782c9758c3940b798b00925c0359d3b3a9 --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_71.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_72.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_72.xml new file mode 100644 index 0000000000000000000000000000000000000000..f1c2b0ab4e5a1bb08cf495809611a61f60115c6e --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_72.xml @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_73.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_73.xml new file mode 100644 index 0000000000000000000000000000000000000000..3ad209782c9758c3940b798b00925c0359d3b3a9 --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_73.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_74.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_74.xml new file mode 100644 index 0000000000000000000000000000000000000000..de41b509a985ade06aaf7b8c02cec8214c80c414 --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_74.xml @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_75.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_75.xml new file mode 100644 index 0000000000000000000000000000000000000000..3ad209782c9758c3940b798b00925c0359d3b3a9 --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/.jobs/vrs_config_75.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.init_design.begin.rst b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.init_design.begin.rst index fdabe298aa3bac26ef3c603ed05f3a8e0c2f4108..3391d15c5924e4253218d126c3590a051265ba84 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.init_design.begin.rst +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.init_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.opt_design.begin.rst b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.opt_design.begin.rst index fdabe298aa3bac26ef3c603ed05f3a8e0c2f4108..3391d15c5924e4253218d126c3590a051265ba84 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.opt_design.begin.rst +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.opt_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.place_design.begin.rst b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.place_design.begin.rst index fdabe298aa3bac26ef3c603ed05f3a8e0c2f4108..3391d15c5924e4253218d126c3590a051265ba84 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.place_design.begin.rst +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.place_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.route_design.begin.rst b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.route_design.begin.rst index fdabe298aa3bac26ef3c603ed05f3a8e0c2f4108..3391d15c5924e4253218d126c3590a051265ba84 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.route_design.begin.rst +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.route_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.vivado.begin.rst b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.vivado.begin.rst index 64db8c8c1855e7dabd4bb3e24d17546be898d850..a468457b27906ca8d34c381d73baba96c2698cb1 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.vivado.begin.rst +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.vivado.begin.rst @@ -1,10 +1,10 @@ - + - + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.write_bitstream.begin.rst b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.write_bitstream.begin.rst index 0f1f8e8f6f4100d6d00f96ea857baa5f090d912d..2cecd9ad34b57ea04a75349858896d61a4cde14f 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.write_bitstream.begin.rst +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.write_bitstream.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/gen_run.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/gen_run.xml index 75ae8ea937862517fc031deffd1bfdae7b009749..fdcef916db24ed7372a3901d8652af97c62ed21f 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/gen_run.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/gen_run.xml @@ -1,5 +1,5 @@ - + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/init_design.pb b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/init_design.pb index 43bb32e11a4fca791640cd2add237a818d668eae..d9cd54adee0b72433e1864fc2e36eb3d7ebf32b1 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/init_design.pb and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/init_design.pb differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper.bin b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper.bin index 30fe4668091b38c27037b4ce6676304910b520cc..f229afe3eecce679d91dc839337dc01e890169d3 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper.bin and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper.bin differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper.bit b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper.bit index f3d5cd03d6129b92e0b51c92d3080bfe38461117..8a6368109972fbb675217c961969f94651507509 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper.bit and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper.bit differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper.hwdef b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper.hwdef index a790e22ce148f90c180353f1a565dedc4d93e8d0..8b5feb24478c04001377711335ac7ec90e2ce4f2 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper.hwdef and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper.hwdef differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper.sysdef b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper.sysdef index 0f684eac521969b0bec5301cf8190cff95866d02..d1f3f9ba14a675ec24b102894abe8dff3cc74a90 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper.sysdef and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper.sysdef differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper.vdi b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper.vdi index 708774d1b63ca55c052d661531b073f3b633f34e..f3674a7559a723f4f257fb0c586db40219bc57d4 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper.vdi +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper.vdi @@ -2,8 +2,8 @@ # Vivado v2017.4 (64-bit) # SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017 # IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 -# Start of session at: Sat Oct 19 01:12:45 2019 -# Process ID: 11113 +# Start of session at: Sun Oct 20 22:44:52 2019 +# Process ID: 6337 # Current directory: /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1 # Command line: vivado -log mz_petalinux_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source mz_petalinux_wrapper.tcl -notrace # Log file: /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper.vdi @@ -140,7 +140,7 @@ INFO: [Project 1-111] Unisim Transformation Summary: 23 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully -link_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:39 . Memory (MB): peak = 2119.613 ; gain = 878.508 ; free physical = 220 ; free virtual = 10178 +link_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:40 . Memory (MB): peak = 2121.133 ; gain = 877.500 ; free physical = 2986 ; free virtual = 9841 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' @@ -151,7 +151,7 @@ INFO: [DRC 23-27] Running DRC with 4 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.94 . Memory (MB): peak = 2151.621 ; gain = 32.008 ; free physical = 203 ; free virtual = 10164 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.78 . Memory (MB): peak = 2153.141 ; gain = 32.008 ; free physical = 2974 ; free virtual = 9831 INFO: [Timing 38-35] Done setting XDC timing constraints. Starting Logic Optimization Task @@ -159,42 +159,42 @@ Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 21 inverter(s) to 94 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: 1e945c820 +Phase 1 Retarget | Checksum: 27c7187ff -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.81 . Memory (MB): peak = 2151.621 ; gain = 0.000 ; free physical = 198 ; free virtual = 10159 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.84 . Memory (MB): peak = 2153.141 ; gain = 0.000 ; free physical = 2976 ; free virtual = 9833 INFO: [Opt 31-389] Phase Retarget created 177 cells and removed 326 cells Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 2 inverter(s) to 10 load pin(s). -Phase 2 Constant propagation | Checksum: 23c38d198 +Phase 2 Constant propagation | Checksum: 27c5940a0 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2151.621 ; gain = 0.000 ; free physical = 198 ; free virtual = 10159 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2153.141 ; gain = 0.000 ; free physical = 2975 ; free virtual = 9832 INFO: [Opt 31-389] Phase Constant propagation created 414 cells and removed 1375 cells Phase 3 Sweep -Phase 3 Sweep | Checksum: 228e8aad1 +Phase 3 Sweep | Checksum: 1b70185b9 -Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2151.621 ; gain = 0.000 ; free physical = 197 ; free virtual = 10158 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2153.141 ; gain = 0.000 ; free physical = 2966 ; free virtual = 9824 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1386 cells Phase 4 BUFG optimization -Phase 4 BUFG optimization | Checksum: 228e8aad1 +Phase 4 BUFG optimization | Checksum: 1b70185b9 -Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2151.621 ; gain = 0.000 ; free physical = 197 ; free virtual = 10158 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2153.141 ; gain = 0.000 ; free physical = 2967 ; free virtual = 9825 INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells Phase 5 Shift Register Optimization -Phase 5 Shift Register Optimization | Checksum: 228e8aad1 +Phase 5 Shift Register Optimization | Checksum: 1b70185b9 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 2151.621 ; gain = 0.000 ; free physical = 194 ; free virtual = 10155 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 2153.141 ; gain = 0.000 ; free physical = 2968 ; free virtual = 9826 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Starting Connectivity Check Task -Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2151.621 ; gain = 0.000 ; free physical = 187 ; free virtual = 10148 -Ending Logic Optimization Task | Checksum: 1bccbb098 +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2153.141 ; gain = 0.000 ; free physical = 2967 ; free virtual = 9826 +Ending Logic Optimization Task | Checksum: 1c2580116 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2151.621 ; gain = 0.000 ; free physical = 187 ; free virtual = 10148 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2153.141 ; gain = 0.000 ; free physical = 2967 ; free virtual = 9826 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. @@ -211,21 +211,21 @@ Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 2 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports Number of BRAM Ports augmented: 2 newly gated: 0 Total Ports: 4 -Ending PowerOpt Patch Enables Task | Checksum: 1e185de09 +Ending PowerOpt Patch Enables Task | Checksum: 2117c7f30 -Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 333 ; free virtual = 10127 -Ending Power Optimization Task | Checksum: 1e185de09 +Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2937 ; free virtual = 9800 +Ending Power Optimization Task | Checksum: 2117c7f30 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2437.027 ; gain = 285.406 ; free physical = 345 ; free virtual = 10139 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2437.586 ; gain = 284.445 ; free physical = 2949 ; free virtual = 9812 INFO: [Common 17-83] Releasing license: Implementation 44 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully -opt_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 2437.027 ; gain = 317.414 ; free physical = 345 ; free virtual = 10139 +opt_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 2437.586 ; gain = 316.453 ; free physical = 2949 ; free virtual = 9812 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 342 ; free virtual = 10139 +Write XDEF Complete: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2945 ; free virtual = 9811 INFO: [Common 17-1381] The checkpoint '/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_opt.dcp' has been generated. INFO: [runtcl-4] Executing : report_drc -file mz_petalinux_wrapper_drc_opted.rpt -pb mz_petalinux_wrapper_drc_opted.pb -rpx mz_petalinux_wrapper_drc_opted.rpx Command: report_drc -file mz_petalinux_wrapper_drc_opted.rpt -pb mz_petalinux_wrapper_drc_opted.pb -rpx mz_petalinux_wrapper_drc_opted.rpx @@ -253,77 +253,77 @@ INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 326 ; free virtual = 10126 +Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2916 ; free virtual = 9786 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 16d2ffea9 -Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 325 ; free virtual = 10125 +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2916 ; free virtual = 9786 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 328 ; free virtual = 10129 +Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2919 ; free virtual = 9790 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 481486a0 -Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 323 ; free virtual = 10123 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2902 ; free virtual = 9776 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 15b3b8ca3 -Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 296 ; free virtual = 10097 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2873 ; free virtual = 9750 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 15b3b8ca3 -Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 296 ; free virtual = 10097 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2873 ; free virtual = 9750 Phase 1 Placer Initialization | Checksum: 15b3b8ca3 -Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 296 ; free virtual = 10097 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2873 ; free virtual = 9750 Phase 2 Global Placement -Phase 2 Global Placement | Checksum: 2099d531c +Phase 2 Global Placement | Checksum: 28ba1f6ee -Time (s): cpu = 00:00:17 ; elapsed = 00:00:10 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 203 ; free virtual = 9985 +Time (s): cpu = 00:00:15 ; elapsed = 00:00:09 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2839 ; free virtual = 9717 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 2099d531c +Phase 3.1 Commit Multi Column Macros | Checksum: 28ba1f6ee -Time (s): cpu = 00:00:17 ; elapsed = 00:00:10 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 203 ; free virtual = 9985 +Time (s): cpu = 00:00:15 ; elapsed = 00:00:09 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2839 ; free virtual = 9717 Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 28ec86f4c +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 224dd24aa -Time (s): cpu = 00:00:18 ; elapsed = 00:00:11 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 198 ; free virtual = 9988 +Time (s): cpu = 00:00:17 ; elapsed = 00:00:10 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2831 ; free virtual = 9710 Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 2aec953a9 +Phase 3.3 Area Swap Optimization | Checksum: 21be4ef07 -Time (s): cpu = 00:00:19 ; elapsed = 00:00:11 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 162 ; free virtual = 9967 +Time (s): cpu = 00:00:17 ; elapsed = 00:00:10 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2831 ; free virtual = 9710 Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 2a4d19a1a +Phase 3.4 Pipeline Register Optimization | Checksum: 1feb18327 -Time (s): cpu = 00:00:19 ; elapsed = 00:00:11 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 161 ; free virtual = 9965 +Time (s): cpu = 00:00:17 ; elapsed = 00:00:10 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2831 ; free virtual = 9710 Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: 24929b323 +Phase 3.5 Small Shape Detail Placement | Checksum: 193e0a32b -Time (s): cpu = 00:00:22 ; elapsed = 00:00:14 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 184 ; free virtual = 9962 +Time (s): cpu = 00:00:19 ; elapsed = 00:00:11 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2824 ; free virtual = 9703 Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: 2e9643032 +Phase 3.6 Re-assign LUT pins | Checksum: 18aaafbc7 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:14 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 184 ; free virtual = 9962 +Time (s): cpu = 00:00:19 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2824 ; free virtual = 9704 Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: 2546130a1 +Phase 3.7 Pipeline Register Optimization | Checksum: 197a73366 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:14 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 184 ; free virtual = 9962 -Phase 3 Detail Placement | Checksum: 2546130a1 +Time (s): cpu = 00:00:19 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2824 ; free virtual = 9704 +Phase 3 Detail Placement | Checksum: 197a73366 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:14 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 184 ; free virtual = 9962 +Time (s): cpu = 00:00:19 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2824 ; free virtual = 9704 Phase 4 Post Placement Optimization and Clean-Up @@ -331,58 +331,58 @@ Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: 2334e3f23 +Post Placement Optimization Initialization | Checksum: 123adb6b7 Phase 4.1.1.1 BUFG Insertion INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 4 CPUs INFO: [Place 46-31] BUFG insertion identified 0 candidate nets, 0 success, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason. -Phase 4.1.1.1 BUFG Insertion | Checksum: 2334e3f23 +Phase 4.1.1.1 BUFG Insertion | Checksum: 123adb6b7 -Time (s): cpu = 00:00:24 ; elapsed = 00:00:16 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 164 ; free virtual = 9910 -INFO: [Place 30-746] Post Placement Timing Summary WNS=2.519. For the most accurate timing information please run report_timing. -Phase 4.1.1 Post Placement Optimization | Checksum: 153c570cc +Time (s): cpu = 00:00:21 ; elapsed = 00:00:13 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2847 ; free virtual = 9728 +INFO: [Place 30-746] Post Placement Timing Summary WNS=2.983. For the most accurate timing information please run report_timing. +Phase 4.1.1 Post Placement Optimization | Checksum: 16b6c8604 -Time (s): cpu = 00:00:24 ; elapsed = 00:00:16 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 180 ; free virtual = 9898 -Phase 4.1 Post Commit Optimization | Checksum: 153c570cc +Time (s): cpu = 00:00:21 ; elapsed = 00:00:13 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2847 ; free virtual = 9728 +Phase 4.1 Post Commit Optimization | Checksum: 16b6c8604 -Time (s): cpu = 00:00:24 ; elapsed = 00:00:16 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 173 ; free virtual = 9896 +Time (s): cpu = 00:00:21 ; elapsed = 00:00:13 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2847 ; free virtual = 9728 Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 153c570cc +Phase 4.2 Post Placement Cleanup | Checksum: 16b6c8604 -Time (s): cpu = 00:00:25 ; elapsed = 00:00:16 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 173 ; free virtual = 9896 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:13 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2847 ; free virtual = 9728 Phase 4.3 Placer Reporting -Phase 4.3 Placer Reporting | Checksum: 153c570cc +Phase 4.3 Placer Reporting | Checksum: 16b6c8604 -Time (s): cpu = 00:00:25 ; elapsed = 00:00:16 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 167 ; free virtual = 9891 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:13 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2848 ; free virtual = 9728 Phase 4.4 Final Placement Cleanup -Phase 4.4 Final Placement Cleanup | Checksum: 11c550246 +Phase 4.4 Final Placement Cleanup | Checksum: 133fc177e -Time (s): cpu = 00:00:25 ; elapsed = 00:00:16 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 172 ; free virtual = 9896 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 11c550246 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:13 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2848 ; free virtual = 9728 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 133fc177e -Time (s): cpu = 00:00:25 ; elapsed = 00:00:16 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 167 ; free virtual = 9891 -Ending Placer Task | Checksum: 1151bc0e7 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:13 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2848 ; free virtual = 9728 +Ending Placer Task | Checksum: bdda7aad -Time (s): cpu = 00:00:25 ; elapsed = 00:00:16 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 182 ; free virtual = 9900 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:13 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2854 ; free virtual = 9735 INFO: [Common 17-83] Releasing license: Implementation 66 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully -place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:18 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 181 ; free virtual = 9899 +place_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:15 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2854 ; free virtual = 9735 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00.99 ; elapsed = 00:00:00.50 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 172 ; free virtual = 9884 +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.42 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2837 ; free virtual = 9732 INFO: [Common 17-1381] The checkpoint '/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_placed.dcp' has been generated. INFO: [runtcl-4] Executing : report_io -file mz_petalinux_wrapper_io_placed.rpt -report_io: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 204 ; free virtual = 9782 +report_io: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2832 ; free virtual = 9718 INFO: [runtcl-4] Executing : report_utilization -file mz_petalinux_wrapper_utilization_placed.rpt -pb mz_petalinux_wrapper_utilization_placed.pb -report_utilization: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.18 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 255 ; free virtual = 9833 +report_utilization: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2842 ; free virtual = 9728 INFO: [runtcl-4] Executing : report_control_sets -verbose -file mz_petalinux_wrapper_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 241 ; free virtual = 9820 +report_control_sets: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2841 ; free virtual = 9727 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' @@ -394,130 +394,129 @@ INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more in Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs -Checksum: PlaceDB: 851d7f0c ConstDB: 0 ShapeSum: 8ffe41db RouteDB: 0 +Checksum: PlaceDB: 2ddc38d2 ConstDB: 0 ShapeSum: 8ffe41db RouteDB: 0 Phase 1 Build RT Design -Phase 1 Build RT Design | Checksum: 921bf8e5 +Phase 1 Build RT Design | Checksum: 11693f65c -Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 193 ; free virtual = 9747 -Post Restoration Checksum: NetGraph: 4242da12 NumContArr: 4fd91ed3 Constraints: 0 Timing: 0 +Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2896 ; free virtual = 9786 +Post Restoration Checksum: NetGraph: 825c6de0 NumContArr: 9437887c Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer -Phase 2.1 Create Timer | Checksum: 921bf8e5 +Phase 2.1 Create Timer | Checksum: 11693f65c -Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 192 ; free virtual = 9747 +Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2895 ; free virtual = 9785 Phase 2.2 Fix Topology Constraints -Phase 2.2 Fix Topology Constraints | Checksum: 921bf8e5 +Phase 2.2 Fix Topology Constraints | Checksum: 11693f65c -Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 178 ; free virtual = 9732 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2881 ; free virtual = 9771 Phase 2.3 Pre Route Cleanup -Phase 2.3 Pre Route Cleanup | Checksum: 921bf8e5 +Phase 2.3 Pre Route Cleanup | Checksum: 11693f65c -Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 178 ; free virtual = 9732 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2881 ; free virtual = 9771 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing -Phase 2.4 Update Timing | Checksum: 20cd07418 +Phase 2.4 Update Timing | Checksum: 232adc1f7 -Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 158 ; free virtual = 9713 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.639 | TNS=0.000 | WHS=-0.242 | THS=-464.001| +Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2843 ; free virtual = 9740 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.002 | TNS=0.000 | WHS=-0.293 | THS=-482.957| Phase 2.5 Update Timing for Bus Skew Phase 2.5.1 Update Timing -Phase 2.5.1 Update Timing | Checksum: 14930d1ce +Phase 2.5.1 Update Timing | Checksum: 242577426 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 171 ; free virtual = 9702 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.639 | TNS=0.000 | WHS=N/A | THS=N/A | +Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2839 ; free virtual = 9736 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.002 | TNS=0.000 | WHS=N/A | THS=N/A | -Phase 2.5 Update Timing for Bus Skew | Checksum: 14930d1ce +Phase 2.5 Update Timing for Bus Skew | Checksum: 242577426 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 171 ; free virtual = 9702 -Phase 2 Router Initialization | Checksum: 1e96f6bd0 +Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2839 ; free virtual = 9736 +Phase 2 Router Initialization | Checksum: 2051f3248 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 171 ; free virtual = 9702 +Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2839 ; free virtual = 9736 Phase 3 Initial Routing -Phase 3 Initial Routing | Checksum: 81038146 +Phase 3 Initial Routing | Checksum: 1c45f8fc9 -Time (s): cpu = 00:00:15 ; elapsed = 00:00:10 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 176 ; free virtual = 9707 +Time (s): cpu = 00:00:15 ; elapsed = 00:00:10 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2844 ; free virtual = 9741 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 697 - Number of Nodes with overlaps = 29 - Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 760 + Number of Nodes with overlaps = 54 + Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.454 | TNS=0.000 | WHS=N/A | THS=N/A | +INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.171 | TNS=0.000 | WHS=N/A | THS=N/A | -Phase 4.1 Global Iteration 0 | Checksum: 18a3a7bb3 +Phase 4.1 Global Iteration 0 | Checksum: 10de83a6c -Time (s): cpu = 00:00:20 ; elapsed = 00:00:11 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 176 ; free virtual = 9706 +Time (s): cpu = 00:00:25 ; elapsed = 00:00:14 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2208 ; free virtual = 9131 Phase 4.2 Global Iteration 1 - Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.454 | TNS=0.000 | WHS=N/A | THS=N/A | +INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.171 | TNS=0.000 | WHS=N/A | THS=N/A | -Phase 4.2 Global Iteration 1 | Checksum: 1657aed59 +Phase 4.2 Global Iteration 1 | Checksum: 18eec784f -Time (s): cpu = 00:00:20 ; elapsed = 00:00:11 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 175 ; free virtual = 9706 +Time (s): cpu = 00:00:27 ; elapsed = 00:00:15 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2115 ; free virtual = 9098 +Phase 4 Rip-up And Reroute | Checksum: 18eec784f -Phase 4.3 Global Iteration 2 - Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.454 | TNS=0.000 | WHS=N/A | THS=N/A | +Time (s): cpu = 00:00:27 ; elapsed = 00:00:15 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2114 ; free virtual = 9097 -Phase 4.3 Global Iteration 2 | Checksum: 1227e9218 +Phase 5 Delay and Skew Optimization -Time (s): cpu = 00:00:20 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 175 ; free virtual = 9706 -Phase 4 Rip-up And Reroute | Checksum: 1227e9218 +Phase 5.1 Delay CleanUp -Time (s): cpu = 00:00:20 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 175 ; free virtual = 9706 +Phase 5.1.1 Update Timing +Phase 5.1.1 Update Timing | Checksum: 188f53d45 -Phase 5 Delay and Skew Optimization +Time (s): cpu = 00:00:28 ; elapsed = 00:00:16 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2070 ; free virtual = 9054 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.249 | TNS=0.000 | WHS=N/A | THS=N/A | -Phase 5.1 Delay CleanUp -Phase 5.1 Delay CleanUp | Checksum: 1227e9218 +Phase 5.1 Delay CleanUp | Checksum: 16a992921 -Time (s): cpu = 00:00:20 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 175 ; free virtual = 9706 +Time (s): cpu = 00:00:28 ; elapsed = 00:00:16 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2070 ; free virtual = 9053 Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: 1227e9218 +Phase 5.2 Clock Skew Optimization | Checksum: 16a992921 -Time (s): cpu = 00:00:20 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 175 ; free virtual = 9706 -Phase 5 Delay and Skew Optimization | Checksum: 1227e9218 +Time (s): cpu = 00:00:28 ; elapsed = 00:00:16 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2060 ; free virtual = 9043 +Phase 5 Delay and Skew Optimization | Checksum: 16a992921 -Time (s): cpu = 00:00:20 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 175 ; free virtual = 9706 +Time (s): cpu = 00:00:28 ; elapsed = 00:00:16 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2059 ; free virtual = 9042 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: 15985f9cc +Phase 6.1.1 Update Timing | Checksum: 19cb5fe22 -Time (s): cpu = 00:00:21 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 175 ; free virtual = 9706 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.467 | TNS=0.000 | WHS=0.021 | THS=0.000 | +Time (s): cpu = 00:00:29 ; elapsed = 00:00:16 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2035 ; free virtual = 9018 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.249 | TNS=0.000 | WHS=0.021 | THS=0.000 | -Phase 6.1 Hold Fix Iter | Checksum: 177fc19ad +Phase 6.1 Hold Fix Iter | Checksum: 169622dd0 -Time (s): cpu = 00:00:21 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 175 ; free virtual = 9706 -Phase 6 Post Hold Fix | Checksum: 177fc19ad +Time (s): cpu = 00:00:29 ; elapsed = 00:00:17 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2033 ; free virtual = 9017 +Phase 6 Post Hold Fix | Checksum: 169622dd0 -Time (s): cpu = 00:00:21 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 175 ; free virtual = 9706 +Time (s): cpu = 00:00:29 ; elapsed = 00:00:17 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2033 ; free virtual = 9017 Phase 7 Route finalize Router Utilization Summary - Global Vertical Routing Utilization = 4.01591 % - Global Horizontal Routing Utilization = 5.28424 % + Global Vertical Routing Utilization = 3.97508 % + Global Horizontal Routing Utilization = 5.28975 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. @@ -526,43 +525,43 @@ Router Utilization Summary Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 -Phase 7 Route finalize | Checksum: 143f6d857 +Phase 7 Route finalize | Checksum: 1c199880b -Time (s): cpu = 00:00:21 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 175 ; free virtual = 9706 +Time (s): cpu = 00:00:29 ; elapsed = 00:00:17 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2033 ; free virtual = 9017 Phase 8 Verifying routed nets Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 143f6d857 +Phase 8 Verifying routed nets | Checksum: 1c199880b -Time (s): cpu = 00:00:21 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 175 ; free virtual = 9705 +Time (s): cpu = 00:00:29 ; elapsed = 00:00:17 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2033 ; free virtual = 9017 Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 13ee7ff31 +Phase 9 Depositing Routes | Checksum: 1df26a672 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 178 ; free virtual = 9705 +Time (s): cpu = 00:00:30 ; elapsed = 00:00:17 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2010 ; free virtual = 8996 Phase 10 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=2.467 | TNS=0.000 | WHS=0.021 | THS=0.000 | +INFO: [Route 35-57] Estimated Timing Summary | WNS=3.249 | TNS=0.000 | WHS=0.021 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. -Phase 10 Post Router Timing | Checksum: 13ee7ff31 +Phase 10 Post Router Timing | Checksum: 1df26a672 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 178 ; free virtual = 9705 +Time (s): cpu = 00:00:30 ; elapsed = 00:00:17 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2009 ; free virtual = 8995 INFO: [Route 35-16] Router Completed Successfully -Time (s): cpu = 00:00:22 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 196 ; free virtual = 9724 +Time (s): cpu = 00:00:30 ; elapsed = 00:00:17 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2026 ; free virtual = 9012 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 85 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully -route_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:14 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 196 ; free virtual = 9724 +route_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:19 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2026 ; free virtual = 9012 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.47 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 175 ; free virtual = 9721 +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.80 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 1973 ; free virtual = 8978 INFO: [Common 17-1381] The checkpoint '/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_routed.dcp' has been generated. INFO: [runtcl-4] Executing : report_drc -file mz_petalinux_wrapper_drc_routed.rpt -pb mz_petalinux_wrapper_drc_routed.pb -rpx mz_petalinux_wrapper_drc_routed.rpx Command: report_drc -file mz_petalinux_wrapper_drc_routed.rpt -pb mz_petalinux_wrapper_drc_routed.pb -rpx mz_petalinux_wrapper_drc_routed.rpx @@ -595,13 +594,13 @@ WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Pl INFO: [runtcl-4] Executing : report_incremental_reuse -file mz_petalinux_wrapper_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. INFO: [runtcl-4] Executing : report_clock_utilization -file mz_petalinux_wrapper_clock_utilization_routed.rpt -INFO: [Common 17-206] Exiting Vivado at Sat Oct 19 01:14:37 2019... +INFO: [Common 17-206] Exiting Vivado at Sun Oct 20 22:46:47 2019... #----------------------------------------------------------- # Vivado v2017.4 (64-bit) # SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017 # IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 -# Start of session at: Sat Oct 19 01:15:01 2019 -# Process ID: 12723 +# Start of session at: Sun Oct 20 22:46:53 2019 +# Process ID: 8060 # Current directory: /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1 # Command line: vivado -log mz_petalinux_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source mz_petalinux_wrapper.tcl -notrace # Log file: /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper.vdi @@ -612,26 +611,26 @@ Command: open_checkpoint mz_petalinux_wrapper_routed.dcp Starting open_checkpoint Task -Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1161.836 ; gain = 0.000 ; free physical = 1248 ; free virtual = 10615 +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.06 . Memory (MB): peak = 1161.832 ; gain = 0.000 ; free physical = 2609 ; free virtual = 9617 INFO: [Netlist 29-17] Analyzing 246 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2017.4 INFO: [Device 21-403] Loading part xc7z010clg400-1 INFO: [Project 1-570] Preparing netlist for logic optimization -Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.Xil/Vivado-12723-nats-MS-7A72/dcp1/mz_petalinux_wrapper_board.xdc] -Finished Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.Xil/Vivado-12723-nats-MS-7A72/dcp1/mz_petalinux_wrapper_board.xdc] -Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.Xil/Vivado-12723-nats-MS-7A72/dcp1/mz_petalinux_wrapper_early.xdc] -Finished Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.Xil/Vivado-12723-nats-MS-7A72/dcp1/mz_petalinux_wrapper_early.xdc] -Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.Xil/Vivado-12723-nats-MS-7A72/dcp1/mz_petalinux_wrapper.xdc] -Finished Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.Xil/Vivado-12723-nats-MS-7A72/dcp1/mz_petalinux_wrapper.xdc] -Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.Xil/Vivado-12723-nats-MS-7A72/dcp1/mz_petalinux_wrapper_late.xdc] -Finished Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.Xil/Vivado-12723-nats-MS-7A72/dcp1/mz_petalinux_wrapper_late.xdc] +Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.Xil/Vivado-8060-nats-MS-7A72/dcp1/mz_petalinux_wrapper_board.xdc] +Finished Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.Xil/Vivado-8060-nats-MS-7A72/dcp1/mz_petalinux_wrapper_board.xdc] +Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.Xil/Vivado-8060-nats-MS-7A72/dcp1/mz_petalinux_wrapper_early.xdc] +Finished Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.Xil/Vivado-8060-nats-MS-7A72/dcp1/mz_petalinux_wrapper_early.xdc] +Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.Xil/Vivado-8060-nats-MS-7A72/dcp1/mz_petalinux_wrapper.xdc] +Finished Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.Xil/Vivado-8060-nats-MS-7A72/dcp1/mz_petalinux_wrapper.xdc] +Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.Xil/Vivado-8060-nats-MS-7A72/dcp1/mz_petalinux_wrapper_late.xdc] +Finished Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/.Xil/Vivado-8060-nats-MS-7A72/dcp1/mz_petalinux_wrapper_late.xdc] Reading XDEF placement. Reading placer database... Reading XDEF routing. -Read XDEF File: Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:00.45 . Memory (MB): peak = 1529.309 ; gain = 13.000 ; free physical = 885 ; free virtual = 10282 -Restored from archive | CPU: 0.450000 secs | Memory: 10.746582 MB | -Finished XDEF File Restore: Time (s): cpu = 00:00:00.44 ; elapsed = 00:00:00.45 . Memory (MB): peak = 1529.309 ; gain = 13.000 ; free physical = 885 ; free virtual = 10282 +Read XDEF File: Time (s): cpu = 00:00:00.61 ; elapsed = 00:00:00.63 . Memory (MB): peak = 1530.305 ; gain = 13.000 ; free physical = 318 ; free virtual = 7387 +Restored from archive | CPU: 0.630000 secs | Memory: 10.738251 MB | +Finished XDEF File Restore: Time (s): cpu = 00:00:00.61 ; elapsed = 00:00:00.63 . Memory (MB): peak = 1530.305 ; gain = 13.000 ; free physical = 318 ; free virtual = 7387 INFO: [Project 1-111] Unisim Transformation Summary: A total of 150 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 2 instances @@ -639,7 +638,7 @@ INFO: [Project 1-111] Unisim Transformation Summary: RAM32M => RAM32M (RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMD32, RAMS32, RAMS32): 146 instances INFO: [Project 1-604] Checkpoint was created with Vivado v2017.4 (64-bit) build 2086221 -open_checkpoint: Time (s): cpu = 00:00:12 ; elapsed = 00:00:23 . Memory (MB): peak = 1529.309 ; gain = 367.473 ; free physical = 917 ; free virtual = 10292 +open_checkpoint: Time (s): cpu = 00:00:14 ; elapsed = 00:00:25 . Memory (MB): peak = 1530.305 ; gain = 368.473 ; free physical = 337 ; free virtual = 7387 WARNING: [Memdata 28-167] Found XPM memory block mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block. WARNING: [Memdata 28-167] Found XPM memory block mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block. WARNING: [Memdata 28-167] Found XPM memory block mz_petalinux_i/axi_smc/inst/s02_nodes/s02_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst with a P_MEMORY_PRIMITIVE property set to distributed. A value of block is required. You will not be able to use the updatemem program to update the bitstream with new data for the mz_petalinux_i/axi_smc/inst/s02_nodes/s02_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst block. @@ -687,9 +686,9 @@ Writing bitstream ./mz_petalinux_wrapper.bit... Writing bitstream ./mz_petalinux_wrapper.bin... INFO: [Vivado 12-1842] Bitgen Completed Successfully. INFO: [Project 1-118] WebTalk data collection is enabled (User setting is ON. Install Setting is ON.). -INFO: [Common 17-186] '/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Sat Oct 19 01:17:56 2019. For additional details about this file, please refer to the WebTalk help file at /home/nats/Xilinx/Vivado/2017.4/doc/webtalk_introduction.html. +INFO: [Common 17-186] '/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/usage_statistics_webtalk.xml' has been successfully sent to Xilinx on Sun Oct 20 22:49:55 2019. For additional details about this file, please refer to the WebTalk help file at /home/nats/Xilinx/Vivado/2017.4/doc/webtalk_introduction.html. INFO: [Common 17-83] Releasing license: Implementation 22 Infos, 23 Warnings, 0 Critical Warnings and 0 Errors encountered. write_bitstream completed successfully -write_bitstream: Time (s): cpu = 00:00:15 ; elapsed = 00:02:24 . Memory (MB): peak = 1965.738 ; gain = 436.430 ; free physical = 938 ; free virtual = 10372 -INFO: [Common 17-206] Exiting Vivado at Sat Oct 19 01:17:56 2019... +write_bitstream: Time (s): cpu = 00:00:20 ; elapsed = 00:02:29 . Memory (MB): peak = 1957.805 ; gain = 427.500 ; free physical = 431 ; free virtual = 6811 +INFO: [Common 17-206] Exiting Vivado at Sun Oct 20 22:49:55 2019... diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_11113.backup.vdi b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_6337.backup.vdi similarity index 80% rename from petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_11113.backup.vdi rename to petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_6337.backup.vdi index e3d07108691fe169d0948711b9276b1d3b074047..3d548115577dd05e3c3195e3aa05b482ec2634bf 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_11113.backup.vdi +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_6337.backup.vdi @@ -2,8 +2,8 @@ # Vivado v2017.4 (64-bit) # SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017 # IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 -# Start of session at: Sat Oct 19 01:12:45 2019 -# Process ID: 11113 +# Start of session at: Sun Oct 20 22:44:52 2019 +# Process ID: 6337 # Current directory: /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1 # Command line: vivado -log mz_petalinux_wrapper.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source mz_petalinux_wrapper.tcl -notrace # Log file: /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper.vdi @@ -140,7 +140,7 @@ INFO: [Project 1-111] Unisim Transformation Summary: 23 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully -link_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:39 . Memory (MB): peak = 2119.613 ; gain = 878.508 ; free physical = 220 ; free virtual = 10178 +link_design: Time (s): cpu = 00:00:22 ; elapsed = 00:00:40 . Memory (MB): peak = 2121.133 ; gain = 877.500 ; free physical = 2986 ; free virtual = 9841 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' @@ -151,7 +151,7 @@ INFO: [DRC 23-27] Running DRC with 4 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.94 . Memory (MB): peak = 2151.621 ; gain = 32.008 ; free physical = 203 ; free virtual = 10164 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.78 . Memory (MB): peak = 2153.141 ; gain = 32.008 ; free physical = 2974 ; free virtual = 9831 INFO: [Timing 38-35] Done setting XDC timing constraints. Starting Logic Optimization Task @@ -159,42 +159,42 @@ Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 21 inverter(s) to 94 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: 1e945c820 +Phase 1 Retarget | Checksum: 27c7187ff -Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.81 . Memory (MB): peak = 2151.621 ; gain = 0.000 ; free physical = 198 ; free virtual = 10159 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.84 . Memory (MB): peak = 2153.141 ; gain = 0.000 ; free physical = 2976 ; free virtual = 9833 INFO: [Opt 31-389] Phase Retarget created 177 cells and removed 326 cells Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 2 inverter(s) to 10 load pin(s). -Phase 2 Constant propagation | Checksum: 23c38d198 +Phase 2 Constant propagation | Checksum: 27c5940a0 -Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2151.621 ; gain = 0.000 ; free physical = 198 ; free virtual = 10159 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 2153.141 ; gain = 0.000 ; free physical = 2975 ; free virtual = 9832 INFO: [Opt 31-389] Phase Constant propagation created 414 cells and removed 1375 cells Phase 3 Sweep -Phase 3 Sweep | Checksum: 228e8aad1 +Phase 3 Sweep | Checksum: 1b70185b9 -Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2151.621 ; gain = 0.000 ; free physical = 197 ; free virtual = 10158 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2153.141 ; gain = 0.000 ; free physical = 2966 ; free virtual = 9824 INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 1386 cells Phase 4 BUFG optimization -Phase 4 BUFG optimization | Checksum: 228e8aad1 +Phase 4 BUFG optimization | Checksum: 1b70185b9 -Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2151.621 ; gain = 0.000 ; free physical = 197 ; free virtual = 10158 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2153.141 ; gain = 0.000 ; free physical = 2967 ; free virtual = 9825 INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells Phase 5 Shift Register Optimization -Phase 5 Shift Register Optimization | Checksum: 228e8aad1 +Phase 5 Shift Register Optimization | Checksum: 1b70185b9 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 2151.621 ; gain = 0.000 ; free physical = 194 ; free virtual = 10155 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 2153.141 ; gain = 0.000 ; free physical = 2968 ; free virtual = 9826 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Starting Connectivity Check Task -Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2151.621 ; gain = 0.000 ; free physical = 187 ; free virtual = 10148 -Ending Logic Optimization Task | Checksum: 1bccbb098 +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2153.141 ; gain = 0.000 ; free physical = 2967 ; free virtual = 9826 +Ending Logic Optimization Task | Checksum: 1c2580116 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2151.621 ; gain = 0.000 ; free physical = 187 ; free virtual = 10148 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:04 . Memory (MB): peak = 2153.141 ; gain = 0.000 ; free physical = 2967 ; free virtual = 9826 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. @@ -211,21 +211,21 @@ Starting PowerOpt Patch Enables Task INFO: [Pwropt 34-162] WRITE_MODE attribute of 0 BRAM(s) out of a total of 2 has been updated to save power. Run report_power_opt to get a complete listing of the BRAMs updated. INFO: [Pwropt 34-201] Structural ODC has moved 0 WE to EN ports Number of BRAM Ports augmented: 2 newly gated: 0 Total Ports: 4 -Ending PowerOpt Patch Enables Task | Checksum: 1e185de09 +Ending PowerOpt Patch Enables Task | Checksum: 2117c7f30 -Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 333 ; free virtual = 10127 -Ending Power Optimization Task | Checksum: 1e185de09 +Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.05 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2937 ; free virtual = 9800 +Ending Power Optimization Task | Checksum: 2117c7f30 -Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2437.027 ; gain = 285.406 ; free physical = 345 ; free virtual = 10139 +Time (s): cpu = 00:00:04 ; elapsed = 00:00:02 . Memory (MB): peak = 2437.586 ; gain = 284.445 ; free physical = 2949 ; free virtual = 9812 INFO: [Common 17-83] Releasing license: Implementation 44 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully -opt_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 2437.027 ; gain = 317.414 ; free physical = 345 ; free virtual = 10139 +opt_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:08 . Memory (MB): peak = 2437.586 ; gain = 316.453 ; free physical = 2949 ; free virtual = 9812 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 342 ; free virtual = 10139 +Write XDEF Complete: Time (s): cpu = 00:00:00.06 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2945 ; free virtual = 9811 INFO: [Common 17-1381] The checkpoint '/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_opt.dcp' has been generated. INFO: [runtcl-4] Executing : report_drc -file mz_petalinux_wrapper_drc_opted.rpt -pb mz_petalinux_wrapper_drc_opted.pb -rpx mz_petalinux_wrapper_drc_opted.rpx Command: report_drc -file mz_petalinux_wrapper_drc_opted.rpt -pb mz_petalinux_wrapper_drc_opted.pb -rpx mz_petalinux_wrapper_drc_opted.rpx @@ -253,77 +253,77 @@ INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 326 ; free virtual = 10126 +Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.03 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2916 ; free virtual = 9786 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 16d2ffea9 -Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 325 ; free virtual = 10125 +Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.04 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2916 ; free virtual = 9786 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 328 ; free virtual = 10129 +Netlist sorting complete. Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2919 ; free virtual = 9790 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 481486a0 -Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 323 ; free virtual = 10123 +Time (s): cpu = 00:00:03 ; elapsed = 00:00:03 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2902 ; free virtual = 9776 Phase 1.3 Build Placer Netlist Model Phase 1.3 Build Placer Netlist Model | Checksum: 15b3b8ca3 -Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 296 ; free virtual = 10097 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2873 ; free virtual = 9750 Phase 1.4 Constrain Clocks/Macros Phase 1.4 Constrain Clocks/Macros | Checksum: 15b3b8ca3 -Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 296 ; free virtual = 10097 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2873 ; free virtual = 9750 Phase 1 Placer Initialization | Checksum: 15b3b8ca3 -Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 296 ; free virtual = 10097 +Time (s): cpu = 00:00:06 ; elapsed = 00:00:04 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2873 ; free virtual = 9750 Phase 2 Global Placement -Phase 2 Global Placement | Checksum: 2099d531c +Phase 2 Global Placement | Checksum: 28ba1f6ee -Time (s): cpu = 00:00:17 ; elapsed = 00:00:10 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 203 ; free virtual = 9985 +Time (s): cpu = 00:00:15 ; elapsed = 00:00:09 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2839 ; free virtual = 9717 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 2099d531c +Phase 3.1 Commit Multi Column Macros | Checksum: 28ba1f6ee -Time (s): cpu = 00:00:17 ; elapsed = 00:00:10 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 203 ; free virtual = 9985 +Time (s): cpu = 00:00:15 ; elapsed = 00:00:09 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2839 ; free virtual = 9717 Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 28ec86f4c +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 224dd24aa -Time (s): cpu = 00:00:18 ; elapsed = 00:00:11 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 198 ; free virtual = 9988 +Time (s): cpu = 00:00:17 ; elapsed = 00:00:10 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2831 ; free virtual = 9710 Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 2aec953a9 +Phase 3.3 Area Swap Optimization | Checksum: 21be4ef07 -Time (s): cpu = 00:00:19 ; elapsed = 00:00:11 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 162 ; free virtual = 9967 +Time (s): cpu = 00:00:17 ; elapsed = 00:00:10 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2831 ; free virtual = 9710 Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 2a4d19a1a +Phase 3.4 Pipeline Register Optimization | Checksum: 1feb18327 -Time (s): cpu = 00:00:19 ; elapsed = 00:00:11 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 161 ; free virtual = 9965 +Time (s): cpu = 00:00:17 ; elapsed = 00:00:10 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2831 ; free virtual = 9710 Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: 24929b323 +Phase 3.5 Small Shape Detail Placement | Checksum: 193e0a32b -Time (s): cpu = 00:00:22 ; elapsed = 00:00:14 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 184 ; free virtual = 9962 +Time (s): cpu = 00:00:19 ; elapsed = 00:00:11 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2824 ; free virtual = 9703 Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: 2e9643032 +Phase 3.6 Re-assign LUT pins | Checksum: 18aaafbc7 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:14 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 184 ; free virtual = 9962 +Time (s): cpu = 00:00:19 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2824 ; free virtual = 9704 Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: 2546130a1 +Phase 3.7 Pipeline Register Optimization | Checksum: 197a73366 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:14 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 184 ; free virtual = 9962 -Phase 3 Detail Placement | Checksum: 2546130a1 +Time (s): cpu = 00:00:19 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2824 ; free virtual = 9704 +Phase 3 Detail Placement | Checksum: 197a73366 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:14 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 184 ; free virtual = 9962 +Time (s): cpu = 00:00:19 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2824 ; free virtual = 9704 Phase 4 Post Placement Optimization and Clean-Up @@ -331,58 +331,58 @@ Phase 4.1 Post Commit Optimization INFO: [Timing 38-35] Done setting XDC timing constraints. Phase 4.1.1 Post Placement Optimization -Post Placement Optimization Initialization | Checksum: 2334e3f23 +Post Placement Optimization Initialization | Checksum: 123adb6b7 Phase 4.1.1.1 BUFG Insertion INFO: [Physopt 32-721] Multithreading enabled for phys_opt_design using a maximum of 4 CPUs INFO: [Place 46-31] BUFG insertion identified 0 candidate nets, 0 success, 0 skipped for placement/routing, 0 skipped for timing, 0 skipped for netlist change reason. -Phase 4.1.1.1 BUFG Insertion | Checksum: 2334e3f23 +Phase 4.1.1.1 BUFG Insertion | Checksum: 123adb6b7 -Time (s): cpu = 00:00:24 ; elapsed = 00:00:16 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 164 ; free virtual = 9910 -INFO: [Place 30-746] Post Placement Timing Summary WNS=2.519. For the most accurate timing information please run report_timing. -Phase 4.1.1 Post Placement Optimization | Checksum: 153c570cc +Time (s): cpu = 00:00:21 ; elapsed = 00:00:13 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2847 ; free virtual = 9728 +INFO: [Place 30-746] Post Placement Timing Summary WNS=2.983. For the most accurate timing information please run report_timing. +Phase 4.1.1 Post Placement Optimization | Checksum: 16b6c8604 -Time (s): cpu = 00:00:24 ; elapsed = 00:00:16 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 180 ; free virtual = 9898 -Phase 4.1 Post Commit Optimization | Checksum: 153c570cc +Time (s): cpu = 00:00:21 ; elapsed = 00:00:13 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2847 ; free virtual = 9728 +Phase 4.1 Post Commit Optimization | Checksum: 16b6c8604 -Time (s): cpu = 00:00:24 ; elapsed = 00:00:16 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 173 ; free virtual = 9896 +Time (s): cpu = 00:00:21 ; elapsed = 00:00:13 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2847 ; free virtual = 9728 Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 153c570cc +Phase 4.2 Post Placement Cleanup | Checksum: 16b6c8604 -Time (s): cpu = 00:00:25 ; elapsed = 00:00:16 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 173 ; free virtual = 9896 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:13 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2847 ; free virtual = 9728 Phase 4.3 Placer Reporting -Phase 4.3 Placer Reporting | Checksum: 153c570cc +Phase 4.3 Placer Reporting | Checksum: 16b6c8604 -Time (s): cpu = 00:00:25 ; elapsed = 00:00:16 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 167 ; free virtual = 9891 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:13 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2848 ; free virtual = 9728 Phase 4.4 Final Placement Cleanup -Phase 4.4 Final Placement Cleanup | Checksum: 11c550246 +Phase 4.4 Final Placement Cleanup | Checksum: 133fc177e -Time (s): cpu = 00:00:25 ; elapsed = 00:00:16 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 172 ; free virtual = 9896 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 11c550246 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:13 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2848 ; free virtual = 9728 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 133fc177e -Time (s): cpu = 00:00:25 ; elapsed = 00:00:16 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 167 ; free virtual = 9891 -Ending Placer Task | Checksum: 1151bc0e7 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:13 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2848 ; free virtual = 9728 +Ending Placer Task | Checksum: bdda7aad -Time (s): cpu = 00:00:25 ; elapsed = 00:00:16 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 182 ; free virtual = 9900 +Time (s): cpu = 00:00:22 ; elapsed = 00:00:13 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2854 ; free virtual = 9735 INFO: [Common 17-83] Releasing license: Implementation 66 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully -place_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:18 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 181 ; free virtual = 9899 +place_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:15 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2854 ; free virtual = 9735 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00.99 ; elapsed = 00:00:00.50 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 172 ; free virtual = 9884 +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.42 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2837 ; free virtual = 9732 INFO: [Common 17-1381] The checkpoint '/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_placed.dcp' has been generated. INFO: [runtcl-4] Executing : report_io -file mz_petalinux_wrapper_io_placed.rpt -report_io: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 204 ; free virtual = 9782 +report_io: Time (s): cpu = 00:00:00.12 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2832 ; free virtual = 9718 INFO: [runtcl-4] Executing : report_utilization -file mz_petalinux_wrapper_utilization_placed.rpt -pb mz_petalinux_wrapper_utilization_placed.pb -report_utilization: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.18 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 255 ; free virtual = 9833 +report_utilization: Time (s): cpu = 00:00:00.13 ; elapsed = 00:00:00.17 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2842 ; free virtual = 9728 INFO: [runtcl-4] Executing : report_control_sets -verbose -file mz_petalinux_wrapper_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.13 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 241 ; free virtual = 9820 +report_control_sets: Time (s): cpu = 00:00:00.09 ; elapsed = 00:00:00.14 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2841 ; free virtual = 9727 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' @@ -394,130 +394,129 @@ INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more in Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs -Checksum: PlaceDB: 851d7f0c ConstDB: 0 ShapeSum: 8ffe41db RouteDB: 0 +Checksum: PlaceDB: 2ddc38d2 ConstDB: 0 ShapeSum: 8ffe41db RouteDB: 0 Phase 1 Build RT Design -Phase 1 Build RT Design | Checksum: 921bf8e5 +Phase 1 Build RT Design | Checksum: 11693f65c -Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 193 ; free virtual = 9747 -Post Restoration Checksum: NetGraph: 4242da12 NumContArr: 4fd91ed3 Constraints: 0 Timing: 0 +Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2896 ; free virtual = 9786 +Post Restoration Checksum: NetGraph: 825c6de0 NumContArr: 9437887c Constraints: 0 Timing: 0 Phase 2 Router Initialization Phase 2.1 Create Timer -Phase 2.1 Create Timer | Checksum: 921bf8e5 +Phase 2.1 Create Timer | Checksum: 11693f65c -Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 192 ; free virtual = 9747 +Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2895 ; free virtual = 9785 Phase 2.2 Fix Topology Constraints -Phase 2.2 Fix Topology Constraints | Checksum: 921bf8e5 +Phase 2.2 Fix Topology Constraints | Checksum: 11693f65c -Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 178 ; free virtual = 9732 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2881 ; free virtual = 9771 Phase 2.3 Pre Route Cleanup -Phase 2.3 Pre Route Cleanup | Checksum: 921bf8e5 +Phase 2.3 Pre Route Cleanup | Checksum: 11693f65c -Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 178 ; free virtual = 9732 +Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2881 ; free virtual = 9771 Number of Nodes with overlaps = 0 Phase 2.4 Update Timing -Phase 2.4 Update Timing | Checksum: 20cd07418 +Phase 2.4 Update Timing | Checksum: 232adc1f7 -Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 158 ; free virtual = 9713 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.639 | TNS=0.000 | WHS=-0.242 | THS=-464.001| +Time (s): cpu = 00:00:12 ; elapsed = 00:00:08 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2843 ; free virtual = 9740 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.002 | TNS=0.000 | WHS=-0.293 | THS=-482.957| Phase 2.5 Update Timing for Bus Skew Phase 2.5.1 Update Timing -Phase 2.5.1 Update Timing | Checksum: 14930d1ce +Phase 2.5.1 Update Timing | Checksum: 242577426 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 171 ; free virtual = 9702 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.639 | TNS=0.000 | WHS=N/A | THS=N/A | +Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2839 ; free virtual = 9736 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.002 | TNS=0.000 | WHS=N/A | THS=N/A | -Phase 2.5 Update Timing for Bus Skew | Checksum: 14930d1ce +Phase 2.5 Update Timing for Bus Skew | Checksum: 242577426 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 171 ; free virtual = 9702 -Phase 2 Router Initialization | Checksum: 1e96f6bd0 +Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2839 ; free virtual = 9736 +Phase 2 Router Initialization | Checksum: 2051f3248 -Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 171 ; free virtual = 9702 +Time (s): cpu = 00:00:13 ; elapsed = 00:00:09 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2839 ; free virtual = 9736 Phase 3 Initial Routing -Phase 3 Initial Routing | Checksum: 81038146 +Phase 3 Initial Routing | Checksum: 1c45f8fc9 -Time (s): cpu = 00:00:15 ; elapsed = 00:00:10 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 176 ; free virtual = 9707 +Time (s): cpu = 00:00:15 ; elapsed = 00:00:10 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2844 ; free virtual = 9741 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 - Number of Nodes with overlaps = 697 - Number of Nodes with overlaps = 29 - Number of Nodes with overlaps = 2 + Number of Nodes with overlaps = 760 + Number of Nodes with overlaps = 54 + Number of Nodes with overlaps = 4 Number of Nodes with overlaps = 1 Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.454 | TNS=0.000 | WHS=N/A | THS=N/A | +INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.171 | TNS=0.000 | WHS=N/A | THS=N/A | -Phase 4.1 Global Iteration 0 | Checksum: 18a3a7bb3 +Phase 4.1 Global Iteration 0 | Checksum: 10de83a6c -Time (s): cpu = 00:00:20 ; elapsed = 00:00:11 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 176 ; free virtual = 9706 +Time (s): cpu = 00:00:25 ; elapsed = 00:00:14 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2208 ; free virtual = 9131 Phase 4.2 Global Iteration 1 - Number of Nodes with overlaps = 1 + Number of Nodes with overlaps = 3 Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.454 | TNS=0.000 | WHS=N/A | THS=N/A | +INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.171 | TNS=0.000 | WHS=N/A | THS=N/A | -Phase 4.2 Global Iteration 1 | Checksum: 1657aed59 +Phase 4.2 Global Iteration 1 | Checksum: 18eec784f -Time (s): cpu = 00:00:20 ; elapsed = 00:00:11 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 175 ; free virtual = 9706 +Time (s): cpu = 00:00:27 ; elapsed = 00:00:15 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2115 ; free virtual = 9098 +Phase 4 Rip-up And Reroute | Checksum: 18eec784f -Phase 4.3 Global Iteration 2 - Number of Nodes with overlaps = 0 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.454 | TNS=0.000 | WHS=N/A | THS=N/A | +Time (s): cpu = 00:00:27 ; elapsed = 00:00:15 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2114 ; free virtual = 9097 -Phase 4.3 Global Iteration 2 | Checksum: 1227e9218 +Phase 5 Delay and Skew Optimization -Time (s): cpu = 00:00:20 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 175 ; free virtual = 9706 -Phase 4 Rip-up And Reroute | Checksum: 1227e9218 +Phase 5.1 Delay CleanUp -Time (s): cpu = 00:00:20 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 175 ; free virtual = 9706 +Phase 5.1.1 Update Timing +Phase 5.1.1 Update Timing | Checksum: 188f53d45 -Phase 5 Delay and Skew Optimization +Time (s): cpu = 00:00:28 ; elapsed = 00:00:16 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2070 ; free virtual = 9054 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.249 | TNS=0.000 | WHS=N/A | THS=N/A | -Phase 5.1 Delay CleanUp -Phase 5.1 Delay CleanUp | Checksum: 1227e9218 +Phase 5.1 Delay CleanUp | Checksum: 16a992921 -Time (s): cpu = 00:00:20 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 175 ; free virtual = 9706 +Time (s): cpu = 00:00:28 ; elapsed = 00:00:16 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2070 ; free virtual = 9053 Phase 5.2 Clock Skew Optimization -Phase 5.2 Clock Skew Optimization | Checksum: 1227e9218 +Phase 5.2 Clock Skew Optimization | Checksum: 16a992921 -Time (s): cpu = 00:00:20 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 175 ; free virtual = 9706 -Phase 5 Delay and Skew Optimization | Checksum: 1227e9218 +Time (s): cpu = 00:00:28 ; elapsed = 00:00:16 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2060 ; free virtual = 9043 +Phase 5 Delay and Skew Optimization | Checksum: 16a992921 -Time (s): cpu = 00:00:20 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 175 ; free virtual = 9706 +Time (s): cpu = 00:00:28 ; elapsed = 00:00:16 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2059 ; free virtual = 9042 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter Phase 6.1.1 Update Timing -Phase 6.1.1 Update Timing | Checksum: 15985f9cc +Phase 6.1.1 Update Timing | Checksum: 19cb5fe22 -Time (s): cpu = 00:00:21 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 175 ; free virtual = 9706 -INFO: [Route 35-416] Intermediate Timing Summary | WNS=2.467 | TNS=0.000 | WHS=0.021 | THS=0.000 | +Time (s): cpu = 00:00:29 ; elapsed = 00:00:16 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2035 ; free virtual = 9018 +INFO: [Route 35-416] Intermediate Timing Summary | WNS=3.249 | TNS=0.000 | WHS=0.021 | THS=0.000 | -Phase 6.1 Hold Fix Iter | Checksum: 177fc19ad +Phase 6.1 Hold Fix Iter | Checksum: 169622dd0 -Time (s): cpu = 00:00:21 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 175 ; free virtual = 9706 -Phase 6 Post Hold Fix | Checksum: 177fc19ad +Time (s): cpu = 00:00:29 ; elapsed = 00:00:17 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2033 ; free virtual = 9017 +Phase 6 Post Hold Fix | Checksum: 169622dd0 -Time (s): cpu = 00:00:21 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 175 ; free virtual = 9706 +Time (s): cpu = 00:00:29 ; elapsed = 00:00:17 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2033 ; free virtual = 9017 Phase 7 Route finalize Router Utilization Summary - Global Vertical Routing Utilization = 4.01591 % - Global Horizontal Routing Utilization = 5.28424 % + Global Vertical Routing Utilization = 3.97508 % + Global Horizontal Routing Utilization = 5.28975 % Routable Net Status* *Does not include unroutable nets such as driverless and loadless. Run report_route_status for detailed report. @@ -526,43 +525,43 @@ Router Utilization Summary Number of Partially Routed Nets = 0 Number of Node Overlaps = 0 -Phase 7 Route finalize | Checksum: 143f6d857 +Phase 7 Route finalize | Checksum: 1c199880b -Time (s): cpu = 00:00:21 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 175 ; free virtual = 9706 +Time (s): cpu = 00:00:29 ; elapsed = 00:00:17 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2033 ; free virtual = 9017 Phase 8 Verifying routed nets Verification completed successfully -Phase 8 Verifying routed nets | Checksum: 143f6d857 +Phase 8 Verifying routed nets | Checksum: 1c199880b -Time (s): cpu = 00:00:21 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 175 ; free virtual = 9705 +Time (s): cpu = 00:00:29 ; elapsed = 00:00:17 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2033 ; free virtual = 9017 Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 13ee7ff31 +Phase 9 Depositing Routes | Checksum: 1df26a672 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 178 ; free virtual = 9705 +Time (s): cpu = 00:00:30 ; elapsed = 00:00:17 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2010 ; free virtual = 8996 Phase 10 Post Router Timing -INFO: [Route 35-57] Estimated Timing Summary | WNS=2.467 | TNS=0.000 | WHS=0.021 | THS=0.000 | +INFO: [Route 35-57] Estimated Timing Summary | WNS=3.249 | TNS=0.000 | WHS=0.021 | THS=0.000 | INFO: [Route 35-327] The final timing numbers are based on the router estimated timing analysis. For a complete and accurate timing signoff, please run report_timing_summary. -Phase 10 Post Router Timing | Checksum: 13ee7ff31 +Phase 10 Post Router Timing | Checksum: 1df26a672 -Time (s): cpu = 00:00:22 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 178 ; free virtual = 9705 +Time (s): cpu = 00:00:30 ; elapsed = 00:00:17 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2009 ; free virtual = 8995 INFO: [Route 35-16] Router Completed Successfully -Time (s): cpu = 00:00:22 ; elapsed = 00:00:12 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 196 ; free virtual = 9724 +Time (s): cpu = 00:00:30 ; elapsed = 00:00:17 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2026 ; free virtual = 9012 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 85 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully -route_design: Time (s): cpu = 00:00:24 ; elapsed = 00:00:14 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 196 ; free virtual = 9724 +route_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:19 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 2026 ; free virtual = 9012 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.47 . Memory (MB): peak = 2437.027 ; gain = 0.000 ; free physical = 175 ; free virtual = 9721 +Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.80 . Memory (MB): peak = 2437.586 ; gain = 0.000 ; free physical = 1973 ; free virtual = 8978 INFO: [Common 17-1381] The checkpoint '/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_routed.dcp' has been generated. INFO: [runtcl-4] Executing : report_drc -file mz_petalinux_wrapper_drc_routed.rpt -pb mz_petalinux_wrapper_drc_routed.pb -rpx mz_petalinux_wrapper_drc_routed.rpx Command: report_drc -file mz_petalinux_wrapper_drc_routed.rpt -pb mz_petalinux_wrapper_drc_routed.pb -rpx mz_petalinux_wrapper_drc_routed.rpx @@ -595,4 +594,4 @@ WARNING: [Timing 38-436] There are set_bus_skew constraint(s) in this design. Pl INFO: [runtcl-4] Executing : report_incremental_reuse -file mz_petalinux_wrapper_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. INFO: [runtcl-4] Executing : report_clock_utilization -file mz_petalinux_wrapper_clock_utilization_routed.rpt -INFO: [Common 17-206] Exiting Vivado at Sat Oct 19 01:14:37 2019... +INFO: [Common 17-206] Exiting Vivado at Sun Oct 20 22:46:47 2019... diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_clock_utilization_routed.rpt b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_clock_utilization_routed.rpt index c77f54794594331c1678decb4c57014142482d06..45b3519d51d410aabeed62ab7ee1d026c537c738 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_clock_utilization_routed.rpt +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_clock_utilization_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 -| Date : Sat Oct 19 01:14:37 2019 +| Date : Sun Oct 20 22:46:47 2019 | Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS | Command : report_clock_utilization -file mz_petalinux_wrapper_clock_utilization_routed.rpt | Design : mz_petalinux_wrapper @@ -22,6 +22,7 @@ Table of Contents 7. Clock Region Cell Placement per Global Clock: Region X0Y0 8. Clock Region Cell Placement per Global Clock: Region X1Y0 9. Clock Region Cell Placement per Global Clock: Region X0Y1 +10. Clock Region Cell Placement per Global Clock: Region X1Y1 1. Clock Primitive Utilization ------------------------------ @@ -45,7 +46,7 @@ Table of Contents +-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+------------+------------------------------------------------------------------------------+----------------------------------------------------+ | Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | +-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+------------+------------------------------------------------------------------------------+----------------------------------------------------+ -| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 3 | 6276 | 0 | 10.000 | clk_fpga_0 | mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | +| g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 4 | 6276 | 0 | 10.000 | clk_fpga_0 | mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | +-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+------------+------------------------------------------------------------------------------+----------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) @@ -71,10 +72,10 @@ Table of Contents +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ | Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ -| X0Y0 | 1 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3334 | 1100 | 1131 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | -| X1Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 2379 | 1100 | 751 | 350 | 0 | 40 | 1 | 20 | 0 | 20 | -| X0Y1 | 1 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 207 | 1100 | 83 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | -| X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1100 | 0 | 350 | 0 | 40 | 0 | 20 | 0 | 20 | +| X0Y0 | 1 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 3321 | 1100 | 1126 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 2364 | 1100 | 772 | 350 | 0 | 40 | 1 | 20 | 0 | 20 | +| X0Y1 | 1 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 224 | 1100 | 95 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | +| X1Y1 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 11 | 1100 | 0 | 350 | 0 | 40 | 0 | 20 | 0 | 20 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ * Global Clock column represents track count; while other columns represents cell counts @@ -86,7 +87,7 @@ All Modules +----+----+----+ | | X0 | X1 | +----+----+----+ -| Y1 | 1 | 0 | +| Y1 | 1 | 1 | | Y0 | 1 | 1 | +----+----+----+ @@ -108,8 +109,8 @@ All Modules +----+-------+-------+ | | X0 | X1 | +----+-------+-------+ -| Y1 | 226 | 0 | -| Y0 | 3407 | 2493 | +| Y1 | 243 | 11 | +| Y0 | 3398 | 2474 | +----+-------+-------+ @@ -119,7 +120,7 @@ All Modules +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------+ -| g0 | n/a | BUFG/O | None | 3407 | 0 | 3334 | 73 | 0 | 0 | 0 | 0 | 0 | 0 | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | +| g0 | n/a | BUFG/O | None | 3398 | 0 | 3321 | 77 | 0 | 0 | 0 | 0 | 0 | 0 | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) @@ -132,7 +133,7 @@ All Modules +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------+ -| g0 | n/a | BUFG/O | None | 2493 | 0 | 2379 | 112 | 1 | 0 | 0 | 0 | 0 | 0 | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | +| g0 | n/a | BUFG/O | None | 2474 | 0 | 2364 | 108 | 1 | 0 | 0 | 0 | 0 | 0 | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | +-----------+-------+-----------------+------------+-------------+-----------------+------+--------+------+-----+----+------+-----+---------+----------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) @@ -145,13 +146,26 @@ All Modules +-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------------------------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------------------------------------------+ -| g0 | n/a | BUFG/O | None | 226 | 0 | 207 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | +| g0 | n/a | BUFG/O | None | 243 | 0 | 224 | 18 | 0 | 0 | 0 | 0 | 0 | 0 | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | +-----------+-------+-----------------+------------+-------------+-----------------+-----+--------+------+-----+----+------+-----+---------+----------------------------------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts +10. Clock Region Cell Placement per Global Clock: Region X1Y1 +------------------------------------------------------------- + ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------------------------------------------+ +| Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------------------------------------------+ +| g0 | n/a | BUFG/O | None | 11 | 0 | 11 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | ++-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+----------------------------------------------------+ +* Clock Loads column represents the clock pin loads (pin count) +** Non-Clock Loads column represents the non-clock pin loads (pin count) +*** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts + + # Location of BUFG Primitives set_property LOC BUFGCTRL_X0Y0 [get_cells mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG] @@ -164,5 +178,5 @@ set_property LOC BUFGCTRL_X0Y0 [get_cells mz_petalinux_i/processing_system7_0/in #startgroup create_pblock {CLKAG_mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0} add_cells_to_pblock [get_pblocks {CLKAG_mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0"}]]] -resize_pblock [get_pblocks {CLKAG_mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0} +resize_pblock [get_pblocks {CLKAG_mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0}] -add {CLOCKREGION_X0Y0:CLOCKREGION_X0Y0 CLOCKREGION_X0Y1:CLOCKREGION_X0Y1 CLOCKREGION_X1Y0:CLOCKREGION_X1Y0 CLOCKREGION_X1Y1:CLOCKREGION_X1Y1} #endgroup diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_control_sets_placed.rpt b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_control_sets_placed.rpt index 23cbce01c6482893537a9a57e0897793566972d2..45e9bfcb0214ed104bfe1e434c7254d690845d68 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_control_sets_placed.rpt +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_control_sets_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 -| Date : Sat Oct 19 01:14:11 2019 +| Date : Sun Oct 20 22:46:16 2019 | Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS | Command : report_control_sets -verbose -file mz_petalinux_wrapper_control_sets_placed.rpt | Design : mz_petalinux_wrapper @@ -33,12 +33,12 @@ Table of Contents +--------------+-----------------------+------------------------+-----------------+--------------+ | Clock Enable | Synchronous Set/Reset | Asynchronous Set/Reset | Total Registers | Total Slices | +--------------+-----------------------+------------------------+-----------------+--------------+ -| No | No | No | 1077 | 307 | +| No | No | No | 1077 | 312 | | No | No | Yes | 0 | 0 | -| No | Yes | No | 635 | 255 | -| Yes | No | No | 1915 | 478 | +| No | Yes | No | 635 | 251 | +| Yes | No | No | 1915 | 466 | | Yes | No | Yes | 0 | 0 | -| Yes | Yes | No | 2391 | 627 | +| Yes | Yes | No | 2391 | 623 | +--------------+-----------------------+------------------------+-----------------+--------------+ @@ -53,310 +53,310 @@ Table of Contents | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_entry_pipeline/s02_si_converter/inst/splitter_inst/gen_no_wsplitter.gen_endpoint_woffset.gen_wbypass_offset_fifo.wbypass_offset_fifo/gen_pipelined.load_mesg | mz_petalinux_i/axi_smc/inst/s02_entry_pipeline/s02_si_converter/inst/splitter_inst/gen_no_wsplitter.gen_endpoint_woffset.gen_wbypass_offset_fifo.wbypass_offset_fifo/gen_pipelined.mesg_reg[1]_i_1_n_0 | 1 | 1 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/gen_srls[0].srl_nx1/shift | | 1 | 1 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/first_xfer | | 1 | 1 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_request_fifos.gen_req_fifo[0].inst_req_fifo/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 2 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_si_handler/gen_m_axis_arb_fifo.inst_axis_arb_fifo/gen_srls[2].srl_nx1/shift | | 1 | 2 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_wr_fifo | | 1 | 2 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/bresp_push | | 1 | 2 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/b_sreg/skid_buffer[1057]_i_2_n_0 | mz_petalinux_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/b_sreg/skid_buffer[1057]_i_1_n_0 | 1 | 2 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_si_handler/gen_m_axis_arb_fifo.inst_axis_arb_fifo/gen_srls[2].srl_nx1/shift | | 1 | 2 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/gen_AB_reg_slice.payld_a | | 1 | 2 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/gen_AB_reg_slice.payld_b | | 1 | 2 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/gen_AB_reg_slice.payld_a | | 1 | 2 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/gen_AB_reg_slice.payld_b | | 1 | 2 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/bresp_push | | 1 | 2 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_request_fifos.gen_req_fifo[0].inst_req_fifo/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 2 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_request_fifos.gen_req_fifo[2].inst_req_fifo/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 2 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/b_sreg/skid_buffer[1057]_i_2_n_0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/b_sreg/skid_buffer[1057]_i_1_n_0 | 1 | 2 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/r_sreg/S00_AXI_rvalid | | 2 | 2 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/ar_reg_stall/skid_buffer[1144]_i_1_n_0 | | 1 | 2 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/ar_reg_stall/m_vector_i | | 1 | 2 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_wr_fifo | | 1 | 2 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/r_sreg/S00_AXI_rvalid | | 2 | 2 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_wr_fifo | | 1 | 2 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/exit_inst/gen_w_cmd_fifo.w_cmd_fifo/gen_srls[2].srl_nx1/shift_qual | | 1 | 2 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_b_node/inst/inst_mi_handler/areset_r | 1 | 3 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/areset_r | 2 | 3 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/s01_nodes/s01_r_node/inst/inst_mi_handler/areset_r | 2 | 3 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_b_node/inst/inst_mi_handler/areset_r | 2 | 3 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/areset_r | 3 | 3 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/s01_nodes/s01_r_node/inst/inst_mi_handler/areset_r | 3 | 3 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/ar_sreg/m_vector_i | | 1 | 3 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/areset_r | 2 | 3 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_b_node/inst/inst_mi_handler/areset_r | 3 | 3 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/ar_sreg/skid_buffer[1144]_i_1__0_n_0 | | 1 | 3 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_b_node/inst/inst_mi_handler/areset_r | 1 | 3 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/areset_r | 1 | 3 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/areset_r | 2 | 3 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sel | | 1 | 3 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/splitter_inst/gen_no_wsplitter.gen_endpoint_woffset.gen_wbypass_offset_fifo.wbypass_offset_fifo/gen_pipelined.load_mesg | | 2 | 4 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/areset_r | 2 | 3 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_burst_dbeat_cntr_reg[3] | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_burst_dbeat_cntr0 | 1 | 4 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_WRITE.REG3_WREADY/p_0_out_0 | 1 | 4 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_WRITE.REG3_WREADY/p_0_out_0 | 2 | 4 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/axlen_cnt_reg[4][0] | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/axlen_cnt_reg[7] | 2 | 4 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_DATA_CNTL/sig_data2mstr_cmd_ready | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_DATA_CNTL/sig_clr_dqual_reg | 1 | 4 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/splitter_inst/gen_no_wsplitter.gen_endpoint_woffset.gen_wbypass_offset_fifo.wbypass_offset_fifo/gen_pipelined.load_mesg | | 2 | 4 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/E[0] | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/axlen_cnt_reg[7] | 2 | 4 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_DATA_CNTL/sig_push_to_wsc_i_2_n_0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_DATA_CNTL/sig_push_to_wsc0 | 1 | 4 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/s_ready_i_reg_0 | 4 | 4 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/m_valid_i_reg_0 | 4 | 4 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/m_sc_areset_r | 1 | 4 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/E[0] | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RESET/mm2s_rlast_del_reg | 1 | 4 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_aw_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 4 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 4 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/gen_pipelined.load_mesg | | 1 | 4 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/s_ready_i_reg_0 | 3 | 4 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/m_valid_i_reg_0 | 3 | 4 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/ar_reg/skid_buffer_reg[1144]_0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/skid_buffer_reg[1128] | 1 | 4 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_DATA_CNTL/sig_push_to_wsc_i_2_n_0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_DATA_CNTL/sig_push_to_wsc0 | 1 | 4 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 4 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_DATA_CNTL/sig_data2mstr_cmd_ready | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_DATA_CNTL/sig_clr_dqual_reg | 1 | 4 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/lpf_int | 3 | 4 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_WRITE.awvalid_d1_i_1_n_0 | 1 | 4 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/E[0] | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/pushed_commands[3]_i_1__0_n_0 | 2 | 4 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/gen_pipelined.load_mesg | | 2 | 4 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/E[0] | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/pushed_commands[3]_i_1_n_0 | 1 | 4 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_BURSTS.cmd_queue/gen_srls[3].srl_nx1/shift | | 1 | 4 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/E[0] | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/pushed_commands[3]_i_1__0_n_0 | 2 | 4 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/E[0] | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RESET/mm2s_rlast_del_reg | 1 | 4 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 4 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_WRITE.awvalid_d1_i_1_n_0 | 1 | 4 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 4 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/I_WRESP_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/E[0] | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 2 | 4 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 4 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/clk_map/psr_aclk/U0/EXT_LPF/lpf_int | 2 | 4 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/s01_nodes/s01_ar_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 4 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/E[0] | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 2 | 4 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/splitter_inst/gen_no_wsplitter.gen_endpoint_woffset.gen_wbypass_offset_fifo.wbypass_offset_fifo/gen_srls[13].srl_nx1/shift | | 2 | 5 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_aw_node/inst/inst_mi_handler/m_sc_areset_r | 1 | 4 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_data_reg_out_en | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 2 | 5 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_s_ready_dup | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 1 | 5 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/splitter_inst/gen_no_wsplitter.gen_endpoint_woffset.gen_wbypass_offset_fifo.wbypass_offset_fifo/gen_srls[13].srl_nx1/shift | | 2 | 5 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/gen_pipelined.load_mesg | | 2 | 5 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RD_DATA_CNTL/sig_push_rd_sts_reg | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_rd_sts_tag_reg0 | 1 | 5 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/gen_srls[4].srl_nx1/shift | | 2 | 5 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_s_ready_dup | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 1 | 5 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RD_DATA_CNTL/sig_push_rd_sts_reg | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_rd_sts_tag_reg0 | 1 | 5 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/rst_ps7_0_100M/U0/EXT_LPF/lpf_int | 2 | 5 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/count_value_i_reg[1] | 2 | 5 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/areset_r | 3 | 5 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_ASYNC_READ.rvalid_reg | 4 | 5 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/count_value_i_reg[1] | 3 | 5 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/areset_r | 3 | 5 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/m_sc_areset_r | 4 | 6 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/E[0] | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 6 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/gen_normal_area.fifo_node_payld_pop_early | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 6 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/E[0] | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 6 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/rst_ps7_0_100M/U0/EXT_LPF/lpf_int | 2 | 5 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_ASYNC_READ.rvalid_reg | 3 | 5 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/areset_r | 4 | 5 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 6 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s01_nodes/s01_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/m_sc_req[0] | mz_petalinux_i/axi_smc/inst/s01_nodes/s01_ar_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 6 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s01_nodes/s01_r_node/inst/inst_si_handler/inst_arb_stall_late/count_r | mz_petalinux_i/axi_smc/inst/s01_nodes/s01_r_node/inst/inst_mi_handler/areset_r | 2 | 6 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/E[0] | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 6 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/count_r_reg[0][0] | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 6 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/aw_sreg/E[0] | mz_petalinux_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/areset | 2 | 6 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/rst_ps7_0_100M/U0/SEQ/seq_cnt_en | mz_petalinux_i/rst_ps7_0_100M/U0/SEQ/SEQ_COUNTER/clear | 1 | 6 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_si_handler/gen_si_handler.gen_arbiter_rr_normal_area.inst_arbiter/E[0] | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/areset_r | 3 | 6 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/w_sreg/E[0] | mz_petalinux_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/areset | 2 | 6 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/aw_sreg/E[0] | mz_petalinux_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/areset | 3 | 6 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/w_sreg/E[0] | mz_petalinux_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/areset | 3 | 6 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 6 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/inst_si_handler/gen_si_handler.gen_arbiter_rr_normal_area.inst_arbiter/s_sc_valid | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/areset_r | 2 | 6 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/clk_map/psr_aclk/U0/SEQ/seq_cnt_en | mz_petalinux_i/axi_smc/inst/clk_map/psr_aclk/U0/SEQ/SEQ_COUNTER/clear | 1 | 6 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 6 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_si_handler/inst_arb_stall_late/count_r | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/areset_r | 3 | 6 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/m_sc_req[0] | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_aw_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 6 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/E[0] | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_aw_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 6 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_entry_pipeline/s02_si_converter/inst/splitter_inst/gen_no_wsplitter.gen_endpoint_woffset.gen_wbypass_offset_fifo.wbypass_offset_fifo/gen_pipelined.load_mesg | | 2 | 6 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/r_reg/E[0] | | 1 | 6 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/rst_ps7_0_100M/U0/SEQ/seq_cnt_en | mz_petalinux_i/rst_ps7_0_100M/U0/SEQ/SEQ_COUNTER/clear | 1 | 6 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_entry_pipeline/s02_si_converter/inst/splitter_inst/gen_no_wsplitter.gen_endpoint_woffset.gen_wbypass_offset_fifo.wbypass_offset_fifo/gen_pipelined.load_mesg | | 3 | 6 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/r_reg/E[0] | | 2 | 6 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_b_node/inst/inst_si_handler/inst_arb_stall_late/s_sc_valid | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_b_node/inst/inst_mi_handler/areset_r | 2 | 6 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_m_valid_dup_reg | 2 | 6 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/count_r_reg[0]_0[0] | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 6 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/m_sc_req[0] | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_si_handler/m_sc_areset_r | 2 | 6 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/m_sc_req[0] | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_si_handler/m_sc_areset_r | 1 | 6 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/m_sc_req[0] | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 6 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s01_nodes/s01_r_node/inst/inst_si_handler/inst_arb_stall_late/count_r | mz_petalinux_i/axi_smc/inst/s01_nodes/s01_r_node/inst/inst_mi_handler/areset_r | 2 | 6 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg_0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/p_5_out | 2 | 6 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_si_handler/inst_arb_stall_late/count_r | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/areset_r | 3 | 6 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/count_r_reg[0]_0[0] | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 6 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_b_node/inst/inst_si_handler/inst_arb_stall_late/s_sc_valid | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_b_node/inst/inst_mi_handler/areset_r | 2 | 6 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/m_sc_req[0] | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 6 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/E[0] | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 6 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/ar_sreg/E[0] | mz_petalinux_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/areset | 2 | 6 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/m_sc_req[0] | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 6 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/E[0] | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 6 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/E[0] | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 6 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/gen_normal_area.fifo_node_payld_pop_early | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 6 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_STATUS_CNTLR/GEN_OMIT_INDET_BTT.I_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/GEN_OMIT_INDET_BTT.sig_coelsc_reg_full_reg_0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/p_5_out | 1 | 6 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/count_r_reg[0]_0[0] | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 6 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/m_sc_req[0] | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_si_handler/m_sc_areset_r | 2 | 6 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/m_sc_req[0] | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 6 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/m_sc_req[0] | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 6 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/m_sc_req[0] | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 6 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/E[0] | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_INDET_BTT.lsig_byte_cntr[13]_i_1_n_0 | 2 | 6 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/ar_sreg/E[0] | mz_petalinux_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/areset | 2 | 6 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_axis_packet_slave_normal_area.inst_allow_transfer_late/E[0] | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/areset_r | 3 | 6 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s01_nodes/s01_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/E[0] | mz_petalinux_i/axi_smc/inst/s01_nodes/s01_ar_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 6 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/aw_sreg/gen_endpoint.w_cnt_reg[0][0] | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/areset | 2 | 6 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/aw_sreg/gen_endpoint.w_cnt_reg[0][0] | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/areset | 3 | 6 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/clk_map/psr_aclk/U0/SEQ/seq_cnt_en | mz_petalinux_i/axi_smc/inst/clk_map/psr_aclk/U0/SEQ/SEQ_COUNTER/clear | 1 | 6 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_b_node/inst/inst_si_handler/inst_arb_stall_late/s_sc_valid | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_b_node/inst/inst_mi_handler/areset_r | 2 | 6 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/aw_sreg/E[0] | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/areset | 3 | 6 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s01_nodes/s01_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/m_sc_req[0] | mz_petalinux_i/axi_smc/inst/s01_nodes/s01_ar_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 6 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/ar_sreg/E[0] | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/areset | 2 | 6 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/ar_sreg/E[0] | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/areset | 3 | 6 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s01_nodes/s01_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/E[0] | mz_petalinux_i/axi_smc/inst/s01_nodes/s01_ar_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 6 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_axis_packet_slave_normal_area.inst_allow_transfer_late/E[0] | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/areset_r | 2 | 6 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_send/E[0] | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/m_sc_areset_r | 2 | 6 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/b_reg/exit_bready | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/areset | 3 | 7 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_data_reg_out_en | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 3 | 7 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_burst_dbeat_cntr_reg[3] | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/SR[0] | 3 | 7 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_entry_pipeline/s02_si_converter/inst/splitter_inst/gen_no_wsplitter.gen_endpoint_woffset.gen_wbypass_offset_fifo.wbypass_offset_fifo/gen_srls[13].srl_nx1/shift | | 2 | 7 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_data_reg_out_en | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 3 | 7 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/b_reg/exit_bready | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/areset | 3 | 7 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 8 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/mhandshake_r | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/SR[0] | 3 | 8 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_wr_fifo | | 1 | 8 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/sig_valid_fifo_ld12_out | | 2 | 8 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 8 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/E[0] | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 3 | 8 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 8 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 8 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 8 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/r_sreg/S00_AXI_rvalid | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/counter0 | 2 | 8 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 8 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/gen_endpoint.decerr_slave_inst/gen_axi.gen_read.read_cnt[7]_i_1_n_0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/areset | 3 | 8 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 8 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 8 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/E[0] | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 2 | 8 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 8 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/gen_endpoint.decerr_slave_inst/gen_axi.gen_read.read_cnt[7]_i_1_n_0 | mz_petalinux_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/areset | 4 | 8 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/r_sreg/S00_AXI_rvalid | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/counter0 | 2 | 8 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_INTERRUPT_LOGIC.I_AXI_SG_INTRPT/GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_reg_n_0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_INTERRUPT_LOGIC.I_AXI_SG_INTRPT/GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_1_n_0 | 3 | 8 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 8 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/sig_valid_fifo_ld12_out | | 3 | 8 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/gen_endpoint.decerr_slave_inst/gen_axi.gen_read.read_cnt[7]_i_1_n_0 | mz_petalinux_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/areset | 3 | 8 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 8 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 1 | 8 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_wr_fifo | | 1 | 8 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/mhandshake_r | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/SR[0] | 3 | 8 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_DATA_CNTL/sig_dbeat_cntr[7]_i_1__0_n_0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RESET/mm2s_rlast_del_reg | 3 | 8 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/E[0] | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_INDET_BTT.lsig_byte_cntr[7]_i_1_n_0 | 2 | 8 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/p_2_out[0] | mz_petalinux_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_WRITE.REG_WADDR_TO_IPCLK1/SR[0] | 2 | 8 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_S2MM_REGISTERS.I_S2MM_DMA_REGISTER/GEN_INCLUDE_S2MM.ch2_thresh_count_reg[0][0] | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 5 | 8 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_WR_DATA_CNTL/sig_dbeat_cntr[7]_i_1__0_n_0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RESET/mm2s_rlast_del_reg | 3 | 8 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_INTERRUPT_LOGIC.I_AXI_SG_INTRPT/GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.GEN_CH2_FAST_COUNTER.ch2_dly_fast_incr_reg_n_0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_INTERRUPT_LOGIC.I_AXI_SG_INTRPT/GEN_INCLUDE_S2MM.GEN_CH2_DELAY_INTERRUPT.ch2_delay_count[7]_i_1_n_0 | 5 | 8 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_S2MM_REGISTERS.I_S2MM_DMA_REGISTER/GEN_INCLUDE_S2MM.ch2_thresh_count_reg[0][0] | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 4 | 8 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/w_reg/s_axi_wready | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/areset | 3 | 9 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/rdp_inst/ram_rd_en_pf | | 2 | 9 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/rdp_inst/ram_rd_en_pf | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/count_value_i_reg[1] | 2 | 9 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_dqual_reg_empty_reg | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_next_calc_error_reg_reg | 2 | 9 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/rdp_inst/ram_rd_en_pf | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/count_value_i_reg[1] | 3 | 9 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/ram_wr_en_pf | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/count_value_i_reg[1] | 2 | 9 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_fwft.ram_regout_en | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/count_value_i_reg[1] | 2 | 9 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_S2MM_REGISTERS.I_S2MM_DMA_REGISTER/SR[0] | 2 | 9 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/ps7_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/SR[0] | 5 | 10 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/s02_entry_pipeline/s02_si_converter/inst/areset | 5 | 10 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_S2MM_REGISTERS.I_S2MM_DMA_REGISTER/SR[0] | 3 | 9 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_dqual_reg_empty_reg | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_next_calc_error_reg_reg | 2 | 9 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/areset | 5 | 10 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_READ.REG_ARVALID_TO_IPCLK/E[0] | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_ASYNC_READ.rvalid_reg | 3 | 10 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/inst_si_handler/m_sc_areset_r | 3 | 10 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/s02_entry_pipeline/s02_si_converter/inst/areset | 4 | 10 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/count_value_i_reg[1] | 4 | 10 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_READ.REG_ARVALID_TO_IPCLK/E[0] | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_ASYNC_READ.rvalid_reg | 3 | 10 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_DATA_CNTL/GEN_DATA_CNTL_FIFO.I_DATA_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_next_calc_error_reg_reg | | 2 | 10 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/exit_inst/gen_r_cmd_fifo.r_cmd_fifo/gen_pipelined.mesg_reg | | 5 | 11 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/inst_si_handler/m_sc_areset_r | 4 | 10 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/ps7_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/SR[0] | 4 | 10 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_si_handler/m_sc_areset_r | 5 | 11 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/exit_inst/gen_r_cmd_fifo.r_cmd_fifo/gen_pipelined.mesg_reg | | 5 | 11 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/exit_inst/gen_r_cmd_fifo.r_cmd_fifo/gen_srls[16].srl_nx1/shift_qual | | 3 | 11 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_b_node/inst/inst_mi_handler/inst_ingress/inst_pipeline_valid/ingress_valid | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_b_node/inst/inst_mi_handler/areset_r | 4 | 12 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/count_r_reg[0]_0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_b_node/inst/inst_mi_handler/m_sc_areset_r | 6 | 12 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/count_r_reg[0]_0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_b_node/inst/inst_mi_handler/m_sc_areset_r | 4 | 12 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/E[0] | | 6 | 12 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/inst_ingress/inst_pipeline_valid/ingress_valid | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/areset_r | 4 | 12 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s01_nodes/s01_r_node/inst/inst_mi_handler/inst_ingress/inst_pipeline_valid/ingress_valid | mz_petalinux_i/axi_smc/inst/s01_nodes/s01_r_node/inst/inst_mi_handler/areset_r | 3 | 12 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/inst_ingress/inst_pipeline_valid/ingress_valid | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/areset_r | 3 | 12 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/E[0] | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/inst_si_handler/m_sc_areset_r | 6 | 12 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/cmd_translator_0/incr_cmd_0/axaddr_incr[11]_i_1_n_0 | | 2 | 12 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/E[0] | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/inst_si_handler/m_sc_areset_r | 4 | 12 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/inst_ingress/inst_pipeline_valid/ingress_valid | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/areset_r | 3 | 12 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/wrap_boundary_axaddr_r_reg[0][0] | | 4 | 12 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/E[0] | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_si_handler/m_sc_areset_r | 4 | 12 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_b_node/inst/inst_mi_handler/inst_ingress/inst_pipeline_valid/ingress_valid | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_b_node/inst/inst_mi_handler/areset_r | 3 | 12 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/E[0] | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_si_handler/m_sc_areset_r | 3 | 12 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/inst_ingress/inst_pipeline_valid/ingress_valid | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/areset_r | 4 | 12 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/count_r_reg[0]_0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/m_sc_areset_r | 3 | 12 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/inst_ingress/inst_pipeline_valid/ingress_valid | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/areset_r | 3 | 12 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/wrap_boundary_axaddr_r_reg[0][0] | | 6 | 12 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s01_nodes/s01_r_node/inst/inst_mi_handler/inst_ingress/inst_pipeline_valid/ingress_valid | mz_petalinux_i/axi_smc/inst/s01_nodes/s01_r_node/inst/inst_mi_handler/areset_r | 3 | 12 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/E[0] | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_si_handler/m_sc_areset_r | 4 | 12 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s01_nodes/s01_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/count_r_reg[0]_0 | mz_petalinux_i/axi_smc/inst/s01_nodes/s01_r_node/inst/inst_mi_handler/m_sc_areset_r | 5 | 12 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/inst_ingress/inst_pipeline_valid/ingress_valid | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/areset_r | 3 | 12 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/cmd_translator_0/incr_cmd_0/axaddr_incr[11]_i_1_n_0 | | 2 | 12 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_b_node/inst/inst_mi_handler/inst_ingress/inst_pipeline_valid/ingress_valid | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_b_node/inst/inst_mi_handler/areset_r | 4 | 12 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s01_nodes/s01_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/count_r_reg[0]_0 | mz_petalinux_i/axi_smc/inst/s01_nodes/s01_r_node/inst/inst_mi_handler/m_sc_areset_r | 4 | 12 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/count_r_reg[0]_0 | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_b_node/inst/inst_mi_handler/m_sc_areset_r | 5 | 12 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_b_node/inst/inst_mi_handler/inst_ingress/inst_pipeline_valid/ingress_valid | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_b_node/inst/inst_mi_handler/areset_r | 5 | 12 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/E[0] | | 6 | 12 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/axaddr_incr_reg[0][0] | | 3 | 12 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/r_push_r | | 4 | 13 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/SS[0] | 4 | 13 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_rd_addrb/count_r_reg[0]_0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/m_sc_areset_r | 4 | 12 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/axaddr_incr_reg[0][0] | | 2 | 12 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/p_2_out[0] | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 4 | 13 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/counter_reg_n_0_[6] | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 2 | 14 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/b.b_pipe/p_1_in | | 3 | 14 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/r_push_r | | 4 | 13 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/SS[0] | 6 | 13 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/areset | 7 | 14 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/rdp_inst/count_value_i_reg[0]_0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/count_value_i_reg[1] | 5 | 14 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/count_value_i_reg[0] | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/count_value_i_reg[1] | 4 | 14 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/b.b_pipe/p_1_in | | 3 | 14 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/b.b_pipe/skid_buffer_reg[0]_0 | | 3 | 14 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/rdp_inst/count_value_i_reg[0]_0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/count_value_i_reg[1] | 5 | 14 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/s01_entry_pipeline/s01_mmu/inst/areset | 7 | 14 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_btt_cntr[13]_i_1_n_0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_reset_reg | 5 | 14 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_child_addr_cntr_lsh[0]_i_1_n_0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_reset_reg | 4 | 16 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_btt_cntr[13]_i_1_n_0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_reset_reg | 4 | 14 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/counter_reg_n_0_[6] | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 2 | 14 | +| mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_dco | mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_2_20[11]_i_1_n_0 | | 2 | 16 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_wr_fifo | | 3 | 16 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s01_nodes/s01_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 2 | 16 | | mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_dco | mz_petalinux_i/LTC2271_SampleGetter_0/inst/fr_up | | 3 | 16 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_MNGR/I_UPDT_SG/s2mm_all_idle | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.sft_rst_dly1_i_1_n_0 | 3 | 16 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/p_0_in | 3 | 16 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_child_addr_cntr_lsh[0]_i_1_n_0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_reset_reg | 4 | 16 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_child_addr_cntr_msh[0]_i_1_n_0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_reset_reg | 4 | 16 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/I_DRE_CNTL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_wr_fifo | | 3 | 16 | -| mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_dco | mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_2_20[11]_i_1_n_0 | | 3 | 16 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/b_push | | 3 | 16 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_MNGR/I_UPDT_SG/s2mm_all_idle | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/GEN_ASYNC_RESET.GEN_PRMRY_GRTR_EQL_SCNDRY.sft_rst_dly1_i_1_n_0 | 3 | 16 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_XD_FIFO/NON_BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/xpm_fifo_rst_inst/ram_wr_en_pf | | 2 | 16 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/p_0_in | 4 | 16 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_S2MM_SG_IF/GEN_DESC_UPDT_QUEUE.GEN_DESC_UPDT_NO_STSAPP.updt_desc_sts[30]_i_1_n_0 | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 3 | 17 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/GEN_ENABLE_INDET_BTT.sig_coelsc_eop_reg | | 3 | 17 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_psm_ld_realigner_reg | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_realign_tag_reg0 | 6 | 18 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_S2MM_SG_IF/GEN_DESC_UPDT_QUEUE.GEN_DESC_UPDT_NO_STSAPP.updt_desc_sts[30]_i_1_n_0 | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 3 | 17 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gc0.count_d1_reg[8][0] | | 4 | 18 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_psm_ld_realigner_reg | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_realign_tag_reg0 | 5 | 18 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_si_handler/m_sc_areset_r | 6 | 18 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/GEN_INCLUDE_STATUS_FIFO.I_STS_FIFO/sig_push_regfifo | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 3 | 18 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/gc0.count_d1_reg[8][0] | | 3 | 18 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_si_handler/m_sc_areset_r | 7 | 18 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/sts2_rden | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 4 | 20 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_S2MM_SG_IF/GEN_Q_FOR_SYNC.S2MM_CHANNEL.NO_APP_UPDATE.sts2_queue_dout_reg[0]_0[0] | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 4 | 20 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_S2MM_SG_IF/GEN_Q_FOR_SYNC.S2MM_CHANNEL.NO_APP_UPDATE.sts2_queue_dout_reg[0]_0[0] | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 3 | 20 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.I_SF_DATA_CNTL_STATUS_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/GEN_ENABLE_INDET_BTT.sig_coelsc_reg_full_reg | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_WR_STATUS_CNTLR/GEN_ENABLE_INDET_BTT.sig_coelsc_interr_reg_i_1_n_0 | 4 | 20 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/axlen_cnt_reg[4][0] | | 11 | 21 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/sts2_rden | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 6 | 20 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/axlen_cnt_reg[4][0] | | 8 | 21 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/E[0] | | 10 | 21 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/areset | 8 | 21 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/E[0] | | 9 | 21 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/inst_si_handler/inst_arb_stall_late/inst_mi_handler/ingress_valid | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/areset_r | 8 | 24 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum[bytes][4][userdata][7]_i_1_n_0 | | 5 | 24 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/E[0] | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/areset_r | 8 | 24 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_si_handler/inst_arb_stall_late/inst_mi_handler/ingress_valid | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/areset_r | 9 | 24 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/E[0] | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/areset_r | 10 | 24 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s01_nodes/s01_ar_node/inst/inst_si_handler/inst_arb_stall_late/inst_mi_handler/ingress_valid | mz_petalinux_i/axi_smc/inst/s01_nodes/s01_ar_node/inst/inst_mi_handler/areset_r | 7 | 24 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_si_handler/inst_arb_stall_late/inst_mi_handler/ingress_valid | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/areset_r | 7 | 24 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/E[0] | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/areset_r | 7 | 24 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/inst_si_handler/inst_arb_stall_late/inst_mi_handler/ingress_valid | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/areset_r | 9 | 24 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_aw_node/inst/inst_si_handler/inst_arb_stall_late/inst_mi_handler/ingress_valid | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_aw_node/inst/inst_mi_handler/areset_r | 8 | 24 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s01_nodes/s01_ar_node/inst/inst_si_handler/inst_arb_stall_late/inst_mi_handler/ingress_valid | mz_petalinux_i/axi_smc/inst/s01_nodes/s01_ar_node/inst/inst_mi_handler/areset_r | 9 | 24 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/E[0] | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/areset_r | 9 | 24 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_si_handler/inst_arb_stall_late/inst_mi_handler/ingress_valid | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/areset_r | 9 | 24 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum[bytes][4][userdata][7]_i_1_n_0 | | 5 | 24 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_si_handler/inst_arb_stall_late/inst_mi_handler/ingress_valid | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/areset_r | 9 | 24 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/w_sreg/m_vector_i | | 9 | 25 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_si_handler/inst_arb_stall_late/inst_mi_handler/ingress_valid | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/areset_r | 9 | 24 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/w_sreg/m_vector_i | | 8 | 25 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/w_sreg/skid_buffer[2052]_i_1_n_0 | | 4 | 25 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_S2MM_SG_IF/E[0] | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 4 | 26 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_SG/ftch_error_addr_reg[6]_0[0] | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 4 | 26 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_SG/E[0] | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 4 | 26 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_PNTR_MNGR/GEN_PNTR_FOR_CH2.ch2_fetch_address_i[31]_i_1_n_0 | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 7 | 26 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/p_2_out[3] | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 8 | 26 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/updt_curdesc0 | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 4 | 26 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/p_0_in1_in | mz_petalinux_i/ps7_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/SR[0] | 10 | 26 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/p_2_out[3] | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 5 | 26 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/updt_curdesc0 | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 5 | 26 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/lsbnxtdesc_tready | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 4 | 26 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_MNGR/I_UPDT_SG/ftch_error_addr_reg[31]_2[0] | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 7 | 26 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_MNGR/I_UPDT_SG/updt_cmnd_wr | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 4 | 26 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_S2MM_SG_IF/E[0] | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 5 | 26 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_SG/ftch_error_addr_reg[6]_0[0] | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 4 | 26 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/lsbnxtdesc_tready | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 5 | 26 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/p_8_out | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 5 | 26 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_S2MM_REGISTERS.I_S2MM_DMA_REGISTER/curdesc_lsb_i | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 9 | 27 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_MNGR/I_UPDT_SG/updt_cmnd_wr | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 4 | 26 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_MNGR/I_UPDT_SG/ftch_error_addr_reg[31]_2[0] | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 7 | 26 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_PNTR_MNGR/GEN_PNTR_FOR_CH2.ch2_fetch_address_i[31]_i_1_n_0 | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 7 | 26 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_SG/E[0] | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 4 | 26 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/update_address_reg[4][0] | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 5 | 27 | +| mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_dco | mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0] | | 5 | 27 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_MNGR/I_FTCH_CMDSTS_IF/USE_SINGLE_REG.sig_regfifo_dout_reg_reg[23][0] | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RESET/mm2s_rlast_del_reg | 5 | 27 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_QUEUE/GEN_QUEUE.I_UPDT_DESC_QUEUE/update_address_reg[4][0] | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 6 | 27 | -| mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_dco | mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwas.wsts/E[0] | | 6 | 27 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_S2MM_REGISTERS.I_S2MM_DMA_REGISTER/curdesc_lsb_i | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 7 | 27 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/E[0] | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_btt_cntr_reg[13] | 8 | 28 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_MNGR/I_UPDT_CMDSTS_IF/E[0] | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RESET/mm2s_rlast_del_reg | 4 | 28 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/E[0] | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/areset | 9 | 30 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/GEN_DESC_UPDATE.I_SG_UPDATE_MNGR/I_UPDT_CMDSTS_IF/E[0] | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RESET/mm2s_rlast_del_reg | 7 | 28 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/E[0] | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/areset | 9 | 30 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_MSTR_SCC/sig_load_input_cmd | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RESET/sig_cmd_addr_reg_reg[6] | 4 | 30 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/ar_reg_stall/skid_buffer[1144]_i_1_n_0 | | 7 | 31 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/ar_reg_stall/m_vector_i | | 9 | 31 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/aw_reg_stall/m_vector_i | | 8 | 31 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/aw_reg_stall/skid_buffer[1144]_i_1__0_n_0 | | 4 | 31 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_ADDR_CNTL/sig_push_addr_reg1_out | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_ADDR_CNTL/sig_next_addr_reg0 | 7 | 31 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/E[0] | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/areset | 9 | 30 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_MSTR_SCC/sig_load_input_cmd | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RESET/sig_cmd_addr_reg_reg[6] | 5 | 30 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/aw_reg_stall/skid_buffer[1144]_i_1__0_n_0 | | 5 | 31 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_reset_reg | 11 | 31 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/ar_reg_stall/m_vector_i | | 10 | 31 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/ar_reg_stall/skid_buffer[1144]_i_1_n_0 | | 7 | 31 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_MSTR_SCC/sig_load_input_cmd | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_ADDR_CNTL/SR[0] | 4 | 31 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/aw_reg_stall/m_vector_i | | 8 | 31 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_ADDR_CNTL/sig_push_addr_reg1_out | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_ADDR_CNTL/sig_next_addr_reg0 | 6 | 31 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/arready_d12 | mz_petalinux_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 | 8 | 32 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/rvalid | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_ASYNC_READ.rvalid_reg | 12 | 32 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/p_1_in | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 4 | 32 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_data_reg_out_en | | 9 | 32 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RESET/mm2s_rlast_del_reg | 13 | 32 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/ar_sreg/skid_buffer[1144]_i_1__1_n_0 | | 6 | 32 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/ar_sreg/m_vector_i | | 9 | 32 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/p_1_in | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 5 | 32 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_s_ready_dup | | 4 | 32 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_MSTR_SCC/sig_push_addr_reg1_out | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_ADDR_CNTL/sig_next_addr_reg0 | 5 | 32 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/gr1.gr1_int.rfwft/E[0] | | 6 | 32 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_S2MM_MMAP_SKID_BUF/sig_s_ready_dup | | 7 | 32 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_MM2S_BASIC.I_MM2S_BASIC_WRAPPER/I_RESET/mm2s_rlast_del_reg | 10 | 32 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_data_reg_out_en | | 9 | 32 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/aw_sreg/skid_buffer[1144]_i_1__2_n_0 | | 5 | 32 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/ar_sreg/skid_buffer[1144]_i_1__1_n_0 | | 6 | 32 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_MSTR_SCC/sig_push_addr_reg1_out | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_ADDR_CNTL/sig_next_addr_reg0 | 6 | 32 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/ar_sreg/m_vector_i | | 10 | 32 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/aw_sreg/skid_buffer[1144]_i_1__2_n_0 | | 4 | 32 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/aw_sreg/m_vector_i | | 9 | 32 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/rvalid | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_ASYNC_READ.rvalid_reg | 10 | 32 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/arready_d12 | mz_petalinux_i/axi_dma_0/U0/I_AXI_DMA_REG_MODULE/GEN_AXI_LITE_IF.AXI_LITE_IF_I/GEN_ASYNC_READ.s_axi_lite_rdata[31]_i_1_n_0 | 10 | 32 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_s_ready_dup | | 6 | 32 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/wr_en0 | | 9 | 34 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_calc_error_reg0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_input_cache_type_reg0 | 8 | 34 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/r_sreg/skid_buffer[1090]_i_2_n_0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/r_sreg/skid_buffer[1090]_i_1_n_0 | 6 | 34 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/r_sreg/skid_buffer[1090]_i_2_n_0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/r_sreg/skid_buffer[1090]_i_1_n_0 | 5 | 34 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_calc_error_reg0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_input_cache_type_reg0 | 7 | 34 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/areset | 16 | 35 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/E[0] | | 11 | 35 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/r_sreg/m_vector_i | | 10 | 35 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/areset | 17 | 35 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_psm_ld_chcmd_reg | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_child_tag_reg0 | 8 | 36 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum[bytes][0][userdata][7]_i_1_n_0 | | 7 | 36 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_psm_ld_chcmd_reg | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_child_tag_reg0 | 7 | 36 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum[bytes][0][userdata][7]_i_1_n_0 | | 9 | 36 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum[bytes][0][userdata][7]_i_1_n_0 | | 7 | 36 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum[bytes][4][userdata][7]_i_1_n_0 | | 6 | 36 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/w_sreg/skid_buffer[2052]_i_1_n_0 | | 6 | 37 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/E[0] | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/sig_data_reg_out0 | 12 | 37 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/w_sreg/m_vector_i | | 10 | 37 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/E[0] | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/sig_data_reg_out0 | 13 | 37 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/w_sreg/skid_buffer[2052]_i_1_n_0 | | 5 | 37 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/ENABLE_AXIS_SKID.I_S2MM_STRM_SKID_BUF/sig_s_ready_dup | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 7 | 37 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_calc_error_reg_reg | | 6 | 39 | -| mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_dco | | | 10 | 39 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/aw_reg_stall/m_vector_i | | 13 | 39 | +| mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_dco | | | 11 | 39 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/aw_reg_stall/skid_buffer[1144]_i_1_n_0 | | 7 | 39 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/aw_sreg/m_vector_i | | 12 | 40 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/aw_reg_stall/m_vector_i | | 14 | 39 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_calc_error_reg_reg | | 6 | 39 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/aw_sreg/skid_buffer[1144]_i_1__0_n_0 | | 6 | 40 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/sig_s_ready_dup | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 7 | 41 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_csm_ld_xfer | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_cache_reg0 | 9 | 41 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/sig_data_reg_out_en | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 13 | 41 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_push_addr_reg1_out | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/sig_next_addr_reg[31]_i_1__1_n_0 | 8 | 42 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/ar_reg/skid_buffer_reg[1144]_0 | | 11 | 43 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/aw_reg/m_vector_i | | 14 | 47 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/aw_reg/skid_buffer[1144]_i_1__0_n_0 | | 10 | 47 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/p_1_in | | 7 | 47 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/skid_buffer_reg[0]_0 | | 10 | 47 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_push_regfifo | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 11 | 47 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/ar_reg/m_vector_i | | 15 | 47 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/s_axi_awready | | 13 | 48 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/s_axi_arready | | 13 | 48 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/m_payload_i_reg[0]_1[0] | | 9 | 48 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_entry_pipeline/s02_mmu/inst/aw_sreg/m_vector_i | | 11 | 40 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/sig_s_ready_dup | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 6 | 41 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/ENABLE_AXIS_SKID.I_INDET_BTT_SKID_BUF/sig_data_reg_out_en | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 11 | 41 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_csm_ld_xfer | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_cache_reg0 | 8 | 41 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/GEN_ADDR_FIFO.I_ADDR_QUAL_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/CNTR_INCR_DECR_ADDN_F_I/sig_push_addr_reg1_out | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_ADDR_CNTL/sig_next_addr_reg[31]_i_1__1_n_0 | 7 | 42 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/ar_reg/skid_buffer_reg[1144]_0 | | 9 | 43 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/sig_push_regfifo | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 14 | 47 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/aw_reg/m_vector_i | | 13 | 47 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/ar_reg/m_vector_i | | 16 | 47 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/skid_buffer_reg[0]_0 | | 8 | 47 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/aw_reg/skid_buffer[1144]_i_1__0_n_0 | | 8 | 47 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/r.r_pipe/p_1_in | | 8 | 47 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/WR.aw_channel_0/aw_cmd_fsm_0/m_payload_i_reg[0][0] | | 9 | 48 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/areset_d1 | 16 | 59 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/S_AXI_ALEN_Q_reg[0]_0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/areset | 13 | 60 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 25 | 63 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/ar.ar_pipe/s_axi_arready | | 12 | 48 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/s_axi_awready | | 10 | 48 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/RD.ar_channel_0/ar_cmd_fsm_0/m_payload_i_reg[0]_1[0] | | 12 | 48 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/areset_d1 | 18 | 59 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/S_AXI_ALEN_Q_reg[0]_0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/areset | 14 | 60 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_RESET/sig_stream_rst | 23 | 63 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/S_AXI_ALEN_Q_reg[0]_0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/areset | 13 | 66 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/r_reg/m_vector_i | | 21 | 67 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/r_reg/skid_buffer[1122]_i_1_n_0 | | 15 | 67 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/areset | 27 | 67 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/w_reg/m_vector_i | | 24 | 73 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/w_reg/skid_buffer[2056]_i_1_n_0 | | 16 | 73 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/queue_wren2_new | mz_petalinux_i/axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/queue_sinit2 | 11 | 73 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/r_reg/m_vector_i | | 20 | 67 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/r_reg/skid_buffer[1122]_i_1_n_0 | | 11 | 67 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/areset | 26 | 67 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/GEN_S2MM_DMA_CONTROL.GEN_SCATTER_GATHER_MODE.I_S2MM_SM/queue_rden2_new | mz_petalinux_i/axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/queue_sinit2 | 12 | 73 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/queue_wren2_new | mz_petalinux_i/axi_dma_0/U0/INCLUDE_S2MM_SOF_EOF_GENERATOR.I_S2MM_DMA_MNGR/queue_sinit2 | 11 | 73 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/w_reg/m_vector_i | | 23 | 73 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/w_reg/skid_buffer[2056]_i_1_n_0 | | 14 | 73 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 11 | 88 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 11 | 88 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 11 | 88 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 29 | 88 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s01_nodes/s01_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 12 | 96 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 12 | 96 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | mz_petalinux_i/axi_dma_0/U0/I_RST_MODULE/GEN_RESET_FOR_S2MM.RESET_I/sinit | 26 | 88 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 12 | 96 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 13 | 104 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 13 | 104 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 12 | 96 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s01_nodes/s01_ar_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 12 | 96 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 13 | 104 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 13 | 104 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 13 | 104 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 13 | 104 | | mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/wr_wea | | 14 | 112 | -| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | | 299 | 1041 | +| mz_petalinux_i/processing_system7_0/inst/FCLK_CLK0 | | | 303 | 1041 | +-----------------------------------------------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------+----------------+ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_drc_opted.rpt b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_drc_opted.rpt index ce65e614548aba6fe80abf727f1bc895bb7e68a2..83a3d7448b4b8fbfcd2c31cfd1a9789f433e447a 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_drc_opted.rpt +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_drc_opted.rpt @@ -1,7 +1,7 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 -| Date : Sat Oct 19 01:13:49 2019 +| Date : Sun Oct 20 22:45:56 2019 | Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS | Command : report_drc -file mz_petalinux_wrapper_drc_opted.rpt -pb mz_petalinux_wrapper_drc_opted.pb -rpx mz_petalinux_wrapper_drc_opted.rpx | Design : mz_petalinux_wrapper diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_drc_routed.rpt b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_drc_routed.rpt index 0e52b3bf3cc58416ee8f086e1d42e517dd30735f..486af417af33e5cba87297b391642e6a39f459fd 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_drc_routed.rpt +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_drc_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------------ | Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 -| Date : Sat Oct 19 01:14:31 2019 +| Date : Sun Oct 20 22:46:41 2019 | Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS | Command : report_drc -file mz_petalinux_wrapper_drc_routed.rpt -pb mz_petalinux_wrapper_drc_routed.pb -rpx mz_petalinux_wrapper_drc_routed.rpx | Design : mz_petalinux_wrapper diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_io_placed.rpt b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_io_placed.rpt index f1f06277d0424a19999f8b9fa903c39cea90f87b..146428aa989d7417918dc6be4d6673f98baa2c86 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_io_placed.rpt +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_io_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 -| Date : Sat Oct 19 01:14:11 2019 +| Date : Sun Oct 20 22:46:15 2019 | Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS | Command : report_io -file mz_petalinux_wrapper_io_placed.rpt | Design : mz_petalinux_wrapper diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_methodology_drc_routed.rpt b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_methodology_drc_routed.rpt index 58c5bb3d3c23728854b0e3f626d04316a19599e9..1823aa43ea4105f885f2dd6b533321aed17c7025 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_methodology_drc_routed.rpt +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_methodology_drc_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 -| Date : Sat Oct 19 01:14:34 2019 +| Date : Sun Oct 20 22:46:44 2019 | Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS | Command : report_methodology -file mz_petalinux_wrapper_methodology_drc_routed.rpt -pb mz_petalinux_wrapper_methodology_drc_routed.pb -rpx mz_petalinux_wrapper_methodology_drc_routed.rpx | Design : mz_petalinux_wrapper diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_opt.dcp b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_opt.dcp index 99f581207c953b18d61c5bae0ae0e33f321a62be..bdb84d796497024a63605927cf3fadd6b261a3da 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_opt.dcp and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_opt.dcp differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_placed.dcp b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_placed.dcp index b95fa7ebece8fe0caf2bf1e9c036f535a09c0099..000e5cd1dac1e4aa137c9b9e52974ed5e6c10875 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_placed.dcp and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_placed.dcp differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_power_routed.rpt b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_power_routed.rpt index 4f8b92ec6243d84fd91a866c6cdeec73f894bbbe..f6e770f7f571a0adea127f9cbd34acb90c3de619 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_power_routed.rpt +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_power_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 -| Date : Sat Oct 19 01:14:36 2019 +| Date : Sun Oct 20 22:46:46 2019 | Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS | Command : report_power -file mz_petalinux_wrapper_power_routed.rpt -pb mz_petalinux_wrapper_power_summary_routed.pb -rpx mz_petalinux_wrapper_power_routed.rpx | Design : mz_petalinux_wrapper @@ -33,7 +33,7 @@ Table of Contents | Total On-Chip Power (W) | 1.767 | | Design Power Budget (W) | Unspecified* | | Power Budget Margin (W) | NA | -| Dynamic (W) | 1.643 | +| Dynamic (W) | 1.642 | | Device Static (W) | 0.124 | | Effective TJA (C/W) | 11.5 | | Max Ambient (C) | 64.6 | @@ -54,14 +54,14 @@ Table of Contents +--------------------------+-----------+----------+-----------+-----------------+ | Clocks | 0.022 | 3 | --- | --- | | Slice Logic | 0.009 | 13038 | --- | --- | -| LUT as Logic | 0.007 | 4114 | 17600 | 23.38 | +| LUT as Logic | 0.007 | 4116 | 17600 | 23.39 | | LUT as Distributed RAM | 0.001 | 588 | 6000 | 9.80 | | Register | <0.001 | 6018 | 35200 | 17.10 | | CARRY4 | <0.001 | 73 | 4400 | 1.66 | | LUT as Shift Register | <0.001 | 159 | 6000 | 2.65 | | F7/F8 Muxes | <0.001 | 1 | 17600 | <0.01 | | Others | 0.000 | 731 | --- | --- | -| Signals | 0.011 | 8912 | --- | --- | +| Signals | 0.011 | 8913 | --- | --- | | Block RAM | <0.001 | 1.5 | 60 | 2.50 | | I/O | 0.066 | 27 | 100 | 27.00 | | PS7 | 1.534 | 1 | --- | --- | @@ -152,7 +152,7 @@ Table of Contents +---------------------------------------------------------------------------------------------------+-----------+ | Name | Power (W) | +---------------------------------------------------------------------------------------------------+-----------+ -| mz_petalinux_wrapper | 1.643 | +| mz_petalinux_wrapper | 1.642 | | IIC_0_scl_iobuf | <0.001 | | IIC_0_sda_iobuf | <0.001 | | mz_petalinux_i | 1.640 | @@ -467,8 +467,8 @@ Table of Contents | gen_normal_area.inst_fifo_send | <0.001 | | inst_si_handler | <0.001 | | inst_arb_stall_late | <0.001 | -| m00_r_node | 0.001 | -| inst | 0.001 | +| m00_r_node | 0.002 | +| inst | 0.002 | | inst_mi_handler | 0.001 | | gen_normal_area.gen_fifo_req.inst_fifo_req | <0.001 | | gen_xpm_memory_fifo.inst_fifo | <0.001 | @@ -658,8 +658,8 @@ Table of Contents | gen_xpm_memory_fifo.inst_fifo | <0.001 | | gen_mem_rep[0].inst_rd_addrb | <0.001 | | gen_wr.inst_wr_addra_p1 | <0.001 | -| gen_normal_area.inst_fifo_node_payld | 0.002 | -| gen_xpm_memory_fifo.inst_fifo | 0.002 | +| gen_normal_area.inst_fifo_node_payld | 0.001 | +| gen_xpm_memory_fifo.inst_fifo | 0.001 | | gen_mem_rep[0].inst_rd_addrb | <0.001 | | gen_mem_rep[0].inst_wr_addra | <0.001 | | gen_mem_rep[0].inst_xpm_memory | <0.001 | diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_power_routed.rpx b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_power_routed.rpx index af76e6a92a26359dd785bde84a24e5a586444c84..41b895a65c1f22a74804425f975ed9695ba4a426 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_power_routed.rpx and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_power_routed.rpx differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_power_summary_routed.pb b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_power_summary_routed.pb index f57ce1d0a367f7786c801163f6517b5ae6a3badd..87235de2e5bd4e94f325f25f17e8ad17a52cd7b1 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_power_summary_routed.pb and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_power_summary_routed.pb differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_route_status.pb b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_route_status.pb index d5dd5bf9d9ace3677cea3e273730598b309e7754..f1cc1dfa0e37ccfa26da2fc5ff8d83534b087ddb 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_route_status.pb and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_route_status.pb differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_route_status.rpt b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_route_status.rpt index 0d29c51088627db38fa1c87ba362d121d3cdea12..16c82b02aa08885dbb87b611fd5824482b97fd6e 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_route_status.rpt +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_route_status.rpt @@ -2,11 +2,11 @@ Design Route Status : # nets : ------------------------------------------- : ----------- : # of logical nets.......................... : 26099 : - # of nets not needing routing.......... : 17043 : - # of internally routed nets........ : 16623 : + # of nets not needing routing.......... : 17042 : + # of internally routed nets........ : 16622 : # of nets with no loads............ : 420 : - # of routable nets..................... : 9056 : - # of fully routed nets............. : 9056 : + # of routable nets..................... : 9057 : + # of fully routed nets............. : 9057 : # of nets with routing errors.......... : 0 : ------------------------------------------- : ----------- : diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_routed.dcp b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_routed.dcp index 08bc43b6d4acad4cf6b5d82b4c0fedc05dcd5295..de1a0fde8dd6ec6a043120dc77b5817f33b6d390 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_routed.dcp and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_routed.dcp differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_timing_summary_routed.rpt b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_timing_summary_routed.rpt index 0c3202395a01cbf2394357eb8a2db61c4fe63ab6..eaf8506089c49dd79cc1ad2b9ce829a1cbc56bd7 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_timing_summary_routed.rpt +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_timing_summary_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 -| Date : Sat Oct 19 01:14:37 2019 +| Date : Sun Oct 20 22:46:47 2019 | Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS | Command : report_timing_summary -max_paths 10 -file mz_petalinux_wrapper_timing_summary_routed.rpt -rpx mz_petalinux_wrapper_timing_summary_routed.rpx -warn_on_violation | Design : mz_petalinux_wrapper @@ -126,7 +126,7 @@ Table of Contents WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- - 2.472 0.000 0 21431 0.023 0.000 0 21413 3.750 0.000 0 7299 + 3.253 0.000 0 21431 0.024 0.000 0 21413 3.750 0.000 0 7299 All user specified timing constraints are met. @@ -149,7 +149,7 @@ clk_fpga_0 {0.000 5.000} 10.000 100.000 Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints ----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- -------------------- -clk_fpga_0 2.472 0.000 0 21413 0.023 0.000 0 21413 3.750 0.000 0 7299 +clk_fpga_0 3.253 0.000 0 21413 0.024 0.000 0 21413 3.750 0.000 0 7299 ------------------------------------------------------------------------------------------------ @@ -159,7 +159,7 @@ clk_fpga_0 2.472 0.000 0 214 From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- - clk_fpga_0 998.311 0.000 0 9 + clk_fpga_0 998.635 0.000 0 9 ------------------------------------------------------------------------------------------------ @@ -169,7 +169,7 @@ From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints ---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -**default** clk_fpga_0 8.701 0.000 0 9 +**default** clk_fpga_0 8.364 0.000 0 9 ------------------------------------------------------------------------------------------------ @@ -182,26 +182,26 @@ Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing From Clock: clk_fpga_0 To Clock: clk_fpga_0 -Setup : 0 Failing Endpoints, Worst Slack 2.472ns, Total Violation 0.000ns -Hold : 0 Failing Endpoints, Worst Slack 0.023ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 3.253ns, Total Violation 0.000ns +Hold : 0 Failing Endpoints, Worst Slack 0.024ns, Total Violation 0.000ns PW : 0 Failing Endpoints, Worst Slack 3.750ns, Total Violation 0.000ns --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 2.472ns (required time - arrival time) +Slack (MET) : 3.253ns (required time - arrival time) Source: mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/gen_pipelined.mesg_reg_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) - Destination: mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.full_r_reg_inv/D + Destination: mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.afull_r_reg/D (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_fpga_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns) - Data Path Delay: 6.984ns (logic 1.387ns (19.859%) route 5.597ns (80.141%)) - Logic Levels: 6 (LUT2=2 LUT3=1 LUT5=1 LUT6=2) - Clock Path Skew: -0.157ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 2.688ns = ( 12.688 - 10.000 ) + Data Path Delay: 6.466ns (logic 1.538ns (23.787%) route 4.928ns (76.213%)) + Logic Levels: 6 (LUT2=2 LUT5=1 LUT6=3) + Clock Path Skew: -0.159ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.686ns = ( 12.686 - 10.000 ) Source Clock Delay (SCD): 2.975ns Clock Pessimism Removal (CPR): 0.130ns Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE @@ -218,23 +218,23 @@ Slack (MET) : 2.472ns (required time - arrival time) net (fo=1, routed) 1.207 1.207 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 1.308 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O net (fo=7300, routed) 1.667 2.975 mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/aclk - SLICE_X10Y21 FDRE r mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/gen_pipelined.mesg_reg_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X10Y21 FDRE (Prop_fdre_C_Q) 0.478 3.453 f mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/gen_pipelined.mesg_reg_reg[4]/Q - net (fo=4, routed) 0.847 4.300 mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.USE_SPLIT_W.write_resp_inst/Q[4] - SLICE_X10Y22 LUT6 (Prop_lut6_I0_O) 0.295 4.595 f mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.USE_SPLIT_W.write_resp_inst/s_axi_bvalid_INST_0_i_1/O - net (fo=3, routed) 0.633 5.228 mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/b_reg/gen_pipelined.mesg_reg_reg[4] - SLICE_X9Y19 LUT2 (Prop_lut2_I1_O) 0.124 5.352 r mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/b_reg/s_axi_bvalid_INST_0/O - net (fo=1, routed) 0.753 6.105 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_si_handler/inst_arb_stall_late/s_sc_send[0] - SLICE_X14Y22 LUT2 (Prop_lut2_I0_O) 0.124 6.229 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_si_handler/inst_arb_stall_late/count_r[5]_i_3__1/O - net (fo=45, routed) 1.589 7.818 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/p_0_in3_in - SLICE_X27Y38 LUT6 (Prop_lut6_I1_O) 0.124 7.942 f mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_rd.fifo_empty_r_i_6/O - net (fo=1, routed) 0.985 8.927 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_rd.fifo_empty_r_i_6_n_0 - SLICE_X27Y38 LUT5 (Prop_lut5_I2_O) 0.124 9.051 f mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_rd.fifo_empty_r_i_2/O - net (fo=2, routed) 0.451 9.502 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_rd.fifo_empty_r_i_2_n_0 - SLICE_X27Y38 LUT3 (Prop_lut3_I1_O) 0.118 9.620 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_wr.full_r_inv_i_1/O - net (fo=1, routed) 0.339 9.959 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1_n_0 - SLICE_X28Y38 FDRE r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.full_r_reg_inv/D + SLICE_X11Y21 FDRE r mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/gen_pipelined.mesg_reg_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y21 FDRE (Prop_fdre_C_Q) 0.419 3.394 r mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/gen_pipelined.mesg_reg_reg[4]/Q + net (fo=4, routed) 0.821 4.215 mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.USE_SPLIT_W.write_resp_inst/Q[4] + SLICE_X11Y23 LUT6 (Prop_lut6_I0_O) 0.299 4.514 r mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.USE_SPLIT_W.write_resp_inst/s_axi_bvalid_INST_0_i_1/O + net (fo=3, routed) 0.416 4.930 mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/b_reg/gen_pipelined.mesg_reg_reg[4] + SLICE_X11Y22 LUT2 (Prop_lut2_I1_O) 0.124 5.054 f mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/b_reg/s_axi_bvalid_INST_0/O + net (fo=1, routed) 0.311 5.364 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_si_handler/inst_arb_stall_late/s_sc_send[0] + SLICE_X12Y23 LUT2 (Prop_lut2_I0_O) 0.124 5.488 f mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_si_handler/inst_arb_stall_late/count_r[5]_i_3__1/O + net (fo=45, routed) 2.035 7.523 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/p_0_in3_in + SLICE_X30Y34 LUT5 (Prop_lut5_I0_O) 0.117 7.640 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_wr.afull_r_i_9/O + net (fo=1, routed) 0.568 8.208 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_wr.afull_r_i_9_n_0 + SLICE_X33Y34 LUT6 (Prop_lut6_I1_O) 0.331 8.539 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_wr.afull_r_i_4/O + net (fo=1, routed) 0.778 9.317 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_wr.afull_r_i_4_n_0 + SLICE_X33Y34 LUT6 (Prop_lut6_I2_O) 0.124 9.441 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_wr.afull_r_i_1/O + net (fo=1, routed) 0.000 9.441 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1_n_0 + SLICE_X33Y34 FDRE r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.afull_r_reg/D ------------------------------------------------------------------- ------------------- (clock clk_fpga_0 rise edge) @@ -242,31 +242,31 @@ Slack (MET) : 2.472ns (required time - arrival time) PS7_X0Y0 PS7 0.000 10.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 1.101 11.101 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 11.192 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 1.496 12.688 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/s_sc_aclk - SLICE_X28Y38 FDRE r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.full_r_reg_inv/C - clock pessimism 0.130 12.818 - clock uncertainty -0.154 12.664 - SLICE_X28Y38 FDRE (Setup_fdre_C_D) -0.233 12.431 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.full_r_reg_inv + net (fo=7300, routed) 1.494 12.686 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/s_sc_aclk + SLICE_X33Y34 FDRE r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.afull_r_reg/C + clock pessimism 0.130 12.816 + clock uncertainty -0.154 12.662 + SLICE_X33Y34 FDRE (Setup_fdre_C_D) 0.031 12.693 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.afull_r_reg ------------------------------------------------------------------- - required time 12.431 - arrival time -9.959 + required time 12.693 + arrival time -9.441 ------------------------------------------------------------------- - slack 2.472 + slack 3.253 -Slack (MET) : 3.068ns (required time - arrival time) - Source: mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/gen_pipelined.mesg_reg_reg[4]/C +Slack (MET) : 3.326ns (required time - arrival time) + Source: mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_dup_reg[1]/C + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_eq_0_reg/D (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) - Destination: mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_rd.fifo_empty_r_reg/D - (rising edge-triggered cell FDSE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_fpga_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns) - Data Path Delay: 6.651ns (logic 1.393ns (20.945%) route 5.258ns (79.055%)) - Logic Levels: 6 (LUT2=3 LUT5=1 LUT6=2) - Clock Path Skew: -0.157ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 2.688ns = ( 12.688 - 10.000 ) - Source Clock Delay (SCD): 2.975ns - Clock Pessimism Removal (CPR): 0.130ns + Data Path Delay: 6.527ns (logic 2.990ns (45.813%) route 3.537ns (54.187%)) + Logic Levels: 9 (CARRY4=4 LUT3=1 LUT4=2 LUT6=2) + Clock Path Skew: -0.022ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.760ns = ( 12.760 - 10.000 ) + Source Clock Delay (SCD): 3.051ns + Clock Pessimism Removal (CPR): 0.269ns Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.300ns @@ -280,24 +280,34 @@ Slack (MET) : 3.068ns (required time - arrival time) PS7_X0Y0 PS7 0.000 0.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 1.207 1.207 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 1.308 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 1.667 2.975 mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/aclk - SLICE_X10Y21 FDRE r mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/gen_pipelined.mesg_reg_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X10Y21 FDRE (Prop_fdre_C_Q) 0.478 3.453 f mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/gen_pipelined.mesg_reg_reg[4]/Q - net (fo=4, routed) 0.847 4.300 mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.USE_SPLIT_W.write_resp_inst/Q[4] - SLICE_X10Y22 LUT6 (Prop_lut6_I0_O) 0.295 4.595 f mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.USE_SPLIT_W.write_resp_inst/s_axi_bvalid_INST_0_i_1/O - net (fo=3, routed) 0.633 5.228 mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/b_reg/gen_pipelined.mesg_reg_reg[4] - SLICE_X9Y19 LUT2 (Prop_lut2_I1_O) 0.124 5.352 r mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/b_reg/s_axi_bvalid_INST_0/O - net (fo=1, routed) 0.753 6.105 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_si_handler/inst_arb_stall_late/s_sc_send[0] - SLICE_X14Y22 LUT2 (Prop_lut2_I0_O) 0.124 6.229 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_si_handler/inst_arb_stall_late/count_r[5]_i_3__1/O - net (fo=45, routed) 1.589 7.818 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/p_0_in3_in - SLICE_X27Y38 LUT6 (Prop_lut6_I1_O) 0.124 7.942 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_rd.fifo_empty_r_i_6/O - net (fo=1, routed) 0.985 8.927 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_rd.fifo_empty_r_i_6_n_0 - SLICE_X27Y38 LUT5 (Prop_lut5_I2_O) 0.124 9.051 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_rd.fifo_empty_r_i_2/O - net (fo=2, routed) 0.451 9.502 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_rd.fifo_empty_r_i_2_n_0 - SLICE_X27Y38 LUT2 (Prop_lut2_I0_O) 0.124 9.626 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_rd.fifo_empty_r_i_1/O - net (fo=1, routed) 0.000 9.626 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1_n_1 - SLICE_X27Y38 FDSE r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_rd.fifo_empty_r_reg/D + net (fo=7300, routed) 1.743 3.051 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/m_axi_s2mm_aclk + SLICE_X42Y31 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_dup_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X42Y31 FDRE (Prop_fdre_C_Q) 0.518 3.569 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_dup_reg[1]/Q + net (fo=4, routed) 1.102 4.671 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/out[1] + SLICE_X43Y31 LUT4 (Prop_lut4_I0_O) 0.124 4.795 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/sig_btt_lteq_max_first_incr0_carry_i_6/O + net (fo=1, routed) 0.000 4.795 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION_n_11 + SLICE_X43Y31 CARRY4 (Prop_carry4_S[0]_CO[3]) + 0.532 5.327 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_lteq_max_first_incr0_carry/CO[3] + net (fo=1, routed) 0.000 5.327 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_lteq_max_first_incr0_carry_n_0 + SLICE_X43Y32 CARRY4 (Prop_carry4_CI_CO[2]) + 0.250 5.577 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_lteq_max_first_incr0_carry__0/CO[2] + net (fo=20, routed) 0.912 6.488 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_lteq_max_first_incr + SLICE_X42Y32 LUT3 (Prop_lut3_I2_O) 0.313 6.801 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_prv0_carry__0_i_1/O + net (fo=1, routed) 0.000 6.801 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_prv0_carry__0_i_1_n_0 + SLICE_X42Y32 CARRY4 (Prop_carry4_S[3]_CO[3]) + 0.376 7.177 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_prv0_carry__0/CO[3] + net (fo=1, routed) 0.000 7.177 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_prv0_carry__0_n_0 + SLICE_X42Y33 CARRY4 (Prop_carry4_CI_O[1]) + 0.323 7.500 f mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_prv0_carry__1/O[1] + net (fo=1, routed) 0.504 8.004 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_prv0[9] + SLICE_X43Y33 LUT4 (Prop_lut4_I3_O) 0.306 8.310 f mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr[9]_i_1__0/O + net (fo=3, routed) 0.456 8.766 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr[9]_i_1__0_n_0 + SLICE_X43Y33 LUT6 (Prop_lut6_I1_O) 0.124 8.890 f mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_eq_0_i_4/O + net (fo=1, routed) 0.564 9.454 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_sm_ld_dre_cmd_reg_1 + SLICE_X40Y32 LUT6 (Prop_lut6_I4_O) 0.124 9.578 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_btt_eq_0_i_1/O + net (fo=1, routed) 0.000 9.578 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF_n_48 + SLICE_X40Y32 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_eq_0_reg/D ------------------------------------------------------------------- ------------------- (clock clk_fpga_0 rise edge) @@ -305,29 +315,29 @@ Slack (MET) : 3.068ns (required time - arrival time) PS7_X0Y0 PS7 0.000 10.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 1.101 11.101 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 11.192 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 1.496 12.688 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/s_sc_aclk - SLICE_X27Y38 FDSE r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_rd.fifo_empty_r_reg/C - clock pessimism 0.130 12.818 - clock uncertainty -0.154 12.664 - SLICE_X27Y38 FDSE (Setup_fdse_C_D) 0.029 12.693 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_rd.fifo_empty_r_reg + net (fo=7300, routed) 1.568 12.760 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/m_axi_s2mm_aclk + SLICE_X40Y32 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_eq_0_reg/C + clock pessimism 0.269 13.029 + clock uncertainty -0.154 12.875 + SLICE_X40Y32 FDRE (Setup_fdre_C_D) 0.029 12.904 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_eq_0_reg ------------------------------------------------------------------- - required time 12.693 - arrival time -9.626 + required time 12.904 + arrival time -9.578 ------------------------------------------------------------------- - slack 3.068 + slack 3.326 -Slack (MET) : 3.109ns (required time - arrival time) +Slack (MET) : 3.354ns (required time - arrival time) Source: mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/gen_pipelined.mesg_reg_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) - Destination: mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.afull_r_reg/D + Destination: mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.full_r_reg_inv/D (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_fpga_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns) - Data Path Delay: 6.609ns (logic 1.589ns (24.041%) route 5.020ns (75.959%)) - Logic Levels: 6 (LUT2=2 LUT5=1 LUT6=3) - Clock Path Skew: -0.159ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 2.686ns = ( 12.686 - 10.000 ) + Data Path Delay: 6.063ns (logic 1.330ns (21.936%) route 4.733ns (78.064%)) + Logic Levels: 6 (LUT2=2 LUT3=1 LUT5=2 LUT6=1) + Clock Path Skew: -0.158ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.688ns = ( 12.688 - 10.000 ) Source Clock Delay (SCD): 2.975ns Clock Pessimism Removal (CPR): 0.130ns Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE @@ -344,23 +354,23 @@ Slack (MET) : 3.109ns (required time - arrival time) net (fo=1, routed) 1.207 1.207 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 1.308 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O net (fo=7300, routed) 1.667 2.975 mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/aclk - SLICE_X10Y21 FDRE r mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/gen_pipelined.mesg_reg_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X10Y21 FDRE (Prop_fdre_C_Q) 0.478 3.453 r mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/gen_pipelined.mesg_reg_reg[4]/Q - net (fo=4, routed) 0.847 4.300 mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.USE_SPLIT_W.write_resp_inst/Q[4] - SLICE_X10Y22 LUT6 (Prop_lut6_I0_O) 0.295 4.595 r mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.USE_SPLIT_W.write_resp_inst/s_axi_bvalid_INST_0_i_1/O - net (fo=3, routed) 0.633 5.228 mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/b_reg/gen_pipelined.mesg_reg_reg[4] - SLICE_X9Y19 LUT2 (Prop_lut2_I1_O) 0.124 5.352 f mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/b_reg/s_axi_bvalid_INST_0/O - net (fo=1, routed) 0.753 6.105 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_si_handler/inst_arb_stall_late/s_sc_send[0] - SLICE_X14Y22 LUT2 (Prop_lut2_I0_O) 0.124 6.229 f mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_si_handler/inst_arb_stall_late/count_r[5]_i_3__1/O - net (fo=45, routed) 1.472 7.701 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/p_0_in3_in - SLICE_X31Y35 LUT5 (Prop_lut5_I0_O) 0.118 7.819 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_wr.afull_r_i_9/O - net (fo=1, routed) 0.594 8.413 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_wr.afull_r_i_9_n_0 - SLICE_X33Y35 LUT6 (Prop_lut6_I1_O) 0.326 8.739 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_wr.afull_r_i_4/O - net (fo=1, routed) 0.722 9.460 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_wr.afull_r_i_4_n_0 - SLICE_X31Y35 LUT6 (Prop_lut6_I2_O) 0.124 9.584 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_wr.afull_r_i_1/O - net (fo=1, routed) 0.000 9.584 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1_n_0 - SLICE_X31Y35 FDRE r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.afull_r_reg/D + SLICE_X11Y21 FDRE r mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/gen_pipelined.mesg_reg_reg[4]/C + ------------------------------------------------------------------- ------------------- + SLICE_X11Y21 FDRE (Prop_fdre_C_Q) 0.419 3.394 f mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/gen_pipelined.mesg_reg_reg[4]/Q + net (fo=4, routed) 0.821 4.215 mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.USE_SPLIT_W.write_resp_inst/Q[4] + SLICE_X11Y23 LUT6 (Prop_lut6_I0_O) 0.299 4.514 f mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.USE_SPLIT_W.write_resp_inst/s_axi_bvalid_INST_0_i_1/O + net (fo=3, routed) 0.416 4.930 mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/b_reg/gen_pipelined.mesg_reg_reg[4] + SLICE_X11Y22 LUT2 (Prop_lut2_I1_O) 0.124 5.054 r mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/b_reg/s_axi_bvalid_INST_0/O + net (fo=1, routed) 0.311 5.364 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_si_handler/inst_arb_stall_late/s_sc_send[0] + SLICE_X12Y23 LUT2 (Prop_lut2_I0_O) 0.124 5.488 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_si_handler/inst_arb_stall_late/count_r[5]_i_3__1/O + net (fo=45, routed) 1.526 7.015 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/p_0_in3_in + SLICE_X26Y36 LUT5 (Prop_lut5_I1_O) 0.124 7.139 f mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_rd.fifo_empty_r_i_4/O + net (fo=1, routed) 0.855 7.994 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_rd.fifo_empty_r_i_4_n_0 + SLICE_X27Y36 LUT5 (Prop_lut5_I0_O) 0.124 8.118 f mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_rd.fifo_empty_r_i_2/O + net (fo=2, routed) 0.422 8.540 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_rd.fifo_empty_r_i_2_n_0 + SLICE_X28Y37 LUT3 (Prop_lut3_I1_O) 0.116 8.656 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_wr.full_r_inv_i_1/O + net (fo=1, routed) 0.382 9.038 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1_n_0 + SLICE_X29Y37 FDRE r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.full_r_reg_inv/D ------------------------------------------------------------------- ------------------- (clock clk_fpga_0 rise edge) @@ -368,31 +378,31 @@ Slack (MET) : 3.109ns (required time - arrival time) PS7_X0Y0 PS7 0.000 10.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 1.101 11.101 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 11.192 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 1.494 12.686 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/s_sc_aclk - SLICE_X31Y35 FDRE r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.afull_r_reg/C - clock pessimism 0.130 12.816 - clock uncertainty -0.154 12.662 - SLICE_X31Y35 FDRE (Setup_fdre_C_D) 0.031 12.693 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.afull_r_reg + net (fo=7300, routed) 1.495 12.688 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/s_sc_aclk + SLICE_X29Y37 FDRE r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.full_r_reg_inv/C + clock pessimism 0.130 12.817 + clock uncertainty -0.154 12.663 + SLICE_X29Y37 FDRE (Setup_fdre_C_D) -0.271 12.392 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.full_r_reg_inv ------------------------------------------------------------------- - required time 12.693 - arrival time -9.584 + required time 12.392 + arrival time -9.038 ------------------------------------------------------------------- - slack 3.109 + slack 3.354 -Slack (MET) : 3.302ns (required time - arrival time) - Source: mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_dup_reg[1]/C +Slack (MET) : 3.443ns (required time - arrival time) + Source: mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/gen_endpoint.w_state_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) - Destination: mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_eq_0_reg/D + Destination: mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.afull_r_reg/D (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_fpga_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns) - Data Path Delay: 6.552ns (logic 3.140ns (47.927%) route 3.412ns (52.073%)) - Logic Levels: 9 (CARRY4=4 LUT4=3 LUT6=2) - Clock Path Skew: -0.021ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 2.761ns = ( 12.761 - 10.000 ) - Source Clock Delay (SCD): 3.051ns - Clock Pessimism Removal (CPR): 0.269ns + Data Path Delay: 6.278ns (logic 1.784ns (28.417%) route 4.494ns (71.583%)) + Logic Levels: 6 (LUT2=3 LUT4=1 LUT6=2) + Clock Path Skew: -0.154ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.676ns = ( 12.677 - 10.000 ) + Source Clock Delay (SCD): 2.960ns + Clock Pessimism Removal (CPR): 0.130ns Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.300ns @@ -406,34 +416,24 @@ Slack (MET) : 3.302ns (required time - arrival time) PS7_X0Y0 PS7 0.000 0.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 1.207 1.207 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 1.308 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 1.743 3.051 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/m_axi_s2mm_aclk - SLICE_X42Y31 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_dup_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X42Y31 FDRE (Prop_fdre_C_Q) 0.518 3.569 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_dup_reg[1]/Q - net (fo=4, routed) 1.049 4.618 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/out[1] - SLICE_X43Y31 LUT4 (Prop_lut4_I0_O) 0.124 4.742 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION/sig_btt_lteq_max_first_incr0_carry_i_6/O - net (fo=1, routed) 0.000 4.742 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/SLICE_INSERTION_n_11 - SLICE_X43Y31 CARRY4 (Prop_carry4_S[0]_CO[3]) - 0.532 5.274 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_lteq_max_first_incr0_carry/CO[3] - net (fo=1, routed) 0.000 5.274 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_lteq_max_first_incr0_carry_n_0 - SLICE_X43Y32 CARRY4 (Prop_carry4_CI_CO[2]) - 0.250 5.524 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_lteq_max_first_incr0_carry__0/CO[2] - net (fo=20, routed) 0.560 6.083 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_lteq_max_first_incr - SLICE_X42Y31 LUT4 (Prop_lut4_I2_O) 0.313 6.396 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_prv0_carry_i_3/O - net (fo=1, routed) 0.000 6.396 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_prv0_carry_i_3_n_0 - SLICE_X42Y31 CARRY4 (Prop_carry4_S[1]_CO[3]) - 0.533 6.929 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_prv0_carry/CO[3] - net (fo=1, routed) 0.000 6.929 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_prv0_carry_n_0 - SLICE_X42Y32 CARRY4 (Prop_carry4_CI_O[3]) - 0.315 7.244 f mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_prv0_carry__0/O[3] - net (fo=1, routed) 0.548 7.792 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr_prv0[7] - SLICE_X43Y33 LUT4 (Prop_lut4_I3_O) 0.307 8.099 f mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr[7]_i_1__0/O - net (fo=3, routed) 0.823 8.922 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_cntr[7]_i_1__0_n_0 - SLICE_X41Y33 LUT6 (Prop_lut6_I4_O) 0.124 9.046 f mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_eq_0_i_2/O - net (fo=1, routed) 0.433 9.479 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_sm_ld_dre_cmd_reg - SLICE_X41Y33 LUT6 (Prop_lut6_I2_O) 0.124 9.603 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/sig_btt_eq_0_i_1/O - net (fo=1, routed) 0.000 9.603 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF_n_48 - SLICE_X41Y33 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_eq_0_reg/D + net (fo=7300, routed) 1.652 2.960 mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/aclk + SLICE_X25Y27 FDRE r mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/gen_endpoint.w_state_reg[1]/C + ------------------------------------------------------------------- ------------------- + SLICE_X25Y27 FDRE (Prop_fdre_C_Q) 0.419 3.379 r mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/gen_endpoint.w_state_reg[1]/Q + net (fo=19, routed) 1.038 4.417 mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/aw_reg_stall/gen_endpoint.w_state[1] + SLICE_X21Y21 LUT2 (Prop_lut2_I1_O) 0.299 4.716 f mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/aw_reg_stall/m_axi_awvalid_INST_0/O + net (fo=5, routed) 0.797 5.514 mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/splitter_inst/gen_no_wsplitter.gen_endpoint_woffset.gen_wbypass_offset_fifo.wbypass_offset_fifo/s_axi_awvalid + SLICE_X21Y15 LUT2 (Prop_lut2_I1_O) 0.118 5.632 f mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_si_converter/inst/splitter_inst/gen_no_wsplitter.gen_endpoint_woffset.gen_wbypass_offset_fifo.wbypass_offset_fifo/m_axi_awvalid_INST_0/O + net (fo=1, routed) 0.436 6.068 mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_si_handler/inst_arb_stall_late/s_sc_send[0] + SLICE_X21Y15 LUT2 (Prop_lut2_I0_O) 0.326 6.394 f mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_si_handler/inst_arb_stall_late/count_r[5]_i_3__1/O + net (fo=48, routed) 0.999 7.393 mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/p_0_in3_in + SLICE_X20Y24 LUT4 (Prop_lut4_I1_O) 0.150 7.543 r mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_wr.afull_r_i_7/O + net (fo=1, routed) 0.286 7.829 mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_wr.afull_r_i_7_n_0 + SLICE_X20Y24 LUT6 (Prop_lut6_I3_O) 0.348 8.177 r mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_wr.afull_r_i_2/O + net (fo=1, routed) 0.937 9.114 mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_wr.afull_r_i_2_n_0 + SLICE_X21Y23 LUT6 (Prop_lut6_I0_O) 0.124 9.238 r mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_wr.afull_r_i_1/O + net (fo=1, routed) 0.000 9.238 mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1_n_1 + SLICE_X21Y23 FDRE r mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.afull_r_reg/D ------------------------------------------------------------------- ------------------- (clock clk_fpga_0 rise edge) @@ -441,31 +441,31 @@ Slack (MET) : 3.302ns (required time - arrival time) PS7_X0Y0 PS7 0.000 10.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 1.101 11.101 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 11.192 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 1.569 12.761 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/m_axi_s2mm_aclk - SLICE_X41Y33 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_eq_0_reg/C - clock pessimism 0.269 13.030 - clock uncertainty -0.154 12.876 - SLICE_X41Y33 FDRE (Setup_fdre_C_D) 0.029 12.905 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/sig_btt_eq_0_reg + net (fo=7300, routed) 1.484 12.676 mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/s_sc_aclk + SLICE_X21Y23 FDRE r mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.afull_r_reg/C + clock pessimism 0.130 12.806 + clock uncertainty -0.154 12.652 + SLICE_X21Y23 FDRE (Setup_fdre_C_D) 0.029 12.681 mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.afull_r_reg ------------------------------------------------------------------- - required time 12.905 - arrival time -9.603 + required time 12.681 + arrival time -9.238 ------------------------------------------------------------------- - slack 3.302 + slack 3.443 -Slack (MET) : 3.374ns (required time - arrival time) - Source: mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/gen_pipelined.mesg_reg_reg[4]/C +Slack (MET) : 3.478ns (required time - arrival time) + Source: mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_input_addr_reg_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) - Destination: mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.full_r_reg_inv/D + Destination: mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_realigner_btt2_reg[10]/D (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_fpga_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns) - Data Path Delay: 6.344ns (logic 1.589ns (25.048%) route 4.755ns (74.952%)) - Logic Levels: 6 (LUT2=2 LUT5=2 LUT6=2) - Clock Path Skew: -0.158ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 2.687ns = ( 12.688 - 10.000 ) - Source Clock Delay (SCD): 2.975ns - Clock Pessimism Removal (CPR): 0.130ns + Data Path Delay: 6.115ns (logic 2.181ns (35.668%) route 3.934ns (64.332%)) + Logic Levels: 7 (CARRY4=1 LUT2=2 LUT4=1 LUT5=1 LUT6=2) + Clock Path Skew: 0.022ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.760ns = ( 12.760 - 10.000 ) + Source Clock Delay (SCD): 2.968ns + Clock Pessimism Removal (CPR): 0.230ns Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns Total Input Jitter (TIJ): 0.300ns @@ -479,24 +479,27 @@ Slack (MET) : 3.374ns (required time - arrival time) PS7_X0Y0 PS7 0.000 0.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 1.207 1.207 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 1.308 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 1.667 2.975 mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/aclk - SLICE_X10Y21 FDRE r mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/gen_pipelined.mesg_reg_reg[4]/C - ------------------------------------------------------------------- ------------------- - SLICE_X10Y21 FDRE (Prop_fdre_C_Q) 0.478 3.453 f mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.write_addr_inst/USE_B_CHANNEL.cmd_b_queue/gen_pipelined.mesg_reg_reg[4]/Q - net (fo=4, routed) 0.847 4.300 mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.USE_SPLIT_W.write_resp_inst/Q[4] - SLICE_X10Y22 LUT6 (Prop_lut6_I0_O) 0.295 4.595 f mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_WRITE.USE_SPLIT_W.write_resp_inst/s_axi_bvalid_INST_0_i_1/O - net (fo=3, routed) 0.633 5.228 mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/b_reg/gen_pipelined.mesg_reg_reg[4] - SLICE_X9Y19 LUT2 (Prop_lut2_I1_O) 0.124 5.352 r mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/b_reg/s_axi_bvalid_INST_0/O - net (fo=1, routed) 0.753 6.105 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_si_handler/inst_arb_stall_late/s_sc_send[0] - SLICE_X14Y22 LUT2 (Prop_lut2_I0_O) 0.124 6.229 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_si_handler/inst_arb_stall_late/count_r[5]_i_3__1/O - net (fo=45, routed) 1.486 7.715 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/p_0_in3_in - SLICE_X30Y35 LUT5 (Prop_lut5_I2_O) 0.116 7.831 f mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_wr.full_r_inv_i_7/O - net (fo=1, routed) 0.469 8.300 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_wr.full_r_inv_i_7_n_0 - SLICE_X30Y35 LUT6 (Prop_lut6_I1_O) 0.328 8.628 f mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_wr.full_r_inv_i_4/O - net (fo=1, routed) 0.567 9.195 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_wr.full_r_inv_i_4_n_0 - SLICE_X33Y35 LUT5 (Prop_lut5_I2_O) 0.124 9.319 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_wr.full_r_inv_i_1__0/O - net (fo=1, routed) 0.000 9.319 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1_n_1 - SLICE_X33Y35 FDRE r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.full_r_reg_inv/D + net (fo=7300, routed) 1.660 2.968 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/m_axi_s2mm_aclk + SLICE_X33Y28 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_input_addr_reg_reg[2]/C + ------------------------------------------------------------------- ------------------- + SLICE_X33Y28 FDRE (Prop_fdre_C_Q) 0.456 3.424 f mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_input_addr_reg_reg[2]/Q + net (fo=11, routed) 0.837 4.261 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_input_addr_reg[2] + SLICE_X33Y29 LUT4 (Prop_lut4_I0_O) 0.124 4.385 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_btt_lt_b2mbaa2_carry_i_10/O + net (fo=3, routed) 0.275 4.660 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_btt_lt_b2mbaa2_carry_i_10_n_0 + SLICE_X33Y29 LUT5 (Prop_lut5_I3_O) 0.124 4.784 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_btt_eq_b2mbaa2_carry_i_4/O + net (fo=1, routed) 0.324 5.109 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_btt_eq_b2mbaa2_carry_i_4_n_0 + SLICE_X34Y28 LUT6 (Prop_lut6_I0_O) 0.124 5.233 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_btt_eq_b2mbaa2_carry_i_2/O + net (fo=1, routed) 0.000 5.233 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_btt_eq_b2mbaa2_carry_i_2_n_0 + SLICE_X34Y28 CARRY4 (Prop_carry4_S[1]_CO[2]) + 0.574 5.807 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_btt_eq_b2mbaa2_carry/CO[2] + net (fo=1, routed) 0.816 6.623 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_btt_eq_b2mbaa2 + SLICE_X34Y30 LUT6 (Prop_lut6_I4_O) 0.310 6.933 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_skip_align2mbaa_s_h_i_2/O + net (fo=3, routed) 0.419 7.352 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_skip_align2mbaa + SLICE_X35Y31 LUT2 (Prop_lut2_I1_O) 0.118 7.470 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_realigner_btt2[13]_i_2/O + net (fo=15, routed) 0.880 8.350 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_realign_cmd_cmplt_reg0 + SLICE_X37Y32 LUT2 (Prop_lut2_I1_O) 0.351 8.701 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_realigner_btt2[10]_i_1/O + net (fo=1, routed) 0.382 9.083 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_realigner_btt[10] + SLICE_X37Y32 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_realigner_btt2_reg[10]/D ------------------------------------------------------------------- ------------------- (clock clk_fpga_0 rise edge) @@ -504,30 +507,30 @@ Slack (MET) : 3.374ns (required time - arrival time) PS7_X0Y0 PS7 0.000 10.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 1.101 11.101 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 11.192 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 1.495 12.687 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/s_sc_aclk - SLICE_X33Y35 FDRE r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.full_r_reg_inv/C - clock pessimism 0.130 12.817 - clock uncertainty -0.154 12.663 - SLICE_X33Y35 FDRE (Setup_fdre_C_D) 0.029 12.692 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_b_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_wr.full_r_reg_inv + net (fo=7300, routed) 1.567 12.759 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/m_axi_s2mm_aclk + SLICE_X37Y32 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_realigner_btt2_reg[10]/C + clock pessimism 0.230 12.990 + clock uncertainty -0.154 12.836 + SLICE_X37Y32 FDRE (Setup_fdre_C_D) -0.275 12.561 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_realigner_btt2_reg[10] ------------------------------------------------------------------- - required time 12.692 - arrival time -9.319 + required time 12.561 + arrival time -9.083 ------------------------------------------------------------------- - slack 3.374 + slack 3.478 -Slack (MET) : 3.547ns (required time - arrival time) - Source: mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/gen_pipelined.state_reg[1]/C +Slack (MET) : 3.497ns (required time - arrival time) + Source: mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_mmap_reset_reg_reg/C (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) - Destination: mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.full_r_reg_inv/D + Destination: mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[15]/R (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_fpga_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns) - Data Path Delay: 5.921ns (logic 1.266ns (21.382%) route 4.655ns (78.618%)) - Logic Levels: 5 (LUT2=2 LUT3=1 LUT5=2) - Clock Path Skew: -0.109ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 2.691ns = ( 12.691 - 10.000 ) - Source Clock Delay (SCD): 3.031ns + Data Path Delay: 5.684ns (logic 0.718ns (12.631%) route 4.966ns (87.369%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.674ns = ( 12.674 - 10.000 ) + Source Clock Delay (SCD): 3.046ns Clock Pessimism Removal (CPR): 0.230ns Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -542,22 +545,14 @@ Slack (MET) : 3.547ns (required time - arrival time) PS7_X0Y0 PS7 0.000 0.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 1.207 1.207 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 1.308 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 1.723 3.031 mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/aclk - SLICE_X3Y14 FDRE r mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/gen_pipelined.state_reg[1]/C - ------------------------------------------------------------------- ------------------- - SLICE_X3Y14 FDRE (Prop_fdre_C_Q) 0.456 3.487 r mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/splitter_inst/gen_axi3.axi3_conv_inst/USE_READ.USE_SPLIT_R.read_addr_inst/USE_R_CHANNEL.cmd_queue/gen_pipelined.state_reg[1]/Q - net (fo=19, routed) 1.058 4.545 mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/r_reg/USE_READ.USE_SPLIT_R.rd_cmd_valid - SLICE_X4Y2 LUT2 (Prop_lut2_I1_O) 0.116 4.661 r mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/r_reg/s_axi_rvalid_INST_0/O - net (fo=1, routed) 0.454 5.115 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_si_handler/inst_arb_stall_late/s_sc_send[0] - SLICE_X5Y2 LUT2 (Prop_lut2_I0_O) 0.328 5.443 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_si_handler/inst_arb_stall_late/count_r[5]_i_3__1/O - net (fo=45, routed) 1.159 6.603 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/p_0_in3_in - SLICE_X15Y5 LUT5 (Prop_lut5_I1_O) 0.124 6.727 f mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_rd.fifo_empty_r_i_4/O - net (fo=1, routed) 0.951 7.677 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_rd.fifo_empty_r_i_4_n_0 - SLICE_X18Y6 LUT5 (Prop_lut5_I0_O) 0.124 7.801 f mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_rd.fifo_empty_r_i_2/O - net (fo=2, routed) 0.426 8.228 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_rd.fifo_empty_r_i_2_n_0 - SLICE_X18Y6 LUT3 (Prop_lut3_I1_O) 0.118 8.346 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1/gen_wr.full_r_inv_i_1/O - net (fo=1, routed) 0.606 8.952 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.inst_wr_addra_p1_n_0 - SLICE_X17Y8 FDRE r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.full_r_reg_inv/D + net (fo=7300, routed) 1.738 3.046 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/m_axi_s2mm_aclk + SLICE_X39Y28 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_mmap_reset_reg_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X39Y28 FDRE (Prop_fdre_C_Q) 0.419 3.465 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_mmap_reset_reg_reg/Q + net (fo=100, routed) 3.741 7.206 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_reset_reg + SLICE_X37Y21 LUT6 (Prop_lut6_I0_O) 0.299 7.505 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_len_reg[4]_i_1/O + net (fo=41, routed) 1.225 8.730 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_cache_reg0 + SLICE_X30Y24 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[15]/R ------------------------------------------------------------------- ------------------- (clock clk_fpga_0 rise edge) @@ -565,30 +560,30 @@ Slack (MET) : 3.547ns (required time - arrival time) PS7_X0Y0 PS7 0.000 10.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 1.101 11.101 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 11.192 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 1.499 12.691 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/s_sc_aclk - SLICE_X17Y8 FDRE r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.full_r_reg_inv/C - clock pessimism 0.230 12.922 - clock uncertainty -0.154 12.768 - SLICE_X17Y8 FDRE (Setup_fdre_C_D) -0.269 12.499 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_wr.full_r_reg_inv + net (fo=7300, routed) 1.482 12.674 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/m_axi_s2mm_aclk + SLICE_X30Y24 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[15]/C + clock pessimism 0.230 12.905 + clock uncertainty -0.154 12.751 + SLICE_X30Y24 FDRE (Setup_fdre_C_R) -0.524 12.227 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[15] ------------------------------------------------------------------- - required time 12.499 - arrival time -8.952 + required time 12.227 + arrival time -8.730 ------------------------------------------------------------------- - slack 3.547 + slack 3.497 -Slack (MET) : 3.580ns (required time - arrival time) - Source: mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][4]_srl16/CLK - (rising edge-triggered cell SRL16E clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) - Destination: mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_burst_dbeat_cntr_reg[0]/R +Slack (MET) : 3.497ns (required time - arrival time) + Source: mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_mmap_reset_reg_reg/C + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[24]/R (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_fpga_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns) - Data Path Delay: 5.778ns (logic 2.232ns (38.629%) route 3.546ns (61.371%)) - Logic Levels: 5 (LUT2=1 LUT4=1 LUT6=3) - Clock Path Skew: -0.059ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 2.752ns = ( 12.752 - 10.000 ) - Source Clock Delay (SCD): 3.042ns + Data Path Delay: 5.684ns (logic 0.718ns (12.631%) route 4.966ns (87.369%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.674ns = ( 12.674 - 10.000 ) + Source Clock Delay (SCD): 3.046ns Clock Pessimism Removal (CPR): 0.230ns Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -603,23 +598,14 @@ Slack (MET) : 3.580ns (required time - arrival time) PS7_X0Y0 PS7 0.000 0.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 1.207 1.207 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 1.308 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 1.734 3.042 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/m_axi_s2mm_aclk - SLICE_X42Y25 SRL16E r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][4]_srl16/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X42Y25 SRL16E (Prop_srl16e_CLK_Q) - 1.612 4.654 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][4]_srl16/Q - net (fo=1, routed) 1.039 5.693 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/storage_data_reg[8][4] - SLICE_X41Y22 LUT6 (Prop_lut6_I0_O) 0.124 5.817 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/xpm_fifo_base_inst_i_10/O - net (fo=3, routed) 0.425 6.242 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/xpm_fifo_base_inst_i_10_n_0 - SLICE_X41Y23 LUT4 (Prop_lut4_I0_O) 0.124 6.366 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/xpm_fifo_base_inst_i_2/O - net (fo=7, routed) 0.515 6.881 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_m_valid_out_reg_0 - SLICE_X40Y25 LUT6 (Prop_lut6_I4_O) 0.124 7.005 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_clr_dbc_reg_i_2/O - net (fo=2, routed) 0.429 7.434 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_clr_dbc_reg_reg - SLICE_X40Y26 LUT2 (Prop_lut2_I0_O) 0.124 7.558 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_burst_dbeat_cntr[3]_i_3/O - net (fo=4, routed) 0.459 8.017 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0 - SLICE_X39Y26 LUT6 (Prop_lut6_I5_O) 0.124 8.141 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_burst_dbeat_cntr[3]_i_1/O - net (fo=4, routed) 0.679 8.820 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_burst_dbeat_cntr0 - SLICE_X39Y26 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_burst_dbeat_cntr_reg[0]/R + net (fo=7300, routed) 1.738 3.046 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/m_axi_s2mm_aclk + SLICE_X39Y28 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_mmap_reset_reg_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X39Y28 FDRE (Prop_fdre_C_Q) 0.419 3.465 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_mmap_reset_reg_reg/Q + net (fo=100, routed) 3.741 7.206 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_reset_reg + SLICE_X37Y21 LUT6 (Prop_lut6_I0_O) 0.299 7.505 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_len_reg[4]_i_1/O + net (fo=41, routed) 1.225 8.730 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_cache_reg0 + SLICE_X30Y24 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[24]/R ------------------------------------------------------------------- ------------------- (clock clk_fpga_0 rise edge) @@ -627,30 +613,30 @@ Slack (MET) : 3.580ns (required time - arrival time) PS7_X0Y0 PS7 0.000 10.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 1.101 11.101 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 11.192 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 1.560 12.752 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/m_axi_s2mm_aclk - SLICE_X39Y26 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_burst_dbeat_cntr_reg[0]/C - clock pessimism 0.230 12.983 - clock uncertainty -0.154 12.829 - SLICE_X39Y26 FDRE (Setup_fdre_C_R) -0.429 12.400 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_burst_dbeat_cntr_reg[0] + net (fo=7300, routed) 1.482 12.674 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/m_axi_s2mm_aclk + SLICE_X30Y24 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[24]/C + clock pessimism 0.230 12.905 + clock uncertainty -0.154 12.751 + SLICE_X30Y24 FDRE (Setup_fdre_C_R) -0.524 12.227 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[24] ------------------------------------------------------------------- - required time 12.400 - arrival time -8.820 + required time 12.227 + arrival time -8.730 ------------------------------------------------------------------- - slack 3.580 + slack 3.497 -Slack (MET) : 3.580ns (required time - arrival time) - Source: mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][4]_srl16/CLK - (rising edge-triggered cell SRL16E clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) - Destination: mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_burst_dbeat_cntr_reg[1]/R +Slack (MET) : 3.497ns (required time - arrival time) + Source: mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_mmap_reset_reg_reg/C + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[25]/R (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_fpga_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns) - Data Path Delay: 5.778ns (logic 2.232ns (38.629%) route 3.546ns (61.371%)) - Logic Levels: 5 (LUT2=1 LUT4=1 LUT6=3) - Clock Path Skew: -0.059ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 2.752ns = ( 12.752 - 10.000 ) - Source Clock Delay (SCD): 3.042ns + Data Path Delay: 5.684ns (logic 0.718ns (12.631%) route 4.966ns (87.369%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.674ns = ( 12.674 - 10.000 ) + Source Clock Delay (SCD): 3.046ns Clock Pessimism Removal (CPR): 0.230ns Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -665,23 +651,14 @@ Slack (MET) : 3.580ns (required time - arrival time) PS7_X0Y0 PS7 0.000 0.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 1.207 1.207 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 1.308 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 1.734 3.042 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/m_axi_s2mm_aclk - SLICE_X42Y25 SRL16E r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][4]_srl16/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X42Y25 SRL16E (Prop_srl16e_CLK_Q) - 1.612 4.654 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][4]_srl16/Q - net (fo=1, routed) 1.039 5.693 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/storage_data_reg[8][4] - SLICE_X41Y22 LUT6 (Prop_lut6_I0_O) 0.124 5.817 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/xpm_fifo_base_inst_i_10/O - net (fo=3, routed) 0.425 6.242 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/xpm_fifo_base_inst_i_10_n_0 - SLICE_X41Y23 LUT4 (Prop_lut4_I0_O) 0.124 6.366 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/xpm_fifo_base_inst_i_2/O - net (fo=7, routed) 0.515 6.881 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_m_valid_out_reg_0 - SLICE_X40Y25 LUT6 (Prop_lut6_I4_O) 0.124 7.005 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_clr_dbc_reg_i_2/O - net (fo=2, routed) 0.429 7.434 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_clr_dbc_reg_reg - SLICE_X40Y26 LUT2 (Prop_lut2_I0_O) 0.124 7.558 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_burst_dbeat_cntr[3]_i_3/O - net (fo=4, routed) 0.459 8.017 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0 - SLICE_X39Y26 LUT6 (Prop_lut6_I5_O) 0.124 8.141 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_burst_dbeat_cntr[3]_i_1/O - net (fo=4, routed) 0.679 8.820 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_burst_dbeat_cntr0 - SLICE_X39Y26 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_burst_dbeat_cntr_reg[1]/R + net (fo=7300, routed) 1.738 3.046 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/m_axi_s2mm_aclk + SLICE_X39Y28 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_mmap_reset_reg_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X39Y28 FDRE (Prop_fdre_C_Q) 0.419 3.465 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_mmap_reset_reg_reg/Q + net (fo=100, routed) 3.741 7.206 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_reset_reg + SLICE_X37Y21 LUT6 (Prop_lut6_I0_O) 0.299 7.505 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_len_reg[4]_i_1/O + net (fo=41, routed) 1.225 8.730 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_cache_reg0 + SLICE_X30Y24 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[25]/R ------------------------------------------------------------------- ------------------- (clock clk_fpga_0 rise edge) @@ -689,30 +666,30 @@ Slack (MET) : 3.580ns (required time - arrival time) PS7_X0Y0 PS7 0.000 10.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 1.101 11.101 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 11.192 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 1.560 12.752 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/m_axi_s2mm_aclk - SLICE_X39Y26 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_burst_dbeat_cntr_reg[1]/C - clock pessimism 0.230 12.983 - clock uncertainty -0.154 12.829 - SLICE_X39Y26 FDRE (Setup_fdre_C_R) -0.429 12.400 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_burst_dbeat_cntr_reg[1] + net (fo=7300, routed) 1.482 12.674 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/m_axi_s2mm_aclk + SLICE_X30Y24 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[25]/C + clock pessimism 0.230 12.905 + clock uncertainty -0.154 12.751 + SLICE_X30Y24 FDRE (Setup_fdre_C_R) -0.524 12.227 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[25] ------------------------------------------------------------------- - required time 12.400 - arrival time -8.820 + required time 12.227 + arrival time -8.730 ------------------------------------------------------------------- - slack 3.580 + slack 3.497 -Slack (MET) : 3.580ns (required time - arrival time) - Source: mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][4]_srl16/CLK - (rising edge-triggered cell SRL16E clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) - Destination: mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_burst_dbeat_cntr_reg[2]/R +Slack (MET) : 3.497ns (required time - arrival time) + Source: mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_mmap_reset_reg_reg/C + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[26]/R (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_fpga_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns) - Data Path Delay: 5.778ns (logic 2.232ns (38.629%) route 3.546ns (61.371%)) - Logic Levels: 5 (LUT2=1 LUT4=1 LUT6=3) - Clock Path Skew: -0.059ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 2.752ns = ( 12.752 - 10.000 ) - Source Clock Delay (SCD): 3.042ns + Data Path Delay: 5.684ns (logic 0.718ns (12.631%) route 4.966ns (87.369%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.674ns = ( 12.674 - 10.000 ) + Source Clock Delay (SCD): 3.046ns Clock Pessimism Removal (CPR): 0.230ns Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -727,23 +704,14 @@ Slack (MET) : 3.580ns (required time - arrival time) PS7_X0Y0 PS7 0.000 0.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 1.207 1.207 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 1.308 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 1.734 3.042 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/m_axi_s2mm_aclk - SLICE_X42Y25 SRL16E r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][4]_srl16/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X42Y25 SRL16E (Prop_srl16e_CLK_Q) - 1.612 4.654 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][4]_srl16/Q - net (fo=1, routed) 1.039 5.693 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/storage_data_reg[8][4] - SLICE_X41Y22 LUT6 (Prop_lut6_I0_O) 0.124 5.817 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/xpm_fifo_base_inst_i_10/O - net (fo=3, routed) 0.425 6.242 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/xpm_fifo_base_inst_i_10_n_0 - SLICE_X41Y23 LUT4 (Prop_lut4_I0_O) 0.124 6.366 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/xpm_fifo_base_inst_i_2/O - net (fo=7, routed) 0.515 6.881 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_m_valid_out_reg_0 - SLICE_X40Y25 LUT6 (Prop_lut6_I4_O) 0.124 7.005 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_clr_dbc_reg_i_2/O - net (fo=2, routed) 0.429 7.434 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_clr_dbc_reg_reg - SLICE_X40Y26 LUT2 (Prop_lut2_I0_O) 0.124 7.558 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_burst_dbeat_cntr[3]_i_3/O - net (fo=4, routed) 0.459 8.017 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0 - SLICE_X39Y26 LUT6 (Prop_lut6_I5_O) 0.124 8.141 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_burst_dbeat_cntr[3]_i_1/O - net (fo=4, routed) 0.679 8.820 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_burst_dbeat_cntr0 - SLICE_X39Y26 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_burst_dbeat_cntr_reg[2]/R + net (fo=7300, routed) 1.738 3.046 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/m_axi_s2mm_aclk + SLICE_X39Y28 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_mmap_reset_reg_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X39Y28 FDRE (Prop_fdre_C_Q) 0.419 3.465 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_mmap_reset_reg_reg/Q + net (fo=100, routed) 3.741 7.206 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_reset_reg + SLICE_X37Y21 LUT6 (Prop_lut6_I0_O) 0.299 7.505 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_len_reg[4]_i_1/O + net (fo=41, routed) 1.225 8.730 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_cache_reg0 + SLICE_X30Y24 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[26]/R ------------------------------------------------------------------- ------------------- (clock clk_fpga_0 rise edge) @@ -751,30 +719,30 @@ Slack (MET) : 3.580ns (required time - arrival time) PS7_X0Y0 PS7 0.000 10.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 1.101 11.101 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 11.192 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 1.560 12.752 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/m_axi_s2mm_aclk - SLICE_X39Y26 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_burst_dbeat_cntr_reg[2]/C - clock pessimism 0.230 12.983 - clock uncertainty -0.154 12.829 - SLICE_X39Y26 FDRE (Setup_fdre_C_R) -0.429 12.400 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_burst_dbeat_cntr_reg[2] + net (fo=7300, routed) 1.482 12.674 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/m_axi_s2mm_aclk + SLICE_X30Y24 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[26]/C + clock pessimism 0.230 12.905 + clock uncertainty -0.154 12.751 + SLICE_X30Y24 FDRE (Setup_fdre_C_R) -0.524 12.227 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[26] ------------------------------------------------------------------- - required time 12.400 - arrival time -8.820 + required time 12.227 + arrival time -8.730 ------------------------------------------------------------------- - slack 3.580 + slack 3.497 -Slack (MET) : 3.580ns (required time - arrival time) - Source: mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][4]_srl16/CLK - (rising edge-triggered cell SRL16E clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) - Destination: mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_burst_dbeat_cntr_reg[3]/R +Slack (MET) : 3.497ns (required time - arrival time) + Source: mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_mmap_reset_reg_reg/C + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[28]/R (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_fpga_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (clk_fpga_0 rise@10.000ns - clk_fpga_0 rise@0.000ns) - Data Path Delay: 5.778ns (logic 2.232ns (38.629%) route 3.546ns (61.371%)) - Logic Levels: 5 (LUT2=1 LUT4=1 LUT6=3) - Clock Path Skew: -0.059ns (DCD - SCD + CPR) - Destination Clock Delay (DCD): 2.752ns = ( 12.752 - 10.000 ) - Source Clock Delay (SCD): 3.042ns + Data Path Delay: 5.684ns (logic 0.718ns (12.631%) route 4.966ns (87.369%)) + Logic Levels: 1 (LUT6=1) + Clock Path Skew: -0.141ns (DCD - SCD + CPR) + Destination Clock Delay (DCD): 2.674ns = ( 12.674 - 10.000 ) + Source Clock Delay (SCD): 3.046ns Clock Pessimism Removal (CPR): 0.230ns Clock Uncertainty: 0.154ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE Total System Jitter (TSJ): 0.071ns @@ -789,23 +757,14 @@ Slack (MET) : 3.580ns (required time - arrival time) PS7_X0Y0 PS7 0.000 0.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 1.207 1.207 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.101 1.308 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 1.734 3.042 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/m_axi_s2mm_aclk - SLICE_X42Y25 SRL16E r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][4]_srl16/CLK - ------------------------------------------------------------------- ------------------- - SLICE_X42Y25 SRL16E (Prop_srl16e_CLK_Q) - 1.612 4.654 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/INFERRED_GEN.data_reg[15][4]_srl16/Q - net (fo=1, routed) 1.039 5.693 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/storage_data_reg[8][4] - SLICE_X41Y22 LUT6 (Prop_lut6_I0_O) 0.124 5.817 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/xpm_fifo_base_inst_i_10/O - net (fo=3, routed) 0.425 6.242 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/xpm_fifo_base_inst_i_10_n_0 - SLICE_X41Y23 LUT4 (Prop_lut4_I0_O) 0.124 6.366 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_MSSAI_SKID_BUF/xpm_fifo_base_inst_i_2/O - net (fo=7, routed) 0.515 6.881 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_m_valid_out_reg_0 - SLICE_X40Y25 LUT6 (Prop_lut6_I4_O) 0.124 7.005 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_clr_dbc_reg_i_2/O - net (fo=2, routed) 0.429 7.434 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_clr_dbc_reg_reg - SLICE_X40Y26 LUT2 (Prop_lut2_I0_O) 0.124 7.558 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_REALIGNER.I_S2MM_REALIGNER/GEN_INCLUDE_SCATTER.I_S2MM_SCATTER/I_TSTRB_FIFO/USE_SRL_FIFO.I_SYNC_FIFO/I_SRL_FIFO_RBU_F/DYNSHREG_F_I/sig_burst_dbeat_cntr[3]_i_3/O - net (fo=4, routed) 0.459 8.017 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_cmd_stat_rst_user_reg_n_cdc_from_reg__0 - SLICE_X39Y26 LUT6 (Prop_lut6_I5_O) 0.124 8.141 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_burst_dbeat_cntr[3]_i_1/O - net (fo=4, routed) 0.679 8.820 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_burst_dbeat_cntr0 - SLICE_X39Y26 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_burst_dbeat_cntr_reg[3]/R + net (fo=7300, routed) 1.738 3.046 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/m_axi_s2mm_aclk + SLICE_X39Y28 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_mmap_reset_reg_reg/C + ------------------------------------------------------------------- ------------------- + SLICE_X39Y28 FDRE (Prop_fdre_C_Q) 0.419 3.465 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_mmap_reset_reg_reg/Q + net (fo=100, routed) 3.741 7.206 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_reset_reg + SLICE_X37Y21 LUT6 (Prop_lut6_I0_O) 0.299 7.505 r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_len_reg[4]_i_1/O + net (fo=41, routed) 1.225 8.730 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_cache_reg0 + SLICE_X30Y24 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[28]/R ------------------------------------------------------------------- ------------------- (clock clk_fpga_0 rise edge) @@ -813,16 +772,16 @@ Slack (MET) : 3.580ns (required time - arrival time) PS7_X0Y0 PS7 0.000 10.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 1.101 11.101 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.091 11.192 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 1.560 12.752 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/m_axi_s2mm_aclk - SLICE_X39Y26 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_burst_dbeat_cntr_reg[3]/C - clock pessimism 0.230 12.983 - clock uncertainty -0.154 12.829 - SLICE_X39Y26 FDRE (Setup_fdre_C_R) -0.429 12.400 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/sig_burst_dbeat_cntr_reg[3] + net (fo=7300, routed) 1.482 12.674 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/m_axi_s2mm_aclk + SLICE_X30Y24 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[28]/C + clock pessimism 0.230 12.905 + clock uncertainty -0.154 12.751 + SLICE_X30Y24 FDRE (Setup_fdre_C_R) -0.524 12.227 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_INCLUDE_IBTTCC.I_S2MM_MSTR_IBTTCC/sig_xfer_addr_reg_reg[28] ------------------------------------------------------------------- - required time 12.400 - arrival time -8.820 + required time 12.227 + arrival time -8.730 ------------------------------------------------------------------- - slack 3.580 + slack 3.497 @@ -830,20 +789,20 @@ Slack (MET) : 3.580ns (required time - arrival time) Min Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 0.023ns (arrival time - required time) - Source: mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/GEN_S2MM.queue_dout2_new_reg[31]/C - (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) - Destination: mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]/D +Slack (MET) : 0.024ns (arrival time - required time) + Source: mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMA/WADR0 + (rising edge-triggered cell RAMD32 clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_fpga_0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns) - Data Path Delay: 0.309ns (logic 0.148ns (47.942%) route 0.161ns (52.058%)) + Data Path Delay: 0.347ns (logic 0.141ns (40.606%) route 0.206ns (59.394%)) Logic Levels: 0 - Clock Path Skew: 0.260ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.182ns - Source Clock Delay (SCD): 0.888ns - Clock Pessimism Removal (CPR): 0.034ns + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.200ns + Source Clock Delay (SCD): 0.903ns + Clock Pessimism Removal (CPR): 0.284ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -852,12 +811,12 @@ Slack (MET) : 0.023ns (arrival time - required time) PS7_X0Y0 PS7 0.000 0.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 0.315 0.315 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 0.547 0.888 mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/m_axi_sg_aclk - SLICE_X20Y25 FDRE r mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/GEN_S2MM.queue_dout2_new_reg[31]/C + net (fo=7300, routed) 0.562 0.903 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/s_sc_aclk + SLICE_X17Y7 FDRE r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X20Y25 FDRE (Prop_fdre_C_Q) 0.148 1.036 r mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/GEN_S2MM.queue_dout2_new_reg[31]/Q - net (fo=1, routed) 0.161 1.196 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/GEN_S2MM.queue_dout2_new_reg[31][46] - SLICE_X23Y25 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]/D + SLICE_X17Y7 FDRE (Prop_fdre_C_Q) 0.141 1.044 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/Q + net (fo=15, routed) 0.206 1.250 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/ADDRD0 + SLICE_X16Y7 RAMD32 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMA/WADR0 ------------------------------------------------------------------- ------------------- (clock clk_fpga_0 rise edge) @@ -865,30 +824,31 @@ Slack (MET) : 0.023ns (arrival time - required time) PS7_X0Y0 PS7 0.000 0.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 0.341 0.341 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 0.812 1.182 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/m_axi_s2mm_aclk - SLICE_X23Y25 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63]/C - clock pessimism -0.034 1.148 - SLICE_X23Y25 FDRE (Hold_fdre_C_D) 0.025 1.173 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_dout_reg_reg[63] + net (fo=7300, routed) 0.830 1.200 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/WCLK + SLICE_X16Y7 RAMD32 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMA/CLK + clock pessimism -0.284 0.916 + SLICE_X16Y7 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 1.226 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMA ------------------------------------------------------------------- - required time -1.173 - arrival time 1.196 + required time -1.226 + arrival time 1.250 ------------------------------------------------------------------- - slack 0.023 + slack 0.024 -Slack (MET) : 0.025ns (arrival time - required time) - Source: mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/GEN_S2MM.queue_dout2_new_reg[30]/C - (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) - Destination: mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_dout_reg_reg[62]/D +Slack (MET) : 0.024ns (arrival time - required time) + Source: mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMA_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_fpga_0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns) - Data Path Delay: 0.308ns (logic 0.148ns (47.977%) route 0.160ns (52.023%)) + Data Path Delay: 0.347ns (logic 0.141ns (40.606%) route 0.206ns (59.394%)) Logic Levels: 0 - Clock Path Skew: 0.260ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.182ns - Source Clock Delay (SCD): 0.888ns - Clock Pessimism Removal (CPR): 0.034ns + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.200ns + Source Clock Delay (SCD): 0.903ns + Clock Pessimism Removal (CPR): 0.284ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -897,12 +857,12 @@ Slack (MET) : 0.025ns (arrival time - required time) PS7_X0Y0 PS7 0.000 0.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 0.315 0.315 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 0.547 0.888 mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/m_axi_sg_aclk - SLICE_X20Y25 FDRE r mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/GEN_S2MM.queue_dout2_new_reg[30]/C + net (fo=7300, routed) 0.562 0.903 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/s_sc_aclk + SLICE_X17Y7 FDRE r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X20Y25 FDRE (Prop_fdre_C_Q) 0.148 1.036 r mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/GEN_S2MM.queue_dout2_new_reg[30]/Q - net (fo=1, routed) 0.160 1.196 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/GEN_S2MM.queue_dout2_new_reg[31][45] - SLICE_X23Y25 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_dout_reg_reg[62]/D + SLICE_X17Y7 FDRE (Prop_fdre_C_Q) 0.141 1.044 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/Q + net (fo=15, routed) 0.206 1.250 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/ADDRD0 + SLICE_X16Y7 RAMD32 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMA_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock clk_fpga_0 rise edge) @@ -910,30 +870,31 @@ Slack (MET) : 0.025ns (arrival time - required time) PS7_X0Y0 PS7 0.000 0.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 0.341 0.341 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 0.812 1.182 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/m_axi_s2mm_aclk - SLICE_X23Y25 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_dout_reg_reg[62]/C - clock pessimism -0.034 1.148 - SLICE_X23Y25 FDRE (Hold_fdre_C_D) 0.023 1.171 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_dout_reg_reg[62] + net (fo=7300, routed) 0.830 1.200 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/WCLK + SLICE_X16Y7 RAMD32 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMA_D1/CLK + clock pessimism -0.284 0.916 + SLICE_X16Y7 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 1.226 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMA_D1 ------------------------------------------------------------------- - required time -1.171 - arrival time 1.196 + required time -1.226 + arrival time 1.250 ------------------------------------------------------------------- - slack 0.025 + slack 0.024 -Slack (MET) : 0.030ns (arrival time - required time) - Source: mz_petalinux_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/gen_normal_area.gen_node_prog_full.inst_node_prog_full/gen_xpm_memory_fifo.inst_fifo/gen_wr.afull_r_reg_inv/C - (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) - Destination: mz_petalinux_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_axis_packet_slave_normal_area.inst_allow_transfer_late/gen_pipe[1].pipe_reg[1][0]/D +Slack (MET) : 0.024ns (arrival time - required time) + Source: mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMB/WADR0 + (rising edge-triggered cell RAMD32 clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_fpga_0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns) - Data Path Delay: 0.366ns (logic 0.141ns (38.566%) route 0.225ns (61.434%)) + Data Path Delay: 0.347ns (logic 0.141ns (40.606%) route 0.206ns (59.394%)) Logic Levels: 0 - Clock Path Skew: 0.260ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.199ns - Source Clock Delay (SCD): 0.905ns - Clock Pessimism Removal (CPR): 0.034ns + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.200ns + Source Clock Delay (SCD): 0.903ns + Clock Pessimism Removal (CPR): 0.284ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -942,12 +903,12 @@ Slack (MET) : 0.030ns (arrival time - required time) PS7_X0Y0 PS7 0.000 0.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 0.315 0.315 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 0.564 0.905 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/gen_normal_area.gen_node_prog_full.inst_node_prog_full/gen_xpm_memory_fifo.inst_fifo/s_sc_aclk - SLICE_X19Y1 FDRE r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/gen_normal_area.gen_node_prog_full.inst_node_prog_full/gen_xpm_memory_fifo.inst_fifo/gen_wr.afull_r_reg_inv/C + net (fo=7300, routed) 0.562 0.903 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/s_sc_aclk + SLICE_X17Y7 FDRE r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X19Y1 FDRE (Prop_fdre_C_Q) 0.141 1.046 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_mi_handler/gen_normal_area.gen_node_prog_full.inst_node_prog_full/gen_xpm_memory_fifo.inst_fifo/gen_wr.afull_r_reg_inv/Q - net (fo=1, routed) 0.225 1.270 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_axis_packet_slave_normal_area.inst_allow_transfer_late/allow_transfer - SLICE_X23Y1 FDRE r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_axis_packet_slave_normal_area.inst_allow_transfer_late/gen_pipe[1].pipe_reg[1][0]/D + SLICE_X17Y7 FDRE (Prop_fdre_C_Q) 0.141 1.044 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/Q + net (fo=15, routed) 0.206 1.250 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/ADDRD0 + SLICE_X16Y7 RAMD32 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMB/WADR0 ------------------------------------------------------------------- ------------------- (clock clk_fpga_0 rise edge) @@ -955,30 +916,31 @@ Slack (MET) : 0.030ns (arrival time - required time) PS7_X0Y0 PS7 0.000 0.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 0.341 0.341 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 0.829 1.199 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_axis_packet_slave_normal_area.inst_allow_transfer_late/s_sc_aclk - SLICE_X23Y1 FDRE r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_axis_packet_slave_normal_area.inst_allow_transfer_late/gen_pipe[1].pipe_reg[1][0]/C - clock pessimism -0.034 1.165 - SLICE_X23Y1 FDRE (Hold_fdre_C_D) 0.075 1.240 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_w_node/inst/inst_si_handler/gen_si_handler.gen_axis_packet_slave_normal_area.inst_allow_transfer_late/gen_pipe[1].pipe_reg[1][0] + net (fo=7300, routed) 0.830 1.200 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/WCLK + SLICE_X16Y7 RAMD32 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMB/CLK + clock pessimism -0.284 0.916 + SLICE_X16Y7 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 1.226 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMB ------------------------------------------------------------------- - required time -1.240 - arrival time 1.270 + required time -1.226 + arrival time 1.250 ------------------------------------------------------------------- - slack 0.030 + slack 0.024 -Slack (MET) : 0.034ns (arrival time - required time) - Source: mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg[22]/C - (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) - Destination: mz_petalinux_i/ps7_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/gen_no_arbiter.m_amesg_i_reg[23]/D +Slack (MET) : 0.024ns (arrival time - required time) + Source: mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMB_D1/WADR0 + (rising edge-triggered cell RAMD32 clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_fpga_0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns) - Data Path Delay: 0.396ns (logic 0.209ns (52.809%) route 0.187ns (47.191%)) - Logic Levels: 1 (LUT4=1) - Clock Path Skew: 0.270ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.224ns - Source Clock Delay (SCD): 0.925ns - Clock Pessimism Removal (CPR): 0.029ns + Data Path Delay: 0.347ns (logic 0.141ns (40.606%) route 0.206ns (59.394%)) + Logic Levels: 0 + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.200ns + Source Clock Delay (SCD): 0.903ns + Clock Pessimism Removal (CPR): 0.284ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -987,14 +949,12 @@ Slack (MET) : 0.034ns (arrival time - required time) PS7_X0Y0 PS7 0.000 0.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 0.315 0.315 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 0.584 0.925 mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/aclk - SLICE_X4Y51 FDRE r mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg[22]/C + net (fo=7300, routed) 0.562 0.903 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/s_sc_aclk + SLICE_X17Y7 FDRE r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X4Y51 FDRE (Prop_fdre_C_Q) 0.164 1.089 r mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc/inst/gen_axilite.gen_b2s_conv.axilite_b2s/SI_REG/aw.aw_pipe/m_payload_i_reg[22]/Q - net (fo=1, routed) 0.187 1.275 mz_petalinux_i/ps7_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/s_axi_awaddr[22] - SLICE_X3Y48 LUT4 (Prop_lut4_I3_O) 0.045 1.320 r mz_petalinux_i/ps7_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/gen_no_arbiter.m_amesg_i[23]_i_1/O - net (fo=1, routed) 0.000 1.320 mz_petalinux_i/ps7_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/s_amesg[23] - SLICE_X3Y48 FDRE r mz_petalinux_i/ps7_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/gen_no_arbiter.m_amesg_i_reg[23]/D + SLICE_X17Y7 FDRE (Prop_fdre_C_Q) 0.141 1.044 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/Q + net (fo=15, routed) 0.206 1.250 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/ADDRD0 + SLICE_X16Y7 RAMD32 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMB_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock clk_fpga_0 rise edge) @@ -1002,30 +962,31 @@ Slack (MET) : 0.034ns (arrival time - required time) PS7_X0Y0 PS7 0.000 0.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 0.341 0.341 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 0.854 1.224 mz_petalinux_i/ps7_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/aclk - SLICE_X3Y48 FDRE r mz_petalinux_i/ps7_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/gen_no_arbiter.m_amesg_i_reg[23]/C - clock pessimism -0.029 1.195 - SLICE_X3Y48 FDRE (Hold_fdre_C_D) 0.091 1.286 mz_petalinux_i/ps7_0_axi_periph/xbar/inst/gen_sasd.crossbar_sasd_0/addr_arbiter_inst/gen_no_arbiter.m_amesg_i_reg[23] + net (fo=7300, routed) 0.830 1.200 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/WCLK + SLICE_X16Y7 RAMD32 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMB_D1/CLK + clock pessimism -0.284 0.916 + SLICE_X16Y7 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 1.226 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMB_D1 ------------------------------------------------------------------- - required time -1.286 - arrival time 1.320 + required time -1.226 + arrival time 1.250 ------------------------------------------------------------------- - slack 0.034 + slack 0.024 -Slack (MET) : 0.035ns (arrival time - required time) - Source: mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_dout_reg_reg[56]/C - (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) - Destination: mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_MSTR_SCC/sig_cmd_addr_reg_reg[24]/D +Slack (MET) : 0.024ns (arrival time - required time) + Source: mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMC/WADR0 + (rising edge-triggered cell RAMD32 clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_fpga_0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns) - Data Path Delay: 0.371ns (logic 0.164ns (44.217%) route 0.207ns (55.783%)) + Data Path Delay: 0.347ns (logic 0.141ns (40.606%) route 0.206ns (59.394%)) Logic Levels: 0 - Clock Path Skew: 0.259ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.190ns - Source Clock Delay (SCD): 0.897ns - Clock Pessimism Removal (CPR): 0.034ns + Clock Path Skew: 0.013ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.200ns + Source Clock Delay (SCD): 0.903ns + Clock Pessimism Removal (CPR): 0.284ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -1034,12 +995,12 @@ Slack (MET) : 0.035ns (arrival time - required time) PS7_X0Y0 PS7 0.000 0.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 0.315 0.315 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 0.556 0.897 mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/m_axi_sg_aclk - SLICE_X20Y34 FDRE r mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_dout_reg_reg[56]/C + net (fo=7300, routed) 0.562 0.903 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/s_sc_aclk + SLICE_X17Y7 FDRE r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X20Y34 FDRE (Prop_fdre_C_Q) 0.164 1.061 r mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_dout_reg_reg[56]/Q - net (fo=1, routed) 0.207 1.267 mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_MSTR_SCC/Q[20] - SLICE_X22Y32 FDRE r mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_MSTR_SCC/sig_cmd_addr_reg_reg[24]/D + SLICE_X17Y7 FDRE (Prop_fdre_C_Q) 0.141 1.044 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/Q + net (fo=15, routed) 0.206 1.250 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/ADDRD0 + SLICE_X16Y7 RAMD32 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMC/WADR0 ------------------------------------------------------------------- ------------------- (clock clk_fpga_0 rise edge) @@ -1047,29 +1008,30 @@ Slack (MET) : 0.035ns (arrival time - required time) PS7_X0Y0 PS7 0.000 0.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 0.341 0.341 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 0.820 1.190 mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_MSTR_SCC/m_axi_sg_aclk - SLICE_X22Y32 FDRE r mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_MSTR_SCC/sig_cmd_addr_reg_reg[24]/C - clock pessimism -0.034 1.156 - SLICE_X22Y32 FDRE (Hold_fdre_C_D) 0.076 1.232 mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_MSTR_SCC/sig_cmd_addr_reg_reg[24] + net (fo=7300, routed) 0.830 1.200 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/WCLK + SLICE_X16Y7 RAMD32 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMC/CLK + clock pessimism -0.284 0.916 + SLICE_X16Y7 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 1.226 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMC ------------------------------------------------------------------- - required time -1.232 - arrival time 1.267 + required time -1.226 + arrival time 1.250 ------------------------------------------------------------------- - slack 0.035 + slack 0.024 -Slack (MET) : 0.037ns (arrival time - required time) - Source: mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum_reg[bytes][2][userdata][1]/C +Slack (MET) : 0.024ns (arrival time - required time) + Source: mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) - Destination: mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_36_41/RAMA/I + Destination: mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMC_D1/WADR0 (rising edge-triggered cell RAMD32 clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_fpga_0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Data Path Delay: 0.347ns (logic 0.141ns (40.606%) route 0.206ns (59.394%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.201ns - Source Clock Delay (SCD): 0.904ns + Destination Clock Delay (DCD): 1.200ns + Source Clock Delay (SCD): 0.903ns Clock Pessimism Removal (CPR): 0.284ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1079,12 +1041,12 @@ Slack (MET) : 0.037ns (arrival time - required time) PS7_X0Y0 PS7 0.000 0.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 0.315 0.315 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 0.563 0.904 mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/s_sc_aclk - SLICE_X29Y5 FDRE r mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum_reg[bytes][2][userdata][1]/C + net (fo=7300, routed) 0.562 0.903 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/s_sc_aclk + SLICE_X17Y7 FDRE r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X29Y5 FDRE (Prop_fdre_C_Q) 0.141 1.044 r mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum_reg[bytes][2][userdata][1]/Q - net (fo=1, routed) 0.056 1.100 mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_36_41/DIA0 - SLICE_X28Y5 RAMD32 r mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_36_41/RAMA/I + SLICE_X17Y7 FDRE (Prop_fdre_C_Q) 0.141 1.044 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/Q + net (fo=15, routed) 0.206 1.250 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/ADDRD0 + SLICE_X16Y7 RAMD32 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMC_D1/WADR0 ------------------------------------------------------------------- ------------------- (clock clk_fpga_0 rise edge) @@ -1092,30 +1054,30 @@ Slack (MET) : 0.037ns (arrival time - required time) PS7_X0Y0 PS7 0.000 0.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 0.341 0.341 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 0.831 1.201 mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_36_41/WCLK - SLICE_X28Y5 RAMD32 r mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_36_41/RAMA/CLK - clock pessimism -0.284 0.917 - SLICE_X28Y5 RAMD32 (Hold_ramd32_CLK_I) - 0.147 1.064 mz_petalinux_i/axi_smc/inst/s02_nodes/s02_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_36_41/RAMA + net (fo=7300, routed) 0.830 1.200 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/WCLK + SLICE_X16Y7 RAMD32 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMC_D1/CLK + clock pessimism -0.284 0.916 + SLICE_X16Y7 RAMD32 (Hold_ramd32_CLK_WADR0) + 0.310 1.226 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMC_D1 ------------------------------------------------------------------- - required time -1.064 - arrival time 1.100 + required time -1.226 + arrival time 1.250 ------------------------------------------------------------------- - slack 0.037 + slack 0.024 -Slack (MET) : 0.037ns (arrival time - required time) - Source: mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/r_reg/m_vector_i_reg[1079]/C +Slack (MET) : 0.024ns (arrival time - required time) + Source: mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) - Destination: mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_47/RAMA/I - (rising edge-triggered cell RAMD32 clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMD/ADR0 + (rising edge-triggered cell RAMS32 clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_fpga_0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Data Path Delay: 0.347ns (logic 0.141ns (40.606%) route 0.206ns (59.394%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.204ns - Source Clock Delay (SCD): 0.907ns + Destination Clock Delay (DCD): 1.200ns + Source Clock Delay (SCD): 0.903ns Clock Pessimism Removal (CPR): 0.284ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) @@ -1125,12 +1087,12 @@ Slack (MET) : 0.037ns (arrival time - required time) PS7_X0Y0 PS7 0.000 0.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 0.315 0.315 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 0.566 0.907 mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/r_reg/aclk - SLICE_X7Y6 FDRE r mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/r_reg/m_vector_i_reg[1079]/C + net (fo=7300, routed) 0.562 0.903 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/s_sc_aclk + SLICE_X17Y7 FDRE r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X7Y6 FDRE (Prop_fdre_C_Q) 0.141 1.048 r mz_petalinux_i/axi_smc/inst/m00_exit_pipeline/m00_exit/inst/r_reg/m_vector_i_reg[1079]/Q - net (fo=1, routed) 0.056 1.103 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_47/DIA0 - SLICE_X6Y6 RAMD32 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_47/RAMA/I + SLICE_X17Y7 FDRE (Prop_fdre_C_Q) 0.141 1.044 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/Q + net (fo=15, routed) 0.206 1.250 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/ADDRD0 + SLICE_X16Y7 RAMS32 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMD/ADR0 ------------------------------------------------------------------- ------------------- (clock clk_fpga_0 rise edge) @@ -1138,31 +1100,31 @@ Slack (MET) : 0.037ns (arrival time - required time) PS7_X0Y0 PS7 0.000 0.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 0.341 0.341 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 0.834 1.204 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_47/WCLK - SLICE_X6Y6 RAMD32 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_47/RAMA/CLK - clock pessimism -0.284 0.920 - SLICE_X6Y6 RAMD32 (Hold_ramd32_CLK_I) - 0.147 1.067 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_42_47/RAMA + net (fo=7300, routed) 0.830 1.200 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/WCLK + SLICE_X16Y7 RAMS32 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMD/CLK + clock pessimism -0.284 0.916 + SLICE_X16Y7 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 1.226 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMD ------------------------------------------------------------------- - required time -1.066 - arrival time 1.103 + required time -1.226 + arrival time 1.250 ------------------------------------------------------------------- - slack 0.037 + slack 0.024 -Slack (MET) : 0.037ns (arrival time - required time) - Source: mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/aw_reg_stall/m_vector_i_reg[1079]/C +Slack (MET) : 0.024ns (arrival time - required time) + Source: mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) - Destination: mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_114_119/RAMA/I - (rising edge-triggered cell RAMD32 clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMD_D1/ADR0 + (rising edge-triggered cell RAMS32 clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_fpga_0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Data Path Delay: 0.347ns (logic 0.141ns (40.606%) route 0.206ns (59.394%)) Logic Levels: 0 Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.185ns - Source Clock Delay (SCD): 0.891ns - Clock Pessimism Removal (CPR): 0.281ns + Destination Clock Delay (DCD): 1.200ns + Source Clock Delay (SCD): 0.903ns + Clock Pessimism Removal (CPR): 0.284ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -1171,12 +1133,12 @@ Slack (MET) : 0.037ns (arrival time - required time) PS7_X0Y0 PS7 0.000 0.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 0.315 0.315 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 0.550 0.891 mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/aw_reg_stall/aclk - SLICE_X17Y24 FDRE r mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/aw_reg_stall/m_vector_i_reg[1079]/C + net (fo=7300, routed) 0.562 0.903 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/s_sc_aclk + SLICE_X17Y7 FDRE r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/C ------------------------------------------------------------------- ------------------- - SLICE_X17Y24 FDRE (Prop_fdre_C_Q) 0.141 1.031 r mz_petalinux_i/axi_smc/inst/s00_entry_pipeline/s00_mmu/inst/aw_reg_stall/m_vector_i_reg[1079]/Q - net (fo=1, routed) 0.056 1.087 mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_114_119/DIA0 - SLICE_X16Y24 RAMD32 r mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_114_119/RAMA/I + SLICE_X17Y7 FDRE (Prop_fdre_C_Q) 0.141 1.044 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_wr_addra/count_r_reg[0]/Q + net (fo=15, routed) 0.206 1.250 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/ADDRD0 + SLICE_X16Y7 RAMS32 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMD_D1/ADR0 ------------------------------------------------------------------- ------------------- (clock clk_fpga_0 rise edge) @@ -1184,31 +1146,31 @@ Slack (MET) : 0.037ns (arrival time - required time) PS7_X0Y0 PS7 0.000 0.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 0.341 0.341 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 0.815 1.185 mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_114_119/WCLK - SLICE_X16Y24 RAMD32 r mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_114_119/RAMA/CLK - clock pessimism -0.281 0.904 - SLICE_X16Y24 RAMD32 (Hold_ramd32_CLK_I) - 0.147 1.051 mz_petalinux_i/axi_smc/inst/s00_nodes/s00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_114_119/RAMA + net (fo=7300, routed) 0.830 1.200 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/WCLK + SLICE_X16Y7 RAMS32 r mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMD_D1/CLK + clock pessimism -0.284 0.916 + SLICE_X16Y7 RAMS32 (Hold_rams32_CLK_ADR0) + 0.310 1.226 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_r_node/inst/inst_mi_handler/gen_normal_area.gen_fifo_req.inst_fifo_req/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_0_5/RAMD_D1 ------------------------------------------------------------------- - required time -1.051 - arrival time 1.087 + required time -1.226 + arrival time 1.250 ------------------------------------------------------------------- - slack 0.037 + slack 0.024 -Slack (MET) : 0.037ns (arrival time - required time) - Source: mz_petalinux_i/axi_smc/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][84]/C +Slack (MET) : 0.029ns (arrival time - required time) + Source: mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/GEN_S2MM.queue_dout2_new_reg[22]/C + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_dout_reg_reg[54]/D (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) - Destination: mz_petalinux_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_84_89/RAMA/I - (rising edge-triggered cell RAMD32 clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_fpga_0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Data Path Delay: 0.305ns (logic 0.128ns (42.006%) route 0.177ns (57.994%)) Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.203ns - Source Clock Delay (SCD): 0.906ns - Clock Pessimism Removal (CPR): 0.284ns + Clock Path Skew: 0.257ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.182ns + Source Clock Delay (SCD): 0.891ns + Clock Pessimism Removal (CPR): 0.034ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -1217,12 +1179,12 @@ Slack (MET) : 0.037ns (arrival time - required time) PS7_X0Y0 PS7 0.000 0.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 0.315 0.315 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 0.565 0.906 mz_petalinux_i/axi_smc/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/aclk - SLICE_X13Y8 FDRE r mz_petalinux_i/axi_smc/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][84]/C + net (fo=7300, routed) 0.550 0.891 mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/m_axi_sg_aclk + SLICE_X18Y24 FDRE r mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/GEN_S2MM.queue_dout2_new_reg[22]/C ------------------------------------------------------------------- ------------------- - SLICE_X13Y8 FDRE (Prop_fdre_C_Q) 0.141 1.047 r mz_petalinux_i/axi_smc/inst/switchboards/r_switchboard/inst/gen_mi[0].inst_opipe_payld/gen_pipe[1].pipe_reg[1][84]/Q - net (fo=1, routed) 0.056 1.102 mz_petalinux_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_84_89/DIA0 - SLICE_X12Y8 RAMD32 r mz_petalinux_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_84_89/RAMA/I + SLICE_X18Y24 FDRE (Prop_fdre_C_Q) 0.128 1.018 r mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/GEN_S2MM.queue_dout2_new_reg[22]/Q + net (fo=1, routed) 0.177 1.195 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/GEN_S2MM.queue_dout2_new_reg[31][37] + SLICE_X22Y24 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_dout_reg_reg[54]/D ------------------------------------------------------------------- ------------------- (clock clk_fpga_0 rise edge) @@ -1230,31 +1192,30 @@ Slack (MET) : 0.037ns (arrival time - required time) PS7_X0Y0 PS7 0.000 0.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 0.341 0.341 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 0.833 1.203 mz_petalinux_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_84_89/WCLK - SLICE_X12Y8 RAMD32 r mz_petalinux_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_84_89/RAMA/CLK - clock pessimism -0.284 0.919 - SLICE_X12Y8 RAMD32 (Hold_ramd32_CLK_I) - 0.147 1.066 mz_petalinux_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_84_89/RAMA + net (fo=7300, routed) 0.812 1.182 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/m_axi_s2mm_aclk + SLICE_X22Y24 FDRE r mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_dout_reg_reg[54]/C + clock pessimism -0.034 1.148 + SLICE_X22Y24 FDRE (Hold_fdre_C_D) 0.018 1.166 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/I_CMD_STATUS/I_CMD_FIFO/USE_SINGLE_REG.sig_regfifo_dout_reg_reg[54] ------------------------------------------------------------------- - required time -1.066 - arrival time 1.102 + required time -1.166 + arrival time 1.195 ------------------------------------------------------------------- - slack 0.037 + slack 0.029 -Slack (MET) : 0.037ns (arrival time - required time) - Source: mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum_reg[bytes][4][userdata][7]/C +Slack (MET) : 0.030ns (arrival time - required time) + Source: mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/DMA_REG2.data_concat_reg[38]/C + (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) + Destination: mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/GEN_S2MM.reg2_reg[38]/D (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) - Destination: mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_60_65/RAMA/I - (rising edge-triggered cell RAMD32 clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_fpga_0 Path Type: Hold (Min at Fast Process Corner) Requirement: 0.000ns (clk_fpga_0 rise@0.000ns - clk_fpga_0 rise@0.000ns) - Data Path Delay: 0.197ns (logic 0.141ns (71.611%) route 0.056ns (28.389%)) + Data Path Delay: 0.365ns (logic 0.141ns (38.606%) route 0.224ns (61.394%)) Logic Levels: 0 - Clock Path Skew: 0.013ns (DCD - SCD - CPR) - Destination Clock Delay (DCD): 1.199ns - Source Clock Delay (SCD): 0.902ns - Clock Pessimism Removal (CPR): 0.284ns + Clock Path Skew: 0.259ns (DCD - SCD - CPR) + Destination Clock Delay (DCD): 1.187ns + Source Clock Delay (SCD): 0.894ns + Clock Pessimism Removal (CPR): 0.034ns Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- @@ -1263,12 +1224,12 @@ Slack (MET) : 0.037ns (arrival time - required time) PS7_X0Y0 PS7 0.000 0.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 0.315 0.315 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.026 0.341 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 0.561 0.901 mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/s_sc_aclk - SLICE_X29Y10 FDRE r mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum_reg[bytes][4][userdata][7]/C + net (fo=7300, routed) 0.553 0.894 mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/m_axi_sg_aclk + SLICE_X18Y28 FDRE r mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/DMA_REG2.data_concat_reg[38]/C ------------------------------------------------------------------- ------------------- - SLICE_X29Y10 FDRE (Prop_fdre_C_Q) 0.141 1.043 r mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.gen_upsizer.inst_upsizer/gen_w_ch.accum_reg[bytes][4][userdata][7]/Q - net (fo=1, routed) 0.056 1.098 mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_60_65/DIA0 - SLICE_X28Y10 RAMD32 r mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_60_65/RAMA/I + SLICE_X18Y28 FDRE (Prop_fdre_C_Q) 0.141 1.035 r mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/DMA_REG2.data_concat_reg[38]/Q + net (fo=1, routed) 0.224 1.259 mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/D[38] + SLICE_X24Y29 FDRE r mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/GEN_S2MM.reg2_reg[38]/D ------------------------------------------------------------------- ------------------- (clock clk_fpga_0 rise edge) @@ -1276,16 +1237,15 @@ Slack (MET) : 0.037ns (arrival time - required time) PS7_X0Y0 PS7 0.000 0.000 r mz_petalinux_i/processing_system7_0/inst/PS7_i/FCLKCLK[0] net (fo=1, routed) 0.341 0.341 mz_petalinux_i/processing_system7_0/inst/FCLK_CLK_unbuffered[0] BUFGCTRL_X0Y0 BUFG (Prop_bufg_I_O) 0.029 0.370 r mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/O - net (fo=7300, routed) 0.829 1.199 mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_60_65/WCLK - SLICE_X28Y10 RAMD32 r mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_60_65/RAMA/CLK - clock pessimism -0.284 0.915 - SLICE_X28Y10 RAMD32 (Hold_ramd32_CLK_I) - 0.147 1.062 mz_petalinux_i/axi_smc/inst/s00_nodes/s00_w_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_60_65/RAMA + net (fo=7300, routed) 0.817 1.187 mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/m_axi_sg_aclk + SLICE_X24Y29 FDRE r mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/GEN_S2MM.reg2_reg[38]/C + clock pessimism -0.034 1.153 + SLICE_X24Y29 FDRE (Hold_fdre_C_D) 0.076 1.229 mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_FETCH_QUEUE/GEN_QUEUE.FTCH_QUEUE_I/GEN_S2MM.reg2_reg[38] ------------------------------------------------------------------- - required time -1.061 - arrival time 1.098 + required time -1.229 + arrival time 1.259 ------------------------------------------------------------------- - slack 0.037 + slack 0.030 @@ -1303,22 +1263,22 @@ Min Period n/a RAMB18E1/CLKARDCLK n/a 2.576 10.00 Min Period n/a RAMB36E1/CLKARDCLK n/a 2.576 10.000 7.424 RAMB36_X2Y2 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKARDCLK Min Period n/a RAMB36E1/CLKBWRCLK n/a 2.576 10.000 7.424 RAMB36_X2Y2 mz_petalinux_i/axi_dma_0/U0/I_PRMRY_DATAMOVER/GEN_S2MM_FULL.I_S2MM_FULL_WRAPPER/GEN_ENABLE_INDET_BTT_SF.I_INDET_BTT/I_DATA_FIFO/BLK_MEM.I_SYNC_FIFOGEN_FIFO/xpm_fifo_instance.xpm_fifo_sync_inst/xpm_fifo_base_inst/gen_sdpram.xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg/CLKBWRCLK Min Period n/a BUFG/I n/a 2.155 10.000 7.845 BUFGCTRL_X0Y0 mz_petalinux_i/processing_system7_0/inst/buffer_fclk_clk_0.FCLK_CLK_0_BUFG/I -Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X18Y29 mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_ADDR_CNTL/sig_next_addr_reg_reg[12]/C -Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X20Y29 mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_ADDR_CNTL/sig_next_addr_reg_reg[13]/C +Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X20Y29 mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_ADDR_CNTL/sig_next_addr_reg_reg[12]/C +Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X21Y28 mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_ADDR_CNTL/sig_next_addr_reg_reg[13]/C Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X20Y29 mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_ADDR_CNTL/sig_next_addr_reg_reg[14]/C -Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X17Y29 mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_ADDR_CNTL/sig_next_addr_reg_reg[15]/C +Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X17Y28 mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_ADDR_CNTL/sig_next_addr_reg_reg[15]/C Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X20Y29 mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_ADDR_CNTL/sig_next_addr_reg_reg[16]/C -Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X17Y29 mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_ADDR_CNTL/sig_next_addr_reg_reg[17]/C -Low Pulse Width Slow RAMD32/CLK n/a 1.250 5.000 3.750 SLICE_X20Y14 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_90_95/RAMC_D1/CLK -Low Pulse Width Fast RAMD32/CLK n/a 1.250 5.000 3.750 SLICE_X20Y14 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_90_95/RAMC_D1/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 5.000 3.750 SLICE_X20Y14 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_90_95/RAMD/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 5.000 3.750 SLICE_X20Y14 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_90_95/RAMD/CLK -Low Pulse Width Slow RAMS32/CLK n/a 1.250 5.000 3.750 SLICE_X20Y14 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_90_95/RAMD_D1/CLK -Low Pulse Width Fast RAMS32/CLK n/a 1.250 5.000 3.750 SLICE_X20Y14 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_90_95/RAMD_D1/CLK +Min Period n/a FDRE/C n/a 1.000 10.000 9.000 SLICE_X14Y28 mz_petalinux_i/axi_dma_0/U0/GEN_SG_ENGINE.I_SG_ENGINE/I_SG_AXI_DATAMOVER/GEN_S2MM_BASIC.I_S2MM_BASIC_WRAPPER/I_ADDR_CNTL/sig_next_addr_reg_reg[17]/C +Low Pulse Width Slow RAMD32/CLK n/a 1.250 5.000 3.750 SLICE_X20Y17 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_90_95/RAMC_D1/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 5.000 3.750 SLICE_X20Y17 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_90_95/RAMD/CLK +Low Pulse Width Slow RAMS32/CLK n/a 1.250 5.000 3.750 SLICE_X20Y17 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_90_95/RAMD_D1/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 5.000 3.750 SLICE_X16Y13 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_96_101/RAMA/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 5.000 3.750 SLICE_X16Y13 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_96_101/RAMA/CLK Low Pulse Width Slow RAMD32/CLK n/a 1.250 5.000 3.750 SLICE_X16Y13 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_96_101/RAMA_D1/CLK Low Pulse Width Fast RAMD32/CLK n/a 1.250 5.000 3.750 SLICE_X16Y13 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_96_101/RAMA_D1/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 5.000 3.750 SLICE_X16Y13 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_96_101/RAMB/CLK +Low Pulse Width Fast RAMD32/CLK n/a 1.250 5.000 3.750 SLICE_X16Y13 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_96_101/RAMB/CLK +Low Pulse Width Slow RAMD32/CLK n/a 1.250 5.000 3.750 SLICE_X16Y13 mz_petalinux_i/axi_smc/inst/m00_nodes/m00_aw_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_96_101/RAMB_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 5.000 3.750 SLICE_X12Y9 mz_petalinux_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_18_23/RAMA/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 5.000 3.750 SLICE_X12Y9 mz_petalinux_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_18_23/RAMA_D1/CLK High Pulse Width Slow RAMD32/CLK n/a 1.250 5.000 3.750 SLICE_X12Y9 mz_petalinux_i/axi_smc/inst/s00_nodes/s00_r_node/inst/inst_mi_handler/gen_normal_area.inst_fifo_node_payld/gen_xpm_memory_fifo.inst_fifo/gen_mem_rep[0].inst_xpm_memory/xpm_memory_base_inst/gen_wr_a.gen_word_narrow.mem_reg_0_31_18_23/RAMB/CLK @@ -1336,264 +1296,264 @@ High Pulse Width Slow RAMD32/CLK n/a 1.250 5.000 From Clock: To Clock: clk_fpga_0 -Setup : 0 Failing Endpoints, Worst Slack 998.311ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 998.635ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 998.311ns (required time - arrival time) - Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C +Slack (MET) : 998.635ns (required time - arrival time) + Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C (rising edge-triggered cell FDRE) - Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_fpga_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 1000.000ns (MaxDelay Path 1000.000ns) - Data Path Delay: 1.413ns (logic 0.479ns (33.905%) route 0.934ns (66.095%)) + Data Path Delay: 1.260ns (logic 0.457ns (36.279%) route 0.803ns (63.721%)) Logic Levels: 1 (FDRE=1) Timing Exception: MaxDelay Path 1000.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X38Y5 FDRE 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C - SLICE_X38Y5 FDRE (Prop_fdre_C_Q) 0.479 0.479 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q - net (fo=1, routed) 0.934 1.413 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] - SLICE_X37Y3 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + SLICE_X36Y3 FDRE 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C + SLICE_X36Y3 FDRE (Prop_fdre_C_Q) 0.457 0.457 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q + net (fo=1, routed) 0.803 1.260 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[2] + SLICE_X36Y4 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D ------------------------------------------------------------------- ------------------- max delay 1000.000 1000.000 - SLICE_X37Y3 FDRE (Setup_fdre_C_D) -0.276 999.724 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + SLICE_X36Y4 FDRE (Setup_fdre_C_D) -0.105 999.895 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] ------------------------------------------------------------------- - required time 999.724 - arrival time -1.413 + required time 999.895 + arrival time -1.260 ------------------------------------------------------------------- - slack 998.311 + slack 998.635 -Slack (MET) : 998.673ns (required time - arrival time) - Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C +Slack (MET) : 998.823ns (required time - arrival time) + Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C (rising edge-triggered cell FDRE) - Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_fpga_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 1000.000ns (MaxDelay Path 1000.000ns) - Data Path Delay: 1.057ns (logic 0.479ns (45.310%) route 0.578ns (54.690%)) + Data Path Delay: 0.911ns (logic 0.420ns (46.097%) route 0.491ns (53.903%)) Logic Levels: 1 (FDRE=1) Timing Exception: MaxDelay Path 1000.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X38Y5 FDRE 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C - SLICE_X38Y5 FDRE (Prop_fdre_C_Q) 0.479 0.479 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q - net (fo=1, routed) 0.578 1.057 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[3] - SLICE_X36Y5 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + SLICE_X39Y5 FDRE 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/C + SLICE_X39Y5 FDRE (Prop_fdre_C_Q) 0.420 0.420 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.491 0.911 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[1] + SLICE_X37Y4 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D ------------------------------------------------------------------- ------------------- max delay 1000.000 1000.000 - SLICE_X36Y5 FDRE (Setup_fdre_C_D) -0.270 999.730 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + SLICE_X37Y4 FDRE (Setup_fdre_C_D) -0.266 999.734 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][1] ------------------------------------------------------------------- - required time 999.730 - arrival time -1.057 + required time 999.734 + arrival time -0.911 ------------------------------------------------------------------- - slack 998.673 + slack 998.823 -Slack (MET) : 998.760ns (required time - arrival time) - Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C +Slack (MET) : 998.958ns (required time - arrival time) + Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[6]/C (rising edge-triggered cell FDRE) - Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][6]/D (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_fpga_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 1000.000ns (MaxDelay Path 1000.000ns) - Data Path Delay: 1.145ns (logic 0.519ns (45.338%) route 0.626ns (54.662%)) + Data Path Delay: 0.949ns (logic 0.457ns (48.179%) route 0.492ns (51.821%)) Logic Levels: 1 (FDRE=1) Timing Exception: MaxDelay Path 1000.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X38Y5 FDRE 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C - SLICE_X38Y5 FDRE (Prop_fdre_C_Q) 0.519 0.519 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q - net (fo=1, routed) 0.626 1.145 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0] - SLICE_X36Y5 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + SLICE_X36Y3 FDRE 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[6]/C + SLICE_X36Y3 FDRE (Prop_fdre_C_Q) 0.457 0.457 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[6]/Q + net (fo=1, routed) 0.492 0.949 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[6] + SLICE_X36Y2 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][6]/D ------------------------------------------------------------------- ------------------- max delay 1000.000 1000.000 - SLICE_X36Y5 FDRE (Setup_fdre_C_D) -0.095 999.905 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + SLICE_X36Y2 FDRE (Setup_fdre_C_D) -0.093 999.907 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][6] ------------------------------------------------------------------- - required time 999.905 - arrival time -1.145 + required time 999.907 + arrival time -0.949 ------------------------------------------------------------------- - slack 998.760 + slack 998.958 -Slack (MET) : 998.775ns (required time - arrival time) - Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[7]/C +Slack (MET) : 998.968ns (required time - arrival time) + Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[8]/C (rising edge-triggered cell FDRE) - Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][7]/D + Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][8]/D (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_fpga_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 1000.000ns (MaxDelay Path 1000.000ns) - Data Path Delay: 0.960ns (logic 0.420ns (43.739%) route 0.540ns (56.261%)) + Data Path Delay: 0.939ns (logic 0.457ns (48.684%) route 0.482ns (51.316%)) Logic Levels: 1 (FDRE=1) Timing Exception: MaxDelay Path 1000.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X37Y1 FDRE 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[7]/C - SLICE_X37Y1 FDRE (Prop_fdre_C_Q) 0.420 0.420 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[7]/Q - net (fo=1, routed) 0.540 0.960 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[7] - SLICE_X36Y1 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][7]/D + SLICE_X43Y3 FDRE 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[8]/C + SLICE_X43Y3 FDRE (Prop_fdre_C_Q) 0.457 0.457 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[8]/Q + net (fo=1, routed) 0.482 0.939 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[8] + SLICE_X40Y3 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][8]/D ------------------------------------------------------------------- ------------------- max delay 1000.000 1000.000 - SLICE_X36Y1 FDRE (Setup_fdre_C_D) -0.265 999.735 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][7] + SLICE_X40Y3 FDRE (Setup_fdre_C_D) -0.093 999.907 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][8] ------------------------------------------------------------------- - required time 999.735 - arrival time -0.960 + required time 999.907 + arrival time -0.939 ------------------------------------------------------------------- - slack 998.775 + slack 998.968 -Slack (MET) : 999.006ns (required time - arrival time) - Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[6]/C +Slack (MET) : 999.004ns (required time - arrival time) + Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[7]/C (rising edge-triggered cell FDRE) - Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][6]/D + Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][7]/D (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_fpga_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 1000.000ns (MaxDelay Path 1000.000ns) - Data Path Delay: 0.901ns (logic 0.457ns (50.739%) route 0.444ns (49.261%)) + Data Path Delay: 0.729ns (logic 0.420ns (57.651%) route 0.309ns (42.349%)) Logic Levels: 1 (FDRE=1) Timing Exception: MaxDelay Path 1000.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X37Y1 FDRE 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[6]/C - SLICE_X37Y1 FDRE (Prop_fdre_C_Q) 0.457 0.457 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[6]/Q - net (fo=1, routed) 0.444 0.901 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[6] - SLICE_X36Y1 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][6]/D + SLICE_X36Y3 FDRE 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[7]/C + SLICE_X36Y3 FDRE (Prop_fdre_C_Q) 0.420 0.420 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[7]/Q + net (fo=1, routed) 0.309 0.729 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[7] + SLICE_X36Y2 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][7]/D ------------------------------------------------------------------- ------------------- max delay 1000.000 1000.000 - SLICE_X36Y1 FDRE (Setup_fdre_C_D) -0.093 999.907 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][6] + SLICE_X36Y2 FDRE (Setup_fdre_C_D) -0.267 999.733 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][7] ------------------------------------------------------------------- - required time 999.907 - arrival time -0.901 + required time 999.733 + arrival time -0.729 ------------------------------------------------------------------- - slack 999.006 + slack 999.004 -Slack (MET) : 999.011ns (required time - arrival time) - Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[5]/C +Slack (MET) : 999.007ns (required time - arrival time) + Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C (rising edge-triggered cell FDRE) - Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][5]/D + Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_fpga_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 1000.000ns (MaxDelay Path 1000.000ns) - Data Path Delay: 0.719ns (logic 0.420ns (58.432%) route 0.299ns (41.568%)) + Data Path Delay: 0.728ns (logic 0.420ns (57.716%) route 0.308ns (42.284%)) Logic Levels: 1 (FDRE=1) Timing Exception: MaxDelay Path 1000.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X37Y1 FDRE 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[5]/C - SLICE_X37Y1 FDRE (Prop_fdre_C_Q) 0.420 0.420 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[5]/Q - net (fo=1, routed) 0.299 0.719 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[5] - SLICE_X37Y2 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][5]/D + SLICE_X36Y3 FDRE 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/C + SLICE_X36Y3 FDRE (Prop_fdre_C_Q) 0.420 0.420 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.308 0.728 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[3] + SLICE_X36Y4 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D ------------------------------------------------------------------- ------------------- max delay 1000.000 1000.000 - SLICE_X37Y2 FDRE (Setup_fdre_C_D) -0.270 999.730 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][5] + SLICE_X36Y4 FDRE (Setup_fdre_C_D) -0.265 999.735 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][3] ------------------------------------------------------------------- - required time 999.730 - arrival time -0.719 + required time 999.735 + arrival time -0.728 ------------------------------------------------------------------- - slack 999.011 + slack 999.007 -Slack (MET) : 999.094ns (required time - arrival time) - Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[8]/C +Slack (MET) : 999.010ns (required time - arrival time) + Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[5]/C (rising edge-triggered cell FDRE) - Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][8]/D + Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][5]/D (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_fpga_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 1000.000ns (MaxDelay Path 1000.000ns) - Data Path Delay: 0.814ns (logic 0.519ns (63.794%) route 0.295ns (36.206%)) + Data Path Delay: 0.724ns (logic 0.420ns (58.016%) route 0.304ns (41.984%)) Logic Levels: 1 (FDRE=1) Timing Exception: MaxDelay Path 1000.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X38Y5 FDRE 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[8]/C - SLICE_X38Y5 FDRE (Prop_fdre_C_Q) 0.519 0.519 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[8]/Q - net (fo=1, routed) 0.295 0.814 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[8] - SLICE_X36Y5 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][8]/D + SLICE_X36Y3 FDRE 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[5]/C + SLICE_X36Y3 FDRE (Prop_fdre_C_Q) 0.420 0.420 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[5]/Q + net (fo=1, routed) 0.304 0.724 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[5] + SLICE_X36Y2 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][5]/D ------------------------------------------------------------------- ------------------- max delay 1000.000 1000.000 - SLICE_X36Y5 FDRE (Setup_fdre_C_D) -0.092 999.908 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][8] + SLICE_X36Y2 FDRE (Setup_fdre_C_D) -0.266 999.734 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][5] ------------------------------------------------------------------- - required time 999.908 - arrival time -0.814 + required time 999.734 + arrival time -0.724 ------------------------------------------------------------------- - slack 999.094 + slack 999.010 -Slack (MET) : 999.096ns (required time - arrival time) - Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C +Slack (MET) : 999.143ns (required time - arrival time) + Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[4]/C (rising edge-triggered cell FDRE) - Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_fpga_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 1000.000ns (MaxDelay Path 1000.000ns) - Data Path Delay: 0.811ns (logic 0.519ns (64.030%) route 0.292ns (35.970%)) + Data Path Delay: 0.762ns (logic 0.457ns (59.942%) route 0.305ns (40.058%)) Logic Levels: 1 (FDRE=1) Timing Exception: MaxDelay Path 1000.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X38Y5 FDRE 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/C - SLICE_X38Y5 FDRE (Prop_fdre_C_Q) 0.519 0.519 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[2]/Q - net (fo=1, routed) 0.292 0.811 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[2] - SLICE_X36Y5 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + SLICE_X36Y3 FDRE 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[4]/C + SLICE_X36Y3 FDRE (Prop_fdre_C_Q) 0.457 0.457 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[4]/Q + net (fo=1, routed) 0.305 0.762 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[4] + SLICE_X36Y2 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D ------------------------------------------------------------------- ------------------- max delay 1000.000 1000.000 - SLICE_X36Y5 FDRE (Setup_fdre_C_D) -0.093 999.907 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + SLICE_X36Y2 FDRE (Setup_fdre_C_D) -0.095 999.905 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4] ------------------------------------------------------------------- - required time 999.907 - arrival time -0.811 + required time 999.905 + arrival time -0.762 ------------------------------------------------------------------- - slack 999.096 + slack 999.143 -Slack (MET) : 999.097ns (required time - arrival time) - Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[4]/C +Slack (MET) : 999.147ns (required time - arrival time) + Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C (rising edge-triggered cell FDRE) - Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D + Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Path Group: clk_fpga_0 Path Type: Setup (Max at Slow Process Corner) Requirement: 1000.000ns (MaxDelay Path 1000.000ns) - Data Path Delay: 0.808ns (logic 0.457ns (56.576%) route 0.351ns (43.424%)) + Data Path Delay: 0.758ns (logic 0.457ns (60.257%) route 0.301ns (39.743%)) Logic Levels: 1 (FDRE=1) Timing Exception: MaxDelay Path 1000.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X37Y1 FDRE 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[4]/C - SLICE_X37Y1 FDRE (Prop_fdre_C_Q) 0.457 0.457 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[4]/Q - net (fo=1, routed) 0.351 0.808 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[4] - SLICE_X36Y1 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D + SLICE_X39Y5 FDRE 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/C + SLICE_X39Y5 FDRE (Prop_fdre_C_Q) 0.457 0.457 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.301 0.758 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/async_path[0] + SLICE_X37Y4 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D ------------------------------------------------------------------- ------------------- max delay 1000.000 1000.000 - SLICE_X36Y1 FDRE (Setup_fdre_C_D) -0.095 999.905 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][4] + SLICE_X37Y4 FDRE (Setup_fdre_C_D) -0.095 999.905 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/wr_pntr_cdc_inst/dest_graysync_ff_reg[0][0] ------------------------------------------------------------------- required time 999.905 - arrival time -0.808 + arrival time -0.758 ------------------------------------------------------------------- - slack 999.097 + slack 999.147 @@ -1604,237 +1564,237 @@ Path Group: **default** From Clock: clk_fpga_0 To Clock: -Setup : 0 Failing Endpoints, Worst Slack 8.701ns, Total Violation 0.000ns +Setup : 0 Failing Endpoints, Worst Slack 8.364ns, Total Violation 0.000ns Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA --------------------------------------------------------------------------------------------------- Max Delay Paths -------------------------------------------------------------------------------------- -Slack (MET) : 8.701ns (required time - arrival time) - Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C +Slack (MET) : 8.364ns (required time - arrival time) + Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) - Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D Path Group: **default** Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (MaxDelay Path 10.000ns) - Data Path Delay: 1.197ns (logic 0.456ns (38.106%) route 0.741ns (61.894%)) + Data Path Delay: 1.357ns (logic 0.419ns (30.879%) route 0.938ns (69.121%)) Logic Levels: 0 Timing Exception: MaxDelay Path 10.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X40Y3 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C - SLICE_X40Y3 FDRE (Prop_fdre_C_Q) 0.456 0.456 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q - net (fo=1, routed) 0.741 1.197 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[0] - SLICE_X39Y1 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D + SLICE_X36Y4 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C + SLICE_X36Y4 FDRE (Prop_fdre_C_Q) 0.419 0.419 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q + net (fo=1, routed) 0.938 1.357 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[1] + SLICE_X39Y2 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D ------------------------------------------------------------------- ------------------- max delay 10.000 10.000 - SLICE_X39Y1 FDRE (Setup_fdre_C_D) -0.102 9.898 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] + SLICE_X39Y2 FDRE (Setup_fdre_C_D) -0.279 9.721 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1] ------------------------------------------------------------------- - required time 9.898 - arrival time -1.197 + required time 9.721 + arrival time -1.357 ------------------------------------------------------------------- - slack 8.701 + slack 8.364 -Slack (MET) : 8.810ns (required time - arrival time) - Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[7]/C +Slack (MET) : 8.517ns (required time - arrival time) + Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) - Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][7]/D + Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D Path Group: **default** Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (MaxDelay Path 10.000ns) - Data Path Delay: 0.923ns (logic 0.419ns (45.404%) route 0.504ns (54.596%)) + Data Path Delay: 1.206ns (logic 0.419ns (34.739%) route 0.787ns (65.261%)) Logic Levels: 0 Timing Exception: MaxDelay Path 10.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X40Y3 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[7]/C - SLICE_X40Y3 FDRE (Prop_fdre_C_Q) 0.419 0.419 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[7]/Q - net (fo=1, routed) 0.504 0.923 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[7] - SLICE_X40Y2 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][7]/D + SLICE_X40Y3 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C + SLICE_X40Y3 FDRE (Prop_fdre_C_Q) 0.419 0.419 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q + net (fo=1, routed) 0.787 1.206 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[3] + SLICE_X39Y2 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D ------------------------------------------------------------------- ------------------- max delay 10.000 10.000 - SLICE_X40Y2 FDRE (Setup_fdre_C_D) -0.267 9.733 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][7] + SLICE_X39Y2 FDRE (Setup_fdre_C_D) -0.277 9.723 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] ------------------------------------------------------------------- - required time 9.733 - arrival time -0.923 + required time 9.723 + arrival time -1.206 ------------------------------------------------------------------- - slack 8.810 + slack 8.517 -Slack (MET) : 8.825ns (required time - arrival time) - Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C +Slack (MET) : 8.725ns (required time - arrival time) + Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[7]/C (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) - Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][7]/D Path Group: **default** Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (MaxDelay Path 10.000ns) - Data Path Delay: 0.906ns (logic 0.419ns (46.242%) route 0.487ns (53.758%)) + Data Path Delay: 1.011ns (logic 0.419ns (41.449%) route 0.592ns (58.551%)) Logic Levels: 0 Timing Exception: MaxDelay Path 10.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X40Y3 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/C - SLICE_X40Y3 FDRE (Prop_fdre_C_Q) 0.419 0.419 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[1]/Q - net (fo=1, routed) 0.487 0.906 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[1] - SLICE_X41Y3 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1]/D + SLICE_X40Y3 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[7]/C + SLICE_X40Y3 FDRE (Prop_fdre_C_Q) 0.419 0.419 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[7]/Q + net (fo=1, routed) 0.592 1.011 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[7] + SLICE_X40Y0 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][7]/D ------------------------------------------------------------------- ------------------- max delay 10.000 10.000 - SLICE_X41Y3 FDRE (Setup_fdre_C_D) -0.269 9.731 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][1] + SLICE_X40Y0 FDRE (Setup_fdre_C_D) -0.264 9.736 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][7] ------------------------------------------------------------------- - required time 9.731 - arrival time -0.906 + required time 9.736 + arrival time -1.011 ------------------------------------------------------------------- - slack 8.825 + slack 8.725 -Slack (MET) : 8.829ns (required time - arrival time) +Slack (MET) : 8.843ns (required time - arrival time) Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[5]/C (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][5]/D Path Group: **default** Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (MaxDelay Path 10.000ns) - Data Path Delay: 0.907ns (logic 0.419ns (46.203%) route 0.488ns (53.797%)) + Data Path Delay: 0.890ns (logic 0.419ns (47.088%) route 0.471ns (52.912%)) Logic Levels: 0 Timing Exception: MaxDelay Path 10.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X40Y3 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[5]/C - SLICE_X40Y3 FDRE (Prop_fdre_C_Q) 0.419 0.419 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[5]/Q - net (fo=1, routed) 0.488 0.907 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[5] - SLICE_X41Y3 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][5]/D + SLICE_X40Y5 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[5]/C + SLICE_X40Y5 FDRE (Prop_fdre_C_Q) 0.419 0.419 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[5]/Q + net (fo=1, routed) 0.471 0.890 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[5] + SLICE_X39Y5 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][5]/D ------------------------------------------------------------------- ------------------- max delay 10.000 10.000 - SLICE_X41Y3 FDRE (Setup_fdre_C_D) -0.264 9.736 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][5] + SLICE_X39Y5 FDRE (Setup_fdre_C_D) -0.267 9.733 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][5] ------------------------------------------------------------------- - required time 9.736 - arrival time -0.907 + required time 9.733 + arrival time -0.890 ------------------------------------------------------------------- - slack 8.829 + slack 8.843 -Slack (MET) : 8.922ns (required time - arrival time) - Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[4]/C +Slack (MET) : 8.888ns (required time - arrival time) + Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[8]/C (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) - Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D + Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][8]/D Path Group: **default** Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (MaxDelay Path 10.000ns) - Data Path Delay: 0.986ns (logic 0.456ns (46.224%) route 0.530ns (53.776%)) + Data Path Delay: 1.018ns (logic 0.456ns (44.797%) route 0.562ns (55.203%)) Logic Levels: 0 Timing Exception: MaxDelay Path 10.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X40Y3 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[4]/C - SLICE_X40Y3 FDRE (Prop_fdre_C_Q) 0.456 0.456 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[4]/Q - net (fo=1, routed) 0.530 0.986 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[4] - SLICE_X41Y3 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D + SLICE_X41Y2 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[8]/C + SLICE_X41Y2 FDRE (Prop_fdre_C_Q) 0.456 0.456 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[8]/Q + net (fo=1, routed) 0.562 1.018 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[8] + SLICE_X41Y0 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][8]/D ------------------------------------------------------------------- ------------------- max delay 10.000 10.000 - SLICE_X41Y3 FDRE (Setup_fdre_C_D) -0.092 9.908 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4] + SLICE_X41Y0 FDRE (Setup_fdre_C_D) -0.094 9.906 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][8] ------------------------------------------------------------------- - required time 9.908 - arrival time -0.986 + required time 9.906 + arrival time -1.018 ------------------------------------------------------------------- - slack 8.922 + slack 8.888 -Slack (MET) : 8.969ns (required time - arrival time) - Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C +Slack (MET) : 9.002ns (required time - arrival time) + Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[6]/C (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) - Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][6]/D Path Group: **default** Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (MaxDelay Path 10.000ns) - Data Path Delay: 0.767ns (logic 0.419ns (54.607%) route 0.348ns (45.393%)) + Data Path Delay: 0.904ns (logic 0.456ns (50.415%) route 0.448ns (49.585%)) Logic Levels: 0 Timing Exception: MaxDelay Path 10.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X40Y3 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/C - SLICE_X40Y3 FDRE (Prop_fdre_C_Q) 0.419 0.419 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[3]/Q - net (fo=1, routed) 0.348 0.767 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[3] - SLICE_X41Y3 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3]/D + SLICE_X40Y3 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[6]/C + SLICE_X40Y3 FDRE (Prop_fdre_C_Q) 0.456 0.456 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[6]/Q + net (fo=1, routed) 0.448 0.904 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[6] + SLICE_X40Y0 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][6]/D ------------------------------------------------------------------- ------------------- max delay 10.000 10.000 - SLICE_X41Y3 FDRE (Setup_fdre_C_D) -0.264 9.736 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][3] + SLICE_X40Y0 FDRE (Setup_fdre_C_D) -0.094 9.906 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][6] ------------------------------------------------------------------- - required time 9.736 - arrival time -0.767 + required time 9.906 + arrival time -0.904 ------------------------------------------------------------------- - slack 8.969 + slack 9.002 Slack (MET) : 9.002ns (required time - arrival time) - Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[6]/C + Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[4]/C (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) - Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][6]/D + Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D Path Group: **default** Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (MaxDelay Path 10.000ns) - Data Path Delay: 0.904ns (logic 0.456ns (50.428%) route 0.448ns (49.572%)) + Data Path Delay: 0.904ns (logic 0.456ns (50.435%) route 0.448ns (49.565%)) Logic Levels: 0 Timing Exception: MaxDelay Path 10.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X40Y3 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[6]/C - SLICE_X40Y3 FDRE (Prop_fdre_C_Q) 0.456 0.456 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[6]/Q - net (fo=1, routed) 0.448 0.904 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[6] - SLICE_X40Y2 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][6]/D + SLICE_X40Y5 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[4]/C + SLICE_X40Y5 FDRE (Prop_fdre_C_Q) 0.456 0.456 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[4]/Q + net (fo=1, routed) 0.448 0.904 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[4] + SLICE_X39Y5 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4]/D ------------------------------------------------------------------- ------------------- max delay 10.000 10.000 - SLICE_X40Y2 FDRE (Setup_fdre_C_D) -0.094 9.906 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][6] + SLICE_X39Y5 FDRE (Setup_fdre_C_D) -0.094 9.906 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][4] ------------------------------------------------------------------- required time 9.906 arrival time -0.904 ------------------------------------------------------------------- slack 9.002 -Slack (MET) : 9.083ns (required time - arrival time) - Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[8]/C +Slack (MET) : 9.143ns (required time - arrival time) + Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) - Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][8]/D + Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D Path Group: **default** Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (MaxDelay Path 10.000ns) - Data Path Delay: 0.825ns (logic 0.518ns (62.776%) route 0.307ns (37.224%)) + Data Path Delay: 0.763ns (logic 0.456ns (59.754%) route 0.307ns (40.246%)) Logic Levels: 0 Timing Exception: MaxDelay Path 10.000ns -datapath_only Location Delay type Incr(ns) Path(ns) Netlist Resource(s) ------------------------------------------------------------------- ------------------- - SLICE_X38Y2 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[8]/C - SLICE_X38Y2 FDRE (Prop_fdre_C_Q) 0.518 0.518 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[8]/Q - net (fo=1, routed) 0.307 0.825 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[8] - SLICE_X40Y2 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][8]/D + SLICE_X36Y4 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/C + SLICE_X36Y4 FDRE (Prop_fdre_C_Q) 0.456 0.456 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[0]/Q + net (fo=1, routed) 0.307 0.763 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[0] + SLICE_X36Y3 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0]/D ------------------------------------------------------------------- ------------------- max delay 10.000 10.000 - SLICE_X40Y2 FDRE (Setup_fdre_C_D) -0.092 9.908 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][8] + SLICE_X36Y3 FDRE (Setup_fdre_C_D) -0.094 9.906 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][0] ------------------------------------------------------------------- - required time 9.908 - arrival time -0.825 + required time 9.906 + arrival time -0.763 ------------------------------------------------------------------- - slack 9.083 + slack 9.143 -Slack (MET) : 9.110ns (required time - arrival time) +Slack (MET) : 9.143ns (required time - arrival time) Source: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C (rising edge-triggered cell FDRE clocked by clk_fpga_0 {rise@0.000ns fall@5.000ns period=10.000ns}) Destination: mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D Path Group: **default** Path Type: Setup (Max at Slow Process Corner) Requirement: 10.000ns (MaxDelay Path 10.000ns) - Data Path Delay: 0.867ns (logic 0.456ns (52.595%) route 0.411ns (47.405%)) + Data Path Delay: 0.763ns (logic 0.456ns (59.754%) route 0.307ns (40.246%)) Logic Levels: 0 Timing Exception: MaxDelay Path 10.000ns -datapath_only @@ -1842,17 +1802,17 @@ Slack (MET) : 9.110ns (required time - arrival time) ------------------------------------------------------------------- ------------------- SLICE_X40Y3 0.000 0.000 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/C SLICE_X40Y3 FDRE (Prop_fdre_C_Q) 0.456 0.456 r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/src_gray_ff_reg[2]/Q - net (fo=1, routed) 0.411 0.867 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[2] - SLICE_X42Y3 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D + net (fo=1, routed) 0.307 0.763 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/async_path[2] + SLICE_X40Y2 FDRE r mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2]/D ------------------------------------------------------------------- ------------------- max delay 10.000 10.000 - SLICE_X42Y3 FDRE (Setup_fdre_C_D) -0.023 9.977 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2] + SLICE_X40Y2 FDRE (Setup_fdre_C_D) -0.094 9.906 mz_petalinux_i/LTC2271_SampleGetter_0/inst/adc_store/U0/inst_fifo_gen/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gcx.clkx/rd_pntr_cdc_inst/dest_graysync_ff_reg[0][2] ------------------------------------------------------------------- - required time 9.977 - arrival time -0.867 + required time 9.906 + arrival time -0.763 ------------------------------------------------------------------- - slack 9.110 + slack 9.143 diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_timing_summary_routed.rpx b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_timing_summary_routed.rpx index 65232b65f6e7c34f361442e2220e1edf996ea69e..e5aec5fb58ed31e56b0333a8d4b01f79393843c7 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_timing_summary_routed.rpx and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_timing_summary_routed.rpx differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_utilization_placed.pb b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_utilization_placed.pb index b4d608b3762a3ed23361b3f5df93839e9184c605..3faf0e5a22dcf5f6205626640cf34fd8fb39efc2 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_utilization_placed.pb and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_utilization_placed.pb differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_utilization_placed.rpt b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_utilization_placed.rpt index cc57060959ccc695fa07d3b58f4c8b94aa3b9b6d..720ed96a4d5bc9c0101750368db9efaf20bce174 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_utilization_placed.rpt +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/mz_petalinux_wrapper_utilization_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 -| Date : Sat Oct 19 01:14:11 2019 +| Date : Sun Oct 20 22:46:15 2019 | Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS | Command : report_utilization -file mz_petalinux_wrapper_utilization_placed.rpt -pb mz_petalinux_wrapper_utilization_placed.pb | Design : mz_petalinux_wrapper @@ -31,8 +31,8 @@ Table of Contents +----------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +----------------------------+------+-------+-----------+-------+ -| Slice LUTs | 4861 | 0 | 17600 | 27.62 | -| LUT as Logic | 4114 | 0 | 17600 | 23.38 | +| Slice LUTs | 4863 | 0 | 17600 | 27.63 | +| LUT as Logic | 4116 | 0 | 17600 | 23.39 | | LUT as Memory | 747 | 0 | 6000 | 12.45 | | LUT as Distributed RAM | 588 | 0 | | | | LUT as Shift Register | 159 | 0 | | | @@ -69,13 +69,13 @@ Table of Contents +-------------------------------------------+------+-------+-----------+-------+ | Site Type | Used | Fixed | Available | Util% | +-------------------------------------------+------+-------+-----------+-------+ -| Slice | 1868 | 0 | 4400 | 42.45 | -| SLICEL | 1217 | 0 | | | -| SLICEM | 651 | 0 | | | -| LUT as Logic | 4114 | 0 | 17600 | 23.38 | +| Slice | 1861 | 0 | 4400 | 42.30 | +| SLICEL | 1208 | 0 | | | +| SLICEM | 653 | 0 | | | +| LUT as Logic | 4116 | 0 | 17600 | 23.39 | | using O5 output only | 0 | | | | -| using O6 output only | 3388 | | | | -| using O5 and O6 | 726 | | | | +| using O6 output only | 3392 | | | | +| using O5 and O6 | 724 | | | | | LUT as Memory | 747 | 0 | 6000 | 12.45 | | LUT as Distributed RAM | 588 | 0 | | | | using O5 output only | 0 | | | | @@ -85,10 +85,10 @@ Table of Contents | using O5 output only | 2 | | | | | using O6 output only | 113 | | | | | using O5 and O6 | 44 | | | | -| LUT Flip Flop Pairs | 2835 | 0 | 17600 | 16.11 | +| LUT Flip Flop Pairs | 2847 | 0 | 17600 | 16.18 | | fully used LUT-FF pairs | 511 | | | | -| LUT-FF pairs with one unused LUT output | 2164 | | | | -| LUT-FF pairs with one unused Flip Flop | 2130 | | | | +| LUT-FF pairs with one unused LUT output | 2177 | | | | +| LUT-FF pairs with one unused Flip Flop | 2140 | | | | | Unique Control Sets | 309 | | | | +-------------------------------------------+------+-------+-----------+-------+ * Note: Review the Control Sets Report for more information regarding control sets. diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/opt_design.pb b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/opt_design.pb index 97667863675bd920b90cf6ee90453b6891f80b79..ef34d92669c543f531b0af1885372558ade7a0bd 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/opt_design.pb and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/opt_design.pb differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/place_design.pb b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/place_design.pb index c02236872fc34371f9ac5a62f0470f59e86225a2..0d435dd04dd638d7c9478a1dfe053f9896b7d4b5 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/place_design.pb and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/place_design.pb differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/route_design.pb b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/route_design.pb index ddf92115815313ae03fc88fda71f9648dc3133f9..c567d18ba6198c24d7ba2105d8b29ae5d35a5714 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/route_design.pb and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/route_design.pb differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/usage_statistics_webtalk.html b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/usage_statistics_webtalk.html index 5514ab8b5713e30039a2266694b5748dc8c1ebe8..6fae4cc7fedad7f480e02e44143904dc095ad341 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/usage_statistics_webtalk.html +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/usage_statistics_webtalk.html @@ -4,11 +4,11 @@ software_version_and_target_device betaFALSE build_version2086221 - date_generatedSat Oct 19 01:17:52 2019 + date_generatedSun Oct 20 22:49:51 2019 os_platformLIN64 product_versionVivado v2017.4 (64-bit) project_id594ce0be76a74b3089360976e4eb0bcd - project_iteration15 + project_iteration20 random_idfbf06e6de5635bd0847c136115d1b984 registration_id211009216_1777520236_210640867_900 route_designTRUE @@ -21,7 +21,7 @@ - + @@ -37,10 +37,10 @@ - + - - + + @@ -57,126 +57,129 @@ - - - + + + + - - + + - - - + + + - - - + + + - - + + - - - + + + - - + + - - + + - - + + - - + + - - - + + + - - + + - - + + - - + + - - - - + + + + + - + - - - + + + - + - + - + - + - + - + - + - + - + - + - - - + + + - - - - + + + + + - - - - + + + + - - + + - - + + - - - - - - + + + + + +
user_environment
cpu_nameIntel(R) Core(TM) i5-7600 CPU @ 3.50GHzcpu_speed3977.813 MHzcpu_speed3924.340 MHz
os_nameUbuntu os_releaseUbuntu 18.04.3 LTS
system_ram16.000 GBaddresstreetablepanel_address_tree_table=1
advclkconfigtreetablepanel_tree_table=31 applyrsbmultiautomationdialog_checkbox_tree=3basedialog_cancel=33basedialog_cancel=36 basedialog_no=1
basedialog_ok=95basedialog_yes=4
basedialog_ok=124basedialog_yes=7 basereporttab_rerun=14 clkconfigmainpanel_tabbed_pane=5
clkconfigtreetablepanel_clk_config_tree_table=20customizecoredialog_documentation=1
customizecoredialog_ip_location=3 expruntreepanel_exp_run_tree_table=11filesetpanel_file_set_panel_tree=197flownavigatortreepanel_flow_navigator_tree=108
gensettingtreetablepanel_gen_setting_tree_table=25filesetpanel_file_set_panel_tree=214flownavigatortreepanel_flow_navigator_tree=110
gensettingtreetablepanel_gen_setting_tree_table=29 gettingstartedview_create_new_project=1 gettingstartedview_open_project=2 gictreetablepanel_gic_tree_table=11
hardwaretreepanel_hardware_tree_table=4hcodeeditor_search_text_combo_box=1 iostandardcombobox_choose_io_standard=1 ipstatussectionpanel_upgrade_selected=17ipstatustablepanel_ip_status_table=1
ipstatustablepanel_more_info=1
ipstatustablepanel_ip_status_table=1ipstatustablepanel_more_info=1 logmonitor_monitor=2 logpanel_log_navigator=7mainmenumgr_edit=2
mainmenumgr_export=43mainmenumgr_file=72
mainmenumgr_edit=2mainmenumgr_export=59mainmenumgr_file=102 mainmenumgr_flow=2mainmenumgr_import=2
mainmenumgr_open_recent_file=33mainmenumgr_open_recent_project=35
mainmenumgr_import=2mainmenumgr_open_recent_file=48mainmenumgr_open_recent_project=49 mainmenumgr_settings=1mainmenumgr_tools=12
mainmenumgr_view=2
mainmenumgr_tools=12mainmenumgr_view=2 mainmenumgr_window=4maintoolbarmgr_run=26mainwinmenumgr_layout=4
mainwinmenumgr_load=1maintoolbarmgr_run=32
mainwinmenumgr_layout=4mainwinmenumgr_load=1 mainwintoolbarmgr_select_or_save_window_layout=2 messagewithoptiondialog_dont_show_this_dialog_again=2mioconfigtreetablepanel_mio_config_tree_table=25
miotablepagepanel_mio_table=7
mioconfigtreetablepanel_mio_config_tree_table=40miotablepagepanel_mio_table=19 msgtreepanel_message_view_tree=8 multifilechooser_add_directories=1newexporthardwaredialog_include_bitstream=10
packagetreepanel_package_tree_panel=2
newexporthardwaredialog_include_bitstream=12packagetreepanel_package_tree_panel=2 pacommandnames_add_sources=2 pacommandnames_auto_connect_ports=17pacommandnames_auto_connect_target=2
pacommandnames_auto_update_hier=8
pacommandnames_auto_connect_target=2pacommandnames_auto_update_hier=8 pacommandnames_bitstream_settings=1 pacommandnames_close_project=3pacommandnames_create_port_interface=2
pacommandnames_create_top_hdl=6
pacommandnames_create_port_interface=2pacommandnames_create_top_hdl=6 pacommandnames_export_bd_tcl=1pacommandnames_export_hardware=18pacommandnames_generate_composite_file=1
pacommandnames_launch_hardware=7pacommandnames_export_hardware=24
pacommandnames_generate_composite_file=1pacommandnames_launch_hardware=16 pacommandnames_make_active_cnsset=1 pacommandnames_open_ip_location=1pacommandnames_project_summary=1
pacommandnames_regenerate_layout=13
pacommandnames_project_summary=1pacommandnames_regenerate_layout=19 pacommandnames_reload_rtl_design=1 pacommandnames_reset_runs=2pacommandnames_run_bitgen=10
pacommandnames_run_implementation=16
pacommandnames_run_bitgen=12pacommandnames_run_implementation=22 pacommandnames_run_synthesis=4 pacommandnames_save_design=11pacommandnames_save_rsb_design=4
pacommandnames_schematic=2
pacommandnames_save_rsb_design=5pacommandnames_schematic=2 pacommandnames_select_area=2 pacommandnames_set_target_ucf=1pacommandnames_validate_rsb_design=8
pacommandnames_view_run_log=1pacommandnames_zoom_fit=7pacommandnames_zoom_out=1
pacommandnames_validate_rsb_design=10pacommandnames_view_run_log=1pacommandnames_zoom_fit=11pacommandnames_zoom_in=5
pacommandnames_zoom_out=6 partchooser_board_vendor_chooser=1
partchooser_boards=1partchooser_boards=1 partchooser_parts=1paviews_address_editor=2paviews_code=12
paviews_dashboard=1
paviews_address_editor=2paviews_code=15paviews_dashboard=1 paviews_schematic=3planaheadtab_refresh_ip_catalog=10
planaheadtab_refresh_ip_catalog=10 portmenu_configure_io_ports=1
programdebugtab_open_target=2programdebugtab_open_target=2 programdebugtab_program_device=2programdebugtab_refresh_device=1
programdebugtab_refresh_device=1 programfpgadialog_program=1
progressdialog_background=1progressdialog_background=2 projectnamechooser_choose_project_location=1projectnamechooser_project_name=1
projectnamechooser_project_name=1 projectsummaryutilizationpanel_project_summary_utilization_panel_tabbed=2
projecttab_close_design=2projecttab_close_design=2 projecttab_reload=2rdicommands_delete=2
rdicommands_delete=2 rdicommands_properties=5
removesourcesdialog_also_delete=1removesourcesdialog_also_delete=1 rsbapplyautomationbar_run_connection_automation=6rsbexternalinterfaceproppanels_name=2
rsbexternalinterfaceproppanels_name=2 rsbexternalportproppanels_name=11
rungadget_show_error=2rungadget_show_error=2 saveprojectutils_cancel=1saveprojectutils_dont_save=1saveprojectutils_save=5
selectmenu_highlight=18
saveprojectutils_dont_save=1saveprojectutils_save=10selectmenu_highlight=18 selectmenu_mark=1settingsdialog_options_tree=1signaltreepanel_signal_tree_table=138
simpleoutputproductdialog_close_dialog_unsaved_changes_will=2simpleoutputproductdialog_generate_output_products_immediately=15
settingsdialog_options_tree=1settingsdialog_project_tree=10signaltreepanel_signal_tree_table=144simpleoutputproductdialog_close_dialog_unsaved_changes_will=2
simpleoutputproductdialog_generate_output_products_immediately=15 srcmenu_ip_hierarchy=7statemonitor_reset_run=1
syntheticagettingstartedview_recent_projects=25syntheticastatemonitor_cancel=2systembuildermenu_add_ip=2statemonitor_reset_run=2syntheticagettingstartedview_recent_projects=27
syntheticastatemonitor_cancel=3systembuildermenu_add_ip=3 systembuildermenu_add_module=1
systembuildermenu_create_port=1systembuildermenu_start_connection_mode=1systembuildermenu_create_port=1
systembuildermenu_start_connection_mode=1 systembuilderview_add_ip=8 systembuilderview_expand_collapse=10
systembuilderview_optimize_routing=6systembuilderview_orientation=1systembuilderview_optimize_routing=8
systembuilderview_orientation=1 systemtab_report_ip_status=2 systemtab_show_ip_status=2
systemtreeview_system_tree=23taskbanner_close=14tclconsoleview_copy=1tclconsoleview_tcl_console_code_editor=3
tclobjecttreetable_treetable=2touchpointsurveydialog_no=1systemtreeview_system_tree=23
taskbanner_close=15tclconsoleview_copy=2tclconsoleview_tcl_console_code_editor=11tclobjecttreetable_treetable=2
touchpointsurveydialog_no=1
@@ -187,49 +190,52 @@ - - + + + + - + - - - - - + + + + + - + - + - - - + + + - - - + + + - - - + + + - - - - - + + + + + - - - - - + + + + + +
java_command_handlers
coreview=1 createportinterface=2 createtophdl=6customizersbblock=26
editdelete=17customizersbblock=36
editcopy=1editdelete=28editpaste=1 editproperties=5exportrsbtclscript=1
exportrsbtclscript=1 launchprogramfpga=2
managecompositetargets=4newexporthardware=18newhardwaredashboard=1newlaunchhardware=7
newproject=1managecompositetargets=4newexporthardware=24
newhardwaredashboard=1newlaunchhardware=16newproject=1 openblockdesign=12openhardwaremanager=3
openhardwaremanager=3 openiplocationhandler=1
openproject=2openproject=2 projectsummary=1refreshdevice=1regeneratersblayout=13
reloaddesign=1
refreshdevice=1regeneratersblayout=19reloaddesign=1 reportipstatus=2runbitgen=19runimplementation=20
runschematic=3
runbitgen=24runimplementation=26runschematic=3 runsynthesis=4savedesign=11saversbdesign=7
settargetconstrfile=1
savedesign=11saversbdesign=8settargetconstrfile=1 showview=7toggleselectareamode=2toolssettings=4
upgradeip=17validatersbdesign=8viewlayoutcmd=3
toggleselectareamode=2toolssettings=5upgradeip=17validatersbdesign=10
viewlayoutcmd=3 viewtaskimplementation=4
viewtaskprojectmanager=9viewtaskrtlanalysis=16viewtasksynthesis=2zoomfit=7
zoomout=1viewtaskprojectmanager=9viewtaskrtlanalysis=17
viewtasksynthesis=2zoomfit=11zoomin=5zoomout=6
- +
other_data
batchmode=2guimode=587guimode=589
@@ -960,18 +966,18 @@ - - - - - - - - - - - - + + + + + + + + + + + + @@ -2653,8 +2659,8 @@ - - + + @@ -2671,8 +2677,8 @@ - - + + @@ -2683,8 +2689,8 @@ - - + + @@ -2692,21 +2698,21 @@ - - - + + + - - + + - - + + - + - + @@ -2759,7 +2765,7 @@
project_data
pcw_single_qspi_data_mode=x4 pcw_smc_peripheral_clksrc=IO PLL
pcw_smc_peripheral_freqmhz=100pcw_spi0_grp_ss0_enable=1pcw_spi0_grp_ss0_io=EMIOpcw_spi0_grp_ss1_enable=1
pcw_spi0_grp_ss1_io=EMIOpcw_spi0_grp_ss2_enable=1pcw_spi0_grp_ss2_io=EMIOpcw_spi0_peripheral_enable=1
pcw_spi0_spi0_io=EMIOpcw_spi1_grp_ss0_enable=0pcw_spi1_grp_ss1_enable=0pcw_spi1_grp_ss2_enable=0
pcw_spi1_peripheral_enable=0pcw_spi0_grp_ss0_enable=0pcw_spi0_grp_ss1_enable=0pcw_spi0_grp_ss2_enable=0
pcw_spi0_peripheral_enable=0pcw_spi1_grp_ss0_enable=1pcw_spi1_grp_ss0_io=EMIOpcw_spi1_grp_ss1_enable=1
pcw_spi1_grp_ss1_io=EMIOpcw_spi1_grp_ss2_enable=1pcw_spi1_grp_ss2_io=EMIOpcw_spi1_peripheral_enable=1
pcw_spi1_spi1_io=EMIO pcw_spi_peripheral_clksrc=IO PLL pcw_spi_peripheral_freqmhz=166.666666 pcw_tpiu_peripheral_clksrc=Externallut_as_distributed_ram_used=588 lut_as_logic_available=17600 lut_as_logic_fixed=0
lut_as_logic_used=4114lut_as_logic_util_percentage=23.38
lut_as_logic_used=4116lut_as_logic_util_percentage=23.39 lut_as_memory_available=6000 lut_as_memory_fixed=0
lut_as_memory_used=747register_as_latch_util_percentage=0.00
slice_luts_available=17600 slice_luts_fixed=0slice_luts_used=4861slice_luts_util_percentage=27.62slice_luts_used=4863slice_luts_util_percentage=27.63
slice_registers_available=35200 slice_registers_fixed=0 slice_registers_used=6018lut_as_distributed_ram_used=588
lut_as_logic_available=17600 lut_as_logic_fixed=0lut_as_logic_used=4114lut_as_logic_util_percentage=23.38lut_as_logic_used=4116lut_as_logic_util_percentage=23.39
lut_as_memory_available=6000 lut_as_memory_fixed=0 lut_as_memory_used=747
lut_as_shift_register_fixed=0 lut_as_shift_register_used=159 lut_ff_pairs_with_one_unused_flip_flop_fixed=159lut_ff_pairs_with_one_unused_flip_flop_used=2130
lut_ff_pairs_with_one_unused_lut_output_fixed=2130lut_ff_pairs_with_one_unused_lut_output_used=2164lut_ff_pairs_with_one_unused_flip_flop_used=2140
lut_ff_pairs_with_one_unused_lut_output_fixed=2140lut_ff_pairs_with_one_unused_lut_output_used=2177 lut_flip_flop_pairs_available=17600 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=2835lut_flip_flop_pairs_util_percentage=16.11
lut_flip_flop_pairs_used=2847lut_flip_flop_pairs_util_percentage=16.18 slice_available=4400 slice_fixed=0
slice_used=1868slice_util_percentage=42.45
slice_used=1861slice_util_percentage=42.30 slicel_fixed=0slicel_used=1217slicel_used=1208
slicem_fixed=0slicem_used=651slicem_used=653 unique_control_sets_used=309 using_o5_and_o6_fixed=309
using_o5_and_o6_used=44
- + @@ -2769,7 +2775,7 @@ - + @@ -2830,10 +2836,10 @@
usage
actual_expansions=4044072
actual_expansions=3990558 bogomips=7008 bram18=1 bram36=1ctrls=309
dsp=0 effort=2estimated_expansions=6534426estimated_expansions=6521268 ff=6018
global_clocks=1 high_fanout_nets=3
- + - - + +
usage
elapsed=00:00:29s
elapsed=00:00:28s hls_ip=0memory_gain=446.809MBmemory_peak=1687.023MBmemory_gain=446.816MBmemory_peak=1689.422MB

diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/usage_statistics_webtalk.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/usage_statistics_webtalk.xml index 8a362d78a452e590402e419182c2fbbe8dce14d4..2c96a94eee247527b38435f1efb4d1f4d9dd2f80 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/usage_statistics_webtalk.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/usage_statistics_webtalk.xml @@ -1,14 +1,14 @@ - +
- + - + @@ -20,7 +20,7 @@
- + @@ -604,18 +604,18 @@ - - - - - - - - - - - - + + + + + + + + + + + + @@ -2195,10 +2195,10 @@ - - - - + + + + @@ -2212,13 +2212,13 @@ - - - + + + - - + + @@ -2231,18 +2231,18 @@ - - + + - - + + - + - + @@ -2288,7 +2288,7 @@
- + @@ -2298,7 +2298,7 @@ - + @@ -2352,10 +2352,10 @@
- + - - + +
@@ -2424,10 +2424,10 @@ - + - - + + @@ -2444,13 +2444,14 @@ - - - + + + + @@ -2458,26 +2459,26 @@ - - + + - - + + - + - - + + - + @@ -2488,32 +2489,33 @@ - + - + - + - - + + - + - + - - + + + - + @@ -2522,7 +2524,7 @@ - + @@ -2537,31 +2539,32 @@ - + - + + - - - - + + + + - + - - - + + +
@@ -2573,15 +2576,17 @@ - - + + + + - + - + @@ -2589,32 +2594,33 @@ - + - - + + - + - + - + - + - - + + +
- +
diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/vivado.pb b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/vivado.pb index e67198d522171b417d03d6a5c7ec88afbe2bf3a5..547dea6dac18924af2b8a3ef47d5fe9b5b021f59 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/vivado.pb and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/vivado.pb differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/write_bitstream.pb b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/write_bitstream.pb index 8c5ccbe25fb3ffe33a08f8b59474f85a39fff47e..0da46c5f995f3f35ce898417a1036af91628fa0c 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/write_bitstream.pb and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/impl_1/write_bitstream.pb differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_LTC2271_SampleGetter_0_0_synth_1/gen_run.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_LTC2271_SampleGetter_0_0_synth_1/gen_run.xml index ba3d8c097e574626644e271cb5a6e7b644bb9bbb..348396af9b31b2b8c901d42953ea6817cb76123d 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_LTC2271_SampleGetter_0_0_synth_1/gen_run.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_LTC2271_SampleGetter_0_0_synth_1/gen_run.xml @@ -1,9 +1,9 @@ + - diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/.vivado.begin.rst b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/.vivado.begin.rst index ce13dfe290d6adffc2d950cefd1e9564718f02eb..dcc1ed068a0172ff2ea0c338fcea04245fd5338a 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/.vivado.begin.rst +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/gen_run.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/gen_run.xml index 7a997a7dcc04d4c24b94188086dcf41ba9b75d6a..1c22694753f13b0879575e1c58f13564c679db13 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/gen_run.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/gen_run.xml @@ -1,11 +1,14 @@ - + + + - - - + + + + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/mz_petalinux_processing_system7_0_0.dcp b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/mz_petalinux_processing_system7_0_0.dcp index c42fdd0eb6c3c28ca444f27086e0630429027184..4d55cf74a10af523bd15ed38fce11357ba24b6a3 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/mz_petalinux_processing_system7_0_0.dcp and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/mz_petalinux_processing_system7_0_0.dcp differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/mz_petalinux_processing_system7_0_0.tcl b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/mz_petalinux_processing_system7_0_0.tcl index 72f3da3b5d5d9588416413a456b47b8a05d41d86..fca962079b81a10bcb39f687c14d472a764817e2 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/mz_petalinux_processing_system7_0_0.tcl +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/mz_petalinux_processing_system7_0_0.tcl @@ -31,9 +31,9 @@ set_property default_lib xil_defaultlib [current_project] set_property target_language Verilog [current_project] set_property board_part em.avnet.com:microzed_7010:part0:1.1 [current_project] set_property ip_repo_paths { - /home/nats/project/VNAV2_Zynq/IP/VNA_Config/VNA_Config_1.0 /home/nats/project/VNAV2_Zynq/IP/VNA_Config/VNA_Config_1.0 /home/nats/project/VNAV2_Zynq/IP/VNA_PeripheralConfig/VNA_PeripheralConfig_1.0 + /home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter } [current_project] set_property ip_output_repo /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/mz_petalinux_processing_system7_0_0.vds b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/mz_petalinux_processing_system7_0_0.vds index bb8b213aa1e610dfbfdcd3784b9edf3a5e00b294..9ac3cc89b3dcd57f51eb6c861531e815cc91c855 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/mz_petalinux_processing_system7_0_0.vds +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/mz_petalinux_processing_system7_0_0.vds @@ -2,8 +2,8 @@ # Vivado v2017.4 (64-bit) # SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017 # IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 -# Start of session at: Fri Jul 12 14:20:07 2019 -# Process ID: 28198 +# Start of session at: Sun Oct 20 22:43:03 2019 +# Process ID: 6057 # Current directory: /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1 # Command line: vivado -log mz_petalinux_processing_system7_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source mz_petalinux_processing_system7_0_0.tcl # Log file: /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/mz_petalinux_processing_system7_0_0.vds @@ -15,9 +15,9 @@ Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010' INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 28295 +INFO: Helper process launched with PID 6064 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1316.621 ; gain = 87.996 ; free physical = 7501 ; free virtual = 11931 +Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1316.156 ; gain = 86.996 ; free physical = 3857 ; free virtual = 10495 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'mz_petalinux_processing_system7_0_0' [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/synth/mz_petalinux_processing_system7_0_0.v:60] INFO: [Synth 8-638] synthesizing module 'processing_system7_v5_5_processing_system7' [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v:162] @@ -168,7 +168,7 @@ WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has un WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_ATID[1] WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port FTMD_TRACEIN_ATID[0] --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1358.152 ; gain = 129.527 ; free physical = 7511 ; free virtual = 11943 +Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1358.688 ; gain = 129.527 ; free physical = 3865 ; free virtual = 10505 --------------------------------------------------------------------------------- Report Check Netlist: @@ -178,7 +178,7 @@ Report Check Netlist: |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:09 . Memory (MB): peak = 1358.152 ; gain = 129.527 ; free physical = 7509 ; free virtual = 11942 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1358.688 ; gain = 129.527 ; free physical = 3866 ; free virtual = 10506 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z010clg400-1 INFO: [Project 1-570] Preparing netlist for logic optimization @@ -196,26 +196,26 @@ Completed Processing XDC Constraints INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1608.598 ; gain = 0.000 ; free physical = 6793 ; free virtual = 11295 +Constraint Validation Runtime : Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1609.125 ; gain = 0.000 ; free physical = 3546 ; free virtual = 10233 --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:38 . Memory (MB): peak = 1608.598 ; gain = 379.973 ; free physical = 6841 ; free virtual = 11352 +Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:32 . Memory (MB): peak = 1609.125 ; gain = 379.965 ; free physical = 3617 ; free virtual = 10306 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z010clg400-1 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:38 . Memory (MB): peak = 1608.598 ; gain = 379.973 ; free physical = 6841 ; free virtual = 11352 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:32 . Memory (MB): peak = 1609.125 ; gain = 379.965 ; free physical = 3617 ; free virtual = 10306 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- Applied set_property DONT_TOUCH = true for inst. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/dont_touch.xdc, line 9). --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:22 ; elapsed = 00:00:38 . Memory (MB): peak = 1608.598 ; gain = 379.973 ; free physical = 6839 ; free virtual = 11349 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:21 ; elapsed = 00:00:32 . Memory (MB): peak = 1609.125 ; gain = 379.965 ; free physical = 3618 ; free virtual = 10307 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:22 ; elapsed = 00:00:38 . Memory (MB): peak = 1608.598 ; gain = 379.973 ; free physical = 6825 ; free virtual = 11336 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:22 ; elapsed = 00:00:32 . Memory (MB): peak = 1609.125 ; gain = 379.965 ; free physical = 3610 ; free virtual = 10299 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -272,7 +272,7 @@ WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has un WARNING: [Synth 8-3331] design processing_system7_v5_5_processing_system7 has unconnected port ENET1_GMII_RXD[3] INFO: [Common 17-14] Message 'Synth 8-3331' appears 100 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings. --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:39 . Memory (MB): peak = 1608.598 ; gain = 379.973 ; free physical = 6809 ; free virtual = 11319 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:33 . Memory (MB): peak = 1625.141 ; gain = 395.980 ; free physical = 3600 ; free virtual = 10290 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -284,13 +284,13 @@ Report RTL Partitions: Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:28 ; elapsed = 00:00:47 . Memory (MB): peak = 1813.598 ; gain = 584.973 ; free physical = 6419 ; free virtual = 10933 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:27 ; elapsed = 00:00:40 . Memory (MB): peak = 1814.141 ; gain = 584.980 ; free physical = 3339 ; free virtual = 10039 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:28 ; elapsed = 00:00:47 . Memory (MB): peak = 1833.605 ; gain = 604.980 ; free physical = 6421 ; free virtual = 10938 +Finished Timing Optimization : Time (s): cpu = 00:00:27 ; elapsed = 00:00:40 . Memory (MB): peak = 1834.148 ; gain = 604.988 ; free physical = 3326 ; free virtual = 10026 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -302,7 +302,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:29 ; elapsed = 00:00:48 . Memory (MB): peak = 1841.613 ; gain = 612.988 ; free physical = 6887 ; free virtual = 11406 +Finished Technology Mapping : Time (s): cpu = 00:00:28 ; elapsed = 00:00:41 . Memory (MB): peak = 1842.156 ; gain = 612.996 ; free physical = 3325 ; free virtual = 10026 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -326,7 +326,7 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:29 ; elapsed = 00:00:50 . Memory (MB): peak = 1841.613 ; gain = 612.988 ; free physical = 6916 ; free virtual = 11437 +Finished IO Insertion : Time (s): cpu = 00:00:29 ; elapsed = 00:00:42 . Memory (MB): peak = 1842.156 ; gain = 612.996 ; free physical = 3320 ; free virtual = 10021 --------------------------------------------------------------------------------- Report Check Netlist: @@ -339,7 +339,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:29 ; elapsed = 00:00:50 . Memory (MB): peak = 1841.613 ; gain = 612.988 ; free physical = 6916 ; free virtual = 11437 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:29 ; elapsed = 00:00:42 . Memory (MB): peak = 1842.156 ; gain = 612.996 ; free physical = 3320 ; free virtual = 10021 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -351,25 +351,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:30 ; elapsed = 00:00:50 . Memory (MB): peak = 1841.613 ; gain = 612.988 ; free physical = 6916 ; free virtual = 11437 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:29 ; elapsed = 00:00:42 . Memory (MB): peak = 1842.156 ; gain = 612.996 ; free physical = 3320 ; free virtual = 10021 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:30 ; elapsed = 00:00:50 . Memory (MB): peak = 1841.613 ; gain = 612.988 ; free physical = 6916 ; free virtual = 11437 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:29 ; elapsed = 00:00:42 . Memory (MB): peak = 1842.156 ; gain = 612.996 ; free physical = 3320 ; free virtual = 10021 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:30 ; elapsed = 00:00:50 . Memory (MB): peak = 1841.613 ; gain = 612.988 ; free physical = 6916 ; free virtual = 11437 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:29 ; elapsed = 00:00:42 . Memory (MB): peak = 1842.156 ; gain = 612.996 ; free physical = 3320 ; free virtual = 10021 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:30 ; elapsed = 00:00:50 . Memory (MB): peak = 1841.613 ; gain = 612.988 ; free physical = 6916 ; free virtual = 11437 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:29 ; elapsed = 00:00:42 . Memory (MB): peak = 1842.156 ; gain = 612.996 ; free physical = 3320 ; free virtual = 10021 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -399,11 +399,11 @@ Report Instance Areas: |2 | inst |processing_system7_v5_5_processing_system7 | 244| +------+---------+-------------------------------------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:30 ; elapsed = 00:00:50 . Memory (MB): peak = 1841.613 ; gain = 612.988 ; free physical = 6916 ; free virtual = 11437 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:29 ; elapsed = 00:00:42 . Memory (MB): peak = 1842.156 ; gain = 612.996 ; free physical = 3320 ; free virtual = 10021 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 79 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:21 ; elapsed = 00:00:28 . Memory (MB): peak = 1841.613 ; gain = 362.543 ; free physical = 6974 ; free virtual = 11494 -Synthesis Optimization Complete : Time (s): cpu = 00:00:30 ; elapsed = 00:00:50 . Memory (MB): peak = 1841.621 ; gain = 612.988 ; free physical = 6981 ; free virtual = 11502 +Synthesis Optimization Runtime : Time (s): cpu = 00:00:21 ; elapsed = 00:00:24 . Memory (MB): peak = 1842.156 ; gain = 362.559 ; free physical = 3377 ; free virtual = 10078 +Synthesis Optimization Complete : Time (s): cpu = 00:00:29 ; elapsed = 00:00:42 . Memory (MB): peak = 1842.164 ; gain = 612.996 ; free physical = 3377 ; free virtual = 10078 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). @@ -413,10 +413,10 @@ No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis 23 Infos, 101 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:31 ; elapsed = 00:00:51 . Memory (MB): peak = 1843.613 ; gain = 639.816 ; free physical = 7101 ; free virtual = 11622 +synth_design: Time (s): cpu = 00:00:30 ; elapsed = 00:00:43 . Memory (MB): peak = 1845.156 ; gain = 640.824 ; free physical = 3512 ; free virtual = 10213 INFO: [Common 17-1381] The checkpoint '/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/mz_petalinux_processing_system7_0_0.dcp' has been generated. INFO: [Coretcl 2-1482] Added synthesis output to IP cache for IP /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0.xci INFO: [Common 17-1381] The checkpoint '/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/mz_petalinux_processing_system7_0_0.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file mz_petalinux_processing_system7_0_0_utilization_synth.rpt -pb mz_petalinux_processing_system7_0_0_utilization_synth.pb -report_utilization: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.12 . Memory (MB): peak = 1843.613 ; gain = 0.000 ; free physical = 7092 ; free virtual = 11614 -INFO: [Common 17-206] Exiting Vivado at Fri Jul 12 14:21:10 2019... +report_utilization: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.11 . Memory (MB): peak = 1845.156 ; gain = 0.000 ; free physical = 3510 ; free virtual = 10213 +INFO: [Common 17-206] Exiting Vivado at Sun Oct 20 22:43:58 2019... diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/mz_petalinux_processing_system7_0_0_utilization_synth.rpt b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/mz_petalinux_processing_system7_0_0_utilization_synth.rpt index 24836e714f298054bccec4461c10b454367a6a2d..7ef0c53c359bebb8f8bdacb4fda5afdcf7dbd61e 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/mz_petalinux_processing_system7_0_0_utilization_synth.rpt +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/mz_petalinux_processing_system7_0_0_utilization_synth.rpt @@ -1,8 +1,8 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 -| Date : Fri Jul 12 14:21:10 2019 -| Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.2 LTS +| Date : Sun Oct 20 22:43:57 2019 +| Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS | Command : report_utilization -file mz_petalinux_processing_system7_0_0_utilization_synth.rpt -pb mz_petalinux_processing_system7_0_0_utilization_synth.pb | Design : mz_petalinux_processing_system7_0_0 | Device : 7z010clg400-1 diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/vivado.pb b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/vivado.pb index 460ce849de31c3ae3898dd5c436f4d206234f0d6..4365fec481c27d2506cea66584dc2ddd51611909 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/vivado.pb and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_processing_system7_0_0_synth_1/vivado.pb differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1/.vivado.begin.rst b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1/.vivado.begin.rst index 3d4fc6346d2b810934a8c60944e8fcfde053450c..a22570dd99b2707010e3f2d03d3ed412b3c61038 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1/.vivado.begin.rst +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1/gen_run.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1/gen_run.xml index 0672641a7330b42c3ac5dc6a9eeac83489fd836f..517eef458970399a694a54a4b7f73012c6551aa0 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1/gen_run.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1/gen_run.xml @@ -1,17 +1,19 @@ - - - - - + + + + + + + @@ -22,9 +24,11 @@ + + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1/mz_petalinux_xlconstant_0_0.dcp b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1/mz_petalinux_xlconstant_0_0.dcp index c213d3c303ecbb823b3b5959176435a8ab7653d0..6bcb731f02b318d4112e5c698eddefda8e2b5f28 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1/mz_petalinux_xlconstant_0_0.dcp and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1/mz_petalinux_xlconstant_0_0.dcp differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1/mz_petalinux_xlconstant_0_0.tcl b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1/mz_petalinux_xlconstant_0_0.tcl index 3660acd659f10982c1540150b05807f6da219dbe..70dbda9202acf705394f0b4abe18f709cfe08a7b 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1/mz_petalinux_xlconstant_0_0.tcl +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1/mz_petalinux_xlconstant_0_0.tcl @@ -16,6 +16,8 @@ proc create_report { reportName command } { send_msg_id runtcl-5 warning "$msg" } } +set_msg_config -id {Synth 8-256} -limit 10000 +set_msg_config -id {Synth 8-638} -limit 10000 set_param project.vivado.isBlockSynthRun true set_msg_config -msgmgr_mode ooc_run create_project -in_memory -part xc7z010clg400-1 @@ -31,9 +33,9 @@ set_property default_lib xil_defaultlib [current_project] set_property target_language Verilog [current_project] set_property board_part em.avnet.com:microzed_7010:part0:1.1 [current_project] set_property ip_repo_paths { - /home/nats/project/VNAV2_Zynq/IP/VNA_Config/VNA_Config_1.0 /home/nats/project/VNAV2_Zynq/IP/VNA_Config/VNA_Config_1.0 /home/nats/project/VNAV2_Zynq/IP/VNA_PeripheralConfig/VNA_PeripheralConfig_1.0 + /home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter } [current_project] set_property ip_output_repo /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/ip [current_project] set_property ip_cache_permissions {read write} [current_project] diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1/mz_petalinux_xlconstant_0_0.vds b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1/mz_petalinux_xlconstant_0_0.vds index 1431674e52a4b72efd4fac8c2d74cabb38c72638..c8c3f2ebf786d378631ed1466cd5fe400c310f42 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1/mz_petalinux_xlconstant_0_0.vds +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1/mz_petalinux_xlconstant_0_0.vds @@ -2,8 +2,8 @@ # Vivado v2017.4 (64-bit) # SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017 # IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 -# Start of session at: Fri Jul 12 14:21:06 2019 -# Process ID: 28452 +# Start of session at: Sun Oct 20 15:59:12 2019 +# Process ID: 31806 # Current directory: /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1 # Command line: vivado -log mz_petalinux_xlconstant_0_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source mz_petalinux_xlconstant_0_0.tcl # Log file: /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1/mz_petalinux_xlconstant_0_0.vds @@ -15,9 +15,9 @@ Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010' INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 28486 +INFO: Helper process launched with PID 31811 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1305.723 ; gain = 86.996 ; free physical = 7206 ; free virtual = 11732 +Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1304.727 ; gain = 87.996 ; free physical = 2650 ; free virtual = 11846 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'mz_petalinux_xlconstant_0_0' [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/synth/mz_petalinux_xlconstant_0_0.v:57] INFO: [Synth 8-638] synthesizing module 'xlconstant_v1_1_3_xlconstant' [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ipshared/0750/hdl/xlconstant_v1_1_vl_rfs.v:23] @@ -26,7 +26,7 @@ INFO: [Synth 8-638] synthesizing module 'xlconstant_v1_1_3_xlconstant' [/home/na INFO: [Synth 8-256] done synthesizing module 'xlconstant_v1_1_3_xlconstant' (1#1) [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ipshared/0750/hdl/xlconstant_v1_1_vl_rfs.v:23] INFO: [Synth 8-256] done synthesizing module 'mz_petalinux_xlconstant_0_0' (2#1) [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/synth/mz_petalinux_xlconstant_0_0.v:57] --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1347.254 ; gain = 128.527 ; free physical = 7199 ; free virtual = 11725 +Finished RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1346.258 ; gain = 129.527 ; free physical = 2665 ; free virtual = 11861 --------------------------------------------------------------------------------- Report Check Netlist: @@ -36,7 +36,7 @@ Report Check Netlist: |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1347.254 ; gain = 128.527 ; free physical = 7209 ; free virtual = 11735 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1346.258 ; gain = 129.527 ; free physical = 2665 ; free virtual = 11861 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z010clg400-1 INFO: [Project 1-570] Preparing netlist for logic optimization @@ -48,25 +48,25 @@ Completed Processing XDC Constraints INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1569.879 ; gain = 0.000 ; free physical = 8060 ; free virtual = 12589 +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1568.875 ; gain = 0.000 ; free physical = 2424 ; free virtual = 11620 --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:20 ; elapsed = 00:00:32 . Memory (MB): peak = 1569.879 ; gain = 351.152 ; free physical = 8100 ; free virtual = 12629 +Finished Constraint Validation : Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 1568.875 ; gain = 352.145 ; free physical = 2488 ; free virtual = 11685 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z010clg400-1 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:20 ; elapsed = 00:00:32 . Memory (MB): peak = 1569.879 ; gain = 351.152 ; free physical = 8100 ; free virtual = 12629 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 1568.875 ; gain = 352.145 ; free physical = 2488 ; free virtual = 11685 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:32 . Memory (MB): peak = 1569.879 ; gain = 351.152 ; free physical = 8102 ; free virtual = 12631 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 1568.875 ; gain = 352.145 ; free physical = 2490 ; free virtual = 11687 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:20 ; elapsed = 00:00:32 . Memory (MB): peak = 1569.879 ; gain = 351.152 ; free physical = 8102 ; free virtual = 12631 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 1568.875 ; gain = 352.145 ; free physical = 2490 ; free virtual = 11687 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -103,7 +103,7 @@ Start Cross Boundary and Area Optimization WARNING: [Synth 8-3330] design mz_petalinux_xlconstant_0_0 has an empty top module INFO: [Synth 8-3917] design mz_petalinux_xlconstant_0_0 has port dout[0] driven by constant 1 --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:33 . Memory (MB): peak = 1569.879 ; gain = 351.152 ; free physical = 8099 ; free virtual = 12629 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:20 ; elapsed = 00:00:30 . Memory (MB): peak = 1568.875 ; gain = 352.145 ; free physical = 2490 ; free virtual = 11686 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -115,13 +115,13 @@ Report RTL Partitions: Start Applying XDC Timing Constraints --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:25 ; elapsed = 00:00:40 . Memory (MB): peak = 1620.879 ; gain = 402.152 ; free physical = 7965 ; free virtual = 12497 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:25 ; elapsed = 00:00:37 . Memory (MB): peak = 1618.875 ; gain = 402.145 ; free physical = 2348 ; free virtual = 11543 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:25 ; elapsed = 00:00:40 . Memory (MB): peak = 1620.879 ; gain = 402.152 ; free physical = 7965 ; free virtual = 12497 +Finished Timing Optimization : Time (s): cpu = 00:00:25 ; elapsed = 00:00:37 . Memory (MB): peak = 1618.875 ; gain = 402.145 ; free physical = 2348 ; free virtual = 11543 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -133,7 +133,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:25 ; elapsed = 00:00:40 . Memory (MB): peak = 1630.895 ; gain = 412.168 ; free physical = 7964 ; free virtual = 12497 +Finished Technology Mapping : Time (s): cpu = 00:00:25 ; elapsed = 00:00:37 . Memory (MB): peak = 1628.898 ; gain = 412.168 ; free physical = 2347 ; free virtual = 11542 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -157,7 +157,7 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:26 ; elapsed = 00:00:40 . Memory (MB): peak = 1630.895 ; gain = 412.168 ; free physical = 7965 ; free virtual = 12497 +Finished IO Insertion : Time (s): cpu = 00:00:26 ; elapsed = 00:00:38 . Memory (MB): peak = 1628.898 ; gain = 412.168 ; free physical = 2346 ; free virtual = 11542 --------------------------------------------------------------------------------- Report Check Netlist: @@ -170,7 +170,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:26 ; elapsed = 00:00:40 . Memory (MB): peak = 1630.895 ; gain = 412.168 ; free physical = 7965 ; free virtual = 12497 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:26 ; elapsed = 00:00:38 . Memory (MB): peak = 1628.898 ; gain = 412.168 ; free physical = 2346 ; free virtual = 11542 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -182,25 +182,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:26 ; elapsed = 00:00:40 . Memory (MB): peak = 1630.895 ; gain = 412.168 ; free physical = 7965 ; free virtual = 12497 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:26 ; elapsed = 00:00:38 . Memory (MB): peak = 1628.898 ; gain = 412.168 ; free physical = 2346 ; free virtual = 11542 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:26 ; elapsed = 00:00:40 . Memory (MB): peak = 1630.895 ; gain = 412.168 ; free physical = 7965 ; free virtual = 12497 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:26 ; elapsed = 00:00:38 . Memory (MB): peak = 1628.898 ; gain = 412.168 ; free physical = 2346 ; free virtual = 11542 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:26 ; elapsed = 00:00:40 . Memory (MB): peak = 1630.895 ; gain = 412.168 ; free physical = 7965 ; free virtual = 12497 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:26 ; elapsed = 00:00:38 . Memory (MB): peak = 1628.898 ; gain = 412.168 ; free physical = 2346 ; free virtual = 11542 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:26 ; elapsed = 00:00:40 . Memory (MB): peak = 1630.895 ; gain = 412.168 ; free physical = 7965 ; free virtual = 12497 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:26 ; elapsed = 00:00:38 . Memory (MB): peak = 1628.898 ; gain = 412.168 ; free physical = 2346 ; free virtual = 11542 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -225,11 +225,11 @@ Report Instance Areas: |1 |top | | 0| +------+---------+-------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:26 ; elapsed = 00:00:40 . Memory (MB): peak = 1630.895 ; gain = 412.168 ; free physical = 7965 ; free virtual = 12497 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:26 ; elapsed = 00:00:38 . Memory (MB): peak = 1628.898 ; gain = 412.168 ; free physical = 2346 ; free virtual = 11542 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 1 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:22 . Memory (MB): peak = 1630.895 ; gain = 189.543 ; free physical = 8023 ; free virtual = 12555 -Synthesis Optimization Complete : Time (s): cpu = 00:00:26 ; elapsed = 00:00:40 . Memory (MB): peak = 1630.902 ; gain = 412.168 ; free physical = 8023 ; free virtual = 12555 +Synthesis Optimization Runtime : Time (s): cpu = 00:00:18 ; elapsed = 00:00:21 . Memory (MB): peak = 1628.898 ; gain = 189.551 ; free physical = 2403 ; free virtual = 11599 +Synthesis Optimization Complete : Time (s): cpu = 00:00:26 ; elapsed = 00:00:38 . Memory (MB): peak = 1628.906 ; gain = 412.168 ; free physical = 2403 ; free virtual = 11599 INFO: [Project 1-571] Translating synthesized netlist INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). @@ -239,10 +239,10 @@ No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis 14 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:41 . Memory (MB): peak = 1639.895 ; gain = 445.996 ; free physical = 8005 ; free virtual = 12538 +synth_design: Time (s): cpu = 00:00:27 ; elapsed = 00:00:38 . Memory (MB): peak = 1638.898 ; gain = 446.996 ; free physical = 2386 ; free virtual = 11582 INFO: [Common 17-1381] The checkpoint '/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1/mz_petalinux_xlconstant_0_0.dcp' has been generated. INFO: [Coretcl 2-1482] Added synthesis output to IP cache for IP /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0.xci INFO: [Common 17-1381] The checkpoint '/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1/mz_petalinux_xlconstant_0_0.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file mz_petalinux_xlconstant_0_0_utilization_synth.rpt -pb mz_petalinux_xlconstant_0_0_utilization_synth.pb -report_utilization: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1639.895 ; gain = 0.000 ; free physical = 8005 ; free virtual = 12538 -INFO: [Common 17-206] Exiting Vivado at Fri Jul 12 14:21:57 2019... +report_utilization: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.09 . Memory (MB): peak = 1638.898 ; gain = 0.000 ; free physical = 2393 ; free virtual = 11589 +INFO: [Common 17-206] Exiting Vivado at Sun Oct 20 15:59:59 2019... diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1/mz_petalinux_xlconstant_0_0_utilization_synth.rpt b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1/mz_petalinux_xlconstant_0_0_utilization_synth.rpt index 5fa6f49d35ec619e018ceb36469992a6e9ace9ab..2988698c43a786e64c3fda3a32a0a65254da96ce 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1/mz_petalinux_xlconstant_0_0_utilization_synth.rpt +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1/mz_petalinux_xlconstant_0_0_utilization_synth.rpt @@ -1,8 +1,8 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 -| Date : Fri Jul 12 14:21:57 2019 -| Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.2 LTS +| Date : Sun Oct 20 15:59:59 2019 +| Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS | Command : report_utilization -file mz_petalinux_xlconstant_0_0_utilization_synth.rpt -pb mz_petalinux_xlconstant_0_0_utilization_synth.pb | Design : mz_petalinux_xlconstant_0_0 | Device : 7z010clg400-1 diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1/vivado.pb b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1/vivado.pb index 630ca3d89a502f6d7725a9ffcb953656b6c7817b..1827fc8882508fb72f300d15b3026f440df1b62a 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1/vivado.pb and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/mz_petalinux_xlconstant_0_0_synth_1/vivado.pb differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/mz_petalinux_wrapper_propImpl.xdc b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/mz_petalinux_wrapper_propImpl.xdc index afec5fcd42c549fd592c027a20d783bc98b4fdaf..dc231be21ee507545b319e8a42c9f457a377f697 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/mz_petalinux_wrapper_propImpl.xdc +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/mz_petalinux_wrapper_propImpl.xdc @@ -1,87 +1,41 @@ set_property SRC_FILE_INFO {cfile:/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/constrs_1/new/pins.xdc rfile:../../../mz_petalinux.srcs/constrs_1/new/pins.xdc id:1} [current_design] -set_property src_info {type:XDC file:1 line:1 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN R19 [get_ports ADC_SCK] -set_property src_info {type:XDC file:1 line:2 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS25 [get_ports ADC_SCK] -set_property src_info {type:XDC file:1 line:3 export:INPUT save:INPUT read:READ} [current_design] -set_property SLEW FAST [get_ports ADC_SCK] -set_property src_info {type:XDC file:1 line:5 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN T19 [get_ports ADC_MOSI] set_property src_info {type:XDC file:1 line:6 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS25 [get_ports ADC_MOSI] -set_property src_info {type:XDC file:1 line:7 export:INPUT save:INPUT read:READ} [current_design] -set_property SLEW FAST [get_ports ADC_MOSI] -set_property src_info {type:XDC file:1 line:10 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN N17 [get_ports ADC2_CS] -set_property src_info {type:XDC file:1 line:11 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS25 [get_ports ADC2_CS] -set_property src_info {type:XDC file:1 line:12 export:INPUT save:INPUT read:READ} [current_design] -set_property SLEW FAST [get_ports ADC2_CS] -set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design] -set_property SLEW FAST [get_ports ADC1_CS] -set_property src_info {type:XDC file:1 line:14 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN T12 [get_ports ADC1_CS] -set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS25 [get_ports ADC1_CS] -set_property src_info {type:XDC file:1 line:16 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS25 [get_ports ADC_MISO] -set_property src_info {type:XDC file:1 line:17 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN P18 [get_ports ADC_MISO] -set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design] -set_property OFFCHIP_TERM NONE [get_ports ADC_MOSI] -set_property src_info {type:XDC file:1 line:20 export:INPUT save:INPUT read:READ} [current_design] -set_property OFFCHIP_TERM NONE [get_ports ADC_SCK] -set_property src_info {type:XDC file:1 line:21 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN P16 [get_ports SI_SCL] -set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS25 [get_ports SI_SCL] -set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN P15 [get_ports SI_SDA] -set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design] -set_property IOSTANDARD LVCMOS25 [get_ports SI_SDA] -set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN P15 [get_ports IIC_0_sda_io] -set_property src_info {type:XDC file:1 line:28 export:INPUT save:INPUT read:READ} [current_design] +set_property src_info {type:XDC file:1 line:8 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN P16 [get_ports IIC_0_scl_io] -set_property src_info {type:XDC file:1 line:31 export:INPUT save:INPUT read:READ} [current_design] +set_property src_info {type:XDC file:1 line:11 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN T12 [get_ports SPI0_CS_ADC1] -set_property src_info {type:XDC file:1 line:33 export:INPUT save:INPUT read:READ} [current_design] +set_property src_info {type:XDC file:1 line:13 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN N17 [get_ports SPI0_CS_ADC2] -set_property src_info {type:XDC file:1 line:35 export:INPUT save:INPUT read:READ} [current_design] +set_property src_info {type:XDC file:1 line:15 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN P18 [get_ports SPI0_MISO_0] -set_property src_info {type:XDC file:1 line:37 export:INPUT save:INPUT read:READ} [current_design] +set_property src_info {type:XDC file:1 line:17 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN T19 [get_ports SPI0_MOSI_0] -set_property src_info {type:XDC file:1 line:39 export:INPUT save:INPUT read:READ} [current_design] +set_property src_info {type:XDC file:1 line:19 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN R19 [get_ports SPI0_SCLK_0] -set_property src_info {type:XDC file:1 line:42 export:INPUT save:INPUT read:READ} [current_design] +set_property src_info {type:XDC file:1 line:22 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN N18 [get_ports AD_DCO_N_0] -set_property src_info {type:XDC file:1 line:43 export:INPUT save:INPUT read:READ} [current_design] +set_property src_info {type:XDC file:1 line:23 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN P19 [get_ports AD_DCO_P_0] -set_property src_info {type:XDC file:1 line:44 export:INPUT save:INPUT read:READ} [current_design] +set_property src_info {type:XDC file:1 line:24 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN U14 [get_ports AD_FR_N_0] -set_property src_info {type:XDC file:1 line:45 export:INPUT save:INPUT read:READ} [current_design] +set_property src_info {type:XDC file:1 line:25 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN U15 [get_ports AD_FR_P_0] -set_property src_info {type:XDC file:1 line:46 export:INPUT save:INPUT read:READ} [current_design] +set_property src_info {type:XDC file:1 line:26 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN V17 [get_ports AD_IN_1A_N_0] -set_property src_info {type:XDC file:1 line:47 export:INPUT save:INPUT read:READ} [current_design] +set_property src_info {type:XDC file:1 line:27 export:INPUT save:INPUT read:READ} [current_design] set_property PACKAGE_PIN V18 [get_ports AD_IN_1A_P_0] +set_property src_info {type:XDC file:1 line:51 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN V20 [get_ports AD_IN_2C_N_0] +set_property src_info {type:XDC file:1 line:52 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN T20 [get_ports AD_IN_2D_N_0] +set_property src_info {type:XDC file:1 line:53 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN Y18 [get_ports AD_IN_2B_N_0] +set_property src_info {type:XDC file:1 line:54 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN V16 [get_ports AD_IN_2A_N_0] set_property src_info {type:XDC file:1 line:55 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN U14 [get_ports AD_FR_P_0] -set_property src_info {type:XDC file:1 line:70 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN N18 [get_ports AD_DCO_P_0] -set_property src_info {type:XDC file:1 line:71 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN V17 [get_ports AD_IN_1A_P_0] -set_property src_info {type:XDC file:1 line:72 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN R16 [get_ports AD_IN_1B_P_0] -set_property src_info {type:XDC file:1 line:73 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN Y18 [get_ports AD_IN_1C_P_0] -set_property src_info {type:XDC file:1 line:74 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN T20 [get_ports AD_IN_1D_P_0] -set_property src_info {type:XDC file:1 line:75 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN T16 [get_ports AD_IN_2A_P_0] -set_property src_info {type:XDC file:1 line:76 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN Y16 [get_ports AD_IN_2B_P_0] -set_property src_info {type:XDC file:1 line:77 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN T14 [get_ports AD_IN_2C_P_0] -set_property src_info {type:XDC file:1 line:78 export:INPUT save:INPUT read:READ} [current_design] -set_property PACKAGE_PIN T11 [get_ports AD_IN_2D_P_0] +set_property PACKAGE_PIN R16 [get_ports AD_IN_1D_N_0] +set_property src_info {type:XDC file:1 line:56 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN T17 [get_ports AD_IN_1C_N_0] +set_property src_info {type:XDC file:1 line:57 export:INPUT save:INPUT read:READ} [current_design] +set_property PACKAGE_PIN W18 [get_ports AD_IN_1B_N_0] diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.vivado.begin.rst b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.vivado.begin.rst index dd3b351964f37a0d185769e0a216d48fb3d7acbd..25919d14849c72bbec14d67f407f6fead8d78584 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.vivado.begin.rst +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/gen_run.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/gen_run.xml index de313a888398272459355829231020f114ee4158..9edc9c8b265ba0875caf106b7295cfffc96277ee 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/gen_run.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/gen_run.xml @@ -1,11 +1,14 @@ - - - - + + + + + + + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/mz_petalinux_wrapper.dcp b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/mz_petalinux_wrapper.dcp index f2a855e5683176c556812f55842c3d20998d440e..f0a02badad4fccc62f5ccb783ee7ce8d13bb1dd7 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/mz_petalinux_wrapper.dcp and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/mz_petalinux_wrapper.dcp differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/mz_petalinux_wrapper.vds b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/mz_petalinux_wrapper.vds index d6b212ee9fffdecb027a4f6ef8e1c401f9b6cbcb..a880d458499d02b2005df277bf82bd20da5d53c0 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/mz_petalinux_wrapper.vds +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/mz_petalinux_wrapper.vds @@ -2,8 +2,8 @@ # Vivado v2017.4 (64-bit) # SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017 # IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 -# Start of session at: Fri Oct 18 01:22:33 2019 -# Process ID: 18654 +# Start of session at: Sun Oct 20 22:43:59 2019 +# Process ID: 6186 # Current directory: /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1 # Command line: vivado -log mz_petalinux_wrapper.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source mz_petalinux_wrapper.tcl # Log file: /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/mz_petalinux_wrapper.vds @@ -21,9 +21,9 @@ Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010' INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 18678 +INFO: Helper process launched with PID 6196 --------------------------------------------------------------------------------- -Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1349.039 ; gain = 83.992 ; free physical = 2424 ; free virtual = 10856 +Starting RTL Elaboration : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1351.430 ; gain = 83.992 ; free physical = 3705 ; free virtual = 10444 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'mz_petalinux_wrapper' [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/hdl/mz_petalinux_wrapper.v:12] INFO: [Synth 8-638] synthesizing module 'IOBUF' [/home/nats/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:22655] @@ -33,17 +33,17 @@ INFO: [Synth 8-638] synthesizing module 'IOBUF' [/home/nats/Xilinx/Vivado/2017.4 Parameter SLEW bound to: SLOW - type: string INFO: [Synth 8-256] done synthesizing module 'IOBUF' (1#1) [/home/nats/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:22655] INFO: [Synth 8-638] synthesizing module 'mz_petalinux' [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/synth/mz_petalinux.v:430] -INFO: [Synth 8-638] synthesizing module 'mz_petalinux_LTC2271_SampleGetter_0_0' [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/realtime/mz_petalinux_LTC2271_SampleGetter_0_0_stub.v:6] -INFO: [Synth 8-256] done synthesizing module 'mz_petalinux_LTC2271_SampleGetter_0_0' (2#1) [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/realtime/mz_petalinux_LTC2271_SampleGetter_0_0_stub.v:6] +INFO: [Synth 8-638] synthesizing module 'mz_petalinux_LTC2271_SampleGetter_0_0' [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/realtime/mz_petalinux_LTC2271_SampleGetter_0_0_stub.v:6] +INFO: [Synth 8-256] done synthesizing module 'mz_petalinux_LTC2271_SampleGetter_0_0' (2#1) [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/realtime/mz_petalinux_LTC2271_SampleGetter_0_0_stub.v:6] WARNING: [Synth 8-350] instance 'LTC2271_SampleGetter_0' of module 'mz_petalinux_LTC2271_SampleGetter_0_0' requires 27 connections, but only 26 given [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/synth/mz_petalinux.v:763] -INFO: [Synth 8-638] synthesizing module 'mz_petalinux_axi_dma_0_0' [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/realtime/mz_petalinux_axi_dma_0_0_stub.v:6] -INFO: [Synth 8-256] done synthesizing module 'mz_petalinux_axi_dma_0_0' (3#1) [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/realtime/mz_petalinux_axi_dma_0_0_stub.v:6] +INFO: [Synth 8-638] synthesizing module 'mz_petalinux_axi_dma_0_0' [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/realtime/mz_petalinux_axi_dma_0_0_stub.v:6] +INFO: [Synth 8-256] done synthesizing module 'mz_petalinux_axi_dma_0_0' (3#1) [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/realtime/mz_petalinux_axi_dma_0_0_stub.v:6] WARNING: [Synth 8-350] instance 'axi_dma_0' of module 'mz_petalinux_axi_dma_0_0' requires 73 connections, but only 71 given [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/synth/mz_petalinux.v:790] -INFO: [Synth 8-638] synthesizing module 'mz_petalinux_axi_smc_0' [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/realtime/mz_petalinux_axi_smc_0_stub.v:6] -INFO: [Synth 8-256] done synthesizing module 'mz_petalinux_axi_smc_0' (4#1) [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/realtime/mz_petalinux_axi_smc_0_stub.v:6] +INFO: [Synth 8-638] synthesizing module 'mz_petalinux_axi_smc_0' [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/realtime/mz_petalinux_axi_smc_0_stub.v:6] +INFO: [Synth 8-256] done synthesizing module 'mz_petalinux_axi_smc_0' (4#1) [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/realtime/mz_petalinux_axi_smc_0_stub.v:6] WARNING: [Synth 8-350] instance 'axi_smc' of module 'mz_petalinux_axi_smc_0' requires 101 connections, but only 96 given [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/synth/mz_petalinux.v:862] -INFO: [Synth 8-638] synthesizing module 'mz_petalinux_processing_system7_0_0' [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/realtime/mz_petalinux_processing_system7_0_0_stub.v:6] -INFO: [Synth 8-256] done synthesizing module 'mz_petalinux_processing_system7_0_0' (5#1) [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/realtime/mz_petalinux_processing_system7_0_0_stub.v:6] +INFO: [Synth 8-638] synthesizing module 'mz_petalinux_processing_system7_0_0' [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/realtime/mz_petalinux_processing_system7_0_0_stub.v:6] +INFO: [Synth 8-256] done synthesizing module 'mz_petalinux_processing_system7_0_0' (5#1) [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/realtime/mz_petalinux_processing_system7_0_0_stub.v:6] WARNING: [Synth 8-350] instance 'processing_system7_0' of module 'mz_petalinux_processing_system7_0_0' requires 134 connections, but only 117 given [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/synth/mz_petalinux.v:959] INFO: [Synth 8-638] synthesizing module 'mz_petalinux_ps7_0_axi_periph_0' [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/synth/mz_petalinux.v:1174] INFO: [Synth 8-638] synthesizing module 'm00_couplers_imp_RIV9K6' [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/synth/mz_petalinux.v:12] @@ -53,20 +53,20 @@ INFO: [Synth 8-256] done synthesizing module 'm01_couplers_imp_W7Q5EU' (7#1) [/h INFO: [Synth 8-638] synthesizing module 'm02_couplers_imp_LGYMCM' [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/synth/mz_petalinux.v:283] INFO: [Synth 8-256] done synthesizing module 'm02_couplers_imp_LGYMCM' (8#1) [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/synth/mz_petalinux.v:283] INFO: [Synth 8-638] synthesizing module 's00_couplers_imp_Z2PNN9' [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/synth/mz_petalinux.v:1889] -INFO: [Synth 8-638] synthesizing module 'mz_petalinux_auto_pc_0' [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/realtime/mz_petalinux_auto_pc_0_stub.v:6] -INFO: [Synth 8-256] done synthesizing module 'mz_petalinux_auto_pc_0' (9#1) [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/realtime/mz_petalinux_auto_pc_0_stub.v:6] +INFO: [Synth 8-638] synthesizing module 'mz_petalinux_auto_pc_0' [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/realtime/mz_petalinux_auto_pc_0_stub.v:6] +INFO: [Synth 8-256] done synthesizing module 'mz_petalinux_auto_pc_0' (9#1) [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/realtime/mz_petalinux_auto_pc_0_stub.v:6] INFO: [Synth 8-256] done synthesizing module 's00_couplers_imp_Z2PNN9' (10#1) [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/synth/mz_petalinux.v:1889] -INFO: [Synth 8-638] synthesizing module 'mz_petalinux_xbar_0' [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/realtime/mz_petalinux_xbar_0_stub.v:6] -INFO: [Synth 8-256] done synthesizing module 'mz_petalinux_xbar_0' (11#1) [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/realtime/mz_petalinux_xbar_0_stub.v:6] +INFO: [Synth 8-638] synthesizing module 'mz_petalinux_xbar_0' [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/realtime/mz_petalinux_xbar_0_stub.v:6] +INFO: [Synth 8-256] done synthesizing module 'mz_petalinux_xbar_0' (11#1) [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/realtime/mz_petalinux_xbar_0_stub.v:6] INFO: [Synth 8-256] done synthesizing module 'mz_petalinux_ps7_0_axi_periph_0' (12#1) [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/synth/mz_petalinux.v:1174] WARNING: [Synth 8-350] instance 'ps7_0_axi_periph' of module 'mz_petalinux_ps7_0_axi_periph_0' requires 102 connections, but only 80 given [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/synth/mz_petalinux.v:1077] -INFO: [Synth 8-638] synthesizing module 'mz_petalinux_rst_ps7_0_100M_0' [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/realtime/mz_petalinux_rst_ps7_0_100M_0_stub.v:6] -INFO: [Synth 8-256] done synthesizing module 'mz_petalinux_rst_ps7_0_100M_0' (13#1) [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/realtime/mz_petalinux_rst_ps7_0_100M_0_stub.v:6] +INFO: [Synth 8-638] synthesizing module 'mz_petalinux_rst_ps7_0_100M_0' [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/realtime/mz_petalinux_rst_ps7_0_100M_0_stub.v:6] +INFO: [Synth 8-256] done synthesizing module 'mz_petalinux_rst_ps7_0_100M_0' (13#1) [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/realtime/mz_petalinux_rst_ps7_0_100M_0_stub.v:6] WARNING: [Synth 8-350] instance 'rst_ps7_0_100M' of module 'mz_petalinux_rst_ps7_0_100M_0' requires 10 connections, but only 7 given [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/synth/mz_petalinux.v:1158] -INFO: [Synth 8-638] synthesizing module 'mz_petalinux_xlconcat_0_0' [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/realtime/mz_petalinux_xlconcat_0_0_stub.v:6] -INFO: [Synth 8-256] done synthesizing module 'mz_petalinux_xlconcat_0_0' (14#1) [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/realtime/mz_petalinux_xlconcat_0_0_stub.v:6] -INFO: [Synth 8-638] synthesizing module 'mz_petalinux_xlconstant_0_0' [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/realtime/mz_petalinux_xlconstant_0_0_stub.v:6] -INFO: [Synth 8-256] done synthesizing module 'mz_petalinux_xlconstant_0_0' (15#1) [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/realtime/mz_petalinux_xlconstant_0_0_stub.v:6] +INFO: [Synth 8-638] synthesizing module 'mz_petalinux_xlconcat_0_0' [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/realtime/mz_petalinux_xlconcat_0_0_stub.v:6] +INFO: [Synth 8-256] done synthesizing module 'mz_petalinux_xlconcat_0_0' (14#1) [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/realtime/mz_petalinux_xlconcat_0_0_stub.v:6] +INFO: [Synth 8-638] synthesizing module 'mz_petalinux_xlconstant_0_0' [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/realtime/mz_petalinux_xlconstant_0_0_stub.v:6] +INFO: [Synth 8-256] done synthesizing module 'mz_petalinux_xlconstant_0_0' (15#1) [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/realtime/mz_petalinux_xlconstant_0_0_stub.v:6] INFO: [Synth 8-256] done synthesizing module 'mz_petalinux' (16#1) [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/synth/mz_petalinux.v:430] INFO: [Synth 8-256] done synthesizing module 'mz_petalinux_wrapper' (17#1) [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/hdl/mz_petalinux_wrapper.v:12] WARNING: [Synth 8-3331] design s00_couplers_imp_Z2PNN9 has unconnected port M_ACLK @@ -84,7 +84,7 @@ WARNING: [Synth 8-3331] design m00_couplers_imp_RIV9K6 has unconnected port M_AR WARNING: [Synth 8-3331] design m00_couplers_imp_RIV9K6 has unconnected port S_ACLK WARNING: [Synth 8-3331] design m00_couplers_imp_RIV9K6 has unconnected port S_ARESETN --------------------------------------------------------------------------------- -Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1391.570 ; gain = 126.523 ; free physical = 2415 ; free virtual = 10847 +Finished RTL Elaboration : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1393.961 ; gain = 126.523 ; free physical = 3717 ; free virtual = 10456 --------------------------------------------------------------------------------- Report Check Netlist: @@ -94,7 +94,7 @@ Report Check Netlist: |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:08 . Memory (MB): peak = 1391.570 ; gain = 126.523 ; free physical = 2411 ; free virtual = 10843 +Finished RTL Optimization Phase 1 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1393.961 ; gain = 126.523 ; free physical = 3717 ; free virtual = 10456 --------------------------------------------------------------------------------- INFO: [Netlist 29-17] Analyzing 2 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds @@ -103,47 +103,26 @@ INFO: [Project 1-570] Preparing netlist for logic optimization Processing XDC Constraints Initializing timing engine -Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc] for cell 'mz_petalinux_i/processing_system7_0' -Finished Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc] for cell 'mz_petalinux_i/processing_system7_0' -Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp10/mz_petalinux_axi_dma_0_0_in_context.xdc] for cell 'mz_petalinux_i/axi_dma_0' -Finished Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp10/mz_petalinux_axi_dma_0_0_in_context.xdc] for cell 'mz_petalinux_i/axi_dma_0' -Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp11/mz_petalinux_rst_ps7_0_100M_0_in_context.xdc] for cell 'mz_petalinux_i/rst_ps7_0_100M' -Finished Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp11/mz_petalinux_rst_ps7_0_100M_0_in_context.xdc] for cell 'mz_petalinux_i/rst_ps7_0_100M' -Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp12/mz_petalinux_axi_smc_0_in_context.xdc] for cell 'mz_petalinux_i/axi_smc' -Finished Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp12/mz_petalinux_axi_smc_0_in_context.xdc] for cell 'mz_petalinux_i/axi_smc' -Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp13/mz_petalinux_xlconcat_0_0_in_context.xdc] for cell 'mz_petalinux_i/xlconcat_0' -Finished Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp13/mz_petalinux_xlconcat_0_0_in_context.xdc] for cell 'mz_petalinux_i/xlconcat_0' -Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp14/mz_petalinux_xbar_0_in_context.xdc] for cell 'mz_petalinux_i/ps7_0_axi_periph/xbar' -Finished Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp14/mz_petalinux_xbar_0_in_context.xdc] for cell 'mz_petalinux_i/ps7_0_axi_periph/xbar' -Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp15/mz_petalinux_xlconstant_0_0_in_context.xdc] for cell 'mz_petalinux_i/xlconstant_0' -Finished Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp15/mz_petalinux_xlconstant_0_0_in_context.xdc] for cell 'mz_petalinux_i/xlconstant_0' -Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc] for cell 'mz_petalinux_i/LTC2271_SampleGetter_0' -Finished Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc] for cell 'mz_petalinux_i/LTC2271_SampleGetter_0' -Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp17/mz_petalinux_auto_pc_0_in_context.xdc] for cell 'mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc' -Finished Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp17/mz_petalinux_auto_pc_0_in_context.xdc] for cell 'mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc' +Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc] for cell 'mz_petalinux_i/processing_system7_0' +Finished Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc] for cell 'mz_petalinux_i/processing_system7_0' +Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp10/mz_petalinux_axi_dma_0_0_in_context.xdc] for cell 'mz_petalinux_i/axi_dma_0' +Finished Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp10/mz_petalinux_axi_dma_0_0_in_context.xdc] for cell 'mz_petalinux_i/axi_dma_0' +Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp11/mz_petalinux_rst_ps7_0_100M_0_in_context.xdc] for cell 'mz_petalinux_i/rst_ps7_0_100M' +Finished Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp11/mz_petalinux_rst_ps7_0_100M_0_in_context.xdc] for cell 'mz_petalinux_i/rst_ps7_0_100M' +Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp12/mz_petalinux_axi_smc_0_in_context.xdc] for cell 'mz_petalinux_i/axi_smc' +Finished Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp12/mz_petalinux_axi_smc_0_in_context.xdc] for cell 'mz_petalinux_i/axi_smc' +Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp13/mz_petalinux_xlconcat_0_0_in_context.xdc] for cell 'mz_petalinux_i/xlconcat_0' +Finished Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp13/mz_petalinux_xlconcat_0_0_in_context.xdc] for cell 'mz_petalinux_i/xlconcat_0' +Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp14/mz_petalinux_xbar_0_in_context.xdc] for cell 'mz_petalinux_i/ps7_0_axi_periph/xbar' +Finished Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp14/mz_petalinux_xbar_0_in_context.xdc] for cell 'mz_petalinux_i/ps7_0_axi_periph/xbar' +Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp15/mz_petalinux_xlconstant_0_0_in_context.xdc] for cell 'mz_petalinux_i/xlconstant_0' +Finished Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp15/mz_petalinux_xlconstant_0_0_in_context.xdc] for cell 'mz_petalinux_i/xlconstant_0' +Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc] for cell 'mz_petalinux_i/LTC2271_SampleGetter_0' +Finished Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc] for cell 'mz_petalinux_i/LTC2271_SampleGetter_0' +Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp17/mz_petalinux_auto_pc_0_in_context.xdc] for cell 'mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc' +Finished Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp17/mz_petalinux_auto_pc_0_in_context.xdc] for cell 'mz_petalinux_i/ps7_0_axi_periph/s00_couplers/auto_pc' Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/constrs_1/new/pins.xdc] -WARNING: [Vivado 12-584] No ports matched 'ADC_SCK'. [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/constrs_1/new/pins.xdc:1] -WARNING: [Vivado 12-584] No ports matched 'ADC_SCK'. [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/constrs_1/new/pins.xdc:2] -WARNING: [Vivado 12-584] No ports matched 'ADC_SCK'. [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/constrs_1/new/pins.xdc:3] -WARNING: [Vivado 12-584] No ports matched 'ADC_MOSI'. [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/constrs_1/new/pins.xdc:5] -WARNING: [Vivado 12-584] No ports matched 'ADC_MOSI'. [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/constrs_1/new/pins.xdc:6] -WARNING: [Vivado 12-584] No ports matched 'ADC_MOSI'. [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/constrs_1/new/pins.xdc:7] -WARNING: [Vivado 12-584] No ports matched 'ADC2_CS'. [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/constrs_1/new/pins.xdc:10] -WARNING: [Vivado 12-584] No ports matched 'ADC2_CS'. [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/constrs_1/new/pins.xdc:11] -WARNING: [Vivado 12-584] No ports matched 'ADC2_CS'. [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/constrs_1/new/pins.xdc:12] -WARNING: [Vivado 12-584] No ports matched 'ADC1_CS'. [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/constrs_1/new/pins.xdc:13] -WARNING: [Vivado 12-584] No ports matched 'ADC1_CS'. [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/constrs_1/new/pins.xdc:14] -WARNING: [Vivado 12-584] No ports matched 'ADC1_CS'. [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/constrs_1/new/pins.xdc:15] -WARNING: [Vivado 12-584] No ports matched 'ADC_MISO'. [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/constrs_1/new/pins.xdc:16] -WARNING: [Vivado 12-584] No ports matched 'ADC_MISO'. [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/constrs_1/new/pins.xdc:17] -WARNING: [Vivado 12-584] No ports matched 'ADC_MOSI'. [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/constrs_1/new/pins.xdc:19] -WARNING: [Vivado 12-584] No ports matched 'ADC_SCK'. [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/constrs_1/new/pins.xdc:20] -WARNING: [Vivado 12-584] No ports matched 'SI_SCL'. [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/constrs_1/new/pins.xdc:21] -WARNING: [Vivado 12-584] No ports matched 'SI_SCL'. [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/constrs_1/new/pins.xdc:22] -WARNING: [Vivado 12-584] No ports matched 'SI_SDA'. [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/constrs_1/new/pins.xdc:23] -WARNING: [Vivado 12-584] No ports matched 'SI_SDA'. [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/constrs_1/new/pins.xdc:24] Finished Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/constrs_1/new/pins.xdc] -WARNING: [Project 1-498] One or more constraints failed evaluation while reading constraint file [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/constrs_1/new/pins.xdc] and the design contains unresolved black boxes. These constraints will be read post-synthesis (as long as their source constraint file is marked as used_in_implementation) and should be applied correctly then. You should review the constraints listed in the file [.Xil/mz_petalinux_wrapper_propImpl.xdc] and check the run log file to verify that these constraints were correctly applied. INFO: [Project 1-236] Implementation specific constraints were found while reading constraint file [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/constrs_1/new/pins.xdc]. These constraints will be ignored for synthesis but will be used in implementation. Impacted constraints are listed in the file [.Xil/mz_petalinux_wrapper_propImpl.xdc]. Resolution: To avoid this warning, move constraints listed in [.Xil/mz_petalinux_wrapper_propImpl.xdc] to another XDC file and exclude this new file from synthesis with the used_in_synthesis property (File Properties dialog in GUI) and re-run elaboration/synthesis. Parsing XDC File [/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/dont_touch.xdc] @@ -154,320 +133,320 @@ INFO: [Project 1-111] Unisim Transformation Summary: A total of 2 instances were transformed. IOBUF => IOBUF (IBUF, OBUFT): 2 instances -Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1666.000 ; gain = 0.000 ; free physical = 2257 ; free virtual = 10689 +Constraint Validation Runtime : Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1668.398 ; gain = 0.000 ; free physical = 3434 ; free virtual = 10178 --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:33 . Memory (MB): peak = 1666.000 ; gain = 400.953 ; free physical = 2537 ; free virtual = 10969 +Finished Constraint Validation : Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 1668.398 ; gain = 400.961 ; free physical = 3499 ; free virtual = 10245 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z010clg400-1 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:33 . Memory (MB): peak = 1666.000 ; gain = 400.953 ; free physical = 2537 ; free virtual = 10969 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:21 ; elapsed = 00:00:31 . Memory (MB): peak = 1668.398 ; gain = 400.961 ; free physical = 3499 ; free virtual = 10245 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Applying 'set_property' XDC Constraints --------------------------------------------------------------------------------- -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[0]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 2). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[0]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 3). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[10]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 4). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[10]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 5). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[11]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 6). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[11]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 7). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[12]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 8). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[12]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 9). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[13]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 10). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[13]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 11). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[14]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 12). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[14]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 13). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[1]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 14). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[1]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 15). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[2]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 16). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[2]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 17). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[3]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 18). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[3]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 19). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[4]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 20). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[4]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 21). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[5]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 22). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[5]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 23). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[6]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 24). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[6]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 25). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[7]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 26). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[7]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 27). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[8]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 28). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[8]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 29). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[9]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 30). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[9]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 31). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_ba[0]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 32). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ba[0]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 33). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_ba[1]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 34). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ba[1]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 35). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_ba[2]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 36). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ba[2]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 37). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_cas_n. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 38). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_cas_n. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 39). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_cke. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 40). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_cke. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 41). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_cs_n. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 42). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_cs_n. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 43). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_ck_p. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 44). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ck_p. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 45). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_ck_n. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 46). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ck_n. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 47). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[0]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 48). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[0]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 49). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[1]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 50). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[1]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 51). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[2]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 52). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[2]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 53). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[3]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 54). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[3]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 55). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[0]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 56). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[0]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 57). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[1]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 58). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[1]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 59). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[2]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 60). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[2]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 61). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[3]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 62). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[3]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 63). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[0]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 64). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[0]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 65). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[1]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 66). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[1]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 67). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[2]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 68). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[2]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 69). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[3]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 70). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[3]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 71). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[0]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 72). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[0]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 73). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[10]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 74). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[10]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 75). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[11]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 76). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[11]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 77). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[12]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 78). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[12]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 79). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[13]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 80). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[13]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 81). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[14]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 82). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[14]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 83). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[15]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 84). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[15]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 85). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[16]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 86). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[16]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 87). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[17]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 88). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[17]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 89). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[18]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 90). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[18]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 91). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[19]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 92). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[19]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 93). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[1]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 94). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[1]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 95). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[20]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 96). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[20]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 97). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[21]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 98). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[21]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 99). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[22]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 100). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[22]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 101). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[23]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 102). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[23]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 103). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[24]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 104). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[24]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 105). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[25]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 106). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[25]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 107). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[26]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 108). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[26]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 109). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[27]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 110). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[27]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 111). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[28]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 112). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[28]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 113). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[29]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 114). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[29]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 115). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[2]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 116). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[2]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 117). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[30]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 118). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[30]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 119). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[31]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 120). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[31]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 121). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[3]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 122). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[3]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 123). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[4]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 124). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[4]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 125). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[5]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 126). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[5]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 127). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[6]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 128). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[6]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 129). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[7]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 130). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[7]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 131). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[8]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 132). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[8]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 133). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[9]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 134). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[9]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 135). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_reset_n. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 136). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_reset_n. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 137). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_odt. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 138). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_odt. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 139). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_ras_n. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 140). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ras_n. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 141). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrn. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 142). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrn. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 143). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrp. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 144). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrp. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 145). -Applied set_property IO_BUFFER_TYPE = NONE for DDR_we_n. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 146). -Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_we_n. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 147). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[0]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 148). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[0]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 149). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[10]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 150). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[10]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 151). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[11]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 152). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[11]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 153). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[12]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 154). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[12]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 155). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[13]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 156). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[13]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 157). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[14]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 158). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[14]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 159). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[15]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 160). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[15]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 161). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[16]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 162). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[16]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 163). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[17]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 164). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[17]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 165). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[18]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 166). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[18]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 167). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[19]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 168). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[19]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 169). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[1]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 170). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[1]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 171). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[20]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 172). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[20]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 173). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[21]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 174). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[21]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 175). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[22]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 176). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[22]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 177). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[23]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 178). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[23]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 179). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[24]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 180). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[24]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 181). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[25]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 182). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[25]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 183). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[26]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 184). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[26]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 185). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[27]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 186). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[27]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 187). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[28]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 188). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[28]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 189). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[29]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 190). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[29]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 191). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[2]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 192). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[2]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 193). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[30]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 194). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[30]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 195). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[31]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 196). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[31]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 197). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[32]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 198). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[32]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 199). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[33]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 200). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[33]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 201). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[34]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 202). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[34]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 203). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[35]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 204). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[35]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 205). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[36]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 206). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[36]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 207). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[37]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 208). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[37]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 209). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[38]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 210). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[38]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 211). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[39]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 212). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[39]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 213). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[3]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 214). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[3]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 215). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[40]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 216). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[40]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 217). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[41]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 218). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[41]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 219). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[42]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 220). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[42]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 221). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[43]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 222). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[43]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 223). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[44]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 224). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[44]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 225). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[45]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 226). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[45]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 227). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[46]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 228). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[46]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 229). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[47]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 230). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[47]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 231). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[48]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 232). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[48]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 233). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[49]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 234). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[49]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 235). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[4]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 236). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[4]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 237). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[50]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 238). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[50]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 239). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[51]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 240). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[51]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 241). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[52]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 242). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[52]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 243). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[53]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 244). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[53]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 245). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[5]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 246). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[5]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 247). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[6]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 248). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[6]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 249). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[7]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 250). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[7]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 251). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[8]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 252). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[8]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 253). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[9]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 254). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[9]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 255). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_clk. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 256). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_clk. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 257). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_porb. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 258). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_porb. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 259). -Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_srstb. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 260). -Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_srstb. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 261). -Applied set_property IO_BUFFER_TYPE = NONE for AD_DCO_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 1). -Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_DCO_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 2). -Applied set_property IO_BUFFER_TYPE = NONE for AD_DCO_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 3). -Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_DCO_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 4). -Applied set_property IO_BUFFER_TYPE = NONE for AD_FR_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 5). -Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_FR_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 6). -Applied set_property IO_BUFFER_TYPE = NONE for AD_FR_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 7). -Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_FR_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 8). -Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_1A_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 9). -Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_1A_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 10). -Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_1A_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 11). -Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_1A_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 12). -Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_1B_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 13). -Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_1B_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 14). -Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_1B_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 15). -Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_1B_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 16). -Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_1C_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 17). -Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_1C_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 18). -Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_1C_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 19). -Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_1C_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 20). -Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_1D_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 21). -Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_1D_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 22). -Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_1D_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 23). -Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_1D_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 24). -Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_2A_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 25). -Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_2A_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 26). -Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_2A_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 27). -Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_2A_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 28). -Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_2B_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 29). -Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_2B_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 30). -Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_2B_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 31). -Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_2B_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 32). -Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_2C_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 33). -Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_2C_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 34). -Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_2C_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 35). -Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_2C_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 36). -Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_2D_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 37). -Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_2D_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 38). -Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_2D_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 39). -Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_2D_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-18654-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 40). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[0]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 2). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[0]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 3). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[10]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 4). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[10]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 5). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[11]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 6). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[11]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 7). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[12]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 8). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[12]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 9). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[13]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 10). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[13]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 11). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[14]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 12). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[14]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 13). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[1]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 14). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[1]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 15). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[2]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 16). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[2]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 17). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[3]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 18). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[3]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 19). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[4]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 20). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[4]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 21). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[5]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 22). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[5]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 23). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[6]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 24). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[6]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 25). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[7]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 26). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[7]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 27). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[8]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 28). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[8]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 29). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_addr[9]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 30). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_addr[9]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 31). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_ba[0]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 32). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ba[0]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 33). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_ba[1]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 34). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ba[1]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 35). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_ba[2]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 36). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ba[2]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 37). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_cas_n. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 38). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_cas_n. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 39). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_cke. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 40). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_cke. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 41). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_cs_n. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 42). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_cs_n. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 43). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_ck_p. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 44). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ck_p. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 45). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_ck_n. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 46). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ck_n. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 47). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[0]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 48). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[0]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 49). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[1]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 50). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[1]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 51). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[2]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 52). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[2]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 53). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dm[3]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 54). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dm[3]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 55). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[0]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 56). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[0]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 57). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[1]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 58). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[1]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 59). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[2]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 60). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[2]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 61). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_p[3]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 62). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_p[3]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 63). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[0]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 64). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[0]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 65). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[1]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 66). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[1]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 67). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[2]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 68). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[2]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 69). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dqs_n[3]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 70). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dqs_n[3]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 71). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[0]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 72). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[0]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 73). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[10]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 74). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[10]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 75). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[11]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 76). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[11]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 77). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[12]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 78). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[12]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 79). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[13]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 80). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[13]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 81). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[14]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 82). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[14]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 83). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[15]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 84). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[15]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 85). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[16]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 86). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[16]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 87). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[17]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 88). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[17]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 89). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[18]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 90). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[18]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 91). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[19]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 92). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[19]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 93). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[1]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 94). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[1]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 95). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[20]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 96). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[20]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 97). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[21]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 98). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[21]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 99). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[22]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 100). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[22]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 101). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[23]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 102). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[23]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 103). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[24]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 104). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[24]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 105). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[25]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 106). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[25]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 107). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[26]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 108). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[26]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 109). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[27]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 110). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[27]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 111). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[28]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 112). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[28]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 113). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[29]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 114). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[29]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 115). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[2]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 116). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[2]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 117). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[30]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 118). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[30]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 119). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[31]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 120). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[31]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 121). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[3]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 122). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[3]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 123). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[4]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 124). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[4]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 125). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[5]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 126). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[5]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 127). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[6]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 128). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[6]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 129). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[7]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 130). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[7]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 131). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[8]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 132). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[8]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 133). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_dq[9]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 134). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_dq[9]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 135). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_reset_n. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 136). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_reset_n. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 137). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_odt. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 138). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_odt. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 139). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_ras_n. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 140). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_ras_n. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 141). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrn. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 142). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrn. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 143). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrp. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 144). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ddr_vrp. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 145). +Applied set_property IO_BUFFER_TYPE = NONE for DDR_we_n. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 146). +Applied set_property CLOCK_BUFFER_TYPE = NONE for DDR_we_n. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 147). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[0]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 148). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[0]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 149). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[10]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 150). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[10]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 151). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[11]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 152). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[11]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 153). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[12]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 154). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[12]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 155). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[13]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 156). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[13]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 157). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[14]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 158). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[14]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 159). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[15]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 160). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[15]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 161). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[16]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 162). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[16]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 163). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[17]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 164). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[17]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 165). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[18]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 166). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[18]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 167). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[19]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 168). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[19]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 169). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[1]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 170). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[1]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 171). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[20]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 172). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[20]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 173). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[21]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 174). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[21]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 175). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[22]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 176). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[22]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 177). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[23]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 178). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[23]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 179). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[24]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 180). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[24]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 181). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[25]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 182). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[25]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 183). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[26]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 184). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[26]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 185). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[27]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 186). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[27]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 187). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[28]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 188). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[28]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 189). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[29]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 190). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[29]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 191). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[2]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 192). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[2]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 193). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[30]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 194). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[30]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 195). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[31]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 196). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[31]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 197). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[32]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 198). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[32]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 199). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[33]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 200). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[33]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 201). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[34]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 202). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[34]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 203). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[35]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 204). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[35]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 205). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[36]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 206). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[36]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 207). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[37]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 208). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[37]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 209). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[38]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 210). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[38]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 211). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[39]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 212). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[39]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 213). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[3]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 214). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[3]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 215). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[40]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 216). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[40]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 217). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[41]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 218). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[41]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 219). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[42]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 220). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[42]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 221). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[43]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 222). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[43]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 223). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[44]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 224). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[44]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 225). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[45]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 226). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[45]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 227). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[46]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 228). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[46]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 229). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[47]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 230). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[47]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 231). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[48]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 232). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[48]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 233). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[49]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 234). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[49]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 235). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[4]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 236). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[4]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 237). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[50]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 238). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[50]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 239). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[51]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 240). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[51]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 241). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[52]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 242). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[52]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 243). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[53]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 244). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[53]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 245). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[5]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 246). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[5]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 247). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[6]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 248). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[6]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 249). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[7]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 250). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[7]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 251). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[8]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 252). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[8]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 253). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_mio[9]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 254). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_mio[9]. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 255). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_clk. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 256). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_clk. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 257). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_porb. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 258). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_porb. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 259). +Applied set_property IO_BUFFER_TYPE = NONE for FIXED_IO_ps_srstb. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 260). +Applied set_property CLOCK_BUFFER_TYPE = NONE for FIXED_IO_ps_srstb. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp9/mz_petalinux_processing_system7_0_0_in_context.xdc, line 261). +Applied set_property IO_BUFFER_TYPE = NONE for AD_DCO_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 1). +Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_DCO_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 2). +Applied set_property IO_BUFFER_TYPE = NONE for AD_DCO_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 3). +Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_DCO_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 4). +Applied set_property IO_BUFFER_TYPE = NONE for AD_FR_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 5). +Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_FR_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 6). +Applied set_property IO_BUFFER_TYPE = NONE for AD_FR_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 7). +Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_FR_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 8). +Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_1A_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 9). +Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_1A_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 10). +Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_1A_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 11). +Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_1A_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 12). +Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_1B_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 13). +Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_1B_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 14). +Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_1B_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 15). +Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_1B_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 16). +Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_1C_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 17). +Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_1C_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 18). +Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_1C_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 19). +Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_1C_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 20). +Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_1D_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 21). +Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_1D_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 22). +Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_1D_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 23). +Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_1D_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 24). +Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_2A_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 25). +Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_2A_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 26). +Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_2A_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 27). +Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_2A_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 28). +Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_2B_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 29). +Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_2B_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 30). +Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_2B_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 31). +Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_2B_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 32). +Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_2C_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 33). +Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_2C_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 34). +Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_2C_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 35). +Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_2C_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 36). +Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_2D_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 37). +Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_2D_N_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 38). +Applied set_property IO_BUFFER_TYPE = NONE for AD_IN_2D_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 39). +Applied set_property CLOCK_BUFFER_TYPE = NONE for AD_IN_2D_P_0. (constraint file /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/.Xil/Vivado-6186-nats-MS-7A72/dcp16/mz_petalinux_LTC2271_SampleGetter_0_0_in_context.xdc, line 40). Applied set_property DONT_TOUCH = true for mz_petalinux_i. (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for mz_petalinux_i/LTC2271_SampleGetter_0. (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for mz_petalinux_i/axi_dma_0. (constraint file auto generated constraint, line ). @@ -480,10 +459,10 @@ Applied set_property DONT_TOUCH = true for mz_petalinux_i/rst_ps7_0_100M. (const Applied set_property DONT_TOUCH = true for mz_petalinux_i/xlconcat_0. (constraint file auto generated constraint, line ). Applied set_property DONT_TOUCH = true for mz_petalinux_i/xlconstant_0. (constraint file auto generated constraint, line ). --------------------------------------------------------------------------------- -Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:21 ; elapsed = 00:00:33 . Memory (MB): peak = 1666.000 ; gain = 400.953 ; free physical = 2542 ; free virtual = 10975 +Finished applying 'set_property' XDC Constraints : Time (s): cpu = 00:00:21 ; elapsed = 00:00:32 . Memory (MB): peak = 1668.398 ; gain = 400.961 ; free physical = 3501 ; free virtual = 10247 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:22 ; elapsed = 00:00:33 . Memory (MB): peak = 1666.000 ; gain = 400.953 ; free physical = 2540 ; free virtual = 10972 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:21 ; elapsed = 00:00:32 . Memory (MB): peak = 1668.398 ; gain = 400.961 ; free physical = 3501 ; free virtual = 10247 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -524,7 +503,7 @@ WARNING: [Synth 8-3331] design mz_petalinux_ps7_0_axi_periph_0 has unconnected p WARNING: [Synth 8-3331] design mz_petalinux_ps7_0_axi_periph_0 has unconnected port M02_ACLK WARNING: [Synth 8-3331] design mz_petalinux_ps7_0_axi_periph_0 has unconnected port M02_ARESETN --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:22 ; elapsed = 00:00:33 . Memory (MB): peak = 1666.000 ; gain = 400.953 ; free physical = 2530 ; free virtual = 10962 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:21 ; elapsed = 00:00:32 . Memory (MB): peak = 1668.398 ; gain = 400.961 ; free physical = 3492 ; free virtual = 10238 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -538,13 +517,13 @@ Start Applying XDC Timing Constraints INFO: [Synth 8-5578] Moved timing constraint from pin 'mz_petalinux_i/processing_system7_0/FCLK_CLK0' to pin 'mz_petalinux_i/processing_system7_0/bbstub_FCLK_CLK0/O' INFO: [Synth 8-5819] Moved 1 constraints on hierarchical pins to their respective driving/loading pins --------------------------------------------------------------------------------- -Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:27 ; elapsed = 00:00:41 . Memory (MB): peak = 1677.000 ; gain = 411.953 ; free physical = 2395 ; free virtual = 10826 +Finished Applying XDC Timing Constraints : Time (s): cpu = 00:00:26 ; elapsed = 00:00:39 . Memory (MB): peak = 1679.398 ; gain = 411.961 ; free physical = 3293 ; free virtual = 10088 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:27 ; elapsed = 00:00:41 . Memory (MB): peak = 1677.000 ; gain = 411.953 ; free physical = 2395 ; free virtual = 10827 +Finished Timing Optimization : Time (s): cpu = 00:00:26 ; elapsed = 00:00:39 . Memory (MB): peak = 1679.398 ; gain = 411.961 ; free physical = 3293 ; free virtual = 10088 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -556,7 +535,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:27 ; elapsed = 00:00:41 . Memory (MB): peak = 1687.016 ; gain = 421.969 ; free physical = 2394 ; free virtual = 10825 +Finished Technology Mapping : Time (s): cpu = 00:00:27 ; elapsed = 00:00:39 . Memory (MB): peak = 1689.414 ; gain = 421.977 ; free physical = 3293 ; free virtual = 10088 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -580,7 +559,7 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:28 ; elapsed = 00:00:41 . Memory (MB): peak = 1687.016 ; gain = 421.969 ; free physical = 2393 ; free virtual = 10825 +Finished IO Insertion : Time (s): cpu = 00:00:27 ; elapsed = 00:00:40 . Memory (MB): peak = 1689.414 ; gain = 421.977 ; free physical = 3293 ; free virtual = 10088 --------------------------------------------------------------------------------- Report Check Netlist: @@ -593,7 +572,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:28 ; elapsed = 00:00:41 . Memory (MB): peak = 1687.016 ; gain = 421.969 ; free physical = 2393 ; free virtual = 10825 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:27 ; elapsed = 00:00:40 . Memory (MB): peak = 1689.414 ; gain = 421.977 ; free physical = 3293 ; free virtual = 10088 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -605,25 +584,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:28 ; elapsed = 00:00:41 . Memory (MB): peak = 1687.016 ; gain = 421.969 ; free physical = 2393 ; free virtual = 10825 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:27 ; elapsed = 00:00:40 . Memory (MB): peak = 1689.414 ; gain = 421.977 ; free physical = 3293 ; free virtual = 10088 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:28 ; elapsed = 00:00:41 . Memory (MB): peak = 1687.016 ; gain = 421.969 ; free physical = 2393 ; free virtual = 10825 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:27 ; elapsed = 00:00:40 . Memory (MB): peak = 1689.414 ; gain = 421.977 ; free physical = 3293 ; free virtual = 10088 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:28 ; elapsed = 00:00:41 . Memory (MB): peak = 1687.016 ; gain = 421.969 ; free physical = 2393 ; free virtual = 10825 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:27 ; elapsed = 00:00:40 . Memory (MB): peak = 1689.414 ; gain = 421.977 ; free physical = 3293 ; free virtual = 10088 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:28 ; elapsed = 00:00:41 . Memory (MB): peak = 1687.016 ; gain = 421.969 ; free physical = 2393 ; free virtual = 10825 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:27 ; elapsed = 00:00:40 . Memory (MB): peak = 1689.414 ; gain = 421.977 ; free physical = 3293 ; free virtual = 10088 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -672,11 +651,11 @@ Report Instance Areas: |4 | s00_couplers |s00_couplers_imp_Z2PNN9 | 177| +------+---------------------+--------------------------------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:28 ; elapsed = 00:00:41 . Memory (MB): peak = 1687.016 ; gain = 421.969 ; free physical = 2393 ; free virtual = 10825 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:27 ; elapsed = 00:00:40 . Memory (MB): peak = 1689.414 ; gain = 421.977 ; free physical = 3293 ; free virtual = 10088 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 6 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1687.016 ; gain = 147.539 ; free physical = 2451 ; free virtual = 10883 -Synthesis Optimization Complete : Time (s): cpu = 00:00:28 ; elapsed = 00:00:41 . Memory (MB): peak = 1687.023 ; gain = 421.969 ; free physical = 2453 ; free virtual = 10884 +Synthesis Optimization Runtime : Time (s): cpu = 00:00:19 ; elapsed = 00:00:22 . Memory (MB): peak = 1689.414 ; gain = 147.539 ; free physical = 3350 ; free virtual = 10145 +Synthesis Optimization Complete : Time (s): cpu = 00:00:27 ; elapsed = 00:00:40 . Memory (MB): peak = 1689.422 ; gain = 421.977 ; free physical = 3354 ; free virtual = 10149 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds @@ -687,10 +666,10 @@ INFO: [Project 1-111] Unisim Transformation Summary: IOBUF => IOBUF (IBUF, OBUFT): 2 instances INFO: [Common 17-83] Releasing license: Synthesis -54 Infos, 48 Warnings, 0 Critical Warnings and 0 Errors encountered. +54 Infos, 27 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:30 ; elapsed = 00:00:43 . Memory (MB): peak = 1693.016 ; gain = 452.801 ; free physical = 2432 ; free virtual = 10864 +synth_design: Time (s): cpu = 00:00:29 ; elapsed = 00:00:41 . Memory (MB): peak = 1695.414 ; gain = 452.809 ; free physical = 3327 ; free virtual = 10122 INFO: [Common 17-1381] The checkpoint '/home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/mz_petalinux_wrapper.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file mz_petalinux_wrapper_utilization_synth.rpt -pb mz_petalinux_wrapper_utilization_synth.pb -report_utilization: Time (s): cpu = 00:00:00.05 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1693.016 ; gain = 0.000 ; free physical = 2432 ; free virtual = 10863 -INFO: [Common 17-206] Exiting Vivado at Fri Oct 18 01:23:27 2019... +report_utilization: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.11 . Memory (MB): peak = 1695.414 ; gain = 0.000 ; free physical = 3328 ; free virtual = 10124 +INFO: [Common 17-206] Exiting Vivado at Sun Oct 20 22:44:51 2019... diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/mz_petalinux_wrapper_utilization_synth.rpt b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/mz_petalinux_wrapper_utilization_synth.rpt index e5378b6952208857ac6c81bb8260e22de858ec8f..16a8c47fb98f3235010c20d39b7b62acf806392e 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/mz_petalinux_wrapper_utilization_synth.rpt +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/mz_petalinux_wrapper_utilization_synth.rpt @@ -1,7 +1,7 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 -| Date : Fri Oct 18 01:23:27 2019 +| Date : Sun Oct 20 22:44:51 2019 | Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS | Command : report_utilization -file mz_petalinux_wrapper_utilization_synth.rpt -pb mz_petalinux_wrapper_utilization_synth.pb | Design : mz_petalinux_wrapper diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/project.wdf b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/project.wdf deleted file mode 100644 index 21601fe20b912a86be9c3ff9936dedfb7e0b2ff8..0000000000000000000000000000000000000000 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.runs/synth_1/project.wdf +++ /dev/null @@ -1,72 +0,0 @@ -version:1 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:737263736574636f756e74:32:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:636f6e73747261696e74736574636f756e74:31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:64657369676e6d6f6465:52544c:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:73796e7468657369737374726174656779:56697661646f2053796e7468657369732044656661756c7473:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:696d706c7374726174656779:56697661646f20496d706c656d656e746174696f6e2044656661756c7473:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e7473796e74686573697372756e:73796e74685f31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:63757272656e74696d706c72756e:696d706c5f31:00:00 -70726f6a656374:76697661646f5f75736167655c70726f6a6563745f64617461:746f74616c73796e74686573697372756e73:39:00:00 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mode 100644 index 0000000000000000000000000000000000000000..cd7c6545e2c1cf7e5346d16008a731363aee32ab --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.directory @@ -0,0 +1,4 @@ +[Dolphin] +Timestamp=2019,10,20,20,41,51 +Version=4 +ViewMode=1 diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/com.xilinx.sdk.targetmanager.ui/dialog_settings.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/com.xilinx.sdk.targetmanager.ui/dialog_settings.xml new file mode 100644 index 0000000000000000000000000000000000000000..5ca0b7769013920648b17f3f51ba3e88139fdf0e --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/com.xilinx.sdk.targetmanager.ui/dialog_settings.xml @@ -0,0 +1,3 @@ + +
+
diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.cdt.core/hello.1561908118211.pdom b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.cdt.core/hello.1561908118211.pdom index 9e0b0df7668387d157b04d5b8c4232afbfcd440c..80cebdd57e9ae3728ac4337784996907214ee232 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.cdt.core/hello.1561908118211.pdom and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.cdt.core/hello.1561908118211.pdom differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/24/50d69cdf7df300191e49b0d673419082 b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/24/50d69cdf7df300191e49b0d673419082 new file mode 100644 index 0000000000000000000000000000000000000000..e99953ad38b8fbbfeaeaf490b824055d233ad13a --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/24/50d69cdf7df300191e49b0d673419082 @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2012 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "si5338.h" +#include "si5338_genconf.h" +#include "sys_init.h" +#include "ltc2271.h" + +void init_i2c() { + i2c_file = open(i2c_name, O_RDWR); + if(i2c_file < 0) { + perror("Can't open i2c Device 0"); + exit(1); + } + detect_si5338(); + init_si5338(); +} + +void close_i2c() { + close(i2c_file); +} + +void close_spi() { + close(adc1_file); + close(adc2_file); +} + +void detect_si5338() { + uint8_t cmd_buffer[6]; + + uint8_t rev = 0; + uint8_t type = 0; + uint8_t grade = 0; + + int status = ioctl(i2c_file, I2C_SLAVE, si5338_addr); + if(status < 0) { + perror("Can't set the Slave Address"); + exit(1); + } + + cmd_buffer[0] = REVID; + write(i2c_file, cmd_buffer, 1); + + /* We try to read the 6 first register to identify the chip */ + read(i2c_file, cmd_buffer, 6); + + rev = (cmd_buffer[0] & 0x7) ? 'B' : 'A'; + type = cmd_buffer[2] & 0x3F; + grade = ((cmd_buffer[3] & 0xF8) >> 3) + 64; /* We map the value to the Grade */ + + printf("Detecting SI5338 - Rev. %c - Type %d - Grade %c \n", rev, type, grade); +} + +void change_si5338_reg(Reg_Data rdata) { + uint8_t addrval[2]; + addrval[0] = rdata.Reg_Addr; + addrval[1] = rdata.Reg_Val; + + uint8_t status = 0; + + if(rdata.Reg_Mask == 0xFF) { + status = write(i2c_file, addrval, 2); + if(status != 2) { + perror("Can't config SI5338"); + exit(1); + } + } else if(rdata.Reg_Mask != 0x00) { + uint8_t oldval[1]; + oldval[0] = 0; + + status = write(i2c_file, addrval, 1); + if(status != 1) { + perror("Can't config SI5338"); + exit(1); + } + + status = read(i2c_file, oldval, 1); + if(status != 1) { + perror("Can't config SI5338"); + exit(1); + } + + addrval[1] = (oldval[0] & ~rdata.Reg_Mask) | (addrval[1] & rdata.Reg_Mask); + status = write(i2c_file, addrval, 2); + if(status != 2) { + perror("Can't config SI5338"); + exit(1); + } + } +} + +void init_si5338() { + /* We use the generated clock builder file + * WIll be replaced by a calculator + */ + int status = ioctl(i2c_file, I2C_SLAVE, si5338_addr); + if(status < 0) { + perror("Can't set the Slave Address"); + exit(1); + } + for(uint16_t i = 0; i < NUM_REGS_MAX; i++) { + change_si5338_reg(Reg_Store[i]); + } +} + +void start_oled() { + int status = ioctl(i2c_file, I2C_SLAVE, oled_addr); + if(status < 0) { + perror("Can't set the Slave Address"); + exit(1); + } + + +} + +void config_ltc2271_reg(Adc_reg rdata) { + uint32_t status = 0; + uint8_t addrval[2]; + addrval[0] = rdata.addr; + addrval[1] = rdata.val; + + status = write(adc1_file, addrval, 2); + if(status != 2) { + perror("Can't config adc1"); + exit(1); + } + status = write(adc2_file, addrval, 2); + if(status != 2) { + perror("Can't config adc2"); + exit(1); + } + printf("ADC Configured\n"); +} + +void init_spi() { + uint32_t status = 0; + + adc1_file = open(adc1_name, O_RDWR); + if(adc1_file < 0) { + perror("Can't open spidev"); + exit(1); + } + adc2_file = open(adc2_name, O_RDWR); + if(adc2_file < 0) { + perror("Can't open spidev"); + exit(1); + } + + status = ioctl(adc1_file, SPI_IOC_WR_MAX_SPEED_HZ, &SPISPEED); + if(status != 0) { + perror("Can't set spi speed"); + exit(1); + } + + status = ioctl(adc2_file, SPI_IOC_WR_MAX_SPEED_HZ, &SPISPEED); + if(status != 0) { + perror("Can't set spi speed"); + exit(1); + } + + /* We set the SPI word to 8bits but send 2 bits back to back */ + + status = ioctl(adc1_file, SPI_IOC_WR_BITS_PER_WORD, &bits); + if(status != 0) { + perror("Can't set spi word"); + exit(1); + } + + status = ioctl(adc2_file, SPI_IOC_WR_BITS_PER_WORD, &bits); + if(status != 0) { + perror("Can't set spi word"); + exit(1); + } + + for(uint8_t i = 0; i < ADC_NBREG; i++) { + config_ltc2271_reg(ADCregs[i]); + } +} + +int main() +{ + printf("Starting VNA Software\n"); + init_i2c(); + init_spi(); + + close_i2c(); + close_spi(); + return 0; +} diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/26/d0ea5f3279f30019129cbbb66e2d8b8e b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/26/d0ea5f3279f30019129cbbb66e2d8b8e new file mode 100644 index 0000000000000000000000000000000000000000..2decb1025873b5944e08ef9c6afd06d7c647bd7a --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/26/d0ea5f3279f30019129cbbb66e2d8b8e @@ -0,0 +1,215 @@ +/* + * Copyright (c) 2012 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "si5338.h" +#include "si5338_genconf.h" +#include "sys_init.h" +#include "ltc2271.h" + +void init_i2c() { + i2c_file = open(i2c_name, O_RDWR); + if(i2c_file < 0) { + perror("Can't open i2c Device 0"); + exit(1); + } + detect_si5338(); + init_si5338(); +} + +void close_i2c() { + close(i2c_file); +} + +void close_spi() { + close(adc1_file); + close(adc2_file); +} + +void detect_si5338() { + uint8_t cmd_buffer[6]; + + uint8_t rev = 0; + uint8_t type = 0; + uint8_t grade = 0; + + int status = ioctl(i2c_file, I2C_SLAVE, si5338_addr); + if(status < 0) { + perror("Can't set the Slave Address"); + exit(1); + } + + cmd_buffer[0] = REVID; + write(i2c_file, cmd_buffer, 1); + + /* We try to read the 6 first register to identify the chip */ + read(i2c_file, cmd_buffer, 6); + + rev = (cmd_buffer[0] & 0x7) ? 'B' : 'A'; + type = cmd_buffer[2] & 0x3F; + grade = ((cmd_buffer[3] & 0xF8) >> 3) + 64; /* We map the value to the Grade */ + + printf("Detecting SI5338 - Rev. %c - Type %d - Grade %c \n", rev, type, grade); +} + +void change_si5338_reg(Reg_Data rdata) { + uint8_t addrval[2]; + addrval[0] = rdata.Reg_Addr; + addrval[1] = rdata.Reg_Val; + + uint8_t status = 0; + + if(rdata.Reg_Mask == 0xFF) { + status = write(i2c_file, addrval, 2); + if(status != 2) { + perror("Can't config SI5338"); + exit(1); + } + } else if(rdata.Reg_Mask != 0x00) { + uint8_t oldval[1]; + oldval[0] = 0; + + status = write(i2c_file, addrval, 1); + if(status != 1) { + perror("Can't config SI5338"); + exit(1); + } + + status = read(i2c_file, oldval, 1); + if(status != 1) { + perror("Can't config SI5338"); + exit(1); + } + + addrval[1] = (oldval[0] & ~rdata.Reg_Mask) | (addrval[1] & rdata.Reg_Mask); + status = write(i2c_file, addrval, 2); + if(status != 2) { + perror("Can't config SI5338"); + exit(1); + } + } +} + +void init_si5338() { + /* We use the generated clock builder file + * WIll be replaced by a calculator + */ + int status = ioctl(i2c_file, I2C_SLAVE, si5338_addr); + if(status < 0) { + perror("Can't set the Slave Address"); + exit(1); + } + for(uint16_t i = 0; i < NUM_REGS_MAX; i++) { + change_si5338_reg(Reg_Store[i]); + } +} + +void start_oled() { + int status = ioctl(i2c_file, I2C_SLAVE, oled_addr); + if(status < 0) { + perror("Can't set the Slave Address"); + exit(1); + } + + +} + +void config_ltc2271_reg(Adc_reg rdata) { + uint32_t status = 0; + uint8_t addrval[2]; + addrval[0] = rdata.addr; + addrval[1] = rdata.val; + + status = write(adc1_file, addrval, 2); + if(status != 2) { + perror("Can't config adc1"); + exit(1); + } + status = write(adc2_file, addrval, 2); + if(status != 2) { + perror("Can't config adc2"); + exit(1); + } + printf("ADC Configured\n"); +} + +void init_spi() { + uint32_t status = 0; + + adc1_file = open(adc1_name, O_RDWR); + if(adc1_file < 0) { + perror("Can't open spidev"); + exit(1); + } + adc2_file = open(adc2_name, O_RDWR); + if(adc2_file < 0) { + perror("Can't open spidev"); + exit(1); + } + + status = ioctl(adc1_file, SPI_IOC_WR_MAX_SPEED_HZ, &SPISPEED); + if(status != 0) { + perror("Can't set spi speed"); + exit(1); + } + + status = ioctl(adc2_file, SPI_IOC_WR_MAX_SPEED_HZ, &SPISPEED); + if(status != 0) { + perror("Can't set spi speed"); + exit(1); + } + + /* We set the SPI word to 8bits but send 2 bits back to back */ + uint8_t bits = 8; + status = ioctl(adc1_file, SPI_IOC_WR_BITS_PER_WORD, &bits); + if(status != 0) { + perror("Can't set spi word"); + exit(1); + } + + status = ioctl(adc2_file, SPI_IOC_WR_BITS_PER_WORD, &bits); + if(status != 0) { + perror("Can't set spi word"); + exit(1); + } + + for(uint8_t i = 0; i < ADC_NBREG; i++) { + config_ltc2271_reg(ADCregs[i]); + } +} + +int main() +{ + printf("Starting VNA Software\n"); + init_i2c(); + init_spi(); + + close_i2c(); + close_spi(); + return 0; +} diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/58/b0d0563f78f30019129cbbb66e2d8b8e b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/58/b0d0563f78f30019129cbbb66e2d8b8e new file mode 100644 index 0000000000000000000000000000000000000000..8614c902d42f10af0b13dd121e098c6dd48bf795 --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/58/b0d0563f78f30019129cbbb66e2d8b8e @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2012 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "si5338.h" +#include "si5338_genconf.h" +#include "sys_init.h" +#include "ltc2271.h" + +void init_i2c() { + i2c_file = open(i2c_name, O_RDWR); + if(i2c_file < 0) { + perror("Can't open i2c Device 0"); + exit(1); + } + detect_si5338(); + init_si5338(); +} + +void close_i2c() { + close(i2c_file); +} + +void close_spi() { + close(adc1_file); + close(adc2_file); +} + +void detect_si5338() { + uint8_t cmd_buffer[6]; + + uint8_t rev = 0; + uint8_t type = 0; + uint8_t grade = 0; + + int status = ioctl(i2c_file, I2C_SLAVE, si5338_addr); + if(status < 0) { + perror("Can't set the Slave Address"); + exit(1); + } + + cmd_buffer[0] = REVID; + write(i2c_file, cmd_buffer, 1); + + /* We try to read the 6 first register to identify the chip */ + read(i2c_file, cmd_buffer, 6); + + rev = (cmd_buffer[0] & 0x7) ? 'B' : 'A'; + type = cmd_buffer[2] & 0x3F; + grade = ((cmd_buffer[3] & 0xF8) >> 3) + 64; /* We map the value to the Grade */ + + printf("Detecting SI5338 - Rev. %c - Type %d - Grade %c \n", rev, type, grade); +} + +void change_si5338_reg(Reg_Data rdata) { + uint8_t addrval[2]; + addrval[0] = rdata.Reg_Addr; + addrval[1] = rdata.Reg_Val; + + uint8_t status = 0; + + if(rdata.Reg_Mask == 0xFF) { + status = write(i2c_file, addrval, 2); + if(status != 2) { + perror("Can't config SI5338"); + exit(1); + } + } else if(rdata.Reg_Mask != 0x00) { + uint8_t oldval[1]; + oldval[0] = 0; + + status = write(i2c_file, addrval, 1); + if(status != 1) { + perror("Can't config SI5338"); + exit(1); + } + + status = read(i2c_file, oldval, 1); + if(status != 1) { + perror("Can't config SI5338"); + exit(1); + } + + addrval[1] = (oldval[0] & ~rdata.Reg_Mask) | (addrval[1] & rdata.Reg_Mask); + status = write(i2c_file, addrval, 2); + if(status != 2) { + perror("Can't config SI5338"); + exit(1); + } + } +} + +void init_si5338() { + /* We use the generated clock builder file + * WIll be replaced by a calculator + */ + int status = ioctl(i2c_file, I2C_SLAVE, si5338_addr); + if(status < 0) { + perror("Can't set the Slave Address"); + exit(1); + } + for(uint16_t i = 0; i < NUM_REGS_MAX; i++) { + change_si5338_reg(Reg_Store[i]); + } +} + +void start_oled() { + int status = ioctl(i2c_file, I2C_SLAVE, oled_addr); + if(status < 0) { + perror("Can't set the Slave Address"); + exit(1); + } + + +} + +void config_ltc2271_reg(Adc_reg rdata) { + uint32_t status = 0; + uint8_t addrval[2]; + addrval[0] = rdata.addr; + addrval[1] = rdata.val; + + status = write(adc1_file, addrval, 2); + if(status != 2) { + perror("Can't config adc1"); + exit(1); + } + status = write(adc2_file, addrval, 2); + if(status != 2) { + perror("Can't config adc2"); + exit(1); + } + printf("ADC Configured\n"); +} + +void init_spi() { + uint32_t status = 0; + + adc1_file = open(adc1_name, O_RDWR); + if(adc1_file < 0) { + perror("Can't open spidev"); + exit(1); + } + adc2_file = open(adc2_name, O_RDWR); + if(adc2_file < 0) { + perror("Can't open spidev"); + exit(1); + } + + status = ioctl(adc1_file, SPI_IOC_WR_MAX_SPEED_HZ, &SPISPEED); + if(status != 0) { + perror("Can't set spi speed"); + exit(1); + } + + status = ioctl(adc2_file, SPI_IOC_WR_MAX_SPEED_HZ, &SPISPEED); + if(status != 0) { + perror("Can't set spi speed"); + exit(1); + } + + /* We set the SPI word to 8bits but send 2 bits back to back */ +// status = ioctl(adc1_file, SPI_IOC_WR_BITS_PER_WORD, 1); +// if(status != 0) { +// perror("Can't set spi word"); +// exit(1); +// } +// +// status = ioctl(adc2_file, SPI_IOC_WR_BITS_PER_WORD, 1); +// if(status != 0) { +// perror("Can't set spi word"); +// exit(1); +// } + + for(uint8_t i = 0; i < ADC_NBREG; i++) { + config_ltc2271_reg(ADCregs[i]); + } +} + +int main() +{ + printf("Starting VNA Software\n"); + init_i2c(); + init_spi(); + + close_i2c(); + close_spi(); + return 0; +} diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/6a/e0ff36e678f30019129cbbb66e2d8b8e b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/6a/e0ff36e678f30019129cbbb66e2d8b8e new file mode 100644 index 0000000000000000000000000000000000000000..0c3cb4618cd51144da3eec2ea5175ff736ede296 --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/6a/e0ff36e678f30019129cbbb66e2d8b8e @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2012 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "si5338.h" +#include "si5338_genconf.h" +#include "sys_init.h" +#include "ltc2271.h" + +void init_i2c() { + i2c_file = open(i2c_name, O_RDWR); + if(i2c_file < 0) { + perror("Can't open i2c Device 0"); + exit(1); + } + detect_si5338(); + init_si5338(); +} + +void close_i2c() { + close(i2c_file); +} + +void close_spi() { + close(adc1_file); + close(adc2_file); +} + +void detect_si5338() { + uint8_t cmd_buffer[6]; + + uint8_t rev = 0; + uint8_t type = 0; + uint8_t grade = 0; + + int status = ioctl(i2c_file, I2C_SLAVE, si5338_addr); + if(status < 0) { + perror("Can't set the Slave Address"); + exit(1); + } + + cmd_buffer[0] = REVID; + write(i2c_file, cmd_buffer, 1); + + /* We try to read the 6 first register to identify the chip */ + read(i2c_file, cmd_buffer, 6); + + rev = (cmd_buffer[0] & 0x7) ? 'B' : 'A'; + type = cmd_buffer[2] & 0x3F; + grade = ((cmd_buffer[3] & 0xF8) >> 3) + 64; /* We map the value to the Grade */ + + printf("Detecting SI5338 - Rev. %c - Type %d - Grade %c \n", rev, type, grade); +} + +void change_si5338_reg(Reg_Data rdata) { + uint8_t addrval[2]; + addrval[0] = rdata.Reg_Addr; + addrval[1] = rdata.Reg_Val; + + uint8_t status = 0; + + if(rdata.Reg_Mask == 0xFF) { + status = write(i2c_file, addrval, 2); + if(status != 2) { + perror("Can't config SI5338"); + exit(1); + } + } else if(rdata.Reg_Mask != 0x00) { + uint8_t oldval[1]; + oldval[0] = 0; + + status = write(i2c_file, addrval, 1); + if(status != 1) { + perror("Can't config SI5338"); + exit(1); + } + + status = read(i2c_file, oldval, 1); + if(status != 1) { + perror("Can't config SI5338"); + exit(1); + } + + addrval[1] = (oldval[0] & ~rdata.Reg_Mask) | (addrval[1] & rdata.Reg_Mask); + status = write(i2c_file, addrval, 2); + if(status != 2) { + perror("Can't config SI5338"); + exit(1); + } + } +} + +void init_si5338() { + /* We use the generated clock builder file + * WIll be replaced by a calculator + */ + int status = ioctl(i2c_file, I2C_SLAVE, si5338_addr); + if(status < 0) { + perror("Can't set the Slave Address"); + exit(1); + } + for(uint16_t i = 0; i < NUM_REGS_MAX; i++) { + change_si5338_reg(Reg_Store[i]); + } +} + +void start_oled() { + int status = ioctl(i2c_file, I2C_SLAVE, oled_addr); + if(status < 0) { + perror("Can't set the Slave Address"); + exit(1); + } + + +} + +void config_ltc2271_reg(Adc_reg rdata) { + uint32_t status = 0; + uint8_t addrval[2]; + addrval[0] = rdata.addr; + addrval[1] = rdata.val; + + status = write(adc1_file, addrval, 2); + if(status != 2) { + perror("Can't config adc1"); + exit(1); + } + status = write(adc2_file, addrval, 2); + if(status != 2) { + perror("Can't config adc2"); + exit(1); + } + printf("ADC Configured\n"); +} + +void init_spi() { + uint32_t status = 0; + + adc1_file = open(adc1_name, O_RDWR); + if(adc1_file < 0) { + perror("Can't open spidev"); + exit(1); + } + adc2_file = open(adc2_name, O_RDWR); + if(adc2_file < 0) { + perror("Can't open spidev"); + exit(1); + } + + status = ioctl(adc1_file, SPI_IOC_WR_MAX_SPEED_HZ, &SPISPEED); + if(status != 0) { + perror("Can't set spi speed"); + exit(1); + } + + status = ioctl(adc2_file, SPI_IOC_WR_MAX_SPEED_HZ, &SPISPEED); + if(status != 0) { + perror("Can't set spi speed"); + exit(1); + } + + /* We set the SPI word to 8bits but send 2 bits back to back */ + status = ioctl(adc1_file, SPI_IOC_WR_BITS_PER_WORD, 1); + if(status != 0) { + perror("Can't set spi word"); + exit(1); + } + + status = ioctl(adc2_file, SPI_IOC_WR_BITS_PER_WORD, 1); + if(status != 0) { + perror("Can't set spi word"); + exit(1); + } + + for(uint8_t i = 0; i < ADC_NBREG; i++) { + config_ltc2271_reg(ADCregs[i]); + } +} + +int main() +{ + printf("Starting VNA Software\n"); + init_i2c(); + init_spi(); + + close_i2c(); + close_spi(); + return 0; +} diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/7a/7082499540f300191cdece84059b9aa6 b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/7a/7082499540f300191cdece84059b9aa6 new file mode 100644 index 0000000000000000000000000000000000000000..5902437001a2965fe8cbff12db50218f4a523b34 --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/7a/7082499540f300191cdece84059b9aa6 @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2012 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "si5338.h" +#include "si5338_genconf.h" +#include "sys_init.h" +#include "ltc2271.h" + +void init_i2c() { + i2c_file = open(i2c_name, O_RDWR); + if(i2c_file < 0) { + perror("Can't open i2c Device 0"); + exit(1); + } + detect_si5338(); + init_si5338(); +} + +void close_i2c() { + close(i2c_file); +} + +void close_spi() { + close(adc1_file); + close(adc2_file); +} + +void detect_si5338() { + uint8_t cmd_buffer[6]; + + uint8_t rev = 0; + uint8_t type = 0; + uint8_t grade = 0; + + int status = ioctl(i2c_file, I2C_SLAVE, si5338_addr); + if(status < 0) { + perror("Can't set the Slave Address"); + exit(1); + } + + cmd_buffer[0] = REVID; + write(i2c_file, cmd_buffer, 1); + + /* We try to read the 6 first register to identify the chip */ + read(i2c_file, cmd_buffer, 6); + + rev = (cmd_buffer[0] & 0x7) ? 'B' : 'A'; + type = cmd_buffer[2] & 0x3F; + grade = ((cmd_buffer[3] & 0xF8) >> 3) + 64; /* We map the value to the Grade */ + + printf("Detecting SI5338 - Rev. %c - Type %d - Grade %c \n", rev, type, grade); +} + +void change_si5338_reg(Reg_Data rdata) { + uint8_t addrval[2]; + addrval[0] = rdata.Reg_Addr; + addrval[1] = rdata.Reg_Val; + + uint8_t status = 0; + + if(rdata.Reg_Mask == 0xFF) { + status = write(i2c_file, addrval, 2); + if(status != 2) { + perror("Can't config SI5338"); + exit(1); + } + } else if(rdata.Reg_Mask != 0x00) { + uint8_t oldval[1]; + oldval[0] = 0; + + status = write(i2c_file, addrval, 1); + if(status != 1) { + perror("Can't config SI5338"); + exit(1); + } + + status = read(i2c_file, oldval, 1); + if(status != 1) { + perror("Can't config SI5338"); + exit(1); + } + + addrval[1] = (oldval[0] & ~rdata.Reg_Mask) | (addrval[1] & rdata.Reg_Mask); + status = write(i2c_file, addrval, 2); + if(status != 2) { + perror("Can't config SI5338"); + exit(1); + } + } +} + +void init_si5338() { + /* We use the generated clock builder file + * WIll be replaced by a calculator + */ + int status = ioctl(i2c_file, I2C_SLAVE, si5338_addr); + if(status < 0) { + perror("Can't set the Slave Address"); + exit(1); + } + for(uint16_t i = 0; i < NUM_REGS_MAX; i++) { + change_si5338_reg(Reg_Store[i]); + } +} + +void start_oled() { + int status = ioctl(i2c_file, I2C_SLAVE, oled_addr); + if(status < 0) { + perror("Can't set the Slave Address"); + exit(1); + } + + +} + +void config_ltc2271_reg(Adc_reg rdata) { + uint32_t status = 0; + uint8_t addrval[2]; + addrval[0] = rdata.addr; + addrval[1] = rdata.val; + + status = write(adc1_file, addrval, 2); + if(status != 2) { + perror("can't config adc1"); + exit(1); + } + status = write(adc2_file, addrval, 2); + if(status != 2) { + perror("can't config adc2"); + exit(1); + } +} + +void init_spi() { + uint32_t status = 0; + + adc1_file = open(adc1_name, O_RDWR); + if(adc1_file < 0) { + perror("Can't open spidev"); + exit(1); + } + adc2_file = open(adc2_name, O_RDWR); + if(adc2_file < 0) { + perror("Can't open spidev"); + exit(1); + } + + status = ioctl(adc1_file, SPI_IOC_WR_MAX_SPEED_HZ, &SPISPEED); + if(status != 0) { + perror("Can't set spi speed"); + exit(1); + } + + status = ioctl(adc2_file, SPI_IOC_WR_MAX_SPEED_HZ, &SPISPEED); + if(status != 0) { + perror("Can't set spi speed"); + exit(1); + } + + /* We set the SPI word to 8bits but send 2 bits back to back */ +// status = ioctl(adc1_file, SPI_IOC_WR_BITS_PER_WORD, 1); +// if(status != 0) { +// perror("Can't set spi word"); +// exit(1); +// } +// +// status = ioctl(adc2_file, SPI_IOC_WR_BITS_PER_WORD, 1); +// if(status != 0) { +// perror("Can't set spi word"); +// exit(1); +// } + + for(uint8_t i = 0; i < ADC_NBREG; i++) { + config_ltc2271_reg(ADCregs[i]); + } +} + +int main() +{ + printf("Starting VNA Software\n"); + init_i2c(); + init_spi(); + + close_i2c(); + close_spi(); + return 0; +} diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/90/70debef455f3001914f8af9fb42ee8cd b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/90/70debef455f3001914f8af9fb42ee8cd new file mode 100644 index 0000000000000000000000000000000000000000..f5f496e234e5d1811577dd5e64706ffecbe51703 --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/90/70debef455f3001914f8af9fb42ee8cd @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2012 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "si5338.h" +#include "si5338_genconf.h" +#include "sys_init.h" +#include "ltc2271.h" + +void init_i2c() { + i2c_file = open(i2c_name, O_RDWR); + if(i2c_file < 0) { + perror("Can't open i2c Device 0"); + exit(1); + } + detect_si5338(); + init_si5338(); +} + +void close_i2c() { + close(i2c_file); +} + +void close_spi() { + close(adc1_file); + close(adc2_file); +} + +void detect_si5338() { + uint8_t cmd_buffer[6]; + + uint8_t rev = 0; + uint8_t type = 0; + uint8_t grade = 0; + + int status = ioctl(i2c_file, I2C_SLAVE, si5338_addr); + if(status < 0) { + perror("Can't set the Slave Address"); + exit(1); + } + + cmd_buffer[0] = REVID; + write(i2c_file, cmd_buffer, 1); + + /* We try to read the 6 first register to identify the chip */ + read(i2c_file, cmd_buffer, 6); + + rev = (cmd_buffer[0] & 0x7) ? 'B' : 'A'; + type = cmd_buffer[2] & 0x3F; + grade = ((cmd_buffer[3] & 0xF8) >> 3) + 64; /* We map the value to the Grade */ + + printf("Detecting SI5338 - Rev. %c - Type %d - Grade %c \n", rev, type, grade); +} + +void change_si5338_reg(Reg_Data rdata) { + uint8_t addrval[2]; + addrval[0] = rdata.Reg_Addr; + addrval[1] = rdata.Reg_Val; + + uint8_t status = 0; + + if(rdata.Reg_Mask == 0xFF) { + status = write(i2c_file, addrval, 2); + if(status != 2) { + perror("Can't config SI5338"); + exit(1); + } + } else if(rdata.Reg_Mask != 0x00) { + uint8_t oldval[1]; + oldval[0] = 0; + + status = write(i2c_file, addrval, 1); + if(status != 1) { + perror("Can't config SI5338"); + exit(1); + } + + status = read(i2c_file, oldval, 1); + if(status != 1) { + perror("Can't config SI5338"); + exit(1); + } + + addrval[1] = (oldval[0] & ~rdata.Reg_Mask) | (addrval[1] & rdata.Reg_Mask); + status = write(i2c_file, addrval, 2); + if(status != 2) { + perror("Can't config SI5338"); + exit(1); + } + } +} + +void init_si5338() { + /* We use the generated clock builder file + * WIll be replaced by a calculator + */ + int status = ioctl(i2c_file, I2C_SLAVE, si5338_addr); + if(status < 0) { + perror("Can't set the Slave Address"); + exit(1); + } + for(uint16_t i = 0; i < NUM_REGS_MAX; i++) { + change_si5338_reg(Reg_Store[i]); + } +} + +void start_oled() { + int status = ioctl(i2c_file, I2C_SLAVE, oled_addr); + if(status < 0) { + perror("Can't set the Slave Address"); + exit(1); + } + + +} + +void config_ltc2271_reg(Adc_reg rdata) { + uint32_t status = 0; + uint8_t addrval[2]; + addrval[0] = rdata.addr; + addrval[1] = rdata.val; + + status = write(adc1_file, addrval, 2); + if(status != 2) { + perror("can't config adc1"); + exit(1); + } + status = write(adc2_file, addrval, 2); + if(status != 2) { + perror("can't config adc2"); + exit(1); + } +} + +void init_spi() { + uint32_t status = 0; + + adc1_file = open(adc1_name, O_RDWR); + if(adc1_file < 0) { + perror("Can't open spidev"); + exit(1); + } + adc2_file = open(adc2_name, O_RDWR); + if(adc2_file < 0) { + perror("Can't open spidev"); + exit(1); + } + +/* status = ioctl(adc1_file, SPI_IOC_WR_MAX_SPEED_HZ, &SPISPEED); + if(status != 0) { + perror("Can't set spi speed"); + exit(1); + } + + status = ioctl(adc2_file, SPI_IOC_WR_MAX_SPEED_HZ, &SPISPEED); + if(status != 0) { + perror("Can't set spi speed"); + exit(1); + }*/ + + /* We set the SPI word to 8bits but send 2 bits back to back */ +// status = ioctl(adc1_file, SPI_IOC_WR_BITS_PER_WORD, 1); +// if(status != 0) { +// perror("Can't set spi word"); +// exit(1); +// } +// +// status = ioctl(adc2_file, SPI_IOC_WR_BITS_PER_WORD, 1); +// if(status != 0) { +// perror("Can't set spi word"); +// exit(1); +// } + + for(uint8_t i = 0; i < ADC_NBREG; i++) { + config_ltc2271_reg(ADCregs[i]); + } +} + +int main() +{ + printf("Starting VNA Software\n"); + init_i2c(); + init_spi(); + + close_i2c(); + close_spi(); + return 0; +} diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/d1/900b633e5cf3001914f8af9fb42ee8cd b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/d1/900b633e5cf3001914f8af9fb42ee8cd new file mode 100644 index 0000000000000000000000000000000000000000..8614c902d42f10af0b13dd121e098c6dd48bf795 --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/d1/900b633e5cf3001914f8af9fb42ee8cd @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2012 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "si5338.h" +#include "si5338_genconf.h" +#include "sys_init.h" +#include "ltc2271.h" + +void init_i2c() { + i2c_file = open(i2c_name, O_RDWR); + if(i2c_file < 0) { + perror("Can't open i2c Device 0"); + exit(1); + } + detect_si5338(); + init_si5338(); +} + +void close_i2c() { + close(i2c_file); +} + +void close_spi() { + close(adc1_file); + close(adc2_file); +} + +void detect_si5338() { + uint8_t cmd_buffer[6]; + + uint8_t rev = 0; + uint8_t type = 0; + uint8_t grade = 0; + + int status = ioctl(i2c_file, I2C_SLAVE, si5338_addr); + if(status < 0) { + perror("Can't set the Slave Address"); + exit(1); + } + + cmd_buffer[0] = REVID; + write(i2c_file, cmd_buffer, 1); + + /* We try to read the 6 first register to identify the chip */ + read(i2c_file, cmd_buffer, 6); + + rev = (cmd_buffer[0] & 0x7) ? 'B' : 'A'; + type = cmd_buffer[2] & 0x3F; + grade = ((cmd_buffer[3] & 0xF8) >> 3) + 64; /* We map the value to the Grade */ + + printf("Detecting SI5338 - Rev. %c - Type %d - Grade %c \n", rev, type, grade); +} + +void change_si5338_reg(Reg_Data rdata) { + uint8_t addrval[2]; + addrval[0] = rdata.Reg_Addr; + addrval[1] = rdata.Reg_Val; + + uint8_t status = 0; + + if(rdata.Reg_Mask == 0xFF) { + status = write(i2c_file, addrval, 2); + if(status != 2) { + perror("Can't config SI5338"); + exit(1); + } + } else if(rdata.Reg_Mask != 0x00) { + uint8_t oldval[1]; + oldval[0] = 0; + + status = write(i2c_file, addrval, 1); + if(status != 1) { + perror("Can't config SI5338"); + exit(1); + } + + status = read(i2c_file, oldval, 1); + if(status != 1) { + perror("Can't config SI5338"); + exit(1); + } + + addrval[1] = (oldval[0] & ~rdata.Reg_Mask) | (addrval[1] & rdata.Reg_Mask); + status = write(i2c_file, addrval, 2); + if(status != 2) { + perror("Can't config SI5338"); + exit(1); + } + } +} + +void init_si5338() { + /* We use the generated clock builder file + * WIll be replaced by a calculator + */ + int status = ioctl(i2c_file, I2C_SLAVE, si5338_addr); + if(status < 0) { + perror("Can't set the Slave Address"); + exit(1); + } + for(uint16_t i = 0; i < NUM_REGS_MAX; i++) { + change_si5338_reg(Reg_Store[i]); + } +} + +void start_oled() { + int status = ioctl(i2c_file, I2C_SLAVE, oled_addr); + if(status < 0) { + perror("Can't set the Slave Address"); + exit(1); + } + + +} + +void config_ltc2271_reg(Adc_reg rdata) { + uint32_t status = 0; + uint8_t addrval[2]; + addrval[0] = rdata.addr; + addrval[1] = rdata.val; + + status = write(adc1_file, addrval, 2); + if(status != 2) { + perror("Can't config adc1"); + exit(1); + } + status = write(adc2_file, addrval, 2); + if(status != 2) { + perror("Can't config adc2"); + exit(1); + } + printf("ADC Configured\n"); +} + +void init_spi() { + uint32_t status = 0; + + adc1_file = open(adc1_name, O_RDWR); + if(adc1_file < 0) { + perror("Can't open spidev"); + exit(1); + } + adc2_file = open(adc2_name, O_RDWR); + if(adc2_file < 0) { + perror("Can't open spidev"); + exit(1); + } + + status = ioctl(adc1_file, SPI_IOC_WR_MAX_SPEED_HZ, &SPISPEED); + if(status != 0) { + perror("Can't set spi speed"); + exit(1); + } + + status = ioctl(adc2_file, SPI_IOC_WR_MAX_SPEED_HZ, &SPISPEED); + if(status != 0) { + perror("Can't set spi speed"); + exit(1); + } + + /* We set the SPI word to 8bits but send 2 bits back to back */ +// status = ioctl(adc1_file, SPI_IOC_WR_BITS_PER_WORD, 1); +// if(status != 0) { +// perror("Can't set spi word"); +// exit(1); +// } +// +// status = ioctl(adc2_file, SPI_IOC_WR_BITS_PER_WORD, 1); +// if(status != 0) { +// perror("Can't set spi word"); +// exit(1); +// } + + for(uint8_t i = 0; i < ADC_NBREG; i++) { + config_ltc2271_reg(ADCregs[i]); + } +} + +int main() +{ + printf("Starting VNA Software\n"); + init_i2c(); + init_spi(); + + close_i2c(); + close_spi(); + return 0; +} diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/e4/006c60bc5bf3001914f8af9fb42ee8cd b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/e4/006c60bc5bf3001914f8af9fb42ee8cd new file mode 100644 index 0000000000000000000000000000000000000000..7bf40797d0d1eeea78f1f0111004164c831078b9 --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/e4/006c60bc5bf3001914f8af9fb42ee8cd @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2012 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "si5338.h" +#include "si5338_genconf.h" +#include "sys_init.h" +#include "ltc2271.h" + +void init_i2c() { + i2c_file = open(i2c_name, O_RDWR); + if(i2c_file < 0) { + perror("Can't open i2c Device 0"); + exit(1); + } + detect_si5338(); + init_si5338(); +} + +void close_i2c() { + close(i2c_file); +} + +void close_spi() { + close(adc1_file); + close(adc2_file); +} + +void detect_si5338() { + uint8_t cmd_buffer[6]; + + uint8_t rev = 0; + uint8_t type = 0; + uint8_t grade = 0; + + int status = ioctl(i2c_file, I2C_SLAVE, si5338_addr); + if(status < 0) { + perror("Can't set the Slave Address"); + exit(1); + } + + cmd_buffer[0] = REVID; + write(i2c_file, cmd_buffer, 1); + + /* We try to read the 6 first register to identify the chip */ + read(i2c_file, cmd_buffer, 6); + + rev = (cmd_buffer[0] & 0x7) ? 'B' : 'A'; + type = cmd_buffer[2] & 0x3F; + grade = ((cmd_buffer[3] & 0xF8) >> 3) + 64; /* We map the value to the Grade */ + + printf("Detecting SI5338 - Rev. %c - Type %d - Grade %c \n", rev, type, grade); +} + +void change_si5338_reg(Reg_Data rdata) { + uint8_t addrval[2]; + addrval[0] = rdata.Reg_Addr; + addrval[1] = rdata.Reg_Val; + + uint8_t status = 0; + + if(rdata.Reg_Mask == 0xFF) { + status = write(i2c_file, addrval, 2); + if(status != 2) { + perror("Can't config SI5338"); + exit(1); + } + } else if(rdata.Reg_Mask != 0x00) { + uint8_t oldval[1]; + oldval[0] = 0; + + status = write(i2c_file, addrval, 1); + if(status != 1) { + perror("Can't config SI5338"); + exit(1); + } + + status = read(i2c_file, oldval, 1); + if(status != 1) { + perror("Can't config SI5338"); + exit(1); + } + + addrval[1] = (oldval[0] & ~rdata.Reg_Mask) | (addrval[1] & rdata.Reg_Mask); + status = write(i2c_file, addrval, 2); + if(status != 2) { + perror("Can't config SI5338"); + exit(1); + } + } +} + +void init_si5338() { + /* We use the generated clock builder file + * WIll be replaced by a calculator + */ + int status = ioctl(i2c_file, I2C_SLAVE, si5338_addr); + if(status < 0) { + perror("Can't set the Slave Address"); + exit(1); + } + for(uint16_t i = 0; i < NUM_REGS_MAX; i++) { + change_si5338_reg(Reg_Store[i]); + } +} + +void start_oled() { + int status = ioctl(i2c_file, I2C_SLAVE, oled_addr); + if(status < 0) { + perror("Can't set the Slave Address"); + exit(1); + } + + +} + +void config_ltc2271_reg(Adc_reg rdata) { + uint32_t status = 0; + uint8_t addrval[2]; + addrval[0] = rdata.addr; + addrval[1] = rdata.val; + + status = write(adc1_file, addrval, 2); + if(status != 2) { + perror("can't config adc1"); + exit(1); + } + status = write(adc2_file, addrval, 2); + if(status != 2) { + perror("can't config adc2"); + exit(1); + } + printf("ADC Configured\n"); +} + +void init_spi() { + uint32_t status = 0; + + adc1_file = open(adc1_name, O_RDWR); + if(adc1_file < 0) { + perror("Can't open spidev"); + exit(1); + } + adc2_file = open(adc2_name, O_RDWR); + if(adc2_file < 0) { + perror("Can't open spidev"); + exit(1); + } + + status = ioctl(adc1_file, SPI_IOC_WR_MAX_SPEED_HZ, &SPISPEED); + if(status != 0) { + perror("Can't set spi speed"); + exit(1); + } + + status = ioctl(adc2_file, SPI_IOC_WR_MAX_SPEED_HZ, &SPISPEED); + if(status != 0) { + perror("Can't set spi speed"); + exit(1); + } + + /* We set the SPI word to 8bits but send 2 bits back to back */ +// status = ioctl(adc1_file, SPI_IOC_WR_BITS_PER_WORD, 1); +// if(status != 0) { +// perror("Can't set spi word"); +// exit(1); +// } +// +// status = ioctl(adc2_file, SPI_IOC_WR_BITS_PER_WORD, 1); +// if(status != 0) { +// perror("Can't set spi word"); +// exit(1); +// } + + for(uint8_t i = 0; i < ADC_NBREG; i++) { + config_ltc2271_reg(ADCregs[i]); + } +} + +int main() +{ + printf("Starting VNA Software\n"); + init_i2c(); + init_spi(); + + close_i2c(); + close_spi(); + return 0; +} diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/ea/a00ba3416df3001911e7b3b20042e599 b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/ea/a00ba3416df3001911e7b3b20042e599 new file mode 100644 index 0000000000000000000000000000000000000000..361701eb92d5fd615f0d0865b6e04562c03ecadd --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/ea/a00ba3416df3001911e7b3b20042e599 @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2012 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "si5338.h" +#include "si5338_genconf.h" +#include "sys_init.h" +#include "ltc2271.h" + +void init_i2c() { + i2c_file = open(i2c_name, O_RDWR); + if(i2c_file < 0) { + perror("Can't open i2c Device 0"); + exit(1); + } + detect_si5338(); + init_si5338(); +} + +void close_i2c() { + close(i2c_file); +} + +void close_spi() { + close(adc1_file); + close(adc2_file); +} + +void detect_si5338() { + uint8_t cmd_buffer[6]; + + uint8_t rev = 0; + uint8_t type = 0; + uint8_t grade = 0; + + int status = ioctl(i2c_file, I2C_SLAVE, si5338_addr); + if(status < 0) { + perror("Can't set the Slave Address"); + exit(1); + } + + cmd_buffer[0] = REVID; + write(i2c_file, cmd_buffer, 1); + + /* We try to read the 6 first register to identify the chip */ + read(i2c_file, cmd_buffer, 6); + + rev = (cmd_buffer[0] & 0x7) ? 'B' : 'A'; + type = cmd_buffer[2] & 0x3F; + grade = ((cmd_buffer[3] & 0xF8) >> 3) + 64; /* We map the value to the Grade */ + + printf("Detecting SI5338 - Rev. %c - Type %d - Grade %c \n", rev, type, grade); +} + +void change_si5338_reg(Reg_Data rdata) { + uint8_t addrval[2]; + addrval[0] = rdata.Reg_Addr; + addrval[1] = rdata.Reg_Val; + + uint8_t status = 0; + + if(rdata.Reg_Mask == 0xFF) { + status = write(i2c_file, addrval, 2); + if(status != 2) { + perror("Can't config SI5338"); + exit(1); + } + } else if(rdata.Reg_Mask != 0x00) { + uint8_t oldval[1]; + oldval[0] = 0; + + status = write(i2c_file, addrval, 1); + if(status != 1) { + perror("Can't config SI5338"); + exit(1); + } + + status = read(i2c_file, oldval, 1); + if(status != 1) { + perror("Can't config SI5338"); + exit(1); + } + + addrval[1] = (oldval[0] & ~rdata.Reg_Mask) | (addrval[1] & rdata.Reg_Mask); + status = write(i2c_file, addrval, 2); + if(status != 2) { + perror("Can't config SI5338"); + exit(1); + } + } +} + +void init_si5338() { + /* We use the generated clock builder file + * WIll be replaced by a calculator + */ + int status = ioctl(i2c_file, I2C_SLAVE, si5338_addr); + if(status < 0) { + perror("Can't set the Slave Address"); + exit(1); + } + for(uint16_t i = 0; i < NUM_REGS_MAX; i++) { + change_si5338_reg(Reg_Store[i]); + } +} + +void start_oled() { + int status = ioctl(i2c_file, I2C_SLAVE, oled_addr); + if(status < 0) { + perror("Can't set the Slave Address"); + exit(1); + } + + +} + +void config_ltc2271_reg(Adc_reg rdata) { + uint32_t status = 0; + uint8_t addrval[2]; + addrval[0] = rdata.addr; + addrval[1] = rdata.val; + + status = write(adc1_file, addrval, 2); + if(status != 2) { + perror("Can't config adc1"); + exit(1); + } + status = write(adc2_file, addrval, 2); + if(status != 2) { + perror("Can't config adc2"); + exit(1); + } + printf("ADC Configured\n"); +} + +void init_spi() { + uint32_t status = 0; + + adc1_file = open(adc1_name, O_RDWR); + if(adc1_file < 0) { + perror("Can't open spidev"); + exit(1); + } + adc2_file = open(adc2_name, O_RDWR); + if(adc2_file < 0) { + perror("Can't open spidev"); + exit(1); + } + + /*status = ioctl(adc1_file, SPI_IOC_WR_MAX_SPEED_HZ, &SPISPEED); + if(status != 0) { + perror("Can't set spi speed"); + exit(1); + } + + status = ioctl(adc2_file, SPI_IOC_WR_MAX_SPEED_HZ, &SPISPEED); + if(status != 0) { + perror("Can't set spi speed"); + exit(1); + }*/ + + /* We set the SPI word to 8bits but send 2 bits back to back */ +// status = ioctl(adc1_file, SPI_IOC_WR_BITS_PER_WORD, 1); +// if(status != 0) { +// perror("Can't set spi word"); +// exit(1); +// } +// +// status = ioctl(adc2_file, SPI_IOC_WR_BITS_PER_WORD, 1); +// if(status != 0) { +// perror("Can't set spi word"); +// exit(1); +// } + + for(uint8_t i = 0; i < ADC_NBREG; i++) { + config_ltc2271_reg(ADCregs[i]); + } +} + +int main() +{ + printf("Starting VNA Software\n"); + init_i2c(); + init_spi(); + + close_i2c(); + close_spi(); + return 0; +} diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/ee/c07cf1e75af3001914f8af9fb42ee8cd b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/ee/c07cf1e75af3001914f8af9fb42ee8cd new file mode 100644 index 0000000000000000000000000000000000000000..5902437001a2965fe8cbff12db50218f4a523b34 --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.history/ee/c07cf1e75af3001914f8af9fb42ee8cd @@ -0,0 +1,213 @@ +/* + * Copyright (c) 2012 Xilinx, Inc. All rights reserved. + * + * Xilinx, Inc. + * XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" AS A + * COURTESY TO YOU. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION AS + * ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION OR + * STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION + * IS FREE FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE + * FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. + * XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO + * THE ADEQUACY OF THE IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO + * ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE + * FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY + * AND FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "si5338.h" +#include "si5338_genconf.h" +#include "sys_init.h" +#include "ltc2271.h" + +void init_i2c() { + i2c_file = open(i2c_name, O_RDWR); + if(i2c_file < 0) { + perror("Can't open i2c Device 0"); + exit(1); + } + detect_si5338(); + init_si5338(); +} + +void close_i2c() { + close(i2c_file); +} + +void close_spi() { + close(adc1_file); + close(adc2_file); +} + +void detect_si5338() { + uint8_t cmd_buffer[6]; + + uint8_t rev = 0; + uint8_t type = 0; + uint8_t grade = 0; + + int status = ioctl(i2c_file, I2C_SLAVE, si5338_addr); + if(status < 0) { + perror("Can't set the Slave Address"); + exit(1); + } + + cmd_buffer[0] = REVID; + write(i2c_file, cmd_buffer, 1); + + /* We try to read the 6 first register to identify the chip */ + read(i2c_file, cmd_buffer, 6); + + rev = (cmd_buffer[0] & 0x7) ? 'B' : 'A'; + type = cmd_buffer[2] & 0x3F; + grade = ((cmd_buffer[3] & 0xF8) >> 3) + 64; /* We map the value to the Grade */ + + printf("Detecting SI5338 - Rev. %c - Type %d - Grade %c \n", rev, type, grade); +} + +void change_si5338_reg(Reg_Data rdata) { + uint8_t addrval[2]; + addrval[0] = rdata.Reg_Addr; + addrval[1] = rdata.Reg_Val; + + uint8_t status = 0; + + if(rdata.Reg_Mask == 0xFF) { + status = write(i2c_file, addrval, 2); + if(status != 2) { + perror("Can't config SI5338"); + exit(1); + } + } else if(rdata.Reg_Mask != 0x00) { + uint8_t oldval[1]; + oldval[0] = 0; + + status = write(i2c_file, addrval, 1); + if(status != 1) { + perror("Can't config SI5338"); + exit(1); + } + + status = read(i2c_file, oldval, 1); + if(status != 1) { + perror("Can't config SI5338"); + exit(1); + } + + addrval[1] = (oldval[0] & ~rdata.Reg_Mask) | (addrval[1] & rdata.Reg_Mask); + status = write(i2c_file, addrval, 2); + if(status != 2) { + perror("Can't config SI5338"); + exit(1); + } + } +} + +void init_si5338() { + /* We use the generated clock builder file + * WIll be replaced by a calculator + */ + int status = ioctl(i2c_file, I2C_SLAVE, si5338_addr); + if(status < 0) { + perror("Can't set the Slave Address"); + exit(1); + } + for(uint16_t i = 0; i < NUM_REGS_MAX; i++) { + change_si5338_reg(Reg_Store[i]); + } +} + +void start_oled() { + int status = ioctl(i2c_file, I2C_SLAVE, oled_addr); + if(status < 0) { + perror("Can't set the Slave Address"); + exit(1); + } + + +} + +void config_ltc2271_reg(Adc_reg rdata) { + uint32_t status = 0; + uint8_t addrval[2]; + addrval[0] = rdata.addr; + addrval[1] = rdata.val; + + status = write(adc1_file, addrval, 2); + if(status != 2) { + perror("can't config adc1"); + exit(1); + } + status = write(adc2_file, addrval, 2); + if(status != 2) { + perror("can't config adc2"); + exit(1); + } +} + +void init_spi() { + uint32_t status = 0; + + adc1_file = open(adc1_name, O_RDWR); + if(adc1_file < 0) { + perror("Can't open spidev"); + exit(1); + } + adc2_file = open(adc2_name, O_RDWR); + if(adc2_file < 0) { + perror("Can't open spidev"); + exit(1); + } + + status = ioctl(adc1_file, SPI_IOC_WR_MAX_SPEED_HZ, &SPISPEED); + if(status != 0) { + perror("Can't set spi speed"); + exit(1); + } + + status = ioctl(adc2_file, SPI_IOC_WR_MAX_SPEED_HZ, &SPISPEED); + if(status != 0) { + perror("Can't set spi speed"); + exit(1); + } + + /* We set the SPI word to 8bits but send 2 bits back to back */ +// status = ioctl(adc1_file, SPI_IOC_WR_BITS_PER_WORD, 1); +// if(status != 0) { +// perror("Can't set spi word"); +// exit(1); +// } +// +// status = ioctl(adc2_file, SPI_IOC_WR_BITS_PER_WORD, 1); +// if(status != 0) { +// perror("Can't set spi word"); +// exit(1); +// } + + for(uint8_t i = 0; i < ADC_NBREG; i++) { + config_ltc2271_reg(ADCregs[i]); + } +} + +int main() +{ + printf("Starting VNA Software\n"); + init_i2c(); + init_spi(); + + close_i2c(); + close_spi(); + return 0; +} diff --git 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a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources index ff4cdbcc04eece6ef5bb5668b3172fbfc3da2297..6395066031e63234de332bf7ae84157e0073f305 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/.safetable/org.eclipse.core.resources differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/13.snap b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/13.snap new file mode 100644 index 0000000000000000000000000000000000000000..d029249663662e2edbd1f217e100526983e33fe1 Binary files /dev/null and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.resources/13.snap differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.xilinx.sdk.utils.prefs b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.xilinx.sdk.utils.prefs index d2f682dfa9f2ba79f8da6e9f4fc477c5d981668b..0de0bd085422673d2879500c8076d9e9cb6982c1 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.xilinx.sdk.utils.prefs +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/com.xilinx.sdk.utils.prefs @@ -1,2 +1,2 @@ -com.xilinx.sdk.preference.invokecount=5 +com.xilinx.sdk.preference.invokecount=13 eclipse.preferences.version=1 diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs index 0d5b3378fe844ace67c87cb8c34a58d443de87f8..a0a6d257691b5f011d5b0be2a9e329ecac8112ff 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.core.runtime/.settings/org.eclipse.debug.ui.prefs @@ -3,5 +3,6 @@ org.eclipse.debug.ui.MemoryView.orientation=0 org.eclipse.debug.ui.PREF_LAUNCH_PERSPECTIVES=\n\n org.eclipse.debug.ui.switch_to_perspective=always pref_state_memento.org.eclipse.debug.ui.DebugVieworg.eclipse.debug.ui.DebugView=\n +pref_state_memento.org.eclipse.debug.ui.VariableView=\n\n\n\n\n\n preferredDetailPanes=DefaultDetailPane\:DefaultDetailPane|org.eclipse.tcf.debug.DetailPaneFactory\:org.eclipse.tcf.debug.DetailPaneFactory| preferredTargets=default,org.eclipse.tcf.debug.toggleTCFBreakpoint\:default|org.eclipse.cdt.debug.ui.toggleCBreakpointTarget,org.eclipse.cdt.debug.ui.toggleCDynamicPrintfTarget,org.eclipse.tcf.debug.toggleTCFBreakpoint\:org.eclipse.tcf.debug.toggleTCFBreakpoint|org.eclipse.tcf.debug.toggleTCFBreakpoint\:org.eclipse.tcf.debug.toggleTCFBreakpoint|org.eclipse.cdt.debug.ui.toggleCBreakpointTarget,org.eclipse.cdt.debug.ui.toggleCDynamicPrintfTarget\:org.eclipse.cdt.debug.ui.toggleCBreakpointTarget| diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.e4.workbench/workbench.xmi b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.e4.workbench/workbench.xmi index 8706572886e2903e3968a21a9eab146b6f0cebb4..bcab62d8360e0c124b0aef8bbd01b0e5cf1e9d85 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.e4.workbench/workbench.xmi +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.e4.workbench/workbench.xmi @@ -1,9 +1,9 @@ - - + + activeSchemeId:org.eclipse.ui.defaultAcceleratorConfiguration ModelMigrationProcessor.001 - + @@ -12,9 +12,9 @@ topLevel shellMaximized - - - + + + persp.actionSet:org.eclipse.ui.cheatsheets.actionSet persp.actionSet:org.eclipse.rse.core.search.searchActionSet @@ -65,45 +65,45 @@ persp.newWizSC:com.xilinx.sdk.profile.ui.wizards.ZpeProjectWizard persp.newWizSC:com.xilinx.sdk.sw.ui.NewBspWizard persp.actionSet:org.eclipse.debug.ui.debugActionSet - - - - - - - + + + + + + + - - + + - - - - - - - + + + + + + + - - - - - - - + + + + + + + - + Debug - - + + - + persp.actionSet:org.eclipse.ui.cheatsheets.actionSet persp.actionSet:org.eclipse.rse.core.search.searchActionSet @@ -137,1437 +137,1619 @@ persp.actionSet:org.eclipse.debug.ui.breakpointActionSet persp.viewSC:org.eclipse.pde.runtime.LogView persp.showIn:org.eclipse.egit.ui.RepositoriesView - - - - - + + + + + org.eclipse.e4.primaryNavigationStack - active - noFocus - - + + - - + + - - - - - - - - - + + + + + + + + + - - - + + + org.eclipse.e4.secondaryNavigationStack - - - + + + - - + + org.eclipse.e4.secondaryDataStack - - - - - - - - + + + + + + + + - + Debug - - + + - - - - + + + + - + View categoryTag:Help - + View categoryTag:General - + ViewMenu menuContribution:menu - + - + View categoryTag:Help - - + + org.eclipse.e4.primaryDataStack EditorStack - - + active + noFocus + + Editor org.eclipse.cdt.ui.editor.CEditor removeOnHide + active + + menuContribution:popup + popup:#CEditorContext + popup:org.eclipse.cdt.ui.editor.CEditor.EditorContext + popup:#AbstractTextEditorContext + + + menuContribution:popup + popup:#CEditorRulerContext + popup:org.eclipse.cdt.ui.editor.CEditor.RulerContext + popup:#AbstractTextEditorRulerContext + + + menuContribution:popup + popup:#OverviewRulerContext + - - + + + Editor + org.eclipse.cdt.ui.editor.CEditor + removeOnHide + + + Editor org.eclipse.cdt.ui.editor.CEditor removeOnHide - + View categoryTag:General - + ViewMenu menuContribution:menu - + + menuContribution:popup + popup:org.eclipse.ui.navigator.ProjectExplorer#PopupMenu + + - + View categoryTag:C/C++ - + View categoryTag:General - + View categoryTag:General - + - + View categoryTag:General - + ViewMenu menuContribution:menu - + + menuContribution:popup + popup:org.eclipse.ui.views.ProblemView + popup:org.eclipse.ui.ide.MarkersView + + - + View categoryTag:General - + ViewMenu menuContribution:menu - + - + View categoryTag:General - + ViewMenu menuContribution:menu - + + menuContribution:popup + popup:org.eclipse.cdt.ui.CDTGlobalBuildConsole + + + menuContribution:popup + popup:org.eclipse.cdt.ui.CDTBuildConsole + + - + View categoryTag:General - + ViewMenu menuContribution:menu - + - + View categoryTag:General - + ViewMenu menuContribution:menu - + + menuContribution:popup + popup:#TranslationUnitOutlinerContext + + - + View categoryTag:Xilinx - + ViewMenu menuContribution:menu - + - + View categoryTag:Xilinx - + ViewMenu menuContribution:menu - + + menuContribution:popup + popup:com.xilinx.sdk.targetmanager.ui.TargetManagementView + + - + View categoryTag:Xilinx - + ViewMenu menuContribution:menu - + - + View categoryTag:C/C++ Packs - + View categoryTag:Make - + View categoryTag:Debug - active - activeOnClose - + ViewMenu menuContribution:menu - + + menuContribution:popup + popup:org.eclipse.debug.ui.DebugView + + + menuContribution:popup + popup:org.eclipse.debug.ui.DebugView + + - + View categoryTag:Debug - + ViewMenu menuContribution:menu - + + menuContribution:popup + popup:org.eclipse.debug.ui.VariableView.detail + + + menuContribution:popup + popup:org.eclipse.debug.ui.VariableView + + - + View categoryTag:Debug - + ViewMenu menuContribution:menu - + + menuContribution:popup + popup:org.eclipse.debug.ui.VariableView.detail + + + menuContribution:popup + popup:org.eclipse.debug.ui.BreakpointView + + - + View categoryTag:Debug - + View categoryTag:Debug - + ViewMenu menuContribution:menu - + - + View categoryTag:Xilinx - + ViewMenu menuContribution:menu - + - + View categoryTag:Xilinx - + View categoryTag:Debug - + View categoryTag:Debug - + ViewMenu menuContribution:menu - + - + View categoryTag:Debug - + View categoryTag:Debug - + View categoryTag:Debug - + View categoryTag:Debug - + View categoryTag:Debug - + View categoryTag:Debug - + ViewMenu menuContribution:menu - + - - + + toolbarSeparator - + - + Draggable - + + Opaque + + + Opaque + + + Opaque + + + Opaque + + + Opaque + + + Opaque + + + Opaque + + + + Opaque + + + Opaque + + + Opaque + + + Opaque + + + Opaque + + + Opaque + + + Opaque + - + toolbarSeparator - + - + Draggable + + Opaque + + + Opaque + + + Opaque + + + Opaque + + + Opaque + - + Draggable + + Opaque + + + Opaque + + + Opaque + + + Opaque + - + Draggable + + Opaque + + + Opaque + + + Opaque + - + Draggable + + Opaque + + + Opaque + + + Opaque + + + Opaque + + + Opaque + + + Opaque + - + toolbarSeparator - + - + Draggable - + + Opaque + + + Opaque + + + Opaque + + + Opaque + + + Opaque + + + + Opaque + + + Opaque + + + Opaque + - + + Draggable + + toolbarSeparator - + - + toolbarSeparator - + - + Draggable + + Opaque + + + Opaque + - + stretch SHOW_RESTORE_MENU - + Draggable HIDEABLE SHOW_RESTORE_MENU - - + + stretch - + Draggable - + Draggable - - + + TrimStack Draggable - + - - - - - + + + + + platform:gtk - - - - - - - - - - - - - + + + + + + + + + + + + + - - - - - - + + + + + + - - - - - - - - - + + + + + + + + + - - + + platform:gtk - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - + + + + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - - + + - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - + + + + + + + + + + + + + - - - - - - - + + + + + + + - - - + + + - - - + + + - - - - - - + + + + + + - - - - - - - - - - + + + + + + + + + + - - - - - - - - + + + + + + + + - - + + - - - - + + + + - - + + - - - + + + - - - - + + + + - - - - + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - + + + + + + + + + - - - + + + - - + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Editor - + View categoryTag:Xilinx - + View categoryTag:Oprofile - + View categoryTag:Xilinx - + View categoryTag:Xilinx - + View categoryTag:Xilinx - + View categoryTag:Xilinx - + View categoryTag:Xilinx - + View categoryTag:Xilinx - + View categoryTag:Xilinx - + View categoryTag:Xilinx - + View categoryTag:Xilinx - + View categoryTag:Xilinx - + View categoryTag:Xilinx - + View categoryTag:Xilinx - + View categoryTag:Xilinx - + View categoryTag:Xilinx - + View categoryTag:C/C++ Packs - + View categoryTag:C/C++ Packs - + View categoryTag:C/C++ Packs - + View categoryTag:C/C++ Packs - + View categoryTag:C/C++ Packs - + View categoryTag:C/C++ Packs - + View categoryTag:C/C++ - + View categoryTag:Debug - + View categoryTag:Debug - + View categoryTag:Debug - + View categoryTag:Debug - + View categoryTag:Debug - + View categoryTag:Make - + View categoryTag:C/C++ - + View categoryTag:C/C++ - + View categoryTag:C/C++ - + View categoryTag:C/C++ - + View categoryTag:C/C++ - + View categoryTag:General - + View categoryTag:Debug - + View categoryTag:Debug - + View categoryTag:Debug - + View categoryTag:Debug - + View categoryTag:Debug - + View categoryTag:Debug - + View categoryTag:Debug - + View categoryTag:Git - + View categoryTag:Git - + View categoryTag:Git - + View categoryTag:Git - + View categoryTag:Git - + View categoryTag:Help - + View categoryTag:Charts - + View categoryTag:Profiling - + View categoryTag:Connections - + View categoryTag:Remote Systems - + View categoryTag:Remote Systems - + View categoryTag:Remote Systems - + View categoryTag:Remote Systems - + View categoryTag:Remote Systems - + View categoryTag:Remote Systems - + View categoryTag:Remote Systems - + View categoryTag:Remote Systems - + View categoryTag:General - + View categoryTag:General - + View categoryTag:Debug - + View categoryTag:Debug - + View categoryTag:Team - + View categoryTag:Team - + View categoryTag:Terminal - + View categoryTag:LTTng - + View categoryTag:LTTng - + View categoryTag:LTTng - + View categoryTag:LTTng - + View categoryTag:LTTng - + View categoryTag:LTTng - + View categoryTag:LTTng - + View categoryTag:Network Tracing - + View categoryTag:Tracing - + View categoryTag:Tracing - + View categoryTag:Tracing - + View categoryTag:Tracing - + View categoryTag:Tracing - + View categoryTag:Tracing - + View categoryTag:Tracing - + View categoryTag:Tracing - + View categoryTag:Tracing - + View categoryTag:General - + View categoryTag:General - + View categoryTag:Help - + View categoryTag:General - + View categoryTag:General - + View categoryTag:General - + View categoryTag:General - + View categoryTag:General - + View categoryTag:General - + View categoryTag:General - + View categoryTag:General - + View categoryTag:General - + View categoryTag:General - - - glue - move_after:PerspectiveSpacer - SHOW_RESTORE_MENU - - - move_after:Spacer Glue - HIDEABLE - SHOW_RESTORE_MENU - - - glue - move_after:SearchField - SHOW_RESTORE_MENU - - - + persp.actionSet:org.eclipse.ui.cheatsheets.actionSet persp.actionSet:org.eclipse.rse.core.search.searchActionSet @@ -1617,881 +1799,890 @@ persp.newWizSC:com.xilinx.sdk.appwiz.AppWizard persp.newWizSC:com.xilinx.sdk.profile.ui.wizards.ZpeProjectWizard persp.newWizSC:com.xilinx.sdk.sw.ui.NewBspWizard - - - - - - - + + + + + + + - - + + - - - - - - - + + + + + + + - - - - - - - + + + + + + + - - + + - - - - - + + + + + - - - - - - - - - - - - - + + + + + + + + + + + + + - - - - - - - + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + 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- - - - - - - - - - + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + - - - - + + + + - - + + - - - - - - - + + + + + + + - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml new file mode 100644 index 0000000000000000000000000000000000000000..aa26784293bfa13c78cdfb5c2c316d817b156f98 --- /dev/null +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.ltk.ui.refactoring/dialog_settings.xml @@ -0,0 +1,7 @@ + +
+
+ + +
+
diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml index 0680e99ab4d7b3c3a6dfee7dec4770298e9f1069..6dcd79d5bd8dcb850d3b5c204ecbfa424ca07990 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.ui.ide/dialog_settings.xml @@ -5,6 +5,6 @@ - +
diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml index 258d27c5b574a930462274b7e96f476fa69270b5..5e0481bef871589119c86258c2c0aa6a4fc12f0a 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/.plugins/org.eclipse.ui.workbench/dialog_settings.xml @@ -1,8 +1,8 @@
- - + +
diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/version.ini b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/version.ini index d91f8e77792701d663c2a4a0bcadd5f5255290fb..21b49b2d270ffa0d00f57a569b9b5a90db24b6e5 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/version.ini +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/.metadata/version.ini @@ -1,3 +1,3 @@ -#Sat Oct 19 01:24:52 CEST 2019 +#Sun Oct 20 22:57:05 CEST 2019 org.eclipse.core.runtime=2 org.eclipse.platform=4.6.1.v20160907-1200 diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/hello/Debug/hello.elf b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/hello/Debug/hello.elf index c7066c22bd2eeb17f3c623b2155c6bf39fcafcf2..86c137c5b5d225a6f6b5bb3a78930634312b79fe 100755 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/hello/Debug/hello.elf and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/hello/Debug/hello.elf differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/hello/Debug/hello.elf.size b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/hello/Debug/hello.elf.size index 9a1930380fceb44624ae6e8dab245817bac80199..559f843489cb058c9d1c8522e3763c0a45b0bd09 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/hello/Debug/hello.elf.size +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/hello/Debug/hello.elf.size @@ -1,2 +1,2 @@ text data bss dec hex filename - 3381 1402 16 4799 12bf hello.elf + 3237 1406 16 4659 1233 hello.elf diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/hello/src/helloworld.c b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/hello/src/helloworld.c index 5902437001a2965fe8cbff12db50218f4a523b34..172c37be0f41ea7d4c4913bf9955cbc6d24f5a9d 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/hello/src/helloworld.c +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/hello/src/helloworld.c @@ -147,14 +147,15 @@ void config_ltc2271_reg(Adc_reg rdata) { status = write(adc1_file, addrval, 2); if(status != 2) { - perror("can't config adc1"); + perror("Can't config adc1"); exit(1); } status = write(adc2_file, addrval, 2); if(status != 2) { - perror("can't config adc2"); + perror("Can't config adc2"); exit(1); } + printf("ADC Configured\n"); } void init_spi() { @@ -171,7 +172,7 @@ void init_spi() { exit(1); } - status = ioctl(adc1_file, SPI_IOC_WR_MAX_SPEED_HZ, &SPISPEED); + /*status = ioctl(adc1_file, SPI_IOC_WR_MAX_SPEED_HZ, &SPISPEED); if(status != 0) { perror("Can't set spi speed"); exit(1); @@ -183,18 +184,17 @@ void init_spi() { exit(1); } - /* We set the SPI word to 8bits but send 2 bits back to back */ -// status = ioctl(adc1_file, SPI_IOC_WR_BITS_PER_WORD, 1); -// if(status != 0) { -// perror("Can't set spi word"); -// exit(1); -// } -// -// status = ioctl(adc2_file, SPI_IOC_WR_BITS_PER_WORD, 1); -// if(status != 0) { -// perror("Can't set spi word"); -// exit(1); -// } + status = ioctl(adc1_file, SPI_IOC_WR_BITS_PER_WORD, &bits); + if(status != 0) { + perror("Can't set spi word"); + exit(1); + } + + status = ioctl(adc2_file, SPI_IOC_WR_BITS_PER_WORD, &bits); + if(status != 0) { + perror("Can't set spi word"); + exit(1); + }*/ for(uint8_t i = 0; i < ADC_NBREG; i++) { config_ltc2271_reg(ADCregs[i]); diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/hello/src/ltc2271.h b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/hello/src/ltc2271.h index 0eb7d54922a4e89b6f70b408d4c5110d57a4d1fa..e2c470628a6ecb7b8fb6c78c55a424239bc339c5 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/hello/src/ltc2271.h +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/hello/src/ltc2271.h @@ -11,6 +11,7 @@ #include uint32_t SPISPEED = 1000000; +uint8_t bits = 8; typedef struct Adc_reg{ uint8_t addr; diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/mz_petalinux_wrapper.hdf b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/mz_petalinux_wrapper.hdf index 0f684eac521969b0bec5301cf8190cff95866d02..d1f3f9ba14a675ec24b102894abe8dff3cc74a90 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/mz_petalinux_wrapper.hdf and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/mz_petalinux_wrapper.hdf differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/mz_petalinux_wrapper_hw_platform_0/mz_petalinux_wrapper.bit b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/mz_petalinux_wrapper_hw_platform_0/mz_petalinux_wrapper.bit index f3d5cd03d6129b92e0b51c92d3080bfe38461117..8a6368109972fbb675217c961969f94651507509 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/mz_petalinux_wrapper_hw_platform_0/mz_petalinux_wrapper.bit and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/mz_petalinux_wrapper_hw_platform_0/mz_petalinux_wrapper.bit differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/mz_petalinux_wrapper_hw_platform_0/ps7_init.c b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/mz_petalinux_wrapper_hw_platform_0/ps7_init.c index 1464a72c78182d435d8840e6842c1d36a5a1897c..1ef86a3b326467098279787f6d0da24b895e0152 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/mz_petalinux_wrapper_hw_platform_0/ps7_init.c +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/mz_petalinux_wrapper_hw_platform_0/ps7_init.c @@ -345,12 +345,12 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. ==> MASK : 0x00003F00U VAL : 0x00001400U // .. EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF8000158[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF8000158[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000158[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U // .. SRCSEL = 0x0 // .. ==> 0XF8000158[5:4] = 0x00000000U // .. ==> MASK : 0x00000030U VAL : 0x00000000U @@ -358,7 +358,7 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. ==> 0XF8000158[13:8] = 0x00000032U // .. ==> MASK : 0x00003F00U VAL : 0x00003200U // .. - EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003201U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003202U), // .. .. START: TRACE CLOCK // .. .. FINISH: TRACE CLOCK // .. .. CLKACT = 0x1 @@ -409,12 +409,12 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. .. SDI1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. SPI0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. SPI1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U // .. .. CAN0_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[16:16] = 0x00000000U // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U @@ -443,7 +443,7 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. .. ==> 0XF800012C[24:24] = 0x00000001U // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U // .. .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC444DU), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC844DU), // .. FINISH: CLOCK CONTROL SLCR REGISTERS // .. START: THIS SHOULD BE BLANK // .. FINISH: THIS SHOULD BE BLANK @@ -4463,12 +4463,12 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. ==> MASK : 0x00003F00U VAL : 0x00001400U // .. EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF8000158[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF8000158[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000158[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U // .. SRCSEL = 0x0 // .. ==> 0XF8000158[5:4] = 0x00000000U // .. ==> MASK : 0x00000030U VAL : 0x00000000U @@ -4476,7 +4476,7 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. ==> 0XF8000158[13:8] = 0x00000032U // .. ==> MASK : 0x00003F00U VAL : 0x00003200U // .. - EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003201U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003202U), // .. .. START: TRACE CLOCK // .. .. FINISH: TRACE CLOCK // .. .. CLKACT = 0x1 @@ -4527,12 +4527,12 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. .. SDI1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. SPI0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. SPI1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U // .. .. CAN0_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[16:16] = 0x00000000U // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U @@ -4561,7 +4561,7 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. .. ==> 0XF800012C[24:24] = 0x00000001U // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U // .. .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC444DU), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC844DU), // .. FINISH: CLOCK CONTROL SLCR REGISTERS // .. START: THIS SHOULD BE BLANK // .. FINISH: THIS SHOULD BE BLANK @@ -8734,12 +8734,12 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. ==> MASK : 0x00003F00U VAL : 0x00001400U // .. EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF8000158[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF8000158[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000158[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U // .. SRCSEL = 0x0 // .. ==> 0XF8000158[5:4] = 0x00000000U // .. ==> MASK : 0x00000030U VAL : 0x00000000U @@ -8747,7 +8747,7 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. ==> 0XF8000158[13:8] = 0x00000032U // .. ==> MASK : 0x00003F00U VAL : 0x00003200U // .. - EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003201U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003202U), // .. .. START: TRACE CLOCK // .. .. FINISH: TRACE CLOCK // .. .. CLKACT = 0x1 @@ -8798,12 +8798,12 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. .. SDI1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. SPI0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. SPI1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U // .. .. CAN0_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[16:16] = 0x00000000U // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U @@ -8832,7 +8832,7 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. .. ==> 0XF800012C[24:24] = 0x00000001U // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U // .. .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC444DU), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC844DU), // .. FINISH: CLOCK CONTROL SLCR REGISTERS // .. START: THIS SHOULD BE BLANK // .. FINISH: THIS SHOULD BE BLANK diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/mz_petalinux_wrapper_hw_platform_0/ps7_init.html b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/mz_petalinux_wrapper_hw_platform_0/ps7_init.html index fcd61f6a602f19ff555cd006d822d28ca0216404..c10a36353f4d5879976f5fc9f8523fb05a27cdb2 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/mz_petalinux_wrapper_hw_platform_0/ps7_init.html +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/mz_petalinux_wrapper_hw_platform_0/ps7_init.html @@ -6907,10 +6907,10 @@ SLCR_LOCK 1
-1 +0 -1 +0 SPI 0 reference clock active: 0: Clock is disabled 1: Clock is enabled @@ -6927,10 +6927,10 @@ SLCR_LOCK 2 -0 +1 -0 +2 SPI 1 reference clock active: 0: Clock is disabled 1: Clock is enabled @@ -6990,7 +6990,7 @@ SLCR_LOCK -3201 +3202 SPI Ref Clock Control @@ -7616,10 +7616,10 @@ SLCR_LOCK 4000 -1 +0 -4000 +0 SPI 0 AMBA Clock control 0: disable, 1: enable @@ -7636,10 +7636,10 @@ SLCR_LOCK 8000 -0 +1 -0 +8000 SPI 1 AMBA Clock control 0: disable, 1: enable @@ -7839,7 +7839,7 @@ SLCR_LOCK -1ec444d +1ec844d AMBA Peripheral Clock Control @@ -52448,10 +52448,10 @@ SLCR_LOCK 1 -1 +0 -1 +0 SPI 0 reference clock active: 0: Clock is disabled 1: Clock is enabled @@ -52468,10 +52468,10 @@ SLCR_LOCK 2 -0 +1 -0 +2 SPI 1 reference clock active: 0: Clock is disabled 1: Clock is enabled @@ -52531,7 +52531,7 @@ SLCR_LOCK -3201 +3202 SPI Ref Clock Control @@ -53157,10 +53157,10 @@ SLCR_LOCK 4000 -1 +0 -4000 +0 SPI 0 AMBA Clock control 0: disable, 1: enable @@ -53177,10 +53177,10 @@ SLCR_LOCK 8000 -0 +1 -0 +8000 SPI 1 AMBA Clock control 0: disable, 1: enable @@ -53380,7 +53380,7 @@ SLCR_LOCK -1ec444d +1ec844d AMBA Peripheral Clock Control @@ -99117,10 +99117,10 @@ SLCR_LOCK 1 -1 +0 -1 +0 SPI 0 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. @@ -99137,10 +99137,10 @@ SLCR_LOCK 2 -0 +1 -0 +2 SPI 1 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. @@ -99200,7 +99200,7 @@ SLCR_LOCK -3201 +3202 SPI Reference Clock Control @@ -99826,10 +99826,10 @@ SLCR_LOCK 4000 -1 +0 -4000 +0 SPI 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. @@ -99846,10 +99846,10 @@ SLCR_LOCK 8000 -0 +1 -0 +8000 SPI 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. @@ -100049,7 +100049,7 @@ SLCR_LOCK -1ec444d +1ec844d AMBA Peripheral Clock Control diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/mz_petalinux_wrapper_hw_platform_0/ps7_init.tcl b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/mz_petalinux_wrapper_hw_platform_0/ps7_init.tcl index 8cf2f177b0ee0f2c3d80c64910d9a3032198281a..24291b4fe2ecfca5e4f47e6f90fa87c07695b715 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/mz_petalinux_wrapper_hw_platform_0/ps7_init.tcl +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/mz_petalinux_wrapper_hw_platform_0/ps7_init.tcl @@ -33,11 +33,11 @@ proc ps7_clock_init_data_3_0 {} { mask_write 0XF800014C 0x00003F31 0x00000501 mask_write 0XF8000150 0x00003F33 0x00002801 mask_write 0XF8000154 0x00003F33 0x00001402 - mask_write 0XF8000158 0x00003F33 0x00003201 + mask_write 0XF8000158 0x00003F33 0x00003202 mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000170 0x03F03F30 0x00200500 mask_write 0XF80001C4 0x00000001 0x00000001 - mask_write 0XF800012C 0x01FFCCCD 0x01EC444D + mask_write 0XF800012C 0x01FFCCCD 0x01EC844D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_3_0 {} { @@ -269,11 +269,11 @@ proc ps7_clock_init_data_2_0 {} { mask_write 0XF800014C 0x00003F31 0x00000501 mask_write 0XF8000150 0x00003F33 0x00002801 mask_write 0XF8000154 0x00003F33 0x00001402 - mask_write 0XF8000158 0x00003F33 0x00003201 + mask_write 0XF8000158 0x00003F33 0x00003202 mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000170 0x03F03F30 0x00200500 mask_write 0XF80001C4 0x00000001 0x00000001 - mask_write 0XF800012C 0x01FFCCCD 0x01EC444D + mask_write 0XF800012C 0x01FFCCCD 0x01EC844D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_2_0 {} { @@ -506,11 +506,11 @@ proc ps7_clock_init_data_1_0 {} { mask_write 0XF800014C 0x00003F31 0x00000501 mask_write 0XF8000150 0x00003F33 0x00002801 mask_write 0XF8000154 0x00003F33 0x00001402 - mask_write 0XF8000158 0x00003F33 0x00003201 + mask_write 0XF8000158 0x00003F33 0x00003202 mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000170 0x03F03F30 0x00200500 mask_write 0XF80001C4 0x00000001 0x00000001 - mask_write 0XF800012C 0x01FFCCCD 0x01EC444D + mask_write 0XF800012C 0x01FFCCCD 0x01EC844D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_1_0 {} { diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/mz_petalinux_wrapper_hw_platform_0/ps7_init_gpl.c b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/mz_petalinux_wrapper_hw_platform_0/ps7_init_gpl.c index bbf216942eb969339c81546949727a55bfc2789a..1db7d3041ef92a17785c88a6d558975a9b47bd17 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/mz_petalinux_wrapper_hw_platform_0/ps7_init_gpl.c +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/mz_petalinux_wrapper_hw_platform_0/ps7_init_gpl.c @@ -336,12 +336,12 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. ==> MASK : 0x00003F00U VAL : 0x00001400U // .. EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF8000158[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF8000158[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000158[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U // .. SRCSEL = 0x0 // .. ==> 0XF8000158[5:4] = 0x00000000U // .. ==> MASK : 0x00000030U VAL : 0x00000000U @@ -349,7 +349,7 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. ==> 0XF8000158[13:8] = 0x00000032U // .. ==> MASK : 0x00003F00U VAL : 0x00003200U // .. - EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003201U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003202U), // .. .. START: TRACE CLOCK // .. .. FINISH: TRACE CLOCK // .. .. CLKACT = 0x1 @@ -400,12 +400,12 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. .. SDI1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. SPI0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. SPI1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U // .. .. CAN0_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[16:16] = 0x00000000U // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U @@ -434,7 +434,7 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. .. ==> 0XF800012C[24:24] = 0x00000001U // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U // .. .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC444DU), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC844DU), // .. FINISH: CLOCK CONTROL SLCR REGISTERS // .. START: THIS SHOULD BE BLANK // .. FINISH: THIS SHOULD BE BLANK @@ -4454,12 +4454,12 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. ==> MASK : 0x00003F00U VAL : 0x00001400U // .. EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF8000158[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF8000158[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000158[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U // .. SRCSEL = 0x0 // .. ==> 0XF8000158[5:4] = 0x00000000U // .. ==> MASK : 0x00000030U VAL : 0x00000000U @@ -4467,7 +4467,7 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. ==> 0XF8000158[13:8] = 0x00000032U // .. ==> MASK : 0x00003F00U VAL : 0x00003200U // .. - EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003201U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003202U), // .. .. START: TRACE CLOCK // .. .. FINISH: TRACE CLOCK // .. .. CLKACT = 0x1 @@ -4518,12 +4518,12 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. .. SDI1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. SPI0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. SPI1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U // .. .. CAN0_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[16:16] = 0x00000000U // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U @@ -4552,7 +4552,7 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. .. ==> 0XF800012C[24:24] = 0x00000001U // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U // .. .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC444DU), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC844DU), // .. FINISH: CLOCK CONTROL SLCR REGISTERS // .. START: THIS SHOULD BE BLANK // .. FINISH: THIS SHOULD BE BLANK @@ -8725,12 +8725,12 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. ==> MASK : 0x00003F00U VAL : 0x00001400U // .. EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF8000158[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF8000158[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000158[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U // .. SRCSEL = 0x0 // .. ==> 0XF8000158[5:4] = 0x00000000U // .. ==> MASK : 0x00000030U VAL : 0x00000000U @@ -8738,7 +8738,7 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. ==> 0XF8000158[13:8] = 0x00000032U // .. ==> MASK : 0x00003F00U VAL : 0x00003200U // .. - EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003201U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003202U), // .. .. START: TRACE CLOCK // .. .. FINISH: TRACE CLOCK // .. .. CLKACT = 0x1 @@ -8789,12 +8789,12 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. .. SDI1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. SPI0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. SPI1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U // .. .. CAN0_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[16:16] = 0x00000000U // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U @@ -8823,7 +8823,7 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. .. ==> 0XF800012C[24:24] = 0x00000001U // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U // .. .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC444DU), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC844DU), // .. FINISH: CLOCK CONTROL SLCR REGISTERS // .. START: THIS SHOULD BE BLANK // .. FINISH: THIS SHOULD BE BLANK diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/mz_petalinux_wrapper_hw_platform_0/system.hdf b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/mz_petalinux_wrapper_hw_platform_0/system.hdf index 0f684eac521969b0bec5301cf8190cff95866d02..d1f3f9ba14a675ec24b102894abe8dff3cc74a90 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/mz_petalinux_wrapper_hw_platform_0/system.hdf and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.sdk/mz_petalinux_wrapper_hw_platform_0/system.hdf differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/hdl/mz_petalinux_wrapper.v b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/hdl/mz_petalinux_wrapper.v index fa8302ec8c4848a63f13cfb68b6e35cce4af56fe..0307da74071634dedbda25be8f4cacd4e331dc8c 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/hdl/mz_petalinux_wrapper.v +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/hdl/mz_petalinux_wrapper.v @@ -1,7 +1,7 @@ //Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. //-------------------------------------------------------------------------------- //Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 -//Date : Fri Oct 18 01:16:08 2019 +//Date : Sun Oct 20 22:42:44 2019 //Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS //Command : generate_target mz_petalinux_wrapper.bd //Design : mz_petalinux_wrapper diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/hw_handoff/mz_petalinux.hwh b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/hw_handoff/mz_petalinux.hwh index 5571bce053dfa036d6bb8680581fced54d9f806a..83c4a21ccda17ae15f17bab1c84fadab00ebbd29 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/hw_handoff/mz_petalinux.hwh +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/hw_handoff/mz_petalinux.hwh @@ -1,5 +1,5 @@  - + @@ -31,29 +31,19 @@ - + - + - + - + - - - - - - - - - - - + @@ -156,6 +146,16 @@ + + + + + + + + + + @@ -2776,8 +2776,8 @@ - - + + @@ -2881,8 +2881,8 @@ - - + + @@ -3051,22 +3051,22 @@ - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + @@ -3438,44 +3438,44 @@ - - + + - - - + + + - - + + - - - + + + - + - + - - + + @@ -3872,12 +3872,12 @@ + - @@ -3962,22 +3962,22 @@ - + - - - - - - - - - - - - - - + + + + + + + + + + + + + + @@ -4987,11 +4987,11 @@ + - @@ -5063,7 +5063,7 @@ - + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/hw_handoff/mz_petalinux_bd.tcl b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/hw_handoff/mz_petalinux_bd.tcl index dbadf4ab6ad49d4be92e24547fc9220f5ef735e4..4679d3d26660eadde90c57513ba04d6014fa9cbc 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/hw_handoff/mz_petalinux_bd.tcl +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/hw_handoff/mz_petalinux_bd.tcl @@ -274,7 +274,8 @@ proc create_root_design { parentCell } { CONFIG.PCW_EN_CLK3_PORT {0} \ CONFIG.PCW_EN_DDR {1} \ CONFIG.PCW_EN_EMIO_I2C0 {1} \ - CONFIG.PCW_EN_EMIO_SPI0 {1} \ + CONFIG.PCW_EN_EMIO_SPI0 {0} \ + CONFIG.PCW_EN_EMIO_SPI1 {1} \ CONFIG.PCW_EN_EMIO_TTC0 {1} \ CONFIG.PCW_EN_ENET0 {1} \ CONFIG.PCW_EN_GPIO {1} \ @@ -285,7 +286,8 @@ proc create_root_design { parentCell } { CONFIG.PCW_EN_RST2_PORT {0} \ CONFIG.PCW_EN_RST3_PORT {0} \ CONFIG.PCW_EN_SDIO0 {1} \ - CONFIG.PCW_EN_SPI0 {1} \ + CONFIG.PCW_EN_SPI0 {0} \ + CONFIG.PCW_EN_SPI1 {1} \ CONFIG.PCW_EN_TTC0 {1} \ CONFIG.PCW_EN_UART1 {1} \ CONFIG.PCW_EN_USB0 {1} \ @@ -593,14 +595,22 @@ proc create_root_design { parentCell } { CONFIG.PCW_SDIO_PERIPHERAL_VALID {1} \ CONFIG.PCW_SINGLE_QSPI_DATA_MODE {x4} \ CONFIG.PCW_SMC_PERIPHERAL_DIVISOR0 {1} \ - CONFIG.PCW_SPI0_GRP_SS0_ENABLE {1} \ - CONFIG.PCW_SPI0_GRP_SS0_IO {EMIO} \ - CONFIG.PCW_SPI0_GRP_SS1_ENABLE {1} \ - CONFIG.PCW_SPI0_GRP_SS1_IO {EMIO} \ - CONFIG.PCW_SPI0_GRP_SS2_ENABLE {1} \ - CONFIG.PCW_SPI0_GRP_SS2_IO {EMIO} \ - CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1} \ - CONFIG.PCW_SPI0_SPI0_IO {EMIO} \ + CONFIG.PCW_SPI0_GRP_SS0_ENABLE {0} \ + CONFIG.PCW_SPI0_GRP_SS0_IO {} \ + CONFIG.PCW_SPI0_GRP_SS2_ENABLE {0} \ + CONFIG.PCW_SPI0_GRP_SS2_IO {} \ + CONFIG.PCW_SPI1_GRP_SS0_ENABLE {1} \ + CONFIG.PCW_SPI1_GRP_SS0_IO {EMIO} \ + CONFIG.PCW_SPI1_GRP_SS1_ENABLE {1} \ + CONFIG.PCW_SPI1_GRP_SS1_IO {EMIO} \ + CONFIG.PCW_SPI1_GRP_SS2_ENABLE {1} \ + CONFIG.PCW_SPI1_GRP_SS2_IO {EMIO} \ + CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1} \ + CONFIG.PCW_SPI1_SPI1_IO {EMIO} \ CONFIG.PCW_SPI_PERIPHERAL_DIVISOR0 {50} \ CONFIG.PCW_SPI_PERIPHERAL_FREQMHZ {166.666666} \ CONFIG.PCW_SPI_PERIPHERAL_VALID {1} \ @@ -692,6 +702,9 @@ proc create_root_design { parentCell } { # Create instance: xlconstant_0, and set properties set xlconstant_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 xlconstant_0 ] + set_property -dict [ list \ + CONFIG.CONST_VAL {1} \ + ] $xlconstant_0 # Create interface connections connect_bd_intf_net -intf_net LTC2271_SampleGetter_0_M00_AXIS [get_bd_intf_pins LTC2271_SampleGetter_0/M00_AXIS] [get_bd_intf_pins axi_dma_0/S_AXIS_S2MM] @@ -725,18 +738,18 @@ proc create_root_design { parentCell } { connect_bd_net -net AD_IN_2C_P_0_1 [get_bd_ports AD_IN_2C_P_0] [get_bd_pins LTC2271_SampleGetter_0/AD_IN_2C_P] connect_bd_net -net AD_IN_2D_N_0_1 [get_bd_ports AD_IN_2D_N_0] [get_bd_pins LTC2271_SampleGetter_0/AD_IN_2D_N] connect_bd_net -net AD_IN_2D_P_0_1 [get_bd_ports AD_IN_2D_P_0] [get_bd_pins LTC2271_SampleGetter_0/AD_IN_2D_P] - connect_bd_net -net SPI0_MISO_I_0_1 [get_bd_ports SPI0_MISO_0] [get_bd_pins processing_system7_0/SPI0_MISO_I] + connect_bd_net -net SPI0_MISO_0_1 [get_bd_ports SPI0_MISO_0] [get_bd_pins processing_system7_0/SPI1_MISO_I] connect_bd_net -net axi_dma_0_s2mm_introut [get_bd_pins axi_dma_0/s2mm_introut] [get_bd_pins xlconcat_0/In1] connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins LTC2271_SampleGetter_0/m00_axis_aclk] [get_bd_pins axi_dma_0/m_axi_s2mm_aclk] [get_bd_pins axi_dma_0/m_axi_sg_aclk] [get_bd_pins axi_dma_0/s_axi_lite_aclk] [get_bd_pins axi_smc/aclk] [get_bd_pins processing_system7_0/FCLK_CLK0] [get_bd_pins processing_system7_0/M_AXI_GP0_ACLK] [get_bd_pins processing_system7_0/S_AXI_HP0_ACLK] [get_bd_pins ps7_0_axi_periph/ACLK] [get_bd_pins ps7_0_axi_periph/M00_ACLK] [get_bd_pins ps7_0_axi_periph/M01_ACLK] [get_bd_pins ps7_0_axi_periph/M02_ACLK] [get_bd_pins ps7_0_axi_periph/S00_ACLK] [get_bd_pins rst_ps7_0_100M/slowest_sync_clk] connect_bd_net -net processing_system7_0_FCLK_RESET0_N [get_bd_pins processing_system7_0/FCLK_RESET0_N] [get_bd_pins rst_ps7_0_100M/ext_reset_in] - connect_bd_net -net processing_system7_0_SPI0_MOSI_O [get_bd_ports SPI0_MOSI_0] [get_bd_pins processing_system7_0/SPI0_MOSI_O] - connect_bd_net -net processing_system7_0_SPI0_SCLK_O [get_bd_ports SPI0_SCLK_0] [get_bd_pins processing_system7_0/SPI0_SCLK_O] - connect_bd_net -net processing_system7_0_SPI0_SS1_O [get_bd_ports SPI0_CS_ADC2] [get_bd_pins processing_system7_0/SPI0_SS1_O] - connect_bd_net -net processing_system7_0_SPI0_SS_O [get_bd_ports SPI0_CS_ADC1] [get_bd_pins processing_system7_0/SPI0_SS_O] + connect_bd_net -net processing_system7_0_SPI1_MOSI_O [get_bd_ports SPI0_MOSI_0] [get_bd_pins processing_system7_0/SPI1_MOSI_O] + connect_bd_net -net processing_system7_0_SPI1_SCLK_O [get_bd_ports SPI0_SCLK_0] [get_bd_pins processing_system7_0/SPI1_SCLK_O] + connect_bd_net -net processing_system7_0_SPI1_SS1_O [get_bd_ports SPI0_CS_ADC2] [get_bd_pins processing_system7_0/SPI1_SS1_O] + connect_bd_net -net processing_system7_0_SPI1_SS_O [get_bd_ports SPI0_CS_ADC1] [get_bd_pins processing_system7_0/SPI1_SS_O] connect_bd_net -net rst_ps7_0_100M_interconnect_aresetn [get_bd_pins ps7_0_axi_periph/ARESETN] [get_bd_pins rst_ps7_0_100M/interconnect_aresetn] connect_bd_net -net rst_ps7_0_100M_peripheral_aresetn [get_bd_pins LTC2271_SampleGetter_0/m00_axis_aresetn] [get_bd_pins axi_dma_0/axi_resetn] [get_bd_pins axi_smc/aresetn] [get_bd_pins ps7_0_axi_periph/M00_ARESETN] [get_bd_pins ps7_0_axi_periph/M01_ARESETN] [get_bd_pins ps7_0_axi_periph/M02_ARESETN] [get_bd_pins ps7_0_axi_periph/S00_ARESETN] [get_bd_pins rst_ps7_0_100M/peripheral_aresetn] connect_bd_net -net xlconcat_0_dout [get_bd_pins processing_system7_0/IRQ_F2P] [get_bd_pins xlconcat_0/dout] - connect_bd_net -net xlconstant_0_dout [get_bd_pins processing_system7_0/SPI0_SS_I] [get_bd_pins xlconstant_0/dout] + connect_bd_net -net xlconstant_0_dout [get_bd_pins processing_system7_0/SPI1_SS_I] [get_bd_pins xlconstant_0/dout] # Create address segments create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces axi_dma_0/Data_SG] [get_bd_addr_segs processing_system7_0/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_0_HP0_DDR_LOWOCM diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_auto_pc_0/mz_petalinux_auto_pc_0.dcp b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_auto_pc_0/mz_petalinux_auto_pc_0.dcp index 8a729b4b8b4bd3883621911795d039577e67a396..8b7ea4ef981bf198ebdb96d5d9bb0c9461e09e8f 100755 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_auto_pc_0/mz_petalinux_auto_pc_0.dcp and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_auto_pc_0/mz_petalinux_auto_pc_0.dcp differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_auto_pc_0/mz_petalinux_auto_pc_0.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_auto_pc_0/mz_petalinux_auto_pc_0.xml index e4cc3347497af3cc814c50952dcde0ac304bc227..75a8a0d976c8c326c2ba9895de99d98044e40d00 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_auto_pc_0/mz_petalinux_auto_pc_0.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_auto_pc_0/mz_petalinux_auto_pc_0.xml @@ -1417,7 +1417,7 @@ GENtimestamp - Thu Oct 17 23:16:13 UTC 2019 + Sun Oct 20 20:43:00 UTC 2019 outputProductCRC @@ -1435,7 +1435,7 @@ GENtimestamp - Thu Oct 17 23:16:13 UTC 2019 + Sun Oct 20 20:43:00 UTC 2019 outputProductCRC @@ -1454,7 +1454,7 @@ GENtimestamp - Thu Oct 17 23:16:13 UTC 2019 + Sun Oct 20 20:43:00 UTC 2019 outputProductCRC @@ -1488,7 +1488,7 @@ GENtimestamp - Thu Oct 17 23:16:13 UTC 2019 + Sun Oct 20 20:43:00 UTC 2019 outputProductCRC @@ -1507,7 +1507,7 @@ GENtimestamp - Thu Oct 17 23:16:13 UTC 2019 + Sun Oct 20 20:43:00 UTC 2019 outputProductCRC @@ -1525,7 +1525,7 @@ GENtimestamp - Thu Oct 17 23:16:13 UTC 2019 + Sun Oct 20 20:43:00 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/bd_df03.bxml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/bd_df03.bxml index 659274af354a61fb78720ce02ac9456bb6e176f6..31a8f7ffe5a63ea6955494d9959d08721337cdb9 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/bd_df03.bxml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/bd_df03.bxml @@ -2,10 +2,10 @@ Composite Fileset - - - - + + + + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/hw_handoff/mz_petalinux_axi_smc_0.hwh b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/hw_handoff/mz_petalinux_axi_smc_0.hwh index 6d65fef2451b16a0919b27b6291c86f7c9a8a345..5425263c9b9e3ce2e641f5ac30cea9220f724933 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/hw_handoff/mz_petalinux_axi_smc_0.hwh +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/hw_handoff/mz_petalinux_axi_smc_0.hwh @@ -1,5 +1,5 @@  - + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_0/bd_df03_one_0.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_0/bd_df03_one_0.xml index 3f6ced00ab8c6f06b59bbd1621d4a1abcc779c4d..2f66a09349429ae06cf010198f8c894d54647351 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_0/bd_df03_one_0.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_0/bd_df03_one_0.xml @@ -36,7 +36,7 @@ GENtimestamp - Thu Oct 17 23:16:12 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC @@ -74,7 +74,7 @@ GENtimestamp - Thu Oct 17 23:16:12 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_1/bd_df03_psr_aclk_0.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_1/bd_df03_psr_aclk_0.xml index bd8bbd247253b1ca7fe2dea4d5858e6d31edd710..1b4416bc24488e22cd929db32e59318b761883fd 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_1/bd_df03_psr_aclk_0.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_1/bd_df03_psr_aclk_0.xml @@ -303,7 +303,7 @@ GENtimestamp - Thu Oct 17 23:16:12 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC @@ -333,7 +333,7 @@ GENtimestamp - Thu Oct 17 23:16:12 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC @@ -374,7 +374,7 @@ GENtimestamp - Thu Oct 17 23:16:12 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC @@ -392,7 +392,7 @@ GENtimestamp - Thu Oct 17 23:16:12 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_10/bd_df03_s00a2s_0.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_10/bd_df03_s00a2s_0.xml index ea76cac92fcb6515db6742fa8c71359c1247410b..4f747347626383328e648b4a206d9d2d8a12b71e 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_10/bd_df03_s00a2s_0.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_10/bd_df03_s00a2s_0.xml @@ -946,7 +946,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -965,7 +965,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -987,7 +987,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -1006,7 +1006,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_11/bd_df03_sarn_0.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_11/bd_df03_sarn_0.xml index 593c61e3b7126e6bd399c22ef4c062344062d34a..8095f4ac92418c7f51205407e19f53a0cce4e874 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_11/bd_df03_sarn_0.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_11/bd_df03_sarn_0.xml @@ -652,7 +652,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -671,7 +671,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC @@ -693,7 +693,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -712,7 +712,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_12/bd_df03_srn_0.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_12/bd_df03_srn_0.xml index e791a571667aaf62b4e5659c8907093942ba6e82..34e36eb293b054c7f901a02478b8467bc2b5a3c6 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_12/bd_df03_srn_0.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_12/bd_df03_srn_0.xml @@ -652,7 +652,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -671,7 +671,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC @@ -693,7 +693,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -712,7 +712,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_13/bd_df03_sawn_0.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_13/bd_df03_sawn_0.xml index bc5b95da53d245d48d0f1ddcc5e1a6dd01b095ab..1649bf06d2763b488fc34f1e86385429199bfa71 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_13/bd_df03_sawn_0.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_13/bd_df03_sawn_0.xml @@ -652,7 +652,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -671,7 +671,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC @@ -693,7 +693,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -712,7 +712,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_14/bd_df03_swn_0.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_14/bd_df03_swn_0.xml index 931b94f8dcca08bed88922ef890846f7b886ea89..43ced5b3a78a84a8d1377df7bff3b5e9ff3c5227 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_14/bd_df03_swn_0.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_14/bd_df03_swn_0.xml @@ -652,7 +652,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -671,7 +671,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC @@ -693,7 +693,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -712,7 +712,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_15/bd_df03_sbn_0.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_15/bd_df03_sbn_0.xml index 0238da72776ce005e64f12c72943790acd46db4b..83a37db74ab8996dd8e86dd02e2fa522b4e1834b 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_15/bd_df03_sbn_0.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_15/bd_df03_sbn_0.xml @@ -652,7 +652,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -671,7 +671,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC @@ -693,7 +693,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -712,7 +712,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_16/bd_df03_s02mmu_0.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_16/bd_df03_s02mmu_0.xml index 95e736a80274ad4f8e667045f2e83a001eaf45e6..62bae0e032521998a6f0407d993f46d22af56bb5 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_16/bd_df03_s02mmu_0.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_16/bd_df03_s02mmu_0.xml @@ -1390,7 +1390,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC @@ -1420,7 +1420,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC @@ -1442,7 +1442,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC @@ -1461,7 +1461,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_17/bd_df03_s02tr_0.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_17/bd_df03_s02tr_0.xml index 1f9262caa53d206176b548188861d90432f660f2..624d036ce5a56f432f0001326a2f558c5710bcff 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_17/bd_df03_s02tr_0.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_17/bd_df03_s02tr_0.xml @@ -1358,7 +1358,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC @@ -1388,7 +1388,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC @@ -1410,7 +1410,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC @@ -1429,7 +1429,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_18/bd_df03_s02sic_0.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_18/bd_df03_s02sic_0.xml index a2decd920f806ab7517bd8cfe583a4e7ff32e9ce..efe69b2b06d7484245c1ec1347dbb8e7b08160af 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_18/bd_df03_s02sic_0.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_18/bd_df03_s02sic_0.xml @@ -1361,7 +1361,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC @@ -1391,7 +1391,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC @@ -1413,7 +1413,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC @@ -1432,7 +1432,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_19/bd_df03_s02a2s_0.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_19/bd_df03_s02a2s_0.xml index efd21f21ee6f548547ed1e3a4cd38e2c9bc65f2e..a20627b78f5145f3cc8bba937daa5339a042c469 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_19/bd_df03_s02a2s_0.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_19/bd_df03_s02a2s_0.xml @@ -946,7 +946,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -965,7 +965,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -987,7 +987,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -1006,7 +1006,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_2/bd_df03_arsw_0.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_2/bd_df03_arsw_0.xml index a652d112a67b1d37ed90e7e6da1c61d567890c7a..cb40e332eb540ca7cbff9727b072138967fa17bd 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_2/bd_df03_arsw_0.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_2/bd_df03_arsw_0.xml @@ -2640,7 +2640,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC @@ -2659,7 +2659,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC @@ -2681,7 +2681,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC @@ -2700,7 +2700,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_20/bd_df03_sawn_1.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_20/bd_df03_sawn_1.xml index 92dbbe13ca3ac9c63902b3fac16c5766fb6b9613..61f792ed34447e125f9328411554376b17d60500 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_20/bd_df03_sawn_1.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_20/bd_df03_sawn_1.xml @@ -652,7 +652,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -671,7 +671,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC @@ -693,7 +693,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -712,7 +712,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_21/bd_df03_swn_1.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_21/bd_df03_swn_1.xml index d5312f47060d16c9835f25ef391aeacb6d69ac56..1d071c427e73b14fd526d40a96c288d27d980b66 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_21/bd_df03_swn_1.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_21/bd_df03_swn_1.xml @@ -652,7 +652,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -671,7 +671,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC @@ -693,7 +693,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -712,7 +712,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_22/bd_df03_sbn_1.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_22/bd_df03_sbn_1.xml index 05a1478c8d174d5e2f39b6e6b90a0356d4de447a..e2d61a17211e7f343decf82647f513a9f7ec7502 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_22/bd_df03_sbn_1.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_22/bd_df03_sbn_1.xml @@ -652,7 +652,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -671,7 +671,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC @@ -693,7 +693,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -712,7 +712,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_23/bd_df03_m00s2a_0.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_23/bd_df03_m00s2a_0.xml index 9bd6610dc543f904ca37935edec6f1369472926c..1a7891dc76eb00e7a9e518b53171ed298347e1a8 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_23/bd_df03_m00s2a_0.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_23/bd_df03_m00s2a_0.xml @@ -946,7 +946,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -965,7 +965,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -987,7 +987,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -1006,7 +1006,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_24/bd_df03_m00arn_0.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_24/bd_df03_m00arn_0.xml index de39f260e57d7b67a6f3f2797609f0e3c3e5ee22..bbcdddd7b6964458267a22e46ee789b737a8e8fc 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_24/bd_df03_m00arn_0.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_24/bd_df03_m00arn_0.xml @@ -652,7 +652,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -671,7 +671,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -693,7 +693,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -712,7 +712,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_25/bd_df03_m00rn_0.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_25/bd_df03_m00rn_0.xml index 0630dfdc3d224ae101cbe5f14ba2abe70a042907..3a10d319b741ec669d20b3e76ba1dd09c0fb6a74 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_25/bd_df03_m00rn_0.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_25/bd_df03_m00rn_0.xml @@ -652,7 +652,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -671,7 +671,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC @@ -693,7 +693,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -712,7 +712,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_26/bd_df03_m00awn_0.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_26/bd_df03_m00awn_0.xml index 9a2011dc1b47f36eea1ea74eeeb6ecd76ababb11..295c2110586bee4f3eddf823b5c8933f3c69b50e 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_26/bd_df03_m00awn_0.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_26/bd_df03_m00awn_0.xml @@ -652,7 +652,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -671,7 +671,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC @@ -693,7 +693,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -712,7 +712,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_27/bd_df03_m00wn_0.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_27/bd_df03_m00wn_0.xml index d795e6fe9102d165c92b1687e05a564a696fd4c7..60b95ba6cd016ff1e0d171793f56e63a1e463687 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_27/bd_df03_m00wn_0.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_27/bd_df03_m00wn_0.xml @@ -652,7 +652,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -671,7 +671,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC @@ -693,7 +693,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -712,7 +712,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_28/bd_df03_m00bn_0.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_28/bd_df03_m00bn_0.xml index 99bf3b663f5e00f6d5ca6ede16dbda7dd71426c8..df4abe0ce2d8a0550ef5e9a60b8ab21b5a50d34c 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_28/bd_df03_m00bn_0.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_28/bd_df03_m00bn_0.xml @@ -652,7 +652,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -671,7 +671,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC @@ -693,7 +693,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -712,7 +712,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_29/bd_df03_m00e_0.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_29/bd_df03_m00e_0.xml index b728a8292d71f3d57f83bbee1743f6bfa1179fc8..08d9b741f664b695af37eee07c9b4870f3411473 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_29/bd_df03_m00e_0.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_29/bd_df03_m00e_0.xml @@ -1330,7 +1330,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -1360,7 +1360,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -1382,7 +1382,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC @@ -1401,7 +1401,7 @@ GENtimestamp - Thu Oct 17 23:16:10 UTC 2019 + Sun Oct 20 20:42:57 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_3/bd_df03_rsw_0.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_3/bd_df03_rsw_0.xml index 7684d2b1ed67a896b1f9f6de8a5dcc7065cb3f75..6410fca5b7b50b5048b3261dc644417eeae70d8e 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_3/bd_df03_rsw_0.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_3/bd_df03_rsw_0.xml @@ -2640,7 +2640,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC @@ -2659,7 +2659,7 @@ GENtimestamp - Thu Oct 17 23:16:12 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC @@ -2681,7 +2681,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC @@ -2700,7 +2700,7 @@ GENtimestamp - Thu Oct 17 23:16:12 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_4/bd_df03_awsw_0.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_4/bd_df03_awsw_0.xml index 45662222d22bb17c2c5ef023996c3858ba0a2224..8194d52a8ff490da60c41c8a13e66ea1da2a8d6f 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_4/bd_df03_awsw_0.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_4/bd_df03_awsw_0.xml @@ -2640,7 +2640,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC @@ -2659,7 +2659,7 @@ GENtimestamp - Thu Oct 17 23:16:12 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC @@ -2681,7 +2681,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC @@ -2700,7 +2700,7 @@ GENtimestamp - Thu Oct 17 23:16:12 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_5/bd_df03_wsw_0.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_5/bd_df03_wsw_0.xml index b284a0fb28d165e95834e63818f64dceb4b9ffac..1551c09fec055af5b468b0754dce881b37150816 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_5/bd_df03_wsw_0.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_5/bd_df03_wsw_0.xml @@ -2640,7 +2640,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC @@ -2659,7 +2659,7 @@ GENtimestamp - Thu Oct 17 23:16:12 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC @@ -2681,7 +2681,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC @@ -2700,7 +2700,7 @@ GENtimestamp - Thu Oct 17 23:16:12 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_6/bd_df03_bsw_0.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_6/bd_df03_bsw_0.xml index e2ee91af22f02d93a973457ad7d6e8254b19495d..f86a0c2481a9ab07055405858bea9ee66243d8ea 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_6/bd_df03_bsw_0.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_6/bd_df03_bsw_0.xml @@ -2640,7 +2640,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC @@ -2659,7 +2659,7 @@ GENtimestamp - Thu Oct 17 23:16:12 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC @@ -2681,7 +2681,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC @@ -2700,7 +2700,7 @@ GENtimestamp - Thu Oct 17 23:16:12 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_7/bd_df03_s00mmu_0.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_7/bd_df03_s00mmu_0.xml index 8d8f816d19a96f770aeadd4a961b9092e399a179..79a28d1b304bf21337f6bbbec3685240186bbee4 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_7/bd_df03_s00mmu_0.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_7/bd_df03_s00mmu_0.xml @@ -1390,7 +1390,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC @@ -1420,7 +1420,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC @@ -1442,7 +1442,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC @@ -1461,7 +1461,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_8/bd_df03_s00tr_0.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_8/bd_df03_s00tr_0.xml index d40f81e7bd11b7b27b74c2d69c5110c376ec9f2f..1b33732d73d6e114c88021e14c5cf5135ba911be 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_8/bd_df03_s00tr_0.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_8/bd_df03_s00tr_0.xml @@ -1358,7 +1358,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC @@ -1388,7 +1388,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC @@ -1410,7 +1410,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC @@ -1429,7 +1429,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_9/bd_df03_s00sic_0.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_9/bd_df03_s00sic_0.xml index 8163f02976575889a60467ff660f3c50527975d3..e7e28fe2fdce04eb8615993a56df539b14a80b91 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_9/bd_df03_s00sic_0.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/ip/ip_9/bd_df03_s00sic_0.xml @@ -1361,7 +1361,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC @@ -1391,7 +1391,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC @@ -1413,7 +1413,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:58 UTC 2019 outputProductCRC @@ -1432,7 +1432,7 @@ GENtimestamp - Thu Oct 17 23:16:11 UTC 2019 + Sun Oct 20 20:42:59 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/synth/mz_petalinux_axi_smc_0.hwdef b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/synth/mz_petalinux_axi_smc_0.hwdef index 69195ad6d111067ce7672267d06e27ae1ad68387..eb0aafdbb8d7d4c6de788b01ba4f27fa3b895b5a 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/synth/mz_petalinux_axi_smc_0.hwdef and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/bd_0/synth/mz_petalinux_axi_smc_0.hwdef differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/mz_petalinux_axi_smc_0.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/mz_petalinux_axi_smc_0.xml index 3846fa5f54df38cf6a0894194e0f8daa3bcacc37..bbb98a9fa42866936e626eac29cd946bd1b3f85c 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/mz_petalinux_axi_smc_0.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_axi_smc_0/mz_petalinux_axi_smc_0.xml @@ -2130,7 +2130,7 @@ GENtimestamp - Thu Oct 17 23:08:56 UTC 2019 + Sun Oct 20 18:02:25 UTC 2019 outputProductCRC diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/hdl/verilog/mz_petalinux_processing_system7_0_0.hwdef b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/hdl/verilog/mz_petalinux_processing_system7_0_0.hwdef index 9ad294f32a20ee40f4583f244e358bb4db8397b1..b462591f928e97c9db9822663e5f7a46a4088832 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/hdl/verilog/mz_petalinux_processing_system7_0_0.hwdef and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/hdl/verilog/mz_petalinux_processing_system7_0_0.hwdef differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v index c226edfa68f6863a0b620860173b225ec4262488..6c81897fc0be96949962643160124731b86b40d3 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/hdl/verilog/processing_system7_v5_5_processing_system7.v @@ -149,12 +149,12 @@ // CR #682573 // Added BIBUF to fixed IO ports and IBUF to fixed input ports //------------------------------------------------------------------------------ -(*POWER= "/>" *) +(*POWER= "/>" *) (* CORE_GENERATION_INFO = "processing_system7_v5.5 ,processing_system7_v5.5_user_configuration,{ PCW_UIPARAM_DDR_FREQ_MHZ=533.333333, PCW_UIPARAM_DDR_BANK_ADDR_COUNT=3, PCW_UIPARAM_DDR_ROW_ADDR_COUNT=15, PCW_UIPARAM_DDR_COL_ADDR_COUNT=10, PCW_UIPARAM_DDR_CL=7, PCW_UIPARAM_DDR_CWL=6, PCW_UIPARAM_DDR_T_RCD=7, PCW_UIPARAM_DDR_T_RP=7, PCW_UIPARAM_DDR_T_RC=48.75, PCW_UIPARAM_DDR_T_RAS_MIN=35.0, PCW_UIPARAM_DDR_T_FAW=40.0, PCW_UIPARAM_DDR_AL=0, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0=-0.073, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1=-0.072, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2=0.024, PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3=0.023, PCW_UIPARAM_DDR_BOARD_DELAY0=0.294, PCW_UIPARAM_DDR_BOARD_DELAY1=0.298, PCW_UIPARAM_DDR_BOARD_DELAY2=0.338, PCW_UIPARAM_DDR_BOARD_DELAY3=0.334, PCW_UIPARAM_DDR_DQS_0_LENGTH_MM=50.05, PCW_UIPARAM_DDR_DQS_1_LENGTH_MM=50.43, PCW_UIPARAM_DDR_DQS_2_LENGTH_MM=50.10, PCW_UIPARAM_DDR_DQS_3_LENGTH_MM=50.01, PCW_UIPARAM_DDR_DQ_0_LENGTH_MM=49.59, PCW_UIPARAM_DDR_DQ_1_LENGTH_MM=51.74, PCW_UIPARAM_DDR_DQ_2_LENGTH_MM=50.32, PCW_UIPARAM_DDR_DQ_3_LENGTH_MM=48.55, PCW_UIPARAM_DDR_CLOCK_0_LENGTH_MM=54.14, PCW_UIPARAM_DDR_CLOCK_1_LENGTH_MM=54.14, PCW_UIPARAM_DDR_CLOCK_2_LENGTH_MM=39.7, PCW_UIPARAM_DDR_CLOCK_3_LENGTH_MM=39.7, PCW_UIPARAM_DDR_DQS_0_PACKAGE_LENGTH=101.239, PCW_UIPARAM_DDR_DQS_1_PACKAGE_LENGTH=79.5025, PCW_UIPARAM_DDR_DQS_2_PACKAGE_LENGTH=60.536, PCW_UIPARAM_DDR_DQS_3_PACKAGE_LENGTH=71.7715, PCW_UIPARAM_DDR_DQ_0_PACKAGE_LENGTH=104.5365, PCW_UIPARAM_DDR_DQ_1_PACKAGE_LENGTH=70.676, PCW_UIPARAM_DDR_DQ_2_PACKAGE_LENGTH=59.1615, PCW_UIPARAM_DDR_DQ_3_PACKAGE_LENGTH=81.319, PCW_UIPARAM_DDR_CLOCK_0_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_1_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_2_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_CLOCK_3_PACKAGE_LENGTH=54.563, PCW_UIPARAM_DDR_DQS_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQS_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_1_PROPOGATION_DELAY=160\ , PCW_UIPARAM_DDR_DQ_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_DQ_3_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_0_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_1_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_2_PROPOGATION_DELAY=160, PCW_UIPARAM_DDR_CLOCK_3_PROPOGATION_DELAY=160, PCW_CRYSTAL_PERIPHERAL_FREQMHZ=33.333333, PCW_APU_PERIPHERAL_FREQMHZ=667, PCW_DCI_PERIPHERAL_FREQMHZ=10.159, PCW_QSPI_PERIPHERAL_FREQMHZ=200, PCW_SMC_PERIPHERAL_FREQMHZ=100, PCW_USB0_PERIPHERAL_FREQMHZ=60, PCW_USB1_PERIPHERAL_FREQMHZ=60, PCW_SDIO_PERIPHERAL_FREQMHZ=25, PCW_UART_PERIPHERAL_FREQMHZ=50, PCW_SPI_PERIPHERAL_FREQMHZ=166.666666, PCW_CAN_PERIPHERAL_FREQMHZ=100, PCW_CAN0_PERIPHERAL_FREQMHZ=-1, PCW_CAN1_PERIPHERAL_FREQMHZ=-1, PCW_WDT_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC_PERIPHERAL_FREQMHZ=50, PCW_TTC0_CLK0_PERIPHERAL_FREQMHZ=111.111115, PCW_TTC0_CLK1_PERIPHERAL_FREQMHZ=111.111115, PCW_TTC0_CLK2_PERIPHERAL_FREQMHZ=111.111115, PCW_TTC1_CLK0_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK1_PERIPHERAL_FREQMHZ=133.333333, PCW_TTC1_CLK2_PERIPHERAL_FREQMHZ=133.333333, PCW_PCAP_PERIPHERAL_FREQMHZ=200, PCW_TPIU_PERIPHERAL_FREQMHZ=200, PCW_FPGA0_PERIPHERAL_FREQMHZ=100, PCW_FPGA1_PERIPHERAL_FREQMHZ=100, PCW_FPGA2_PERIPHERAL_FREQMHZ=33.333333, PCW_FPGA3_PERIPHERAL_FREQMHZ=50, PCW_OVERRIDE_BASIC_CLOCK=1, PCW_ARMPLL_CTRL_FBDIV=40, PCW_IOPLL_CTRL_FBDIV=30, PCW_DDRPLL_CTRL_FBDIV=32, PCW_CPU_CPU_PLL_FREQMHZ=1333.333, PCW_IO_IO_PLL_FREQMHZ=1000.000, PCW_DDR_DDR_PLL_FREQMHZ=1066.667, PCW_USE_M_AXI_GP0=1, PCW_USE_M_AXI_GP1=0, PCW_USE_S_AXI_GP0=0, PCW_USE_S_AXI_GP1=0, PCW_USE_S_AXI_ACP=0, PCW_USE_S_AXI_HP0=1, PCW_USE_S_AXI_HP1=0, PCW_USE_S_AXI_HP2=0, PCW_USE_S_AXI_HP3=0, PCW_M_AXI_GP0_FREQMHZ=99\ , PCW_M_AXI_GP1_FREQMHZ=10, PCW_S_AXI_GP0_FREQMHZ=10, PCW_S_AXI_GP1_FREQMHZ=10, PCW_S_AXI_ACP_FREQMHZ=10, PCW_S_AXI_HP0_FREQMHZ=99, PCW_S_AXI_HP1_FREQMHZ=10, PCW_S_AXI_HP2_FREQMHZ=10, PCW_S_AXI_HP3_FREQMHZ=10, PCW_USE_CROSS_TRIGGER=0, PCW_FTM_CTI_IN0=DISABLED, PCW_FTM_CTI_IN1=DISABLED, PCW_FTM_CTI_IN2=DISABLED, PCW_FTM_CTI_IN3=DISABLED, PCW_FTM_CTI_OUT0=DISABLED, PCW_FTM_CTI_OUT1=DISABLED, PCW_FTM_CTI_OUT2=DISABLED, PCW_FTM_CTI_OUT3=DISABLED, PCW_UART0_BAUD_RATE=115200, PCW_UART1_BAUD_RATE=115200, PCW_S_AXI_HP0_DATA_WIDTH=64, PCW_S_AXI_HP1_DATA_WIDTH=64, PCW_S_AXI_HP2_DATA_WIDTH=64, PCW_S_AXI_HP3_DATA_WIDTH=64, PCW_IRQ_F2P_MODE=DIRECT, PCW_PRESET_BANK0_VOLTAGE=LVCMOS 3.3V, PCW_PRESET_BANK1_VOLTAGE=LVCMOS 1.8V, PCW_UIPARAM_DDR_ENABLE=1, PCW_UIPARAM_DDR_ADV_ENABLE=0, PCW_UIPARAM_DDR_MEMORY_TYPE=DDR 3, PCW_UIPARAM_DDR_ECC=Disabled, PCW_UIPARAM_DDR_BUS_WIDTH=32 Bit, PCW_UIPARAM_DDR_BL=8, PCW_UIPARAM_DDR_HIGH_TEMP=Normal (0-85), PCW_UIPARAM_DDR_PARTNO=MT41K256M16 RE-125, PCW_UIPARAM_DDR_DRAM_WIDTH=16 Bits, PCW_UIPARAM_DDR_DEVICE_CAPACITY=4096 MBits, PCW_UIPARAM_DDR_SPEED_BIN=DDR3_1066F, PCW_UIPARAM_DDR_TRAIN_WRITE_LEVEL=1, PCW_UIPARAM_DDR_TRAIN_READ_GATE=1, PCW_UIPARAM_DDR_TRAIN_DATA_EYE=1, PCW_UIPARAM_DDR_CLOCK_STOP_EN=0, PCW_UIPARAM_DDR_USE_INTERNAL_VREF=0, PCW_DDR_PORT0_HPR_ENABLE=0, PCW_DDR_PORT1_HPR_ENABLE=0, PCW_DDR_PORT2_HPR_ENABLE=0, PCW_DDR_PORT3_HPR_ENABLE=0, PCW_DDR_HPRLPR_QUEUE_PARTITION=HPR(0)/LPR(32), PCW_DDR_LPR_TO_CRITICAL_PRIORITY_LEVEL=2, PCW_DDR_HPR_TO_CRITICAL_PRIORITY_LEVEL=15, PCW_DDR_WRITE_TO_CRITICAL_PRIORITY_LEVEL=2\ -, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=1, PCW_QSPI_GRP_FBCLK_IO=MIO 8, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_SINGLE_QSPI_DATA_MODE=x4, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=1, PCW_SD0_SD0_IO=MIO 40 .. 45, PCW_SD0_GRP_CD_ENABLE=1, PCW_SD0_GRP_CD_IO=MIO 46, PCW_SD0_GRP_WP_ENABLE=1, PCW_SD0_GRP_WP_IO=MIO 50, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 48 .. 49, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=1, PCW_SPI0_SPI0_IO=EMIO, PCW_SPI0_GRP_SS0_ENABLE=1, PCW_SPI0_GRP_SS0_IO=EMIO, PCW_SPI0_GRP_SS1_ENABLE=1, PCW_SPI0_GRP_SS1_IO=EMIO, PCW_SPI0_GRP_SS2_ENABLE=1, PCW_SPI0_GRP_SS2_IO=EMIO\ -, PCW_SPI1_PERIPHERAL_ENABLE=0, PCW_SPI1_GRP_SS0_ENABLE=0, PCW_SPI1_GRP_SS1_ENABLE=0, PCW_SPI1_GRP_SS2_ENABLE=0, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=1, PCW_TTC0_TTC0_IO=EMIO, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=1, PCW_USB0_RESET_IO=MIO 7, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=1, PCW_I2C0_I2C0_IO=EMIO, PCW_I2C0_GRP_INT_ENABLE=1, PCW_I2C0_GRP_INT_IO=EMIO, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=1, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL\ +, PCW_NAND_PERIPHERAL_ENABLE=0, PCW_NAND_GRP_D8_ENABLE=0, PCW_NOR_PERIPHERAL_ENABLE=0, PCW_NOR_GRP_A25_ENABLE=0, PCW_NOR_GRP_CS0_ENABLE=0, PCW_NOR_GRP_SRAM_CS0_ENABLE=0, PCW_NOR_GRP_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_CS1_ENABLE=0, PCW_NOR_GRP_SRAM_INT_ENABLE=0, PCW_QSPI_PERIPHERAL_ENABLE=1, PCW_QSPI_QSPI_IO=MIO 1 .. 6, PCW_QSPI_GRP_SINGLE_SS_ENABLE=1, PCW_QSPI_GRP_SINGLE_SS_IO=MIO 1 .. 6, PCW_QSPI_GRP_SS1_ENABLE=0, PCW_QSPI_GRP_IO1_ENABLE=0, PCW_QSPI_GRP_FBCLK_ENABLE=1, PCW_QSPI_GRP_FBCLK_IO=MIO 8, PCW_QSPI_INTERNAL_HIGHADDRESS=0xFCFFFFFF, PCW_SINGLE_QSPI_DATA_MODE=x4, PCW_ENET0_PERIPHERAL_ENABLE=1, PCW_ENET0_ENET0_IO=MIO 16 .. 27, PCW_ENET0_GRP_MDIO_ENABLE=1, PCW_ENET0_RESET_ENABLE=0, PCW_ENET1_PERIPHERAL_ENABLE=0, PCW_ENET1_GRP_MDIO_ENABLE=0, PCW_ENET1_RESET_ENABLE=0, PCW_SD0_PERIPHERAL_ENABLE=1, PCW_SD0_SD0_IO=MIO 40 .. 45, PCW_SD0_GRP_CD_ENABLE=1, PCW_SD0_GRP_CD_IO=MIO 46, PCW_SD0_GRP_WP_ENABLE=1, PCW_SD0_GRP_WP_IO=MIO 50, PCW_SD0_GRP_POW_ENABLE=0, PCW_SD1_PERIPHERAL_ENABLE=0, PCW_SD1_GRP_CD_ENABLE=0, PCW_SD1_GRP_WP_ENABLE=0, PCW_SD1_GRP_POW_ENABLE=0, PCW_UART0_PERIPHERAL_ENABLE=0, PCW_UART0_GRP_FULL_ENABLE=0, PCW_UART1_PERIPHERAL_ENABLE=1, PCW_UART1_UART1_IO=MIO 48 .. 49, PCW_UART1_GRP_FULL_ENABLE=0, PCW_SPI0_PERIPHERAL_ENABLE=0, PCW_SPI0_GRP_SS0_ENABLE=0, PCW_SPI0_GRP_SS1_ENABLE=0, PCW_SPI0_GRP_SS2_ENABLE=0, PCW_SPI1_PERIPHERAL_ENABLE=1, PCW_SPI1_SPI1_IO=EMIO, PCW_SPI1_GRP_SS0_ENABLE=1, PCW_SPI1_GRP_SS0_IO=EMIO\ +, PCW_SPI1_GRP_SS1_ENABLE=1, PCW_SPI1_GRP_SS1_IO=EMIO, PCW_SPI1_GRP_SS2_ENABLE=1, PCW_SPI1_GRP_SS2_IO=EMIO, PCW_CAN0_PERIPHERAL_ENABLE=0, PCW_CAN0_GRP_CLK_ENABLE=0, PCW_CAN1_PERIPHERAL_ENABLE=0, PCW_CAN1_GRP_CLK_ENABLE=0, PCW_TRACE_PERIPHERAL_ENABLE=0, PCW_TRACE_GRP_2BIT_ENABLE=0, PCW_TRACE_GRP_4BIT_ENABLE=0, PCW_TRACE_GRP_8BIT_ENABLE=0, PCW_TRACE_GRP_16BIT_ENABLE=0, PCW_TRACE_GRP_32BIT_ENABLE=0, PCW_WDT_PERIPHERAL_ENABLE=0, PCW_TTC0_PERIPHERAL_ENABLE=1, PCW_TTC0_TTC0_IO=EMIO, PCW_TTC1_PERIPHERAL_ENABLE=0, PCW_PJTAG_PERIPHERAL_ENABLE=0, PCW_USB0_PERIPHERAL_ENABLE=1, PCW_USB0_USB0_IO=MIO 28 .. 39, PCW_USB0_RESET_ENABLE=1, PCW_USB0_RESET_IO=MIO 7, PCW_USB1_PERIPHERAL_ENABLE=0, PCW_USB1_RESET_ENABLE=0, PCW_I2C0_PERIPHERAL_ENABLE=1, PCW_I2C0_I2C0_IO=EMIO, PCW_I2C0_GRP_INT_ENABLE=1, PCW_I2C0_GRP_INT_IO=EMIO, PCW_I2C0_RESET_ENABLE=0, PCW_I2C1_PERIPHERAL_ENABLE=0, PCW_I2C1_GRP_INT_ENABLE=0, PCW_I2C1_RESET_ENABLE=0, PCW_GPIO_PERIPHERAL_ENABLE=1, PCW_GPIO_MIO_GPIO_ENABLE=1, PCW_GPIO_MIO_GPIO_IO=MIO, PCW_GPIO_EMIO_GPIO_ENABLE=0, PCW_APU_CLK_RATIO_ENABLE=6:2:1, PCW_ENET0_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_ENET1_PERIPHERAL_FREQMHZ=1000 Mbps, PCW_CPU_PERIPHERAL_CLKSRC=ARM PLL, PCW_DDR_PERIPHERAL_CLKSRC=DDR PLL, PCW_SMC_PERIPHERAL_CLKSRC=IO PLL, PCW_QSPI_PERIPHERAL_CLKSRC=IO PLL, PCW_SDIO_PERIPHERAL_CLKSRC=IO PLL, PCW_UART_PERIPHERAL_CLKSRC=IO PLL, PCW_SPI_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK0_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK1_PERIPHERAL_CLKSRC=IO PLL\ , PCW_FCLK2_PERIPHERAL_CLKSRC=IO PLL, PCW_FCLK3_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET0_PERIPHERAL_CLKSRC=IO PLL, PCW_ENET1_PERIPHERAL_CLKSRC=IO PLL, PCW_CAN0_PERIPHERAL_CLKSRC=External, PCW_CAN1_PERIPHERAL_CLKSRC=External, PCW_TPIU_PERIPHERAL_CLKSRC=External, PCW_TTC0_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC0_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK0_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK1_PERIPHERAL_CLKSRC=CPU_1X, PCW_TTC1_CLK2_PERIPHERAL_CLKSRC=CPU_1X, PCW_WDT_PERIPHERAL_CLKSRC=CPU_1X, PCW_DCI_PERIPHERAL_CLKSRC=DDR PLL, PCW_PCAP_PERIPHERAL_CLKSRC=IO PLL, PCW_USB_RESET_POLARITY=Active Low, PCW_ENET_RESET_POLARITY=Active Low, PCW_I2C_RESET_POLARITY=Active Low, PCW_FPGA_FCLK0_ENABLE=1, PCW_FPGA_FCLK1_ENABLE=0, PCW_FPGA_FCLK2_ENABLE=0, PCW_FPGA_FCLK3_ENABLE=0, PCW_NOR_SRAM_CS0_T_TR=1, PCW_NOR_SRAM_CS0_T_PC=1, PCW_NOR_SRAM_CS0_T_WP=1, PCW_NOR_SRAM_CS0_T_CEOE=1, PCW_NOR_SRAM_CS0_T_WC=11, PCW_NOR_SRAM_CS0_T_RC=11, PCW_NOR_SRAM_CS0_WE_TIME=0, PCW_NOR_SRAM_CS1_T_TR=1, PCW_NOR_SRAM_CS1_T_PC=1, PCW_NOR_SRAM_CS1_T_WP=1, PCW_NOR_SRAM_CS1_T_CEOE=1, PCW_NOR_SRAM_CS1_T_WC=11, PCW_NOR_SRAM_CS1_T_RC=11, PCW_NOR_SRAM_CS1_WE_TIME=0, PCW_NOR_CS0_T_TR=1, PCW_NOR_CS0_T_PC=1, PCW_NOR_CS0_T_WP=1, PCW_NOR_CS0_T_CEOE=1, PCW_NOR_CS0_T_WC=11, PCW_NOR_CS0_T_RC=11, PCW_NOR_CS0_WE_TIME=0, PCW_NOR_CS1_T_TR=1, PCW_NOR_CS1_T_PC=1, PCW_NOR_CS1_T_WP=1, PCW_NOR_CS1_T_CEOE=1, PCW_NOR_CS1_T_WC=11, PCW_NOR_CS1_T_RC=11\ , PCW_NOR_CS1_WE_TIME=0, PCW_NAND_CYCLES_T_RR=1, PCW_NAND_CYCLES_T_AR=1, PCW_NAND_CYCLES_T_CLR=1, PCW_NAND_CYCLES_T_WP=1, PCW_NAND_CYCLES_T_REA=1, PCW_NAND_CYCLES_T_WC=11, PCW_NAND_CYCLES_T_RC=11 }" *) (* HW_HANDOFF = "mz_petalinux_processing_system7_0_0.hwdef" *) diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0.dcp b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0.dcp index c42fdd0eb6c3c28ca444f27086e0630429027184..4d55cf74a10af523bd15ed38fce11357ba24b6a3 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0.dcp and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0.dcp differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0.xci b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0.xci index 513632d5aced538ff09c8dc03e470eeb9e82f4ee..6fdfbd211f72e16aca3ef469a0049ee37183771a 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0.xci +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0.xci @@ -656,8 +656,8 @@ 0 0 0 - 1 - 0 + 0 + 1 0 0 1 @@ -685,8 +685,8 @@ 1 0 0 - 1 - 0 + 0 + 1 0 1 0 @@ -1149,25 +1149,25 @@ 100 0 0xE0006000 - 1 - EMIO - 1 - EMIO - 1 - EMIO + 0 + <Select> + 0 + <Select> + 0 + <Select> 0xE0006FFF - 1 - EMIO + 0 + <Select> 0xE0007000 - 0 - <Select> - 0 - <Select> - 0 - <Select> + 1 + EMIO + 1 + EMIO + 1 + EMIO 0xE0007FFF - 0 - <Select> + 1 + EMIO IO PLL 50 166.666666 @@ -1538,6 +1538,7 @@ + @@ -1549,6 +1550,7 @@ + @@ -1866,6 +1868,14 @@ + + + + + + + + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0.xml index 718eaffaa5c4cf2cb9ace1bd513689047db25946..f79126c249b2d9a489a639caaa6d8f56c2b3406f 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0.xml @@ -1362,7 +1362,7 @@ - true + false @@ -1489,7 +1489,7 @@ - false + true @@ -14041,11 +14041,11 @@ GENtimestamp - Fri Jul 12 12:19:57 UTC 2019 + Sun Oct 20 20:42:53 UTC 2019 outputProductCRC - 7:c92426b7 + 7:fe454724 @@ -14060,11 +14060,11 @@ GENtimestamp - Fri Jul 12 12:19:57 UTC 2019 + Sun Oct 20 20:42:53 UTC 2019 outputProductCRC - 7:c92426b7 + 7:fe454724 @@ -14090,7 +14090,7 @@ outputProductCRC - 7:0aeb1a27 + 7:f00120e5 @@ -14104,11 +14104,11 @@ GENtimestamp - Fri Jul 12 12:19:57 UTC 2019 + Sun Oct 20 20:42:54 UTC 2019 outputProductCRC - 7:0aeb1a27 + 7:f00120e5 sim_type @@ -14130,11 +14130,11 @@ GENtimestamp - Fri Jul 12 12:19:57 UTC 2019 + Sun Oct 20 20:42:54 UTC 2019 outputProductCRC - 7:0aeb1a27 + 7:f00120e5 @@ -14148,11 +14148,11 @@ GENtimestamp - Fri Jul 12 12:19:59 UTC 2019 + Sun Oct 20 20:42:56 UTC 2019 outputProductCRC - 7:0aeb1a27 + 7:f00120e5 sim_type @@ -14170,11 +14170,11 @@ GENtimestamp - Fri Jul 12 12:21:10 UTC 2019 + Sun Oct 20 20:43:58 UTC 2019 outputProductCRC - 7:c92426b7 + 7:fe454724 @@ -16356,7 +16356,7 @@ - true + false @@ -16376,7 +16376,7 @@ - true + false @@ -16396,7 +16396,7 @@ - true + false @@ -16419,7 +16419,7 @@ - true + false @@ -16439,7 +16439,7 @@ - true + false @@ -16459,7 +16459,7 @@ - true + false @@ -16482,7 +16482,7 @@ - true + false @@ -16502,7 +16502,7 @@ - true + false @@ -16522,7 +16522,7 @@ - true + false @@ -16545,7 +16545,7 @@ - true + false @@ -16565,7 +16565,7 @@ - true + false @@ -16585,7 +16585,7 @@ - true + false @@ -16605,7 +16605,7 @@ - true + false @@ -16625,7 +16625,7 @@ - true + false @@ -16648,7 +16648,7 @@ - false + true @@ -16668,7 +16668,7 @@ - false + true @@ -16688,7 +16688,7 @@ - false + true @@ -16711,7 +16711,7 @@ - false + true @@ -16731,7 +16731,7 @@ - false + true @@ -16751,7 +16751,7 @@ - false + true @@ -16774,7 +16774,7 @@ - false + true @@ -16794,7 +16794,7 @@ - false + true @@ -16814,7 +16814,7 @@ - false + true @@ -16837,7 +16837,7 @@ - false + true @@ -16857,7 +16857,7 @@ - false + true @@ -16877,7 +16877,7 @@ - false + true @@ -16897,7 +16897,7 @@ - false + true @@ -16917,7 +16917,7 @@ - false + true @@ -30067,6 +30067,14 @@ 4 2 + + choice_list_129b798f + <Select> + EMIO + MIO 18 + MIO 30 + MIO 42 + choice_list_13f07802 DISABLED @@ -30135,13 +30143,6 @@ <Select> MIO 3 .. 39 - - choice_list_35acfb50 - EMIO - MIO 18 - MIO 30 - MIO 42 - choice_list_35b40bd0 6 @@ -30159,6 +30160,14 @@ choice_list_3740015d 0xE0103fff + + choice_list_390b0393 + <Select> + EMIO + MIO 16 .. 21 + MIO 28 .. 33 + MIO 40 .. 45 + choice_list_3b9f1944 <Select> @@ -30219,6 +30228,14 @@ 0x00100000 0x00040000 + + choice_list_4b3359e9 + EMIO + MIO 15 + MIO 27 + MIO 39 + MIO 51 + choice_list_4d36a164 <Select> @@ -30302,13 +30319,6 @@ x2 x4 - - choice_list_5cca4107 - EMIO - MIO 20 - MIO 32 - MIO 44 - choice_list_5d0f73c4 <Select> @@ -30470,6 +30480,14 @@ choice_list_6a48f1e0 MIO + + choice_list_6b183472 + EMIO + MIO 14 + MIO 26 + MIO 38 + MIO 50 + choice_list_6bc4d474 LVCMOS 3.3V @@ -30479,6 +30497,14 @@ Active High Active Low + + choice_list_6e6efe45 + EMIO + MIO 13 + MIO 25 + MIO 37 + MIO 49 + choice_list_727c50f2 EMIO @@ -30609,6 +30635,14 @@ 16 Bit 32 Bit + + choice_list_7bfdc3d8 + <Select> + EMIO + MIO 20 + MIO 32 + MIO 44 + choice_list_7d098ed6 ARM PLL @@ -30773,15 +30807,6 @@ MIO 12 .. 13 MIO 24 .. 25 - - choice_list_93a2bb4f - <Select> - EMIO - MIO 13 - MIO 25 - MIO 37 - MIO 49 - choice_list_93e94109 0xE0105000 @@ -30800,15 +30825,6 @@ out inout - - choice_list_96d47178 - <Select> - EMIO - MIO 14 - MIO 26 - MIO 38 - MIO 50 - choice_list_96d47805 32 @@ -30963,15 +30979,6 @@ EMIO MIO 28 .. 39 - - choice_list_b6ff1ce3 - <Select> - EMIO - MIO 15 - MIO 27 - MIO 39 - MIO 51 - choice_list_b76ed1eb 0xE000A000 @@ -31152,11 +31159,12 @@ MIO 53 - choice_list_d6a579c1 + choice_list_d8fa963a EMIO - MIO 19 - MIO 31 - MIO 43 + MIO 10 .. 15 + MIO 22 .. 27 + MIO 34 .. 39 + MIO 46 .. 51 choice_list_da0dabdb @@ -31222,6 +31230,14 @@ 16 Bits 32 Bits + + choice_list_f192fb1e + <Select> + EMIO + MIO 19 + MIO 31 + MIO 43 + choice_list_f585525a 110 @@ -31769,7 +31785,7 @@ - true + false @@ -31781,7 +31797,7 @@ - true + false @@ -31793,7 +31809,7 @@ - false + true @@ -31805,7 +31821,7 @@ - false + true @@ -33249,12 +33265,12 @@ PCW_EN_EMIO_SPI0 PCW EN EMIO SPI0 - 1 + 0 PCW_EN_EMIO_SPI1 PCW EN EMIO SPI1 - 0 + 1 PCW_EN_EMIO_UART0 @@ -34114,12 +34130,12 @@ PCW_EN_SPI0 PCW EN SPI0 - 1 + 0 PCW_EN_SPI1 PCW EN SPI1 - 0 + 1 PCW_EN_UART0 @@ -34554,7 +34570,7 @@ - true + false @@ -34638,7 +34654,7 @@ - false + true @@ -35673,16 +35689,23 @@ PCW_SPI0_PERIPHERAL_ENABLE PCW SPI0 PERIPHERAL ENABLE - 1 + 0 PCW_SPI0_SPI0_IO PCW SPI0 SPI0 IO - EMIO + <Select> + + + + false + + + PCW_SPI0_GRP_SS0_ENABLE - 1 + 0 @@ -35694,7 +35717,7 @@ PCW_SPI0_GRP_SS0_IO PCW SPI0 GRP SS0 IO - EMIO + <Select> @@ -35705,7 +35728,7 @@ PCW_SPI0_GRP_SS1_ENABLE - 1 + 0 @@ -35717,7 +35740,7 @@ PCW_SPI0_GRP_SS1_IO PCW SPI0 GRP SS1 IO - EMIO + <Select> @@ -35728,7 +35751,7 @@ PCW_SPI0_GRP_SS2_ENABLE - 1 + 0 @@ -35740,7 +35763,7 @@ PCW_SPI0_GRP_SS2_IO PCW SPI0 GRP SS2 IO - EMIO + <Select> @@ -35752,23 +35775,16 @@ PCW_SPI1_PERIPHERAL_ENABLE PCW SPI1 PERIPHERAL ENABLE - 0 + 1 PCW_SPI1_SPI1_IO PCW SPI1 SPI1 IO - <Select> - - - - false - - - + EMIO PCW_SPI1_GRP_SS0_ENABLE - 0 + 1 @@ -35780,7 +35796,7 @@ PCW_SPI1_GRP_SS0_IO PCW SPI1 GRP SS0 IO - <Select> + EMIO @@ -35791,7 +35807,7 @@ PCW_SPI1_GRP_SS1_ENABLE - 0 + 1 @@ -35803,7 +35819,7 @@ PCW_SPI1_GRP_SS1_IO PCW SPI1 GRP SS1 IO - <Select> + EMIO @@ -35814,7 +35830,7 @@ PCW_SPI1_GRP_SS2_ENABLE - 0 + 1 @@ -35826,7 +35842,7 @@ PCW_SPI1_GRP_SS2_IO PCW SPI1 GRP SS2 IO - <Select> + EMIO @@ -38457,6 +38473,7 @@ + @@ -38468,6 +38485,7 @@ + @@ -38785,6 +38803,14 @@ + + + + + + + + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0_sim_netlist.v b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0_sim_netlist.v index d58f58825a83aad31fee15e4a376e0f2fa7da777..f473bbc5f74defa5d8ce88253295c0022c801839 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0_sim_netlist.v +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0_sim_netlist.v @@ -1,8 +1,8 @@ // Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 -// Date : Fri Jul 12 14:21:10 2019 -// Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.2 LTS +// Date : Sun Oct 20 22:43:58 2019 +// Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS // Command : write_verilog -force -mode funcsim // /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0_sim_netlist.v // Design : mz_petalinux_processing_system7_0_0 @@ -21,20 +21,20 @@ module mz_petalinux_processing_system7_0_0 I2C0_SCL_I, I2C0_SCL_O, I2C0_SCL_T, - SPI0_SCLK_I, - SPI0_SCLK_O, - SPI0_SCLK_T, - SPI0_MOSI_I, - SPI0_MOSI_O, - SPI0_MOSI_T, - SPI0_MISO_I, - SPI0_MISO_O, - SPI0_MISO_T, - SPI0_SS_I, - SPI0_SS_O, - SPI0_SS1_O, - SPI0_SS2_O, - SPI0_SS_T, + SPI1_SCLK_I, + SPI1_SCLK_O, + SPI1_SCLK_T, + SPI1_MOSI_I, + SPI1_MOSI_O, + SPI1_MOSI_T, + SPI1_MISO_I, + SPI1_MISO_O, + SPI1_MISO_T, + SPI1_SS_I, + SPI1_SS_O, + SPI1_SS1_O, + SPI1_SS2_O, + SPI1_SS_T, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, @@ -155,20 +155,20 @@ module mz_petalinux_processing_system7_0_0 (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_I" *) input I2C0_SCL_I; (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_O" *) output I2C0_SCL_O; (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_T" *) output I2C0_SCL_T; - (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SCK_I" *) input SPI0_SCLK_I; - (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SCK_O" *) output SPI0_SCLK_O; - (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SCK_T" *) output SPI0_SCLK_T; - (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 IO0_I" *) input SPI0_MOSI_I; - (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 IO0_O" *) output SPI0_MOSI_O; - (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 IO0_T" *) output SPI0_MOSI_T; - (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 IO1_I" *) input SPI0_MISO_I; - (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 IO1_O" *) output SPI0_MISO_O; - (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 IO1_T" *) output SPI0_MISO_T; - (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SS_I" *) input SPI0_SS_I; - (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SS_O" *) output SPI0_SS_O; - (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SS1_O" *) output SPI0_SS1_O; - (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SS2_O" *) output SPI0_SS2_O; - (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SS_T" *) output SPI0_SS_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SCK_I" *) input SPI1_SCLK_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SCK_O" *) output SPI1_SCLK_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SCK_T" *) output SPI1_SCLK_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO0_I" *) input SPI1_MOSI_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO0_O" *) output SPI1_MOSI_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO0_T" *) output SPI1_MOSI_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO1_I" *) input SPI1_MISO_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO1_O" *) output SPI1_MISO_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO1_T" *) output SPI1_MISO_T; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS_I" *) input SPI1_SS_I; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS_O" *) output SPI1_SS_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS1_O" *) output SPI1_SS1_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS2_O" *) output SPI1_SS2_O; + (* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS_T" *) output SPI1_SS_T; output TTC0_WAVE0_OUT; output TTC0_WAVE1_OUT; output TTC0_WAVE2_OUT; @@ -259,7 +259,7 @@ module mz_petalinux_processing_system7_0_0 (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WID" *) input [5:0]S_AXI_HP0_WID; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WDATA" *) input [63:0]S_AXI_HP0_WDATA; (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WSTRB" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI_HP0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 64, PROTOCOL AXI3, FREQ_HZ 99999999, ID_WIDTH 6, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, MAX_BURST_LENGTH 8, PHASE 0.000, CLK_DOMAIN mz_petalinux_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input [7:0]S_AXI_HP0_WSTRB; - (* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH:LEVEL_HIGH, PortWidth 2" *) input [1:0]IRQ_F2P; + (* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH:NULL, PortWidth 2" *) input [1:0]IRQ_F2P; (* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 FCLK_CLK0 CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 99999999, PHASE 0.000, CLK_DOMAIN mz_petalinux_processing_system7_0_0_FCLK_CLK0" *) output FCLK_CLK0; (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 FCLK_RESET0_N RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_RESET0_N, POLARITY ACTIVE_LOW" *) output FCLK_RESET0_N; (* X_INTERFACE_INFO = "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO" *) inout [53:0]MIO; @@ -353,20 +353,20 @@ module mz_petalinux_processing_system7_0_0 wire PS_CLK; wire PS_PORB; wire PS_SRSTB; - wire SPI0_MISO_I; - wire SPI0_MISO_O; - wire SPI0_MISO_T; - wire SPI0_MOSI_I; - wire SPI0_MOSI_O; - wire SPI0_MOSI_T; - wire SPI0_SCLK_I; - wire SPI0_SCLK_O; - wire SPI0_SCLK_T; - wire SPI0_SS1_O; - wire SPI0_SS2_O; - wire SPI0_SS_I; - wire SPI0_SS_O; - wire SPI0_SS_T; + wire SPI1_MISO_I; + wire SPI1_MISO_O; + wire SPI1_MISO_T; + wire SPI1_MOSI_I; + wire SPI1_MOSI_O; + wire SPI1_MOSI_T; + wire SPI1_SCLK_I; + wire SPI1_SCLK_O; + wire SPI1_SCLK_T; + wire SPI1_SS1_O; + wire SPI1_SS2_O; + wire SPI1_SS_I; + wire SPI1_SS_O; + wire SPI1_SS_T; wire S_AXI_HP0_ACLK; wire [31:0]S_AXI_HP0_ARADDR; wire [1:0]S_AXI_HP0_ARBURST; @@ -529,16 +529,16 @@ module mz_petalinux_processing_system7_0_0 wire NLW_inst_SDIO1_CMD_O_UNCONNECTED; wire NLW_inst_SDIO1_CMD_T_UNCONNECTED; wire NLW_inst_SDIO1_LED_UNCONNECTED; - wire NLW_inst_SPI1_MISO_O_UNCONNECTED; - wire NLW_inst_SPI1_MISO_T_UNCONNECTED; - wire NLW_inst_SPI1_MOSI_O_UNCONNECTED; - wire NLW_inst_SPI1_MOSI_T_UNCONNECTED; - wire NLW_inst_SPI1_SCLK_O_UNCONNECTED; - wire NLW_inst_SPI1_SCLK_T_UNCONNECTED; - wire NLW_inst_SPI1_SS1_O_UNCONNECTED; - wire NLW_inst_SPI1_SS2_O_UNCONNECTED; - wire NLW_inst_SPI1_SS_O_UNCONNECTED; - wire NLW_inst_SPI1_SS_T_UNCONNECTED; + wire NLW_inst_SPI0_MISO_O_UNCONNECTED; + wire NLW_inst_SPI0_MISO_T_UNCONNECTED; + wire NLW_inst_SPI0_MOSI_O_UNCONNECTED; + wire NLW_inst_SPI0_MOSI_T_UNCONNECTED; + wire NLW_inst_SPI0_SCLK_O_UNCONNECTED; + wire NLW_inst_SPI0_SCLK_T_UNCONNECTED; + wire NLW_inst_SPI0_SS1_O_UNCONNECTED; + wire NLW_inst_SPI0_SS2_O_UNCONNECTED; + wire NLW_inst_SPI0_SS_O_UNCONNECTED; + wire NLW_inst_SPI0_SS_T_UNCONNECTED; wire NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED; wire NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED; wire NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED; @@ -734,7 +734,7 @@ module mz_petalinux_processing_system7_0_0 (* C_USE_S_AXI_HP2 = "0" *) (* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "mz_petalinux_processing_system7_0_0.hwdef" *) - (* POWER = "/>" *) + (* POWER = "/>" *) (* USE_TRACE_DATA_EDGE_DETECTOR = "0" *) mz_petalinux_processing_system7_0_0_processing_system7_v5_5_processing_system7 inst (.CAN0_PHY_RX(1'b0), @@ -1047,34 +1047,34 @@ module mz_petalinux_processing_system7_0_0 .SDIO1_DATA_T(NLW_inst_SDIO1_DATA_T_UNCONNECTED[3:0]), .SDIO1_LED(NLW_inst_SDIO1_LED_UNCONNECTED), .SDIO1_WP(1'b0), - .SPI0_MISO_I(SPI0_MISO_I), - .SPI0_MISO_O(SPI0_MISO_O), - .SPI0_MISO_T(SPI0_MISO_T), - .SPI0_MOSI_I(SPI0_MOSI_I), - .SPI0_MOSI_O(SPI0_MOSI_O), - .SPI0_MOSI_T(SPI0_MOSI_T), - .SPI0_SCLK_I(SPI0_SCLK_I), - .SPI0_SCLK_O(SPI0_SCLK_O), - .SPI0_SCLK_T(SPI0_SCLK_T), - .SPI0_SS1_O(SPI0_SS1_O), - .SPI0_SS2_O(SPI0_SS2_O), - .SPI0_SS_I(SPI0_SS_I), - .SPI0_SS_O(SPI0_SS_O), - .SPI0_SS_T(SPI0_SS_T), - .SPI1_MISO_I(1'b0), - .SPI1_MISO_O(NLW_inst_SPI1_MISO_O_UNCONNECTED), - .SPI1_MISO_T(NLW_inst_SPI1_MISO_T_UNCONNECTED), - .SPI1_MOSI_I(1'b0), - .SPI1_MOSI_O(NLW_inst_SPI1_MOSI_O_UNCONNECTED), - .SPI1_MOSI_T(NLW_inst_SPI1_MOSI_T_UNCONNECTED), - .SPI1_SCLK_I(1'b0), - .SPI1_SCLK_O(NLW_inst_SPI1_SCLK_O_UNCONNECTED), - .SPI1_SCLK_T(NLW_inst_SPI1_SCLK_T_UNCONNECTED), - .SPI1_SS1_O(NLW_inst_SPI1_SS1_O_UNCONNECTED), - .SPI1_SS2_O(NLW_inst_SPI1_SS2_O_UNCONNECTED), - .SPI1_SS_I(1'b0), - .SPI1_SS_O(NLW_inst_SPI1_SS_O_UNCONNECTED), - .SPI1_SS_T(NLW_inst_SPI1_SS_T_UNCONNECTED), + .SPI0_MISO_I(1'b0), + .SPI0_MISO_O(NLW_inst_SPI0_MISO_O_UNCONNECTED), + .SPI0_MISO_T(NLW_inst_SPI0_MISO_T_UNCONNECTED), + .SPI0_MOSI_I(1'b0), + .SPI0_MOSI_O(NLW_inst_SPI0_MOSI_O_UNCONNECTED), + .SPI0_MOSI_T(NLW_inst_SPI0_MOSI_T_UNCONNECTED), + .SPI0_SCLK_I(1'b0), + .SPI0_SCLK_O(NLW_inst_SPI0_SCLK_O_UNCONNECTED), + .SPI0_SCLK_T(NLW_inst_SPI0_SCLK_T_UNCONNECTED), + .SPI0_SS1_O(NLW_inst_SPI0_SS1_O_UNCONNECTED), + .SPI0_SS2_O(NLW_inst_SPI0_SS2_O_UNCONNECTED), + .SPI0_SS_I(1'b0), + .SPI0_SS_O(NLW_inst_SPI0_SS_O_UNCONNECTED), + .SPI0_SS_T(NLW_inst_SPI0_SS_T_UNCONNECTED), + .SPI1_MISO_I(SPI1_MISO_I), + .SPI1_MISO_O(SPI1_MISO_O), + .SPI1_MISO_T(SPI1_MISO_T), + .SPI1_MOSI_I(SPI1_MOSI_I), + .SPI1_MOSI_O(SPI1_MOSI_O), + .SPI1_MOSI_T(SPI1_MOSI_T), + .SPI1_SCLK_I(SPI1_SCLK_I), + .SPI1_SCLK_O(SPI1_SCLK_O), + .SPI1_SCLK_T(SPI1_SCLK_T), + .SPI1_SS1_O(SPI1_SS1_O), + .SPI1_SS2_O(SPI1_SS2_O), + .SPI1_SS_I(SPI1_SS_I), + .SPI1_SS_O(SPI1_SS_O), + .SPI1_SS_T(SPI1_SS_T), .SRAM_INTIN(1'b0), .S_AXI_ACP_ACLK(1'b0), .S_AXI_ACP_ARADDR({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), @@ -1443,7 +1443,7 @@ endmodule (* C_USE_S_AXI_ACP = "0" *) (* C_USE_S_AXI_GP0 = "0" *) (* C_USE_S_AXI_GP1 = "0" *) (* C_USE_S_AXI_HP0 = "1" *) (* C_USE_S_AXI_HP1 = "0" *) (* C_USE_S_AXI_HP2 = "0" *) (* C_USE_S_AXI_HP3 = "0" *) (* HW_HANDOFF = "mz_petalinux_processing_system7_0_0.hwdef" *) (* ORIG_REF_NAME = "processing_system7_v5_5_processing_system7" *) -(* POWER = "/>" *) (* USE_TRACE_DATA_EDGE_DETECTOR = "0" *) +(* POWER = "/>" *) (* USE_TRACE_DATA_EDGE_DETECTOR = "0" *) module mz_petalinux_processing_system7_0_0_processing_system7_v5_5_processing_system7 (CAN0_PHY_TX, CAN0_PHY_RX, diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0_sim_netlist.vhdl b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0_sim_netlist.vhdl index 1537526d94d90ad254afda82dda6036f121dce6e..4c27810b46388b86825f813517dc4c3f007e7acc 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0_sim_netlist.vhdl +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0_sim_netlist.vhdl @@ -1,8 +1,8 @@ -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 --- Date : Fri Jul 12 14:21:10 2019 --- Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.2 LTS +-- Date : Sun Oct 20 22:43:58 2019 +-- Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS -- Command : write_vhdl -force -mode funcsim -- /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0_sim_netlist.vhdl -- Design : mz_petalinux_processing_system7_0_0 @@ -817,7 +817,7 @@ entity mz_petalinux_processing_system7_0_0_processing_system7_v5_5_processing_sy attribute ORIG_REF_NAME : string; attribute ORIG_REF_NAME of mz_petalinux_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "processing_system7_v5_5_processing_system7"; attribute POWER : string; - attribute POWER of mz_petalinux_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "/>"; + attribute POWER of mz_petalinux_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is "/>"; attribute USE_TRACE_DATA_EDGE_DETECTOR : integer; attribute USE_TRACE_DATA_EDGE_DETECTOR of mz_petalinux_processing_system7_0_0_processing_system7_v5_5_processing_system7 : entity is 0; end mz_petalinux_processing_system7_0_0_processing_system7_v5_5_processing_system7; @@ -3365,20 +3365,20 @@ entity mz_petalinux_processing_system7_0_0 is I2C0_SCL_I : in STD_LOGIC; I2C0_SCL_O : out STD_LOGIC; I2C0_SCL_T : out STD_LOGIC; - SPI0_SCLK_I : in STD_LOGIC; - SPI0_SCLK_O : out STD_LOGIC; - SPI0_SCLK_T : out STD_LOGIC; - SPI0_MOSI_I : in STD_LOGIC; - SPI0_MOSI_O : out STD_LOGIC; - SPI0_MOSI_T : out STD_LOGIC; - SPI0_MISO_I : in STD_LOGIC; - SPI0_MISO_O : out STD_LOGIC; - SPI0_MISO_T : out STD_LOGIC; - SPI0_SS_I : in STD_LOGIC; - SPI0_SS_O : out STD_LOGIC; - SPI0_SS1_O : out STD_LOGIC; - SPI0_SS2_O : out STD_LOGIC; - SPI0_SS_T : out STD_LOGIC; + SPI1_SCLK_I : in STD_LOGIC; + SPI1_SCLK_O : out STD_LOGIC; + SPI1_SCLK_T : out STD_LOGIC; + SPI1_MOSI_I : in STD_LOGIC; + SPI1_MOSI_O : out STD_LOGIC; + SPI1_MOSI_T : out STD_LOGIC; + SPI1_MISO_I : in STD_LOGIC; + SPI1_MISO_O : out STD_LOGIC; + SPI1_MISO_T : out STD_LOGIC; + SPI1_SS_I : in STD_LOGIC; + SPI1_SS_O : out STD_LOGIC; + SPI1_SS1_O : out STD_LOGIC; + SPI1_SS2_O : out STD_LOGIC; + SPI1_SS_T : out STD_LOGIC; TTC0_WAVE0_OUT : out STD_LOGIC; TTC0_WAVE1_OUT : out STD_LOGIC; TTC0_WAVE2_OUT : out STD_LOGIC; @@ -3616,16 +3616,16 @@ architecture STRUCTURE of mz_petalinux_processing_system7_0_0 is signal NLW_inst_SDIO1_CMD_O_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_CMD_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_SDIO1_LED_UNCONNECTED : STD_LOGIC; - signal NLW_inst_SPI1_MISO_O_UNCONNECTED : STD_LOGIC; - signal NLW_inst_SPI1_MISO_T_UNCONNECTED : STD_LOGIC; - signal NLW_inst_SPI1_MOSI_O_UNCONNECTED : STD_LOGIC; - signal NLW_inst_SPI1_MOSI_T_UNCONNECTED : STD_LOGIC; - signal NLW_inst_SPI1_SCLK_O_UNCONNECTED : STD_LOGIC; - signal NLW_inst_SPI1_SCLK_T_UNCONNECTED : STD_LOGIC; - signal NLW_inst_SPI1_SS1_O_UNCONNECTED : STD_LOGIC; - signal NLW_inst_SPI1_SS2_O_UNCONNECTED : STD_LOGIC; - signal NLW_inst_SPI1_SS_O_UNCONNECTED : STD_LOGIC; - signal NLW_inst_SPI1_SS_T_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI0_MISO_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI0_MISO_T_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI0_MOSI_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI0_MOSI_T_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI0_SCLK_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI0_SCLK_T_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI0_SS1_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI0_SS2_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI0_SS_O_UNCONNECTED : STD_LOGIC; + signal NLW_inst_SPI0_SS_T_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_ARESETN_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_ARREADY_UNCONNECTED : STD_LOGIC; signal NLW_inst_S_AXI_ACP_AWREADY_UNCONNECTED : STD_LOGIC; @@ -3877,7 +3877,7 @@ architecture STRUCTURE of mz_petalinux_processing_system7_0_0 is attribute HW_HANDOFF : string; attribute HW_HANDOFF of inst : label is "mz_petalinux_processing_system7_0_0.hwdef"; attribute POWER : string; - attribute POWER of inst : label is "/>"; + attribute POWER of inst : label is "/>"; attribute USE_TRACE_DATA_EDGE_DETECTOR : integer; attribute USE_TRACE_DATA_EDGE_DETECTOR of inst : label is 0; attribute X_INTERFACE_INFO : string; @@ -3921,20 +3921,20 @@ architecture STRUCTURE of mz_petalinux_processing_system7_0_0 is attribute X_INTERFACE_INFO of PS_PORB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_PORB"; attribute X_INTERFACE_PARAMETER of PS_PORB : signal is "XIL_INTERFACENAME FIXED_IO, CAN_DEBUG false"; attribute X_INTERFACE_INFO of PS_SRSTB : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO PS_SRSTB"; - attribute X_INTERFACE_INFO of SPI0_MISO_I : signal is "xilinx.com:interface:spi:1.0 SPI_0 IO1_I"; - attribute X_INTERFACE_INFO of SPI0_MISO_O : signal is "xilinx.com:interface:spi:1.0 SPI_0 IO1_O"; - attribute X_INTERFACE_INFO of SPI0_MISO_T : signal is "xilinx.com:interface:spi:1.0 SPI_0 IO1_T"; - attribute X_INTERFACE_INFO of SPI0_MOSI_I : signal is "xilinx.com:interface:spi:1.0 SPI_0 IO0_I"; - attribute X_INTERFACE_INFO of SPI0_MOSI_O : signal is "xilinx.com:interface:spi:1.0 SPI_0 IO0_O"; - attribute X_INTERFACE_INFO of SPI0_MOSI_T : signal is "xilinx.com:interface:spi:1.0 SPI_0 IO0_T"; - attribute X_INTERFACE_INFO of SPI0_SCLK_I : signal is "xilinx.com:interface:spi:1.0 SPI_0 SCK_I"; - attribute X_INTERFACE_INFO of SPI0_SCLK_O : signal is "xilinx.com:interface:spi:1.0 SPI_0 SCK_O"; - attribute X_INTERFACE_INFO of SPI0_SCLK_T : signal is "xilinx.com:interface:spi:1.0 SPI_0 SCK_T"; - attribute X_INTERFACE_INFO of SPI0_SS1_O : signal is "xilinx.com:interface:spi:1.0 SPI_0 SS1_O"; - attribute X_INTERFACE_INFO of SPI0_SS2_O : signal is "xilinx.com:interface:spi:1.0 SPI_0 SS2_O"; - attribute X_INTERFACE_INFO of SPI0_SS_I : signal is "xilinx.com:interface:spi:1.0 SPI_0 SS_I"; - attribute X_INTERFACE_INFO of SPI0_SS_O : signal is "xilinx.com:interface:spi:1.0 SPI_0 SS_O"; - attribute X_INTERFACE_INFO of SPI0_SS_T : signal is "xilinx.com:interface:spi:1.0 SPI_0 SS_T"; + attribute X_INTERFACE_INFO of SPI1_MISO_I : signal is "xilinx.com:interface:spi:1.0 SPI_1 IO1_I"; + attribute X_INTERFACE_INFO of SPI1_MISO_O : signal is "xilinx.com:interface:spi:1.0 SPI_1 IO1_O"; + attribute X_INTERFACE_INFO of SPI1_MISO_T : signal is "xilinx.com:interface:spi:1.0 SPI_1 IO1_T"; + attribute X_INTERFACE_INFO of SPI1_MOSI_I : signal is "xilinx.com:interface:spi:1.0 SPI_1 IO0_I"; + attribute X_INTERFACE_INFO of SPI1_MOSI_O : signal is "xilinx.com:interface:spi:1.0 SPI_1 IO0_O"; + attribute X_INTERFACE_INFO of SPI1_MOSI_T : signal is "xilinx.com:interface:spi:1.0 SPI_1 IO0_T"; + attribute X_INTERFACE_INFO of SPI1_SCLK_I : signal is "xilinx.com:interface:spi:1.0 SPI_1 SCK_I"; + attribute X_INTERFACE_INFO of SPI1_SCLK_O : signal is "xilinx.com:interface:spi:1.0 SPI_1 SCK_O"; + attribute X_INTERFACE_INFO of SPI1_SCLK_T : signal is "xilinx.com:interface:spi:1.0 SPI_1 SCK_T"; + attribute X_INTERFACE_INFO of SPI1_SS1_O : signal is "xilinx.com:interface:spi:1.0 SPI_1 SS1_O"; + attribute X_INTERFACE_INFO of SPI1_SS2_O : signal is "xilinx.com:interface:spi:1.0 SPI_1 SS2_O"; + attribute X_INTERFACE_INFO of SPI1_SS_I : signal is "xilinx.com:interface:spi:1.0 SPI_1 SS_I"; + attribute X_INTERFACE_INFO of SPI1_SS_O : signal is "xilinx.com:interface:spi:1.0 SPI_1 SS_O"; + attribute X_INTERFACE_INFO of SPI1_SS_T : signal is "xilinx.com:interface:spi:1.0 SPI_1 SS_T"; attribute X_INTERFACE_INFO of S_AXI_HP0_ACLK : signal is "xilinx.com:signal:clock:1.0 S_AXI_HP0_ACLK CLK"; attribute X_INTERFACE_PARAMETER of S_AXI_HP0_ACLK : signal is "XIL_INTERFACENAME S_AXI_HP0_ACLK, ASSOCIATED_BUSIF S_AXI_HP0, FREQ_HZ 99999999, PHASE 0.000, CLK_DOMAIN mz_petalinux_processing_system7_0_0_FCLK_CLK0"; attribute X_INTERFACE_INFO of S_AXI_HP0_ARREADY : signal is "xilinx.com:interface:aximm:1.0 S_AXI_HP0 ARREADY"; @@ -3961,7 +3961,7 @@ architecture STRUCTURE of mz_petalinux_processing_system7_0_0 is attribute X_INTERFACE_PARAMETER of DDR_DQS : signal is "XIL_INTERFACENAME DDR, CAN_DEBUG false, TIMEPERIOD_PS 1250, MEMORY_TYPE COMPONENTS, DATA_WIDTH 8, CS_ENABLED true, DATA_MASK_ENABLED true, SLOT Single, MEM_ADDR_MAP ROW_COLUMN_BANK, BURST_LENGTH 8, AXI_ARBITRATION_SCHEME TDM, CAS_LATENCY 11, CAS_WRITE_LATENCY 11"; attribute X_INTERFACE_INFO of DDR_DQS_n : signal is "xilinx.com:interface:ddrx:1.0 DDR DQS_N"; attribute X_INTERFACE_INFO of IRQ_F2P : signal is "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT"; - attribute X_INTERFACE_PARAMETER of IRQ_F2P : signal is "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH:LEVEL_HIGH, PortWidth 2"; + attribute X_INTERFACE_PARAMETER of IRQ_F2P : signal is "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH:NULL, PortWidth 2"; attribute X_INTERFACE_INFO of MIO : signal is "xilinx.com:display_processing_system7:fixedio:1.0 FIXED_IO MIO"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARADDR : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARADDR"; attribute X_INTERFACE_INFO of M_AXI_GP0_ARBURST : signal is "xilinx.com:interface:aximm:1.0 M_AXI_GP0 ARBURST"; @@ -4335,34 +4335,34 @@ inst: entity work.mz_petalinux_processing_system7_0_0_processing_system7_v5_5_pr SDIO1_DATA_T(3 downto 0) => NLW_inst_SDIO1_DATA_T_UNCONNECTED(3 downto 0), SDIO1_LED => NLW_inst_SDIO1_LED_UNCONNECTED, SDIO1_WP => '0', - SPI0_MISO_I => SPI0_MISO_I, - SPI0_MISO_O => SPI0_MISO_O, - SPI0_MISO_T => SPI0_MISO_T, - SPI0_MOSI_I => SPI0_MOSI_I, - SPI0_MOSI_O => SPI0_MOSI_O, - SPI0_MOSI_T => SPI0_MOSI_T, - SPI0_SCLK_I => SPI0_SCLK_I, - SPI0_SCLK_O => SPI0_SCLK_O, - SPI0_SCLK_T => SPI0_SCLK_T, - SPI0_SS1_O => SPI0_SS1_O, - SPI0_SS2_O => SPI0_SS2_O, - SPI0_SS_I => SPI0_SS_I, - SPI0_SS_O => SPI0_SS_O, - SPI0_SS_T => SPI0_SS_T, - SPI1_MISO_I => '0', - SPI1_MISO_O => NLW_inst_SPI1_MISO_O_UNCONNECTED, - SPI1_MISO_T => NLW_inst_SPI1_MISO_T_UNCONNECTED, - SPI1_MOSI_I => '0', - SPI1_MOSI_O => NLW_inst_SPI1_MOSI_O_UNCONNECTED, - SPI1_MOSI_T => NLW_inst_SPI1_MOSI_T_UNCONNECTED, - SPI1_SCLK_I => '0', - SPI1_SCLK_O => NLW_inst_SPI1_SCLK_O_UNCONNECTED, - SPI1_SCLK_T => NLW_inst_SPI1_SCLK_T_UNCONNECTED, - SPI1_SS1_O => NLW_inst_SPI1_SS1_O_UNCONNECTED, - SPI1_SS2_O => NLW_inst_SPI1_SS2_O_UNCONNECTED, - SPI1_SS_I => '0', - SPI1_SS_O => NLW_inst_SPI1_SS_O_UNCONNECTED, - SPI1_SS_T => NLW_inst_SPI1_SS_T_UNCONNECTED, + SPI0_MISO_I => '0', + SPI0_MISO_O => NLW_inst_SPI0_MISO_O_UNCONNECTED, + SPI0_MISO_T => NLW_inst_SPI0_MISO_T_UNCONNECTED, + SPI0_MOSI_I => '0', + SPI0_MOSI_O => NLW_inst_SPI0_MOSI_O_UNCONNECTED, + SPI0_MOSI_T => NLW_inst_SPI0_MOSI_T_UNCONNECTED, + SPI0_SCLK_I => '0', + SPI0_SCLK_O => NLW_inst_SPI0_SCLK_O_UNCONNECTED, + SPI0_SCLK_T => NLW_inst_SPI0_SCLK_T_UNCONNECTED, + SPI0_SS1_O => NLW_inst_SPI0_SS1_O_UNCONNECTED, + SPI0_SS2_O => NLW_inst_SPI0_SS2_O_UNCONNECTED, + SPI0_SS_I => '0', + SPI0_SS_O => NLW_inst_SPI0_SS_O_UNCONNECTED, + SPI0_SS_T => NLW_inst_SPI0_SS_T_UNCONNECTED, + SPI1_MISO_I => SPI1_MISO_I, + SPI1_MISO_O => SPI1_MISO_O, + SPI1_MISO_T => SPI1_MISO_T, + SPI1_MOSI_I => SPI1_MOSI_I, + SPI1_MOSI_O => SPI1_MOSI_O, + SPI1_MOSI_T => SPI1_MOSI_T, + SPI1_SCLK_I => SPI1_SCLK_I, + SPI1_SCLK_O => SPI1_SCLK_O, + SPI1_SCLK_T => SPI1_SCLK_T, + SPI1_SS1_O => SPI1_SS1_O, + SPI1_SS2_O => SPI1_SS2_O, + SPI1_SS_I => SPI1_SS_I, + SPI1_SS_O => SPI1_SS_O, + SPI1_SS_T => SPI1_SS_T, SRAM_INTIN => '0', S_AXI_ACP_ACLK => '0', S_AXI_ACP_ARADDR(31 downto 0) => B"00000000000000000000000000000000", diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0_stub.v b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0_stub.v index 23626a9efb5e4e5756ef09325f811b3ce623a66b..faf53bf61eee07bcacfbf82b42cfa37d558a65a3 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0_stub.v +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0_stub.v @@ -1,8 +1,8 @@ // Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 -// Date : Fri Jul 12 14:21:10 2019 -// Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.2 LTS +// Date : Sun Oct 20 22:43:57 2019 +// Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS // Command : write_verilog -force -mode synth_stub // /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0_stub.v // Design : mz_petalinux_processing_system7_0_0 @@ -15,9 +15,9 @@ // Please paste the declaration into a Verilog source file or add the file as an additional source. (* X_CORE_INFO = "processing_system7_v5_5_processing_system7,Vivado 2017.4" *) module mz_petalinux_processing_system7_0_0(I2C0_SDA_I, I2C0_SDA_O, I2C0_SDA_T, I2C0_SCL_I, - I2C0_SCL_O, I2C0_SCL_T, SPI0_SCLK_I, SPI0_SCLK_O, SPI0_SCLK_T, SPI0_MOSI_I, SPI0_MOSI_O, - SPI0_MOSI_T, SPI0_MISO_I, SPI0_MISO_O, SPI0_MISO_T, SPI0_SS_I, SPI0_SS_O, SPI0_SS1_O, - SPI0_SS2_O, SPI0_SS_T, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, USB0_PORT_INDCTL, + I2C0_SCL_O, I2C0_SCL_T, SPI1_SCLK_I, SPI1_SCLK_O, SPI1_SCLK_T, SPI1_MOSI_I, SPI1_MOSI_O, + SPI1_MOSI_T, SPI1_MISO_I, SPI1_MISO_O, SPI1_MISO_T, SPI1_SS_I, SPI1_SS_O, SPI1_SS1_O, + SPI1_SS2_O, SPI1_SS_T, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, USB0_PORT_INDCTL, USB0_VBUS_PWRSELECT, USB0_VBUS_PWRFAULT, M_AXI_GP0_ARVALID, M_AXI_GP0_AWVALID, M_AXI_GP0_BREADY, M_AXI_GP0_RREADY, M_AXI_GP0_WLAST, M_AXI_GP0_WVALID, M_AXI_GP0_ARID, M_AXI_GP0_AWID, M_AXI_GP0_WID, M_AXI_GP0_ARBURST, M_AXI_GP0_ARLOCK, M_AXI_GP0_ARSIZE, @@ -39,27 +39,27 @@ module mz_petalinux_processing_system7_0_0(I2C0_SDA_I, I2C0_SDA_O, I2C0_SDA_T, I S_AXI_HP0_WDATA, S_AXI_HP0_WSTRB, IRQ_F2P, FCLK_CLK0, FCLK_RESET0_N, MIO, DDR_CAS_n, DDR_CKE, DDR_Clk_n, DDR_Clk, DDR_CS_n, DDR_DRSTB, DDR_ODT, DDR_RAS_n, DDR_WEB, DDR_BankAddr, DDR_Addr, DDR_VRN, DDR_VRP, DDR_DM, DDR_DQ, DDR_DQS_n, DDR_DQS, PS_SRSTB, PS_CLK, PS_PORB) -/* synthesis syn_black_box black_box_pad_pin="I2C0_SDA_I,I2C0_SDA_O,I2C0_SDA_T,I2C0_SCL_I,I2C0_SCL_O,I2C0_SCL_T,SPI0_SCLK_I,SPI0_SCLK_O,SPI0_SCLK_T,SPI0_MOSI_I,SPI0_MOSI_O,SPI0_MOSI_T,SPI0_MISO_I,SPI0_MISO_O,SPI0_MISO_T,SPI0_SS_I,SPI0_SS_O,SPI0_SS1_O,SPI0_SS2_O,SPI0_SS_T,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],S_AXI_HP0_ARREADY,S_AXI_HP0_AWREADY,S_AXI_HP0_BVALID,S_AXI_HP0_RLAST,S_AXI_HP0_RVALID,S_AXI_HP0_WREADY,S_AXI_HP0_BRESP[1:0],S_AXI_HP0_RRESP[1:0],S_AXI_HP0_BID[5:0],S_AXI_HP0_RID[5:0],S_AXI_HP0_RDATA[63:0],S_AXI_HP0_RCOUNT[7:0],S_AXI_HP0_WCOUNT[7:0],S_AXI_HP0_RACOUNT[2:0],S_AXI_HP0_WACOUNT[5:0],S_AXI_HP0_ACLK,S_AXI_HP0_ARVALID,S_AXI_HP0_AWVALID,S_AXI_HP0_BREADY,S_AXI_HP0_RDISSUECAP1_EN,S_AXI_HP0_RREADY,S_AXI_HP0_WLAST,S_AXI_HP0_WRISSUECAP1_EN,S_AXI_HP0_WVALID,S_AXI_HP0_ARBURST[1:0],S_AXI_HP0_ARLOCK[1:0],S_AXI_HP0_ARSIZE[2:0],S_AXI_HP0_AWBURST[1:0],S_AXI_HP0_AWLOCK[1:0],S_AXI_HP0_AWSIZE[2:0],S_AXI_HP0_ARPROT[2:0],S_AXI_HP0_AWPROT[2:0],S_AXI_HP0_ARADDR[31:0],S_AXI_HP0_AWADDR[31:0],S_AXI_HP0_ARCACHE[3:0],S_AXI_HP0_ARLEN[3:0],S_AXI_HP0_ARQOS[3:0],S_AXI_HP0_AWCACHE[3:0],S_AXI_HP0_AWLEN[3:0],S_AXI_HP0_AWQOS[3:0],S_AXI_HP0_ARID[5:0],S_AXI_HP0_AWID[5:0],S_AXI_HP0_WID[5:0],S_AXI_HP0_WDATA[63:0],S_AXI_HP0_WSTRB[7:0],IRQ_F2P[1:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */; +/* synthesis syn_black_box black_box_pad_pin="I2C0_SDA_I,I2C0_SDA_O,I2C0_SDA_T,I2C0_SCL_I,I2C0_SCL_O,I2C0_SCL_T,SPI1_SCLK_I,SPI1_SCLK_O,SPI1_SCLK_T,SPI1_MOSI_I,SPI1_MOSI_O,SPI1_MOSI_T,SPI1_MISO_I,SPI1_MISO_O,SPI1_MISO_T,SPI1_SS_I,SPI1_SS_O,SPI1_SS1_O,SPI1_SS2_O,SPI1_SS_T,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],S_AXI_HP0_ARREADY,S_AXI_HP0_AWREADY,S_AXI_HP0_BVALID,S_AXI_HP0_RLAST,S_AXI_HP0_RVALID,S_AXI_HP0_WREADY,S_AXI_HP0_BRESP[1:0],S_AXI_HP0_RRESP[1:0],S_AXI_HP0_BID[5:0],S_AXI_HP0_RID[5:0],S_AXI_HP0_RDATA[63:0],S_AXI_HP0_RCOUNT[7:0],S_AXI_HP0_WCOUNT[7:0],S_AXI_HP0_RACOUNT[2:0],S_AXI_HP0_WACOUNT[5:0],S_AXI_HP0_ACLK,S_AXI_HP0_ARVALID,S_AXI_HP0_AWVALID,S_AXI_HP0_BREADY,S_AXI_HP0_RDISSUECAP1_EN,S_AXI_HP0_RREADY,S_AXI_HP0_WLAST,S_AXI_HP0_WRISSUECAP1_EN,S_AXI_HP0_WVALID,S_AXI_HP0_ARBURST[1:0],S_AXI_HP0_ARLOCK[1:0],S_AXI_HP0_ARSIZE[2:0],S_AXI_HP0_AWBURST[1:0],S_AXI_HP0_AWLOCK[1:0],S_AXI_HP0_AWSIZE[2:0],S_AXI_HP0_ARPROT[2:0],S_AXI_HP0_AWPROT[2:0],S_AXI_HP0_ARADDR[31:0],S_AXI_HP0_AWADDR[31:0],S_AXI_HP0_ARCACHE[3:0],S_AXI_HP0_ARLEN[3:0],S_AXI_HP0_ARQOS[3:0],S_AXI_HP0_AWCACHE[3:0],S_AXI_HP0_AWLEN[3:0],S_AXI_HP0_AWQOS[3:0],S_AXI_HP0_ARID[5:0],S_AXI_HP0_AWID[5:0],S_AXI_HP0_WID[5:0],S_AXI_HP0_WDATA[63:0],S_AXI_HP0_WSTRB[7:0],IRQ_F2P[1:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB" */; input I2C0_SDA_I; output I2C0_SDA_O; output I2C0_SDA_T; input I2C0_SCL_I; output I2C0_SCL_O; output I2C0_SCL_T; - input SPI0_SCLK_I; - output SPI0_SCLK_O; - output SPI0_SCLK_T; - input SPI0_MOSI_I; - output SPI0_MOSI_O; - output SPI0_MOSI_T; - input SPI0_MISO_I; - output SPI0_MISO_O; - output SPI0_MISO_T; - input SPI0_SS_I; - output SPI0_SS_O; - output SPI0_SS1_O; - output SPI0_SS2_O; - output SPI0_SS_T; + input SPI1_SCLK_I; + output SPI1_SCLK_O; + output SPI1_SCLK_T; + input SPI1_MOSI_I; + output SPI1_MOSI_O; + output SPI1_MOSI_T; + input SPI1_MISO_I; + output SPI1_MISO_O; + output SPI1_MISO_T; + input SPI1_SS_I; + output SPI1_SS_O; + output SPI1_SS1_O; + output SPI1_SS2_O; + output SPI1_SS_T; output TTC0_WAVE0_OUT; output TTC0_WAVE1_OUT; output TTC0_WAVE2_OUT; diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0_stub.vhdl b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0_stub.vhdl index a1320a448fbf51a4aa4d4cc85dcafdae65a879f8..a2d639b18f11722e5ec96f47379399c76c8482d0 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0_stub.vhdl +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0_stub.vhdl @@ -1,8 +1,8 @@ -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 --- Date : Fri Jul 12 14:21:10 2019 --- Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.2 LTS +-- Date : Sun Oct 20 22:43:57 2019 +-- Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS -- Command : write_vhdl -force -mode synth_stub -- /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/mz_petalinux_processing_system7_0_0_stub.vhdl -- Design : mz_petalinux_processing_system7_0_0 @@ -20,20 +20,20 @@ entity mz_petalinux_processing_system7_0_0 is I2C0_SCL_I : in STD_LOGIC; I2C0_SCL_O : out STD_LOGIC; I2C0_SCL_T : out STD_LOGIC; - SPI0_SCLK_I : in STD_LOGIC; - SPI0_SCLK_O : out STD_LOGIC; - SPI0_SCLK_T : out STD_LOGIC; - SPI0_MOSI_I : in STD_LOGIC; - SPI0_MOSI_O : out STD_LOGIC; - SPI0_MOSI_T : out STD_LOGIC; - SPI0_MISO_I : in STD_LOGIC; - SPI0_MISO_O : out STD_LOGIC; - SPI0_MISO_T : out STD_LOGIC; - SPI0_SS_I : in STD_LOGIC; - SPI0_SS_O : out STD_LOGIC; - SPI0_SS1_O : out STD_LOGIC; - SPI0_SS2_O : out STD_LOGIC; - SPI0_SS_T : out STD_LOGIC; + SPI1_SCLK_I : in STD_LOGIC; + SPI1_SCLK_O : out STD_LOGIC; + SPI1_SCLK_T : out STD_LOGIC; + SPI1_MOSI_I : in STD_LOGIC; + SPI1_MOSI_O : out STD_LOGIC; + SPI1_MOSI_T : out STD_LOGIC; + SPI1_MISO_I : in STD_LOGIC; + SPI1_MISO_O : out STD_LOGIC; + SPI1_MISO_T : out STD_LOGIC; + SPI1_SS_I : in STD_LOGIC; + SPI1_SS_O : out STD_LOGIC; + SPI1_SS1_O : out STD_LOGIC; + SPI1_SS2_O : out STD_LOGIC; + SPI1_SS_T : out STD_LOGIC; TTC0_WAVE0_OUT : out STD_LOGIC; TTC0_WAVE1_OUT : out STD_LOGIC; TTC0_WAVE2_OUT : out STD_LOGIC; @@ -156,7 +156,7 @@ architecture stub of mz_petalinux_processing_system7_0_0 is attribute syn_black_box : boolean; attribute black_box_pad_pin : string; attribute syn_black_box of stub : architecture is true; -attribute black_box_pad_pin of stub : architecture is "I2C0_SDA_I,I2C0_SDA_O,I2C0_SDA_T,I2C0_SCL_I,I2C0_SCL_O,I2C0_SCL_T,SPI0_SCLK_I,SPI0_SCLK_O,SPI0_SCLK_T,SPI0_MOSI_I,SPI0_MOSI_O,SPI0_MOSI_T,SPI0_MISO_I,SPI0_MISO_O,SPI0_MISO_T,SPI0_SS_I,SPI0_SS_O,SPI0_SS1_O,SPI0_SS2_O,SPI0_SS_T,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],S_AXI_HP0_ARREADY,S_AXI_HP0_AWREADY,S_AXI_HP0_BVALID,S_AXI_HP0_RLAST,S_AXI_HP0_RVALID,S_AXI_HP0_WREADY,S_AXI_HP0_BRESP[1:0],S_AXI_HP0_RRESP[1:0],S_AXI_HP0_BID[5:0],S_AXI_HP0_RID[5:0],S_AXI_HP0_RDATA[63:0],S_AXI_HP0_RCOUNT[7:0],S_AXI_HP0_WCOUNT[7:0],S_AXI_HP0_RACOUNT[2:0],S_AXI_HP0_WACOUNT[5:0],S_AXI_HP0_ACLK,S_AXI_HP0_ARVALID,S_AXI_HP0_AWVALID,S_AXI_HP0_BREADY,S_AXI_HP0_RDISSUECAP1_EN,S_AXI_HP0_RREADY,S_AXI_HP0_WLAST,S_AXI_HP0_WRISSUECAP1_EN,S_AXI_HP0_WVALID,S_AXI_HP0_ARBURST[1:0],S_AXI_HP0_ARLOCK[1:0],S_AXI_HP0_ARSIZE[2:0],S_AXI_HP0_AWBURST[1:0],S_AXI_HP0_AWLOCK[1:0],S_AXI_HP0_AWSIZE[2:0],S_AXI_HP0_ARPROT[2:0],S_AXI_HP0_AWPROT[2:0],S_AXI_HP0_ARADDR[31:0],S_AXI_HP0_AWADDR[31:0],S_AXI_HP0_ARCACHE[3:0],S_AXI_HP0_ARLEN[3:0],S_AXI_HP0_ARQOS[3:0],S_AXI_HP0_AWCACHE[3:0],S_AXI_HP0_AWLEN[3:0],S_AXI_HP0_AWQOS[3:0],S_AXI_HP0_ARID[5:0],S_AXI_HP0_AWID[5:0],S_AXI_HP0_WID[5:0],S_AXI_HP0_WDATA[63:0],S_AXI_HP0_WSTRB[7:0],IRQ_F2P[1:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB"; +attribute black_box_pad_pin of stub : architecture is "I2C0_SDA_I,I2C0_SDA_O,I2C0_SDA_T,I2C0_SCL_I,I2C0_SCL_O,I2C0_SCL_T,SPI1_SCLK_I,SPI1_SCLK_O,SPI1_SCLK_T,SPI1_MOSI_I,SPI1_MOSI_O,SPI1_MOSI_T,SPI1_MISO_I,SPI1_MISO_O,SPI1_MISO_T,SPI1_SS_I,SPI1_SS_O,SPI1_SS1_O,SPI1_SS2_O,SPI1_SS_T,TTC0_WAVE0_OUT,TTC0_WAVE1_OUT,TTC0_WAVE2_OUT,USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],S_AXI_HP0_ARREADY,S_AXI_HP0_AWREADY,S_AXI_HP0_BVALID,S_AXI_HP0_RLAST,S_AXI_HP0_RVALID,S_AXI_HP0_WREADY,S_AXI_HP0_BRESP[1:0],S_AXI_HP0_RRESP[1:0],S_AXI_HP0_BID[5:0],S_AXI_HP0_RID[5:0],S_AXI_HP0_RDATA[63:0],S_AXI_HP0_RCOUNT[7:0],S_AXI_HP0_WCOUNT[7:0],S_AXI_HP0_RACOUNT[2:0],S_AXI_HP0_WACOUNT[5:0],S_AXI_HP0_ACLK,S_AXI_HP0_ARVALID,S_AXI_HP0_AWVALID,S_AXI_HP0_BREADY,S_AXI_HP0_RDISSUECAP1_EN,S_AXI_HP0_RREADY,S_AXI_HP0_WLAST,S_AXI_HP0_WRISSUECAP1_EN,S_AXI_HP0_WVALID,S_AXI_HP0_ARBURST[1:0],S_AXI_HP0_ARLOCK[1:0],S_AXI_HP0_ARSIZE[2:0],S_AXI_HP0_AWBURST[1:0],S_AXI_HP0_AWLOCK[1:0],S_AXI_HP0_AWSIZE[2:0],S_AXI_HP0_ARPROT[2:0],S_AXI_HP0_AWPROT[2:0],S_AXI_HP0_ARADDR[31:0],S_AXI_HP0_AWADDR[31:0],S_AXI_HP0_ARCACHE[3:0],S_AXI_HP0_ARLEN[3:0],S_AXI_HP0_ARQOS[3:0],S_AXI_HP0_AWCACHE[3:0],S_AXI_HP0_AWLEN[3:0],S_AXI_HP0_AWQOS[3:0],S_AXI_HP0_ARID[5:0],S_AXI_HP0_AWID[5:0],S_AXI_HP0_WID[5:0],S_AXI_HP0_WDATA[63:0],S_AXI_HP0_WSTRB[7:0],IRQ_F2P[1:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB"; attribute X_CORE_INFO : string; attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2017.4"; begin diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/ps7_init.c b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/ps7_init.c index 1464a72c78182d435d8840e6842c1d36a5a1897c..1ef86a3b326467098279787f6d0da24b895e0152 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/ps7_init.c +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/ps7_init.c @@ -345,12 +345,12 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. ==> MASK : 0x00003F00U VAL : 0x00001400U // .. EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF8000158[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF8000158[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000158[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U // .. SRCSEL = 0x0 // .. ==> 0XF8000158[5:4] = 0x00000000U // .. ==> MASK : 0x00000030U VAL : 0x00000000U @@ -358,7 +358,7 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. ==> 0XF8000158[13:8] = 0x00000032U // .. ==> MASK : 0x00003F00U VAL : 0x00003200U // .. - EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003201U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003202U), // .. .. START: TRACE CLOCK // .. .. FINISH: TRACE CLOCK // .. .. CLKACT = 0x1 @@ -409,12 +409,12 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. .. SDI1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. SPI0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. SPI1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U // .. .. CAN0_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[16:16] = 0x00000000U // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U @@ -443,7 +443,7 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. .. ==> 0XF800012C[24:24] = 0x00000001U // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U // .. .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC444DU), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC844DU), // .. FINISH: CLOCK CONTROL SLCR REGISTERS // .. START: THIS SHOULD BE BLANK // .. FINISH: THIS SHOULD BE BLANK @@ -4463,12 +4463,12 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. ==> MASK : 0x00003F00U VAL : 0x00001400U // .. EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF8000158[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF8000158[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000158[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U // .. SRCSEL = 0x0 // .. ==> 0XF8000158[5:4] = 0x00000000U // .. ==> MASK : 0x00000030U VAL : 0x00000000U @@ -4476,7 +4476,7 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. ==> 0XF8000158[13:8] = 0x00000032U // .. ==> MASK : 0x00003F00U VAL : 0x00003200U // .. - EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003201U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003202U), // .. .. START: TRACE CLOCK // .. .. FINISH: TRACE CLOCK // .. .. CLKACT = 0x1 @@ -4527,12 +4527,12 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. .. SDI1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. SPI0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. SPI1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U // .. .. CAN0_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[16:16] = 0x00000000U // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U @@ -4561,7 +4561,7 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. .. ==> 0XF800012C[24:24] = 0x00000001U // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U // .. .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC444DU), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC844DU), // .. FINISH: CLOCK CONTROL SLCR REGISTERS // .. START: THIS SHOULD BE BLANK // .. FINISH: THIS SHOULD BE BLANK @@ -8734,12 +8734,12 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. ==> MASK : 0x00003F00U VAL : 0x00001400U // .. EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF8000158[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF8000158[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000158[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U // .. SRCSEL = 0x0 // .. ==> 0XF8000158[5:4] = 0x00000000U // .. ==> MASK : 0x00000030U VAL : 0x00000000U @@ -8747,7 +8747,7 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. ==> 0XF8000158[13:8] = 0x00000032U // .. ==> MASK : 0x00003F00U VAL : 0x00003200U // .. - EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003201U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003202U), // .. .. START: TRACE CLOCK // .. .. FINISH: TRACE CLOCK // .. .. CLKACT = 0x1 @@ -8798,12 +8798,12 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. .. SDI1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. SPI0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. SPI1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U // .. .. CAN0_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[16:16] = 0x00000000U // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U @@ -8832,7 +8832,7 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. .. ==> 0XF800012C[24:24] = 0x00000001U // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U // .. .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC444DU), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC844DU), // .. FINISH: CLOCK CONTROL SLCR REGISTERS // .. START: THIS SHOULD BE BLANK // .. FINISH: THIS SHOULD BE BLANK diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/ps7_init.html b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/ps7_init.html index fcd61f6a602f19ff555cd006d822d28ca0216404..c10a36353f4d5879976f5fc9f8523fb05a27cdb2 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/ps7_init.html +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/ps7_init.html @@ -6907,10 +6907,10 @@ SLCR_LOCK 1 -1 +0 -1 +0 SPI 0 reference clock active: 0: Clock is disabled 1: Clock is enabled @@ -6927,10 +6927,10 @@ SLCR_LOCK 2 -0 +1 -0 +2 SPI 1 reference clock active: 0: Clock is disabled 1: Clock is enabled @@ -6990,7 +6990,7 @@ SLCR_LOCK -3201 +3202 SPI Ref Clock Control @@ -7616,10 +7616,10 @@ SLCR_LOCK 4000 -1 +0 -4000 +0 SPI 0 AMBA Clock control 0: disable, 1: enable @@ -7636,10 +7636,10 @@ SLCR_LOCK 8000 -0 +1 -0 +8000 SPI 1 AMBA Clock control 0: disable, 1: enable @@ -7839,7 +7839,7 @@ SLCR_LOCK -1ec444d +1ec844d AMBA Peripheral Clock Control @@ -52448,10 +52448,10 @@ SLCR_LOCK 1 -1 +0 -1 +0 SPI 0 reference clock active: 0: Clock is disabled 1: Clock is enabled @@ -52468,10 +52468,10 @@ SLCR_LOCK 2 -0 +1 -0 +2 SPI 1 reference clock active: 0: Clock is disabled 1: Clock is enabled @@ -52531,7 +52531,7 @@ SLCR_LOCK -3201 +3202 SPI Ref Clock Control @@ -53157,10 +53157,10 @@ SLCR_LOCK 4000 -1 +0 -4000 +0 SPI 0 AMBA Clock control 0: disable, 1: enable @@ -53177,10 +53177,10 @@ SLCR_LOCK 8000 -0 +1 -0 +8000 SPI 1 AMBA Clock control 0: disable, 1: enable @@ -53380,7 +53380,7 @@ SLCR_LOCK -1ec444d +1ec844d AMBA Peripheral Clock Control @@ -99117,10 +99117,10 @@ SLCR_LOCK 1 -1 +0 -1 +0 SPI 0 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. @@ -99137,10 +99137,10 @@ SLCR_LOCK 2 -0 +1 -0 +2 SPI 1 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. @@ -99200,7 +99200,7 @@ SLCR_LOCK -3201 +3202 SPI Reference Clock Control @@ -99826,10 +99826,10 @@ SLCR_LOCK 4000 -1 +0 -4000 +0 SPI 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. @@ -99846,10 +99846,10 @@ SLCR_LOCK 8000 -0 +1 -0 +8000 SPI 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. @@ -100049,7 +100049,7 @@ SLCR_LOCK -1ec444d +1ec844d AMBA Peripheral Clock Control diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/ps7_init.tcl b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/ps7_init.tcl index 8cf2f177b0ee0f2c3d80c64910d9a3032198281a..24291b4fe2ecfca5e4f47e6f90fa87c07695b715 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/ps7_init.tcl +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/ps7_init.tcl @@ -33,11 +33,11 @@ proc ps7_clock_init_data_3_0 {} { mask_write 0XF800014C 0x00003F31 0x00000501 mask_write 0XF8000150 0x00003F33 0x00002801 mask_write 0XF8000154 0x00003F33 0x00001402 - mask_write 0XF8000158 0x00003F33 0x00003201 + mask_write 0XF8000158 0x00003F33 0x00003202 mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000170 0x03F03F30 0x00200500 mask_write 0XF80001C4 0x00000001 0x00000001 - mask_write 0XF800012C 0x01FFCCCD 0x01EC444D + mask_write 0XF800012C 0x01FFCCCD 0x01EC844D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_3_0 {} { @@ -269,11 +269,11 @@ proc ps7_clock_init_data_2_0 {} { mask_write 0XF800014C 0x00003F31 0x00000501 mask_write 0XF8000150 0x00003F33 0x00002801 mask_write 0XF8000154 0x00003F33 0x00001402 - mask_write 0XF8000158 0x00003F33 0x00003201 + mask_write 0XF8000158 0x00003F33 0x00003202 mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000170 0x03F03F30 0x00200500 mask_write 0XF80001C4 0x00000001 0x00000001 - mask_write 0XF800012C 0x01FFCCCD 0x01EC444D + mask_write 0XF800012C 0x01FFCCCD 0x01EC844D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_2_0 {} { @@ -506,11 +506,11 @@ proc ps7_clock_init_data_1_0 {} { mask_write 0XF800014C 0x00003F31 0x00000501 mask_write 0XF8000150 0x00003F33 0x00002801 mask_write 0XF8000154 0x00003F33 0x00001402 - mask_write 0XF8000158 0x00003F33 0x00003201 + mask_write 0XF8000158 0x00003F33 0x00003202 mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000170 0x03F03F30 0x00200500 mask_write 0XF80001C4 0x00000001 0x00000001 - mask_write 0XF800012C 0x01FFCCCD 0x01EC444D + mask_write 0XF800012C 0x01FFCCCD 0x01EC844D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_1_0 {} { diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/ps7_init_gpl.c b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/ps7_init_gpl.c index bbf216942eb969339c81546949727a55bfc2789a..1db7d3041ef92a17785c88a6d558975a9b47bd17 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/ps7_init_gpl.c +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/ps7_init_gpl.c @@ -336,12 +336,12 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. ==> MASK : 0x00003F00U VAL : 0x00001400U // .. EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF8000158[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF8000158[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000158[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U // .. SRCSEL = 0x0 // .. ==> 0XF8000158[5:4] = 0x00000000U // .. ==> MASK : 0x00000030U VAL : 0x00000000U @@ -349,7 +349,7 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. ==> 0XF8000158[13:8] = 0x00000032U // .. ==> MASK : 0x00003F00U VAL : 0x00003200U // .. - EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003201U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003202U), // .. .. START: TRACE CLOCK // .. .. FINISH: TRACE CLOCK // .. .. CLKACT = 0x1 @@ -400,12 +400,12 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. .. SDI1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. SPI0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. SPI1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U // .. .. CAN0_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[16:16] = 0x00000000U // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U @@ -434,7 +434,7 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. .. ==> 0XF800012C[24:24] = 0x00000001U // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U // .. .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC444DU), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC844DU), // .. FINISH: CLOCK CONTROL SLCR REGISTERS // .. START: THIS SHOULD BE BLANK // .. FINISH: THIS SHOULD BE BLANK @@ -4454,12 +4454,12 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. ==> MASK : 0x00003F00U VAL : 0x00001400U // .. EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF8000158[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF8000158[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000158[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U // .. SRCSEL = 0x0 // .. ==> 0XF8000158[5:4] = 0x00000000U // .. ==> MASK : 0x00000030U VAL : 0x00000000U @@ -4467,7 +4467,7 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. ==> 0XF8000158[13:8] = 0x00000032U // .. ==> MASK : 0x00003F00U VAL : 0x00003200U // .. - EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003201U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003202U), // .. .. START: TRACE CLOCK // .. .. FINISH: TRACE CLOCK // .. .. CLKACT = 0x1 @@ -4518,12 +4518,12 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. .. SDI1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. SPI0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. SPI1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U // .. .. CAN0_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[16:16] = 0x00000000U // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U @@ -4552,7 +4552,7 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. .. ==> 0XF800012C[24:24] = 0x00000001U // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U // .. .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC444DU), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC844DU), // .. FINISH: CLOCK CONTROL SLCR REGISTERS // .. START: THIS SHOULD BE BLANK // .. FINISH: THIS SHOULD BE BLANK @@ -8725,12 +8725,12 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. ==> MASK : 0x00003F00U VAL : 0x00001400U // .. EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF8000158[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF8000158[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000158[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U // .. SRCSEL = 0x0 // .. ==> 0XF8000158[5:4] = 0x00000000U // .. ==> MASK : 0x00000030U VAL : 0x00000000U @@ -8738,7 +8738,7 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. ==> 0XF8000158[13:8] = 0x00000032U // .. ==> MASK : 0x00003F00U VAL : 0x00003200U // .. - EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003201U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003202U), // .. .. START: TRACE CLOCK // .. .. FINISH: TRACE CLOCK // .. .. CLKACT = 0x1 @@ -8789,12 +8789,12 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. .. SDI1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. SPI0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. SPI1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U // .. .. CAN0_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[16:16] = 0x00000000U // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U @@ -8823,7 +8823,7 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. .. ==> 0XF800012C[24:24] = 0x00000001U // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U // .. .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC444DU), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC844DU), // .. FINISH: CLOCK CONTROL SLCR REGISTERS // .. START: THIS SHOULD BE BLANK // .. FINISH: THIS SHOULD BE BLANK diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/ps7_parameters.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/ps7_parameters.xml index 8cdc451a550b73a875629491746ea09d241ccd5a..838c0c3c09651dfbeae3189a2b90ab8d137cd944 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/ps7_parameters.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/ps7_parameters.xml @@ -446,22 +446,22 @@ - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/sim/mz_petalinux_processing_system7_0_0.sv b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/sim/mz_petalinux_processing_system7_0_0.sv index be293ad6f04854835338729c9dc9ebea44530cf4..5d04511d8934ee779fc7548051128d205a09782b 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/sim/mz_petalinux_processing_system7_0_0.sv +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/sim/mz_petalinux_processing_system7_0_0.sv @@ -683,20 +683,20 @@ I2C0_SCL_I, I2C0_SCL_O, I2C0_SCL_T, - SPI0_SCLK_I, - SPI0_SCLK_O, - SPI0_SCLK_T, - SPI0_MOSI_I, - SPI0_MOSI_O, - SPI0_MOSI_T, - SPI0_MISO_I, - SPI0_MISO_O, - SPI0_MISO_T, - SPI0_SS_I, - SPI0_SS_O, - SPI0_SS1_O, - SPI0_SS2_O, - SPI0_SS_T, + SPI1_SCLK_I, + SPI1_SCLK_O, + SPI1_SCLK_T, + SPI1_MOSI_I, + SPI1_MOSI_O, + SPI1_MOSI_T, + SPI1_MISO_I, + SPI1_MISO_O, + SPI1_MISO_T, + SPI1_SS_I, + SPI1_SS_O, + SPI1_SS1_O, + SPI1_SS2_O, + SPI1_SS_T, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, @@ -880,20 +880,20 @@ input I2C0_SCL_I; output I2C0_SCL_O; output I2C0_SCL_T; - input SPI0_SCLK_I; - output SPI0_SCLK_O; - output SPI0_SCLK_T; - input SPI0_MOSI_I; - output SPI0_MOSI_O; - output SPI0_MOSI_T; - input SPI0_MISO_I; - output SPI0_MISO_O; - output SPI0_MISO_T; - input SPI0_SS_I; - output SPI0_SS_O; - output SPI0_SS1_O; - output SPI0_SS2_O; - output SPI0_SS_T; + input SPI1_SCLK_I; + output SPI1_SCLK_O; + output SPI1_SCLK_T; + input SPI1_MOSI_I; + output SPI1_MOSI_O; + output SPI1_MOSI_T; + input SPI1_MISO_I; + output SPI1_MISO_O; + output SPI1_MISO_T; + input SPI1_SS_I; + output SPI1_SS_O; + output SPI1_SS1_O; + output SPI1_SS2_O; + output SPI1_SS_T; output TTC0_WAVE0_OUT; output TTC0_WAVE1_OUT; output TTC0_WAVE2_OUT; @@ -1015,16 +1015,16 @@ reg I2C0_SDA_T; reg I2C0_SCL_O; reg I2C0_SCL_T; - reg SPI0_SCLK_O; - reg SPI0_SCLK_T; - reg SPI0_MOSI_O; - reg SPI0_MOSI_T; - reg SPI0_MISO_O; - reg SPI0_MISO_T; - reg SPI0_SS_O; - reg SPI0_SS1_O; - reg SPI0_SS2_O; - reg SPI0_SS_T; + reg SPI1_SCLK_O; + reg SPI1_SCLK_T; + reg SPI1_MOSI_O; + reg SPI1_MOSI_T; + reg SPI1_MISO_O; + reg SPI1_MISO_T; + reg SPI1_SS_O; + reg SPI1_SS1_O; + reg SPI1_SS2_O; + reg SPI1_SS_T; reg TTC0_WAVE0_OUT; reg TTC0_WAVE1_OUT; reg TTC0_WAVE2_OUT; diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/sim/mz_petalinux_processing_system7_0_0.v b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/sim/mz_petalinux_processing_system7_0_0.v index 1f1bc526161d1083c0fbe07bbcca210e77339070..e20169695226cb4fe03f76fd59b43ed3d4d6518e 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/sim/mz_petalinux_processing_system7_0_0.v +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/sim/mz_petalinux_processing_system7_0_0.v @@ -62,20 +62,20 @@ I2C0_SDA_T, I2C0_SCL_I, I2C0_SCL_O, I2C0_SCL_T, -SPI0_SCLK_I, -SPI0_SCLK_O, -SPI0_SCLK_T, -SPI0_MOSI_I, -SPI0_MOSI_O, -SPI0_MOSI_T, -SPI0_MISO_I, -SPI0_MISO_O, -SPI0_MISO_T, -SPI0_SS_I, -SPI0_SS_O, -SPI0_SS1_O, -SPI0_SS2_O, -SPI0_SS_T, +SPI1_SCLK_I, +SPI1_SCLK_O, +SPI1_SCLK_T, +SPI1_MOSI_I, +SPI1_MOSI_O, +SPI1_MOSI_T, +SPI1_MISO_I, +SPI1_MISO_O, +SPI1_MISO_T, +SPI1_SS_I, +SPI1_SS_O, +SPI1_SS1_O, +SPI1_SS2_O, +SPI1_SS_T, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, @@ -197,20 +197,20 @@ output I2C0_SDA_T; input I2C0_SCL_I; output I2C0_SCL_O; output I2C0_SCL_T; -input SPI0_SCLK_I; -output SPI0_SCLK_O; -output SPI0_SCLK_T; -input SPI0_MOSI_I; -output SPI0_MOSI_O; -output SPI0_MOSI_T; -input SPI0_MISO_I; -output SPI0_MISO_O; -output SPI0_MISO_T; -input SPI0_SS_I; -output SPI0_SS_O; -output SPI0_SS1_O; -output SPI0_SS2_O; -output SPI0_SS_T; +input SPI1_SCLK_I; +output SPI1_SCLK_O; +output SPI1_SCLK_T; +input SPI1_MOSI_I; +output SPI1_MOSI_O; +output SPI1_MOSI_T; +input SPI1_MISO_I; +output SPI1_MISO_O; +output SPI1_MISO_T; +input SPI1_SS_I; +output SPI1_SS_O; +output SPI1_SS1_O; +output SPI1_SS2_O; +output SPI1_SS_T; output TTC0_WAVE0_OUT; output TTC0_WAVE1_OUT; output TTC0_WAVE2_OUT; diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/synth/mz_petalinux_processing_system7_0_0.v b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/synth/mz_petalinux_processing_system7_0_0.v index 6f2d8289b5bf8f545e7b7673d4bc6d6626c97b2c..7da8beea8ebe2b95902eea4f97f8099967cbf97a 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/synth/mz_petalinux_processing_system7_0_0.v +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_processing_system7_0_0/synth/mz_petalinux_processing_system7_0_0.v @@ -64,20 +64,20 @@ module mz_petalinux_processing_system7_0_0 ( I2C0_SCL_I, I2C0_SCL_O, I2C0_SCL_T, - SPI0_SCLK_I, - SPI0_SCLK_O, - SPI0_SCLK_T, - SPI0_MOSI_I, - SPI0_MOSI_O, - SPI0_MOSI_T, - SPI0_MISO_I, - SPI0_MISO_O, - SPI0_MISO_T, - SPI0_SS_I, - SPI0_SS_O, - SPI0_SS1_O, - SPI0_SS2_O, - SPI0_SS_T, + SPI1_SCLK_I, + SPI1_SCLK_O, + SPI1_SCLK_T, + SPI1_MOSI_I, + SPI1_MOSI_O, + SPI1_MOSI_T, + SPI1_MISO_I, + SPI1_MISO_O, + SPI1_MISO_T, + SPI1_SS_I, + SPI1_SS_O, + SPI1_SS1_O, + SPI1_SS2_O, + SPI1_SS_T, TTC0_WAVE0_OUT, TTC0_WAVE1_OUT, TTC0_WAVE2_OUT, @@ -206,34 +206,34 @@ input wire I2C0_SCL_I; output wire I2C0_SCL_O; (* X_INTERFACE_INFO = "xilinx.com:interface:iic:1.0 IIC_0 SCL_T" *) output wire I2C0_SCL_T; -(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SCK_I" *) -input wire SPI0_SCLK_I; -(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SCK_O" *) -output wire SPI0_SCLK_O; -(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SCK_T" *) -output wire SPI0_SCLK_T; -(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 IO0_I" *) -input wire SPI0_MOSI_I; -(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 IO0_O" *) -output wire SPI0_MOSI_O; -(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 IO0_T" *) -output wire SPI0_MOSI_T; -(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 IO1_I" *) -input wire SPI0_MISO_I; -(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 IO1_O" *) -output wire SPI0_MISO_O; -(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 IO1_T" *) -output wire SPI0_MISO_T; -(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SS_I" *) -input wire SPI0_SS_I; -(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SS_O" *) -output wire SPI0_SS_O; -(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SS1_O" *) -output wire SPI0_SS1_O; -(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SS2_O" *) -output wire SPI0_SS2_O; -(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_0 SS_T" *) -output wire SPI0_SS_T; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SCK_I" *) +input wire SPI1_SCLK_I; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SCK_O" *) +output wire SPI1_SCLK_O; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SCK_T" *) +output wire SPI1_SCLK_T; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO0_I" *) +input wire SPI1_MOSI_I; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO0_O" *) +output wire SPI1_MOSI_O; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO0_T" *) +output wire SPI1_MOSI_T; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO1_I" *) +input wire SPI1_MISO_I; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO1_O" *) +output wire SPI1_MISO_O; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 IO1_T" *) +output wire SPI1_MISO_T; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS_I" *) +input wire SPI1_SS_I; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS_O" *) +output wire SPI1_SS_O; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS1_O" *) +output wire SPI1_SS1_O; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS2_O" *) +output wire SPI1_SS2_O; +(* X_INTERFACE_INFO = "xilinx.com:interface:spi:1.0 SPI_1 SS_T" *) +output wire SPI1_SS_T; output wire TTC0_WAVE0_OUT; output wire TTC0_WAVE1_OUT; output wire TTC0_WAVE2_OUT; @@ -415,7 +415,7 @@ input wire [63 : 0] S_AXI_HP0_WDATA; (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI_HP0, NUM_WRITE_OUTSTANDING 8, NUM_READ_OUTSTANDING 8, DATA_WIDTH 64, PROTOCOL AXI3, FREQ_HZ 99999999, ID_WIDTH 6, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, MAX_BURST_LENGTH 8, PHASE 0.000, CLK_DOMAIN mz_petalinux_processing_system7_0_0_FCLK_CLK0, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) (* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI_HP0 WSTRB" *) input wire [7 : 0] S_AXI_HP0_WSTRB; -(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH:LEVEL_HIGH, PortWidth 2" *) +(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME IRQ_F2P, SENSITIVITY LEVEL_HIGH:NULL, PortWidth 2" *) (* X_INTERFACE_INFO = "xilinx.com:signal:interrupt:1.0 IRQ_F2P INTERRUPT" *) input wire [1 : 0] IRQ_F2P; (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME FCLK_CLK0, FREQ_HZ 99999999, PHASE 0.000, CLK_DOMAIN mz_petalinux_processing_system7_0_0_FCLK_CLK0" *) @@ -626,34 +626,34 @@ inout wire PS_PORB; .SDIO1_WP(1'B0), .SDIO1_BUSPOW(), .SDIO1_BUSVOLT(), - .SPI0_SCLK_I(SPI0_SCLK_I), - .SPI0_SCLK_O(SPI0_SCLK_O), - .SPI0_SCLK_T(SPI0_SCLK_T), - .SPI0_MOSI_I(SPI0_MOSI_I), - .SPI0_MOSI_O(SPI0_MOSI_O), - .SPI0_MOSI_T(SPI0_MOSI_T), - .SPI0_MISO_I(SPI0_MISO_I), - .SPI0_MISO_O(SPI0_MISO_O), - .SPI0_MISO_T(SPI0_MISO_T), - .SPI0_SS_I(SPI0_SS_I), - .SPI0_SS_O(SPI0_SS_O), - .SPI0_SS1_O(SPI0_SS1_O), - .SPI0_SS2_O(SPI0_SS2_O), - .SPI0_SS_T(SPI0_SS_T), - .SPI1_SCLK_I(1'B0), - .SPI1_SCLK_O(), - .SPI1_SCLK_T(), - .SPI1_MOSI_I(1'B0), - .SPI1_MOSI_O(), - .SPI1_MOSI_T(), - .SPI1_MISO_I(1'B0), - .SPI1_MISO_O(), - .SPI1_MISO_T(), - .SPI1_SS_I(1'B0), - .SPI1_SS_O(), - .SPI1_SS1_O(), - .SPI1_SS2_O(), - .SPI1_SS_T(), + .SPI0_SCLK_I(1'B0), + .SPI0_SCLK_O(), + .SPI0_SCLK_T(), + .SPI0_MOSI_I(1'B0), + .SPI0_MOSI_O(), + .SPI0_MOSI_T(), + .SPI0_MISO_I(1'B0), + .SPI0_MISO_O(), + .SPI0_MISO_T(), + .SPI0_SS_I(1'B0), + .SPI0_SS_O(), + .SPI0_SS1_O(), + .SPI0_SS2_O(), + .SPI0_SS_T(), + .SPI1_SCLK_I(SPI1_SCLK_I), + .SPI1_SCLK_O(SPI1_SCLK_O), + .SPI1_SCLK_T(SPI1_SCLK_T), + .SPI1_MOSI_I(SPI1_MOSI_I), + .SPI1_MOSI_O(SPI1_MOSI_O), + .SPI1_MOSI_T(SPI1_MOSI_T), + .SPI1_MISO_I(SPI1_MISO_I), + .SPI1_MISO_O(SPI1_MISO_O), + .SPI1_MISO_T(SPI1_MISO_T), + .SPI1_SS_I(SPI1_SS_I), + .SPI1_SS_O(SPI1_SS_O), + .SPI1_SS1_O(SPI1_SS1_O), + .SPI1_SS2_O(SPI1_SS2_O), + .SPI1_SS_T(SPI1_SS_T), .UART0_DTRN(), .UART0_RTSN(), .UART0_TX(), diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0.dcp b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0.dcp index c213d3c303ecbb823b3b5959176435a8ab7653d0..6bcb731f02b318d4112e5c698eddefda8e2b5f28 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0.dcp and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0.dcp differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0.xci b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0.xci index 9c5899ada936905cc5b8dd4c3a908b656012e93a..eb033f67e27e1153e5aaf081a82ca41de03bc67a 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0.xci +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0.xci @@ -34,6 +34,13 @@ 2017.4 OUT_OF_CONTEXT + + + + + + + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0.xml index 64c3086a04f2a9e03bbefb4c035460c286e17f97..673b9135745ea8439696970abbb78d17539fe9bc 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0.xml @@ -36,7 +36,7 @@ GENtimestamp - Fri Jul 12 12:20:04 UTC 2019 + Sun Oct 20 13:59:08 UTC 2019 outputProductCRC @@ -74,7 +74,7 @@ GENtimestamp - Fri Jul 12 12:20:04 UTC 2019 + Sun Oct 20 13:59:08 UTC 2019 outputProductCRC @@ -92,7 +92,7 @@ GENtimestamp - Fri Jul 12 12:21:57 UTC 2019 + Sun Oct 20 13:59:59 UTC 2019 outputProductCRC @@ -225,6 +225,9 @@ Constant 3 + + + 2017.4 diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0_sim_netlist.v b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0_sim_netlist.v index 5a8b18da46bdc094e6c249516c591ea3883faa7b..2ae50d819f51489295909f3e18f4d67589b77b65 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0_sim_netlist.v +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0_sim_netlist.v @@ -1,8 +1,8 @@ // Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 -// Date : Fri Jul 12 14:21:57 2019 -// Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.2 LTS +// Date : Sun Oct 20 15:59:59 2019 +// Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS // Command : write_verilog -force -mode funcsim // /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0_sim_netlist.v // Design : mz_petalinux_xlconstant_0_0 diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0_sim_netlist.vhdl b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0_sim_netlist.vhdl index 5314d1a9a7c7a7e181da3da11864cc3edd88aeab..384293cfe0b6dee5ca15e8877aee52d8477808cf 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0_sim_netlist.vhdl +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0_sim_netlist.vhdl @@ -1,8 +1,8 @@ -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 --- Date : Fri Jul 12 14:21:57 2019 --- Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.2 LTS +-- Date : Sun Oct 20 15:59:59 2019 +-- Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS -- Command : write_vhdl -force -mode funcsim -- /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0_sim_netlist.vhdl -- Design : mz_petalinux_xlconstant_0_0 diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0_stub.v b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0_stub.v index d072213b5d90b675072c2fa769b40f991c40dd7d..9ff91d5d95b607f69159d1a4487a1961a4ca6366 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0_stub.v +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0_stub.v @@ -1,8 +1,8 @@ // Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. // -------------------------------------------------------------------------------- // Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 -// Date : Fri Jul 12 14:21:57 2019 -// Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.2 LTS +// Date : Sun Oct 20 15:59:59 2019 +// Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS // Command : write_verilog -force -mode synth_stub // /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0_stub.v // Design : mz_petalinux_xlconstant_0_0 diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0_stub.vhdl b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0_stub.vhdl index c60155b8f7bc7285dcf2be619d68a81cc9d7859d..57e4f772385ac59c1ad44439df862dab2577a5d9 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0_stub.vhdl +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0_stub.vhdl @@ -1,8 +1,8 @@ -- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. -- -------------------------------------------------------------------------------- -- Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 --- Date : Fri Jul 12 14:21:57 2019 --- Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.2 LTS +-- Date : Sun Oct 20 15:59:59 2019 +-- Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS -- Command : write_vhdl -force -mode synth_stub -- /home/nats/project/VNAV2_Zynq/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ip/mz_petalinux_xlconstant_0_0/mz_petalinux_xlconstant_0_0_stub.vhdl -- Design : mz_petalinux_xlconstant_0_0 diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/mz_petalinux.bd b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/mz_petalinux.bd index 721baf5f373328c1548b8e231810bb301f76c2dd..6ae6a9d36d22284d5256b705e216d3af97b11a27 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/mz_petalinux.bd +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/mz_petalinux.bd @@ -180,18 +180,6 @@ in - - SPI0_CS_ADC1 - - out - - - - SPI0_CS_ADC2 - - out - - AD_FR_P_0 @@ -312,6 +300,18 @@ in + + SPI0_CS_ADC1 + + out + + + + SPI0_CS_ADC2 + + out + + @@ -431,7 +431,8 @@ 1 1 1 - 1 + 0 + 1 1 1 0 @@ -443,7 +444,8 @@ 1 1 1 - 1 + 0 + 1 1 1 1 @@ -496,8 +498,9 @@ 1 MIO 48 .. 49 0 - 1 - EMIO + 0 + 1 + EMIO 1 EMIO 1 @@ -735,6 +738,7 @@ mz_petalinux_xlconstant_0_0 + 1 @@ -788,12 +792,12 @@ + - processing_system7_0_FCLK_RESET0_N @@ -805,11 +809,11 @@ + - rst_ps7_0_100M_interconnect_aresetn @@ -826,36 +830,6 @@ - - processing_system7_0_SPI0_SCLK_O - - - - - processing_system7_0_SPI0_MOSI_O - - - - - SPI0_MISO_I_0_1 - - - - - processing_system7_0_SPI0_SS_O - - - - - processing_system7_0_SPI0_SS1_O - - - - - xlconstant_0_dout - - - AD_FR_P_0_1 @@ -956,6 +930,36 @@ + + processing_system7_0_SPI1_SCLK_O + + + + + processing_system7_0_SPI1_MOSI_O + + + + + processing_system7_0_SPI1_SS_O + + + + + processing_system7_0_SPI1_SS1_O + + + + + SPI0_MISO_0_1 + + + + + xlconstant_0_dout + + + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/mz_petalinux.bxml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/mz_petalinux.bxml index f9e4122ad72fded703f4b2be29c427b564906b64..a2507785376a2e0963e96fc4b938690a97e458de 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/mz_petalinux.bxml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/mz_petalinux.bxml @@ -2,10 +2,10 @@ Composite Fileset - - - - + + + + diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/sim/mz_petalinux.v b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/sim/mz_petalinux.v index e208933bd6d296c228c2c3edd5719fd91a769673..5b382be4cfe26e883c02efa3535acfdda36227b6 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/sim/mz_petalinux.v +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/sim/mz_petalinux.v @@ -1,7 +1,7 @@ //Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. //-------------------------------------------------------------------------------- //Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 -//Date : Fri Oct 18 01:16:08 2019 +//Date : Sun Oct 20 22:42:44 2019 //Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS //Command : generate_target mz_petalinux.bd //Design : mz_petalinux @@ -557,7 +557,7 @@ module mz_petalinux wire LTC2271_SampleGetter_0_M00_AXIS_TLAST; wire LTC2271_SampleGetter_0_M00_AXIS_TREADY; wire LTC2271_SampleGetter_0_M00_AXIS_TVALID; - wire SPI0_MISO_I_0_1; + wire SPI0_MISO_0_1; wire [31:0]axi_dma_0_M_AXI_S2MM_AWADDR; wire [1:0]axi_dma_0_M_AXI_S2MM_AWBURST; wire [3:0]axi_dma_0_M_AXI_S2MM_AWCACHE; @@ -704,10 +704,10 @@ module mz_petalinux wire processing_system7_0_M_AXI_GP0_WREADY; wire [3:0]processing_system7_0_M_AXI_GP0_WSTRB; wire processing_system7_0_M_AXI_GP0_WVALID; - wire processing_system7_0_SPI0_MOSI_O; - wire processing_system7_0_SPI0_SCLK_O; - wire processing_system7_0_SPI0_SS1_O; - wire processing_system7_0_SPI0_SS_O; + wire processing_system7_0_SPI1_MOSI_O; + wire processing_system7_0_SPI1_SCLK_O; + wire processing_system7_0_SPI1_SS1_O; + wire processing_system7_0_SPI1_SS_O; wire [31:0]ps7_0_axi_periph_M00_AXI_ARADDR; wire ps7_0_axi_periph_M00_AXI_ARREADY; wire [0:0]ps7_0_axi_periph_M00_AXI_ARVALID; @@ -753,11 +753,11 @@ module mz_petalinux assign IIC_0_scl_t = processing_system7_0_IIC_0_SCL_T; assign IIC_0_sda_o = processing_system7_0_IIC_0_SDA_O; assign IIC_0_sda_t = processing_system7_0_IIC_0_SDA_T; - assign SPI0_CS_ADC1 = processing_system7_0_SPI0_SS_O; - assign SPI0_CS_ADC2 = processing_system7_0_SPI0_SS1_O; - assign SPI0_MISO_I_0_1 = SPI0_MISO_0; - assign SPI0_MOSI_0 = processing_system7_0_SPI0_MOSI_O; - assign SPI0_SCLK_0 = processing_system7_0_SPI0_SCLK_O; + assign SPI0_CS_ADC1 = processing_system7_0_SPI1_SS_O; + assign SPI0_CS_ADC2 = processing_system7_0_SPI1_SS1_O; + assign SPI0_MISO_0_1 = SPI0_MISO_0; + assign SPI0_MOSI_0 = processing_system7_0_SPI1_MOSI_O; + assign SPI0_SCLK_0 = processing_system7_0_SPI1_SCLK_O; assign processing_system7_0_IIC_0_SCL_I = IIC_0_scl_i; assign processing_system7_0_IIC_0_SDA_I = IIC_0_sda_i; mz_petalinux_LTC2271_SampleGetter_0_0 LTC2271_SampleGetter_0 @@ -1026,14 +1026,14 @@ module mz_petalinux .PS_CLK(FIXED_IO_ps_clk), .PS_PORB(FIXED_IO_ps_porb), .PS_SRSTB(FIXED_IO_ps_srstb), - .SPI0_MISO_I(SPI0_MISO_I_0_1), - .SPI0_MOSI_I(1'b0), - .SPI0_MOSI_O(processing_system7_0_SPI0_MOSI_O), - .SPI0_SCLK_I(1'b0), - .SPI0_SCLK_O(processing_system7_0_SPI0_SCLK_O), - .SPI0_SS1_O(processing_system7_0_SPI0_SS1_O), - .SPI0_SS_I(xlconstant_0_dout), - .SPI0_SS_O(processing_system7_0_SPI0_SS_O), + .SPI1_MISO_I(SPI0_MISO_0_1), + .SPI1_MOSI_I(1'b0), + .SPI1_MOSI_O(processing_system7_0_SPI1_MOSI_O), + .SPI1_SCLK_I(1'b0), + .SPI1_SCLK_O(processing_system7_0_SPI1_SCLK_O), + .SPI1_SS1_O(processing_system7_0_SPI1_SS1_O), + .SPI1_SS_I(xlconstant_0_dout), + .SPI1_SS_O(processing_system7_0_SPI1_SS_O), .S_AXI_HP0_ACLK(processing_system7_0_FCLK_CLK0), .S_AXI_HP0_ARADDR(axi_smc_M00_AXI_ARADDR), .S_AXI_HP0_ARBURST(axi_smc_M00_AXI_ARBURST), diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/synth/mz_petalinux.hwdef b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/synth/mz_petalinux.hwdef index ca7b63f3e6ff4888d10903c54ca10c8f1df6bfa0..fb09960a783f78248a1839f19bf860ee9fffcf8a 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/synth/mz_petalinux.hwdef and b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/synth/mz_petalinux.hwdef differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/synth/mz_petalinux.v b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/synth/mz_petalinux.v index e208933bd6d296c228c2c3edd5719fd91a769673..5b382be4cfe26e883c02efa3535acfdda36227b6 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/synth/mz_petalinux.v +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/synth/mz_petalinux.v @@ -1,7 +1,7 @@ //Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. //-------------------------------------------------------------------------------- //Tool Version: Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 -//Date : Fri Oct 18 01:16:08 2019 +//Date : Sun Oct 20 22:42:44 2019 //Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS //Command : generate_target mz_petalinux.bd //Design : mz_petalinux @@ -557,7 +557,7 @@ module mz_petalinux wire LTC2271_SampleGetter_0_M00_AXIS_TLAST; wire LTC2271_SampleGetter_0_M00_AXIS_TREADY; wire LTC2271_SampleGetter_0_M00_AXIS_TVALID; - wire SPI0_MISO_I_0_1; + wire SPI0_MISO_0_1; wire [31:0]axi_dma_0_M_AXI_S2MM_AWADDR; wire [1:0]axi_dma_0_M_AXI_S2MM_AWBURST; wire [3:0]axi_dma_0_M_AXI_S2MM_AWCACHE; @@ -704,10 +704,10 @@ module mz_petalinux wire processing_system7_0_M_AXI_GP0_WREADY; wire [3:0]processing_system7_0_M_AXI_GP0_WSTRB; wire processing_system7_0_M_AXI_GP0_WVALID; - wire processing_system7_0_SPI0_MOSI_O; - wire processing_system7_0_SPI0_SCLK_O; - wire processing_system7_0_SPI0_SS1_O; - wire processing_system7_0_SPI0_SS_O; + wire processing_system7_0_SPI1_MOSI_O; + wire processing_system7_0_SPI1_SCLK_O; + wire processing_system7_0_SPI1_SS1_O; + wire processing_system7_0_SPI1_SS_O; wire [31:0]ps7_0_axi_periph_M00_AXI_ARADDR; wire ps7_0_axi_periph_M00_AXI_ARREADY; wire [0:0]ps7_0_axi_periph_M00_AXI_ARVALID; @@ -753,11 +753,11 @@ module mz_petalinux assign IIC_0_scl_t = processing_system7_0_IIC_0_SCL_T; assign IIC_0_sda_o = processing_system7_0_IIC_0_SDA_O; assign IIC_0_sda_t = processing_system7_0_IIC_0_SDA_T; - assign SPI0_CS_ADC1 = processing_system7_0_SPI0_SS_O; - assign SPI0_CS_ADC2 = processing_system7_0_SPI0_SS1_O; - assign SPI0_MISO_I_0_1 = SPI0_MISO_0; - assign SPI0_MOSI_0 = processing_system7_0_SPI0_MOSI_O; - assign SPI0_SCLK_0 = processing_system7_0_SPI0_SCLK_O; + assign SPI0_CS_ADC1 = processing_system7_0_SPI1_SS_O; + assign SPI0_CS_ADC2 = processing_system7_0_SPI1_SS1_O; + assign SPI0_MISO_0_1 = SPI0_MISO_0; + assign SPI0_MOSI_0 = processing_system7_0_SPI1_MOSI_O; + assign SPI0_SCLK_0 = processing_system7_0_SPI1_SCLK_O; assign processing_system7_0_IIC_0_SCL_I = IIC_0_scl_i; assign processing_system7_0_IIC_0_SDA_I = IIC_0_sda_i; mz_petalinux_LTC2271_SampleGetter_0_0 LTC2271_SampleGetter_0 @@ -1026,14 +1026,14 @@ module mz_petalinux .PS_CLK(FIXED_IO_ps_clk), .PS_PORB(FIXED_IO_ps_porb), .PS_SRSTB(FIXED_IO_ps_srstb), - .SPI0_MISO_I(SPI0_MISO_I_0_1), - .SPI0_MOSI_I(1'b0), - .SPI0_MOSI_O(processing_system7_0_SPI0_MOSI_O), - .SPI0_SCLK_I(1'b0), - .SPI0_SCLK_O(processing_system7_0_SPI0_SCLK_O), - .SPI0_SS1_O(processing_system7_0_SPI0_SS1_O), - .SPI0_SS_I(xlconstant_0_dout), - .SPI0_SS_O(processing_system7_0_SPI0_SS_O), + .SPI1_MISO_I(SPI0_MISO_0_1), + .SPI1_MOSI_I(1'b0), + .SPI1_MOSI_O(processing_system7_0_SPI1_MOSI_O), + .SPI1_SCLK_I(1'b0), + .SPI1_SCLK_O(processing_system7_0_SPI1_SCLK_O), + .SPI1_SS1_O(processing_system7_0_SPI1_SS1_O), + .SPI1_SS_I(xlconstant_0_dout), + .SPI1_SS_O(processing_system7_0_SPI1_SS_O), .S_AXI_HP0_ACLK(processing_system7_0_FCLK_CLK0), .S_AXI_HP0_ARADDR(axi_smc_M00_AXI_ARADDR), .S_AXI_HP0_ARBURST(axi_smc_M00_AXI_ARBURST), diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ui/bd_82e05180.ui b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ui/bd_82e05180.ui index b32ec61ebb3a070402eb63aaaf5c2398c8521d47..779d047adc34bd9575753c11dc37351e63d504d4 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ui/bd_82e05180.ui +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.srcs/sources_1/bd/mz_petalinux/ui/bd_82e05180.ui @@ -2,84 +2,84 @@ ExpandedHierarchyInLayout: "", guistr: "# # String gsaved with Nlview 6.6.11 2017-06-12 bk=1.3860 VDI=40 GEI=35 GUI=JA:1.6 # -string -flagsOSRD -preplace port AD_IN_1B_P_0 -pg 1 -y -100 -defaultsOSRD -preplace port AD_IN_2D_P_0 -pg 1 -y 140 -defaultsOSRD -preplace port AD_IN_2C_P_0 -pg 1 -y 100 -defaultsOSRD -preplace port SPI0_MISO_0 -pg 1 -y 340 -defaultsOSRD -preplace port DDR -pg 1 -y 150 -defaultsOSRD -preplace port AD_IN_1A_N_0 -pg 1 -y -120 -defaultsOSRD -preplace port AD_IN_1A_P_0 -pg 1 -y -140 -defaultsOSRD -preplace port AD_IN_2A_N_0 -pg 1 -y 40 -defaultsOSRD -preplace port AD_FR_P_0 -pg 1 -y -220 -defaultsOSRD -preplace port SPI0_CS_ADC1 -pg 1 -y 310 -defaultsOSRD -preplace port SPI0_CS_ADC2 -pg 1 -y 330 -defaultsOSRD -preplace port AD_IN_2B_P_0 -pg 1 -y 60 -defaultsOSRD -preplace port AD_IN_1D_P_0 -pg 1 -y -20 -defaultsOSRD -preplace port AD_IN_1D_N_0 -pg 1 -y 0 -defaultsOSRD -preplace port AD_IN_2B_N_0 -pg 1 -y 80 -defaultsOSRD -preplace port AD_IN_1C_N_0 -pg 1 -y -40 -defaultsOSRD -preplace port AD_IN_1B_N_0 -pg 1 -y -80 -defaultsOSRD -preplace port AD_IN_2C_N_0 -pg 1 -y 120 -defaultsOSRD -preplace port SPI0_MOSI_0 -pg 1 -y 250 -defaultsOSRD -preplace port SPI0_SCLK_0 -pg 1 -y 230 -defaultsOSRD -preplace port IIC_0 -pg 1 -y 190 -defaultsOSRD -preplace port FIXED_IO -pg 1 -y 170 -defaultsOSRD -preplace port AD_DCO_N_0 -pg 1 -y -160 -defaultsOSRD -preplace port AD_DCO_P_0 -pg 1 -y -180 -defaultsOSRD -preplace port AD_FR_N_0 -pg 1 -y -200 -defaultsOSRD -preplace port AD_IN_2D_N_0 -pg 1 -y 160 -defaultsOSRD -preplace port AD_IN_1C_P_0 -pg 1 -y -60 -defaultsOSRD -preplace port AD_IN_2A_P_0 -pg 1 -y 20 -defaultsOSRD -preplace inst axi_dma_0 -pg 1 -lvl 3 -y 320 -defaultsOSRD -preplace inst xlconstant_0 -pg 1 -lvl 5 -y 60 -defaultsOSRD -preplace inst LTC2271_SampleGetter_0 -pg 1 -lvl 2 -y -10 -defaultsOSRD -preplace inst axi_smc -pg 1 -lvl 4 -y 290 -defaultsOSRD -preplace inst xlconcat_0 -pg 1 -lvl 4 -y 440 -defaultsOSRD +preplace port AD_IN_1B_P_0 -pg 1 -y 170 -defaultsOSRD +preplace port AD_IN_2D_P_0 -pg 1 -y 410 -defaultsOSRD +preplace port AD_IN_2C_P_0 -pg 1 -y 370 -defaultsOSRD +preplace port SPI0_MISO_0 -pg 1 -y 590 -defaultsOSRD -right +preplace port DDR -pg 1 -y 470 -defaultsOSRD +preplace port AD_IN_1A_N_0 -pg 1 -y 150 -defaultsOSRD +preplace port AD_IN_1A_P_0 -pg 1 -y 130 -defaultsOSRD +preplace port SPI0_CS_ADC1 -pg 1 -y 630 -defaultsOSRD +preplace port AD_IN_2A_N_0 -pg 1 -y 310 -defaultsOSRD +preplace port AD_FR_P_0 -pg 1 -y 50 -defaultsOSRD +preplace port SPI0_CS_ADC2 -pg 1 -y 650 -defaultsOSRD +preplace port AD_IN_2B_P_0 -pg 1 -y 330 -defaultsOSRD +preplace port AD_IN_1D_P_0 -pg 1 -y 250 -defaultsOSRD +preplace port AD_IN_1D_N_0 -pg 1 -y 270 -defaultsOSRD +preplace port AD_IN_2B_N_0 -pg 1 -y 350 -defaultsOSRD +preplace port AD_IN_1C_N_0 -pg 1 -y 230 -defaultsOSRD +preplace port AD_IN_1B_N_0 -pg 1 -y 190 -defaultsOSRD +preplace port AD_IN_2C_N_0 -pg 1 -y 390 -defaultsOSRD +preplace port SPI0_MOSI_0 -pg 1 -y 570 -defaultsOSRD +preplace port SPI0_SCLK_0 -pg 1 -y 550 -defaultsOSRD +preplace port IIC_0 -pg 1 -y 510 -defaultsOSRD +preplace port FIXED_IO -pg 1 -y 490 -defaultsOSRD +preplace port AD_DCO_N_0 -pg 1 -y 110 -defaultsOSRD +preplace port AD_DCO_P_0 -pg 1 -y 90 -defaultsOSRD +preplace port AD_FR_N_0 -pg 1 -y 70 -defaultsOSRD +preplace port AD_IN_2D_N_0 -pg 1 -y 430 -defaultsOSRD +preplace port AD_IN_1C_P_0 -pg 1 -y 210 -defaultsOSRD +preplace port AD_IN_2A_P_0 -pg 1 -y 290 -defaultsOSRD +preplace inst axi_dma_0 -pg 1 -lvl 3 -y 600 -defaultsOSRD +preplace inst xlconstant_0 -pg 1 -lvl 5 -y 380 -defaultsOSRD +preplace inst LTC2271_SampleGetter_0 -pg 1 -lvl 2 -y 260 -defaultsOSRD +preplace inst axi_smc -pg 1 -lvl 4 -y 610 -defaultsOSRD +preplace inst xlconcat_0 -pg 1 -lvl 4 -y 760 -defaultsOSRD preplace inst ps7_0_axi_periph -pg 1 -lvl 2 -y 700 -defaultsOSRD -preplace inst rst_ps7_0_100M -pg 1 -lvl 1 -y 620 -defaultsOSRD -preplace inst processing_system7_0 -pg 1 -lvl 5 -y 310 -defaultsOSRD +preplace inst rst_ps7_0_100M -pg 1 -lvl 1 -y 530 -defaultsOSRD +preplace inst processing_system7_0 -pg 1 -lvl 5 -y 630 -defaultsOSRD preplace netloc processing_system7_0_DDR 1 5 1 NJ -preplace netloc AD_IN_1C_P_0_1 1 0 2 NJ -60 NJ -preplace netloc AD_IN_2B_P_0_1 1 0 2 NJ 60 NJ -preplace netloc AD_FR_P_0_1 1 0 2 NJ -220 NJ -preplace netloc AD_IN_1D_N_0_1 1 0 2 NJ 0 NJ -preplace netloc AD_IN_2A_P_0_1 1 0 2 NJ 20 NJ -preplace netloc AD_IN_2A_N_0_1 1 0 2 NJ 40 NJ -preplace netloc processing_system7_0_M_AXI_GP0 1 1 5 520 520 NJ 520 NJ 520 NJ 520 2050 -preplace netloc AD_IN_1B_P_0_1 1 0 2 NJ -100 NJ -preplace netloc AD_DCO_P_0_1 1 0 2 NJ -180 NJ -preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 1 3 500 260 840 220 1220 +preplace netloc AD_IN_1C_P_0_1 1 0 2 NJ 210 NJ +preplace netloc AD_IN_2B_P_0_1 1 0 2 NJ 330 NJ +preplace netloc AD_FR_P_0_1 1 0 2 NJ 50 NJ +preplace netloc AD_IN_1D_N_0_1 1 0 2 NJ 270 NJ +preplace netloc AD_IN_2A_P_0_1 1 0 2 NJ 290 NJ +preplace netloc AD_IN_2A_N_0_1 1 0 2 NJ 310 NJ +preplace netloc processing_system7_0_M_AXI_GP0 1 1 5 420 860 NJ 860 NJ 860 NJ 860 1900 +preplace netloc processing_system7_0_SPI1_SS_O 1 5 1 NJ +preplace netloc AD_IN_1B_P_0_1 1 0 2 NJ 170 NJ +preplace netloc AD_DCO_P_0_1 1 0 2 NJ 90 NJ +preplace netloc rst_ps7_0_100M_peripheral_aresetn 1 1 3 410 530 710 710 1130J preplace netloc axi_smc_M00_AXI 1 4 1 N -preplace netloc AD_IN_2C_P_0_1 1 0 2 NJ 100 NJ -preplace netloc AD_FR_N_0_1 1 0 2 NJ -200 NJ -preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 6 -60J 530 490J 540 800J 550 NJ 550 NJ 550 2060 +preplace netloc AD_IN_2C_P_0_1 1 0 2 NJ 370 NJ +preplace netloc AD_FR_N_0_1 1 0 2 NJ 70 NJ +preplace netloc processing_system7_0_FCLK_RESET0_N 1 0 6 20 620 390J 540 700J 720 1100J 820 1410J 850 1880 preplace netloc processing_system7_0_IIC_0 1 5 1 NJ -preplace netloc axi_dma_0_M_AXI_SG 1 3 1 1210 -preplace netloc SPI0_MISO_I_0_1 1 0 6 NJ 340 NJ 340 800J 180 NJ 180 1570J 540 2070 -preplace netloc AD_IN_1D_P_0_1 1 0 2 NJ -20 NJ -preplace netloc AD_IN_1B_N_0_1 1 0 2 NJ -80 NJ -preplace netloc AD_IN_1A_N_0_1 1 0 2 NJ -120 NJ -preplace netloc axi_dma_0_s2mm_introut 1 3 1 1230 -preplace netloc xlconstant_0_dout 1 5 1 2040 -preplace netloc processing_system7_0_SPI0_SS1_O 1 5 1 NJ -preplace netloc processing_system7_0_SPI0_MOSI_O 1 5 1 NJ -preplace netloc xlconcat_0_dout 1 4 1 1580 +preplace netloc axi_dma_0_M_AXI_SG 1 3 1 N +preplace netloc processing_system7_0_SPI1_SS1_O 1 5 1 NJ +preplace netloc processing_system7_0_SPI1_MOSI_O 1 5 1 NJ +preplace netloc AD_IN_1D_P_0_1 1 0 2 NJ 250 NJ +preplace netloc AD_IN_1B_N_0_1 1 0 2 NJ 190 NJ +preplace netloc AD_IN_1A_N_0_1 1 0 2 NJ 150 NJ +preplace netloc axi_dma_0_s2mm_introut 1 3 1 1110 +preplace netloc xlconstant_0_dout 1 5 1 1900 +preplace netloc xlconcat_0_dout 1 4 1 1410J preplace netloc processing_system7_0_FIXED_IO 1 5 1 NJ -preplace netloc LTC2271_SampleGetter_0_M00_AXIS 1 2 1 810 -preplace netloc AD_DCO_N_0_1 1 0 2 NJ -160 NJ -preplace netloc AD_IN_1A_P_0_1 1 0 2 NJ -140 NJ -preplace netloc axi_dma_0_M_AXI_S2MM 1 3 1 1230 -preplace netloc AD_IN_2B_N_0_1 1 0 2 NJ 80 NJ -preplace netloc AD_IN_2D_P_0_1 1 0 2 NJ 140 NJ -preplace netloc AD_IN_2C_N_0_1 1 0 2 NJ 120 NJ -preplace netloc processing_system7_0_SPI0_SS_O 1 5 1 NJ -preplace netloc processing_system7_0_SPI0_SCLK_O 1 5 1 NJ -preplace netloc processing_system7_0_FCLK_CLK0 1 0 6 -70 520 510 250 830 200 1240 200 1560 530 2040 -preplace netloc ps7_0_axi_periph_M00_AXI 1 2 1 820 -preplace netloc AD_IN_2D_N_0_1 1 0 2 NJ 160 NJ -preplace netloc AD_IN_1C_N_0_1 1 0 2 NJ -40 NJ -preplace netloc rst_ps7_0_100M_interconnect_aresetn 1 1 1 N -levelinfo -pg 1 -90 310 660 1030 1420 1810 2090 -top -500 -bot 860 +preplace netloc LTC2271_SampleGetter_0_M00_AXIS 1 2 1 740 +preplace netloc AD_DCO_N_0_1 1 0 2 NJ 110 NJ +preplace netloc AD_IN_1A_P_0_1 1 0 2 NJ 130 NJ +preplace netloc axi_dma_0_M_AXI_S2MM 1 3 1 1110 +preplace netloc AD_IN_2B_N_0_1 1 0 2 NJ 350 NJ +preplace netloc SPI0_MISO_0_1 1 5 1 NJ +preplace netloc AD_IN_2D_P_0_1 1 0 2 NJ 410 NJ +preplace netloc AD_IN_2C_N_0_1 1 0 2 NJ 390 NJ +preplace netloc processing_system7_0_FCLK_CLK0 1 0 6 20 440 400 520 730 700 1120 700 1420 840 1890 +preplace netloc ps7_0_axi_periph_M00_AXI 1 2 1 720 +preplace netloc processing_system7_0_SPI1_SCLK_O 1 5 1 NJ +preplace netloc AD_IN_2D_N_0_1 1 0 2 NJ 430 NJ +preplace netloc AD_IN_1C_N_0_1 1 0 2 NJ 230 NJ +preplace netloc rst_ps7_0_100M_interconnect_aresetn 1 1 1 380 +levelinfo -pg 1 0 200 560 920 1270 1650 1920 -top 0 -bot 870 ", } { diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.xpr b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.xpr index db1b4bf040dbbad2bff1dcb482403f93d4e3500d..b1f1b37454b941b99bfad9f8aa0acade5b29f4cb 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.xpr +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.xpr @@ -65,12 +65,12 @@ - - - + + + diff --git a/petalinux/mz7010_fmccc_2017_4/project-spec/configs/config b/petalinux/mz7010_fmccc_2017_4/project-spec/configs/config index 2cf26c5519291c7fb104b63034e162ca31353076..6a370ced8fa8cbe8f25e196c374adc473bab23d5 100644 --- a/petalinux/mz7010_fmccc_2017_4/project-spec/configs/config +++ b/petalinux/mz7010_fmccc_2017_4/project-spec/configs/config @@ -256,4 +256,10 @@ CONFIG_USER_LAYER_0="" + + + + + + CONFIG_SUBSYSTEM_BOOTARGS_GENERATED="console=ttyPS0,115200 earlyprintk" diff --git a/petalinux/mz7010_fmccc_2017_4/project-spec/hw-description/mz_petalinux_wrapper.bit b/petalinux/mz7010_fmccc_2017_4/project-spec/hw-description/mz_petalinux_wrapper.bit index f3d5cd03d6129b92e0b51c92d3080bfe38461117..8a6368109972fbb675217c961969f94651507509 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/project-spec/hw-description/mz_petalinux_wrapper.bit and b/petalinux/mz7010_fmccc_2017_4/project-spec/hw-description/mz_petalinux_wrapper.bit differ diff --git a/petalinux/mz7010_fmccc_2017_4/project-spec/hw-description/ps7_init.c b/petalinux/mz7010_fmccc_2017_4/project-spec/hw-description/ps7_init.c index 1464a72c78182d435d8840e6842c1d36a5a1897c..1ef86a3b326467098279787f6d0da24b895e0152 100644 --- a/petalinux/mz7010_fmccc_2017_4/project-spec/hw-description/ps7_init.c +++ b/petalinux/mz7010_fmccc_2017_4/project-spec/hw-description/ps7_init.c @@ -345,12 +345,12 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. ==> MASK : 0x00003F00U VAL : 0x00001400U // .. EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF8000158[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF8000158[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000158[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U // .. SRCSEL = 0x0 // .. ==> 0XF8000158[5:4] = 0x00000000U // .. ==> MASK : 0x00000030U VAL : 0x00000000U @@ -358,7 +358,7 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. ==> 0XF8000158[13:8] = 0x00000032U // .. ==> MASK : 0x00003F00U VAL : 0x00003200U // .. - EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003201U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003202U), // .. .. START: TRACE CLOCK // .. .. FINISH: TRACE CLOCK // .. .. CLKACT = 0x1 @@ -409,12 +409,12 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. .. SDI1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. SPI0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. SPI1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U // .. .. CAN0_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[16:16] = 0x00000000U // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U @@ -443,7 +443,7 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. .. ==> 0XF800012C[24:24] = 0x00000001U // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U // .. .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC444DU), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC844DU), // .. FINISH: CLOCK CONTROL SLCR REGISTERS // .. START: THIS SHOULD BE BLANK // .. FINISH: THIS SHOULD BE BLANK @@ -4463,12 +4463,12 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. ==> MASK : 0x00003F00U VAL : 0x00001400U // .. EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF8000158[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF8000158[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000158[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U // .. SRCSEL = 0x0 // .. ==> 0XF8000158[5:4] = 0x00000000U // .. ==> MASK : 0x00000030U VAL : 0x00000000U @@ -4476,7 +4476,7 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. ==> 0XF8000158[13:8] = 0x00000032U // .. ==> MASK : 0x00003F00U VAL : 0x00003200U // .. - EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003201U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003202U), // .. .. START: TRACE CLOCK // .. .. FINISH: TRACE CLOCK // .. .. CLKACT = 0x1 @@ -4527,12 +4527,12 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. .. SDI1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. SPI0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. SPI1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U // .. .. CAN0_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[16:16] = 0x00000000U // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U @@ -4561,7 +4561,7 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. .. ==> 0XF800012C[24:24] = 0x00000001U // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U // .. .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC444DU), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC844DU), // .. FINISH: CLOCK CONTROL SLCR REGISTERS // .. START: THIS SHOULD BE BLANK // .. FINISH: THIS SHOULD BE BLANK @@ -8734,12 +8734,12 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. ==> MASK : 0x00003F00U VAL : 0x00001400U // .. EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF8000158[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF8000158[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000158[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U // .. SRCSEL = 0x0 // .. ==> 0XF8000158[5:4] = 0x00000000U // .. ==> MASK : 0x00000030U VAL : 0x00000000U @@ -8747,7 +8747,7 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. ==> 0XF8000158[13:8] = 0x00000032U // .. ==> MASK : 0x00003F00U VAL : 0x00003200U // .. - EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003201U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003202U), // .. .. START: TRACE CLOCK // .. .. FINISH: TRACE CLOCK // .. .. CLKACT = 0x1 @@ -8798,12 +8798,12 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. .. SDI1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. SPI0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. SPI1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U // .. .. CAN0_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[16:16] = 0x00000000U // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U @@ -8832,7 +8832,7 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. .. ==> 0XF800012C[24:24] = 0x00000001U // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U // .. .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC444DU), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC844DU), // .. FINISH: CLOCK CONTROL SLCR REGISTERS // .. START: THIS SHOULD BE BLANK // .. FINISH: THIS SHOULD BE BLANK diff --git a/petalinux/mz7010_fmccc_2017_4/project-spec/hw-description/ps7_init.html b/petalinux/mz7010_fmccc_2017_4/project-spec/hw-description/ps7_init.html index fcd61f6a602f19ff555cd006d822d28ca0216404..c10a36353f4d5879976f5fc9f8523fb05a27cdb2 100644 --- a/petalinux/mz7010_fmccc_2017_4/project-spec/hw-description/ps7_init.html +++ b/petalinux/mz7010_fmccc_2017_4/project-spec/hw-description/ps7_init.html @@ -6907,10 +6907,10 @@ SLCR_LOCK 1 -1 +0 -1 +0 SPI 0 reference clock active: 0: Clock is disabled 1: Clock is enabled @@ -6927,10 +6927,10 @@ SLCR_LOCK 2 -0 +1 -0 +2 SPI 1 reference clock active: 0: Clock is disabled 1: Clock is enabled @@ -6990,7 +6990,7 @@ SLCR_LOCK -3201 +3202 SPI Ref Clock Control @@ -7616,10 +7616,10 @@ SLCR_LOCK 4000 -1 +0 -4000 +0 SPI 0 AMBA Clock control 0: disable, 1: enable @@ -7636,10 +7636,10 @@ SLCR_LOCK 8000 -0 +1 -0 +8000 SPI 1 AMBA Clock control 0: disable, 1: enable @@ -7839,7 +7839,7 @@ SLCR_LOCK -1ec444d +1ec844d AMBA Peripheral Clock Control @@ -52448,10 +52448,10 @@ SLCR_LOCK 1 -1 +0 -1 +0 SPI 0 reference clock active: 0: Clock is disabled 1: Clock is enabled @@ -52468,10 +52468,10 @@ SLCR_LOCK 2 -0 +1 -0 +2 SPI 1 reference clock active: 0: Clock is disabled 1: Clock is enabled @@ -52531,7 +52531,7 @@ SLCR_LOCK -3201 +3202 SPI Ref Clock Control @@ -53157,10 +53157,10 @@ SLCR_LOCK 4000 -1 +0 -4000 +0 SPI 0 AMBA Clock control 0: disable, 1: enable @@ -53177,10 +53177,10 @@ SLCR_LOCK 8000 -0 +1 -0 +8000 SPI 1 AMBA Clock control 0: disable, 1: enable @@ -53380,7 +53380,7 @@ SLCR_LOCK -1ec444d +1ec844d AMBA Peripheral Clock Control @@ -99117,10 +99117,10 @@ SLCR_LOCK 1 -1 +0 -1 +0 SPI 0 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. @@ -99137,10 +99137,10 @@ SLCR_LOCK 2 -0 +1 -0 +2 SPI 1 reference clock active. 0 - Clock is disabled. 1 - Clock is enabled. @@ -99200,7 +99200,7 @@ SLCR_LOCK -3201 +3202 SPI Reference Clock Control @@ -99826,10 +99826,10 @@ SLCR_LOCK 4000 -1 +0 -4000 +0 SPI 0 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. @@ -99846,10 +99846,10 @@ SLCR_LOCK 8000 -0 +1 -0 +8000 SPI 1 AMBA Clock active. 0 - Clock is disabled. 1 - Clock is enabled. @@ -100049,7 +100049,7 @@ SLCR_LOCK -1ec444d +1ec844d AMBA Peripheral Clock Control diff --git a/petalinux/mz7010_fmccc_2017_4/project-spec/hw-description/ps7_init.tcl b/petalinux/mz7010_fmccc_2017_4/project-spec/hw-description/ps7_init.tcl index 8cf2f177b0ee0f2c3d80c64910d9a3032198281a..24291b4fe2ecfca5e4f47e6f90fa87c07695b715 100644 --- a/petalinux/mz7010_fmccc_2017_4/project-spec/hw-description/ps7_init.tcl +++ b/petalinux/mz7010_fmccc_2017_4/project-spec/hw-description/ps7_init.tcl @@ -33,11 +33,11 @@ proc ps7_clock_init_data_3_0 {} { mask_write 0XF800014C 0x00003F31 0x00000501 mask_write 0XF8000150 0x00003F33 0x00002801 mask_write 0XF8000154 0x00003F33 0x00001402 - mask_write 0XF8000158 0x00003F33 0x00003201 + mask_write 0XF8000158 0x00003F33 0x00003202 mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000170 0x03F03F30 0x00200500 mask_write 0XF80001C4 0x00000001 0x00000001 - mask_write 0XF800012C 0x01FFCCCD 0x01EC444D + mask_write 0XF800012C 0x01FFCCCD 0x01EC844D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_3_0 {} { @@ -269,11 +269,11 @@ proc ps7_clock_init_data_2_0 {} { mask_write 0XF800014C 0x00003F31 0x00000501 mask_write 0XF8000150 0x00003F33 0x00002801 mask_write 0XF8000154 0x00003F33 0x00001402 - mask_write 0XF8000158 0x00003F33 0x00003201 + mask_write 0XF8000158 0x00003F33 0x00003202 mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000170 0x03F03F30 0x00200500 mask_write 0XF80001C4 0x00000001 0x00000001 - mask_write 0XF800012C 0x01FFCCCD 0x01EC444D + mask_write 0XF800012C 0x01FFCCCD 0x01EC844D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_2_0 {} { @@ -506,11 +506,11 @@ proc ps7_clock_init_data_1_0 {} { mask_write 0XF800014C 0x00003F31 0x00000501 mask_write 0XF8000150 0x00003F33 0x00002801 mask_write 0XF8000154 0x00003F33 0x00001402 - mask_write 0XF8000158 0x00003F33 0x00003201 + mask_write 0XF8000158 0x00003F33 0x00003202 mask_write 0XF8000168 0x00003F31 0x00000501 mask_write 0XF8000170 0x03F03F30 0x00200500 mask_write 0XF80001C4 0x00000001 0x00000001 - mask_write 0XF800012C 0x01FFCCCD 0x01EC444D + mask_write 0XF800012C 0x01FFCCCD 0x01EC844D mwr -force 0XF8000004 0x0000767B } proc ps7_ddr_init_data_1_0 {} { diff --git a/petalinux/mz7010_fmccc_2017_4/project-spec/hw-description/ps7_init_gpl.c b/petalinux/mz7010_fmccc_2017_4/project-spec/hw-description/ps7_init_gpl.c index bbf216942eb969339c81546949727a55bfc2789a..1db7d3041ef92a17785c88a6d558975a9b47bd17 100644 --- a/petalinux/mz7010_fmccc_2017_4/project-spec/hw-description/ps7_init_gpl.c +++ b/petalinux/mz7010_fmccc_2017_4/project-spec/hw-description/ps7_init_gpl.c @@ -336,12 +336,12 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. ==> MASK : 0x00003F00U VAL : 0x00001400U // .. EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF8000158[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF8000158[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000158[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U // .. SRCSEL = 0x0 // .. ==> 0XF8000158[5:4] = 0x00000000U // .. ==> MASK : 0x00000030U VAL : 0x00000000U @@ -349,7 +349,7 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. ==> 0XF8000158[13:8] = 0x00000032U // .. ==> MASK : 0x00003F00U VAL : 0x00003200U // .. - EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003201U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003202U), // .. .. START: TRACE CLOCK // .. .. FINISH: TRACE CLOCK // .. .. CLKACT = 0x1 @@ -400,12 +400,12 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. .. SDI1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. SPI0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. SPI1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U // .. .. CAN0_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[16:16] = 0x00000000U // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U @@ -434,7 +434,7 @@ unsigned long ps7_clock_init_data_3_0[] = { // .. .. ==> 0XF800012C[24:24] = 0x00000001U // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U // .. .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC444DU), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC844DU), // .. FINISH: CLOCK CONTROL SLCR REGISTERS // .. START: THIS SHOULD BE BLANK // .. FINISH: THIS SHOULD BE BLANK @@ -4454,12 +4454,12 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. ==> MASK : 0x00003F00U VAL : 0x00001400U // .. EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF8000158[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF8000158[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000158[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U // .. SRCSEL = 0x0 // .. ==> 0XF8000158[5:4] = 0x00000000U // .. ==> MASK : 0x00000030U VAL : 0x00000000U @@ -4467,7 +4467,7 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. ==> 0XF8000158[13:8] = 0x00000032U // .. ==> MASK : 0x00003F00U VAL : 0x00003200U // .. - EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003201U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003202U), // .. .. START: TRACE CLOCK // .. .. FINISH: TRACE CLOCK // .. .. CLKACT = 0x1 @@ -4518,12 +4518,12 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. .. SDI1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. SPI0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. SPI1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U // .. .. CAN0_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[16:16] = 0x00000000U // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U @@ -4552,7 +4552,7 @@ unsigned long ps7_clock_init_data_2_0[] = { // .. .. ==> 0XF800012C[24:24] = 0x00000001U // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U // .. .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC444DU), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC844DU), // .. FINISH: CLOCK CONTROL SLCR REGISTERS // .. START: THIS SHOULD BE BLANK // .. FINISH: THIS SHOULD BE BLANK @@ -8725,12 +8725,12 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. ==> MASK : 0x00003F00U VAL : 0x00001400U // .. EMIT_MASKWRITE(0XF8000154, 0x00003F33U ,0x00001402U), - // .. CLKACT0 = 0x1 - // .. ==> 0XF8000158[0:0] = 0x00000001U - // .. ==> MASK : 0x00000001U VAL : 0x00000001U - // .. CLKACT1 = 0x0 - // .. ==> 0XF8000158[1:1] = 0x00000000U - // .. ==> MASK : 0x00000002U VAL : 0x00000000U + // .. CLKACT0 = 0x0 + // .. ==> 0XF8000158[0:0] = 0x00000000U + // .. ==> MASK : 0x00000001U VAL : 0x00000000U + // .. CLKACT1 = 0x1 + // .. ==> 0XF8000158[1:1] = 0x00000001U + // .. ==> MASK : 0x00000002U VAL : 0x00000002U // .. SRCSEL = 0x0 // .. ==> 0XF8000158[5:4] = 0x00000000U // .. ==> MASK : 0x00000030U VAL : 0x00000000U @@ -8738,7 +8738,7 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. ==> 0XF8000158[13:8] = 0x00000032U // .. ==> MASK : 0x00003F00U VAL : 0x00003200U // .. - EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003201U), + EMIT_MASKWRITE(0XF8000158, 0x00003F33U ,0x00003202U), // .. .. START: TRACE CLOCK // .. .. FINISH: TRACE CLOCK // .. .. CLKACT = 0x1 @@ -8789,12 +8789,12 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. .. SDI1_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[11:11] = 0x00000000U // .. .. ==> MASK : 0x00000800U VAL : 0x00000000U - // .. .. SPI0_CPU_1XCLKACT = 0x1 - // .. .. ==> 0XF800012C[14:14] = 0x00000001U - // .. .. ==> MASK : 0x00004000U VAL : 0x00004000U - // .. .. SPI1_CPU_1XCLKACT = 0x0 - // .. .. ==> 0XF800012C[15:15] = 0x00000000U - // .. .. ==> MASK : 0x00008000U VAL : 0x00000000U + // .. .. SPI0_CPU_1XCLKACT = 0x0 + // .. .. ==> 0XF800012C[14:14] = 0x00000000U + // .. .. ==> MASK : 0x00004000U VAL : 0x00000000U + // .. .. SPI1_CPU_1XCLKACT = 0x1 + // .. .. ==> 0XF800012C[15:15] = 0x00000001U + // .. .. ==> MASK : 0x00008000U VAL : 0x00008000U // .. .. CAN0_CPU_1XCLKACT = 0x0 // .. .. ==> 0XF800012C[16:16] = 0x00000000U // .. .. ==> MASK : 0x00010000U VAL : 0x00000000U @@ -8823,7 +8823,7 @@ unsigned long ps7_clock_init_data_1_0[] = { // .. .. ==> 0XF800012C[24:24] = 0x00000001U // .. .. ==> MASK : 0x01000000U VAL : 0x01000000U // .. .. - EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC444DU), + EMIT_MASKWRITE(0XF800012C, 0x01FFCCCDU ,0x01EC844DU), // .. FINISH: CLOCK CONTROL SLCR REGISTERS // .. START: THIS SHOULD BE BLANK // .. FINISH: THIS SHOULD BE BLANK diff --git a/petalinux/mz7010_fmccc_2017_4/project-spec/hw-description/system.hdf b/petalinux/mz7010_fmccc_2017_4/project-spec/hw-description/system.hdf index 0f684eac521969b0bec5301cf8190cff95866d02..d1f3f9ba14a675ec24b102894abe8dff3cc74a90 100644 Binary files a/petalinux/mz7010_fmccc_2017_4/project-spec/hw-description/system.hdf and b/petalinux/mz7010_fmccc_2017_4/project-spec/hw-description/system.hdf differ diff --git a/petalinux/mz7010_fmccc_2017_4/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi b/petalinux/mz7010_fmccc_2017_4/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi index 35752887186a5a7484a21ca39ec3d3fdd0f42d9c..cbe666e2c1785a9b1125e5ac12dbc0bcfcb765a6 100644 --- a/petalinux/mz7010_fmccc_2017_4/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi +++ b/petalinux/mz7010_fmccc_2017_4/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi @@ -52,18 +52,18 @@ usb-phy = <&usb_phy0>; }; -&spi0 { +&spi1 { status = "okay"; - num-cs = <3>; + num-cs = <2>; is-decoded-cs = <0>; spidev@0 { compatible = "linux,spidev"; - spi-max-frequency = <25000000>; + spi-max-frequency = <1000000>; reg = <0>; }; spidev@1 { compatible = "linux,spidev"; - spi-max-frequency = <25000000>; + spi-max-frequency = <1000000>; reg = <1>; }; };