Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 | Date : Tue Oct 15 02:05:21 2019 | Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS | Command : report_clock_utilization -file LTC2271_SampleGetter_v1_0_clock_utilization_routed.rpt | Design : LTC2271_SampleGetter_v1_0 | Device : 7z010-clg400 | Speed File : -1 PRODUCTION 1.11 2014-09-11 ------------------------------------------------------------------------------------------------------- Clock Utilization Report Table of Contents ----------------- 1. Clock Primitive Utilization 2. Global Clock Resources 3. Global Clock Source Details 4. Clock Regions: Key Resource Utilization 5. Clock Regions : Global Clock Summary 6. Device Cell Placement Summary for Global Clock g0 7. Clock Region Cell Placement per Global Clock: Region X1Y0 1. Clock Primitive Utilization ------------------------------ +----------+------+-----------+-----+--------------+--------+ | Type | Used | Available | LOC | Clock Region | Pblock | +----------+------+-----------+-----+--------------+--------+ | BUFGCTRL | 1 | 32 | 0 | 0 | 0 | | BUFH | 0 | 48 | 0 | 0 | 0 | | BUFIO | 0 | 8 | 0 | 0 | 0 | | BUFMR | 0 | 4 | 0 | 0 | 0 | | BUFR | 0 | 8 | 0 | 0 | 0 | | MMCM | 0 | 2 | 0 | 0 | 0 | | PLL | 0 | 2 | 0 | 0 | 0 | +----------+------+-----------+-----+--------------+--------+ 2. Global Clock Resources ------------------------- +-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+--------------------------------+-------------------------+ | Global Id | Source Id | Driver Type/Pin | Constraint | Site | Clock Region | Load Clock Region | Clock Loads | Non-Clock Loads | Clock Period | Clock | Driver Pin | Net | +-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+--------------------------------+-------------------------+ | g0 | src0 | BUFG/O | None | BUFGCTRL_X0Y0 | n/a | 1 | 64 | 0 | | | m00_axis_aclk_IBUF_BUFG_inst/O | m00_axis_aclk_IBUF_BUFG | +-----------+-----------+-----------------+------------+---------------+--------------+-------------------+-------------+-----------------+--------------+-------+--------------------------------+-------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) 3. Global Clock Source Details ------------------------------ +-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+---------------------------+--------------------+ | Source Id | Global Id | Driver Type/Pin | Constraint | Site | Clock Region | Clock Loads | Non-Clock Loads | Source Clock Period | Source Clock | Driver Pin | Net | +-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+---------------------------+--------------------+ | src0 | g0 | IBUF/O | None | IOB_X0Y28 | X1Y0 | 1 | 0 | | | m00_axis_aclk_IBUF_inst/O | m00_axis_aclk_IBUF | +-----------+-----------+-----------------+------------+-----------+--------------+-------------+-----------------+---------------------+--------------+---------------------------+--------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) 4. Clock Regions: Key Resource Utilization ------------------------------------------ +-------------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+ | | Global Clock | BUFRs | BUFMRs | BUFIOs | MMCM | PLL | GT | PCI | ILOGIC | OLOGIC | FF | LUTM | RAMB18 | RAMB36 | DSP48E2 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ | Clock Region Name | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | Used | Avail | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ | X0Y0 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1100 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | | X1Y0 | 1 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 64 | 1100 | 17 | 350 | 0 | 40 | 0 | 20 | 0 | 20 | | X0Y1 | 0 | 12 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1100 | 0 | 400 | 0 | 20 | 0 | 10 | 0 | 20 | | X1Y1 | 0 | 12 | 0 | 4 | 0 | 2 | 0 | 4 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 50 | 0 | 50 | 0 | 1100 | 0 | 350 | 0 | 40 | 0 | 20 | 0 | 20 | +-------------------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+------+-------+ * Global Clock column represents track count; while other columns represents cell counts 5. Clock Regions : Global Clock Summary --------------------------------------- All Modules +----+----+----+ | | X0 | X1 | +----+----+----+ | Y1 | 0 | 0 | | Y0 | 0 | 1 | +----+----+----+ 6. Device Cell Placement Summary for Global Clock g0 ---------------------------------------------------- +-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------------------+ | Global Id | Driver Type/Pin | Driver Region (D) | Clock | Period (ns) | Waveform (ns) | Slice Loads | IO Loads | Clocking Loads | GT Loads | Net | +-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------------------+ | g0 | BUFG/O | n/a | | | | 64 | 0 | 0 | 0 | m00_axis_aclk_IBUF_BUFG | +-----------+-----------------+-------------------+-------+-------------+---------------+-------------+----------+----------------+----------+-------------------------+ * Logic Loads column represents load cell count of all cell types other than IO, GT and clock resources ** IO Loads column represents load cell count of IO types *** Clocking Loads column represents load cell count that are clock resources (global clock buffer, MMCM, PLL, etc) **** GT Loads column represents load cell count of GT types +----+----+-----+ | | X0 | X1 | +----+----+-----+ | Y1 | 0 | 0 | | Y0 | 0 | 64 | +----+----+-----+ 7. Clock Region Cell Placement per Global Clock: Region X1Y0 ------------------------------------------------------------ +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------------+ | Global Id | Track | Driver Type/Pin | Constraint | Clock Loads | Non-Clock Loads | FF | LUTRAM | RAMB | DSP | GT | MMCM | PLL | Hard IP | Net | +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------------+ | g0 | n/a | BUFG/O | None | 64 | 0 | 64 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | m00_axis_aclk_IBUF_BUFG | +-----------+-------+-----------------+------------+-------------+-----------------+----+--------+------+-----+----+------+-----+---------+-------------------------+ * Clock Loads column represents the clock pin loads (pin count) ** Non-Clock Loads column represents the non-clock pin loads (pin count) *** Columns FF, LUTRAM, RAMB through 'Hard IP' represents load cell counts # Location of BUFG Primitives set_property LOC BUFGCTRL_X0Y0 [get_cells m00_axis_aclk_IBUF_BUFG_inst] # Location of IO Primitives which is load of clock spine # Location of clock ports set_property LOC IOB_X0Y28 [get_ports m00_axis_aclk] # Clock net "m00_axis_aclk_IBUF_BUFG" driven by instance "m00_axis_aclk_IBUF_BUFG_inst" located at site "BUFGCTRL_X0Y0" #startgroup create_pblock {CLKAG_m00_axis_aclk_IBUF_BUFG} add_cells_to_pblock [get_pblocks {CLKAG_m00_axis_aclk_IBUF_BUFG}] [get_cells -filter { PRIMITIVE_GROUP != I/O && IS_PRIMITIVE==1 && PRIMITIVE_LEVEL !=INTERNAL } -of_object [get_pins -filter {DIRECTION==IN} -of_objects [get_nets -hierarchical -filter {PARENT=="m00_axis_aclk_IBUF_BUFG"}]]] resize_pblock [get_pblocks {CLKAG_m00_axis_aclk_IBUF_BUFG}] -add {CLOCKREGION_X1Y0:CLOCKREGION_X1Y0} #endgroup