Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
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| Tool Version     : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
| Date             : Tue Oct 15 02:05:21 2019
| Host             : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS
| Command          : report_power -file LTC2271_SampleGetter_v1_0_power_routed.rpt -pb LTC2271_SampleGetter_v1_0_power_summary_routed.pb -rpx LTC2271_SampleGetter_v1_0_power_routed.rpx
| Design           : LTC2271_SampleGetter_v1_0
| Device           : xc7z010clg400-1
| Design State     : routed
| Grade            : commercial
| Process          : typical
| Characterization : Production
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Power Report

Table of Contents
-----------------
1. Summary
1.1 On-Chip Components
1.2 Power Supply Summary
1.3 Confidence Level
2. Settings
2.1 Environment
2.2 Clock Constraints
3. Detailed Reports
3.1 By Hierarchy

1. Summary
----------

+--------------------------+----------------------------------+
| Total On-Chip Power (W)  | 11.738 (Junction temp exceeded!) |
| Design Power Budget (W)  | Unspecified*                     |
| Power Budget Margin (W)  | NA                               |
| Dynamic (W)              | 10.991                           |
| Device Static (W)        | 0.747                            |
| Effective TJA (C/W)      | 11.5                             |
| Max Ambient (C)          | 0.0                              |
| Junction Temperature (C) | 125.0                            |
| Confidence Level         | Low                              |
| Setting File             | ---                              |
| Simulation Activity File | ---                              |
| Design Nets Matched      | NA                               |
+--------------------------+----------------------------------+
* Specify Design Power Budget using, set_operating_conditions -design_power_budget <value in Watts>


1.1 On-Chip Components
----------------------

+----------------+-----------+----------+-----------+-----------------+
| On-Chip        | Power (W) | Used     | Available | Utilization (%) |
+----------------+-----------+----------+-----------+-----------------+
| Slice Logic    |     0.049 |       76 |       --- |             --- |
|   Register     |     0.025 |       64 |     35200 |            0.18 |
|   CARRY4       |     0.017 |        8 |      4400 |            0.18 |
|   BUFG         |     0.006 |        1 |        32 |            3.13 |
|   LUT as Logic |     0.001 |        1 |     17600 |           <0.01 |
|   Others       |     0.000 |        2 |       --- |             --- |
| Signals        |     0.261 |       73 |       --- |             --- |
| I/O            |    10.680 |       39 |       100 |           39.00 |
| Static Power   |     0.747 |          |           |                 |
| Total          |    11.738 |          |           |                 |
+----------------+-----------+----------+-----------+-----------------+


1.2 Power Supply Summary
------------------------

+-----------+-------------+-----------+-------------+------------+
| Source    | Voltage (V) | Total (A) | Dynamic (A) | Static (A) |
+-----------+-------------+-----------+-------------+------------+
| Vccint    |       1.000 |     0.443 |       0.314 |      0.129 |
| Vccaux    |       1.800 |     0.914 |       0.874 |      0.040 |
| Vcco33    |       3.300 |     0.000 |       0.000 |      0.000 |
| Vcco25    |       2.500 |     0.000 |       0.000 |      0.000 |
| Vcco18    |       1.800 |     5.058 |       5.057 |      0.001 |
| Vcco15    |       1.500 |     0.000 |       0.000 |      0.000 |
| Vcco135   |       1.350 |     0.000 |       0.000 |      0.000 |
| Vcco12    |       1.200 |     0.000 |       0.000 |      0.000 |
| Vccaux_io |       1.800 |     0.000 |       0.000 |      0.000 |
| Vccbram   |       1.000 |     0.011 |       0.000 |      0.011 |
| MGTAVcc   |       1.000 |     0.000 |       0.000 |      0.000 |
| MGTAVtt   |       1.200 |     0.000 |       0.000 |      0.000 |
| MGTVccaux |       1.800 |     0.000 |       0.000 |      0.000 |
| Vccpint   |       1.000 |     0.473 |       0.000 |      0.473 |
| Vccpaux   |       1.800 |     0.010 |       0.000 |      0.010 |
| Vccpll    |       1.800 |     0.003 |       0.000 |      0.003 |
| Vcco_ddr  |       1.500 |     0.000 |       0.000 |      0.000 |
| Vcco_mio0 |       1.800 |     0.000 |       0.000 |      0.000 |
| Vcco_mio1 |       1.800 |     0.000 |       0.000 |      0.000 |
| Vccadc    |       1.800 |     0.020 |       0.000 |      0.020 |
+-----------+-------------+-----------+-------------+------------+


1.3 Confidence Level
--------------------

+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| User Input Data             | Confidence | Details                                                | Action                                                                                                             |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+
| Design implementation state | High       | Design is routed                                       |                                                                                                                    |
| Clock nodes activity        | Low        | User specified less than 75% of clocks                 | Provide missing clock activity with a constraint file, simulation results or by editing the "By Clock Domain" view |
| I/O nodes activity          | Low        | More than 75% of inputs are missing user specification | Provide missing input activity with simulation results or by editing the "By Resource Type -> I/Os" view           |
| Internal nodes activity     | Medium     | User specified less than 25% of internal nodes         | Provide missing internal nodes activity with simulation results or by editing the "By Resource Type" views         |
| Device models               | High       | Device models are Production                           |                                                                                                                    |
|                             |            |                                                        |                                                                                                                    |
| Overall confidence level    | Low        |                                                        |                                                                                                                    |
+-----------------------------+------------+--------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------+


2. Settings
-----------

2.1 Environment
---------------

+-----------------------+------------------------+
| Ambient Temp (C)      | 25.0                   |
| ThetaJA (C/W)         | 11.5                   |
| Airflow (LFM)         | 250                    |
| Heat Sink             | none                   |
| ThetaSA (C/W)         | 0.0                    |
| Board Selection       | medium (10"x10")       |
| # of Board Layers     | 8to11 (8 to 11 Layers) |
| Board Temperature (C) | 25.0                   |
+-----------------------+------------------------+


2.2 Clock Constraints
---------------------

+-------+--------+-----------------+
| Clock | Domain | Constraint (ns) |
+-------+--------+-----------------+


3. Detailed Reports
-------------------

3.1 By Hierarchy
----------------

+---------------------------+-----------+
| Name                      | Power (W) |
+---------------------------+-----------+
| LTC2271_SampleGetter_v1_0 |    10.991 |
+---------------------------+-----------+