*** Running vivado with args -log LTC2271_SampleGetter_v1_0.vds -m64 -product Vivado -mode batch -messageDb vivado.pb -notrace -source LTC2271_SampleGetter_v1_0.tcl ****** Vivado v2017.4 (64-bit) **** SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017 **** IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. source LTC2271_SampleGetter_v1_0.tcl -notrace Command: synth_design -top LTC2271_SampleGetter_v1_0 -part xc7z010clg400-1 Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010' INFO: Launching helper process for spawning children vivado processes INFO: Helper process launched with PID 16325 --------------------------------------------------------------------------------- Starting Synthesize : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1290.672 ; gain = 87.996 ; free physical = 923 ; free virtual = 10972 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'LTC2271_SampleGetter_v1_0' [/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v:4] Parameter C_M00_AXIS_TDATA_WIDTH bound to: 32 - type: integer Parameter C_M00_AXIS_START_COUNT bound to: 32 - type: integer INFO: [Synth 8-638] synthesizing module 'IBUFDS' [/home/nats/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:19483] Parameter CAPACITANCE bound to: DONT_CARE - type: string Parameter DIFF_TERM bound to: TRUE - type: string Parameter DQS_BIAS bound to: FALSE - type: string Parameter IBUF_DELAY_VALUE bound to: 0 - type: string Parameter IBUF_LOW_PWR bound to: FALSE - type: string Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-256] done synthesizing module 'IBUFDS' (1#1) [/home/nats/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:19483] INFO: [Synth 8-638] synthesizing module 'IDDR' [/home/nats/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:21382] Parameter DDR_CLK_EDGE bound to: SAME_EDGE_PIPELINED - type: string Parameter INIT_Q1 bound to: 1'b0 Parameter INIT_Q2 bound to: 1'b0 Parameter IS_C_INVERTED bound to: 1'b0 Parameter IS_D_INVERTED bound to: 1'b0 Parameter SRTYPE bound to: SYNC - type: string INFO: [Synth 8-256] done synthesizing module 'IDDR' (2#1) [/home/nats/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:21382] WARNING: [Synth 8-350] instance 'DDR_1A' of module 'IDDR' requires 7 connections, but only 5 given [/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v:93] WARNING: [Synth 8-350] instance 'DDR_2A' of module 'IDDR' requires 7 connections, but only 5 given [/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v:101] INFO: [Synth 8-256] done synthesizing module 'LTC2271_SampleGetter_v1_0' (3#1) [/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v:4] WARNING: [Synth 8-3331] design LTC2271_SampleGetter_v1_0 has unconnected port m00_axis_aresetn WARNING: [Synth 8-3331] design LTC2271_SampleGetter_v1_0 has unconnected port m00_axis_tready --------------------------------------------------------------------------------- Finished Synthesize : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1332.203 ; gain = 129.527 ; free physical = 936 ; free virtual = 10987 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1332.203 ; gain = 129.527 ; free physical = 935 ; free virtual = 10986 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z010clg400-1 --------------------------------------------------------------------------------- Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1340.207 ; gain = 137.531 ; free physical = 935 ; free virtual = 10986 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z010clg400-1 WARNING: [Synth 8-6014] Unused sequential element cnt_reg was removed. [/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v:119] --------------------------------------------------------------------------------- Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1348.215 ; gain = 145.539 ; free physical = 934 ; free virtual = 10985 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start RTL Component Statistics --------------------------------------------------------------------------------- Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 2 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- Hierarchical RTL Component report Module LTC2271_SampleGetter_v1_0 Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 4 Bit Registers := 1 1 Bit Registers := 2 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Part Resource Summary --------------------------------------------------------------------------------- Part Resources: DSPs: 80 (col length:40) BRAMs: 120 (col length: RAMB18 40 RAMB36 20) --------------------------------------------------------------------------------- Finished Part Resource Summary --------------------------------------------------------------------------------- No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- WARNING: [Synth 8-6014] Unused sequential element cnt_reg was removed. [/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v:119] WARNING: [Synth 8-3331] design LTC2271_SampleGetter_v1_0 has unconnected port m00_axis_aresetn WARNING: [Synth 8-3331] design LTC2271_SampleGetter_v1_0 has unconnected port m00_axis_tready INFO: [Synth 8-3333] propagating constant 0 across sequential element (m00_axis_tlast_reg) INFO: [Synth 8-3886] merging instance 'm00_axis_tstrb_reg[0]' (FD) to 'm00_axis_tstrb_reg[3]' INFO: [Synth 8-3886] merging instance 'm00_axis_tstrb_reg[1]' (FD) to 'm00_axis_tstrb_reg[3]' INFO: [Synth 8-3886] merging instance 'm00_axis_tstrb_reg[2]' (FD) to 'm00_axis_tstrb_reg[3]' INFO: [Synth 8-3886] merging instance 'm00_axis_tstrb_reg[3]' (FD) to 'm00_axis_tvalid_reg' INFO: [Synth 8-3333] propagating constant 1 across sequential element (m00_axis_tvalid_reg) WARNING: [Synth 8-3332] Sequential element (m00_axis_tvalid_reg) is unused and will be removed from module LTC2271_SampleGetter_v1_0. WARNING: [Synth 8-3332] Sequential element (m00_axis_tlast_reg) is unused and will be removed from module LTC2271_SampleGetter_v1_0. --------------------------------------------------------------------------------- Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:22 . Memory (MB): peak = 1448.566 ; gain = 245.891 ; free physical = 759 ; free virtual = 10836 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ No constraint files found. --------------------------------------------------------------------------------- Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Timing Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:22 . Memory (MB): peak = 1448.566 ; gain = 245.891 ; free physical = 758 ; free virtual = 10835 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Technology Mapping : Time (s): cpu = 00:00:13 ; elapsed = 00:00:22 . Memory (MB): peak = 1457.582 ; gain = 254.906 ; free physical = 757 ; free virtual = 10835 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Flattening Before IO Insertion --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished IO Insertion : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1457.582 ; gain = 254.906 ; free physical = 754 ; free virtual = 10832 --------------------------------------------------------------------------------- Report Check Netlist: +------+------------------+-------+---------+-------+------------------+ | |Item |Errors |Warnings |Status |Description | +------+------------------+-------+---------+-------+------------------+ |1 |multi_driven_nets | 0| 0|Passed |Multi driven nets | +------+------------------+-------+---------+-------+------------------+ --------------------------------------------------------------------------------- Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Instances : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1457.582 ; gain = 254.906 ; free physical = 754 ; free virtual = 10832 --------------------------------------------------------------------------------- Report RTL Partitions: +-+--------------+------------+----------+ | |RTL Partition |Replication |Instances | +-+--------------+------------+----------+ +-+--------------+------------+----------+ --------------------------------------------------------------------------------- Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1457.582 ; gain = 254.906 ; free physical = 754 ; free virtual = 10832 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Ports : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1457.582 ; gain = 254.906 ; free physical = 754 ; free virtual = 10832 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1457.582 ; gain = 254.906 ; free physical = 754 ; free virtual = 10832 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Finished Renaming Generated Nets : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1457.582 ; gain = 254.906 ; free physical = 754 ; free virtual = 10832 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report --------------------------------------------------------------------------------- Report BlackBoxes: +-+--------------+----------+ | |BlackBox name |Instances | +-+--------------+----------+ +-+--------------+----------+ Report Cell Usage: +------+-------+------+ | |Cell |Count | +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 8| |3 |IDDR | 2| |4 |LUT1 | 1| |5 |FDRE | 64| |6 |IBUF | 1| |7 |IBUFDS | 10| |8 |OBUF | 38| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ |1 |top | | 125| +------+---------+-------+------+ --------------------------------------------------------------------------------- Finished Writing Synthesis Report : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1457.582 ; gain = 254.906 ; free physical = 754 ; free virtual = 10832 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 10 warnings. Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1457.582 ; gain = 254.906 ; free physical = 756 ; free virtual = 10833 Synthesis Optimization Complete : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1457.590 ; gain = 254.906 ; free physical = 756 ; free virtual = 10833 INFO: [Project 1-571] Translating synthesized netlist INFO: [Netlist 29-17] Analyzing 21 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis 21 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully synth_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1534.582 ; gain = 357.734 ; free physical = 699 ; free virtual = 10792 INFO: [Common 17-1381] The checkpoint '/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/LTC2271_SampleGetter_v1_0.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file LTC2271_SampleGetter_v1_0_utilization_synth.rpt -pb LTC2271_SampleGetter_v1_0_utilization_synth.pb report_utilization: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1558.594 ; gain = 0.000 ; free physical = 703 ; free virtual = 10795 INFO: [Common 17-206] Exiting Vivado at Tue Oct 15 02:04:16 2019...