rfporn.org
user
VNA_Config
1.0
VNA_Config_AXI
AWADDR
vna_config_axi_awaddr
AWPROT
vna_config_axi_awprot
AWVALID
vna_config_axi_awvalid
AWREADY
vna_config_axi_awready
WDATA
vna_config_axi_wdata
WSTRB
vna_config_axi_wstrb
WVALID
vna_config_axi_wvalid
WREADY
vna_config_axi_wready
BRESP
vna_config_axi_bresp
BVALID
vna_config_axi_bvalid
BREADY
vna_config_axi_bready
ARADDR
vna_config_axi_araddr
ARPROT
vna_config_axi_arprot
ARVALID
vna_config_axi_arvalid
ARREADY
vna_config_axi_arready
RDATA
vna_config_axi_rdata
RRESP
vna_config_axi_rresp
RVALID
vna_config_axi_rvalid
RREADY
vna_config_axi_rready
WIZ_DATA_WIDTH
32
WIZ_NUM_REG
4
SUPPORTS_NARROW_BURST
0
IRQ
INTERRUPT
irq
SENSITIVITY
LEVEL_HIGH
S_AXI_INTR
AWADDR
s_axi_intr_awaddr
AWPROT
s_axi_intr_awprot
AWVALID
s_axi_intr_awvalid
AWREADY
s_axi_intr_awready
WDATA
s_axi_intr_wdata
WSTRB
s_axi_intr_wstrb
WVALID
s_axi_intr_wvalid
WREADY
s_axi_intr_wready
BRESP
s_axi_intr_bresp
BVALID
s_axi_intr_bvalid
BREADY
s_axi_intr_bready
ARADDR
s_axi_intr_araddr
ARPROT
s_axi_intr_arprot
ARVALID
s_axi_intr_arvalid
ARREADY
s_axi_intr_arready
RDATA
s_axi_intr_rdata
RRESP
s_axi_intr_rresp
RVALID
s_axi_intr_rvalid
RREADY
s_axi_intr_rready
WIZ_DATA_WIDTH
32
WIZ_NUM_REG
5
SUPPORTS_NARROW_BURST
0
VNA_Config_AXI_RST
RST
vna_config_axi_aresetn
POLARITY
ACTIVE_LOW
VNA_Config_AXI_CLK
CLK
vna_config_axi_aclk
ASSOCIATED_BUSIF
VNA_Config_AXI
ASSOCIATED_RESET
vna_config_axi_aresetn
S_AXI_INTR_RST
RST
s_axi_intr_aresetn
POLARITY
ACTIVE_LOW
S_AXI_INTR_CLK
CLK
s_axi_intr_aclk
ASSOCIATED_BUSIF
S_AXI_INTR
ASSOCIATED_RESET
s_axi_intr_aresetn
VNA_Config_AXI
VNA_Config_AXI_reg
0
4096
32
register
OFFSET_BASE_PARAM
C_VNA_Config_AXI_BASEADDR
OFFSET_HIGH_PARAM
C_VNA_Config_AXI_HIGHADDR
S_AXI_INTR
S_AXI_INTR_reg
0
4096
32
register
OFFSET_BASE_PARAM
C_S_AXI_INTR_BASEADDR
OFFSET_HIGH_PARAM
C_S_AXI_INTR_HIGHADDR
xilinx_verilogsynthesis
Verilog Synthesis
verilogSource:vivado.xilinx.com:synthesis
verilog
VNA_Config_v1_0
xilinx_verilogsynthesis_view_fileset
viewChecksum
ff08bdb3
xilinx_verilogbehavioralsimulation
Verilog Simulation
verilogSource:vivado.xilinx.com:simulation
verilog
VNA_Config_v1_0
xilinx_verilogbehavioralsimulation_view_fileset
viewChecksum
ff08bdb3
xilinx_softwaredriver
Software Driver
:vivado.xilinx.com:sw.driver
xilinx_softwaredriver_view_fileset
viewChecksum
2c65fc92
xilinx_xpgui
UI Layout
:vivado.xilinx.com:xgui.ui
xilinx_xpgui_view_fileset
viewChecksum
beab2fb5
bd_tcl
Block Diagram
:vivado.xilinx.com:block.diagram
bd_tcl_view_fileset
viewChecksum
45a2f450
ADC_SCK
out
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
ADC_MOSI
out
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
ADC1_CS
out
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
ADC2_CS
out
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
ADC_MISO
in
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
SI_SCL
out
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
SI_SDA
out
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
vna_config_axi_awaddr
in
3
0
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
vna_config_axi_awprot
in
2
0
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
vna_config_axi_awvalid
in
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
vna_config_axi_awready
out
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
vna_config_axi_wdata
in
31
0
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
vna_config_axi_wstrb
in
3
0
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
vna_config_axi_wvalid
in
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
vna_config_axi_wready
out
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
vna_config_axi_bresp
out
1
0
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
vna_config_axi_bvalid
out
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
vna_config_axi_bready
in
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
vna_config_axi_araddr
in
3
0
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
vna_config_axi_arprot
in
2
0
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
vna_config_axi_arvalid
in
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
vna_config_axi_arready
out
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
vna_config_axi_rdata
out
31
0
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
vna_config_axi_rresp
out
1
0
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
vna_config_axi_rvalid
out
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
vna_config_axi_rready
in
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
vna_config_axi_aclk
in
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
vna_config_axi_aresetn
in
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
s_axi_intr_awaddr
in
4
0
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
s_axi_intr_awprot
in
2
0
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
s_axi_intr_awvalid
in
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
s_axi_intr_awready
out
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
s_axi_intr_wdata
in
31
0
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
s_axi_intr_wstrb
in
3
0
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
s_axi_intr_wvalid
in
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
s_axi_intr_wready
out
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
s_axi_intr_bresp
out
1
0
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
s_axi_intr_bvalid
out
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
s_axi_intr_bready
in
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
s_axi_intr_araddr
in
4
0
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
s_axi_intr_arprot
in
2
0
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
s_axi_intr_arvalid
in
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
s_axi_intr_arready
out
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
s_axi_intr_rdata
out
31
0
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
s_axi_intr_rresp
out
1
0
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
s_axi_intr_rvalid
out
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
s_axi_intr_rready
in
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
s_axi_intr_aclk
in
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
s_axi_intr_aresetn
in
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
irq
out
wire
xilinx_verilogsynthesis
xilinx_verilogbehavioralsimulation
C_VNA_Config_AXI_DATA_WIDTH
C VNA Config AXI DATA WIDTH
Width of S_AXI data bus
32
C_VNA_Config_AXI_ADDR_WIDTH
C VNA Config AXI ADDR WIDTH
Width of S_AXI address bus
4
C_S_AXI_INTR_DATA_WIDTH
C S AXI INTR DATA WIDTH
Width of S_AXI data bus
32
C_S_AXI_INTR_ADDR_WIDTH
C S AXI INTR ADDR WIDTH
Width of S_AXI address bus
5
C_NUM_OF_INTR
C NUM OF INTR
Number of Interrupts
1
C_INTR_SENSITIVITY
C INTR SENSITIVITY
Each bit corresponds to Sensitivity of interrupt : 0 - EDGE, 1 - LEVEL
0xFFFFFFFF
C_INTR_ACTIVE_STATE
C INTR ACTIVE STATE
Each bit corresponds to Sub-type of INTR: [0 - FALLING_EDGE, 1 - RISING_EDGE : if C_INTR_SENSITIVITY is EDGE(0)] and [ 0 - LEVEL_LOW, 1 - LEVEL_LOW : if C_INTR_SENSITIVITY is LEVEL(1) ]
0xFFFFFFFF
C_IRQ_SENSITIVITY
C IRQ SENSITIVITY
Sensitivity of IRQ: 0 - EDGE, 1 - LEVEL
1
C_IRQ_ACTIVE_STATE
C IRQ ACTIVE STATE
Sub-type of IRQ: [0 - FALLING_EDGE, 1 - RISING_EDGE : if C_IRQ_SENSITIVITY is EDGE(0)] and [ 0 - LEVEL_LOW, 1 - LEVEL_LOW : if C_IRQ_SENSITIVITY is LEVEL(1) ]
1
choice_list_6fc15197
32
choice_list_99a1d2b9
LEVEL_HIGH
LEVEL_LOW
EDGE_RISING
EDGE_FALLING
choice_pairs_ce1226b1
1
0
xilinx_verilogsynthesis_view_fileset
hdl/VNA_Config_v1_0_VNA_Config_AXI.v
verilogSource
hdl/VNA_Config_v1_0_S_AXI_INTR.v
verilogSource
hdl/config_fsm.v
verilogSource
src/i2c_master.v
verilogSource
src/spi_master.v
verilogSource
hdl/VNA_Config_v1_0.v
verilogSource
CHECKSUM_6398e8c0
xilinx_verilogbehavioralsimulation_view_fileset
hdl/VNA_Config_v1_0_VNA_Config_AXI.v
verilogSource
hdl/VNA_Config_v1_0_S_AXI_INTR.v
verilogSource
hdl/config_fsm.v
verilogSource
src/i2c_master.v
verilogSource
src/spi_master.v
verilogSource
hdl/VNA_Config_v1_0.v
verilogSource
xilinx_softwaredriver_view_fileset
drivers/VNA_Config_v1_0/data/VNA_Config.mdd
mdd
driver_mdd
drivers/VNA_Config_v1_0/data/VNA_Config.tcl
tclSource
driver_tcl
drivers/VNA_Config_v1_0/src/Makefile
driver_src
drivers/VNA_Config_v1_0/src/VNA_Config.h
cSource
driver_src
drivers/VNA_Config_v1_0/src/VNA_Config.c
cSource
driver_src
drivers/VNA_Config_v1_0/src/VNA_Config_selftest.c
cSource
driver_src
xilinx_xpgui_view_fileset
xgui/VNA_Config_v1_0.tcl
tclSource
CHECKSUM_beab2fb5
XGUI_VERSION_2
bd_tcl_view_fileset
bd/bd.tcl
tclSource
Configuration of VNA Peripheral
C_VNA_Config_AXI_DATA_WIDTH
C VNA Config AXI DATA WIDTH
Width of S_AXI data bus
32
false
C_VNA_Config_AXI_ADDR_WIDTH
C VNA Config AXI ADDR WIDTH
Width of S_AXI address bus
4
false
C_VNA_Config_AXI_BASEADDR
C VNA Config AXI BASEADDR
0xFFFFFFFF
false
C_VNA_Config_AXI_HIGHADDR
C VNA Config AXI HIGHADDR
0x00000000
false
C_S_AXI_INTR_DATA_WIDTH
C S AXI INTR DATA WIDTH
Width of S_AXI data bus
32
false
C_S_AXI_INTR_ADDR_WIDTH
C S AXI INTR ADDR WIDTH
Width of S_AXI address bus
5
false
C_NUM_OF_INTR
C NUM OF INTR
Number of Interrupts
1
C_INTR_SENSITIVITY
C INTR SENSITIVITY
Each bit corresponds to Sensitivity of interrupt : 0 - EDGE, 1 - LEVEL
0xFFFFFFFF
C_INTR_ACTIVE_STATE
C INTR ACTIVE STATE
Each bit corresponds to Sub-type of INTR: [0 - FALLING_EDGE, 1 - RISING_EDGE : if C_INTR_SENSITIVITY is EDGE(0)] and [ 0 - LEVEL_LOW, 1 - LEVEL_LOW : if C_INTR_SENSITIVITY is LEVEL(1) ]
0xFFFFFFFF
C_IRQ_SENSITIVITY
C IRQ SENSITIVITY
Sensitivity of IRQ: 0 - EDGE, 1 - LEVEL
1
C_IRQ_ACTIVE_STATE
C IRQ ACTIVE STATE
Sub-type of IRQ: [0 - FALLING_EDGE, 1 - RISING_EDGE : if C_IRQ_SENSITIVITY is EDGE(0)] and [ 0 - LEVEL_LOW, 1 - LEVEL_LOW : if C_IRQ_SENSITIVITY is LEVEL(1) ]
1
C_S_AXI_INTR_BASEADDR
C S AXI INTR BASEADDR
0xFFFFFFFF
false
C_S_AXI_INTR_HIGHADDR
C S AXI INTR HIGHADDR
0x00000000
false
Component_Name
VNA_Config_v1_0
zynq
AXI_Peripheral
VNA_Config_v1.0
3
2019-07-09T22:56:14Z
/home/nats/project/VNAV2_Zynq/IP/VNA_Config/VNA_Config_1.0
/home/nats/project/VNAV2_Zynq/IP/VNA_Config/VNA_Config_1.0
2017.4