diff --git a/IP/LTC2271_ADCGetter/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v b/IP/LTC2271_ADCGetter/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v index 871d23e38e379911b2a73e1e945cc10fc50c6e1b..86186246c6747f2bcdbb7e6a72e843ac960d1852 100644 --- a/IP/LTC2271_ADCGetter/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v +++ b/IP/LTC2271_ADCGetter/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v @@ -84,7 +84,36 @@ IBUFDS #(.DIFF_TERM("TRUE"),.IBUF_LOW_PWR("FALSE"),.IOSTANDARD("DEFAULT")) ADC_2B_BUF (.O(adc2b),.IB(AD_IN_2B_P),.I(AD_IN_2B_N)); IBUFDS #(.DIFF_TERM("TRUE"),.IBUF_LOW_PWR("FALSE"),.IOSTANDARD("DEFAULT")) ADC_2C_BUF (.O(adc2c),.IB(AD_IN_2C_P),.I(AD_IN_2C_N)); IBUFDS #(.DIFF_TERM("TRUE"),.IBUF_LOW_PWR("FALSE"),.IOSTANDARD("DEFAULT")) ADC_2D_BUF (.O(adc2d),.IB(AD_IN_2D_P),.I(AD_IN_2D_N)); - + + /* Extract data using IDDR -> don't forget delay */ + wire low_1a, high_1a, low_2a, high_2a, low_3a, high_3a, low_4a, high_4a; + wire low_1b, high_1b, low_2b, high_2b, low_3b, high_3b, low_4b, high_4b; + + /* Same Edge Pipelined mode add 1 latency cycle ! */ + IDDR #(.DDR_CLK_EDGE("SAME_EDGE_PIPELINED")) DDR_1A ( + .C(adc_dco), + .CE(1'b1), + .D(adc1a), + .Q1(low_1a), + .Q2(high_1a) + ); + + IDDR #(.DDR_CLK_EDGE("SAME_EDGE_PIPELINED")) DDR_2A ( + .C(adc_dco), + .CE(1'b1), + .D(adc2a), + .Q1(low_2a), + .Q2(high_2a) + ); + + IDDR #(.DDR_CLK_EDGE("SAME_EDGE_PIPELINED")) DDR_3A ( + .C(adc_dco), + .CE(1'b1), + .D(adc3a), + .Q1(low_3a), + .Q2(high_3a) + ); + /* Instantiate FIFO */ diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.cache/wt/gui_handlers.wdf b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.cache/wt/gui_handlers.wdf index dffb73b5baecd4ef090af8f23fd61e4184d295a2..446450777c56279116c04dca18e0e831d32bac64 100644 --- a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.cache/wt/gui_handlers.wdf +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.cache/wt/gui_handlers.wdf @@ -1,12 +1,12 @@ version:1 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index bb83a953f004f71a085e9d4a58a3b7e20cc6b65f..147a1ad3e3cee218fd6278295a0cf197a3abdb33 100644 --- a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.cache/wt/synthesis.wdf +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.cache/wt/synthesis.wdf @@ -33,7 +33,7 @@ version:1 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d617373657274:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d6e6f5f74696d696e675f64726976656e:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 73796e746865736973:73796e7468657369735c636f6d6d616e645f6c696e655f6f7074696f6e73:2d73666375:64656661756c743a3a5b6e6f745f7370656369666965645d:00:00 -73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313473:00:00 -73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313435372e3539344d42:00:00 +73796e746865736973:73796e7468657369735c7573616765:656c6170736564:30303a30303a313373:00:00 +73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f7065616b:313435372e3539304d42:00:00 73796e746865736973:73796e7468657369735c7573616765:6d656d6f72795f6761696e:3237392e3734324d42:00:00 -eof:3671629437 +eof:2835939642 diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.cache/wt/webtalk_pa.xml b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.cache/wt/webtalk_pa.xml index 3547a7b1c63614500c88308bd134af3699d403ca..e29adca77c793c4216c7acbef3c452916b9b87e8 100644 --- a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.cache/wt/webtalk_pa.xml +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.cache/wt/webtalk_pa.xml @@ -3,10 +3,10 @@ - +
- +
@@ -21,13 +21,14 @@ This means code written to parse this file will need to be revisited each subseq + - - + + @@ -36,13 +37,13 @@ This means code written to parse this file will need to be revisited each subseq - - + + - + @@ -53,7 +54,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -73,7 +74,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -88,13 +89,13 @@ This means code written to parse this file will need to be revisited each subseq - + - + - +
diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/.jobs/vrs_config_10.xml b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/.jobs/vrs_config_10.xml new file mode 100644 index 0000000000000000000000000000000000000000..65fc84c7489c29413da443ee8f4f622d53795170 --- /dev/null +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/.jobs/vrs_config_10.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/.jobs/vrs_config_11.xml b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/.jobs/vrs_config_11.xml new file mode 100644 index 0000000000000000000000000000000000000000..c9c0b7b8d034c286afbb9ef39903a713bc652b35 --- /dev/null +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/.jobs/vrs_config_11.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/fifo_generator_0_synth_1/gen_run.xml b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/fifo_generator_0_synth_1/gen_run.xml index 90b369eab7896382b4f834049217ec08ce515061..6c0e7f5a014c9950b1d095ea7382b5b43a201349 100644 --- a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/fifo_generator_0_synth_1/gen_run.xml +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/fifo_generator_0_synth_1/gen_run.xml @@ -1,7 +1,7 @@ - + diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/.init_design.begin.rst b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/.init_design.begin.rst index 3893d139c927d042f770999b165376d062580b20..92a342a659e790f5893666edd49dc6902507d500 100644 --- a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/.init_design.begin.rst +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/.init_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/.opt_design.begin.rst b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/.opt_design.begin.rst index 3893d139c927d042f770999b165376d062580b20..92a342a659e790f5893666edd49dc6902507d500 100644 --- a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/.opt_design.begin.rst +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/.opt_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/.place_design.begin.rst b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/.place_design.begin.rst index 3893d139c927d042f770999b165376d062580b20..92a342a659e790f5893666edd49dc6902507d500 100644 --- a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/.place_design.begin.rst +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/.place_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/.route_design.begin.rst b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/.route_design.begin.rst index 3893d139c927d042f770999b165376d062580b20..92a342a659e790f5893666edd49dc6902507d500 100644 --- a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/.route_design.begin.rst +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/.route_design.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/.vivado.begin.rst b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/.vivado.begin.rst index fb7e2943ddd204d84c9488aef4729b9b403b9b03..71f67869059114e784a4653de53815c963a58ba4 100644 --- a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/.vivado.begin.rst +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0.tcl b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0.tcl index bc4a9594dcd42371273b9586caf6fbdfb0b7cd22..6979422a66c4971c5d02c375d3cfc6c69caef40e 100644 --- a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0.tcl +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0.tcl @@ -60,8 +60,6 @@ proc step_failed { step } { close $ch } -set_msg_config -id {Synth 8-256} -limit 10000 -set_msg_config -id {Synth 8-638} -limit 10000 start_step init_design set ACTIVE_STEP init_design diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0.vdi b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0.vdi index 9369233ad9a699b9871f3a8174c36ccd87c9a9e9..153cee994caaa8359ec1c1ae6a52281ae9753979 100644 --- a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0.vdi +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0.vdi @@ -2,8 +2,8 @@ # Vivado v2017.4 (64-bit) # SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017 # IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 -# Start of session at: Tue Oct 8 19:27:32 2019 -# Process ID: 10378 +# Start of session at: Tue Oct 15 02:04:27 2019 +# Process ID: 16468 # Current directory: /home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1 # Command line: vivado -log LTC2271_SampleGetter_v1_0.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source LTC2271_SampleGetter_v1_0.tcl -notrace # Log file: /home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0.vdi @@ -13,7 +13,7 @@ source LTC2271_SampleGetter_v1_0.tcl -notrace Command: link_design -top LTC2271_SampleGetter_v1_0 -part xc7z010clg400-1 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 -INFO: [Netlist 29-17] Analyzing 19 Unisim elements for replacement +INFO: [Netlist 29-17] Analyzing 21 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2017.4 INFO: [Device 21-403] Loading part xc7z010clg400-1 @@ -24,7 +24,7 @@ No Unisim elements were transformed. 7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully -link_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:17 . Memory (MB): peak = 1445.273 ; gain = 263.418 ; free physical = 589 ; free virtual = 9588 +link_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:17 . Memory (MB): peak = 1445.273 ; gain = 263.418 ; free physical = 716 ; free virtual = 10751 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' @@ -35,7 +35,7 @@ INFO: [DRC 23-27] Running DRC with 4 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. -Time (s): cpu = 00:00:00.92 ; elapsed = 00:00:00.79 . Memory (MB): peak = 1495.289 ; gain = 50.016 ; free physical = 581 ; free virtual = 9581 +Time (s): cpu = 00:00:00.93 ; elapsed = 00:00:00.75 . Memory (MB): peak = 1495.289 ; gain = 50.016 ; free physical = 705 ; free virtual = 10739 INFO: [Timing 38-35] Done setting XDC timing constraints. Starting Logic Optimization Task @@ -43,52 +43,52 @@ Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: d7fef689 +Phase 1 Retarget | Checksum: 11a1103dc -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1935.781 ; gain = 0.000 ; free physical = 193 ; free virtual = 9197 +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1941.781 ; gain = 0.000 ; free physical = 334 ; free virtual = 10391 INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: d7fef689 +Phase 2 Constant propagation | Checksum: 11a1103dc -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1935.781 ; gain = 0.000 ; free physical = 193 ; free virtual = 9197 +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1941.781 ; gain = 0.000 ; free physical = 334 ; free virtual = 10391 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 3 Sweep -Phase 3 Sweep | Checksum: dd0768e1 +Phase 3 Sweep | Checksum: 1416cddf6 -Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1935.781 ; gain = 0.000 ; free physical = 193 ; free virtual = 9197 -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 10 cells +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1941.781 ; gain = 0.000 ; free physical = 334 ; free virtual = 10391 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 12 cells Phase 4 BUFG optimization -Phase 4 BUFG optimization | Checksum: dd0768e1 +Phase 4 BUFG optimization | Checksum: 1416cddf6 -Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1935.781 ; gain = 0.000 ; free physical = 193 ; free virtual = 9197 +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1941.781 ; gain = 0.000 ; free physical = 334 ; free virtual = 10391 INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells Phase 5 Shift Register Optimization -Phase 5 Shift Register Optimization | Checksum: dd0768e1 +Phase 5 Shift Register Optimization | Checksum: 1416cddf6 -Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1935.781 ; gain = 0.000 ; free physical = 193 ; free virtual = 9197 +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1941.781 ; gain = 0.000 ; free physical = 334 ; free virtual = 10391 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Starting Connectivity Check Task -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1935.781 ; gain = 0.000 ; free physical = 193 ; free virtual = 9197 -Ending Logic Optimization Task | Checksum: dd0768e1 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1941.781 ; gain = 0.000 ; free physical = 334 ; free virtual = 10391 +Ending Logic Optimization Task | Checksum: 1416cddf6 -Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1935.781 ; gain = 0.000 ; free physical = 193 ; free virtual = 9197 +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1941.781 ; gain = 0.000 ; free physical = 334 ; free virtual = 10391 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: 10f419eea +Ending Power Optimization Task | Checksum: 164b434d3 -Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1935.781 ; gain = 0.000 ; free physical = 193 ; free virtual = 9197 +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1941.781 ; gain = 0.000 ; free physical = 333 ; free virtual = 10391 INFO: [Common 17-83] Releasing license: Implementation 22 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully -opt_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 1935.781 ; gain = 490.508 ; free physical = 193 ; free virtual = 9197 +opt_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1941.781 ; gain = 496.508 ; free physical = 333 ; free virtual = 10391 INFO: [Common 17-1381] The checkpoint '/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_opt.dcp' has been generated. INFO: [runtcl-4] Executing : report_drc -file LTC2271_SampleGetter_v1_0_drc_opted.rpt -pb LTC2271_SampleGetter_v1_0_drc_opted.pb -rpx LTC2271_SampleGetter_v1_0_drc_opted.rpx Command: report_drc -file LTC2271_SampleGetter_v1_0_drc_opted.rpt -pb LTC2271_SampleGetter_v1_0_drc_opted.pb -rpx LTC2271_SampleGetter_v1_0_drc_opted.rpx @@ -143,105 +143,105 @@ INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1967.797 ; gain = 0.000 ; free physical = 181 ; free virtual = 9165 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1973.797 ; gain = 0.000 ; free physical = 301 ; free virtual = 10359 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 7a3346c4 -Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1967.797 ; gain = 0.000 ; free physical = 181 ; free virtual = 9165 +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1973.797 ; gain = 0.000 ; free physical = 301 ; free virtual = 10359 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1967.797 ; gain = 0.000 ; free physical = 187 ; free virtual = 9170 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1973.797 ; gain = 0.000 ; free physical = 301 ; free virtual = 10359 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 12799f854 +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 155e88f66 -Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1967.797 ; gain = 0.000 ; free physical = 183 ; free virtual = 9167 +Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1973.797 ; gain = 0.000 ; free physical = 266 ; free virtual = 10327 Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 19563683a +Phase 1.3 Build Placer Netlist Model | Checksum: 1c3b1ff4c -Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.30 . Memory (MB): peak = 1967.797 ; gain = 0.000 ; free physical = 183 ; free virtual = 9167 +Time (s): cpu = 00:00:00.60 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1973.797 ; gain = 0.000 ; free physical = 290 ; free virtual = 10352 Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 19563683a +Phase 1.4 Constrain Clocks/Macros | Checksum: 1c3b1ff4c -Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.30 . Memory (MB): peak = 1967.797 ; gain = 0.000 ; free physical = 183 ; free virtual = 9167 -Phase 1 Placer Initialization | Checksum: 19563683a +Time (s): cpu = 00:00:00.60 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1973.797 ; gain = 0.000 ; free physical = 290 ; free virtual = 10352 +Phase 1 Placer Initialization | Checksum: 1c3b1ff4c -Time (s): cpu = 00:00:00.60 ; elapsed = 00:00:00.30 . Memory (MB): peak = 1967.797 ; gain = 0.000 ; free physical = 183 ; free virtual = 9167 +Time (s): cpu = 00:00:00.61 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1973.797 ; gain = 0.000 ; free physical = 290 ; free virtual = 10352 Phase 2 Global Placement -Phase 2 Global Placement | Checksum: 21b75ead0 +Phase 2 Global Placement | Checksum: 249c481e2 -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2023.824 ; gain = 56.027 ; free physical = 179 ; free virtual = 9163 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.57 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 295 ; free virtual = 10358 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 21b75ead0 +Phase 3.1 Commit Multi Column Macros | Checksum: 249c481e2 -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2023.824 ; gain = 56.027 ; free physical = 179 ; free virtual = 9163 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.57 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 295 ; free virtual = 10358 Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: d20492c7 +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 137fd55f9 -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2023.824 ; gain = 56.027 ; free physical = 179 ; free virtual = 9163 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.58 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 295 ; free virtual = 10358 Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 100671bf7 +Phase 3.3 Area Swap Optimization | Checksum: 1665fdf29 -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2023.824 ; gain = 56.027 ; free physical = 179 ; free virtual = 9163 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.58 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 295 ; free virtual = 10358 Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 100671bf7 +Phase 3.4 Pipeline Register Optimization | Checksum: 1665fdf29 -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2023.824 ; gain = 56.027 ; free physical = 179 ; free virtual = 9163 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.58 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 295 ; free virtual = 10358 Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: 1e5fe1d07 +Phase 3.5 Small Shape Detail Placement | Checksum: 145f087de -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2023.824 ; gain = 56.027 ; free physical = 178 ; free virtual = 9162 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 293 ; free virtual = 10356 Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: 1e5fe1d07 +Phase 3.6 Re-assign LUT pins | Checksum: 145f087de -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2023.824 ; gain = 56.027 ; free physical = 178 ; free virtual = 9162 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 293 ; free virtual = 10356 Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: 1e5fe1d07 +Phase 3.7 Pipeline Register Optimization | Checksum: 145f087de -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2023.824 ; gain = 56.027 ; free physical = 178 ; free virtual = 9162 -Phase 3 Detail Placement | Checksum: 1e5fe1d07 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 293 ; free virtual = 10356 +Phase 3 Detail Placement | Checksum: 145f087de -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2023.824 ; gain = 56.027 ; free physical = 178 ; free virtual = 9162 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 293 ; free virtual = 10356 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization -Phase 4.1 Post Commit Optimization | Checksum: 1e5fe1d07 +Phase 4.1 Post Commit Optimization | Checksum: 145f087de -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2023.824 ; gain = 56.027 ; free physical = 178 ; free virtual = 9162 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 293 ; free virtual = 10356 Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 1e5fe1d07 +Phase 4.2 Post Placement Cleanup | Checksum: 145f087de -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2023.824 ; gain = 56.027 ; free physical = 179 ; free virtual = 9163 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 293 ; free virtual = 10356 Phase 4.3 Placer Reporting -Phase 4.3 Placer Reporting | Checksum: 1e5fe1d07 +Phase 4.3 Placer Reporting | Checksum: 145f087de -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2023.824 ; gain = 56.027 ; free physical = 179 ; free virtual = 9163 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.63 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 293 ; free virtual = 10356 Phase 4.4 Final Placement Cleanup -Phase 4.4 Final Placement Cleanup | Checksum: 1e5fe1d07 +Phase 4.4 Final Placement Cleanup | Checksum: 145f087de -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2023.824 ; gain = 56.027 ; free physical = 179 ; free virtual = 9163 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1e5fe1d07 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.63 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 293 ; free virtual = 10356 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 145f087de -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2023.824 ; gain = 56.027 ; free physical = 179 ; free virtual = 9163 -Ending Placer Task | Checksum: 159b9a35b +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.63 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 293 ; free virtual = 10356 +Ending Placer Task | Checksum: b9ac0e32 -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2023.824 ; gain = 56.027 ; free physical = 181 ; free virtual = 9165 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.63 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 296 ; free virtual = 10359 INFO: [Common 17-83] Releasing license: Implementation 44 Infos, 22 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully @@ -249,14 +249,14 @@ Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2023.824 ; gain = 0.000 ; free physical = 179 ; free virtual = 9165 +Write XDEF Complete: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2029.824 ; gain = 0.000 ; free physical = 294 ; free virtual = 10359 INFO: [Common 17-1381] The checkpoint '/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_placed.dcp' has been generated. INFO: [runtcl-4] Executing : report_io -file LTC2271_SampleGetter_v1_0_io_placed.rpt -report_io: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.15 . Memory (MB): peak = 2023.824 ; gain = 0.000 ; free physical = 196 ; free virtual = 9153 +report_io: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2029.824 ; gain = 0.000 ; free physical = 268 ; free virtual = 10332 INFO: [runtcl-4] Executing : report_utilization -file LTC2271_SampleGetter_v1_0_utilization_placed.rpt -pb LTC2271_SampleGetter_v1_0_utilization_placed.pb -report_utilization: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.10 . Memory (MB): peak = 2023.824 ; gain = 0.000 ; free physical = 205 ; free virtual = 9163 +report_utilization: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2029.824 ; gain = 0.000 ; free physical = 267 ; free virtual = 10331 INFO: [runtcl-4] Executing : report_control_sets -verbose -file LTC2271_SampleGetter_v1_0_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.10 . Memory (MB): peak = 2023.824 ; gain = 0.000 ; free physical = 205 ; free virtual = 9162 +report_control_sets: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2029.824 ; gain = 0.000 ; free physical = 267 ; free virtual = 10331 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' @@ -288,61 +288,61 @@ INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more in Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs -Checksum: PlaceDB: df865c97 ConstDB: 0 ShapeSum: 7a3346c4 RouteDB: 0 +Checksum: PlaceDB: 3f78c76e ConstDB: 0 ShapeSum: 7a3346c4 RouteDB: 0 Phase 1 Build RT Design -Phase 1 Build RT Design | Checksum: 935836da +Phase 1 Build RT Design | Checksum: de37470a -Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2048.812 ; gain = 24.988 ; free physical = 176 ; free virtual = 9079 -Post Restoration Checksum: NetGraph: 3b924642 NumContArr: 57c5f098 Constraints: 0 Timing: 0 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2051.812 ; gain = 21.988 ; free physical = 198 ; free virtual = 10262 +Post Restoration Checksum: NetGraph: 23d02fed NumContArr: ba67171d Constraints: 0 Timing: 0 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints -Phase 2.1 Fix Topology Constraints | Checksum: 935836da +Phase 2.1 Fix Topology Constraints | Checksum: de37470a -Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2062.812 ; gain = 38.988 ; free physical = 162 ; free virtual = 9065 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2065.812 ; gain = 35.988 ; free physical = 183 ; free virtual = 10248 Phase 2.2 Pre Route Cleanup -Phase 2.2 Pre Route Cleanup | Checksum: 935836da +Phase 2.2 Pre Route Cleanup | Checksum: de37470a -Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2062.812 ; gain = 38.988 ; free physical = 162 ; free virtual = 9065 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2065.812 ; gain = 35.988 ; free physical = 183 ; free virtual = 10248 Number of Nodes with overlaps = 0 -Phase 2 Router Initialization | Checksum: 13a2040af +Phase 2 Router Initialization | Checksum: d0d39c49 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2067.812 ; gain = 43.988 ; free physical = 157 ; free virtual = 9060 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2070.812 ; gain = 40.988 ; free physical = 177 ; free virtual = 10242 Phase 3 Initial Routing -Phase 3 Initial Routing | Checksum: db222f30 +Phase 3 Initial Routing | Checksum: 113154229 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2067.812 ; gain = 43.988 ; free physical = 158 ; free virtual = 9061 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2070.812 ; gain = 40.988 ; free physical = 177 ; free virtual = 10242 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 0 -Phase 4.1 Global Iteration 0 | Checksum: faf6e8b1 +Phase 4.1 Global Iteration 0 | Checksum: 16ca5cd1d -Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2067.812 ; gain = 43.988 ; free physical = 158 ; free virtual = 9061 -Phase 4 Rip-up And Reroute | Checksum: faf6e8b1 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2070.812 ; gain = 40.988 ; free physical = 177 ; free virtual = 10242 +Phase 4 Rip-up And Reroute | Checksum: 16ca5cd1d -Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2067.812 ; gain = 43.988 ; free physical = 158 ; free virtual = 9061 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2070.812 ; gain = 40.988 ; free physical = 177 ; free virtual = 10242 Phase 5 Delay and Skew Optimization -Phase 5 Delay and Skew Optimization | Checksum: faf6e8b1 +Phase 5 Delay and Skew Optimization | Checksum: 16ca5cd1d -Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2067.812 ; gain = 43.988 ; free physical = 158 ; free virtual = 9061 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2070.812 ; gain = 40.988 ; free physical = 177 ; free virtual = 10242 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter -Phase 6.1 Hold Fix Iter | Checksum: faf6e8b1 +Phase 6.1 Hold Fix Iter | Checksum: 16ca5cd1d -Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2067.812 ; gain = 43.988 ; free physical = 158 ; free virtual = 9061 -Phase 6 Post Hold Fix | Checksum: faf6e8b1 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2070.812 ; gain = 40.988 ; free physical = 177 ; free virtual = 10242 +Phase 6 Post Hold Fix | Checksum: 16ca5cd1d -Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2067.812 ; gain = 43.988 ; free physical = 158 ; free virtual = 9061 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2070.812 ; gain = 40.988 ; free physical = 177 ; free virtual = 10242 Phase 7 Route finalize @@ -363,35 +363,35 @@ North Dir 1x1 Area, Max Cong = 26.1261%, No Congested Regions. South Dir 1x1 Area, Max Cong = 32.4324%, No Congested Regions. East Dir 1x1 Area, Max Cong = 10.2941%, No Congested Regions. West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. -Phase 7 Route finalize | Checksum: faf6e8b1 +Phase 7 Route finalize | Checksum: 16ca5cd1d -Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2067.812 ; gain = 43.988 ; free physical = 158 ; free virtual = 9061 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2070.812 ; gain = 40.988 ; free physical = 177 ; free virtual = 10242 Phase 8 Verifying routed nets Verification completed successfully -Phase 8 Verifying routed nets | Checksum: faf6e8b1 +Phase 8 Verifying routed nets | Checksum: 16ca5cd1d -Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2069.812 ; gain = 45.988 ; free physical = 157 ; free virtual = 9060 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2072.812 ; gain = 42.988 ; free physical = 176 ; free virtual = 10241 Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 6b619e79 +Phase 9 Depositing Routes | Checksum: 1a9e23637 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2069.812 ; gain = 45.988 ; free physical = 157 ; free virtual = 9060 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2072.812 ; gain = 42.988 ; free physical = 176 ; free virtual = 10241 INFO: [Route 35-16] Router Completed Successfully -Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2069.812 ; gain = 45.988 ; free physical = 172 ; free virtual = 9076 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2072.812 ; gain = 42.988 ; free physical = 192 ; free virtual = 10257 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 56 Infos, 42 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully -route_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2069.812 ; gain = 45.988 ; free physical = 172 ; free virtual = 9075 +route_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2072.812 ; gain = 42.988 ; free physical = 192 ; free virtual = 10257 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2069.812 ; gain = 0.000 ; free physical = 171 ; free virtual = 9076 +Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2072.812 ; gain = 0.000 ; free physical = 192 ; free virtual = 10258 INFO: [Common 17-1381] The checkpoint '/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_routed.dcp' has been generated. INFO: [runtcl-4] Executing : report_drc -file LTC2271_SampleGetter_v1_0_drc_routed.rpt -pb LTC2271_SampleGetter_v1_0_drc_routed.pb -rpx LTC2271_SampleGetter_v1_0_drc_routed.rpx Command: report_drc -file LTC2271_SampleGetter_v1_0_drc_routed.rpt -pb LTC2271_SampleGetter_v1_0_drc_routed.pb -rpx LTC2271_SampleGetter_v1_0_drc_routed.rpx @@ -424,4 +424,4 @@ WARNING: [Timing 38-313] There are no user specified timing constraints. Timing INFO: [runtcl-4] Executing : report_incremental_reuse -file LTC2271_SampleGetter_v1_0_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. INFO: [runtcl-4] Executing : report_clock_utilization -file LTC2271_SampleGetter_v1_0_clock_utilization_routed.rpt -INFO: [Common 17-206] Exiting Vivado at Tue Oct 8 19:28:29 2019... +INFO: [Common 17-206] Exiting Vivado at Tue Oct 15 02:05:21 2019... diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_clock_utilization_routed.rpt b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_clock_utilization_routed.rpt index cf66f353cd7f4dde72f569adfed8349cb0bcfdc6..ebc69e268d4cdca5dc231c785b14b0d6e85dda91 100644 --- a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_clock_utilization_routed.rpt +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_clock_utilization_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 -| Date : Tue Oct 8 19:28:29 2019 +| Date : Tue Oct 15 02:05:21 2019 | Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS | Command : report_clock_utilization -file LTC2271_SampleGetter_v1_0_clock_utilization_routed.rpt | Design : LTC2271_SampleGetter_v1_0 diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_control_sets_placed.rpt b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_control_sets_placed.rpt index 3f445df20b6920e52c9d1ab55adb889cbd63cb87..d0634c3d024a5af728a8a82a36798b9eefe59cf8 100644 --- a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_control_sets_placed.rpt +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_control_sets_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------ | Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 -| Date : Tue Oct 8 19:28:18 2019 +| Date : Tue Oct 15 02:05:11 2019 | Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS | Command : report_control_sets -verbose -file LTC2271_SampleGetter_v1_0_control_sets_placed.rpt | Design : LTC2271_SampleGetter_v1_0 diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_drc_opted.rpt b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_drc_opted.rpt index bc01eb290e8ddedc8f977aa533c53d6de960d23e..4f70f8c08b2bbba88c237984d399ba14c8537b79 100644 --- a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_drc_opted.rpt +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_drc_opted.rpt @@ -1,7 +1,7 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------------------------ | Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 -| Date : Tue Oct 8 19:28:16 2019 +| Date : Tue Oct 15 02:05:09 2019 | Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS | Command : report_drc -file LTC2271_SampleGetter_v1_0_drc_opted.rpt -pb LTC2271_SampleGetter_v1_0_drc_opted.pb -rpx LTC2271_SampleGetter_v1_0_drc_opted.rpx | Design : LTC2271_SampleGetter_v1_0 diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_drc_opted.rpx b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_drc_opted.rpx index 43076727e2a3778cdad76e954c6ddb33758eebcc..ed7c8b0572060a9211c8aa121c959f14df4d9c18 100644 Binary files a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_drc_opted.rpx and b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_drc_opted.rpx differ diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_drc_routed.rpt b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_drc_routed.rpt index e5e6186e824d645d00ec09190e40e57958bd31a7..ef802e130b59f892cfa4b7799ae56db4a96583e4 100644 --- a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_drc_routed.rpt +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_drc_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 -| Date : Tue Oct 8 19:28:27 2019 +| Date : Tue Oct 15 02:05:19 2019 | Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS | Command : report_drc -file LTC2271_SampleGetter_v1_0_drc_routed.rpt -pb LTC2271_SampleGetter_v1_0_drc_routed.pb -rpx LTC2271_SampleGetter_v1_0_drc_routed.rpx | Design : LTC2271_SampleGetter_v1_0 diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_drc_routed.rpx b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_drc_routed.rpx index 6887052f8705effe62d5388e2909e611ef28b085..0f369a604db92d9bb166a9cdc5db8ae46bb114bc 100644 Binary files a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_drc_routed.rpx and b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_drc_routed.rpx differ diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_io_placed.rpt b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_io_placed.rpt index 83005b67d420905e0282eacb7ca5b8ceb344edaa..a55e98e8fcfc02a929ee4521831f028a73978f03 100644 --- a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_io_placed.rpt +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_io_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 -| Date : Tue Oct 8 19:28:18 2019 +| Date : Tue Oct 15 02:05:11 2019 | Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS | Command : report_io -file LTC2271_SampleGetter_v1_0_io_placed.rpt | Design : LTC2271_SampleGetter_v1_0 @@ -328,7 +328,7 @@ Table of Contents | R11 | | Dedicated | DONE_0 | Config | | 0 | | | | | | | | | | | | | | | R12 | | | GND | GND | | | | | | | 0.0 | | | | | | | | | | R13 | | | VCCINT | VCCINT | | | | | | | | | | | | | | | | -| R14 | m00_axis_tlast | High Range | IO_L6N_T0_VREF_34 | TRISTATE | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | +| R14 | m00_axis_tlast | High Range | IO_L6N_T0_VREF_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | | R15 | | High Range | VCCO_34 | VCCO | | 34 | | | | | 1.80 | | | | | | | | | | R16 | m00_axis_tdata[12] | High Range | IO_L19P_T3_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | | R17 | m00_axis_tdata[11] | High Range | IO_L19N_T3_VREF_34 | OUTPUT | LVCMOS18* | 34 | 12 | SLOW | | FP_VTT_50 | | UNFIXED | | | | NONE | | | | diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_methodology_drc_routed.rpt b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_methodology_drc_routed.rpt index adf5da92f4731066e1d506ca01facc5440d6d719..2b53ee2ad4edf8ad26cb3685494ed9b9bb94acbd 100644 --- a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_methodology_drc_routed.rpt +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_methodology_drc_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 -| Date : Tue Oct 8 19:28:28 2019 +| Date : Tue Oct 15 02:05:20 2019 | Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS | Command : report_methodology -file LTC2271_SampleGetter_v1_0_methodology_drc_routed.rpt -pb LTC2271_SampleGetter_v1_0_methodology_drc_routed.pb -rpx LTC2271_SampleGetter_v1_0_methodology_drc_routed.rpx | Design : LTC2271_SampleGetter_v1_0 diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_methodology_drc_routed.rpx b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_methodology_drc_routed.rpx index 5ed883d33612de8e0edbccc41457f29186226f87..dfa182498ee33da58678212694342fb2cff4b0a2 100644 Binary files a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_methodology_drc_routed.rpx and b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_methodology_drc_routed.rpx differ diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_opt.dcp b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_opt.dcp index 03493081414c07b394920bd2fb254d1c68ab2bd2..9114664fe03d67c45fd211d43e8f1cc3881843ba 100644 Binary files a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_opt.dcp and b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_opt.dcp differ diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_placed.dcp b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_placed.dcp index 6e270f2e12c52263cf64ff0fc428d4bc174f9a0f..d25e774972b9f8609307188e7c27f836bb098fc1 100644 Binary files a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_placed.dcp and b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_placed.dcp differ diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_power_routed.rpt b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_power_routed.rpt index 5d696ad4d3de52d92fe83bf0638de787c30718aa..acaf1836592bf977ff1a5a8aec450cafe0c7f2b4 100644 --- a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_power_routed.rpt +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_power_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 -| Date : Tue Oct 8 19:28:29 2019 +| Date : Tue Oct 15 02:05:21 2019 | Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS | Command : report_power -file LTC2271_SampleGetter_v1_0_power_routed.rpt -pb LTC2271_SampleGetter_v1_0_power_summary_routed.pb -rpx LTC2271_SampleGetter_v1_0_power_routed.rpx | Design : LTC2271_SampleGetter_v1_0 diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_power_routed.rpx b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_power_routed.rpx index 7c9bc086e99d259d957150f9f1e1adc3ed6ababc..dc2252d5dc43d5e42cae6049776a27a56a4c46ef 100644 Binary files a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_power_routed.rpx and b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_power_routed.rpx differ diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_routed.dcp b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_routed.dcp index 6973586d3bff413c3f00ca063a718fd27ca65ef2..b41db44b24258f51a1d7d69e3a4515468fba2daa 100644 Binary files a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_routed.dcp and b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_routed.dcp differ diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_timing_summary_routed.rpt b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_timing_summary_routed.rpt index 4ddf8438d0aa2de228ebf4e82ec87de235739775..40e39ccd296d6edf4c3e281fa66ad1f7ffa672cf 100644 --- a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_timing_summary_routed.rpt +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_timing_summary_routed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 -| Date : Tue Oct 8 19:28:29 2019 +| Date : Tue Oct 15 02:05:21 2019 | Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS | Command : report_timing_summary -max_paths 10 -file LTC2271_SampleGetter_v1_0_timing_summary_routed.rpt -rpx LTC2271_SampleGetter_v1_0_timing_summary_routed.rpx -warn_on_violation | Design : LTC2271_SampleGetter_v1_0 diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_timing_summary_routed.rpx b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_timing_summary_routed.rpx index eff13dc2c856e182c6af78b3ddcb67e9f4810cd9..475253bfdf19dc24bd396d890476c7dec078855c 100644 Binary files a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_timing_summary_routed.rpx and b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_timing_summary_routed.rpx differ diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_utilization_placed.rpt b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_utilization_placed.rpt index fd14dc05e927c43fd54c723d96d6eef95d79f259..9108879d35320574dd448a987e69c8ca43bd7df3 100644 --- a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_utilization_placed.rpt +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_utilization_placed.rpt @@ -1,7 +1,7 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. ----------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 -| Date : Tue Oct 8 19:28:18 2019 +| Date : Tue Oct 15 02:05:11 2019 | Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS | Command : report_utilization -file LTC2271_SampleGetter_v1_0_utilization_placed.rpt -pb LTC2271_SampleGetter_v1_0_utilization_placed.pb | Design : LTC2271_SampleGetter_v1_0 @@ -174,9 +174,8 @@ Table of Contents | Ref Name | Used | Functional Category | +----------+------+---------------------+ | FDRE | 64 | Flop & Latch | -| OBUF | 37 | IO | +| OBUF | 38 | IO | | CARRY4 | 8 | CarryLogic | -| OBUFT | 1 | IO | | LUT1 | 1 | LUT | | IBUF | 1 | IO | | BUFG | 1 | Clock | diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/gen_run.xml b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/gen_run.xml index 8e47e2b40683fd5524033557eedb2522e77dbb82..3f3949fc8884767427f12e6288cabf32e6139cd5 100644 --- a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/gen_run.xml +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/gen_run.xml @@ -1,5 +1,5 @@ - + diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/init_design.pb b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/init_design.pb index 86dde0acfc83fd24b6f7820a53a2b7eb105ad106..9a0bea1ead638f6238962731f302e0f602cca0a4 100644 Binary files a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/init_design.pb and b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/init_design.pb differ diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/opt_design.pb b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/opt_design.pb index 29eb0d82d21068cfd8d554c36b48c02b768ccb5e..343aedb1d10a8741f79ccbfe33b7ad2189738993 100644 Binary files a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/opt_design.pb and b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/opt_design.pb differ diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/place_design.pb b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/place_design.pb index 16920999ab64158e63940b351cc51ef4599d3ffe..467dbeb42bc72cd61787d18e92bfd013d947ef17 100644 Binary files a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/place_design.pb and b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/place_design.pb differ diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/route_design.pb b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/route_design.pb index d6b4a62994b05ace1e1c59ba4cab7e6f62735207..244e5272dd6cb9a7eed67dbc446f94120bf88b12 100644 Binary files a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/route_design.pb and b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/route_design.pb differ diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/runme.log b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/runme.log index ac73a55c44ca18b8f5c52f85106a3f8ed18c2857..f72347e8ab52e559e2f80bf6c346a19998708f05 100644 --- a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/runme.log +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/runme.log @@ -12,7 +12,7 @@ source LTC2271_SampleGetter_v1_0.tcl -notrace Command: link_design -top LTC2271_SampleGetter_v1_0 -part xc7z010clg400-1 Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 -INFO: [Netlist 29-17] Analyzing 19 Unisim elements for replacement +INFO: [Netlist 29-17] Analyzing 21 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-479] Netlist was created with Vivado 2017.4 INFO: [Device 21-403] Loading part xc7z010clg400-1 @@ -23,7 +23,7 @@ No Unisim elements were transformed. 7 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. link_design completed successfully -link_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:17 . Memory (MB): peak = 1445.273 ; gain = 263.418 ; free physical = 589 ; free virtual = 9588 +link_design: Time (s): cpu = 00:00:08 ; elapsed = 00:00:17 . Memory (MB): peak = 1445.273 ; gain = 263.418 ; free physical = 716 ; free virtual = 10751 Command: opt_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' @@ -34,7 +34,7 @@ INFO: [DRC 23-27] Running DRC with 4 threads INFO: [Project 1-461] DRC finished with 0 Errors INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information. -Time (s): cpu = 00:00:00.92 ; elapsed = 00:00:00.79 . Memory (MB): peak = 1495.289 ; gain = 50.016 ; free physical = 581 ; free virtual = 9581 +Time (s): cpu = 00:00:00.93 ; elapsed = 00:00:00.75 . Memory (MB): peak = 1495.289 ; gain = 50.016 ; free physical = 705 ; free virtual = 10739 INFO: [Timing 38-35] Done setting XDC timing constraints. Starting Logic Optimization Task @@ -42,52 +42,52 @@ Starting Logic Optimization Task Phase 1 Retarget INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). INFO: [Opt 31-49] Retargeted 0 cell(s). -Phase 1 Retarget | Checksum: d7fef689 +Phase 1 Retarget | Checksum: 11a1103dc -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1935.781 ; gain = 0.000 ; free physical = 193 ; free virtual = 9197 +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1941.781 ; gain = 0.000 ; free physical = 334 ; free virtual = 10391 INFO: [Opt 31-389] Phase Retarget created 0 cells and removed 0 cells Phase 2 Constant propagation INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Phase 2 Constant propagation | Checksum: d7fef689 +Phase 2 Constant propagation | Checksum: 11a1103dc -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1935.781 ; gain = 0.000 ; free physical = 193 ; free virtual = 9197 +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1941.781 ; gain = 0.000 ; free physical = 334 ; free virtual = 10391 INFO: [Opt 31-389] Phase Constant propagation created 0 cells and removed 0 cells Phase 3 Sweep -Phase 3 Sweep | Checksum: dd0768e1 +Phase 3 Sweep | Checksum: 1416cddf6 -Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1935.781 ; gain = 0.000 ; free physical = 193 ; free virtual = 9197 -INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 10 cells +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1941.781 ; gain = 0.000 ; free physical = 334 ; free virtual = 10391 +INFO: [Opt 31-389] Phase Sweep created 0 cells and removed 12 cells Phase 4 BUFG optimization -Phase 4 BUFG optimization | Checksum: dd0768e1 +Phase 4 BUFG optimization | Checksum: 1416cddf6 -Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1935.781 ; gain = 0.000 ; free physical = 193 ; free virtual = 9197 +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1941.781 ; gain = 0.000 ; free physical = 334 ; free virtual = 10391 INFO: [Opt 31-389] Phase BUFG optimization created 0 cells and removed 0 cells Phase 5 Shift Register Optimization -Phase 5 Shift Register Optimization | Checksum: dd0768e1 +Phase 5 Shift Register Optimization | Checksum: 1416cddf6 -Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1935.781 ; gain = 0.000 ; free physical = 193 ; free virtual = 9197 +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1941.781 ; gain = 0.000 ; free physical = 334 ; free virtual = 10391 INFO: [Opt 31-389] Phase Shift Register Optimization created 0 cells and removed 0 cells Starting Connectivity Check Task -Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1935.781 ; gain = 0.000 ; free physical = 193 ; free virtual = 9197 -Ending Logic Optimization Task | Checksum: dd0768e1 +Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1941.781 ; gain = 0.000 ; free physical = 334 ; free virtual = 10391 +Ending Logic Optimization Task | Checksum: 1416cddf6 -Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1935.781 ; gain = 0.000 ; free physical = 193 ; free virtual = 9197 +Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1941.781 ; gain = 0.000 ; free physical = 334 ; free virtual = 10391 Starting Power Optimization Task INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 2.00 ns. -Ending Power Optimization Task | Checksum: 10f419eea +Ending Power Optimization Task | Checksum: 164b434d3 -Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1935.781 ; gain = 0.000 ; free physical = 193 ; free virtual = 9197 +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.02 . Memory (MB): peak = 1941.781 ; gain = 0.000 ; free physical = 333 ; free virtual = 10391 INFO: [Common 17-83] Releasing license: Implementation 22 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered. opt_design completed successfully -opt_design: Time (s): cpu = 00:00:10 ; elapsed = 00:00:17 . Memory (MB): peak = 1935.781 ; gain = 490.508 ; free physical = 193 ; free virtual = 9197 +opt_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:16 . Memory (MB): peak = 1941.781 ; gain = 496.508 ; free physical = 333 ; free virtual = 10391 INFO: [Common 17-1381] The checkpoint '/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_opt.dcp' has been generated. INFO: [runtcl-4] Executing : report_drc -file LTC2271_SampleGetter_v1_0_drc_opted.rpt -pb LTC2271_SampleGetter_v1_0_drc_opted.pb -rpx LTC2271_SampleGetter_v1_0_drc_opted.rpx Command: report_drc -file LTC2271_SampleGetter_v1_0_drc_opted.rpt -pb LTC2271_SampleGetter_v1_0_drc_opted.pb -rpx LTC2271_SampleGetter_v1_0_drc_opted.rpx @@ -142,105 +142,105 @@ INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of Phase 1 Placer Initialization Phase 1.1 Placer Initialization Netlist Sorting -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1967.797 ; gain = 0.000 ; free physical = 181 ; free virtual = 9165 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1973.797 ; gain = 0.000 ; free physical = 301 ; free virtual = 10359 Phase 1.1 Placer Initialization Netlist Sorting | Checksum: 7a3346c4 -Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00 . Memory (MB): peak = 1967.797 ; gain = 0.000 ; free physical = 181 ; free virtual = 9165 +Time (s): cpu = 00:00:00.01 ; elapsed = 00:00:00.01 . Memory (MB): peak = 1973.797 ; gain = 0.000 ; free physical = 301 ; free virtual = 10359 INFO: [Timing 38-35] Done setting XDC timing constraints. INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). -Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1967.797 ; gain = 0.000 ; free physical = 187 ; free virtual = 9170 +Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1973.797 ; gain = 0.000 ; free physical = 301 ; free virtual = 10359 Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device INFO: [Timing 38-35] Done setting XDC timing constraints. -Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 12799f854 +Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 155e88f66 -Time (s): cpu = 00:00:00.53 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1967.797 ; gain = 0.000 ; free physical = 183 ; free virtual = 9167 +Time (s): cpu = 00:00:00.51 ; elapsed = 00:00:00.24 . Memory (MB): peak = 1973.797 ; gain = 0.000 ; free physical = 266 ; free virtual = 10327 Phase 1.3 Build Placer Netlist Model -Phase 1.3 Build Placer Netlist Model | Checksum: 19563683a +Phase 1.3 Build Placer Netlist Model | Checksum: 1c3b1ff4c -Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.30 . Memory (MB): peak = 1967.797 ; gain = 0.000 ; free physical = 183 ; free virtual = 9167 +Time (s): cpu = 00:00:00.60 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1973.797 ; gain = 0.000 ; free physical = 290 ; free virtual = 10352 Phase 1.4 Constrain Clocks/Macros -Phase 1.4 Constrain Clocks/Macros | Checksum: 19563683a +Phase 1.4 Constrain Clocks/Macros | Checksum: 1c3b1ff4c -Time (s): cpu = 00:00:00.59 ; elapsed = 00:00:00.30 . Memory (MB): peak = 1967.797 ; gain = 0.000 ; free physical = 183 ; free virtual = 9167 -Phase 1 Placer Initialization | Checksum: 19563683a +Time (s): cpu = 00:00:00.60 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1973.797 ; gain = 0.000 ; free physical = 290 ; free virtual = 10352 +Phase 1 Placer Initialization | Checksum: 1c3b1ff4c -Time (s): cpu = 00:00:00.60 ; elapsed = 00:00:00.30 . Memory (MB): peak = 1967.797 ; gain = 0.000 ; free physical = 183 ; free virtual = 9167 +Time (s): cpu = 00:00:00.61 ; elapsed = 00:00:00.27 . Memory (MB): peak = 1973.797 ; gain = 0.000 ; free physical = 290 ; free virtual = 10352 Phase 2 Global Placement -Phase 2 Global Placement | Checksum: 21b75ead0 +Phase 2 Global Placement | Checksum: 249c481e2 -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2023.824 ; gain = 56.027 ; free physical = 179 ; free virtual = 9163 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.57 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 295 ; free virtual = 10358 Phase 3 Detail Placement Phase 3.1 Commit Multi Column Macros -Phase 3.1 Commit Multi Column Macros | Checksum: 21b75ead0 +Phase 3.1 Commit Multi Column Macros | Checksum: 249c481e2 -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2023.824 ; gain = 56.027 ; free physical = 179 ; free virtual = 9163 +Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.57 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 295 ; free virtual = 10358 Phase 3.2 Commit Most Macros & LUTRAMs -Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: d20492c7 +Phase 3.2 Commit Most Macros & LUTRAMs | Checksum: 137fd55f9 -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2023.824 ; gain = 56.027 ; free physical = 179 ; free virtual = 9163 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.58 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 295 ; free virtual = 10358 Phase 3.3 Area Swap Optimization -Phase 3.3 Area Swap Optimization | Checksum: 100671bf7 +Phase 3.3 Area Swap Optimization | Checksum: 1665fdf29 -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2023.824 ; gain = 56.027 ; free physical = 179 ; free virtual = 9163 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.58 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 295 ; free virtual = 10358 Phase 3.4 Pipeline Register Optimization -Phase 3.4 Pipeline Register Optimization | Checksum: 100671bf7 +Phase 3.4 Pipeline Register Optimization | Checksum: 1665fdf29 -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2023.824 ; gain = 56.027 ; free physical = 179 ; free virtual = 9163 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.58 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 295 ; free virtual = 10358 Phase 3.5 Small Shape Detail Placement -Phase 3.5 Small Shape Detail Placement | Checksum: 1e5fe1d07 +Phase 3.5 Small Shape Detail Placement | Checksum: 145f087de -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2023.824 ; gain = 56.027 ; free physical = 178 ; free virtual = 9162 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 293 ; free virtual = 10356 Phase 3.6 Re-assign LUT pins -Phase 3.6 Re-assign LUT pins | Checksum: 1e5fe1d07 +Phase 3.6 Re-assign LUT pins | Checksum: 145f087de -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2023.824 ; gain = 56.027 ; free physical = 178 ; free virtual = 9162 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 293 ; free virtual = 10356 Phase 3.7 Pipeline Register Optimization -Phase 3.7 Pipeline Register Optimization | Checksum: 1e5fe1d07 +Phase 3.7 Pipeline Register Optimization | Checksum: 145f087de -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2023.824 ; gain = 56.027 ; free physical = 178 ; free virtual = 9162 -Phase 3 Detail Placement | Checksum: 1e5fe1d07 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 293 ; free virtual = 10356 +Phase 3 Detail Placement | Checksum: 145f087de -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2023.824 ; gain = 56.027 ; free physical = 178 ; free virtual = 9162 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 293 ; free virtual = 10356 Phase 4 Post Placement Optimization and Clean-Up Phase 4.1 Post Commit Optimization -Phase 4.1 Post Commit Optimization | Checksum: 1e5fe1d07 +Phase 4.1 Post Commit Optimization | Checksum: 145f087de -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2023.824 ; gain = 56.027 ; free physical = 178 ; free virtual = 9162 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 293 ; free virtual = 10356 Phase 4.2 Post Placement Cleanup -Phase 4.2 Post Placement Cleanup | Checksum: 1e5fe1d07 +Phase 4.2 Post Placement Cleanup | Checksum: 145f087de -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2023.824 ; gain = 56.027 ; free physical = 179 ; free virtual = 9163 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.62 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 293 ; free virtual = 10356 Phase 4.3 Placer Reporting -Phase 4.3 Placer Reporting | Checksum: 1e5fe1d07 +Phase 4.3 Placer Reporting | Checksum: 145f087de -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2023.824 ; gain = 56.027 ; free physical = 179 ; free virtual = 9163 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.63 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 293 ; free virtual = 10356 Phase 4.4 Final Placement Cleanup -Phase 4.4 Final Placement Cleanup | Checksum: 1e5fe1d07 +Phase 4.4 Final Placement Cleanup | Checksum: 145f087de -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2023.824 ; gain = 56.027 ; free physical = 179 ; free virtual = 9163 -Phase 4 Post Placement Optimization and Clean-Up | Checksum: 1e5fe1d07 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.63 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 293 ; free virtual = 10356 +Phase 4 Post Placement Optimization and Clean-Up | Checksum: 145f087de -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2023.824 ; gain = 56.027 ; free physical = 179 ; free virtual = 9163 -Ending Placer Task | Checksum: 159b9a35b +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.63 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 293 ; free virtual = 10356 +Ending Placer Task | Checksum: b9ac0e32 -Time (s): cpu = 00:00:03 ; elapsed = 00:00:01 . Memory (MB): peak = 2023.824 ; gain = 56.027 ; free physical = 181 ; free virtual = 9165 +Time (s): cpu = 00:00:02 ; elapsed = 00:00:00.63 . Memory (MB): peak = 2029.824 ; gain = 56.027 ; free physical = 296 ; free virtual = 10359 INFO: [Common 17-83] Releasing license: Implementation 44 Infos, 22 Warnings, 0 Critical Warnings and 0 Errors encountered. place_design completed successfully @@ -248,14 +248,14 @@ Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2023.824 ; gain = 0.000 ; free physical = 179 ; free virtual = 9165 +Write XDEF Complete: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2029.824 ; gain = 0.000 ; free physical = 294 ; free virtual = 10359 INFO: [Common 17-1381] The checkpoint '/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_placed.dcp' has been generated. INFO: [runtcl-4] Executing : report_io -file LTC2271_SampleGetter_v1_0_io_placed.rpt -report_io: Time (s): cpu = 00:00:00.10 ; elapsed = 00:00:00.15 . Memory (MB): peak = 2023.824 ; gain = 0.000 ; free physical = 196 ; free virtual = 9153 +report_io: Time (s): cpu = 00:00:00.14 ; elapsed = 00:00:00.16 . Memory (MB): peak = 2029.824 ; gain = 0.000 ; free physical = 268 ; free virtual = 10332 INFO: [runtcl-4] Executing : report_utilization -file LTC2271_SampleGetter_v1_0_utilization_placed.rpt -pb LTC2271_SampleGetter_v1_0_utilization_placed.pb -report_utilization: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.10 . Memory (MB): peak = 2023.824 ; gain = 0.000 ; free physical = 205 ; free virtual = 9163 +report_utilization: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2029.824 ; gain = 0.000 ; free physical = 267 ; free virtual = 10331 INFO: [runtcl-4] Executing : report_control_sets -verbose -file LTC2271_SampleGetter_v1_0_control_sets_placed.rpt -report_control_sets: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.10 . Memory (MB): peak = 2023.824 ; gain = 0.000 ; free physical = 205 ; free virtual = 9162 +report_control_sets: Time (s): cpu = 00:00:00.07 ; elapsed = 00:00:00.11 . Memory (MB): peak = 2029.824 ; gain = 0.000 ; free physical = 267 ; free virtual = 10331 Command: route_design Attempting to get a license for feature 'Implementation' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z010' @@ -287,61 +287,61 @@ INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more in Starting Routing Task INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 4 CPUs -Checksum: PlaceDB: df865c97 ConstDB: 0 ShapeSum: 7a3346c4 RouteDB: 0 +Checksum: PlaceDB: 3f78c76e ConstDB: 0 ShapeSum: 7a3346c4 RouteDB: 0 Phase 1 Build RT Design -Phase 1 Build RT Design | Checksum: 935836da +Phase 1 Build RT Design | Checksum: de37470a -Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2048.812 ; gain = 24.988 ; free physical = 176 ; free virtual = 9079 -Post Restoration Checksum: NetGraph: 3b924642 NumContArr: 57c5f098 Constraints: 0 Timing: 0 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2051.812 ; gain = 21.988 ; free physical = 198 ; free virtual = 10262 +Post Restoration Checksum: NetGraph: 23d02fed NumContArr: ba67171d Constraints: 0 Timing: 0 Phase 2 Router Initialization INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode. Phase 2.1 Fix Topology Constraints -Phase 2.1 Fix Topology Constraints | Checksum: 935836da +Phase 2.1 Fix Topology Constraints | Checksum: de37470a -Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2062.812 ; gain = 38.988 ; free physical = 162 ; free virtual = 9065 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2065.812 ; gain = 35.988 ; free physical = 183 ; free virtual = 10248 Phase 2.2 Pre Route Cleanup -Phase 2.2 Pre Route Cleanup | Checksum: 935836da +Phase 2.2 Pre Route Cleanup | Checksum: de37470a -Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2062.812 ; gain = 38.988 ; free physical = 162 ; free virtual = 9065 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2065.812 ; gain = 35.988 ; free physical = 183 ; free virtual = 10248 Number of Nodes with overlaps = 0 -Phase 2 Router Initialization | Checksum: 13a2040af +Phase 2 Router Initialization | Checksum: d0d39c49 -Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2067.812 ; gain = 43.988 ; free physical = 157 ; free virtual = 9060 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2070.812 ; gain = 40.988 ; free physical = 177 ; free virtual = 10242 Phase 3 Initial Routing -Phase 3 Initial Routing | Checksum: db222f30 +Phase 3 Initial Routing | Checksum: 113154229 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2067.812 ; gain = 43.988 ; free physical = 158 ; free virtual = 9061 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2070.812 ; gain = 40.988 ; free physical = 177 ; free virtual = 10242 Phase 4 Rip-up And Reroute Phase 4.1 Global Iteration 0 Number of Nodes with overlaps = 0 -Phase 4.1 Global Iteration 0 | Checksum: faf6e8b1 +Phase 4.1 Global Iteration 0 | Checksum: 16ca5cd1d -Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2067.812 ; gain = 43.988 ; free physical = 158 ; free virtual = 9061 -Phase 4 Rip-up And Reroute | Checksum: faf6e8b1 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2070.812 ; gain = 40.988 ; free physical = 177 ; free virtual = 10242 +Phase 4 Rip-up And Reroute | Checksum: 16ca5cd1d -Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2067.812 ; gain = 43.988 ; free physical = 158 ; free virtual = 9061 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2070.812 ; gain = 40.988 ; free physical = 177 ; free virtual = 10242 Phase 5 Delay and Skew Optimization -Phase 5 Delay and Skew Optimization | Checksum: faf6e8b1 +Phase 5 Delay and Skew Optimization | Checksum: 16ca5cd1d -Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2067.812 ; gain = 43.988 ; free physical = 158 ; free virtual = 9061 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2070.812 ; gain = 40.988 ; free physical = 177 ; free virtual = 10242 Phase 6 Post Hold Fix Phase 6.1 Hold Fix Iter -Phase 6.1 Hold Fix Iter | Checksum: faf6e8b1 +Phase 6.1 Hold Fix Iter | Checksum: 16ca5cd1d -Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2067.812 ; gain = 43.988 ; free physical = 158 ; free virtual = 9061 -Phase 6 Post Hold Fix | Checksum: faf6e8b1 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2070.812 ; gain = 40.988 ; free physical = 177 ; free virtual = 10242 +Phase 6 Post Hold Fix | Checksum: 16ca5cd1d -Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2067.812 ; gain = 43.988 ; free physical = 158 ; free virtual = 9061 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2070.812 ; gain = 40.988 ; free physical = 177 ; free virtual = 10242 Phase 7 Route finalize @@ -362,35 +362,35 @@ North Dir 1x1 Area, Max Cong = 26.1261%, No Congested Regions. South Dir 1x1 Area, Max Cong = 32.4324%, No Congested Regions. East Dir 1x1 Area, Max Cong = 10.2941%, No Congested Regions. West Dir 1x1 Area, Max Cong = 2.94118%, No Congested Regions. -Phase 7 Route finalize | Checksum: faf6e8b1 +Phase 7 Route finalize | Checksum: 16ca5cd1d -Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2067.812 ; gain = 43.988 ; free physical = 158 ; free virtual = 9061 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2070.812 ; gain = 40.988 ; free physical = 177 ; free virtual = 10242 Phase 8 Verifying routed nets Verification completed successfully -Phase 8 Verifying routed nets | Checksum: faf6e8b1 +Phase 8 Verifying routed nets | Checksum: 16ca5cd1d -Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2069.812 ; gain = 45.988 ; free physical = 157 ; free virtual = 9060 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2072.812 ; gain = 42.988 ; free physical = 176 ; free virtual = 10241 Phase 9 Depositing Routes -Phase 9 Depositing Routes | Checksum: 6b619e79 +Phase 9 Depositing Routes | Checksum: 1a9e23637 -Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2069.812 ; gain = 45.988 ; free physical = 157 ; free virtual = 9060 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2072.812 ; gain = 42.988 ; free physical = 176 ; free virtual = 10241 INFO: [Route 35-16] Router Completed Successfully -Time (s): cpu = 00:00:08 ; elapsed = 00:00:07 . Memory (MB): peak = 2069.812 ; gain = 45.988 ; free physical = 172 ; free virtual = 9076 +Time (s): cpu = 00:00:07 ; elapsed = 00:00:06 . Memory (MB): peak = 2072.812 ; gain = 42.988 ; free physical = 192 ; free virtual = 10257 Routing Is Done. INFO: [Common 17-83] Releasing license: Implementation 56 Infos, 42 Warnings, 0 Critical Warnings and 0 Errors encountered. route_design completed successfully -route_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2069.812 ; gain = 45.988 ; free physical = 172 ; free virtual = 9075 +route_design: Time (s): cpu = 00:00:09 ; elapsed = 00:00:07 . Memory (MB): peak = 2072.812 ; gain = 42.988 ; free physical = 192 ; free virtual = 10257 Writing placer database... Writing XDEF routing. Writing XDEF routing logical nets. Writing XDEF routing special nets. -Write XDEF Complete: Time (s): cpu = 00:00:00.03 ; elapsed = 00:00:00.01 . Memory (MB): peak = 2069.812 ; gain = 0.000 ; free physical = 171 ; free virtual = 9076 +Write XDEF Complete: Time (s): cpu = 00:00:00.02 ; elapsed = 00:00:00.02 . Memory (MB): peak = 2072.812 ; gain = 0.000 ; free physical = 192 ; free virtual = 10258 INFO: [Common 17-1381] The checkpoint '/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0_routed.dcp' has been generated. INFO: [runtcl-4] Executing : report_drc -file LTC2271_SampleGetter_v1_0_drc_routed.rpt -pb LTC2271_SampleGetter_v1_0_drc_routed.pb -rpx LTC2271_SampleGetter_v1_0_drc_routed.rpx Command: report_drc -file LTC2271_SampleGetter_v1_0_drc_routed.rpt -pb LTC2271_SampleGetter_v1_0_drc_routed.pb -rpx LTC2271_SampleGetter_v1_0_drc_routed.rpx @@ -423,4 +423,4 @@ WARNING: [Timing 38-313] There are no user specified timing constraints. Timing INFO: [runtcl-4] Executing : report_incremental_reuse -file LTC2271_SampleGetter_v1_0_incremental_reuse_routed.rpt INFO: [Vivado_Tcl 4-545] No incremental reuse to report, no incremental placement and routing data was found. INFO: [runtcl-4] Executing : report_clock_utilization -file LTC2271_SampleGetter_v1_0_clock_utilization_routed.rpt -INFO: [Common 17-206] Exiting Vivado at Tue Oct 8 19:28:29 2019... +INFO: [Common 17-206] Exiting Vivado at Tue Oct 15 02:05:21 2019... diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/vivado.jou b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/vivado.jou index 5e1f23542c2e95b8201b2e582169b871c55a7c62..34ca9030ed9eda3f6b732002d013fd5d01b72aa9 100644 --- a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/vivado.jou +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/vivado.jou @@ -2,8 +2,8 @@ # Vivado v2017.4 (64-bit) # SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017 # IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 -# Start of session at: Tue Oct 8 19:27:32 2019 -# Process ID: 10378 +# Start of session at: Tue Oct 15 02:04:27 2019 +# Process ID: 16468 # Current directory: /home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1 # Command line: vivado -log LTC2271_SampleGetter_v1_0.vdi -applog -product Vivado -messageDb vivado.pb -mode batch -source LTC2271_SampleGetter_v1_0.tcl -notrace # Log file: /home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/LTC2271_SampleGetter_v1_0.vdi diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/vivado.pb b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/vivado.pb index fc6d6df740a948c12b982f08531c1b1fb2b2f950..525db572e4eda757361a34054c22e4473deaaf86 100644 Binary files a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/vivado.pb and b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/impl_1/vivado.pb differ diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/.vivado.begin.rst b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/.vivado.begin.rst index 1ce6b12f8a896f24f8decac8d77d45410fdc4077..0128cd12b4a040a1f9d987f46aadc1828b31dc8a 100644 --- a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/.vivado.begin.rst +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/.vivado.begin.rst @@ -1,5 +1,5 @@ - + diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/LTC2271_SampleGetter_v1_0.dcp b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/LTC2271_SampleGetter_v1_0.dcp index 6457a5a4f343b1bd579114c3712e0a807c444d0b..a5b7f25a632e8601055529984682f38f136fb9d7 100644 Binary files a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/LTC2271_SampleGetter_v1_0.dcp and b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/LTC2271_SampleGetter_v1_0.dcp differ diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/LTC2271_SampleGetter_v1_0.tcl b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/LTC2271_SampleGetter_v1_0.tcl index 975b66ef3261ce9a407260fc18068994655412e4..dc28dcaa9bbbae73ddf385f2d25bb2dc1d41efab 100644 --- a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/LTC2271_SampleGetter_v1_0.tcl +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/LTC2271_SampleGetter_v1_0.tcl @@ -16,8 +16,6 @@ proc create_report { reportName command } { send_msg_id runtcl-5 warning "$msg" } } -set_msg_config -id {Synth 8-256} -limit 10000 -set_msg_config -id {Synth 8-638} -limit 10000 create_project -in_memory -part xc7z010clg400-1 set_param project.singleFileAddWarning.threshold 0 diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/LTC2271_SampleGetter_v1_0.vds b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/LTC2271_SampleGetter_v1_0.vds index 6d24f97f565efa86cfb502f7d159762201765d2f..ee57c608ddcf4900aa4b5c68bb8ee61b0e45a6f6 100644 --- a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/LTC2271_SampleGetter_v1_0.vds +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/LTC2271_SampleGetter_v1_0.vds @@ -2,8 +2,8 @@ # Vivado v2017.4 (64-bit) # SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017 # IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 -# Start of session at: Tue Oct 8 19:26:40 2019 -# Process ID: 10218 +# Start of session at: Tue Oct 15 02:03:45 2019 +# Process ID: 16321 # Current directory: /home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1 # Command line: vivado -log LTC2271_SampleGetter_v1_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source LTC2271_SampleGetter_v1_0.tcl # Log file: /home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/LTC2271_SampleGetter_v1_0.vds @@ -15,9 +15,9 @@ Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010' INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 10237 +INFO: Helper process launched with PID 16325 --------------------------------------------------------------------------------- -Starting Synthesize : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1290.676 ; gain = 87.996 ; free physical = 822 ; free virtual = 9820 +Starting Synthesize : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1290.672 ; gain = 87.996 ; free physical = 923 ; free virtual = 10972 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'LTC2271_SampleGetter_v1_0' [/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v:4] Parameter C_M00_AXIS_TDATA_WIDTH bound to: 32 - type: integer @@ -31,28 +31,36 @@ INFO: [Synth 8-638] synthesizing module 'IBUFDS' [/home/nats/Xilinx/Vivado/2017. Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-256] done synthesizing module 'IBUFDS' (1#1) [/home/nats/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:19483] -WARNING: [Synth 8-3848] Net m00_axis_tlast in module/entity LTC2271_SampleGetter_v1_0 does not have driver. [/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v:57] -INFO: [Synth 8-256] done synthesizing module 'LTC2271_SampleGetter_v1_0' (2#1) [/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v:4] -WARNING: [Synth 8-3331] design LTC2271_SampleGetter_v1_0 has unconnected port m00_axis_tlast +INFO: [Synth 8-638] synthesizing module 'IDDR' [/home/nats/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:21382] + Parameter DDR_CLK_EDGE bound to: SAME_EDGE_PIPELINED - type: string + Parameter INIT_Q1 bound to: 1'b0 + Parameter INIT_Q2 bound to: 1'b0 + Parameter IS_C_INVERTED bound to: 1'b0 + Parameter IS_D_INVERTED bound to: 1'b0 + Parameter SRTYPE bound to: SYNC - type: string +INFO: [Synth 8-256] done synthesizing module 'IDDR' (2#1) [/home/nats/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:21382] +WARNING: [Synth 8-350] instance 'DDR_1A' of module 'IDDR' requires 7 connections, but only 5 given [/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v:93] +WARNING: [Synth 8-350] instance 'DDR_2A' of module 'IDDR' requires 7 connections, but only 5 given [/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v:101] +INFO: [Synth 8-256] done synthesizing module 'LTC2271_SampleGetter_v1_0' (3#1) [/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v:4] WARNING: [Synth 8-3331] design LTC2271_SampleGetter_v1_0 has unconnected port m00_axis_aresetn WARNING: [Synth 8-3331] design LTC2271_SampleGetter_v1_0 has unconnected port m00_axis_tready --------------------------------------------------------------------------------- -Finished Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1332.207 ; gain = 129.527 ; free physical = 834 ; free virtual = 9833 +Finished Synthesize : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1332.203 ; gain = 129.527 ; free physical = 936 ; free virtual = 10987 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1332.207 ; gain = 129.527 ; free physical = 834 ; free virtual = 9833 +Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1332.203 ; gain = 129.527 ; free physical = 935 ; free virtual = 10986 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z010clg400-1 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1340.211 ; gain = 137.531 ; free physical = 834 ; free virtual = 9833 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1340.207 ; gain = 137.531 ; free physical = 935 ; free virtual = 10986 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z010clg400-1 -WARNING: [Synth 8-6014] Unused sequential element cnt_reg was removed. [/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v:96] +WARNING: [Synth 8-6014] Unused sequential element cnt_reg was removed. [/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v:119] --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1348.219 ; gain = 145.539 ; free physical = 833 ; free virtual = 9831 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1348.215 ; gain = 145.539 ; free physical = 934 ; free virtual = 10985 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -68,7 +76,7 @@ Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 4 Bit Registers := 1 - 1 Bit Registers := 1 + 1 Bit Registers := 2 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- @@ -81,7 +89,7 @@ Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 4 Bit Registers := 1 - 1 Bit Registers := 1 + 1 Bit Registers := 2 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- @@ -98,18 +106,19 @@ No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- -WARNING: [Synth 8-6014] Unused sequential element cnt_reg was removed. [/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v:96] -WARNING: [Synth 8-3331] design LTC2271_SampleGetter_v1_0 has unconnected port m00_axis_tlast +WARNING: [Synth 8-6014] Unused sequential element cnt_reg was removed. [/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v:119] WARNING: [Synth 8-3331] design LTC2271_SampleGetter_v1_0 has unconnected port m00_axis_aresetn WARNING: [Synth 8-3331] design LTC2271_SampleGetter_v1_0 has unconnected port m00_axis_tready -INFO: [Synth 8-3886] merging instance 'm00_axis_tstrb_reg[0]' (FD) to 'm00_axis_tvalid_reg' -INFO: [Synth 8-3886] merging instance 'm00_axis_tstrb_reg[1]' (FD) to 'm00_axis_tvalid_reg' -INFO: [Synth 8-3886] merging instance 'm00_axis_tstrb_reg[2]' (FD) to 'm00_axis_tvalid_reg' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (m00_axis_tlast_reg) +INFO: [Synth 8-3886] merging instance 'm00_axis_tstrb_reg[0]' (FD) to 'm00_axis_tstrb_reg[3]' +INFO: [Synth 8-3886] merging instance 'm00_axis_tstrb_reg[1]' (FD) to 'm00_axis_tstrb_reg[3]' +INFO: [Synth 8-3886] merging instance 'm00_axis_tstrb_reg[2]' (FD) to 'm00_axis_tstrb_reg[3]' INFO: [Synth 8-3886] merging instance 'm00_axis_tstrb_reg[3]' (FD) to 'm00_axis_tvalid_reg' INFO: [Synth 8-3333] propagating constant 1 across sequential element (m00_axis_tvalid_reg) WARNING: [Synth 8-3332] Sequential element (m00_axis_tvalid_reg) is unused and will be removed from module LTC2271_SampleGetter_v1_0. +WARNING: [Synth 8-3332] Sequential element (m00_axis_tlast_reg) is unused and will be removed from module LTC2271_SampleGetter_v1_0. --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 1448.570 ; gain = 245.891 ; free physical = 673 ; free virtual = 9672 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:22 . Memory (MB): peak = 1448.566 ; gain = 245.891 ; free physical = 759 ; free virtual = 10836 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -122,7 +131,7 @@ No constraint files found. Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 1448.570 ; gain = 245.891 ; free physical = 672 ; free virtual = 9671 +Finished Timing Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:22 . Memory (MB): peak = 1448.566 ; gain = 245.891 ; free physical = 758 ; free virtual = 10835 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -134,7 +143,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 1457.586 ; gain = 254.906 ; free physical = 672 ; free virtual = 9670 +Finished Technology Mapping : Time (s): cpu = 00:00:13 ; elapsed = 00:00:22 . Memory (MB): peak = 1457.582 ; gain = 254.906 ; free physical = 757 ; free virtual = 10835 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -158,7 +167,7 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 1457.586 ; gain = 254.906 ; free physical = 671 ; free virtual = 9670 +Finished IO Insertion : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1457.582 ; gain = 254.906 ; free physical = 754 ; free virtual = 10832 --------------------------------------------------------------------------------- Report Check Netlist: @@ -171,7 +180,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 1457.586 ; gain = 254.906 ; free physical = 671 ; free virtual = 9670 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1457.582 ; gain = 254.906 ; free physical = 754 ; free virtual = 10832 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -183,25 +192,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 1457.586 ; gain = 254.906 ; free physical = 671 ; free virtual = 9670 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1457.582 ; gain = 254.906 ; free physical = 754 ; free virtual = 10832 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 1457.586 ; gain = 254.906 ; free physical = 671 ; free virtual = 9670 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1457.582 ; gain = 254.906 ; free physical = 754 ; free virtual = 10832 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 1457.586 ; gain = 254.906 ; free physical = 671 ; free virtual = 9670 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1457.582 ; gain = 254.906 ; free physical = 754 ; free virtual = 10832 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 1457.586 ; gain = 254.906 ; free physical = 671 ; free virtual = 9670 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1457.582 ; gain = 254.906 ; free physical = 754 ; free virtual = 10832 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -219,28 +228,28 @@ Report Cell Usage: +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 8| -|3 |LUT1 | 1| -|4 |FDRE | 64| -|5 |IBUF | 1| -|6 |IBUFDS | 10| -|7 |OBUF | 37| -|8 |OBUFT | 1| +|3 |IDDR | 2| +|4 |LUT1 | 1| +|5 |FDRE | 64| +|6 |IBUF | 1| +|7 |IBUFDS | 10| +|8 |OBUF | 38| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ -|1 |top | | 123| +|1 |top | | 125| +------+---------+-------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 1457.586 ; gain = 254.906 ; free physical = 671 ; free virtual = 9670 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1457.582 ; gain = 254.906 ; free physical = 754 ; free virtual = 10832 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 10 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 1457.586 ; gain = 254.906 ; free physical = 672 ; free virtual = 9671 -Synthesis Optimization Complete : Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 1457.594 ; gain = 254.906 ; free physical = 672 ; free virtual = 9671 +Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1457.582 ; gain = 254.906 ; free physical = 756 ; free virtual = 10833 +Synthesis Optimization Complete : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1457.590 ; gain = 254.906 ; free physical = 756 ; free virtual = 10833 INFO: [Project 1-571] Translating synthesized netlist -INFO: [Netlist 29-17] Analyzing 19 Unisim elements for replacement +INFO: [Netlist 29-17] Analyzing 21 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). @@ -248,10 +257,10 @@ INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis -18 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered. +21 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:26 . Memory (MB): peak = 1534.586 ; gain = 357.734 ; free physical = 629 ; free virtual = 9629 +synth_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1534.582 ; gain = 357.734 ; free physical = 699 ; free virtual = 10792 INFO: [Common 17-1381] The checkpoint '/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/LTC2271_SampleGetter_v1_0.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file LTC2271_SampleGetter_v1_0_utilization_synth.rpt -pb LTC2271_SampleGetter_v1_0_utilization_synth.pb -report_utilization: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1558.598 ; gain = 0.000 ; free physical = 631 ; free virtual = 9630 -INFO: [Common 17-206] Exiting Vivado at Tue Oct 8 19:27:14 2019... +report_utilization: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1558.594 ; gain = 0.000 ; free physical = 703 ; free virtual = 10795 +INFO: [Common 17-206] Exiting Vivado at Tue Oct 15 02:04:16 2019... diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/LTC2271_SampleGetter_v1_0_utilization_synth.rpt b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/LTC2271_SampleGetter_v1_0_utilization_synth.rpt index 7e49da7362c0a3d41802807b161523a68362a8ed..6bcc3360d25332250d99b9e485b649d885950e98 100644 --- a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/LTC2271_SampleGetter_v1_0_utilization_synth.rpt +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/LTC2271_SampleGetter_v1_0_utilization_synth.rpt @@ -1,7 +1,7 @@ Copyright 1986-2017 Xilinx, Inc. All Rights Reserved. --------------------------------------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017 -| Date : Tue Oct 8 19:27:14 2019 +| Date : Tue Oct 15 02:04:16 2019 | Host : nats-MS-7A72 running 64-bit Ubuntu 18.04.3 LTS | Command : report_utilization -file LTC2271_SampleGetter_v1_0_utilization_synth.rpt -pb LTC2271_SampleGetter_v1_0_utilization_synth.pb | Design : LTC2271_SampleGetter_v1_0 @@ -102,7 +102,8 @@ Table of Contents | PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 8 | 0.00 | | PHASER_IN/PHASER_IN_PHY | 0 | 0 | 8 | 0.00 | | IDELAYE2/IDELAYE2_FINEDELAY | 0 | 0 | 100 | 0.00 | -| ILOGIC | 0 | 0 | 100 | 0.00 | +| ILOGIC | 2 | 0 | 100 | 2.00 | +| IDDR | 2 | | | | | OLOGIC | 0 | 0 | 100 | 0.00 | +-----------------------------+------+-------+-----------+-------+ @@ -147,10 +148,10 @@ Table of Contents | Ref Name | Used | Functional Category | +----------+------+---------------------+ | FDRE | 64 | Flop & Latch | -| OBUF | 37 | IO | +| OBUF | 38 | IO | | IBUFDS | 10 | IO | | CARRY4 | 8 | CarryLogic | -| OBUFT | 1 | IO | +| IDDR | 2 | IO | | LUT1 | 1 | LUT | | IBUF | 1 | IO | | BUFG | 1 | Clock | diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/gen_run.xml b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/gen_run.xml index 28e0925d35f9960eb3879906a2f6cc32fafae24f..a6f902711966d448d373994564bf9e2b38bc9869 100644 --- a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/gen_run.xml +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/gen_run.xml @@ -1,5 +1,5 @@ - + diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/runme.log b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/runme.log index 5fd8dce0e5c2b949247e21ec664652c536d5a5aa..7f7198484e2a0e7f547aa55171e235dadffdcac0 100644 --- a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/runme.log +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/runme.log @@ -14,9 +14,9 @@ Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7z010' INFO: [Common 17-349] Got license for feature 'Synthesis' and/or device 'xc7z010' INFO: Launching helper process for spawning children vivado processes -INFO: Helper process launched with PID 10237 +INFO: Helper process launched with PID 16325 --------------------------------------------------------------------------------- -Starting Synthesize : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1290.676 ; gain = 87.996 ; free physical = 822 ; free virtual = 9820 +Starting Synthesize : Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 1290.672 ; gain = 87.996 ; free physical = 923 ; free virtual = 10972 --------------------------------------------------------------------------------- INFO: [Synth 8-638] synthesizing module 'LTC2271_SampleGetter_v1_0' [/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v:4] Parameter C_M00_AXIS_TDATA_WIDTH bound to: 32 - type: integer @@ -30,28 +30,36 @@ INFO: [Synth 8-638] synthesizing module 'IBUFDS' [/home/nats/Xilinx/Vivado/2017. Parameter IFD_DELAY_VALUE bound to: AUTO - type: string Parameter IOSTANDARD bound to: DEFAULT - type: string INFO: [Synth 8-256] done synthesizing module 'IBUFDS' (1#1) [/home/nats/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:19483] -WARNING: [Synth 8-3848] Net m00_axis_tlast in module/entity LTC2271_SampleGetter_v1_0 does not have driver. [/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v:57] -INFO: [Synth 8-256] done synthesizing module 'LTC2271_SampleGetter_v1_0' (2#1) [/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v:4] -WARNING: [Synth 8-3331] design LTC2271_SampleGetter_v1_0 has unconnected port m00_axis_tlast +INFO: [Synth 8-638] synthesizing module 'IDDR' [/home/nats/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:21382] + Parameter DDR_CLK_EDGE bound to: SAME_EDGE_PIPELINED - type: string + Parameter INIT_Q1 bound to: 1'b0 + Parameter INIT_Q2 bound to: 1'b0 + Parameter IS_C_INVERTED bound to: 1'b0 + Parameter IS_D_INVERTED bound to: 1'b0 + Parameter SRTYPE bound to: SYNC - type: string +INFO: [Synth 8-256] done synthesizing module 'IDDR' (2#1) [/home/nats/Xilinx/Vivado/2017.4/scripts/rt/data/unisim_comp.v:21382] +WARNING: [Synth 8-350] instance 'DDR_1A' of module 'IDDR' requires 7 connections, but only 5 given [/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v:93] +WARNING: [Synth 8-350] instance 'DDR_2A' of module 'IDDR' requires 7 connections, but only 5 given [/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v:101] +INFO: [Synth 8-256] done synthesizing module 'LTC2271_SampleGetter_v1_0' (3#1) [/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v:4] WARNING: [Synth 8-3331] design LTC2271_SampleGetter_v1_0 has unconnected port m00_axis_aresetn WARNING: [Synth 8-3331] design LTC2271_SampleGetter_v1_0 has unconnected port m00_axis_tready --------------------------------------------------------------------------------- -Finished Synthesize : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1332.207 ; gain = 129.527 ; free physical = 834 ; free virtual = 9833 +Finished Synthesize : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1332.203 ; gain = 129.527 ; free physical = 936 ; free virtual = 10987 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Constraint Validation : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1332.207 ; gain = 129.527 ; free physical = 834 ; free virtual = 9833 +Finished Constraint Validation : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1332.203 ; gain = 129.527 ; free physical = 935 ; free virtual = 10986 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Loading Part and Timing Information --------------------------------------------------------------------------------- Loading part: xc7z010clg400-1 --------------------------------------------------------------------------------- -Finished Loading Part and Timing Information : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1340.211 ; gain = 137.531 ; free physical = 834 ; free virtual = 9833 +Finished Loading Part and Timing Information : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1340.207 ; gain = 137.531 ; free physical = 935 ; free virtual = 10986 --------------------------------------------------------------------------------- INFO: [Device 21-403] Loading part xc7z010clg400-1 -WARNING: [Synth 8-6014] Unused sequential element cnt_reg was removed. [/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v:96] +WARNING: [Synth 8-6014] Unused sequential element cnt_reg was removed. [/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v:119] --------------------------------------------------------------------------------- -Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:07 ; elapsed = 00:00:07 . Memory (MB): peak = 1348.219 ; gain = 145.539 ; free physical = 833 ; free virtual = 9831 +Finished RTL Optimization Phase 2 : Time (s): cpu = 00:00:06 ; elapsed = 00:00:07 . Memory (MB): peak = 1348.215 ; gain = 145.539 ; free physical = 934 ; free virtual = 10985 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -67,7 +75,7 @@ Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 4 Bit Registers := 1 - 1 Bit Registers := 1 + 1 Bit Registers := 2 --------------------------------------------------------------------------------- Finished RTL Component Statistics --------------------------------------------------------------------------------- @@ -80,7 +88,7 @@ Detailed RTL Component Info : +---Registers : 32 Bit Registers := 1 4 Bit Registers := 1 - 1 Bit Registers := 1 + 1 Bit Registers := 2 --------------------------------------------------------------------------------- Finished RTL Hierarchical Component Statistics --------------------------------------------------------------------------------- @@ -97,18 +105,19 @@ No constraint files found. --------------------------------------------------------------------------------- Start Cross Boundary and Area Optimization --------------------------------------------------------------------------------- -WARNING: [Synth 8-6014] Unused sequential element cnt_reg was removed. [/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v:96] -WARNING: [Synth 8-3331] design LTC2271_SampleGetter_v1_0 has unconnected port m00_axis_tlast +WARNING: [Synth 8-6014] Unused sequential element cnt_reg was removed. [/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/LTC2271_SampleGetter_1.0/hdl/LTC2271_SampleGetter_v1_0.v:119] WARNING: [Synth 8-3331] design LTC2271_SampleGetter_v1_0 has unconnected port m00_axis_aresetn WARNING: [Synth 8-3331] design LTC2271_SampleGetter_v1_0 has unconnected port m00_axis_tready -INFO: [Synth 8-3886] merging instance 'm00_axis_tstrb_reg[0]' (FD) to 'm00_axis_tvalid_reg' -INFO: [Synth 8-3886] merging instance 'm00_axis_tstrb_reg[1]' (FD) to 'm00_axis_tvalid_reg' -INFO: [Synth 8-3886] merging instance 'm00_axis_tstrb_reg[2]' (FD) to 'm00_axis_tvalid_reg' +INFO: [Synth 8-3333] propagating constant 0 across sequential element (m00_axis_tlast_reg) +INFO: [Synth 8-3886] merging instance 'm00_axis_tstrb_reg[0]' (FD) to 'm00_axis_tstrb_reg[3]' +INFO: [Synth 8-3886] merging instance 'm00_axis_tstrb_reg[1]' (FD) to 'm00_axis_tstrb_reg[3]' +INFO: [Synth 8-3886] merging instance 'm00_axis_tstrb_reg[2]' (FD) to 'm00_axis_tstrb_reg[3]' INFO: [Synth 8-3886] merging instance 'm00_axis_tstrb_reg[3]' (FD) to 'm00_axis_tvalid_reg' INFO: [Synth 8-3333] propagating constant 1 across sequential element (m00_axis_tvalid_reg) WARNING: [Synth 8-3332] Sequential element (m00_axis_tvalid_reg) is unused and will be removed from module LTC2271_SampleGetter_v1_0. +WARNING: [Synth 8-3332] Sequential element (m00_axis_tlast_reg) is unused and will be removed from module LTC2271_SampleGetter_v1_0. --------------------------------------------------------------------------------- -Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 1448.570 ; gain = 245.891 ; free physical = 673 ; free virtual = 9672 +Finished Cross Boundary and Area Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:22 . Memory (MB): peak = 1448.566 ; gain = 245.891 ; free physical = 759 ; free virtual = 10836 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -121,7 +130,7 @@ No constraint files found. Start Timing Optimization --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Timing Optimization : Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 1448.570 ; gain = 245.891 ; free physical = 672 ; free virtual = 9671 +Finished Timing Optimization : Time (s): cpu = 00:00:13 ; elapsed = 00:00:22 . Memory (MB): peak = 1448.566 ; gain = 245.891 ; free physical = 758 ; free virtual = 10835 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -133,7 +142,7 @@ Report RTL Partitions: Start Technology Mapping --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Technology Mapping : Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 1457.586 ; gain = 254.906 ; free physical = 672 ; free virtual = 9670 +Finished Technology Mapping : Time (s): cpu = 00:00:13 ; elapsed = 00:00:22 . Memory (MB): peak = 1457.582 ; gain = 254.906 ; free physical = 757 ; free virtual = 10835 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -157,7 +166,7 @@ Start Final Netlist Cleanup Finished Final Netlist Cleanup --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished IO Insertion : Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 1457.586 ; gain = 254.906 ; free physical = 671 ; free virtual = 9670 +Finished IO Insertion : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1457.582 ; gain = 254.906 ; free physical = 754 ; free virtual = 10832 --------------------------------------------------------------------------------- Report Check Netlist: @@ -170,7 +179,7 @@ Report Check Netlist: Start Renaming Generated Instances --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Instances : Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 1457.586 ; gain = 254.906 ; free physical = 671 ; free virtual = 9670 +Finished Renaming Generated Instances : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1457.582 ; gain = 254.906 ; free physical = 754 ; free virtual = 10832 --------------------------------------------------------------------------------- Report RTL Partitions: @@ -182,25 +191,25 @@ Report RTL Partitions: Start Rebuilding User Hierarchy --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 1457.586 ; gain = 254.906 ; free physical = 671 ; free virtual = 9670 +Finished Rebuilding User Hierarchy : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1457.582 ; gain = 254.906 ; free physical = 754 ; free virtual = 10832 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Ports --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Ports : Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 1457.586 ; gain = 254.906 ; free physical = 671 ; free virtual = 9670 +Finished Renaming Generated Ports : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1457.582 ; gain = 254.906 ; free physical = 754 ; free virtual = 10832 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Handling Custom Attributes --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Handling Custom Attributes : Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 1457.586 ; gain = 254.906 ; free physical = 671 ; free virtual = 9670 +Finished Handling Custom Attributes : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1457.582 ; gain = 254.906 ; free physical = 754 ; free virtual = 10832 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Renaming Generated Nets --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- -Finished Renaming Generated Nets : Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 1457.586 ; gain = 254.906 ; free physical = 671 ; free virtual = 9670 +Finished Renaming Generated Nets : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1457.582 ; gain = 254.906 ; free physical = 754 ; free virtual = 10832 --------------------------------------------------------------------------------- --------------------------------------------------------------------------------- Start Writing Synthesis Report @@ -218,28 +227,28 @@ Report Cell Usage: +------+-------+------+ |1 |BUFG | 1| |2 |CARRY4 | 8| -|3 |LUT1 | 1| -|4 |FDRE | 64| -|5 |IBUF | 1| -|6 |IBUFDS | 10| -|7 |OBUF | 37| -|8 |OBUFT | 1| +|3 |IDDR | 2| +|4 |LUT1 | 1| +|5 |FDRE | 64| +|6 |IBUF | 1| +|7 |IBUFDS | 10| +|8 |OBUF | 38| +------+-------+------+ Report Instance Areas: +------+---------+-------+------+ | |Instance |Module |Cells | +------+---------+-------+------+ -|1 |top | | 123| +|1 |top | | 125| +------+---------+-------+------+ --------------------------------------------------------------------------------- -Finished Writing Synthesis Report : Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 1457.586 ; gain = 254.906 ; free physical = 671 ; free virtual = 9670 +Finished Writing Synthesis Report : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1457.582 ; gain = 254.906 ; free physical = 754 ; free virtual = 10832 --------------------------------------------------------------------------------- Synthesis finished with 0 errors, 0 critical warnings and 10 warnings. -Synthesis Optimization Runtime : Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 1457.586 ; gain = 254.906 ; free physical = 672 ; free virtual = 9671 -Synthesis Optimization Complete : Time (s): cpu = 00:00:14 ; elapsed = 00:00:24 . Memory (MB): peak = 1457.594 ; gain = 254.906 ; free physical = 672 ; free virtual = 9671 +Synthesis Optimization Runtime : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1457.582 ; gain = 254.906 ; free physical = 756 ; free virtual = 10833 +Synthesis Optimization Complete : Time (s): cpu = 00:00:13 ; elapsed = 00:00:23 . Memory (MB): peak = 1457.590 ; gain = 254.906 ; free physical = 756 ; free virtual = 10833 INFO: [Project 1-571] Translating synthesized netlist -INFO: [Netlist 29-17] Analyzing 19 Unisim elements for replacement +INFO: [Netlist 29-17] Analyzing 21 Unisim elements for replacement INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds INFO: [Project 1-570] Preparing netlist for logic optimization INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s). @@ -247,10 +256,10 @@ INFO: [Project 1-111] Unisim Transformation Summary: No Unisim elements were transformed. INFO: [Common 17-83] Releasing license: Synthesis -18 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered. +21 Infos, 10 Warnings, 0 Critical Warnings and 0 Errors encountered. synth_design completed successfully -synth_design: Time (s): cpu = 00:00:16 ; elapsed = 00:00:26 . Memory (MB): peak = 1534.586 ; gain = 357.734 ; free physical = 629 ; free virtual = 9629 +synth_design: Time (s): cpu = 00:00:15 ; elapsed = 00:00:24 . Memory (MB): peak = 1534.582 ; gain = 357.734 ; free physical = 699 ; free virtual = 10792 INFO: [Common 17-1381] The checkpoint '/home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/LTC2271_SampleGetter_v1_0.dcp' has been generated. INFO: [runtcl-4] Executing : report_utilization -file LTC2271_SampleGetter_v1_0_utilization_synth.rpt -pb LTC2271_SampleGetter_v1_0_utilization_synth.pb -report_utilization: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1558.598 ; gain = 0.000 ; free physical = 631 ; free virtual = 9630 -INFO: [Common 17-206] Exiting Vivado at Tue Oct 8 19:27:14 2019... +report_utilization: Time (s): cpu = 00:00:00.08 ; elapsed = 00:00:00.10 . Memory (MB): peak = 1558.594 ; gain = 0.000 ; free physical = 703 ; free virtual = 10795 +INFO: [Common 17-206] Exiting Vivado at Tue Oct 15 02:04:16 2019... diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/vivado.jou b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/vivado.jou index 99868349c8e717f59bf722083bae3e6a9c35d430..1f9faa8498a1ade6636fd6fe2a81b7301984511c 100644 --- a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/vivado.jou +++ b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/vivado.jou @@ -2,8 +2,8 @@ # Vivado v2017.4 (64-bit) # SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017 # IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017 -# Start of session at: Tue Oct 8 19:26:40 2019 -# Process ID: 10218 +# Start of session at: Tue Oct 15 02:03:45 2019 +# Process ID: 16321 # Current directory: /home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1 # Command line: vivado -log LTC2271_SampleGetter_v1_0.vds -product Vivado -mode batch -messageDb vivado.pb -notrace -source LTC2271_SampleGetter_v1_0.tcl # Log file: /home/nats/project/VNAV2_Zynq/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/LTC2271_SampleGetter_v1_0.vds diff --git a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/vivado.pb b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/vivado.pb index c888948ccf7a9977ec9d01dc5e9234054c9ba970..333734c066495d0acac2344d4acf1d0632ee1e16 100644 Binary files a/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/vivado.pb and b/IP/LTC2271_ADCGetter/edit_LTC2271_SampleGetter_v1_0.runs/synth_1/vivado.pb differ diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/wt/gui_handlers.wdf b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/wt/gui_handlers.wdf index 52e165932624a4e0dc1aae4ba5c345ed41314871..228e022a85b1947d4624f62c5531bb0526cf7bec 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/wt/gui_handlers.wdf +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/wt/gui_handlers.wdf @@ -24,12 +24,12 @@ version:1 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:637573746f6d697a65636f72656469616c6f675f646f63756d656e746174696f6e:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:637573746f6d697a65636f72656469616c6f675f69705f6c6f636174696f6e:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:65787072756e7472656570616e656c5f6578705f72756e5f747265655f7461626c65:39:00:00 -70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:313636:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:66696c6573657470616e656c5f66696c655f7365745f70616e656c5f74726565:313639:00:00 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-70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7a6f6f6d5f666974:36:00:00 +70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7a6f6f6d5f666974:37:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7061636f6d6d616e646e616d65735f7a6f6f6d5f6f7574:31:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f616464726573735f656469746f72:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:706176696577735f636f6465:3132:00:00 @@ -124,7 +124,7 @@ version:1 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:73696d706c656f757470757470726f647563746469616c6f675f67656e65726174655f6f75747075745f70726f64756374735f696d6d6564696174656c79:3131:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:7372636d656e755f69705f686965726172636879:37:00:00 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70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74636c636f6e736f6c65766965775f74636c5f636f6e736f6c655f636f64655f656469746f72:33:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:74636c6f626a656374747265657461626c655f747265657461626c65:32:00:00 70726f6a656374:76697661646f5f75736167655c6775695f68616e646c657273:746f756368706f696e747375727665796469616c6f675f6e6f:31:00:00 -eof:762558716 +eof:2743579528 diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/wt/java_command_handlers.wdf b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/wt/java_command_handlers.wdf index 4c5cc6aabf1fc38c7666d72d556502b4f26e085e..165329daa4b5d13d8c749d8c62ed2e1d9b4c5e26 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/wt/java_command_handlers.wdf +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/wt/java_command_handlers.wdf @@ -19,7 +19,7 @@ version:1 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a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/wt/project.wpc b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/wt/project.wpc index 113930bfc324021da54d06476702ab2b1f11aa77..a0b1b7aae2ff3cf4d143162efc25c2ca87a2c7d6 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/wt/project.wpc +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/wt/project.wpc @@ -1,5 +1,5 @@ version:1 57656254616c6b5472616e736d697373696f6e417474656d70746564:14 6d6f64655f636f756e7465727c42617463684d6f6465:2 -6d6f64655f636f756e7465727c4755494d6f6465:26 +6d6f64655f636f756e7465727c4755494d6f6465:27 eof: diff --git a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/wt/webtalk_pa.xml b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/wt/webtalk_pa.xml index 66cd0fc055c7f47ee19147a49af5649a05a15d10..3b4b3cbf90d244fa8d031f8a5068dd77c20872cb 100644 --- a/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/wt/webtalk_pa.xml +++ b/petalinux/mz7010_fmccc_2017_4/hardware/MZ7010_FMCCC/mz_petalinux.cache/wt/webtalk_pa.xml @@ -3,7 +3,7 @@ - +
@@ -37,7 +37,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -60,7 +60,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -89,12 +89,12 @@ This means code written to parse this file will need to be revisited each subseq - + - + @@ -150,7 +150,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -189,7 +189,7 @@ This means code written to parse this file will need to be revisited each subseq - + @@ -211,7 +211,7 @@ This means code written to parse this file will need to be revisited each subseq - +