/* This file is part of MutekH. MutekH is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public License as published by the Free Software Foundation; version 2.1 of the License. MutekH is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details. You should have received a copy of the GNU Lesser General Public License along with this program. If not, see . Copyright Nicolas Pouillon (c) 2016 */ #include #include #include #include #include #include #include DEV_DECLARE_STATIC(clock_dev, "clock", 0, nrf5x_clock_drv, // Muxes DEV_STATIC_RES_CMU_MUX(NRF_CLOCK_OSC_HFXO, NRF_CLOCK_SRC_HFCLK, 0b100, 1, 1), DEV_STATIC_RES_CMU_MUX(NRF_CLOCK_OSC_HFRC, NRF_CLOCK_SRC_HFCLK, 0b011, 1, 1), DEV_STATIC_RES_CMU_MUX(NRF_CLOCK_OSC_HFRC, NRF_CLOCK_SRC_LFCLK, 0b110, 1, 1), DEV_STATIC_RES_CMU_MUX(NRF_CLOCK_OSC_LFRC, NRF_CLOCK_SRC_LFCLK, 0b001, 1, 1), // Oscillators DEV_STATIC_RES_CMU_OSC_ACC(NRF_CLOCK_OSC_LFRC, 0b001, 32768, 1, 2, 25), // 2% DEV_STATIC_RES_CMU_OSC_ACC(NRF_CLOCK_OSC_HFXO, 0b111, 32000000, 1, 7, 15), // 31ppm DEV_STATIC_RES_CMU_OSC_ACC(NRF_CLOCK_OSC_HFRC, 0b111, 16000000, 1, 2, 25), // 2% NRF_STATIC_RES_PERIPHERAL_MEM(NRF5X_CLOCK), DEV_STATIC_RES_DEV_ICU("/cpu"), DEV_STATIC_RES_IRQ(0, NRF5X_CLOCK, DEV_IRQ_SENSE_HIGH_LEVEL, 0, 1), ); #if defined(CONFIG_DRIVER_NRF5X_UART) DEV_DECLARE_STATIC(uart_dev, "uart0", 0, nrf5x_uart_drv, NRF_STATIC_RES_PERIPHERAL_MEM(NRF5X_UART0), DEV_STATIC_RES_DEV_ICU("/cpu"), DEV_STATIC_RES_IRQ(0, NRF5X_UART0, DEV_IRQ_SENSE_HIGH_LEVEL, 0, 1), DEV_STATIC_RES_DEV_IOMUX("/gpio"), DEV_STATIC_RES_UART(1000000, 8, DEV_UART_PARITY_NONE, 1, 0, 0), DEV_STATIC_RES_IOMUX("tx", 0, 19, 0, 0), DEV_STATIC_RES_IOMUX("rx", 0, 20, 0, 0) ); #endif #if defined(CONFIG_DRIVER_NRF5X_SPI) DEV_DECLARE_STATIC(spi_dev, "spi0", 0, nrf5x_spi_drv, NRF_STATIC_RES_PERIPHERAL_MEM(NRF5X_SPI1), DEV_STATIC_RES_DEV_ICU("/cpu"), DEV_STATIC_RES_IRQ(0, NRF5X_SPI1, DEV_IRQ_SENSE_HIGH_LEVEL, 0, 1), DEV_STATIC_RES_DEV_IOMUX("/gpio"), DEV_STATIC_RES_IOMUX("clk", 0, 29, 0, 0), DEV_STATIC_RES_IOMUX("mosi", 0, 28, 0, 0), DEV_STATIC_RES_IOMUX("miso", 0, 27, 0, 0) // DEV_STATIC_RES_IOMUX("miso", 0, 12, 0, 0) ); # if defined(CONFIG_DRIVER_NFC_MICORE2) DEV_DECLARE_STATIC(micore2_dev, "nfc0", 0, micore2_drv, DEV_STATIC_RES_DEV_PARAM("spi", "/spi*"), DEV_STATIC_RES_DEV_PARAM("gpio", "/gpio"), DEV_STATIC_RES_DEV_PARAM("icu", "/gpio"), DEV_STATIC_RES_IRQ(0, 2, DEV_IRQ_SENSE_FALLING_EDGE, 0, 1), DEV_STATIC_RES_UINT_PARAM("gpio-cs-id", 1), DEV_STATIC_RES_DEV_TIMER("rtc* timer*"), DEV_STATIC_RES_GPIO("resetn", 0, 1), ); # endif # if defined(CONFIG_DRIVER_MCP2515) DEV_DECLARE_STATIC(mcp2515_dev, "can0", 0, mcp2515_drv, DEV_STATIC_RES_DEV_PARAM("spi", "/spi*"), DEV_STATIC_RES_DEV_PARAM("gpio", "/gpio"), DEV_STATIC_RES_DEV_PARAM("icu", "/gpio"), DEV_STATIC_RES_IRQ(0, 30, DEV_IRQ_SENSE_FALLING_EDGE, 0, 1), DEV_STATIC_RES_GPIO("nirq", 30, 1), DEV_STATIC_RES_GPIO("rst", 25, 1), DEV_STATIC_RES_UINT_PARAM("gpio-cs-id", 26), ); # endif #endif #if defined(CONFIG_DRIVER_HD44780) DEV_DECLARE_STATIC(hd44780_dev, "lcd0", 0, hd44780_drv, DEV_STATIC_RES_DEV_PARAM("gpio", "/gpio"), DEV_STATIC_RES_DEV_TIMER("rtc* timer*"), DEV_STATIC_RES_GPIO("rs", 18, 1), DEV_STATIC_RES_GPIO("e", 17, 1), DEV_STATIC_RES_GPIO("d", 13, 4), ); #endif #if defined(CONFIG_DRIVER_NRF5X_GPIO_PWM) DEV_DECLARE_STATIC(pwm_dev, "pwm", 0, nrf5x_gpio_pwm_drv, NRF_STATIC_RES_PERIPHERAL_MEM(NRF5X_TIMER2), DEV_STATIC_RES_DEV_ICU("/cpu"), DEV_STATIC_RES_IRQ(0, NRF5X_TIMER2, DEV_IRQ_SENSE_HIGH_LEVEL, 0, 1), DEV_STATIC_RES_DEV_IOMUX("/gpio"), DEV_STATIC_RES_IOMUX("p0", 0, 12, 0, 0), ); #endif