Commit 4ebf5736 authored by Papy's avatar Papy Committed by Nicolas Pouillon

brain: fix phy clock source init

parent 3c046532
...@@ -85,11 +85,12 @@ DEV_DECLARE_STATIC(dwc10100_dev, "eth0", 0, dwc10100_drv, ...@@ -85,11 +85,12 @@ DEV_DECLARE_STATIC(dwc10100_dev, "eth0", 0, dwc10100_drv,
DEV_STATIC_RES_MEM(STM32_ETHERNET_DMA_ADDR, STM32_ETHERNET_DMA_ADDR + STM32_ETHERNET_DMA_SIZE), DEV_STATIC_RES_MEM(STM32_ETHERNET_DMA_ADDR, STM32_ETHERNET_DMA_ADDR + STM32_ETHERNET_DMA_SIZE),
DEV_STATIC_RES_FREQ(72000000, 1), DEV_STATIC_RES_FREQ(72000000, 1),
DEV_STATIC_RES_DEV_PARAM("gpio", "/gpio"),
DEV_STATIC_RES_DEV_IOMUX("/gpio"),
DEV_STATIC_RES_DEV_IOMUX("/gpio"),
DEV_STATIC_RES_IOMUX("mdc", 0, STM32_PC1, 0, 0), DEV_STATIC_RES_IOMUX("mdc", 0, STM32_PC1, 0, 0),
DEV_STATIC_RES_IOMUX("mdio", 0, STM32_PA2, 0, 0), DEV_STATIC_RES_IOMUX("mdio", 0, STM32_PA2, 0, 0),
DEV_STATIC_RES_DEV_PARAM("gpio", "/gpio"),
DEV_STATIC_RES_GPIO("resetn", STM32_PC7, 1), DEV_STATIC_RES_GPIO("resetn", STM32_PC7, 1),
DEV_STATIC_RES_DEV_ICU("/cpu"), DEV_STATIC_RES_DEV_ICU("/cpu"),
...@@ -100,6 +101,7 @@ DEV_DECLARE_STATIC(dwc10100_dev, "eth0", 0, dwc10100_drv, ...@@ -100,6 +101,7 @@ DEV_DECLARE_STATIC(dwc10100_dev, "eth0", 0, dwc10100_drv,
#include <hexo/endian.h> #include <hexo/endian.h>
#include <hexo/iospace.h> #include <hexo/iospace.h>
#include <arch/stm32/f1/rcc.h> #include <arch/stm32/f1/rcc.h>
#include <arch/stm32/f1/gpio.h>
#include <mutek/startup.h> #include <mutek/startup.h>
#define __IO volatile #define __IO volatile
...@@ -227,4 +229,11 @@ void stm32_clock_init(void) ...@@ -227,4 +229,11 @@ void stm32_clock_init(void)
cpu_mem_write_32(STM32_RCC_ADDR + STM32_RCC_AHBRSTR_ADDR, -1); cpu_mem_write_32(STM32_RCC_ADDR + STM32_RCC_AHBRSTR_ADDR, -1);
cpu_mem_write_32(STM32_RCC_ADDR + STM32_RCC_AHBRSTR_ADDR, 0); cpu_mem_write_32(STM32_RCC_ADDR + STM32_RCC_AHBRSTR_ADDR, 0);
// Set MCO pin as alternate function
a = STM32_GPIO_ADDR + STM32_GPIO_CRH_ADDR(0);
x = endian_le32(cpu_mem_read_32(a));
STM32_GPIO_CRH_CNF_SET(0, x, ALT_PUSH_PULL);
STM32_GPIO_CRH_MODE_SET(0, x, OUTPUT_50_MHZ);
cpu_mem_write_32(a, endian_le32(x));
} }
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