Commit 40e7b8d2 authored by unknown's avatar unknown

Finished layout.

parent 68eeb2b2
This diff is collapsed.
{
"board": {
"active_layer": 0,
"active_layer": 31,
"active_layer_preset": "",
"auto_track_width": true,
"hidden_nets": [],
......@@ -63,7 +63,7 @@
35,
36
],
"visible_layers": "ffcffff_ffffffff",
"visible_layers": "7ffffff_80000001",
"zone_display_mode": 0
},
"meta": {
......
......@@ -48,7 +48,13 @@
"min_clearance": 0.508
}
},
"diff_pair_dimensions": [],
"diff_pair_dimensions": [
{
"gap": 0.0,
"via_gap": 0.0,
"width": 0.0
}
],
"drc_exclusions": [],
"meta": {
"version": 2
......@@ -110,8 +116,15 @@
"solder_mask_min_width": 0.0,
"use_height_for_length_calcs": true
},
"track_widths": [],
"via_dimensions": [],
"track_widths": [
0.0
],
"via_dimensions": [
{
"diameter": 0.0,
"drill": 0.0
}
],
"zones_allow_external_fillets": false,
"zones_use_no_outline": true
},
......@@ -352,6 +365,32 @@
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
},
{
"bus_width": 6.0,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "PWR",
"nets": [
"+5V",
"+BATT",
"-BATT",
"/GND_AUDIO",
"/SP+",
"/SP-",
"GNDPWR"
],
"pcb_color": "rgba(0, 0, 0, 0,000)",
"schematic_color": "rgb(0, 0, 0)",
"track_width": 0.5,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
}
],
"meta": {
......
This diff is collapsed.
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