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(kicad_pcb (version 4) (host pcbnew 4.0.7)
(general
(links 65)
(no_connects 0)
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(zones 0)
(modules 33)
(nets 23)
)
(page A4)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user)
)
(setup
(last_trace_width 0.5)
(user_trace_width 0.4)
(user_trace_width 0.5)
(user_trace_width 1)
(trace_clearance 0.2)
(zone_45_only no)
(trace_min 0.2)
(segment_width 0.2)
(edge_width 0.15)
(via_size 0.6)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.15)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 1.524 1.524)
(pad_drill 0.762)
(pad_to_mask_clearance 0.2)
(aux_axis_origin 0 0)
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(visible_elements FFFFFF7F)
(pcbplotparams
(layerselection 0x00030_80000001)
(usegerberextensions false)
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15)
(hpglpenoverlay 2)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory ""))
)
(net 0 "")
(net 1 "Net-(C101-Pad1)")
(net 2 "Net-(C101-Pad2)")
(net 3 "Net-(C102-Pad2)")
(net 4 GND)
(net 5 "Net-(C103-Pad2)")
(net 6 "Net-(C104-Pad2)")
(net 7 "Net-(C105-Pad2)")
(net 8 "Net-(R102-Pad2)")
(net 9 "Net-(C102-Pad1)")
(net 10 "Net-(C106-Pad2)")
(net 11 "Net-(L101-Pad1)")
(net 12 "Net-(L102-Pad2)")
(net 13 "Net-(L105-Pad2)")
(net 14 "Net-(L106-Pad1)")
(net 15 "Net-(R104-Pad2)")
(net 16 "Net-(R105-Pad1)")
(net 17 VDD)
(net 18 "Net-(D101-PadA)")
(net 19 "Net-(D102-Pad1)")
(net 20 "Net-(D102-Pad2)")
(net 21 "Net-(D103-Pad1)")
(net 22 "Net-(D103-Pad2)")
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.25)
(via_dia 0.6)
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(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net GND)
(add_net "Net-(C101-Pad1)")
(add_net "Net-(C101-Pad2)")
(add_net "Net-(C102-Pad1)")
(add_net "Net-(C102-Pad2)")
(add_net "Net-(C103-Pad2)")
(add_net "Net-(C104-Pad2)")
(add_net "Net-(C105-Pad2)")
(add_net "Net-(C106-Pad2)")
(add_net "Net-(D101-PadA)")
(add_net "Net-(D102-Pad1)")
(add_net "Net-(D102-Pad2)")
(add_net "Net-(D103-Pad1)")
(add_net "Net-(D103-Pad2)")
(add_net "Net-(L101-Pad1)")
(add_net "Net-(L102-Pad2)")
(add_net "Net-(L105-Pad2)")
(add_net "Net-(L106-Pad1)")
(add_net "Net-(R102-Pad2)")
(add_net "Net-(R104-Pad2)")
(add_net "Net-(R105-Pad1)")
(add_net VDD)
)
(module txrxdep:0603_m1608 (layer F.Cu) (tedit 5A37FEDB) (tstamp 59C54592)
(at 23.5 20.75 180)
(descr "Resistor SMD 0603, reflow soldering, Vishay (see dcrcw.pdf)")
(tags "resistor 0603")
(path /59C53DB0)
(attr smd)
(effects (font (size 0.5 0.5) (thickness 0.125)))
)
(fp_text value 100p (at 0 1.9 180) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -0.75 0 180) (size 0.5 0.9) (layers F.Cu F.Paste F.Mask)
(net 1 "Net-(C101-Pad1)"))
(pad 2 smd rect (at 0.75 0 180) (size 0.5 0.9) (layers F.Cu F.Paste F.Mask)
(net 2 "Net-(C101-Pad2)"))
(model Resistors_SMD/R_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module txrxdep:0603_m1608 (layer F.Cu) (tedit 5A37FEBF) (tstamp 59C5459A)
(at 23.75 36 180)
(descr "Resistor SMD 0603, reflow soldering, Vishay (see dcrcw.pdf)")
(tags "resistor 0603")
(path /59C53DEA)
(attr smd)
(effects (font (size 0.5 0.5) (thickness 0.125)))
)
(fp_text value 100p (at 0 1.9 180) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -0.75 0 180) (size 0.5 0.9) (layers F.Cu F.Paste F.Mask)
(net 9 "Net-(C102-Pad1)"))
(pad 2 smd rect (at 0.75 0 180) (size 0.5 0.9) (layers F.Cu F.Paste F.Mask)
(net 3 "Net-(C102-Pad2)"))
(model Resistors_SMD/R_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
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