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Kolb.
* Atmel SAMA5:
- SAMA5: Stefan Kolb's change to the SAMV7 Oneshot Timer should also
be applied to the SAMA5 oneshot time since the drivers are identical.
* Atmel SAM3/4:
- SAM3/4: Stefan Kolb's change to the SAMV7 Oneshot Timer should also
be applied to the SAM3/4 oneshot time since the drivers are identical.
* Atmel SAMV7 Drivers:
- SAMV7 TWIHS (as well as SAM3/4 and SAMA5: Ensure that the TWIHS
(i2c) hw get's its clock set when the sequence of
sam_i2cbus_initialize(), sam_i2cbus_uninitialize(), then
sam_i2cbus_initialize() or twi_reset() is called. I found this a
while back in the stm32 family, so there may be more arch-es with
this sort of bug. I suppose any driver that has the notion of "do
not set the freq if it is already set" could be suspect. From David
Sidrane.
- USBHS Device: Remove disabling of whole USB on suspend of USBHS.
This fix removes the disabling of the whole USB peripheral on
suspend interrupt. Its enough to freeze the clock instead. When
disabling the whole peripheral, the next wakeup-interrupt comes up
with an disabled clocking. The unfreeze clock has no effect, because
the master clock is disabled. This makes all registers, including
the IDR unwriteable and the IRQ falls in an endless loop blocking
the whole system. Furthermore the disabling of the peripheral clock
prevents hotplugging or reconnecting the USB. From Frank Benkert.
- MCAN: Fix missing unlock of device in MCAN mcan_txempty(). From
Frank Benkert.
* STMicro STM32:
- STM32 L4 Clocking: Problem with resetting backup domain clears
clocking options set up before in *rcc.c use INITS flag to avoid
magic reg value to detect power up reset state of RTC correct a
problem clearing interrupt flags (they weren't) which prevented an
alarm from ever being used more than once per reset cycle. From
Dave (ziggurat29)
* STMicro STM32 Drivers:
- STM32L4 SPI: That STM32Lr SPI driver is quite different. They now
handle frames of arbitrary size between 4 and 16 bits. It was broken
before a new bit has to be set (RX fifo threshold) to handle <= 8-bit
transactions. If not set, the default is 16-bit packed >=8-bit
frames and the RXNE bit is never set (it is set when 16-bits are
received). weird things as always. This also add 8-bit access
routines to the data register, because a 16-bit access to the data
register when the frame size is below 9 bits is interpreted as a
packed dual frame exchange. Sebastien Lorquet.
- STM32: Correct some bad commits that broke the LTDC display example.
From Marco Krahl.
- STM32 F4 RTC: Fix logic in F4 RTCC driver that prevent ALARM
interrupt. From Neil Hancock.
- STM32 F1 ADC: Fix STM32 ValueLine ADC IRQ number selection. From
David Sidrane.
* STMicro STM32 Boards:
- STM32F429I Discovery: Correct some bad commits that broke the LTDC
display example. From Marco Krahl.
* TI Tiva:
- GPIO Interrupts: Fix a bug of GPIO falling-edge interrupt for tiva.
From Young.
* C Library:
- math: Add a NAN test on 'x' in asin function of lib_asin.c. Suggested
by Pierre-noel Bouteville.
* Build/Configuration System:
- Several Makefiles: Add .PHONY definitions to prevent 'clean up to date'
message weirdness when 'make clean' is done with no .config or
Make.defs file.