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/****************************************************************************
* drivers/wireless/generic/si4463.h
*
Sebastien Lorquet
committed
* Copyright (C) 2017-2018 Sebastien Lorquet. All rights reserved.
* Author: Sebastien Lorquet <sebastien@lorquet.fr>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __DRIVERS_WIRELESS_GENERIC_SI4463_H
#define __DRIVERS_WIRELESS_GENERIC_SI4463_H
#include <nuttx/wqueue.h>
#include <nuttx/wireless/generic/genradio.h>
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#define SI4463_CMD_POWER_UP 0x02
#define SI4463_CMD_NOP 0x00
#define SI4463_CMD_PART_INFO 0x01
#define SI4463_CMD_FUNC_INFO 0x10
#define SI4463_CMD_SET_PROPERTY 0x11
#define SI4463_CMD_GET_PROPERTY 0x12
#define SI4463_CMD_GPIO_PIN_CFG 0x13
#define SI4463_CMD_FIFO_INFO 0x15
#define SI4463_CMD_GET_INT_STATUS 0x20
#define SI4463_CMD_REQUEST_DEVICE_STATE 0x33
#define SI4463_CMD_CHANGE_STATE 0x34
#define SI4463_CMD_READ_CMD_BUFF 0x44
#define SI4463_CMD_FRR_A_READ 0x50
#define SI4463_CMD_FRR_B_READ 0x51
#define SI4463_CMD_FRR_C_READ 0x53
#define SI4463_CMD_FRR_D_READ 0x57
#define SI4463_CMD_IRCAL 0x17
#define SI4463_CMD_IRCAL_MANUAL 0x1A
#define SI4463_CMD_START_TX 0x31
#define SI4463_CMD_TX_HOP 0x37
#define SI4463_CMD_WRITE_TX_FIFO 0x66
#define SI4463_CMD_PACKET_INFO 0x16
#define SI4463_CMD_GET_MODEM_STATUS 0x22
#define SI4463_CMD_START_RX 0x32
#define SI4463_CMD_RX_HOP 0x36
#define SI4463_CMD_READ_RX_FIFO 0x77
#define SI4463_CMD_GET_ADC_READING 0x14
#define SI4463_CMD_GET_PH_STATUS 0x21
#define SI4463_CMD_GET_CHIP_STATUS 0x23
/* Command and response data structures */
/* POWER ON command */
begin_packed_struct
{
uint8_t boot_options;
uint8_t xtal_options;
uint32_t xo_freq;
}
end_packed_struct;
#define PWRUP_BOOTOPT_NO_PATCH 0
#define PWRUP_BOOTOPT_PATCH (1<<7)
#define PWRUP_BOOTOPT_FUNC_SHIFT 0
#define PWRUP_BOOTOPT_FUNC_PRO (0x01<<PWRUP_BOOTOPT_FUNC_SHIFT)
#define PWRUP_XTALOPT_XTAL 0
#define PWRUP_XTALOPT_TCXO (1<<0)
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/* PART INFO response */
begin_packed_struct
struct si4463_rsp_partinfo_s
{
uint8_t chiprev;
uint16_t part;
uint8_t pbuild;
uint16_t id;
uint8_t customer;
uint8_t romid;
}
end_packed_struct;
/* FUNC INFO response */
begin_packed_struct
struct si4463_rsp_funcinfo_s
{
uint8_t revext;
uint8_t revbranch;
uint8_t revint;
uint16_t patch;
uint8_t func;
}
end_packed_struct;
/* SET PROPERTY command */
begin_packed_struct
struct si4463_cmd_setproperty_s
{
uint8_t group;
uint8_t start_prop;
uint8_t data[12];
}
end_packed_struct;
/* GET PROPERTY command */
begin_packed_struct
struct si4463_cmd_getproperty_s
{
uint8_t group;
uint8_t start_prop;
}
end_packed_struct;
/* GET PROPERTY response */
begin_packed_struct
struct si4463_rsp_getproperty_s
{
uint8_t data[16];
}
end_packed_struct;
/* GPIO_PIN_CFG command or response */
begin_packed_struct
struct si4463_cmdrsp_gpiopincfg_s
{
uint8_t gpio[4];
uint8_t nirq;
uint8_t sdo;
uint8_t genconfig;
}
end_packed_struct;
#define PINCFG_PULL_DIS 0
#define PINCFG_PULL_EN (1<<6)
#define PINCFG_DONOTHING 0
#define PINCFG_TRISTATE 1
#define PINCFG_DRIVE0 2
#define PINCFG_DRIVE1 3
#define PINCFG_INPUT 4
#define PINCFG_32K_CLK 5
#define PINCFG_BOOT_CLK 6
#define PINCFG_DIV_CLK 7
#define PINCFG_CTS 8
#define PINCFG_INV_CTS 9
#define PINCFG_CMD_OVERLAP 10
#define PINCFG_SDO 11
#define PINCFG_POR 12
#define PINCFG_CAL_WUT 13
#define PINCFG_WUT 14
#define PINCFG_EN_PA 15
#define PINCFG_TX_DATA_CLK 16
#define PINCFG_RX_DATA_CLK 17
#define PINCFG_EN_LNA 18
#define PINCFG_TX_DATA 19
#define PINCFG_RX_DATA 20
#define PINCFG_RX_RAW_DATA 21
#define PINCFG_ANTENNA_1_SW 22
#define PINCFG_ANTENNA_2_SW 23
#define PINCFG_VALID_PREAMBLE 24
#define PINCFG_INVALID_PREAMBLE 25
#define PINCFG_SYNC_WORD_DETECT 26
#define PINCFG_CCA 27
#define PINCFG_IN_SLEEP 28
#define PINCFG_PKT_TRACE 29
#define PINCFG_TX_RX_DATA_CLK 31
#define PINCFG_TX_STATE 32
#define PINCFG_RX_STATE 33
#define PINCFG_RX_FIFO_FULL 34
#define PINCFG_TX_FIFO_EMPTY 35
#define PINCFG_LOW_BATT 36
#define PINCFG_CCA_LATCH 37
#define PINCFG_HOPPED 38
#define PINCFG_HOP_TABLE_WRAP 39
#define PINCFG_NIRQ_NIRQ 39
#define DRV_STRENGTH_HIGH (0<<5)
#define DRV_STRENGTH_MED_HIGH (1<<5)
#define DRV_STRENGTH_MED_LOW (2<<5)
#define DRV_STRENGTH_LOW (3<<5)
/* FIFO_INFO command */
begin_packed_struct
struct si4463_cmd_fifoinfo_s
{
uint8_t fifo;
}
end_packed_struct;
/* FIFO_INFO response */
begin_packed_struct
struct si4463_rsp_fifoinfo_s
{
uint8_t rx_fifo_count;
uint8_t tx_fifo_space;
}
end_packed_struct;
#define FIFOINFO_CLEAR_TX (1 << 0)
#define FIFOINFO_CLEAR_RX (1 << 1)
/* GET_INT_STATUS command */
begin_packed_struct
struct si4463_cmd_getintstatus_s
{
uint8_t ph_clr_pend;
uint8_t modem_clr_pend;
uint8_t chip_clr_pend;
}
end_packed_struct;
#define INTSTATUS_PH_FILTER_MATCH (1 << 7)
#define INTSTATUS_PH_FILTER_MISS (1 << 6)
#define INTSTATUS_PH_PACKET_SENT (1 << 5)
#define INTSTATUS_PH_PACKET_RX (1 << 4)
#define INTSTATUS_PH_CRC_ERROR (1 << 3)
#define INTSTATUS_PH_ALTCRC_ERROR (1 << 2)
#define INTSTATUS_PH_TX_FIFO_ALMOST_EMPTY (1 << 1)
#define INTSTATUS_PH_RX_FIFO_ALMOST_FULL (1 << 0)
#define INTSTATUS_MODEM_POSTAMBLE_DETECT (1 << 6)
#define INTSTATUS_MODEM_INVALID_SYNC (1 << 5)
#define INTSTATUS_MODEM_RSSI_JUMP (1 << 4)
#define INTSTATUS_MODEM_RSSI (1 << 3)
#define INTSTATUS_MODEM_INVALID_PREAMBLE (1 << 2)
#define INTSTATUS_MODEM_PREAMBLE_DETECT (1 << 1)
#define INTSTATUS_MODEM_SYNC_DETECT (1 << 0)
#define INTSTATUS_CHIP_CAL (1 << 6)
#define INTSTATUS_CHIP_FIFO_UNDEROVERFLOW (1 << 5)
#define INTSTATUS_CHIP_STATE_CHANGE (1 << 4)
#define INTSTTAUS_CHIP_CMD_ERROR (1 << 3)
#define INTSTATUS_CHIP_READY (1 << 2)
#define INTSTATUS_CHIP_LOW_BATT (1 << 1)
#define INTSTATUS_CHIP_WUT (1 << 0)
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/* GET_INT_STATUS response */
begin_packed_struct
struct si4463_rsp_getintstatus_s
{
uint8_t int_pend;
uint8_t int_status;
uint8_t ph_pend;
uint8_t ph_status;
uint8_t modem_pend;
uint8_t modem_status;
uint8_t chip_pend;
uint8_t chip_status;
}
end_packed_struct;
/* REQUEST_DEVICE_STATE response */
begin_packed_struct
struct si4463_rsp_requestdevicestate_s
{
uint8_t curr_state;
uint8_t current_channel;
}
end_packed_struct;
/* CHANGE_STATE command */
begin_packed_struct
struct si4463_cmd_changestate_s
{
uint8_t next_state1;
}
end_packed_struct;
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#define NEWSTATE_NOCHANGE 0
#define NEWSTATE_SLEEP 1
#define NEWSTATE_SPI_ACTIVE 2
#define NEWSTATE_READY 3
#define NEWSTATE_TX_TUNE 5
#define NEWSTATE_RX_TUNE 6
#define NEWSTATE_TX 7
#define NEWSTATE_RX 8
uint8_t searching_step_size;
uint8_t searching_rssi_avg;
uint8_t rx_chain_settings1;
uint8_t rx_chain_setting2;
/* IRCAL_MANUAL command and response */
struct si4463_cmdrsp_ircalmanual_s
uint8_t ircal_amp;
uint8_t ircal_ph;
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struct si4463_cmd_starttx_b1b_s
{
uint8_t channel;
uint8_t condition;
uint16_t txlen;
}
end_packed_struct;
begin_packed_struct
struct si4463_cmd_starttx_c1a_s
uint8_t channel;
uint8_t condition;
uint16_t txlen;
uint8_t txdelay;
uint8_t num_repeat;
#define STARTTX_COND_TXCOMPLETE_NOCHANGE (0 << 4)
#define STARTTX_COND_TXCOMPLETE_SLEEP (1 << 4)
#define STARTTX_COND_TXCOMPLETE_SPI_ACTIVE (2 << 4)
#define STARTTX_COND_TXCOMPLETE_READY (3 << 4)
#define STARTTX_COND_TXCOMPLETE_READY2 (4 << 4)
#define STARTTX_COND_TXCOMPLETE_TX_TUNE (5 << 4)
#define STARTTX_COND_TXCOMPLETE_RX_TUNE (6 << 4)
#define STARTTX_COND_TXCOMPLETE_RESERVED (7 << 4)
#define STARTTX_COND_TXCOMPLETE_RX (8 << 4)
#define STARTTX_COND_RETRANSMIT (1 << 2)
#define STARTTX_COND_START_IMMEDIATE (0 << 0)
#define STARTTX_COND_START_WUT (1 << 0)
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/* TX_HOP command */
begin_packed_struct
struct si4463_cmd_txhop_s
{
uint8_t inte;
uint8_t frac[3];
uint16_t vco_cnt;
uint16_t pll_settle_time;
}
end_packed_struct;
/* PACKET_INFO command */
begin_packed_struct
struct si4463_cmd_packetinfo_s
{
uint8_t field_number;
uint16_t len;
uint16_t len_diff;
}
end_packed_struct;
/* PACKET_INFO response */
begin_packed_struct
struct si4463_rsp_packetinfo_s
{
uint16_t length;
}
end_packed_struct;
/* GET_MODEM_STATUS command */
begin_packed_struct
struct si4463_cmd_getmodemstatus_s
{
uint8_t modem_clr_pend;
}
end_packed_struct;
/* GET_MODEM_STATUS response */
begin_packed_struct
struct si4463_rsp_getmodemstatus_s
{
uint8_t modem_pend;
uint8_t modem_status;
uint8_t curr_rssi;
uint8_t latch_rssi;
uint8_t ant1_rssi;
uint8_t ant2_rssi;
uint16_t afc_freq_offset;
}
end_packed_struct;
/* START_RX command */
begin_packed_struct
struct si4463_cmd_startrx_s
{
uint8_t channel;
uint8_t condition;
uint16_t rx_len;
uint8_t next_state1; /* RX timeout */
uint8_t next_state2; /* RX valid */
uint8_t next_state3; /* RX invalid */
}
end_packed_struct;
#define STARTRX_CONDITION_WUT (1 << 0)
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#define STARTRX_CONDITION_IMMEDIATE (0 << 0)
#define STARTRX_STATE_NOCHANGE 0
#define STARTRX_STATE_SLEEP 1
#define STARTRX_STATE_SPI_ACTIVE 2
#define STARTRX_STATE_READY 3
#define STARTRX_STATE_READY2 4
#define STARTRX_STATE_TX_TUNE 5
#define STARTRX_STATE_RX_TUNE 6
#define STARTRX_STATE_TX 7
#define STARTRX_STATE_RX 8
/* RX_HOP command */
begin_packed_struct
struct si4463_cmd_rxhop_s
{
uint8_t inte;
uint8_t frac[3];
uint16_t vco_cnt;
}
end_packed_struct;
/* GET_ADC_READING command */
begin_packed_struct
struct si4463_cmd_getadcreading_s
{
uint8_t adc_en;
uint8_t adc_cfg;
}
end_packed_struct;
#define ADC_EN_GPIO_PIN_SHIFT 0
#define ADC_EN_GPIO_PIN_MASK (3 << ADC_EN_GPIO_PIN_SHIFT)
#define ADC_EN_GPIO_PIN(n) ((n&3) << ADC_EN_GPIO_PIN_SHIFT)
#define ADC_EN_GPIO_EN (1 << 2)
#define ADC_EN_BATTERY_VOLTAGE_EN (1 << 3)
#define ADC_EN_TEMPERATURE_EN (1 << 4)
#define ADC_CFG_UDTIME_SHIFT 4
#define ADC_CFG_UDTIME_MASK (15 << ADC_CFG_UDTIME_SHIFT)
#define ADC_CFG_UDTIME_305HZ (0x0C << ADC_CFG_UDTIME_SHIFT)
#define ADC_CFG_UDTIME_1220HZ (0x0A << ADC_CFG_UDTIME_SHIFT)
#define ADC_CFG_GPIOATT_SHIFT 0
#define ADC_CFG_GPIOATT_MASK (15 << ADC_CFG_GPIOATT_SHIFT)
#define ADC_CFG_GPIOATT_0P8 ( 0 << ADC_CFG_GPIOATT_SHIFT)
#define ADC_CFG_GPIOATT_1P6 ( 4 << ADC_CFG_GPIOATT_SHIFT)
#define ADC_CFG_GPIOATT_3P2 ( 5 << ADC_CFG_GPIOATT_SHIFT)
#define ADC_CFG_GPIOATT_2P4 ( 8 << ADC_CFG_GPIOATT_SHIFT)
#define ADC_CFG_GPIOATT_3P6 ( 9 << ADC_CFG_GPIOATT_SHIFT)
/* GET_ADC_READING response */
begin_packed_struct
struct si4463_rsp_getadcreading_s
{
uint16_t gpio_adc;
uint16_t battery_adc;
uint16_t temp_adc;
}
end_packed_struct;
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/* GET_PH_STATUS command */
begin_packed_struct
struct si4463_cmd_getphstatus_s
{
uint8_t ph_clr_pend;
}
end_packed_struct;
/* GET_PH_STATUS response */
begin_packed_struct
struct si4463_rsp_getphstatus_s
{
uint8_t ph_pend;
uint8_t ph_status;
}
end_packed_struct;
/* GET_CHIP_STATUS command */
begin_packed_struct
struct si4463_cmd_getchipstatus_s
{
uint8_t chip_clr_pend;
}
end_packed_struct;
/* GET_CHIP_STATUS response */
begin_packed_struct
struct si4463_rsp_getchipstatus_s
{
uint8_t chip_pend;
uint8_t chip_status;
uint8_t cmd_err_status;
uint8_t cmd_err_cmd_id;
/* CHIP_STATUS bit definitions for command and response */
#define CHIP_STATUS_CAL_PEND (1<<6)
#define CHIP_STATUS_FIFO_OVERUNDERFLOW (1<<5)
#define CHIP_STATUS_STATE_CHANGE (1<<4)
#define CHIP_STATUS_CMD_ERROR (1<<3)
#define CHIP_STATUS_CHIP_READY (1<<2)
#define CHIP_STATUS_LOW_BATT (1<<1)
#define CHIP_STATUS_WUT (1<<0)
#define CMD_ERROR_OK 0
#define CMD_ERROR_BAD_COMMAND 16
#define CMD_ERROR_BAD_ARG 17
#define CMD_ERROR_COMMAND_BUSY 18
#define CMD_ERROR_INVALID_STATE 19
#define CMD_ERROR_BAD_BOOTMODE 49
#define CMD_ERROR_BAD_PROPERTY 64
#define CMD_ERROR_TIMEOUT 240 /* UNDOCUMENTED, discovered experimentally while testing tx*/
/* Properties */
#define SI4463_PROP_GLOBAL_XO_TUNE 0x0000
#define SI4463_PROP_GLOBAL_CLK_CFG 0x0001
#define SI4463_PROP_GLOBAL_LOW_BATT_THRES 0x0002
#define SI4463_PROP_GLOBAL_CONFIG 0x0003
#define SI4463_PROP_GLOBAL_WUT_CONFIG 0x0004
#define SI4463_PROP_GLOBAL_WUT_M_0 0x0005
#define SI4463_PROP_GLOBAL_WUT_M_1 0x0006
#define SI4463_PROP_GLOBAL_WUT_R 0x0007
#define SI4463_PROP_GLOBAL_WUT_LDC 0x0008
#define SI4463_PROP_GLOBAL_WUT_CAL 0x0009
#define SI4463_PROP_INT_CTL_ENABLE 0x0100
#define SI4463_PROP_INT_CTL_PH_ENABLE 0x0101
#define SI4463_PROP_INT_CTL_MODEM_ENABLE 0x0102
#define SI4463_PROP_INT_CTL_CHIP_ENABLE 0x0103
#define SI4463_PROP_FRR_CTL_A_MODE 0x0200
#define SI4463_PROP_FRR_CTL_B_MODE 0x0201
#define SI4463_PROP_FRR_CTL_C_MODE 0x0202
#define SI4463_PROP_FRR_CTL_D_MODE 0x0203
#define SI4463_PROP_PREAMBLE_TX_LENGTH 0x1000
#define SI4463_PROP_PREAMBLE_CONFIG_STD_1 0x1001
#define SI4463_PROP_PREAMBLE_PATTERN_0 0x1005
#define SI4463_PROP_PREAMBLE_PATTERN_1 0x1006
#define SI4463_PROP_PREAMBLE_PATTERN_2 0x1007
#define SI4463_PROP_PREAMBLE_PATTERN_3 0x1008
#define SI4463_PROP_PREAMBLE_POSTAMBLE_CONFIG 0x1009
#define SI4463_PROP_PREAMBLE_POSTAMBLE_PATTERN_0 0x100A
#define SI4463_PROP_PREAMBLE_POSTAMBLE_PATTERN_1 0x100B
#define SI4463_PROP_PREAMBLE_POSTAMBLE_PATTERN_2 0x100C
#define SI4463_PROP_PREAMBLE_POSTAMBLE_PATTERN_3 0x100D
#define SI4463_PROP_SYNC_CONFIG 0x1100
#define SI4463_PROP_SYNC_BITS_0 0x1101
#define SI4463_PROP_SYNC_BITS_1 0x1102
#define SI4463_PROP_SYNC_BITS_2 0x1103
#define SI4463_PROP_SYNC_BITS_3 0x1104
#define SI4463_PROP_SYNC_CONFIG2 0x1105
#define SI4463_PROP_PKT_CRC_CONFIG 0x1200
#define SI4463_PROP_PKT_WHT_POLY_0 0x1201
#define SI4463_PROP_PKT_WHT_POLY_1 0x1202
#define SI4463_PROP_PKT_WHT_SEED_0 0x1203
#define SI4463_PROP_PKT_WHT_SEED_1 0x1204
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#define SI4463_PROP_PKT_WHT_BIT_NUM 0x1205
#define SI4463_PROP_PKT_CONFIG1 0x1206
#define SI4463_PROP_PKT_CONFIG2 0x1207
#define SI4463_PROP_PKT_LEN 0x1208
#define SI4463_PROP_PKT_LEN_FIELD_SOURCE 0x1209
#define SI4463_PROP_PKT_LEN_ADJUST 0x120A
#define SI4463_PROP_PKT_TX_THRESHOLD 0x120B
#define SI4463_PROP_PKT_RX_THRESHOLD 0x120C
#define SI4463_PROP_PKT_FIELD_1_LENGTH_0 0x120D
#define SI4463_PROP_PKT_FIELD_1_LENGTH_1 0x120E
#define SI4463_PROP_PKT_FIELD_1_CONFIG 0x120F
#define SI4463_PROP_PKT_FIELD_1_CRC_CONFIG 0x1210
#define SI4463_PROP_PKT_FIELD_2_LENGTH_0 0x1211
#define SI4463_PROP_PKT_FIELD_2_LENGTH_1 0x1212
#define SI4463_PROP_PKT_FIELD_2_CONFIG 0x1213
#define SI4463_PROP_PKT_FIELD_2_CRC_CONFIG 0x1214
#define SI4463_PROP_PKT_FIELD_3_LENGTH_0 0x1215
#define SI4463_PROP_PKT_FIELD_3_LENGTH_1 0x1216
#define SI4463_PROP_PKT_FIELD_3_CONFIG 0x1217
#define SI4463_PROP_PKT_FIELD_3_CRC_CONFIG 0x1218
#define SI4463_PROP_PKT_FIELD_4_LENGTH_0 0x1219
#define SI4463_PROP_PKT_FIELD_4_LENGTH_1 0x121A
#define SI4463_PROP_PKT_FIELD_4_CONFIG 0x121B
#define SI4463_PROP_PKT_FIELD_4_CRC_CONFIG 0x121C
#define SI4463_PROP_PKT_FIELD_5_LENGTH_0 0x121D
#define SI4463_PROP_PKT_FIELD_5_LENGTH_1 0x121E
#define SI4463_PROP_PKT_FIELD_5_CONFIG 0x121F
#define SI4463_PROP_PKT_FIELD_5_CRC_CONFIG 0x1220
#define SI4463_PROP_PKT_RX_FIELD_1_LENGTH_0 0x1221
#define SI4463_PROP_PKT_RX_FIELD_1_LENGTH_1 0x1222
#define SI4463_PROP_PKT_RX_FIELD_1_CONFIG 0x1223
#define SI4463_PROP_PKT_RX_FIELD_1_CRC_CONFIG 0x1224
#define SI4463_PROP_PKT_RX_FIELD_2_LENGTH_0 0x1225
#define SI4463_PROP_PKT_RX_FIELD_2_LENGTH_1 0x1226
#define SI4463_PROP_PKT_RX_FIELD_2_CONFIG 0x1227
#define SI4463_PROP_PKT_RX_FIELD_2_CRC_CONFIG 0x1228
#define SI4463_PROP_PKT_RX_FIELD_3_LENGTH_0 0x1229
#define SI4463_PROP_PKT_RX_FIELD_3_LENGTH_1 0x122A
#define SI4463_PROP_PKT_RX_FIELD_3_CONFIG 0x122B
#define SI4463_PROP_PKT_RX_FIELD_3_CRC_CONFIG 0x122C
#define SI4463_PROP_PKT_RX_FIELD_4_LENGTH_0 0x122D
#define SI4463_PROP_PKT_RX_FIELD_4_LENGTH_1 0x122E
#define SI4463_PROP_PKT_RX_FIELD_4_CONFIG 0x122F
#define SI4463_PROP_PKT_RX_FIELD_4_CRC_CONFIG 0x1230
#define SI4463_PROP_PKT_RX_FIELD_5_LENGTH_0 0x1231
#define SI4463_PROP_PKT_RX_FIELD_5_LENGTH_1 0x1232
#define SI4463_PROP_PKT_RX_FIELD_5_CONFIG 0x1233
#define SI4463_PROP_PKT_RX_FIELD_5_CRC_CONFIG 0x1234
#define SI4463_PROP_PKT_CRC_SEED_0 0x1236
#define SI4463_PROP_PKT_CRC_SEED_1 0x1237
#define SI4463_PROP_PKT_CRC_SEED_2 0x1238
#define SI4463_PROP_PKT_CRC_SEED_3 0x1239
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#define SI4463_PROP_MODEM_MOD_TYPE 0x2000
#define SI4463_PROP_MODEM_MAP_CONTROL 0x2001
#define SI4463_PROP_MODEM_DSM_CTRL 0x2002
#define SI4463_PROP_MODEM_DATA_RATE_0 0x2003
#define SI4463_PROP_MODEM_DATA_RATE_1 0x2004
#define SI4463_PROP_MODEM_DATA_RATE_2 0x2005
#define SI4463_PROP_MODEM_TX_NCO_MODE_0 0x2006
#define SI4463_PROP_MODEM_TX_NCO_MODE_1 0x2007
#define SI4463_PROP_MODEM_TX_NCO_MODE_2 0x2008
#define SI4463_PROP_MODEM_TX_NCO_MODE_3 0x2009
#define SI4463_PROP_MODEM_FREQ_DEV_0 0x200A
#define SI4463_PROP_MODEM_FREQ_DEV_1 0x200B
#define SI4463_PROP_MODEM_FREQ_DEV_2 0x200C
#define SI4463_PROP_MODEM_FREQ_OFFSET_0 0x200D
#define SI4463_PROP_MODEM_FREQ_OFFSET_1 0x200E
#define SI4463_PROP_MODEM_TX_FILTER_COEFF_8 0x200F
#define SI4463_PROP_MODEM_TX_FILTER_COEFF_7 0x2010
#define SI4463_PROP_MODEM_TX_FILTER_COEFF_6 0x2011
#define SI4463_PROP_MODEM_TX_FILTER_COEFF_5 0x2012
#define SI4463_PROP_MODEM_TX_FILTER_COEFF_4 0x2013
#define SI4463_PROP_MODEM_TX_FILTER_COEFF_3 0x2014
#define SI4463_PROP_MODEM_TX_FILTER_COEFF_2 0x2015
#define SI4463_PROP_MODEM_TX_FILTER_COEFF_1 0x2016
#define SI4463_PROP_MODEM_TX_FILTER_COEFF_0 0x2017
#define SI4463_PROP_MODEM_TX_RAMP_DELAY 0x2018
#define SI4463_PROP_MODEM_MDM_CTRL 0x2019
#define SI4463_PROP_MODEM_IF_CONTROL 0x201A
#define SI4463_PROP_MODEM_IF_FREQ_0 0x201B
#define SI4463_PROP_MODEM_IF_FREQ_1 0x201C
#define SI4463_PROP_MODEM_IF_FREQ_2 0x201D
#define SI4463_PROP_MODEM_DECOMATION_CFG1 0x201E
#define SI4463_PROP_MODEM_DECOMATION_CFG0 0x201F
#define SI4463_PROP_MODEM_DECOMATION_CFG2 0x2020
#define SI4463_PROP_MODEM_IFPKD_THRESHOLDS 0x2021
#define SI4463_PROP_MODEM_BCR_OSR_0 0x2022
#define SI4463_PROP_MODEM_BCR_OSR_1 0x2023
#define SI4463_PROP_MODEM_BCR_NCO_OFFSET_0 0x2024
#define SI4463_PROP_MODEM_BCR_NCO_OFFSET_1 0x2025
#define SI4463_PROP_MODEM_BCR_NCO_OFFSET_2 0x2026
#define SI4463_PROP_MODEM_BCR_GAIN_0 0x2027
#define SI4463_PROP_MODEM_BCR_GAIN_1 0x2028
#define SI4463_PROP_MODEM_BCR_GEAR 0x2029
#define SI4463_PROP_MODEM_BCR_MISC1 0x202A
#define SI4463_PROP_MODEM_BCR_MISC0 0x202B
#define SI4463_PROP_MODEM_AFC_GEAR 0x202C
#define SI4463_PROP_MODEM_AFC_WAIT 0x202D
#define SI4463_PROP_MODEM_AFC_GAIN_0 0x202E
#define SI4463_PROP_MODEM_AFC_GAIN_1 0x202F
#define SI4463_PROP_MODEM_AFC_LIMITER_0 0x2030
#define SI4463_PROP_MODEM_AFC_LIMITER_1 0x2031
#define SI4463_PROP_MODEM_AFC_MISC 0x2032
#define SI4463_PROP_MODEM_AFC_ZIFOFF 0x2033
#define SI4463_PROP_MODEM_ADC_CTRL 0x2034
#define SI4463_PROP_MODEM_AGC_CONTROL 0x2035
#define SI4463_PROP_MODEM_AGC_WINDOW_SIZE 0x2038
#define SI4463_PROP_MODEM_AGC_RFPD_DECAY 0x2039
#define SI4463_PROP_MODEM_AGC_IFPD_DECAY 0x203A
#define SI4463_PROP_MODEM_FSK4_GAIN1 0x203B
#define SI4463_PROP_MODEM_FSK4_GAIN0 0x203C
#define SI4463_PROP_MODEM_FSK4_TH_0 0x203D
#define SI4463_PROP_MODEM_FSK4_TH_1 0x203E
#define SI4463_PROP_MODEM_FSK4_MAP 0x203F
#define SI4463_PROP_MODEM_OOK_PDTC 0x2040
#define SI4463_PROP_MODEM_OOK_BLOPK 0x2041
#define SI4463_PROP_MODEM_OOK_CNT1 0x2042
#define SI4463_PROP_MODEM_OOK_MISC 0x2043
#define SI4463_PROP_MODEM_RAW_CONTROL 0x2045
#define SI4463_PROP_MODEM_RAW_EYE_0 0x2046
#define SI4463_PROP_MODEM_RAW_EYE_1 0x2047
#define SI4463_PROP_MODEM_ANT_DIV_MODE 0x2048
#define SI4463_PROP_MODEM_ANT_DIV_CONTROL 0x2049
#define SI4463_PROP_MODEM_RSSI_THRESH 0x204A
#define SI4463_PROP_MODEM_RSSI_JUMP_THRESH 0x204B
#define SI4463_PROP_MODEM_RSSI_CONTROL 0x204C
#define SI4463_PROP_MODEM_RSSI_CONTROL2 0x204D
#define SI4463_PROP_MODEM_RSSI_COMP 0x204E
#define SI4463_PROP_MODEM_RAW_SEARCH2 0x2050
#define SI4463_PROP_MODEM_CLKGEN_BAND 0x2051
#define SI4463_PROP_MODEM_SPIKE_DET 0x2054
#define SI4463_PROP_MODEM_ONE_SHOT_AFC 0x2055
#define SI4463_PROP_MODEM_RSSI_HYSTERESIS 0x2056
#define SI4463_PROP_MODEM_RSSI_MUTE 0x2057
#define SI4463_PROP_MODEM_FAST_RSSI_DELAY 0x2058
#define SI4463_PROP_MODEM_PSM_0 0x2059
#define SI4463_PROP_MODEM_PSM_1 0x205A
#define SI4463_PROP_MODEM_DSA_CTRL1 0x205B
#define SI4463_PROP_MODEM_DSA_CTRL2 0x205C
#define SI4463_PROP_MODEM_DSA_QUAL 0x205D
#define SI4463_PROP_MODEM_DSA_RSSI 0x205E
#define SI4463_PROP_MODEM_DSA_MISC 0x205F
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#define SI4463_PROP_MODEM_CHFLT_RX1_CHFLT_COE_0 0x2100
#define SI4463_PROP_MODEM_CHFLT_RX1_CHFLT_COE_1 0x2101
#define SI4463_PROP_MODEM_CHFLT_RX1_CHFLT_COE_2 0x2102
#define SI4463_PROP_MODEM_CHFLT_RX1_CHFLT_COE_3 0x2103
#define SI4463_PROP_MODEM_CHFLT_RX1_CHFLT_COE_4 0x2104
#define SI4463_PROP_MODEM_CHFLT_RX1_CHFLT_COE_5 0x2105
#define SI4463_PROP_MODEM_CHFLT_RX1_CHFLT_COE_6 0x2106
#define SI4463_PROP_MODEM_CHFLT_RX1_CHFLT_COE_7 0x2107
#define SI4463_PROP_MODEM_CHFLT_RX1_CHFLT_COE_8 0x2108
#define SI4463_PROP_MODEM_CHFLT_RX1_CHFLT_COE_9 0x2109
#define SI4463_PROP_MODEM_CHFLT_RX1_CHFLT_COE_10 0x210A
#define SI4463_PROP_MODEM_CHFLT_RX1_CHFLT_COE_11 0x210B
#define SI4463_PROP_MODEM_CHFLT_RX1_CHFLT_COE_12 0x210C
#define SI4463_PROP_MODEM_CHFLT_RX1_CHFLT_COE_13 0x210D
#define SI4463_PROP_MODEM_CHFLT_RX1_CHFLT_COE_14 0x210E
#define SI4463_PROP_MODEM_CHFLT_RX1_CHFLT_COE_15 0x210F
#define SI4463_PROP_MODEM_CHFLT_RX1_CHFLT_COE_16 0x2110
#define SI4463_PROP_MODEM_CHFLT_RX1_CHFLT_COE_17 0x2111
#define SI4463_PROP_MODEM_CHFLT_RX2_CHFLT_COE_0 0x2112
#define SI4463_PROP_MODEM_CHFLT_RX2_CHFLT_COE_1 0x2113
#define SI4463_PROP_MODEM_CHFLT_RX2_CHFLT_COE_2 0x2114
#define SI4463_PROP_MODEM_CHFLT_RX2_CHFLT_COE_3 0x2115
#define SI4463_PROP_MODEM_CHFLT_RX2_CHFLT_COE_4 0x2116
#define SI4463_PROP_MODEM_CHFLT_RX2_CHFLT_COE_5 0x2117
#define SI4463_PROP_MODEM_CHFLT_RX2_CHFLT_COE_6 0x2118
#define SI4463_PROP_MODEM_CHFLT_RX2_CHFLT_COE_7 0x2119
#define SI4463_PROP_MODEM_CHFLT_RX2_CHFLT_COE_8 0x211A
#define SI4463_PROP_MODEM_CHFLT_RX2_CHFLT_COE_9 0x211B
#define SI4463_PROP_MODEM_CHFLT_RX2_CHFLT_COE_10 0x211C
#define SI4463_PROP_MODEM_CHFLT_RX2_CHFLT_COE_11 0x211D
#define SI4463_PROP_MODEM_CHFLT_RX2_CHFLT_COE_12 0x211E
#define SI4463_PROP_MODEM_CHFLT_RX2_CHFLT_COE_13 0x211F
#define SI4463_PROP_MODEM_CHFLT_RX2_CHFLT_COE_14 0x2120
#define SI4463_PROP_MODEM_CHFLT_RX2_CHFLT_COE_15 0x2121
#define SI4463_PROP_MODEM_CHFLT_RX2_CHFLT_COE_16 0x2122
#define SI4463_PROP_MODEM_CHFLT_RX2_CHFLT_COE_17 0x2123
#define SI4463_PROP_PA_MODE 0x2200
#define SI4463_PROP_PA_PWR_LVL 0x2201
#define SI4463_PROP_PA_BIAS_CLKDUTY 0x2202
#define SI4463_PROP_PA_TC 0x2203
#define SI4463_PROP_PA_RAMP_EX 0x2204
#define SI4463_PROP_PA_RAMP_DOWN_DELAY 0x2205
#define SI4463_PROP_PA_DIG_PWR_SEQ_CONFIG 0x2206
#define SI4463_PROP_SYNTH_PFDCP_CPFF 0x2300
#define SI4463_PROP_SYNTH_PFDCP_CPINT 0x2301
#define SI4463_PROP_SYNTH_VCO_KV 0x2302
#define SI4463_PROP_SYNTH_LPFILT3 0x2303
#define SI4463_PROP_SYNTH_LPFILT2 0x2304
#define SI4463_PROP_SYNTH_LPFILT1 0x2305
#define SI4463_PROP_SYNTH_LPFILT0 0x2306
#define SI4463_PROP_SYNTH_VCO_KVCAL 0x2307
#define SI4463_PROP_MATCH_VALUE_1 0x3000
#define SI4463_PROP_MATCH_MASK_1 0x3001
#define SI4463_PROP_MATCH_CTRL_1 0x3002
#define SI4463_PROP_MATCH_VALUE_2 0x3003
#define SI4463_PROP_MATCH_MASK_2 0x3004
#define SI4463_PROP_MATCH_CTRL_2 0x3005
#define SI4463_PROP_MATCH_VALUE_3 0x3006
#define SI4463_PROP_MATCH_MASK_3 0x3007
#define SI4463_PROP_MATCH_CTRL_3 0x3008
#define SI4463_PROP_MATCH_VALUE_4 0x3009
#define SI4463_PROP_MATCH_MASK_4 0x300A
#define SI4463_PROP_MATCH_CTRL_4 0x300B
#define SI4463_PROP_FREQ_CONTROL_INTE 0x4000
#define SI4463_PROP_FREQ_CONTROL_FRAC_0 0x4001
#define SI4463_PROP_FREQ_CONTROL_FRAC_1 0x4002
#define SI4463_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_0 0x4003
#define SI4463_PROP_FREQ_CONTROL_CHANNEL_STEP_SIZE_1 0x4004
#define SI4463_PROP_FREQ_CONTROL_W_SIZE 0x4005
#define SI4463_PROP_FREQ_CONTROL_VCOCNT_RX_ADJ 0x4006
#define SI4463_PROP_RX_HOP_CONTROL 0x5000
#define SI4463_PROP_RX_HOP_TABLE_SIZE 0x5001
#define SI4463_PROP_RX_HOP_TABLE_ENTRY_0 0x5002
#define SI4463_PROP_RX_HOP_TABLE_ENTRY_COUNT 64
#define SI4463_PROP_PTI_CTL 0xf000
#define SI4463_PROP_PTI_BAUD_0 0xf001
#define SI4463_PROP_PTI_BAUD_1 0xf002
#define SI4463_PROP_PTI_LOG_EN 0xf003
/* Bit definitions for properties */
/* 0x0003 GLOBAL_CONFIG */
#define GLOBAL_CONFIG_POWER_HIGH_PERF 0
#define GLOBAL_CONFIG_POWER_LOW (1 << 0)
#define GLOBAL_CONFIG_PROTOCOL_SHIFT 1
#define GLOBAL_CONFIG_PROTOCOL_MASK (7 << GLOBAL_CONFIG_PROTOCOL_SHIFT)
#define GLOBAL_CONFIG_PROTOCOL_GENERIC (0 << GLOBAL_CONFIG_PROTOCOL_SHIFT)
#define GLOBAL_CONFIG_PROTOCOL_IE154G (1 << GLOBAL_CONFIG_PROTOCOL_SHIFT)
#define GLOBAL_CONFIG_FIFO_SPLIT 0 /* Use two 64-byte FIFOs */
#define GLOBAL_CONFIG_FIFO_HALFDUPLEX (1 << 4) /* Use one big 129-byte FIFO */
#define GLOBAL_CONFIG_SEQUENCER_GUARANTEED 0 /* START_TX to actual TX fixed */
#define GLOBAL_CONFIG_SEQUENCER_QUICK (1 << 5) /* START_TX to actual TX quicker but variable */
#define GLOBAL_CONFIG_RESERVED (1 << 6) /* Must be set */
/* FRR */
#define FRR_DISABLED 0
#define FRR_INT_STATUS 1
#define FRR_INT_PEND 2
#define FRR_INT_PH_STATUS 3
#define FRR_INT_PH_PEND 4
#define FRR_INT_MODEM_STATUS 5
#define FRR_INT_MODEM_PEND 6
#define FRR_INT_CHIP_STATUS 7
#define FRR_INT_CHIP_PEND 8
#define FRR_CURRENT_STATE 9
#define FRR_LATCHED_RSSI 10
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/* 0x0100 SI4463_PROP_INT_CTL_ENABLE */
#define INT_CTL_PH_INT (1 << 0)
#define INT_CTL_MODEM_INT (1 << 1)
#define INT_CTL_CHIP_INT (1 << 2)
/* 0x0101 SI4463_PROP_INT_CTL_PH_ENABLE */
#define INT_CTL_PH_RX_FIFO_ALMOST_FULL (1 << 0)
#define INT_CTL_PH_TX_FIFO_ALMOST_EMPTY (1 << 1)
#define INT_CTL_PH_CRC_ERROR (1 << 3)
#define INT_CTL_PH_PACKET_RX (1 << 4)
#define INT_CTL_PH_PACKET_SENT (1 << 5)
#define INT_CTL_PH_FILTER_MISS (1 << 6)
#define INT_CTL_PH_FILTER_MATCH (1 << 7)
/* 0x0102 SI4463_PROP_INT_CTL_MODEM_ENABLE */
#define INT_CTL_MODEM_SYNC_DETECT (1 << 0)
#define INT_CTL_MODEM_PREAMBLE_DETECT (1 << 1)
#define INT_CTL_MODEM_INVALID_PREAMBLE (1 << 2)
#define INT_CTL_MODEM_RSSI (1 << 3)
#define INT_CTL_MODEM_RSSI_JUMP (1 << 4)
#define INT_CTL_MODEM_INVALID_SYNC (1 << 5)
#define INT_CTL_MODEM_POSTAMBLE_DETECT (1 << 6)
#define INT_CTL_MODEM_RSSI_LATCH (1 << 7)
/* SI4463_PROP_INT_CTL_CHIP_ENABLE 0x0103 */
#define INT_CTL_CHIP_WUT (1 << 0)
#define INT_CTL_CHIP_LOW_BATT (1 << 1)
#define INT_CTL_CHIP_CHIP_READY (1 << 2)
#define INT_CTL_CHIP_CMD_ERROR (1 << 3)
#define INT_CTL_CHIP_STATE_CHANGE (1 << 4)
#define INT_CTL_CHIP_FIFO_UNDERFLOW_OVERFLOW_ERROR (1 << 5)
#define INT_CTL_CHIP_CAL (1 << 6)
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/* 0x1001 PREAMBLE_CONFIG_STD_1*/
#define PREAMBLE_CONFIG_STD_1_SKIP_SYNC_TIMEOUT_DISABLE 0
#define PREAMBLE_CONFIG_STD_1_SKIP_SYNC_TIMEOUT_ENABLE (1 << 7)
#define PREAMBLE_CONFIG_STD_1_RX_THRES_SHIFT 0
#define PREAMBLE_CONFIG_STD_1_RX_THRES_MASK (0x7F << PREAMBLE_CONFIG_STD_1_RX_THRES_SHIFT)
#define PREAMBLE_CONFIG_STD_1_RX_THRES(n) (((n)&0x7F) << PREAMBLE_CONFIG_STD_1_RX_THRES_SHIFT)
#define SI4463_PROP_PREAMBLE_CONFIG_NSTD 0x1002
#define SI4463_PROP_PREAMBLE_CONFIG_STD_2 0x1003
#define SI4463_PROP_PREAMBLE_CONFIG 0x1004
/* 0x1004 PREAMBLE_CONFIG */
#define PREAMBLE_CONFIG_RX_PREAM_SRC_STANDARD 0
#define PREAMBLE_CONFIG_RX_PREAM_SRC_DSA_ONLY (1 << 7)
#define PREAMBLE_CONFIG_PREAM_FIRST_0 0
#define PREAMBLE_CONFIG_PREAM_FIRST_1 (1 << 5)
#define PREAMBLE_CONFIG_LENGTH_CONFIG_NIBBLE 0
#define PREAMBLE_CONFIG_LENGTH_CONFIG_BYTE (1 << 4)
#define PREAMBLE_CONFIG_MAN_NO_CON 0
#define PREAMBLE_CONFIG_MAN_CONST (1 << 3)
#define PREAMBLE_CONFIG_MAN_DISABLE 0
#define PREAMBLE_CONFIG_MAN_ENABLE (1 << 2)
#define PREAMBLE_CONFIG_STANDARD_PREAM_SHIFT 0
#define PREAMBLE_CONFIG_STANDARD_PREAM_MASK (3 << PREAMBLE_CONFIG_STANDARD_PREAM_SHIFT)
#define PREAMBLE_CONFIG_PRE_NS (0 << PREAMBLE_CONFIG_STANDARD_PREAM_SHIFT)
#define PREAMBLE_CONFIG_PRE_1010 (1 << PREAMBLE_CONFIG_STANDARD_PREAM_SHIFT)
#define PREAMBLE_CONFIG_PRE_0101 (2 << PREAMBLE_CONFIG_STANDARD_PREAM_SHIFT)
/* 0x1100 SYNC_CONFIG */
#define SYNC_CONFIG_LENGTH_SHIFT 0
#define SYNC_CONFIG_LENGTH_MASK ( 3 << SYNC_CONFIG_LENGTH_SHIFT)
#define SYNC_CONFIG_LENGTH(n) (((n)&3) << SYNC_CONFIG_LENGTH_SHIFT)
#define SYNC_CONFIG_MANCH (1 << 2)
#define SYNC_CONFIG_4FSK (1 << 3)
#define SYNC_CONFIG_RX_ERRORS_SHIFT 4
#define SYNC_CONFIG_RX_ERRORS_MASK (7 << SYNC_CONFIG_RX_ERRORS_SHIFT)
#define SYNC_CONFIG_RX_ERRORS(n) (((n)&7) << SYNC_CONFIG_RX_ERRORS_SHIFT)
#define SYNC_CONFIG_SKIP_TX (1 << 7)
/* 0x1105 SYNC_CONFIG2 */
#define SYNC_CONFIG2_LENGTH_SUB_SHIFT 0
#define SYNC_CONFIG2_LENGTH_SUB_MASK (3 << SYNC_CONFIG2_LENGTH_SUB_SHIFT)
#define SYNC_CONFIG2_LENGTH_SUB(n) (((n)&3) << SYNC_CONFIG2_LENGTH_SUB_SHIFT)
#define SYNC_CONFIG2_SYNC_ERROR_BEGIN (1<<7)