Add support for fast GPIO on lpc214x

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@1766 42af7a65-404d-4744-a932-0658087f49c3

ChangeLog

@@ -714,4 +714,6 @@
 	  for verifying this.
 	* Began adding support for the MicroMint Eagle100 board.  This board has a
 	  Luminary LM3S6918 Cortex-M3.
+	* Add configuration option to enable fast GPIO (vs. legacy, "slow" GPIO) for
+	  LPC214x.
 

Documentation/NuttX.html

@@ -8,7 +8,7 @@
   <tr align="center" bgcolor="#e4e4e4">
     <td>
       <h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
-      <p>Last Updated: May 7, 2009</p>
+      <p>Last Updated: May 9, 2009</p>
     </td>
   </tr>
 </table>
@@ -1400,6 +1400,8 @@ nuttx-0.4.6 2009-xx-xx Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;
 	  for verifying this.
 	* Began adding support for the MicroMint Eagle100 board.  This board has a
 	  Luminary LM3S6918 Cortex-M3.
+	* Add configuration option to enable fast GPIO (vs. legacy, "slow" GPIO) for
+	  LPC214x.
 
 pascal-0.1.3 2009-xx-xx Gregory Nutt &lt;spudmonkey@racsa.co.cr&gt;
 

arch/arm/src/lpc214x/chip.h

@@ -47,6 +47,7 @@
 /* Memory Map ***************************************************************************************/
 
 #define LPC214X_FLASH_BASE              0x00000000
+#define LPC214X_FIO_BASE                0x3fffc000
 #define LPC214X_ONCHIP_RAM_BASE         0x40000000
 #define LPC214X_USBDMA_RAM_BASE         0x7fd00000
 #define LPC214X_BOOT_BLOCK              0x7fffd000
@@ -56,7 +57,12 @@
 
 /* Peripheral Registers ****************************************************************************/
 
-/* Register block base addresses */
+/* FIO Register block base addresses */
+
+#define LPC214X_FIO0_BASE               0x3fffc000  /* Fast I/O 0 base address */
+#define LPC214X_FIO1_BASE               0x3fffc020  /* Fast I/O 1 base address */
+
+/* APB Register block base addresses */
 
 #define LPC214X_WD_BASE                 0xe0000000  /* Watchdog base address */
 #define LPC214X_TMR0_BASE               0xe0004000  /* Timer 0 base address*/
@@ -79,12 +85,15 @@
 
 #define LPC214X_SCB_BASE                0xe01fc000  /* System Control Block (SBC) base address */
 #define   LPC214X_MAM_BASE              0xe01fc000  /* Memory Accelerator Module (MAM) base address */
+#define   LPC214X_SCS                   0xe01fc1a0  /* System Control and Status flags (SCS) */
 #define   LPC214X_MEMMAP                0xe01fc040  /* Memory Mapping Control */
 #define   LPC214X_PLL_BASE              0xe01fc080  /* Phase Locked Loop (PLL) base address */
 #define   LPC214X_PCON_BASE             0xe01fc0c0  /* Power Control (PCON) base address */
 #define   LPC214X_APBDIV                0xe01fc100  /* APBDIV Address */
 #define   LPC214X_EXT_BASE              0xe01fc140  /* External Interrupt base address */       
 
+/* AHB Register block base addresses */
+
 #define LPC214X_EMC_BASE                0xffe00000  /* External Memory Controller (EMC) base address */
 #define LPC214X_VIC_BASE                0xfffff000  /* Vectored Interrupt Controller (VIC) Base */
 
@@ -169,6 +178,7 @@
 #define LPC214X_PINSEL2_OFFSET          0x14   /* Pin function select register 2 */
 
 /* Analog to Digital (AD) Converter registger offsets */
+
 #define LPC214X_AD_ADCR_OFFSET          0x00   /* A/D Control Register */
 #define LPC214X_AD_ADGDR_OFFSET         0x04   /* A/D Global Data Register (only one common register!) */
 #define LPC214X_AD_ADGSR_OFFSET         0x08   /* A/D Global Start Register */
@@ -240,6 +250,14 @@
 #define LPC214X_GPIO_DIR_OFFSET         0x08   /* Pin Direction Register */
 #define LPC214X_GPIO_CLR_OFFSET         0x0c   /* Pin Output Clear Register */
 
+/* FIO register offsets */
+
+#define LPC214X_FIO_DIR_OFFSET          0x00   /* Fast GPIO Port Direction Register */
+#define LPC214X_FIO_MASK_OFFSET         0x10   /* Fast GPIO Mask Register */
+#define LPC214X_FIO_PIN_OFFSET          0x14   /* Fast GPIO Pin Value Register */
+#define LPC214X_FIO_SET_OFFSET          0x18   /* Fast GPIO Port Output Set Register */
+#define LPC214X_FIO_CLR_OFFSET          0x1c   /* Fast GPIO Port Output Clear Register */
+
 /* Memory Accelerator Module (MAM) Regiser Offsets */
 
 #define LPC214X_MAM_CR_OFFSET           0x00   /* MAM Control Offset*/

arch/arm/src/lpc214x/lpc214x_head.S

@@ -433,6 +433,14 @@
 #endif
 	.endm
 
+	.macro configfastport, base, tmp
+#ifdef CONFIG_LPC214x_FIO
+	ldr	\base, =LPC214X_SCS
+	mov	\tmp, #0x03
+	str	\tmp,[\base]
+#endif
+	.endm
+
 /*****************************************************************************
  * Text
  *****************************************************************************/
@@ -534,6 +542,10 @@ __start:
 	
 	configdac	r0, r1
 
+	/* Configure Fast GPIO Port */
+
+	configfastport  r0, r1
+
 	/* Configure the uart so that we can get debug output as soon
 	 * as possible.  Modifies r0, r1, r2, and r14.
 	 */

configs/mcu123-lpc214x/README.txt

@@ -98,10 +98,13 @@ ARM/LPC214X-specific Configuration Options
 
   LPC2148 specific chip initialization
 
+    These provide register setup values:
 	CONFIG_EXTMEM_MODE, CONFIG_RAM_MODE, CONFIG_CODE_BASE, CONFIG_PLL_SETUP,
 	CONFIG_MAM_SETUP, CONFIG_APBDIV_SETUP, CONFIG_EMC_SETUP, CONFIG_BCFG0_SETUP,
 	CONFIG_BCFG1_SETUP, CONFIG_BCFG2_SETUP, CONFIG_BCFG3_SETUP, CONFIG_ADC_SETUP
 
+	CONFIG_LPC214x_FIO - Enable fast GPIO (vs. legacy, "old" GPIO).
+
   LPC214X specific device driver settings
 
 	CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the

configs/mcu123-lpc214x/nsh/ld.script

@@ -33,6 +33,12 @@
  *
  ****************************************************************************/
 
+MEMORY
+{
+	flash	(rx) : ORIGIN = 0, LENGTH = 500K
+	ram	(rw) : ORIGIN = 0x40000000, LENGTH = 32K - 32
+}
+
 OUTPUT_ARCH(arm)
 ENTRY(_stext)
 SECTIONS
@@ -42,7 +48,6 @@ SECTIONS
 	 * 0x00000000 (default MEMMAP mode assumed)
 	 */
 
-	. = 0x00000000;
 	.text : {
 		_stext = ABSOLUTE(.);
 		*(.text)
@@ -54,7 +59,7 @@ SECTIONS
 		*(.glue_7t)
 		*(.got)			/* Global offset table		*/
 		_etext = ABSOLUTE(.);
-	}
+	} > flash
 	_eronly = ABSOLUTE(.);		/* This is where the .data section
 					 * is relocated for execution out
 					 * FLASH */
@@ -64,20 +69,22 @@ SECTIONS
 	 * to _sdata at boot time.
 	 */
 
-	. = 0x40000000;
 	.data : {
 		_sdata = ABSOLUTE(.);
 		*(.data)
 		CONSTRUCTORS
 		_edata = ABSOLUTE(.);
-	}
+	} >ram AT>flash
 
+	. = ALIGN(32 / 8);
 	.bss : {			/* BSS				*/
 		_sbss = ABSOLUTE(.);
 		*(.bss)
 		*(COMMON)
 		_ebss = ABSOLUTE(.);
 	}
+
+	. = ALIGN(32 / 8);
 					/* Stabs debugging sections.	*/
 	.stab 0 : { *(.stab) }
 	.stabstr 0 : { *(.stabstr) }

configs/mcu123-lpc214x/src/up_leds.c

@@ -50,11 +50,25 @@
 
 /* P1.16-P1.23 control LEDS 1-8 */
 
-#define LEDBIT(led)  (0x00010000 << (led))
-#define ALLLEDS      (0x00ff0000)
+#define LEDBIT(led)     (0x00010000 << (led))
+#define ALLLEDS         (0x00ff0000)
 
-#define putled(v,r)  putreg32((v),(LPC214X_GPIO1_BASE+(r)))
-#define CLRLEDS      putled(ALLLEDS,LPC214X_GPIO_SET_OFFSET)
+#ifdef CONFIG_LPC214x_FIO
+#  define putled(v,r)    putreg32((v),(LPC214X_FIO1_BASE+(r)))
+#  define CLRLEDS        putled(ALLLEDS,LPC214X_FIO_SET_OFFSET)
+
+#  define LED_SET_OFFSET LPC214X_FIO_SET_OFFSET
+#  define LED_CLR_OFFSET LPC214X_FIO_CLR_OFFSET
+#  define LED_DIR_OFFSET LPC214X_FIO_DIR_OFFSET
+
+#else
+#  define putled(v,r)    putreg32((v),(LPC214X_GPIO1_BASE+(r)))
+#  define CLRLEDS        putled(ALLLEDS,LPC214X_GPIO_SET_OFFSET)
+
+#  define LED_SET_OFFSET LPC214X_GPIO_SET_OFFSET
+#  define LED_CLR_OFFSET LPC214X_GPIO_CLR_OFFSET
+#  define LED_DIR_OFFSET LPC214X_GPIO_DIR_OFFSET
+#endif
 
 /****************************************************************************
  * Private Data
@@ -77,9 +91,9 @@ void up_ledinit(void)
 {
   /* Initilize GIOs P1.16-P1.23 */
 
-  putled(ALLLEDS,LPC214X_GPIO_DIR_OFFSET);
-  putled(ALLLEDS,LPC214X_GPIO_SET_OFFSET);
-  putled(LEDBIT(0),LPC214X_GPIO_CLR_OFFSET);
+  putled(ALLLEDS,LED_DIR_OFFSET);
+  putled(ALLLEDS,LED_SET_OFFSET);
+  putled(LEDBIT(0),LED_CLR_OFFSET);
 }
 
 /****************************************************************************
@@ -88,7 +102,7 @@ void up_ledinit(void)
 
 void up_ledon(int led)
 {
-  putled(LEDBIT(led),LPC214X_GPIO_CLR_OFFSET);
+  putled(LEDBIT(led),LED_CLR_OFFSET);
 }
 
 /****************************************************************************
@@ -97,6 +111,6 @@ void up_ledon(int led)
 
 void up_ledoff(int led)
 {
-  putled(LEDBIT(led),LPC214X_GPIO_SET_OFFSET);
+  putled(LEDBIT(led),LED_SET_OFFSET);
 }
 #endif /* CONFIG_ARCH_LEDS */

configs/mcu123-lpc214x/src/up_spi.c

@@ -82,6 +82,16 @@
 #define LPC214X_CCLKFREQ  (LPC214X_FOSC*LPC214X_PLL_M)
 #define LPC214X_PCLKFREQ  (LPC214X_CCLKFREQ/LPC214X_APB_DIV)
 
+#ifdef CONFIG_LPC214x_FIO
+#  define CS_SET_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_SET_OFFSET)
+#  define CS_CLR_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_CLR_OFFSET)
+#  define CS_DIR_REGISTER (LPC214X_FIO0_BASE+LPC214X_FIO_DIR_OFFSET)
+#else
+#  define CS_SET_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_SET_OFFSET)
+#  define CS_CLR_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_CLR_OFFSET)
+#  define CS_DIR_REGISTER (LPC214X_GPIO0_BASE+LPC214X_GPIO_DIR_OFFSET)
+#endif
+
 /****************************************************************************
  * Private Function Prototypes
  ****************************************************************************/
@@ -143,13 +153,13 @@ static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, boolean
     {
       /* Enable slave select (low enables) */
 
-      putreg32(bit, LPC214X_GPIO0_BASE+LPC214X_GPIO_CLR_OFFSET);
+      putreg32(bit, CS_CLR_REGISTER);
     }
   else
     {
       /* Disable slave select (low enables) */
 
-      putreg32(bit, LPC214X_GPIO0_BASE+LPC214X_GPIO_SET_OFFSET);
+      putreg32(bit, CS_SET_REGISTER);
 
       /* Wait for the TX FIFO not full indication */
 
@@ -425,7 +435,7 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
    *   PINSEL1 P0.17/CAP1.2/SCK1/MAT1.2  Bits 2-3=10 for SCK1
    *   PINSEL1 P0.18/CAP1.3/MISO1/MAT1.3 Bits 4-5=10 for MISO1
    *   PINSEL1 P0.19/MAT1.2/MOSI1/CAP1.2 Bits 6-7=10 for MOSI1
-   *   PINSEL1 P0.20/MAT1.3/SSEL1/EINT3  Bits 8-9=10 for P0.20 (we'll control it via GPIO)
+   *   PINSEL1 P0.20/MAT1.3/SSEL1/EINT3  Bits 8-9=10 for P0.20 (we'll control it via GPIO or FIO)
    */
 
   regval32  = getreg32(LPC214X_PINSEL1);
@@ -438,9 +448,9 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
   /* Disable chip select using P0.20 (SSEL1)  (low enables) */
 
   regval32 = 1 << 20;
-  putreg32(regval32, LPC214X_GPIO0_BASE+LPC214X_GPIO_SET_OFFSET);
-  regval32 |= getreg32(LPC214X_GPIO0_BASE+LPC214X_GPIO_DIR_OFFSET);
-  putreg32(regval32, LPC214X_GPIO0_BASE+LPC214X_GPIO_DIR_OFFSET);
+  putreg32(regval32, CS_SET_REGISTER);
+  regval32 |= getreg32(CS_DIR_REGISTER);
+  putreg32(regval32, CS_DIR_REGISTER);
 
   /* Enable peripheral clocking to SPI1 */