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Commit 294152fe authored by Gregory Nutt's avatar Gregory Nutt
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SAM D20: A little more clock configuration logic (still incomplete)

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arch/arm/src/samd/chip/sam_nvmctrl.h
+ 188
− 1
View file @ 294152fe
......@@ -144,12 +144,199 @@
/* Address register */
#define NVMCTRL_ADDR_MASK (0x003fffff) /* Bits 0-21: NVM Address */
#define NVMCTRL_ADDR_MASK (0x003fffff) /* Bits 0-21: NVM Address */
/* Lock section register */
#define NVMCTRL_LOCK_REGION(n) (1 << (n)) /* Region n is locked */
/* Fuse definitions *************************************************************************/
#define ADC_FUSES_BIASCAL_ADDR (SAM_AUX1_AREA4 + 4)
#define ADC_FUSES_BIASCAL_SHIFT (3) /* ADC Bias Calibration */
#define ADC_FUSES_BIASCAL_MASK (7 << ADC_FUSES_BIASCAL_SHIFT)
# define ADC_FUSES_BIASCAL(n) ((n) << ADC_FUSES_BIASCAL_SHIFT)
#define ADC_FUSES_BIAS_OPA_ADDR (SAM_AUX1_AREA2 + 4)
#define ADC_FUSES_BIAS_OPA_SHIFT (19) /* ADC OPA Bias */
#define ADC_FUSES_BIAS_OPA_MASK (1 << ADC_FUSES_BIAS_OPA_SHIFT)
#define ADC_FUSES_BOOSTEN_ADDR (SAM_AUX1_AREA2 + 4)
#define ADC_FUSES_BOOSTEN_SHIFT (17) /* ADC Boost Enable */
#define ADC_FUSES_BOOSTEN_MASK (1 << ADC_FUSES_BOOSTEN_SHIFT)
#define ADC_FUSES_CMPDELAY_ADDR (SAM_AUX1_AREA2 + 4)
#define ADC_FUSES_CMPDELAY_SHIFT (16) /* ADC Comparator Delay */
#define ADC_FUSES_CMPDELAY_MASK (1 << ADC_FUSES_CMPDELAY_SHIFT)
#define ADC_FUSES_DCFG_ADDR (SAM_AUX1_AREA2 + 4)
#define ADC_FUSES_DCFG_SHIFT (16) /* ADC Device Configuration */
#define ADC_FUSES_DCFG_MASK (15 << ADC_FUSES_DCFG_SHIFT)
# define ADC_FUSES_DCFG(n) ((n) << ADC_FUSES_DCFG_SHIFT)
#define ADC_FUSES_GAINCORR_ADDR (SAM_AUX1_AREA4 + 0)
#define ADC_FUSES_GAINCORR_SHIFT (3) /* ADC Gain Correction */
#define ADC_FUSES_GAINCORR_MASK (0xfff << ADC_FUSES_GAINCORR_SHIFT)
# define ADC_FUSES_GAINCORR(n) ((n) << ADC_FUSES_GAINCORR_SHIFT)
#define ADC_FUSES_LINEARITY_0_ADDR (SAM_AUX1_AREA4 + 0)
#define ADC_FUSES_LINEARITY_0_SHIFT (27) /* ADC Linearity bits 4:0 */
#define ADC_FUSES_LINEARITY_0_MASK (0x1f << ADC_FUSES_LINEARITY_0_SHIFT)
# define ADC_FUSES_LINEARITY_0(n) ((n) << ADC_FUSES_LINEARITY_0_SHIFT)
#define ADC_FUSES_LINEARITY_1_ADDR (SAM_AUX1_AREA4 + 4)
#define ADC_FUSES_LINEARITY_1_SHIFT (0) /* ADC Linearity bits 7:5 */
#define ADC_FUSES_LINEARITY_1_MASK (7 << ADC_FUSES_LINEARITY_1_SHIFT)
# define ADC_FUSES_LINEARITY_1(n) ((n) << ADC_FUSES_LINEARITY_1_SHIFT)
#define ADC_FUSES_OFFSETCORR_ADDR (SAM_AUX1_AREA4 + 0)
#define ADC_FUSES_OFFSETCORR_SHIFT (15) /* ADC Offset Correction */
#define ADC_FUSES_OFFSETCORR_MASK (0xfff << ADC_FUSES_OFFSETCORR_SHIFT)
# define ADC_FUSES_OFFSETCORR(n) ((n) << ADC_FUSES_OFFSETCORR_SHIFT)
#define ADC_FUSES_VCMPULSE_ADDR (SAM_AUX1_AREA2 + 4)
#define ADC_FUSES_VCMPULSE_SHIFT (18) /* ADC VCM Pulse */
#define ADC_FUSES_VCMPULSE_MASK (1 << ADC_FUSES_VCMPULSE_SHIFT)
#define DSU_FUSES_DCFG0_ADDR (SAM_AUX1_AREA2 + 0)
#define DSU_FUSES_DCFG0_SHIFT (0) /* Device Configuration 0 */
#define DSU_FUSES_DCFG0_MASK (0xffffffff << DSU_FUSES_DCFG0_SHIFT)
# define DSU_FUSES_DCFG0(n) ((n) << DSU_FUSES_DCFG0_SHIFT)
#define DSU_FUSES_DCFG1_ADDR (SAM_AUX1_AREA2 + 4)
#define DSU_FUSES_DCFG1_SHIFT (0) /* Device Configuration 1 */
#define DSU_FUSES_DCFG1_MASK (0xffffffff << DSU_FUSES_DCFG1_SHIFT)
# define DSU_FUSES_DCFG1(n) ((n) << DSU_FUSES_DCFG1_SHIFT)
#define DSU_FUSES_DEV_FAMILY_CFG_0_ADDR (SAM_AUX1_AREA2 + 0)
#define DSU_FUSES_DEV_FAMILY_CFG_0_SHIFT (5) /* Device Family Configuration bits 26:0 */
#define DSU_FUSES_DEV_FAMILY_CFG_0_MASK (0x7ffffff << DSU_FUSES_DEV_FAMILY_CFG_0_SHIFT)
# define DSU_FUSES_DEV_FAMILY_CFG_0(n) ((n) << DSU_FUSES_DEV_FAMILY_CFG_0_SHIFT)
#define DSU_FUSES_DEV_FAMILY_CFG_1_ADDR (SAM_AUX1_AREA2 + 4)
#define DSU_FUSES_DEV_FAMILY_CFG_1_SHIFT (0) /* Device Family Configuration bits 42:27 */
#define DSU_FUSES_DEV_FAMILY_CFG_1_MASK (0xffff << DSU_FUSES_DEV_FAMILY_CFG_1_SHIFT)
# define DSU_FUSES_DEV_FAMILY_CFG_1(n) ((n) << DSU_FUSES_DEV_FAMILY_CFG_1_SHIFT)
#define DSU_FUSES_DID_DEVSEL_ADDR (SAM_AUX1_AREA2 + 0)
#define DSU_FUSES_DID_DEVSEL_SHIFT (0) /* Device Number */
#define DSU_FUSES_DID_DEVSEL_MASK (0x1f << DSU_FUSES_DID_DEVSEL_SHIFT)
# define DSU_FUSES_DID_DEVSEL(n) ((n) << DSU_FUSES_DID_DEVSEL_SHIFT)
#define DSU_FUSES_RAM_BIAS_ADDR (SAM_AUX1_AREA2 + 4)
#define DSU_FUSES_RAM_BIAS_SHIFT (20) /* RAM Bias */
#define DSU_FUSES_RAM_BIAS_MASK (3 << DSU_FUSES_RAM_BIAS_SHIFT)
# define DSU_FUSES_RAM_BIAS(n) ((n) << DSU_FUSES_RAM_BIAS_SHIFT)
#define DSU_FUSES_RAM_READ_MARGIN_ADDR (SAM_AUX1_AREA2 + 4)
#define DSU_FUSES_RAM_READ_MARGIN_SHIFT (22) /* RAM Read Margin */
#define DSU_FUSES_RAM_READ_MARGIN_MASK (15 << DSU_FUSES_RAM_READ_MARGIN_SHIFT)
# define DSU_FUSES_RAM_READ_MARGIN(n) ((n) << DSU_FUSES_RAM_READ_MARGIN_SHIFT)
#define NVMCTRL_FUSES_BOOTPROT_ADDR (SAM_AUX0_BASE + 0)
#define NVMCTRL_FUSES_BOOTPROT_SHIFT (0) /* Bootloader Size */
#define NVMCTRL_FUSES_BOOTPROT_MASK (7 << NVMCTRL_FUSES_BOOTPROT_SHIFT)
# define NVMCTRL_FUSES_BOOTPROT(n) ((n) << NVMCTRL_FUSES_BOOTPROT_SHIFT)
#define NVMCTRL_FUSES_EEPROM_SIZE_ADDR (SAM_AUX0_BASE + 0)
#define NVMCTRL_FUSES_EEPROM_SIZE_SHIFT (4) /* EEPROM Size */
#define NVMCTRL_FUSES_EEPROM_SIZE_MASK (7 << NVMCTRL_FUSES_EEPROM_SIZE_SHIFT)
# define NVMCTRL_FUSES_EEPROM_SIZE(n) ((n) << NVMCTRL_FUSES_EEPROM_SIZE_SHIFT)
#define NVMCTRL_FUSES_LOCKFIELD_ADDR (SAM_LOCKBIT_BASE + 0)
#define NVMCTRL_FUSES_LOCKFIELD_SHIFT (0) /* LOCK Region */
#define NVMCTRL_FUSES_LOCKFIELD_MASK (0xff << NVMCTRL_FUSES_LOCKFIELD_SHIFT)
# define NVMCTRL_FUSES_LOCKFIELD(n) ((n) << NVMCTRL_FUSES_LOCKFIELD_SHIFT)
#define NVMCTRL_FUSES_NVMP_ADDR (SAM_AUX1_AREA1 + 0)
#define NVMCTRL_FUSES_NVMP_SHIFT (16 /* Number of NVM Pages */
#define NVMCTRL_FUSES_NVMP_MASK (0xffff << NVMCTRL_FUSES_NVMP_SHIFT)
# define NVMCTRL_FUSES_NVMP(n) ((n) << NVMCTRL_FUSES_NVMP_SHIFT)
#define NVMCTRL_FUSES_NVM_LOCK_ADDR (SAM_AUX1_AREA1 + 0)
#define NVMCTRL_FUSES_NVM_LOCK_SHIFT (0) /* NVM Lock */
#define NVMCTRL_FUSES_NVM_LOCK_MASK (0xff << NVMCTRL_FUSES_NVM_LOCK_SHIFT)
# define NVMCTRL_FUSES_NVM_LOCK(n) ((n) << NVMCTRL_FUSES_NVM_LOCK_SHIFT)
#define NVMCTRL_FUSES_PSZ_ADDR (SAM_AUX1_AREA1 + 0)
#define NVMCTRL_FUSES_PSZ_SHIFT (8) /* NVM Page Size */
#define NVMCTRL_FUSES_PSZ_MASK (15 << NVMCTRL_FUSES_PSZ_SHIFT)
# define NVMCTRL_FUSES_PSZ(n) ((n) << NVMCTRL_FUSES_PSZ_SHIFT)
#define NVMCTRL_FUSES_REGION_LOCKS_ADDR (SAM_AUX0_BASE + 4)
#define NVMCTRL_FUSES_REGION_LOCKS_SHIFT (16) /* NVM Region Locks */
#define NVMCTRL_FUSES_REGION_LOCKS_MASK (0xffff << NVMCTRL_FUSES_REGION_LOCKS_SHIFT)
# define NVMCTRL_FUSES_REGION_LOCKS(n) ((n) << NVMCTRL_FUSES_REGION_LOCKS_SHIFT)
#define SYSCTRL_FUSES_OSC32KCAL_ADDR (SAM_AUX1_AREA4 + 4)
#define SYSCTRL_FUSES_OSC32KCAL_SHIFT (6) /* OSC32K Calibration */
#define SYSCTRL_FUSES_OSC32KCAL_MASK (0x7f << SYSCTRL_FUSES_OSC32KCAL_SHIFT)
# define SYSCTRL_FUSES_OSC32KCAL(n) ((n) << SYSCTRL_FUSES_OSC32KCAL_SHIFT)
#define SYSCTRL_FUSES_BOD12USERLEVEL_ADDR (SAM_AUX0_BASE + 0)
#define SYSCTRL_FUSES_BOD12USERLEVEL_SHIFT (17) /* BOD12 User Level */
#define SYSCTRL_FUSES_BOD12USERLEVEL_MASK (0x1f << SYSCTRL_FUSES_BOD12USERLEVEL_SHIFT)
# define SYSCTRL_FUSES_BOD12USERLEVEL(n) ((n) << SYSCTRL_FUSES_BOD12USERLEVEL_SHIFT)
#define SYSCTRL_FUSES_BOD12_ACTION_ADDR (SAM_AUX0_BASE + 0)
#define SYSCTRL_FUSES_BOD12_ACTION_SHIFT (23) /* BOD12 Action */
#define SYSCTRL_FUSES_BOD12_ACTION_MASK (3 << SYSCTRL_FUSES_BOD12_ACTION_SHIFT)
# define SYSCTRL_FUSES_BOD12_ACTION(n) ((n) << SYSCTRL_FUSES_BOD12_ACTION_SHIFT)
#define SYSCTRL_FUSES_BOD12_EN_ADDR (SAM_AUX0_BASE + 0)
#define SYSCTRL_FUSES_BOD12_EN_SHIFT (22) /* BOD12 Enable */
#define SYSCTRL_FUSES_BOD12_EN_MASK (1 << SYSCTRL_FUSES_BOD12_EN_SHIFT)
#define SYSCTRL_FUSES_BOD33USERLEVEL_ADDR (SAM_AUX0_BASE + 8)
#define SYSCTRL_FUSES_BOD33USERLEVEL_SHIFT (8) /* BOD33 User Level */
#define SYSCTRL_FUSES_BOD33USERLEVEL_MASK (0x3f << SYSCTRL_FUSES_BOD33USERLEVEL_SHIFT)
# define SYSCTRL_FUSES_BOD33USERLEVEL(n) ((n) << SYSCTRL_FUSES_BOD33USERLEVEL_SHIFT)
#define SYSCTRL_FUSES_BOD33_ACTION_ADDR (SAM_AUX0_BASE + 0)
#define SYSCTRL_FUSES_BOD33_ACTION_SHIFT (15) /* BOD33 Action */
#define SYSCTRL_FUSES_BOD33_ACTION_MASK (3 << SYSCTRL_FUSES_BOD33_ACTION_SHIFT)
# define SYSCTRL_FUSES_BOD33_ACTION(n) ((n) << SYSCTRL_FUSES_BOD33_ACTION_SHIFT)
#define SYSCTRL_FUSES_BOD33_EN_ADDR (SAM_AUX0_BASE + 0)
#define SYSCTRL_FUSES_BOD33_EN_SHIFT (14) /* BOD33 Enable */
#define SYSCTRL_FUSES_BOD33_EN_MASK (1 << SYSCTRL_FUSES_BOD33_EN_SHIFT)
#define SYSCTRL_FUSES_ULPVREG_ADDR (SAM_AUX1_AREA4 + 0)
#define SYSCTRL_FUSES_ULPVREG_SHIFT (0) /* ULP Regulator Fallback Mode */
#define SYSCTRL_FUSES_ULPVREG_MASK (7 << SYSCTRL_FUSES_ULPVREG_SHIFT)
# define SYSCTRL_FUSES_ULPVREG(n) ((n) << SYSCTRL_FUSES_ULPVREG_SHIFT)
#define WDT_FUSES_ALWAYSON_ADDR (SAM_AUX0_BASE
#define WDT_FUSES_ALWAYSON_SHIFT (26) /* WDT Always On */
#define WDT_FUSES_ALWAYSON_MASK (1 << WDT_FUSES_ALWAYSON_SHIFT)
#define WDT_FUSES_ENABLE_ADDR (SAM_AUX0_BASE + 0)
#define WDT_FUSES_ENABLE_SHIFT (25) /* WDT Enable */
#define WDT_FUSES_ENABLE_MASK (1 << WDT_FUSES_ENABLE_SHIFT)
#define WDT_FUSES_EWOFFSET_ADDR (SAM_AUX0_BASE + 4)
#define WDT_FUSES_EWOFFSET_SHIFT (3) /* WDT Early Warning Offset */
#define WDT_FUSES_EWOFFSET_MASK (15 << WDT_FUSES_EWOFFSET_SHIFT)
# define WDT_FUSES_EWOFFSET(n) ((n) << WDT_FUSES_EWOFFSET_SHIFT)
#define WDT_FUSES_PER_ADDR (SAM_AUX0_BASE + 0)
#define WDT_FUSES_PER_SHIFT (27) /* WDT Period */
#define WDT_FUSES_PER_MASK (15 << WDT_FUSES_PER_SHIFT)
# define WDT_FUSES_PER(n) ((n) << WDT_FUSES_PER_SHIFT)
#define WDT_FUSES_WEN_ADDR (SAM_AUX0_BASE + 4)
#define WDT_FUSES_WEN_SHIFT (7) /* WDT Window Mode Enable */
#define WDT_FUSES_WEN_MASK (1 << WDT_FUSES_WEN_SHIFT)
#define WDT_FUSES_WINDOW_0_ADDR (SAM_AUX0_BASE + 0)
#define WDT_FUSES_WINDOW_0_SHIFT (31) /* WDT Window bit 0 */
#define WDT_FUSES_WINDOW_0_MASK (1 << WDT_FUSES_WINDOW_0_SHIFT)
#define WDT_FUSES_WINDOW_1_ADDR (SAM_AUX0_BASE + 4)
#define WDT_FUSES_WINDOW_1_SHIFT (0) /* WDT Window bits 3:1 */
#define WDT_FUSES_WINDOW_1_MASK (7 << WDT_FUSES_WINDOW_1_SHIFT)
# define WDT_FUSES_WINDOW_1(n) ((n) << WDT_FUSES_WINDOW_1_SHIFT)
/********************************************************************************************
* Public Types
********************************************************************************************/
......
arch/arm/src/samd/chip/samd20_memorymap.h
+ 1
− 0
View file @ 294152fe
......@@ -58,6 +58,7 @@
/* Calibration and Auxiliary Space */
#define SAM_LOCKBIT_BASE 0x00802000 /* LOCKBIT Base Address */
#define SAM_AUX0_BASE 0x00804000 /* AUX0 offset address */
#define SAM_AUX1_BASE 0x00806000 /* AUX1 offset address */
# define SAM_AUX1_AREA1 0x00806000 /* Area 1 offset address (reserved, 64 bits) */
......
arch/arm/src/samd/sam_clockconfig.c
+ 228
− 20
View file @ 294152fe
......@@ -70,6 +70,9 @@
*
* Description:
* Set the FLASH wait states based on settings in the board.h header file
* Depends on:
*
* BOARD_FLASH_WAITSTATES - Number of wait states
*
* Input Parameters:
* None
......@@ -94,6 +97,15 @@ static inline void sam_flash_waitstates(void)
*
* Description:
* Configure XOSC based on settings in the board.h header file
* Depends on:
*
* BOARD_XOSC_ENABLE - Boolean (defined / not defined)
* BOARD_XOSC_FREQUENCY - In Hz
* BOARD_XOSC_STARTUPTIME - See SYSCTRL_XOSC_STARTUP_* definitions
* BOARD_XOSC_ISCRYSTAL - Boolean (defined / not defined)
* BOARD_XOSC_AMPGC - Boolean (defined / not defined)
* BOARD_XOSC_ONDEMAND - Boolean (defined / not defined)
* BOARD_XOSC_RUNINSTANDBY - Boolean (defined / not defined)
*
* Input Parameters:
* None
......@@ -106,7 +118,55 @@ static inline void sam_flash_waitstates(void)
#if defined(CONFIG_SAMD_XOSC) || defined(BOARD_XOSC_ENABLE)
static inline void sam_xosc_config(void)
{
#warning Missing logic
uint16_t regval;
/* Configure the XOSC clock */
regval = BOARD_XOSC_STARTUPTIME
#ifdef BOARD_XOSC_ISCRYSTAL
/* XOSC is a crystal */
regval |= SYSCTRL_XOSC_XTALEN;
#endif
#ifdef BOARD_XOSC_AMPGC
/* Enable automatic gain control */
regval |= SYSCTRL_XOSC_AMPGC;
#else
/* Set gain if automatic gain control is not selected */
#if BOARD_XOSC_FREQUENCY <= 2000000
regval |= SYSCTRL_XOSC_GAIN_2MHZ;
#elif BOARD_XOSC_FREQUENCY <= 4000000
regval |= SYSCTRL_XOSC_GAIN_4MHZ;
#elif BOARD_XOSC_FREQUENCY <= 8000000
regval |= SYSCTRL_XOSC_GAIN_8MHZ;
#elif BOARD_XOSC_FREQUENCY <= 16000000
regval |= SYSCTRL_XOSC_GAIN_16MHZ;
#elif BOARD_XOSC_FREQUENCY <= 30000000
regval |= SYSCTRL_XOSC_GAIN_30MHZ;
#else
# error BOARD_XOSC_FREQUENCY out of range
#endif
#endif /* BOARD_XOSC_AMPGC */
#ifdef BOARD_XOSC_ONDEMAND
regval |= SYSCTRL_XOSC_ONDEMAND;
#endif
#ifdef BOARD_XOSC_RUNINSTANDBY
regval |= SYSCTRL_XOSC_RUNSTDBY;
#endif
putreg16(regval, SAM_SYSCTRL_XOSC);
/* Then enable the XOSC clock */
regval |= SYSCTRL_XOSC_ENABLE;
putreg16(regval, SAM_SYSCTRL_XOSC);
}
#else
# define sam_xosc_config()
......@@ -116,7 +176,18 @@ static inline void sam_xosc_config(void)
* Name: sam_xosc32k_config
*
* Description:
* Configure XOSC32K based on settings in the board.h header file
* Configure XOSC32K based on settings in the board.h header file.
* Depends on:
*
* BOARD_XOSC32K_ENABLE - Boolean (defined / not defined)
* BOARD_XOSC32K_FREQUENCY - In Hz
* BOARD_XOSC32K_STARTUPTIME - See SYSCTRL_XOSC32K_STARTUP_* definitions
* BOARD_XOSC32K_ISCRYSTAL - Boolean (defined / not defined)
* BOARD_XOSC32K_AAMPEN - Boolean (defined / not defined)
* BOARD_XOSC32K_EN1KHZ - Boolean (defined / not defined)
* BOARD_XOSC32K_EN32KHZ - Boolean (defined / not defined)
* BOARD_XOSC32K_ONDEMAND - Boolean (defined / not defined)
* BOARD_XOSC32K_RUNINSTANDBY - Boolean (defined / not defined)
*
* Input Parameters:
* None
......@@ -126,10 +197,45 @@ static inline void sam_xosc_config(void)
*
****************************************************************************/
#if defined(CONFIG_SAMD_XOSC32K) || defined(BOARD_XOSC32_ENABLE)
#if defined(CONFIG_SAMD_XOSC32K) || defined(BOARD_XOSC32K_ENABLE)
static inline void sam_xosc32k_config(void)
{
#warning Missing logic
uint16_t regval;
/* Configure XOSC32K */
regval = BOARD_XOSC32K_STARTUPTIME
#ifdef BOARD_XOSC32K_ISCRYSTAL
regval |= SYSCTRL_XOSC32K_XTALEN;
#endif
#ifdef BOARD_XOSC32K_AAMPEN
regval |= SYSCTRL_XOSC32K_AAMPEN;
#endif
#ifdef BOARD_XOSC32K_EN1KHZ
regval |= SYSCTRL_XOSC32K_EN1K;
#endif
#ifdef BOARD_XOSC32K_EN32KHZ
regval |= SYSCTRL_XOSC32K_EN32K;
#endif
#ifdef BOARD_XOSC32K_ONDEMAND
regval |= SYSCTRL_XOSC32K_ONDEMAND;
#endif
#ifdef BOARD_XOSC32K_RUNINSTANDBY
regval |= SYSCTRL_XOSC32K_RUNSTDBY;
#endif
putreg16(regval, SAM_SYSCTRL_XOSC32K);
/* Then enable the XOSC clock */
regval |= SYSCTRL_XOSC32K_ENABLE;
putreg16(regval, SAM_SYSCTRL_XOSC32K);
}
#else
# define sam_xosc32k_config()
......@@ -139,7 +245,16 @@ static inline void sam_xosc32k_config(void)
* Name: sam_osc32k_config
*
* Description:
* Configure OSC32K based on settings in the board.h header file
* Configure OSC32K based on settings in the board.h header file.
* Depends on:
*
* BOARD_OSC32K_ENABLE - Boolean (defined / not defined)
* BOARD_OSC32K_FREQUENCY - In Hz
* BOARD_OSC32K_STARTUPTIME - See SYSCTRL_OSC32K_STARTUP_* definitions
* BOARD_OSC32K_EN1KHZ - Boolean (defined / not defined)
* BOARD_OSC32K_EN32KHZ - Boolean (defined / not defined)
* BOARD_OSC32K_ONDEMAND - Boolean (defined / not defined)
* BOARD_OSC32K_RUNINSTANDBY - Boolean (defined / not defined)
*
* Input Parameters:
* None
......@@ -149,20 +264,59 @@ static inline void sam_xosc32k_config(void)
*
****************************************************************************/
#if defined(CONFIG_SAMD_OSC32K) || defined(BOARD_OSC32_ENABLE)
#if defined(CONFIG_SAMD_OSC32K) || defined(BOARD_OSC32K_ENABLE)
static inline void sam_osc32k_config(void)
{
#warning Missing logic
uint32_t regval;
uint32_t calib;
/* Recover OSC32K calibration data from OTP "fuse" memory */
regval = getreg32(SYSCTRL_FUSES_OSC32KCAL_ADDR)
calib = (regval & SYSCTRL_FUSES_OSC32KCAL_MASK) >> SYSCTRL_FUSES_OSC32KCAL_SHIFT;
regval = calib << SYSCTRL_OSC32K_CALIB_SHIFT;
/* Configure OSC32K */
regval |= BOARD_OSC32K_STARTUPTIME;
#ifdef BOARD_OSC32K_EN1KHZ
regval |= SYSCTRL_OSC32K_EN1K;
#endif
#ifdef BOARD_OSC32K_EN32KHZ
regval |= SYSCTRL_OSC32K_EN32K;
#endif
#ifdef BOARD_OSC32K_ONDEMAND
regval |= SYSCTRL_OSC32K_ONDEMAND;
#endif
#ifdef BOARD_OSC32K_RUNINSTANDBY
regval |= SYSCTRL_OSC32K_RUNSTDBY;
#endif
putreg32(regval, SAM_SYSCTRL_OSC32K);
/* Then enable OSC32K */
regval |= SYSCTRL_OSC32K_ENABLE;
putreg32(regval, SAM_SYSCTRL_OSC32K);
}
#else
# define sam_osc32k_config()
#endif
/****************************************************************************
* Name: sam_dfll_config
* Name: sam_osc8m_config
*
* Description:
* Configure the DFLL based on settings in the board.h header file
* Configure OSC8M based on settings in the board.h header file.
* Depends on:
*
* BOARD_OSC8M_PRESCALER - See SYSCTRL_OSC8M_PRESC_DIV* definitions
* BOARD_OSC8M_ONDEMAND - Boolean (defined / not defined)
* BOARD_OSC8M_RUNINSTANDBY - Boolean (defined / not defined)
*
* Input Parameters:
* None
......@@ -172,20 +326,38 @@ static inline void sam_osc32k_config(void)
*
****************************************************************************/
#if defined(CONFIG_SAMD_DFLL) || defined(BOARD_DFLL_ENABLE)
static inline void sam_dfll_config(void)
static inline void sam_osc8m_config(void)
{
#warning Missing logic
}
#else
# define sam_dfll_config()
uint32_t regval;
/* Configure OSC8M */
regval = BOARD_OSC8M_PRESCALER;
#ifdef BOARD_OSC8M_ONDEMAND
regval |= SYSCTRL_OSC8M_ONDEMAND;
#endif
#ifdef BOARD_OSC8M_RUNINSTANDBY
regval |= SYSCTRL_OSC8M_RUNSTDBY;
#endif
putreg32(regval, SAM_SYSCTRL_OSC8M);
/* Then enable OSC8M */
regval |= SYSCTRL_OSC8M_ENABLE;
putreg32(regval, SAM_SYSCTRL_OSC8M);
}
/****************************************************************************
* Name: sam_osc8m_config
* Name: sam_dfll_config
*
* Description:
* Configure OSC8M based on settings in the board.h header file
* Configure the DFLL based on settings in the board.h header file.
* Depends on:
*
*
*
* Input Parameters:
* None
......@@ -195,16 +367,23 @@ static inline void sam_dfll_config(void)
*
****************************************************************************/
static inline void sam_osc8m_config(void)
#if defined(CONFIG_SAMD_DFLL) || defined(BOARD_DFLL_ENABLE)
static inline void sam_dfll_config(void)
{
#warning Missing logic
}
#else
# define sam_dfll_config()
#endif
/****************************************************************************
* Name: sam_gclk_config
*
* Description:
* Configure GCLK(s) based on settings in the board.h header file
* Configure GCLK(s) based on settings in the board.h header file.
* Depends on:
*
*
*
* Input Parameters:
* None
......@@ -228,6 +407,17 @@ static inline void sam_gclk_config(void)
*
* Description:
* Setup PM main clock dividers to generate CPU, AHB, and APB clocks.
* Depends on:
*
* BOARD_CPU_DIVIDER - See PM_CPUSEL_CPUDIV_* definitions
* BOARD_CPU_FRQUENCY - In Hz
* BOARD_CPU_FAILDECT - Boolean (defined / not defined)
* BOARD_APBA_DIVIDER - See M_APBASEL_APBADIV_* definitions
* BOARD_APBA_FRQUENCY - In Hz
* BOARD_APBB_DIVIDER - See M_APBBSEL_APBBDIV_* definitions
* BOARD_APBB_FRQUENCY - In Hz
* BOARD_APBC_DIVIDER - See M_APBCSEL_APBCDIV_* definitions
* BOARD_APBC_FRQUENCY - In Hz
*
* Input Parameters:
* None
......@@ -239,7 +429,25 @@ static inline void sam_gclk_config(void)
static inline void sam_dividers(void)
{
#warning Missing logic
uint8_t regval;
/* Set CPU divider and, optionally, enable failure detection */
putreg8(BOARD_CPU_DIVIDER, SAM_PM_CPUSEL);
regval = getreg8(SAM_PM_CTRL);
#ifdef BOARD_CPU_FAILDECT
regval |= PM_CTRL_CFDEN;
#else
regval &= ~PM_CTRL_CFDEN;
#endif
putreg8(regval, SAM_PM_CTRL);
/* Set the APBA, B, and C dividers */
putreg8(BOARD_APBA_DIVIDER, SAM_PM_APBASEL);
putreg8(BOARD_APBB_DIVIDER, SAM_PM_APBBSEL);
putreg8(BOARD_APBC_DIVIDER, SAM_PM_APBCSEL);
}
/****************************************************************************
......
configs/samd20-xplained/include/board.h
+ 90
− 17
View file @ 294152fe
......@@ -60,7 +60,6 @@
* may vary with temperature changes.
*/
#define BOARD_OSC32K_FREQUENCY 32768 /* 32.768kHz internal oscillator */
#define BOARD_OSCULP32K_FREQUENCY 32000 /* 32kHz ultra-low-power internal oscillator */
#define BOARD_OSC8M_FREQUENCY 8000000 /* 8MHz high-accuracy internal oscillator */
#define BOARD_DFLL48M_FREQUENCY 48000000 /* 48MHz Digital Frequency Locked Loop */
......@@ -70,14 +69,77 @@
* XC101 32.768KHz XOSC32
*/
/* XOSC Configuration -- Not available */
/* XOSC Configuration -- Not available
*
* BOARD_XOSC_ENABLE - Boolean (defined / not defined)
* BOARD_XOSC_FREQUENCY - In Hz
* BOARD_XOSC_STARTUPTIME - See SYSCTRL_XOSC_STARTUP_* definitions
* BOARD_XOSC_ISCRYSTAL - Boolean (defined / not defined)
* BOARD_XOSC_AMPGC - Boolean (defined / not defined)
* BOARD_XOSC_ONDEMAND - Boolean (defined / not defined)
* BOARD_XOSC_RUNINSTANDBY - Boolean (defined / not defined)
*/
#undef BOARD_XOSC_FREQUENCY
#undef BOARD_XOSC_ENABLE
#define BOARD_XOSC_FREQUENCY 12000000UL
#define BOARD_XOSC_STARTUPTIME SYSCTRL_XOSC_STARTUP_1S
#define BOARD_XOSC_ISCRYSTAL 1
#define BOARD_XOSC_AMPGC 1
#define BOARD_XOSC_ONDEMAND 1
#undef BOARD_XOSC_RUNINSTANDBY
/* XOSC32 Configuration */
/* XOSC32 Configuration -- Not used
*
* BOARD_XOSC32K_ENABLE - Boolean (defined / not defined)
* BOARD_XOSC32K_FREQUENCY - In Hz
* BOARD_XOSC32K_STARTUPTIME - See SYSCTRL_XOSC32K_STARTUP_* definitions
* BOARD_XOSC32K_ISCRYSTAL - Boolean (defined / not defined)
* BOARD_XOSC32K_AAMPEN - Boolean (defined / not defined)
* BOARD_XOSC32K_EN1KHZ - Boolean (defined / not defined)
* BOARD_XOSC32K_EN32KHZ - Boolean (defined / not defined)
* BOARD_XOSC32K_ONDEMAND - Boolean (defined / not defined)
* BOARD_XOSC32K_RUNINSTANDBY - Boolean (defined / not defined)
*/
#define BOARD_XOSC32_FREQUENCY 32768 /* 32.768KHz XTAL */
#define BOARD_XOSC32_STARTUP_US 6100
#undef BOARD_XOSC32K_ENABLE
#define BOARD_XOSC32K_FREQUENCY 32768 /* 32.768KHz XTAL */
#define BOARD_XOSC32K_STARTUPTIME SYSCTRL_XOSC32K_STARTUP_2S
#define BOARD_XOSC32K_ISCRYSTAL 1
#define BOARD_XOSC32K_AAMPEN 1
#undef BOARD_XOSC32K_EN1KHZ
#define BOARD_XOSC32K_EN32KHZ 1
#define BOARD_XOSC32K_ONDEMAND 1
#undef BOARD_XOSC32K_RUNINSTANDBY
/* OSC32 Configuration -- not used
*
* BOARD_OSC32K_ENABLE - Boolean (defined / not defined)
* BOARD_OSC32K_FREQUENCY - In Hz
* BOARD_OSC32K_STARTUPTIME - See SYSCTRL_OSC32K_STARTUP_* definitions
* BOARD_OSC32K_EN1KHZ - Boolean (defined / not defined)
* BOARD_OSC32K_EN32KHZ - Boolean (defined / not defined)
* BOARD_OSC32K_ONDEMAND - Boolean (defined / not defined)
* BOARD_OSC32K_RUNINSTANDBY - Boolean (defined / not defined)
*/
#undef BOARD_OSC32K_ENABLE
#define BOARD_OSC32K_FREQUENCY 32768 /* 32.768kHz internal oscillator */
#define BOARD_OSC32K_STARTUPTIME SYSCTRL_OSC32K_STARTUP_4MS
#define BOARD_OSC32K_EN1KHZ 1
#define BOARD_OSC32K_EN32KHZ 1
#define BOARD_OSC32K_ONDEMAND 1
#undef BOARD_OSC32K_RUNINSTANDBY
/* OSC8M Configuration -- always enabled
*
* BOARD_OSC8M_PRESCALER - See SYSCTRL_OSC8M_PRESC_DIV* definitions
* BOARD_OSC8M_ONDEMAND - Boolean (defined / not defined)
* BOARD_OSC8M_RUNINSTANDBY - Boolean (defined / not defined)
*/
#define BOARD_OSC8M_PRESCALER SYSCTRL_OSC8M_PRESC_DIV1
#define BOARD_OSC8M_ONDEMAND 1
#undef BOARD_OSC8M_RUNINSTANDBY
/* The source of the main clock is always GLCK_MAIN. Also called GCLKGEN[0], this is
* the clock feeding the Power Manager. The Power Manager, in turn, generates main
......@@ -119,22 +181,33 @@
#define BOARD_DFLL48M_MUL (BOARD_DFLL0_TARGET / BOARD_GCK_MAIN_FREQUENCY)
#define BOARD_DFLL48M_FREQUENCY (BOARD_DFLL48M_MUL * BOARD_GCK_MAIN_FREQUENCY)
/* System clock dividers: Fbus = Fmck >> BUSshift */
/* Main clock dividers
*
* BOARD_CPU_DIVIDER - See PM_CPUSEL_CPUDIV_* definitions
* BOARD_CPU_FRQUENCY - In Hz
* BOARD_CPU_FAILDECT - Boolean (defined / not defined)
* BOARD_APBA_DIVIDER - See M_APBASEL_APBADIV_* definitions
* BOARD_APBA_FRQUENCY - In Hz
* BOARD_APBB_DIVIDER - See M_APBBSEL_APBBDIV_* definitions
* BOARD_APBB_FRQUENCY - In Hz
* BOARD_APBC_DIVIDER - See M_APBCSEL_APBCDIV_* definitions
* BOARD_APBC_FRQUENCY - In Hz
*/
#define BOARD_CPU_SHIFT 0 /* Fcpu = Fmck = 48MHz */
#define BOARD_PBA_SHIFT 0 /* Fpba = Fmck = 48MHz */
#define BOARD_PBB_SHIFT 0 /* Fpbb = Fmck = 48MHz */
#define BOARD_PBC_SHIFT 0 /* Fpbc = Fmck = 48MHz */
#define BOARD_PBD_SHIFT 0 /* Fpbd = Fmck = 48MHz */
#define BOARD_CPU_FAILDECT 1
#define BOARD_CPU_DIVIDER PM_CPUSEL_CPUDIV_1
#define BOARD_APBA_DIVIDER PM_APBASEL_APBADIV_1
#define BOARD_APBB_DIVIDER PM_APBBSEL_APBBDIV_1
#define BOARD_APBC_DIVIDER PM_APBCSEL_APBCDIV_1
/* Resulting frequencies */
#define BOARD_MCK_FREQUENCY (BOARD_GLCK_MAIN_FREQUENCY)
#define BOARD_CPU_FREQUENCY (BOARD_MCK_FREQUENCY >> BOARD_CPU_SHIFT)
#define BOARD_PBA_FREQUENCY (BOARD_MCK_FREQUENCY >> BOARD_PBA_SHIFT)
#define BOARD_PBB_FREQUENCY (BOARD_MCK_FREQUENCY >> BOARD_PBB_SHIFT)
#define BOARD_PBC_FREQUENCY (BOARD_MCK_FREQUENCY >> BOARD_PBC_SHIFT)
#define BOARD_PBD_FREQUENCY (BOARD_MCK_FREQUENCY >> BOARD_PBD_SHIFT)
#define BOARD_CPU_FREQUENCY (BOARD_MCK_FREQUENCY / 1)
#define BOARD_PBA_FREQUENCY (BOARD_MCK_FREQUENCY / 1)
#define BOARD_PBB_FREQUENCY (BOARD_MCK_FREQUENCY / 1)
#define BOARD_PBC_FREQUENCY (BOARD_MCK_FREQUENCY / 1)
#define BOARD_PBD_FREQUENCY (BOARD_MCK_FREQUENCY / 1)
/* FLASH wait states */
......
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