Add timer ISR

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2442 42af7a65-404d-4744-a932-0658087f49c3

arch/arm/src/lpc313x/Make.defs

@@ -47,7 +47,7 @@ CMN_CSRCS	= up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
 
 CGU_ASRCS	= 
 CGU_CSRCS	= lpc313x_clkdomain.c lpc313x_clkfreq.c lpc313x_esrndx.c \
-		  lpc313x_fdcndx.c
+		  lpc313x_fdcndx.c lpc313x_softreset.c
 
 CHIP_ASRCS	= $(CGU_ASRCS)
-CHIP_CSRCS	= lpc313x_irq.c lpc313x_allocateheap.c $(CGU_CSRCS)
+CHIP_CSRCS	= lpc313x_allocateheap.c lpc313x_irq.c lpc313x_timerisr.c $(CGU_CSRCS)

arch/arm/src/lpc313x/lpc313x_cgu.h

@@ -484,6 +484,10 @@
 #define LPC313X_CGU_WDBARK_OFFSET        0x004 /* Watch dog bark register */
 #define LPC313X_CGU_FFASTON_OFFSET       0x008 /* Activate fast oscillator register */
 #define LPC313X_CGU_FFASTBYP_OFFSET      0x00c /* Bypass comparator register fast oscillator reset */
+
+/* Reset control */
+
+#define LPC313X_CGU_SOFTRST_OFFSET(n)    (0x010+((n)<<2))
 #define LPC313X_CGU_APB0RST_OFFSET       0x010 /* Reset AHB part of AHB_TO_APB0 bridge */
 #define LPC313X_CGU_AHB2APB0RST_OFFSET   0x014 /* Reset APB part of AHB_TO_APB0 bridge */
 #define LPC313X_CGU_APB1RST_OFFSET       0x018 /* Reset AHB part of AHB_TO_APB1 bridge */
@@ -524,10 +528,11 @@
 #define LPC313X_CGU_LCDRST_OFFSET        0x0b4 /* Reset LCD Interface */
 #define LPC313X_CGU_SPIRSTAPB_OFFSET     0x0b8 /* Reset apb_clk domain of SPI */
 #define LPC313X_CGU_SPIRSTIP_OFFSET      0x0bc /* Reset ip_clk domain of SPI */
-#define LPC313X_CGU_DMA_RST_OFFSET       0x0c0 /* Reset DMA */
+#define LPC313X_CGU_DMARST_OFFSET        0x0c0 /* Reset DMA */
 #define LPC313X_CGU_NANDECCRST_OFFSET    0x0c4 /* Reset Nandflash Controller ECC clock */
                                                /* 0x0c8: Reserved */
 #define LPC313X_CGU_NANDCTRLRST_OFFSET   0x0cc /* Reset of Nandflash Controller */
+#define LPC313X_CGU_RNGRST_OFFSET        0x0d0 /* Reset of RNG */
 #define LPC313X_CGU_SDMMCRST_OFFSET      0x0d4 /* Reset MCI (on AHB clock) */
 #define LPC313X_CGU_SDMMCRSTCKIN_OFFSET  0x0d8 /* Reset MCI synchronous (on IP clock) */
 #define LPC313X_CGU_USBOTGAHBRST_OFFSET  0x0dc /* Reset USB_OTG */
@@ -986,6 +991,10 @@
 #define LPC313X_CGU_WDBARK               (LPC313X_CGU_CFG_VBASE+LPC313X_CGU_WDBARK_OFFSET)
 #define LPC313X_CGU_FFASTON              (LPC313X_CGU_CFG_VBASE+LPC313X_CGU_FFASTON_OFFSET)
 #define LPC313X_CGU_FFASTBYP             (LPC313X_CGU_CFG_VBASE+LPC313X_CGU_FFASTBYP_OFFSET)
+
+/* Reset control */
+
+#define LPC313X_CGU_SOFTRST(n)           (LPC313X_CGU_CFG_VBASE+LPC313X_CGU_SOFTRST_OFFSET(n))
 #define LPC313X_CGU_APB0RST              (LPC313X_CGU_CFG_VBASE+LPC313X_CGU_APB0RST_OFFSET)
 #define LPC313X_CGU_AHB2APB0RST          (LPC313X_CGU_CFG_VBASE+LPC313X_CGU_AHB2APB0RST_OFFSET)
 #define LPC313X_CGU_APB1RST              (LPC313X_CGU_CFG_VBASE+LPC313X_CGU_APB1RST_OFFSET)
@@ -1025,7 +1034,7 @@
 #define LPC313X_CGU_LCDRST               (LPC313X_CGU_CFG_VBASE+LPC313X_CGU_LCDRST_OFFSET)
 #define LPC313X_CGU_SPIRSTAPB            (LPC313X_CGU_CFG_VBASE+LPC313X_CGU_SPIRSTAPB_OFFSET)
 #define LPC313X_CGU_SPIRSTIP             (LPC313X_CGU_CFG_VBASE+LPC313X_CGU_SPIRSTIP_OFFSET)
-#define LPC313X_CGU_DMA_RST              (LPC313X_CGU_CFG_VBASE+LPC313X_CGU_DMA_RST_OFFSET)
+#define LPC313X_CGU_DMARST               (LPC313X_CGU_CFG_VBASE+LPC313X_CGU_DMARST_OFFSET)
 #define LPC313X_CGU_NANDECCRST           (LPC313X_CGU_CFG_VBASE+LPC313X_CGU_NANDECCRST_OFFSET)
 #define LPC313X_CGU_NANDCTRLRST          (LPC313X_CGU_CFG_VBASE+LPC313X_CGU_NANDCTRLRST_OFFSET)
 #define LPC313X_CGU_SDMMCRST             (LPC313X_CGU_CFG_VBASE+LPC313X_CGU_SDMMCRST_OFFSET)
@@ -1256,6 +1265,9 @@
 #define CGU_FFASTBYP_TESTMODE            (1 << 0)  /* Bit 0: Oscillator test mode */
 
 /* Reset control registers */
+
+#define CGU_SOFTRESET                    (1 << 0)  /* Bit 0: in all of the reset control registers */
+
 /* APB0_RESETN_SOFT register, address 0x13004c10 */
 
 #define CGU_APB0RST_RESET                (1 << 0)  /* Bit 0: Reserved */
@@ -1414,7 +1426,7 @@
 
 /* DMA_PNRES_SOFT register, address 0x13004cc0 */
 
-#define CGU_DMA_RST_RESET                (1 << 0)  /* Bit 0:  Reset for DMA */
+#define CGU_DMARST_RESET                 (1 << 0)  /* Bit 0:  Reset for DMA */
 
 /* NANDFLASH_CTRL_ECC_RESET_N_SOFT register, address 0x13004cc4 */
 
@@ -1628,6 +1640,7 @@
  ************************************************************************************************/
 
 #ifndef __ASSEMBLY__
+
 /************************************************************************************************
  * Public Data
  ************************************************************************************************/

arch/arm/src/lpc313x/lpc313x_cgudrvr.h

@@ -45,6 +45,7 @@
  ************************************************************************/
 
 #include <nuttx/config.h>
+#include "up_arch.h"
 #include "lpc313x_cgu.h"
 
 /************************************************************************
@@ -238,7 +239,7 @@ enum lpc313x_clockid_e
   CLKID_MPMCCFGCLK3,      /* 28 MPMC_CFG_CLK3 */
   CLKID_INTCCLK,          /* 29 INTC_CLK */
 
-  /* Domain 1: AHB0APB0BASE */
+  /* Domain 1: AHB0APB0_BASE */
 
   CLKID_AHB2APB0PCLK,     /* 30 AHB_TO_APB0_PCLK */
   CLKID_EVENTROUTERPCLK,  /* 31 EVENT_ROUTER_PCLK */
@@ -251,7 +252,7 @@ enum lpc313x_clockid_e
   CLKID_OTPPCLK,          /* 38 OTP_PCLK (Reserved on LPC313X) */
   CLKID_RNGPCLK,          /* 39 RNG_PCLK */
 
-  /* Domain 2: AHB0APB1BASE */
+  /* Domain 2: AHB0APB1_BASE */
 
   CLKID_AHB2APB1PCLK,     /* 40 AHB_TO_APB1_PCLK */
   CLKID_TIMER0PCLK,       /* 41 TIMER0_PCLK */
@@ -264,7 +265,7 @@ enum lpc313x_clockid_e
   CLKID_I2C0PCLK,         /* 48 I2C0_PCLK */
   CLKID_I2C1PCLK,         /* 49 I2C1_PCLK */
 
-  /* Domain 3: AHB0APB2BASE */
+  /* Domain 3: AHB0APB2_BASE */
 
   CLKID_AHB2APB2PCLK,     /* 50 AHB_TO_APB2_PCLK */
   CLKID_PCMPCLK,          /* 51 PCM_PCLK */
@@ -333,6 +334,68 @@ enum lpc313x_clockid_e
   CLKID_SYSCLKO           /* 91 SYSCLK_O */
 };
 
+/* Indices into the CGU configuration reset control registers */
+
+enum lpc313x_resetid_e
+{
+  RESETID_APB0RST,        /*  4 AHB part of AHB_TO_APB0 bridge (Reserved) */
+  RESETID_AHB2APB0RST,    /*  5 APB part of AHB_TO_APB0 bridge (Reserved) */
+  RESETID_APB1RST,        /*  6 AHB part of AHB_TO_APB1 bridge */
+  RESETID_AHB2PB1RST,     /*  7 APB part of AHB_TO_APB1 bridge */
+  RESETID_APB2RST,        /*  8 AHB part of AHB_TO_APB2 bridge */
+  RESETID_AHB2APB2RST,    /*  9 APB part of AHB_TO_APB2 bridge */
+  RESETID_APB3RST,        /* 10 AHB part of AHB_TO_APB3 bridge */
+  RESETID_AHB2APB3RST,    /* 11 APB part of AHB_TO_APB3 bridge */
+  RESETID_APB4RST,        /* 12 AHB_TO_APB4 bridge */
+  RESETID_AHB2INTCRST,    /* 13 AHB_TO_INTC */
+  RESETID_AHB0RST,        /* 14 AHB0 */
+  RESETID_EBIRST,         /* 15 EBI */
+  RESETID_PCMAPBRST,      /* 16 APB domain of PCM */
+  RESETID_PCMCLKIPRST,    /* 17 synchronous clk_ip domain of PCM */
+  RESETID_PCMRSTASYNC,    /* 18 asynchronous clk_ip domain of PCM */
+  RESETID_TIMER0RST,      /* 19 Timer0 */
+  RESETID_TIMER1RST,      /* 20 Timer1 */
+  RESETID_TIMER2RST,      /* 21 Timer2 */
+  RESETID_TIMER3RST,      /* 22 Timer3 */
+  RESETID_ADCPRST,        /* 23 controller of 10 bit ADC Interface */
+  RESETID_ADCRST,         /* 24 A/D converter of ADC Interface */
+  RESETID_PWMRST,         /* 25 PWM */
+  RESETID_UARTRST,        /* 26 UART/IrDA */
+  RESETID_I2C0RST,        /* 27 I2C0 */
+  RESETID_I2C1RST,        /* 28 I2C1 */
+  RESETID_I2SCFGRST,      /* 29 I2S_Config */
+  RESETID_I2SNSOFRST,     /* 30 NSOF counter of I2S_CONFIG */
+  RESETID_EDGEDETRST,     /* 31 Edge_det */
+  RESETID_I2STXFF0RST,    /* 32 I2STX_FIFO_0 */
+  RESETID_I2STXIF0RST,    /* 33 I2STX_IF_0 */
+  RESETID_I2STXFF1RST,    /* 34 I2STX_FIFO_1 */
+  RESETID_I2STXIF1RST,    /* 35 I2STX_IF_1 */
+  RESETID_I2SRXFF0RST,    /* 36 I2SRX_FIFO_0 */
+  RESETID_I2SRXIF0RST,    /* 37 I2SRX_IF_0 */
+  RESETID_I2SRXFF1RST,    /* 38 I2SRX_FIFO_1 */
+  RESETID_I2SRXIF1RST,    /* 39 I2SRX_IF_1 */
+  RESETID_RESERVED40,     /* 40 Reserved */    
+  RESETID_RESERVED41,     /* 41 Reserved */    
+  RESETID_RESERVED42,     /* 42 Reserved */    
+  RESETID_RESERVED43,     /* 43 Reserved */    
+  RESETID_RESERVED44,     /* 44 Reserved */ 
+  RESETID_LCDRST,         /* 45 LCD Interface */
+  RESETID_SPIRSTAPB,      /* 46 apb_clk domain of SPI */
+  RESETID_SPIRSTIP,       /* 47 ip_clk domain of SPI */
+  RESETID_DMARST,         /* 48 DMA */
+  RESETID_NANDECCRST,     /* 49 Nandflash Controller ECC clock */
+  RESETID_NANDAESRST,     /* 50 Nandflash Controller AES clock (reserved for lpc313x) */
+  RESETID_NANDCTRLRST,    /* 51 Nandflash Controller */
+  RESETID_RNG,            /* 52 RNG */
+  RESETID_SDMMCRST,       /* 53 MCI (on AHB clock) */
+  RESETID_SDMMCRSTCKIN,   /* 54 CI synchronous (on IP clock) */
+  RESETID_USBOTGAHBRST,   /* 55 USB_OTG */
+  RESETID_REDCTLRST,      /* 56 Redundancy Controller */
+  RESETID_AHBMPMCHRST,    /* 57 MPMC */
+  RESETID_AHBMPMCRFRST,   /* 58 refresh generator used for MPMC */
+  RESETID_INTCRST,        /* 59 Interrupt Controller */
+};
+
 /************************************************************************
  * Public Data
  ************************************************************************/
@@ -411,6 +474,16 @@ static inline void lpc313x_disableclock(enum lpc313x_clockid_e clkid)
  * Public Functions
  ************************************************************************/
 
+/************************************************************************
+ * Name: lpc313x_softreset
+ *
+ * Description:
+ *   Perform a soft reset on the specified module.
+ *
+ ************************************************************************/
+
+EXTERN void lpc313x_softreset(enum lpc313x_resetid_e resetid);
+
 /************************************************************************
  * Name: lpc313x_clkdomain
  *

arch/arm/src/lpc313x/lpc313x_softreset.c

+/************************************************************************
+ * arch/arm/src/lpc313x/lpc313x_softreset.c
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * References:
+ *   - UM10314 LPC3130/31 User manual Rev. 1.01 — 9 September 2009
+ *   - lpc313x.cdl.drivers.zip example driver code
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************/
+
+/************************************************************************
+ * Included Files
+ ************************************************************************/
+
+#include <nuttx/config.h>
+#include <stdint.h>
+
+#include "up_arch.h"
+#include "lpc313x_cgudrvr.h"
+
+/************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************/
+
+/************************************************************************
+ * Private Data
+ ************************************************************************/
+
+/************************************************************************
+ * Private Functions
+ ************************************************************************/
+
+/************************************************************************
+ * Public Functions
+ ************************************************************************/
+
+/************************************************************************
+ * Name: lpc313x_softreset
+ *
+ * Description:
+ *   Perform a soft reset on the specified module.
+ *
+ ************************************************************************/
+
+void lpc313x_softreset(enum lpc313x_resetid_e resetid)
+{
+  uint32_t address = LPC313X_CGU_SOFTRST(resetid);
+  volatile int i;
+
+  /* Clear and set the register */
+
+  putreg32(0, address);
+
+  /* Delay a bit */
+
+  for (i = 0;i < 1000; i++);
+
+  /* Then set the the soft reset bit */
+
+  putreg32(CGU_SOFTRESET, address);
+}

arch/arm/src/lpc313x/lpc313x_timerisr.c

+/****************************************************************************
+ * arch/arm/src/lpc313x/lpc313x_timerisr.c
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <time.h>
+#include <debug.h>
+
+#include <nuttx/arch.h>
+#include <arch/board/board.h>
+
+#include "clock_internal.h"
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "lpc313x_timer.h"
+#include "lpc313x_internal.h"
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Global Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Function:  up_timerisr
+ *
+ * Description:
+ *   The timer ISR will perform a variety of services for various portions
+ *   of the systems.
+ *
+ ****************************************************************************/
+
+int up_timerisr(int irq, uint32_t *regs)
+{
+  /* Clear the lattched timer interrupt (Writing any value to the CLEAR register
+   * clears the interrupt generated by the counter timer
+   */
+
+  putreg32(1, LPC313X_TIMER0_CLEAR);
+
+  /* Process timer interrupt */
+
+  sched_process_timer();
+  return 0;
+}
+
+/****************************************************************************
+ * Function:  up_timerinit
+ *
+ * Description:
+ *   This function is called during start-up to initialize
+ *   the timer interrupt.
+ *
+ ****************************************************************************/
+
+void up_timerinit(void)
+{
+  uint32_t regval;
+  uint64_t load;
+  uint64_t freq;
+
+  /* Enable the timer0 system clock */
+
+  lpc313x_enableclock(CLKID_TIMER0PCLK);
+
+  /* Soft reset the timer0 module so that we start in a known state */
+
+  lpc313x_softreset(RESETID_TIMER0RST);
+
+  /* Set timer load register to 10mS (100Hz).  First, get the frequency
+   * of the timer0 module clock (in the AHB0APB1_BASE domain (2)).
+   */
+
+  freq = (uint64_t)lpc313x_clkfreq(CLKID_TIMER0PCLK, DOMAINID_AHB0APB1);
+
+  /* If the clock is >1MHz, use pre-dividers */
+
+  regval = getreg32(LPC313X_TIMER0_CTRL);
+  if (freq > 1000000)
+  {
+    /* Use the divide by 16 pre-divider */
+
+    regval &= ~TIMER_CTRL_PRESCALE_MASK;
+    regval |=  TIMER_CTRL_PRESCALE_DIV16;
+    freq   >>= 4;
+  }
+
+  load =((freq * (uint64_t)10000) / 1000000);
+  putreg32((uint32_t)load, LPC313X_TIMER0_LOAD);
+
+  /* Set periodic mode */
+
+  regval |= TIMER_CTRL_PERIODIC;
+  putreg32(regval, LPC313X_TIMER0_CTRL);
+
+  /* Attach the timer interrupt vector */
+
+  (void)irq_attach(LPC313X_IRQ_TMR0, (xcpt_t)up_timerisr);
+
+   /* Clear any latched timer interrupt (Writing any value to the CLEAR register
+   * clears the latched interrupt generated by the counter timer)
+   */
+
+  putreg32(1, LPC313X_TIMER0_CLEAR);
+
+  /* Enable timers (starts counting) */
+
+  regval |= TIMER_CTRL_ENABLE;
+  putreg32(regval, LPC313X_TIMER0_CTRL);
+
+  /* Enable timer match interrupts in the interrupt controller */
+
+  up_enable_irq(LPC313X_IRQ_TMR0);
+}