i.MX6: Clean up some initializers

arch/arm/src/imx6/imx_cpuboot.c

@@ -70,44 +70,44 @@ typedef CODE void (*cpu_start_t)(void);
 #if 0 /* Not used */
 static const uint32_t g_cpu_reset[CONFIG_SMP_NCPUS] =
 {
-  0,
+    SRC_SCR_CORE0_RST
 #if CONFIG_SMP_NCPUS > 1
-  SRC_SCR_CORE1_RST,
+  , SRC_SCR_CORE1_RST
 #endif
 #if CONFIG_SMP_NCPUS > 2
-  SRC_SCR_CORE2_RST,
+  , SRC_SCR_CORE2_RST
 #endif
 #if CONFIG_SMP_NCPUS > 3
-  SRC_SCR_CORE3_RST
+  , SRC_SCR_CORE3_RST
 #endif
 };
 #endif
 
 static const uint32_t g_cpu_ctrl[CONFIG_SMP_NCPUS] =
 {
-  0,
+    0
 #if CONFIG_SMP_NCPUS > 1
-  SRC_SCR_CORE1_ENABLE,
+  , SRC_SCR_CORE1_ENABLE
 #endif
 #if CONFIG_SMP_NCPUS > 2
-  SRC_SCR_CORE2_ENABLE,
+  , SRC_SCR_CORE2_ENABLE
 #endif
 #if CONFIG_SMP_NCPUS > 3
-  SRC_SCR_CORE3_ENABLE
+  , SRC_SCR_CORE3_ENABLE
 #endif
 };
 
 static const uintptr_t g_cpu_gpr[CONFIG_SMP_NCPUS] =
 {
-  0,
+    IMX_SRC_GPR1
 #if CONFIG_SMP_NCPUS > 1
-  IMX_SRC_GPR3,
+  , IMX_SRC_GPR3
 #endif
 #if CONFIG_SMP_NCPUS > 2
-  IMX_SRC_GPR5,
+  , IMX_SRC_GPR5
 #endif
 #if CONFIG_SMP_NCPUS > 3
-  IMX_SRC_GPR7
+  , IMX_SRC_GPR7
 #endif
 };
 

arch/arm/src/lpc43xx/chip/lpc4337jet100_pinconfig.h

 /****************************************************************************************************
  * arch/arm/src/lpc43xx/chip/lpc4337jet100_pinconfig.h
  *
- *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without