Kinetis:Refactor you use SIM_SOPT2_PLLFLLSEL, added warning
The warning has been added because: SIM_SOPT2_PLLFLLSEL is a clock selection that may feed many clock subsystem: USB, TPM, SDHCSRC, LPUARTSRC. Therefore, there needs to be a global board level setting to select the source for SIM_SOPT2_PLLFLLSEL and then derive all the sub selections and proper fractions/divisors for each modules clock.
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12c24f26
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