STM32L15X UART, DMA, and heap initialization support

ChangeLog

@@ -4739,4 +4739,6 @@
 	  More updates for the STM32L152 (2013-5-19).
 	* configs/stm32ldiscovey: Configuration for the STM32L-Discovery board.
 	  Still does not build on initial check-in (2013-5-19)
+	* STM32L15X:  Add DMA and UART start.  Correctly initialize the heap
+	  (2013-5-19).
 

arch/arm/src/stm32/chip/stm32f10xxx_dma.h

@@ -269,7 +269,7 @@
 /* DMA channel number of data register */
 
 #define DMA_CNDTR_NDT_SHIFT       (0)       /* Bits 15-0: Number of data to Transfer */
-#define DMA_CNDTR_NDT_MASK       (0xffff << DMA_CNDTR_NDT_SHIFT)
+#define DMA_CNDTR_NDT_MASK        (0xffff << DMA_CNDTR_NDT_SHIFT)
 
 /* DMA Channel mapping.  Each DMA channel has a mapping to several possible
  * sources/sinks of data.  The requests from peripherals assigned to a channel
@@ -295,7 +295,70 @@
 #define STM32_DMA2_CHAN4          (10)
 #define STM32_DMA2_CHAN5          (11)
 
-#if defined(CONFIG_STM32_STM32F10XX)
+#if defined(CONFIG_STM32_STM32L15XX)
+
+#  define DMACHAN_ADC1            STM32_DMA1_CHAN1
+#  define DMACHAN_TIM2_CH3        STM32_DMA1_CHAN1
+#  define DMACHAN_TIM4_CH1        STM32_DMA1_CHAN1
+
+#  define DMACHAN_SPI1_RX         STM32_DMA1_CHAN2
+#  define DMACHAN_USART3_TX       STM32_DMA1_CHAN2
+#  define DMACHAN_TIM2_UP         STM32_DMA1_CHAN2
+#  define DMACHAN_TIM3_CH3        STM32_DMA1_CHAN2
+#  define DMACHAN_TIM6_UP         STM32_DMA1_CHAN2
+#  define DMACHAN_DAC_CHAN1       STM32_DMA1_CHAN2
+
+#  define DMACHAN_SPI1_TX         STM32_DMA1_CHAN3
+#  define DMACHAN_USART3_RX       STM32_DMA1_CHAN3
+#  define DMACHAN_TIM3_CH4        STM32_DMA1_CHAN3
+#  define DMACHAN_TIM3_UP         STM32_DMA1_CHAN3
+#  define DMACHAN_TIM7_UP         STM32_DMA1_CHAN3
+#  define DMACHAN_DAC_CHAN2       STM32_DMA1_CHAN3
+
+#  define DMACHAN_SPI2_RX         STM32_DMA1_CHAN4
+#  define DMACHAN_USART1_TX       STM32_DMA1_CHAN4
+#  define DMACHAN_I2C2_TX         STM32_DMA1_CHAN4
+#  define DMACHAN_TIM4_CH2        STM32_DMA1_CHAN4
+
+#  define DMACHAN_SPI2_TX         STM32_DMA1_CHAN5
+#  define DMACHAN_USART1_RX       STM32_DMA1_CHAN5
+#  define DMACHAN_I2C2_RX         STM32_DMA1_CHAN5
+#  define DMACHAN_TIM2_CH1        STM32_DMA1_CHAN5
+#  define DMACHAN_TIM4_CH3        STM32_DMA1_CHAN5
+
+#  define DMACHAN_USART2_RX       STM32_DMA1_CHAN6
+#  define DMACHAN_I2C1_TX         STM32_DMA1_CHAN6
+#  define DMACHAN_TIM3_CH1        STM32_DMA1_CHAN6
+#  define DMACHAN_TIM3_TRIG       STM32_DMA1_CHAN6
+
+#  define DMACHAN_USART2_TX       STM32_DMA1_CHAN7
+#  define DMACHAN_I2C1_RX         STM32_DMA1_CHAN7
+#  define DMACHAN_TIM2_CH2        STM32_DMA1_CHAN7
+#  define DMACHAN_TIM2_CH4        STM32_DMA1_CHAN7
+#  define DMACHAN_TIM4_UP         STM32_DMA1_CHAN7
+
+#  define DMACHAN_SPI3_RX         STM32_DMA2_CHAN1
+#  define DMACHAN_USART5_TX       STM32_DMA2_CHAN1
+#  define DMACHAN_TIM5_CH4        STM32_DMA2_CHAN1
+#  define DMACHAN_TIM5_TRIG       STM32_DMA2_CHAN1
+#  define DMACHAN_TIM5_COM        STM32_DMA2_CHAN1
+
+#  define DMACHAN_SPI3_TX         STM32_DMA2_CHAN2
+#  define DMACHAN_USART5_RX       STM32_DMA2_CHAN2
+#  define DMACHAN_TIM5_CH3        STM32_DMA2_CHAN2
+#  define DMACHAN_TIM5_UP         STM32_DMA2_CHAN2
+
+#  define DMACHAN_UART4_RX        STM32_DMA2_CHAN3
+#  define DMACHAN_AES_OUT         STM32_DMA2_CHAN3
+
+#  define DMACHAN_TIM5_CH2        STM32_DMA2_CHAN4
+#  define DMACHAN_SDIO            STM32_DMA2_CHAN4
+
+#  define DMACHAN_UART4_TX        STM32_DMA2_CHAN5
+#  define DMACHAN_TIM5_CH1        STM32_DMA2_CHAN5
+#  define DMACHAN_AES_IN          STM32_DMA2_CHAN5
+
+#elif defined(CONFIG_STM32_STM32F10XX)
 
 #  define DMACHAN_ADC1            STM32_DMA1_CHAN1
 #  define DMACHAN_TIM2_CH3        STM32_DMA1_CHAN1
@@ -353,7 +416,6 @@
 #  define DMACHAN_I2S3_TX         STM32_DMA2_CHAN2
 #  define DMACHAN_TIM5_CH3        STM32_DMA2_CHAN2
 #  define DMACHAN_TIM5_UP         STM32_DMA2_CHAN2
-#  define DMACHAN_TIM5_UP         STM32_DMA2_CHAN2
 #  define DMACHAN_TIM8_TRIG       STM32_DMA2_CHAN2
 #  define DMACHAN_TIM8_COM        STM32_DMA2_CHAN2
 

arch/arm/src/stm32/chip/stm32l15xxx_uart.h

+/************************************************************************************
+ * arch/arm/src/stm32/chip/stm32l15xxx_uart.h
+ * For STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx advanced ARM-based
+ * 32-bit MCUs
+ *
+ *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_STC_STM32_CHIP_STM32L15XXX_UART_H
+#define __ARCH_ARM_STC_STM32_CHIP_STM32L15XXX_UART_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_USART_SR_OFFSET     0x0000  /* Status register (32-bits) */
+#define STM32_USART_DR_OFFSET     0x0004  /* Data register (32-bits) */
+#define STM32_USART_BRR_OFFSET    0x0008  /* Baud Rate Register (32-bits) */
+#define STM32_USART_CR1_OFFSET    0x000c  /* Control register 1 (32-bits) */
+#define STM32_USART_CR2_OFFSET    0x0010  /* Control register 2 (32-bits) */
+#define STM32_USART_CR3_OFFSET    0x0014  /* Control register 3 (32-bits) */
+#define STM32_USART_GTPR_OFFSET   0x0018  /* Guard time and prescaler register (32-bits) */
+
+/* Register Addresses ***************************************************************/
+
+#if STM32_NUSART > 0
+#  define STM32_USART1_SR         (STM32_USART1_BASE+STM32_USART_SR_OFFSET)
+#  define STM32_USART1_DR         (STM32_USART1_BASE+STM32_USART_DR_OFFSET)
+#  define STM32_USART1_BRR        (STM32_USART1_BASE+STM32_USART_BRR_OFFSET)
+#  define STM32_USART1_CR1        (STM32_USART1_BASE+STM32_USART_CR1_OFFSET)
+#  define STM32_USART1_CR2        (STM32_USART1_BASE+STM32_USART_CR2_OFFSET)
+#  define STM32_USART1_CR3        (STM32_USART1_BASE+STM32_USART_CR3_OFFSET)
+#  define STM32_USART1_GTPR       (STM32_USART1_BASE+STM32_USART_GTPR_OFFSET)
+#endif
+
+#if STM32_NUSART > 1
+#  define STM32_USART2_SR         (STM32_USART2_BASE+STM32_USART_SR_OFFSET)
+#  define STM32_USART2_DR         (STM32_USART2_BASE+STM32_USART_DR_OFFSET)
+#  define STM32_USART2_BRR        (STM32_USART2_BASE+STM32_USART_BRR_OFFSET)
+#  define STM32_USART2_CR1        (STM32_USART2_BASE+STM32_USART_CR1_OFFSET)
+#  define STM32_USART2_CR2        (STM32_USART2_BASE+STM32_USART_CR2_OFFSET)
+#  define STM32_USART2_CR3        (STM32_USART2_BASE+STM32_USART_CR3_OFFSET)
+#  define STM32_USART2_GTPR       (STM32_USART2_BASE+STM32_USART_GTPR_OFFSET)
+#endif
+
+#if STM32_NUSART > 2
+#  define STM32_USART3_SR         (STM32_USART3_BASE+STM32_USART_SR_OFFSET)
+#  define STM32_USART3_DR         (STM32_USART3_BASE+STM32_USART_DR_OFFSET)
+#  define STM32_USART3_BRR        (STM32_USART3_BASE+STM32_USART_BRR_OFFSET)
+#  define STM32_USART3_CR1        (STM32_USART3_BASE+STM32_USART_CR1_OFFSET)
+#  define STM32_USART3_CR2        (STM32_USART3_BASE+STM32_USART_CR2_OFFSET)
+#  define STM32_USART3_CR3        (STM32_USART3_BASE+STM32_USART_CR3_OFFSET)
+#  define STM32_USART3_GTPR       (STM32_USART3_BASE+STM32_USART_GTPR_OFFSET)
+#endif
+
+#if STM32_NUSART > 3
+#  define STM32_USART4_SR         (STM32_USART4_BASE+STM32_USART_SR_OFFSET)
+#  define STM32_USART4_DR         (STM32_USART4_BASE+STM32_USART_DR_OFFSET)
+#  define STM32_USART4_BRR        (STM32_USART4_BASE+STM32_USART_BRR_OFFSET)
+#  define STM32_USART4_CR1        (STM32_USART4_BASE+STM32_USART_CR1_OFFSET)
+#  define STM32_USART4_CR2        (STM32_USART4_BASE+STM32_USART_CR2_OFFSET)
+#  define STM32_USART4_CR3        (STM32_USART4_BASE+STM32_USART_CR3_OFFSET)
+#endif
+
+#if STM32_NUSART > 4
+#  define STM32_USART5_SR         (STM32_USART5_BASE+STM32_USART_SR_OFFSET)
+#  define STM32_USART5_DR         (STM32_USART5_BASE+STM32_USART_DR_OFFSET)
+#  define STM32_USART5_BRR        (STM32_USART5_BASE+STM32_USART_BRR_OFFSET)
+#  define STM32_USART5_CR1        (STM32_USART5_BASE+STM32_USART_CR1_OFFSET)
+#  define STM32_USART5_CR2        (STM32_USART5_BASE+STM32_USART_CR2_OFFSET)
+#  define STM32_USART5_CR3        (STM32_USART5_BASE+STM32_USART_CR3_OFFSET)
+#endif
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* Status register */
+
+#define USART_SR_PE               (1 << 0)  /* Bit 0: Parity Error */
+#define USART_SR_FE               (1 << 1)  /* Bit 1: Framing Error */
+#define USART_SR_NE               (1 << 2)  /* Bit 2: Noise Error Flag */
+#define USART_SR_ORE              (1 << 3)  /* Bit 3: OverRun Error */
+#define USART_SR_IDLE             (1 << 4)  /* Bit 4: IDLE line detected */
+#define USART_SR_RXNE             (1 << 5)  /* Bit 5: Read Data Register Not Empty */
+#define USART_SR_TC               (1 << 6)  /* Bit 6: Transmission Complete */
+#define USART_SR_TXE              (1 << 7)  /* Bit 7: Transmit Data Register Empty */
+#define USART_SR_LBD              (1 << 8)  /* Bit 8: LIN Break Detection Flag */
+#define USART_SR_CTS              (1 << 9)  /* Bit 9: CTS Flag */
+
+#define USART_SR_ALLBITS          (0x03ff)
+#define USART_SR_CLRBITS          (USART_SR_CTS|USART_SR_LBD) /* Cleared by SW write to SR */
+
+/* Data register */
+
+#define USART_DR_SHIFT            (0)       /* Bits 8:0: Data value */
+#define USART_DR_MASK             (0x1ff << USART_DR_SHIFT)
+
+/* Baud Rate Register */
+
+#define USART_BRR_FRAC_SHIFT      (0)       /* Bits 3-0: fraction of USARTDIV */
+#define USART_BRR_FRAC_MASK       (0x0f << USART_BRR_FRAC_SHIFT)
+#define USART_BRR_MANT_SHIFT      (4)       /* Bits 15-4: mantissa of USARTDIV */
+#define USART_BRR_MANT_MASK       (0x0fff << USART_BRR_MANT_SHIFT)
+
+/* Control register 1 */
+
+#define USART_CR1_SBK             (1 << 0)  /* Bit 0: Send Break */
+#define USART_CR1_RWU             (1 << 1)  /* Bit 1: Receiver wakeup */
+#define USART_CR1_RE              (1 << 2)  /* Bit 2: Receiver Enable */
+#define USART_CR1_TE              (1 << 3)  /* Bit 3: Transmitter Enable */
+#define USART_CR1_IDLEIE          (1 << 4)  /* Bit 4: IDLE Interrupt Enable */
+#define USART_CR1_RXNEIE          (1 << 5)  /* Bit 5: RXNE Interrupt Enable */
+#define USART_CR1_TCIE            (1 << 6)  /* Bit 6: Transmission Complete Interrupt Enable */
+#define USART_CR1_TXEIE           (1 << 7)  /* Bit 7: TXE Interrupt Enable */
+#define USART_CR1_PEIE            (1 << 8)  /* Bit 8: PE Interrupt Enable */
+#define USART_CR1_PS              (1 << 9)  /* Bit 9: Parity Selection */
+#define USART_CR1_PCE             (1 << 10) /* Bit 10: Parity Control Enable */
+#define USART_CR1_WAKE            (1 << 11) /* Bit 11: Wakeup method */
+#define USART_CR1_M               (1 << 12) /* Bit 12: word length */
+#define USART_CR1_UE              (1 << 13) /* Bit 13: USART Enable */
+#define USART_CR1_OVER8           (1 << 15) /* Bit 15: Oversampling mode */
+
+#define USART_CR1_ALLINTS         (USART_CR1_IDLEIE|USART_CR1_RXNEIE|USART_CR1_TCIE|USART_CR1_PEIE)
+
+/* Control register 2 */
+
+#define USART_CR2_ADD_SHIFT       (0)       /* Bits 3-0: Address of the USART node */
+#define USART_CR2_ADD_MASK        (0x0f << USART_CR2_ADD_SHIFT)
+#define USART_CR2_LBDL            (1 << 5)  /* Bit 5: LIN Break Detection Length */
+#define USART_CR2_LBDIE           (1 << 6)  /* Bit 6: LIN Break Detection Interrupt Enable */
+#define USART_CR2_LBCL            (1 << 8)  /* Bit 8: Last Bit Clock pulse */
+#define USART_CR2_CPHA            (1 << 9)  /* Bit 9: Clock Phase */
+#define USART_CR2_CPOL            (1 << 10) /* Bit 10: Clock Polarity */
+#define USART_CR2_CLKEN           (1 << 11) /* Bit 11: Clock Enable */
+#define USART_CR2_STOP_SHIFT      (12)      /* Bits 13-12: STOP bits */
+#define USART_CR2_STOP_MASK       (3 << USART_CR2_STOP_SHIFT)
+#  define USART_CR2_STOP1         (0 << USART_CR2_STOP_SHIFT) /* 00: 1 Stop bit */
+#  define USART_CR2_STOP0p5       (1 << USART_CR2_STOP_SHIFT) /* 01: 0.5 Stop bit */
+#  define USART_CR2_STOP2         (2 << USART_CR2_STOP_SHIFT) /* 10: 2 Stop bits */
+#  define USART_CR2_STOP1p5       (3 << USART_CR2_STOP_SHIFT) /* 11: 1.5 Stop bit */
+#define USART_CR2_LINEN           (1 << 14) /* Bit 14: LIN mode enable */
+
+/* Control register 3 */
+
+#define USART_CR3_EIE             (1 << 0)  /* Bit 0: Error Interrupt Enable */
+#define USART_CR3_IREN            (1 << 1)  /* Bit 1: IrDA mode Enable */
+#define USART_CR3_IRLP            (1 << 2)  /* Bit 2: IrDA Low-Power */
+#define USART_CR3_HDSEL           (1 << 3)  /* Bit 3: Half-Duplex Selection */
+#define USART_CR3_NACK            (1 << 4)  /* Bit 4: Smartcard NACK enable */
+#define USART_CR3_SCEN            (1 << 5)  /* Bit 5: Smartcard mode enable */
+#define USART_CR3_DMAR            (1 << 6)  /* Bit 6: DMA Enable Receiver */
+#define USART_CR3_DMAT            (1 << 7)  /* Bit 7: DMA Enable Transmitter */
+#define USART_CR3_RTSE            (1 << 8)  /* Bit 8: RTS Enable */
+#define USART_CR3_CTSE            (1 << 9)  /* Bit 9: CTS Enable */
+#define USART_CR3_CTSIE           (1 << 10) /* Bit 10: CTS Interrupt Enable */
+#define USART_CR1_ONEBIT          (1 << 11) /* Bit 11: One sample bit method enable */
+
+/* Guard time and prescaler register */
+
+#define USART_GTPR_PSC_SHIFT      (0) /* Bits 0-7: Prescaler value */
+#define USART_GTPR_PSC_MASK       (0xff << USART_GTPR_PSC_SHIFT)
+#define USART_GTPR_GT_SHIFT       (8) /* Bits 8-15: Guard time value */
+#define USART_GTPR_GT_MASK        (0xff <<  USART_GTPR_GT_SHIFT)
+
+/* Compatibility definitions ********************************************************/
+/* L15 Transmit/Read registers */
+
+#define STM32_USART_RDR_OFFSET    STM32_USART_DR_OFFSET  /* Receive data register */
+#define STM32_USART_TDR_OFFSET    STM32_USART_DR_OFFSET  /* Transmit data register */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_STC_STM32_CHIP_STM32L15XXX_UART_H */

arch/arm/src/stm32/chip/stm32l15xxx_vectors.h

 /************************************************************************************
  * arch/arm/src/stm32/chip/stm32l15xxx_vectors.h
- * For STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx advanced ARM-based 32-bit MCUs
+ * For STM32L100xx, STM32L151xx, STM32L152xx and STM32L162xx advanced ARM-based
+ * 32-bit MCUs
  *
  *   Copyright (C) 2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>

arch/arm/src/stm32/stm32_allocateheap.c

@@ -92,12 +92,37 @@
 #  undef CONFIG_STM32_FSMC_SRAM
 #endif
 
+/* The STM32L15xxx family has only internal SRAM.  The heap is in one contiguous
+ * block starting at g_idle_topstack and extending through CONFIG_DRAM_END.
+ */
+
+#if defined(CONFIG_STM32_STM32L15XX)
+
+   /* Set the end of system SRAM */
+
+#  define SRAM1_END CONFIG_DRAM_END
+
+   /* There is no FSMC (Other EnergyLite STM32's do have an FSMC, but not the STM32L15X */
+
+#  undef CONFIG_STM32_FSMC_SRAM
+
+   /* The STM32L EnergyLite family has no CCM SRAM */
+
+#  undef CONFIG_STM32_CCMEXCLUDE
+#  define CONFIG_STM32_CCMEXCLUDE 1
+
+   /* Only one memory region can be support (internal SRAM) */
+ 
+#  if CONFIG_MM_REGIONS > 1
+#    error "CONFIG_MM_REGIONS > 1.  The STM32L15X has only one memory region."
+#  endif
+
 /* For the STM312F10xxx family, all internal SRAM is in one contiguous block
- * starting at g_idle_topstack and extending through CONFIG_DRAM_END (my apologies for
- * the bad naming).  In addition, external FSMC SRAM may be available.
+ * starting at g_idle_topstack and extending through CONFIG_DRAM_END (my apologies
+ * for the bad naming).  In addition, external FSMC SRAM may be available.
  */
 
-#if defined(CONFIG_STM32_STM32F10XX)
+#elif defined(CONFIG_STM32_STM32F10XX)
 
    /* Set the end of system SRAM */
 

arch/arm/src/stm32/stm32_dma.c

@@ -71,7 +71,8 @@
  * channels.
  */
 
-#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
+#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
+    defined(CONFIG_STM32_STM32F30XX)
 #  include "stm32f10xxx_dma.c"
 #elif defined(CONFIG_STM32_STM32F20XX)
 #  include "stm32f20xxx_dma.c"

arch/arm/src/stm32/stm32_dma.h

@@ -47,7 +47,8 @@
 
 /* Include the correct DMA register definitions for this STM32 family */
 
-#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
+#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
+    defined(CONFIG_STM32_STM32F30XX)
 #  include "chip/stm32f10xxx_dma.h"
 #elif defined(CONFIG_STM32_STM32F20XX)
 #  include "chip/stm32f20xxx_dma.h"
@@ -61,7 +62,8 @@
  * DMA callback function (see dma_callback_t).
  */
 
-#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
+#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
+    defined(CONFIG_STM32_STM32F30XX)
 #  define DMA_STATUS_FEIF         0                     /* (Not available in F1) */
 #  define DMA_STATUS_DMEIF        0                     /* (Not available in F1) */
 #  define DMA_STATUS_TEIF         DMA_CHAN_TEIF_BIT     /* Channel Transfer Error */
@@ -103,7 +105,8 @@ typedef FAR void *DMA_HANDLE;
 typedef void (*dma_callback_t)(DMA_HANDLE handle, uint8_t status, void *arg);
 
 #ifdef CONFIG_DEBUG_DMA
-#if defined(CONFIG_STM32_STM32F10XX) || defined(CONFIG_STM32_STM32F30XX)
+#if defined(CONFIG_STM32_STM32L15XX) || defined(CONFIG_STM32_STM32F10XX) || \
+    defined(CONFIG_STM32_STM32F30XX)
 struct stm32_dmaregs_s
 {
   uint32_t isr;

arch/arm/src/stm32/stm32_uart.h

 /************************************************************************************
  * arch/arm/src/stm32/stm32_uart.h
  *
- *   Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009, 2012-2013 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -44,7 +44,9 @@
 
 #include "chip.h"
 
-#if defined(CONFIG_STM32_STM32F10XX)
+#if defined(CONFIG_STM32_STM32L15XX)
+#  include "chip/stm32l15xxx_uart.h"
+#elif defined(CONFIG_STM32_STM32F10XX)
 #  include "chip/stm32f10xxx_uart.h"
 #elif defined(CONFIG_STM32_STM32F20XX)
 #  include "chip/stm32f20xxx_uart.h"