arch/arm/src/stm32f7: Completes support for the STM32F72x/73x family.

arch/arm/src/stm32f7/chip/stm32_adc.h

@@ -44,7 +44,9 @@
 #include <nuttx/config.h>
 #include "chip.h"
 
-#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
+#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
+#  include "chip/stm32f72xx73xx_adc.h"
+#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
     defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
 #  include "chip/stm32f74xx77xx_adc.h"
 #else

arch/arm/src/stm32f7/chip/stm32_sdmmc.h

@@ -45,8 +45,9 @@
 #include <nuttx/config.h>
 #include "chip.h"
 
-#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) || \
-    defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
+#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
+#  include "stm32f72xx73xx_sdmmc.h"
+#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
     defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
 #  include "stm32f74xx77xx_sdmmc.h"
 #else

arch/arm/src/stm32f7/chip/stm32_spi.h

@@ -45,8 +45,9 @@
 #include <nuttx/config.h>
 #include "chip.h"
 
-#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX) || \
-    defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
+#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
+#  include "chip/stm32f72xx73xx_spi.h"
+#elif defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
     defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
 #  include "chip/stm32f74xx77xx_spi.h"
 #else

arch/arm/src/stm32f7/chip/stm32f72xx73xx_memorymap.h

@@ -159,6 +159,7 @@
 
 /* AHB1 Base Addresses **************************************************************/
 
+#define STM32_GPIO_INCR      0x400          /* 1K spacing between GPIO groups */
 #define STM32_GPIOA_BASE     0x40020000     /* 0x40020000-0x400203ff: GPIOA */
 #define STM32_GPIOB_BASE     0x40020400     /* 0x40020400-0x400207ff: GPIOB */
 #define STM32_GPIOC_BASE     0x40020800     /* 0x40020800-0x40020bff: GPIOC */

arch/arm/src/stm32f7/chip/stm32f72xx73xx_pinmap.h

@@ -52,7 +52,7 @@
  * Pre-processor Definitions
  ************************************************************************************/
 
-/* Alternate Pin Functions.  All members of the STM32F72|3xxx family share the same
+/* Alternate Pin Functions.  All members of the STM32F72|73xxx family share the same
  * pin multiplexing (although they may differ in the pins physically available).
  *
  * Alternative pin selections are provided with a numeric suffix like _1, _2, etc.

arch/arm/src/stm32f7/chip/stm32f72xx73xx_sdmmc.h

+ /* arch/arm/src/stm32f7/chip/stm32f72xx73xx_sdmmc.h
+ *
+ *   Copyright (C) 2009, 2011-2017 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *            David Sidrane <david_s5@nscdg.com>
+ *            Bob Feretich <bob.feretich@rafresearch.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_SDMMC_H
+#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_SDMMC_H
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_SDMMC_POWER_OFFSET              0x0000 /* SDMMC power control register */
+#define STM32_SDMMC_CLKCR_OFFSET              0x0004 /* SDMMC clock control register */
+#define STM32_SDMMC_ARG_OFFSET                0x0008 /* SDMMC argument register */
+#define STM32_SDMMC_CMD_OFFSET                0x000c /* SDMMC command register */
+#define STM32_SDMMC_RESPCMD_OFFSET            0x0010 /* SDMMC command response register */
+#define STM32_SDMMC_RESP_OFFSET(n)            (0x0010+4*(n))
+#define STM32_SDMMC_RESP1_OFFSET              0x0014 /* SDMMC response 1 register */
+#define STM32_SDMMC_RESP2_OFFSET              0x0018 /* SDMMC response 2 register */
+#define STM32_SDMMC_RESP3_OFFSET              0x001c /* SDMMC response 3 register */
+#define STM32_SDMMC_RESP4_OFFSET              0x0020 /* SDMMC response 4 register */
+#define STM32_SDMMC_DTIMER_OFFSET             0x0024 /* SDMMC data timer register */
+#define STM32_SDMMC_DLEN_OFFSET               0x0028 /* SDMMC data length register */
+#define STM32_SDMMC_DCTRL_OFFSET              0x002c /* SDMMC data control register */
+#define STM32_SDMMC_DCOUNT_OFFSET             0x0030 /* SDMMC data counter register */
+#define STM32_SDMMC_STA_OFFSET                0x0034 /* SDMMC status register */
+#define STM32_SDMMC_ICR_OFFSET                0x0038 /* SDMMC interrupt clear register */
+#define STM32_SDMMC_MASK_OFFSET               0x003c /* SDMMC mask register */
+#define STM32_SDMMC_FIFOCNT_OFFSET            0x0048 /* SDMMC FIFO counter register */
+#define STM32_SDMMC_FIFO_OFFSET               0x0080 /* SDMMC data FIFO register */
+
+
+/* Register Bitfield Definitions ****************************************************/
+
+#define STM32_SDMMC_POWER_PWRCTRL_SHIFT       (0)       /* Bits 0-1: Power supply control bits */
+#define STM32_SDMMC_POWER_PWRCTRL_MASK        (3 << STM32_SDMMC_POWER_PWRCTRL_SHIFT)
+#  define STM32_SDMMC_POWER_PWRCTRL_OFF       (0 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) /* 00: Power-off: card clock stopped */
+#  define STM32_SDMMC_POWER_PWRCTRL_PWRUP     (2 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) /* 10: Reserved power-up */
+#  define STM32_SDMMC_POWER_PWRCTRL_ON        (3 << STM32_SDMMC_POWER_PWRCTRL_SHIFT) /* 11: Power-on: card is clocked */
+
+#define STM32_SDMMC_POWER_RESET               (0)       /* Reset value */
+
+#define STM32_SDMMC_CLKCR_CLKDIV_SHIFT        (0)       /* Bits 7-0: Clock divide factor */
+#define STM32_SDMMC_CLKCR_CLKDIV_MASK         (0xff << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+#define STM32_SDMMC_CLKCR_CLKEN               (1 << 8)  /* Bit 8: Clock enable bit */
+#define STM32_SDMMC_CLKCR_PWRSAV              (1 << 9)  /* Bit 9: Power saving configuration bit */
+#define STM32_SDMMC_CLKCR_BYPASS              (1 << 10) /* Bit 10: Clock divider bypass enable bit */
+#define STM32_SDMMC_CLKCR_WIDBUS_SHIFT        (11)      /* Bits 12-11: Wide bus mode enable bits */
+#define STM32_SDMMC_CLKCR_WIDBUS_MASK         (3 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT)
+#  define STM32_SDMMC_CLKCR_WIDBUS_D1         (0 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 00: Default (STM32_SDMMC_D0) */
+#  define STM32_SDMMC_CLKCR_WIDBUS_D4         (1 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 01: 4-wide (STM32_SDMMC_D[3:0]) */
+#  define STM32_SDMMC_CLKCR_WIDBUS_D8         (2 << STM32_SDMMC_CLKCR_WIDBUS_SHIFT) /* 10: 8-wide (STM32_SDMMC_D[7:0]) */
+#define STM32_SDMMC_CLKCR_NEGEDGE             (1 << 13) /* Bit 13: STM32_SDMMC_CK dephasing selection bit */
+#define STM32_SDMMC_CLKCR_HWFC_EN             (1 << 14) /* Bit 14: HW Flow Control enable */
+
+#define STM32_SDMMC_CLKCR_RESET               (0)       /* Reset value */
+
+#define STM32_SDMMC_ARG_RESET                 (0)       /* Reset value */
+
+#define STM32_SDMMC_CMD_CMDINDEX_SHIFT        (0)
+#define STM32_SDMMC_CMD_CMDINDEX_MASK         (0x3f << STM32_SDMMC_CMD_CMDINDEX_SHIFT)
+#define STM32_SDMMC_CMD_WAITRESP_SHIFT        (6)       /* Bits 7-6: Wait for response bits */
+#define STM32_SDMMC_CMD_WAITRESP_MASK         (3 << STM32_SDMMC_CMD_WAITRESP_SHIFT)
+#  define STM32_SDMMC_CMD_NORESPONSE          (0 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 00/10: No response */
+#  define STM32_SDMMC_CMD_SHORTRESPONSE       (1 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 01: Short response */
+#  define STM32_SDMMC_CMD_LONGRESPONSE        (3 << STM32_SDMMC_CMD_WAITRESP_SHIFT) /* 11: Long response */
+#define STM32_SDMMC_CMD_WAITINT               (1 << 8)  /* Bit 8: CPSM waits for interrupt request */
+#define STM32_SDMMC_CMD_WAITPEND              (1 << 9)  /* Bit 9: CPSM Waits for ends of data transfer */
+#define STM32_SDMMC_CMD_CPSMEN                (1 << 10) /* Bit 10: Command path state machine enable */
+#define STM32_SDMMC_CMD_SUSPEND               (1 << 11) /* Bit 11: SD I/O suspend command */
+#define STM32_SDMMC_CMD_ENDCMD                (1 << 12) /* Bit 12: Enable CMD completion */
+#define STM32_SDMMC_CMD_NIEN                  (1 << 13) /* Bit 13: not Interrupt Enable */
+#define STM32_SDMMC_CMD_ATACMD                (1 << 14) /* Bit 14: CE-ATA command */
+
+#define STM32_SDMMC_CMD_RESET                 (0)       /* Reset value */
+
+#define STM32_SDMMC_RESPCMD_SHIFT             (0)
+#define STM32_SDMMC_RESPCMD_MASK              (0x3f << STM32_SDMMC_RESPCMD_SHIFT)
+
+#define STM32_SDMMC_DTIMER_RESET              (0)       /* Reset value */
+
+#define STM32_SDMMC_DLEN_SHIFT                (0)
+#define STM32_SDMMC_DLEN_MASK                 (0x01ffffff << STM32_SDMMC_DLEN_SHIFT)
+
+#define STM32_SDMMC_DLEN_RESET                (0)       /* Reset value */
+
+#define STM32_SDMMC_DCTRL_DTEN                (1 << 0)  /* Bit 0: Data transfer enabled bit */
+#define STM32_SDMMC_DCTRL_DTDIR               (1 << 1)  /* Bit 1: Data transfer direction */
+#define STM32_SDMMC_DCTRL_DTMODE              (1 << 2)  /* Bit 2: Data transfer mode */
+#define STM32_SDMMC_DCTRL_DMAEN               (1 << 3)  /* Bit 3: DMA enable bit */
+#define STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT    (4)       /* Bits 7-4: Data block size */
+#define STM32_SDMMC_DCTRL_DBLOCKSIZE_MASK     (15 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#  define STM32_SDMMC_DCTRL_1BYTE             (0 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#  define STM32_SDMMC_DCTRL_2BYTES            (1 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#  define STM32_SDMMC_DCTRL_4BYTES            (2 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#  define STM32_SDMMC_DCTRL_8BYTES            (3 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#  define STM32_SDMMC_DCTRL_16BYTES           (4 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#  define STM32_SDMMC_DCTRL_32BYTES           (5 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#  define STM32_SDMMC_DCTRL_64BYTES           (6 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#  define STM32_SDMMC_DCTRL_128BYTES          (7 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#  define STM32_SDMMC_DCTRL_256BYTES          (8 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#  define STM32_SDMMC_DCTRL_512BYTES          (9 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#  define STM32_SDMMC_DCTRL_1KBYTE            (10 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#  define STM32_SDMMC_DCTRL_2KBYTES           (11 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#  define STM32_SDMMC_DCTRL_4KBYTES           (12 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#  define STM32_SDMMC_DCTRL_8KBYTES           (13 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#  define STM32_SDMMC_DCTRL_16KBYTES          (14 << STM32_SDMMC_DCTRL_DBLOCKSIZE_SHIFT)
+#define STM32_SDMMC_DCTRL_RWSTART             (1 << 8)  /* Bit 8: Read wait start */
+#define STM32_SDMMC_DCTRL_RWSTOP              (1 << 9)  /* Bit 9: Read wait stop */
+#define STM32_SDMMC_DCTRL_RWMOD               (1 << 10) /* Bit 10: Read wait mode */
+#define STM32_SDMMC_DCTRL_SDIOEN              (1 << 11) /* Bit 11: SD I/O enable functions */
+
+#define STM32_SDMMC_DCTRL_RESET               (0)       /* Reset value */
+
+#define STM32_SDMMC_DCOUNT_SHIFT              (0)
+#define STM32_SDMMC_DCOUNT_MASK               (0x01ffffff << STM32_SDMMC_DCOUNT_SHIFT)
+
+#define STM32_SDMMC_STA_CCRCFAIL              (1 << 0)  /* Bit 0: Command response CRC fail */
+#define STM32_SDMMC_STA_DCRCFAIL              (1 << 1)  /* Bit 1: Data block CRC fail */
+#define STM32_SDMMC_STA_CTIMEOUT              (1 << 2)  /* Bit 2: Command response timeout */
+#define STM32_SDMMC_STA_DTIMEOUT              (1 << 3)  /* Bit 3: Data timeout */
+#define STM32_SDMMC_STA_TXUNDERR              (1 << 4)  /* Bit 4: Transmit FIFO underrun error */
+#define STM32_SDMMC_STA_RXOVERR               (1 << 5)  /* Bit 5: Received FIFO overrun error */
+#define STM32_SDMMC_STA_CMDREND               (1 << 6)  /* Bit 6: Command response received  */
+#define STM32_SDMMC_STA_CMDSENT               (1 << 7)  /* Bit 7: Command sent  */
+#define STM32_SDMMC_STA_DATAEND               (1 << 8)  /* Bit 8: Data end */
+#define STM32_SDMMC_STA_STBITERR              (1 << 9)  /* Bit 9: Start bit not detected  */
+#define STM32_SDMMC_STA_DBCKEND               (1 << 10) /* Bit 10: Data block sent/received  */
+#define STM32_SDMMC_STA_CMDACT                (1 << 11) /* Bit 11: Command transfer in progress */
+#define STM32_SDMMC_STA_TXACT                 (1 << 12) /* Bit 12: Data transmit in progress */
+#define STM32_SDMMC_STA_RXACT                 (1 << 13) /* Bit 13: Data receive in progress */
+#define STM32_SDMMC_STA_TXFIFOHE              (1 << 14) /* Bit 14: Transmit FIFO half empty */
+#define STM32_SDMMC_STA_RXFIFOHF              (1 << 15) /* Bit 15: Receive FIFO half full */
+#define STM32_SDMMC_STA_TXFIFOF               (1 << 16) /* Bit 16: Transmit FIFO full */
+#define STM32_SDMMC_STA_RXFIFOF               (1 << 17) /* Bit 17: Receive FIFO full */
+#define STM32_SDMMC_STA_TXFIFOE               (1 << 18) /* Bit 18: Transmit FIFO empty */
+#define STM32_SDMMC_STA_RXFIFOE               (1 << 19) /* Bit 19: Receive FIFO empty */
+#define STM32_SDMMC_STA_TXDAVL                (1 << 20) /* Bit 20: Data available in transmit FIFO */
+#define STM32_SDMMC_STA_RXDAVL                (1 << 21) /* Bit 21: Data available in receive FIFO */
+#define STM32_SDMMC_STA_SDIOIT                (1 << 22) /* Bit 22: SDIO interrupt received */
+#define STM32_SDMMC_STA_CEATAEND              (1 << 23) /* Bit 23: CMD6 CE-ATA command completion */
+
+#define STM32_SDMMC_ICR_CCRCFAILC             (1 << 0)  /* Bit 0: CCRCFAIL flag clear bit */
+#define STM32_SDMMC_ICR_DCRCFAILC             (1 << 1)  /* Bit 1: DCRCFAIL flag clear bit */
+#define STM32_SDMMC_ICR_CTIMEOUTC             (1 << 2)  /* Bit 2: CTIMEOUT flag clear bit */
+#define STM32_SDMMC_ICR_DTIMEOUTC             (1 << 3)  /* Bit 3: DTIMEOUT flag clear bit */
+#define STM32_SDMMC_ICR_TXUNDERRC             (1 << 4)  /* Bit 4: TXUNDERR flag clear bit */
+#define STM32_SDMMC_ICR_RXOVERRC              (1 << 5)  /* Bit 5: RXOVERR flag clear bit */
+#define STM32_SDMMC_ICR_CMDRENDC              (1 << 6)  /* Bit 6: CMDREND flag clear bit */
+#define STM32_SDMMC_ICR_CMDSENTC              (1 << 7)  /* Bit 7: CMDSENT flag clear bit */
+#define STM32_SDMMC_ICR_DATAENDC              (1 << 8)  /* Bit 8: DATAEND flag clear bit */
+#define STM32_SDMMC_ICR_STBITERRC             (1 << 9)  /* Bit 9: STBITERR flag clear bit */
+#define STM32_SDMMC_ICR_DBCKENDC              (1 << 10) /* Bit 10: DBCKEND flag clear bit */
+#define STM32_SDMMC_ICR_SDIOITC               (1 << 22) /* Bit 22: SDIOIT flag clear bit */
+#define STM32_SDMMC_ICR_CEATAENDC             (1 << 23) /* Bit 23: CEATAEND flag clear bit */
+
+#define STM32_SDMMC_ICR_RESET                 0x00c007ff
+#define STM32_SDMMC_ICR_STATICFLAGS           0x000005ff
+
+#define STM32_SDMMC_MASK_CCRCFAILIE           (1 << 0)  /* Bit 0: Command CRC fail interrupt enable */
+#define STM32_SDMMC_MASK_DCRCFAILIE           (1 << 1)  /* Bit 1: Data CRC fail interrupt enable */
+#define STM32_SDMMC_MASK_CTIMEOUTIE           (1 << 2)  /* Bit 2: Command timeout interrupt enable */
+#define STM32_SDMMC_MASK_DTIMEOUTIE           (1 << 3)  /* Bit 3: Data timeout interrupt enable */
+#define STM32_SDMMC_MASK_TXUNDERRIE           (1 << 4)  /* Bit 4: Tx FIFO underrun error interrupt enable */
+#define STM32_SDMMC_MASK_RXOVERRIE            (1 << 5)  /* Bit 5: Rx FIFO overrun error interrupt enable */
+#define STM32_SDMMC_MASK_CMDRENDIE            (1 << 6)  /* Bit 6: Command response received interrupt enable */
+#define STM32_SDMMC_MASK_CMDSENTIE            (1 << 7)  /* Bit 7: Command sent interrupt enable */
+#define STM32_SDMMC_MASK_DATAENDIE            (1 << 8)  /* Bit 8: Data end interrupt enable */
+#define STM32_SDMMC_MASK_STBITERRIE           (1 << 9)  /* Bit 9: Start bit error interrupt enable */
+#define STM32_SDMMC_MASK_DBCKENDIE            (1 << 10) /* Bit 10: Data block end interrupt enable */
+#define STM32_SDMMC_MASK_CMDACTIE             (1 << 11) /* Bit 11: Command acting interrupt enable */
+#define STM32_SDMMC_MASK_TXACTIE              (1 << 12) /* Bit 12: Data transmit acting interrupt enable */
+#define STM32_SDMMC_MASK_RXACTIE              (1 << 13) /* Bit 13: Data receive acting interrupt enable */
+#define STM32_SDMMC_MASK_TXFIFOHEIE           (1 << 14) /* Bit 14: Tx FIFO half empty interrupt enable */
+#define STM32_SDMMC_MASK_RXFIFOHFIE           (1 << 15) /* Bit 15: Rx FIFO half full interrupt enable */
+#define STM32_SDMMC_MASK_TXFIFOFIE            (1 << 16) /* Bit 16: Tx FIFO full interrupt enable */
+#define STM32_SDMMC_MASK_RXFIFOFIE            (1 << 17) /* Bit 17: Rx FIFO full interrupt enable */
+#define STM32_SDMMC_MASK_TXFIFOEIE            (1 << 18) /* Bit 18: Tx FIFO empty interrupt enable */
+#define STM32_SDMMC_MASK_RXFIFOEIE            (1 << 19) /* Bit 19: Rx FIFO empty interrupt enable */
+#define STM32_SDMMC_MASK_TXDAVLIE             (1 << 20) /* Bit 20: Data available in Tx FIFO interrupt enable */
+#define STM32_SDMMC_MASK_RXDAVLIE             (1 << 21) /* Bit 21: Data available in Rx FIFO interrupt enable */
+#define STM32_SDMMC_MASK_SDIOITIE             (1 << 22) /* Bit 22: SDIO mode interrupt received interrupt enable */
+#define STM32_SDMMC_MASK_CEATAENDIE           (1 << 23) /* Bit 23: CE-ATA command completion interrupt enable */
+
+#define STM32_SDMMC_MASK_RESET                (0)
+
+#define STM32_SDMMC_FIFOCNT_SHIFT             (0)
+#define STM32_SDMMC_FIFOCNT_MASK              (0x0ffffff << STM32_SDMMC_FIFOCNT_SHIFT)
+
+#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_SDMMC_H */

arch/arm/src/stm32f7/chip/stm32f72xx73xx_spi.h

+/************************************************************************************
+ * arch/arm/src/stm32f7/chip/stm32f72xx73xx_spi.h
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *            David Sidrane <david_s5@nscdg.com>
+ *            Bob Feretich <bob.feretich@rafresearch.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_SPI_H
+#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_SPI_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip.h"
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Maximum allowed speed as per data sheet for all SPIs (both pclk1 and pclk2)*/
+
+#  define STM32_SPI_CLK_MAX       50000000UL
+
+/* Register Offsets *****************************************************************/
+
+#define STM32_SPI_CR1_OFFSET      0x0000  /* SPI Control Register 1 (16-bit) */
+#define STM32_SPI_CR2_OFFSET      0x0004  /* SPI control register 2 (16-bit) */
+#define STM32_SPI_SR_OFFSET       0x0008  /* SPI status register (16-bit) */
+#define STM32_SPI_DR_OFFSET       0x000c  /* SPI data register (16-bit) */
+#define STM32_SPI_CRCPR_OFFSET    0x0010  /* SPI CRC polynomial register (16-bit) */
+#define STM32_SPI_RXCRCR_OFFSET   0x0014  /* SPI Rx CRC register (16-bit) */
+#define STM32_SPI_TXCRCR_OFFSET   0x0018  /* SPI Tx CRC register (16-bit) */
+#define STM32_SPI_I2SCFGR_OFFSET  0x001c  /* I2S configuration register */
+#define STM32_SPI_I2SPR_OFFSET    0x0020  /* I2S prescaler register */
+
+/* Register Addresses ***************************************************************/
+
+#if STM32F7_NSPI > 0
+#  define STM32_SPI1_CR1          (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET)
+#  define STM32_SPI1_CR2          (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET)
+#  define STM32_SPI1_SR           (STM32_SPI1_BASE+STM32_SPI_SR_OFFSET)
+#  define STM32_SPI1_DR           (STM32_SPI1_BASE+STM32_SPI_DR_OFFSET)
+#  define STM32_SPI1_CRCPR        (STM32_SPI1_BASE+STM32_SPI_CRCPR_OFFSET)
+#  define STM32_SPI1_RXCRCR       (STM32_SPI1_BASE+STM32_SPI_RXCRCR_OFFSET)
+#  define STM32_SPI1_TXCRCR       (STM32_SPI1_BASE+STM32_SPI_TXCRCR_OFFSET)
+#endif
+
+#if STM32F7_NSPI > 1
+#  define STM32_SPI2_CR1          (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET)
+#  define STM32_SPI2_CR2          (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET)
+#  define STM32_SPI2_SR           (STM32_SPI2_BASE+STM32_SPI_SR_OFFSET)
+#  define STM32_SPI2_DR           (STM32_SPI2_BASE+STM32_SPI_DR_OFFSET)
+#  define STM32_SPI2_CRCPR        (STM32_SPI2_BASE+STM32_SPI_CRCPR_OFFSET)
+#  define STM32_SPI2_RXCRCR       (STM32_SPI2_BASE+STM32_SPI_RXCRCR_OFFSET)
+#  define STM32_SPI2_TXCRCR       (STM32_SPI2_BASE+STM32_SPI_TXCRCR_OFFSET)
+#  define STM32_SPI2_I2SCFGR      (STM32_SPI2_BASE+STM32_SPI_I2SCFGR_OFFSET)
+#  define STM32_SPI2_I2SPR        (STM32_SPI2_BASE+STM32_SPI_I2SPR_OFFSET)
+#endif
+
+#if STM32F7_NSPI > 2
+#  define STM32_SPI3_CR1          (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET)
+#  define STM32_SPI3_CR2          (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET)
+#  define STM32_SPI3_SR           (STM32_SPI3_BASE+STM32_SPI_SR_OFFSET)
+#  define STM32_SPI3_DR           (STM32_SPI3_BASE+STM32_SPI_DR_OFFSET)
+#  define STM32_SPI3_CRCPR        (STM32_SPI3_BASE+STM32_SPI_CRCPR_OFFSET)
+#  define STM32_SPI3_RXCRCR       (STM32_SPI3_BASE+STM32_SPI_RXCRCR_OFFSET)
+#  define STM32_SPI3_TXCRCR       (STM32_SPI3_BASE+STM32_SPI_TXCRCR_OFFSET)
+#  define STM32_SPI3_I2SCFGR      (STM32_SPI3_BASE+STM32_SPI_I2SCFGR_OFFSET)
+#  define STM32_SPI3_I2SPR        (STM32_SPI3_BASE+STM32_SPI_I2SPR_OFFSET)
+#endif
+
+#if STM32F7_NSPI > 3
+#  define STM32_SPI4_CR1          (STM32_SPI4_BASE+STM32_SPI_CR1_OFFSET)
+#  define STM32_SPI4_CR2          (STM32_SPI4_BASE+STM32_SPI_CR2_OFFSET)
+#  define STM32_SPI4_SR           (STM32_SPI4_BASE+STM32_SPI_SR_OFFSET)
+#  define STM32_SPI4_DR           (STM32_SPI4_BASE+STM32_SPI_DR_OFFSET)
+#  define STM32_SPI4_CRCPR        (STM32_SPI4_BASE+STM32_SPI_CRCPR_OFFSET)
+#  define STM32_SPI4_RXCRCR       (STM32_SPI4_BASE+STM32_SPI_RXCRCR_OFFSET)
+#  define STM32_SPI4_TXCRCR       (STM32_SPI4_BASE+STM32_SPI_TXCRCR_OFFSET)
+#  define STM32_SPI4_I2SCFGR      (STM32_SPI4_BASE+STM32_SPI_I2SCFGR_OFFSET)
+#  define STM32_SPI4_I2SPR        (STM32_SPI4_BASE+STM32_SPI_I2SPR_OFFSET)
+#endif
+
+#if STM32F7_NSPI > 4
+#  define STM32_SPI5_CR1          (STM32_SPI5_BASE+STM32_SPI_CR1_OFFSET)
+#  define STM32_SPI5_CR2          (STM32_SPI5_BASE+STM32_SPI_CR2_OFFSET)
+#  define STM32_SPI5_SR           (STM32_SPI5_BASE+STM32_SPI_SR_OFFSET)
+#  define STM32_SPI5_DR           (STM32_SPI5_BASE+STM32_SPI_DR_OFFSET)
+#  define STM32_SPI5_CRCPR        (STM32_SPI5_BASE+STM32_SPI_CRCPR_OFFSET)
+#  define STM32_SPI5_RXCRCR       (STM32_SPI5_BASE+STM32_SPI_RXCRCR_OFFSET)
+#  define STM32_SPI5_TXCRCR       (STM32_SPI5_BASE+STM32_SPI_TXCRCR_OFFSET)
+#  define STM32_SPI5_I2SCFGR      (STM32_SPI5_BASE+STM32_SPI_I2SCFGR_OFFSET)
+#  define STM32_SPI5_I2SPR        (STM32_SPI5_BASE+STM32_SPI_I2SPR_OFFSET)
+#endif
+
+#if STM32F7_NSPI > 5
+#  define STM32_SPI6_CR1          (STM32_SPI6_BASE+STM32_SPI_CR1_OFFSET)
+#  define STM32_SPI6_CR2          (STM32_SPI6_BASE+STM32_SPI_CR2_OFFSET)
+#  define STM32_SPI6_SR           (STM32_SPI6_BASE+STM32_SPI_SR_OFFSET)
+#  define STM32_SPI6_DR           (STM32_SPI6_BASE+STM32_SPI_DR_OFFSET)
+#  define STM32_SPI6_CRCPR        (STM32_SPI6_BASE+STM32_SPI_CRCPR_OFFSET)
+#  define STM32_SPI6_RXCRCR       (STM32_SPI6_BASE+STM32_SPI_RXCRCR_OFFSET)
+#  define STM32_SPI6_TXCRCR       (STM32_SPI6_BASE+STM32_SPI_TXCRCR_OFFSET)
+#  define STM32_SPI6_I2SCFGR      (STM32_SPI6_BASE+STM32_SPI_I2SCFGR_OFFSET)
+#  define STM32_SPI6_I2SPR        (STM32_SPI6_BASE+STM32_SPI_I2SPR_OFFSET)
+#endif
+
+/* Register Bitfield Definitions ****************************************************/
+
+/* SPI Control Register 1 */
+
+#define SPI_CR1_CPHA              (1 << 0)  /* Bit 0: Clock Phase */
+#define SPI_CR1_CPOL              (1 << 1)  /* Bit 1: Clock Polarity */
+#define SPI_CR1_MSTR              (1 << 2)  /* Bit 2: Master Selection */
+#define SPI_CR1_BR_SHIFT          (3)       /* Bits 5:3 Baud Rate Control */
+#define SPI_CR1_BR_MASK           (7 << SPI_CR1_BR_SHIFT)
+#  define SPI_CR1_FPCLCKd2        (0 << SPI_CR1_BR_SHIFT) /* 000: fPCLK/2 */
+#  define SPI_CR1_FPCLCKd4        (1 << SPI_CR1_BR_SHIFT) /* 001: fPCLK/4 */
+#  define SPI_CR1_FPCLCKd8        (2 << SPI_CR1_BR_SHIFT) /* 010: fPCLK/8 */
+#  define SPI_CR1_FPCLCKd16       (3 << SPI_CR1_BR_SHIFT) /* 011: fPCLK/16 */
+#  define SPI_CR1_FPCLCKd32       (4 << SPI_CR1_BR_SHIFT) /* 100: fPCLK/32 */
+#  define SPI_CR1_FPCLCKd64       (5 << SPI_CR1_BR_SHIFT) /* 101: fPCLK/64 */
+#  define SPI_CR1_FPCLCKd128      (6 << SPI_CR1_BR_SHIFT) /* 110: fPCLK/128 */
+#  define SPI_CR1_FPCLCKd256      (7 << SPI_CR1_BR_SHIFT) /* 111: fPCLK/256 */
+#define SPI_CR1_SPE               (1 << 6)  /* Bit 6: SPI Enable */
+#define SPI_CR1_LSBFIRST          (1 << 7)  /* Bit 7: Frame Format */
+#define SPI_CR1_SSI               (1 << 8)  /* Bit 8: Internal slave select */
+#define SPI_CR1_SSM               (1 << 9)  /* Bit 9: Software slave management */
+#define SPI_CR1_RXONLY            (1 << 10) /* Bit 10: Receive only */
+#define SPI_CR1_CRCL              (1 << 11) /* Bit 11: CRC length */
+#define SPI_CR1_CRCNEXT           (1 << 12) /* Bit 12: Transmit CRC next */
+#define SPI_CR1_CRCEN             (1 << 13) /* Bit 13: Hardware CRC calculation enable */
+#define SPI_CR1_BIDIOE            (1 << 14) /* Bit 14: Output enable in bidirectional mode */
+#define SPI_CR1_BIDIMODE          (1 << 15) /* Bit 15: Bidirectional data mode enable */
+
+/* SPI Control Register 2 */
+
+#define SPI_CR2_RXDMAEN           (1 << 0)  /* Bit 0: Rx Buffer DMA Enable */
+#define SPI_CR2_TXDMAEN           (1 << 1)  /* Bit 1: Tx Buffer DMA Enable */
+#define SPI_CR2_SSOE              (1 << 2)  /* Bit 2: SS Output Enable */
+#define SPI_CR2_NSSP              (1 << 3)  /* Bit 3 NSSP: NSS pulse management */
+#define SPI_CR2_FRF               (1 << 4)  /* Bit 4: Frame format */
+#define SPI_CR2_ERRIE             (1 << 5)  /* Bit 5: Error interrupt enable */
+#define SPI_CR2_RXNEIE            (1 << 6)  /* Bit 6: RX buffer not empty interrupt enable */
+#define SPI_CR2_TXEIE             (1 << 7)  /* Bit 7: Tx buffer empty interrupt enable */
+#define SPI_CR2_DS_SHIFT          (8)       /* Bits 8-11:  Data size */
+#define SPI_CR2_DS_MASK           (0xf << SPI_CR2_DS_SHIFT)
+#  define SPI_CR2_DS_VAL(bits)    (((bits)-1) << SPI_CR2_DS_SHIFT)
+#  define SPI_CR2_DS_4BIT         SPI_CR2_DS_VAL(4)
+#  define SPI_CR2_DS_5BIT         SPI_CR2_DS_VAL(5)
+#  define SPI_CR2_DS_6BIT         SPI_CR2_DS_VAL(6)
+#  define SPI_CR2_DS_7BIT         SPI_CR2_DS_VAL(7)
+#  define SPI_CR2_DS_8BIT         SPI_CR2_DS_VAL(8)
+#  define SPI_CR2_DS_9BIT         SPI_CR2_DS_VAL(9)
+#  define SPI_CR2_DS_10BIT        SPI_CR2_DS_VAL(10)
+#  define SPI_CR2_DS_11BIT        SPI_CR2_DS_VAL(11)
+#  define SPI_CR2_DS_12BIT        SPI_CR2_DS_VAL(12)
+#  define SPI_CR2_DS_13BIT        SPI_CR2_DS_VAL(13)
+#  define SPI_CR2_DS_14BIT        SPI_CR2_DS_VAL(14)
+#  define SPI_CR2_DS_15BIT        SPI_CR2_DS_VAL(15)
+#  define SPI_CR2_DS_16BIT        SPI_CR2_DS_VAL(16)
+#define SPI_CR2_FRXTH             (1 << 12) /* Bit 12: FIFO reception threshold */
+#define SPI_CR2_LDMARX            (1 << 13) /* Bit 13: Last DMA transfer for receptione */
+#define SPI_CR2_LDMATX            (1 << 14) /* Bit 14: Last DMA transfer for transmission */
+
+/* SPI status register */
+
+#define SPI_SR_RXNE               (1 << 0)  /* Bit 0: Receive buffer not empty */
+#define SPI_SR_TXE                (1 << 1)  /* Bit 1: Transmit buffer empty */
+#define SPI_SR_CHSIDE             (1 << 2)  /* Bit 2: Channel side (i2s) */
+#define SPI_SR_UDR                (1 << 3)  /* Bit 3: Underrun flag (i2s) */
+#define SPI_SR_CRCERR             (1 << 4)  /* Bit 4: CRC error flag */
+#define SPI_SR_MODF               (1 << 5)  /* Bit 5: Mode fault */
+#define SPI_SR_OVR                (1 << 6)  /* Bit 6: Overrun flag */
+#define SPI_SR_BSY                (1 << 7)  /* Bit 7: Busy flag */
+#define SPI_SR_FRE                (1 << 8)  /* Bit 8: Frame format error */
+#define SPI_SR_FRLVL_SHIFT        (9)       /* Bits 9-10: FIFO reception level */
+#define SPI_SR_FRLVL_MASK         (3 << SPI_SR_FRLVL_SHIFT)
+#  define SPI_SR_FRLVL_EMPTY      (0 << SPI_SR_FRLVL_SHIFT) /* FIFO empty */
+#  define SPI_SR_FRLVL_QUARTER    (1 << SPI_SR_FRLVL_SHIFT) /* 1/4 FIFO */
+#  define SPI_SR_FRLVL_HALF       (2 << SPI_SR_FRLVL_SHIFT) /* 1/2 FIFO */
+#  define SPI_SR_FRLVL_FULL       (3 << SPI_SR_FRLVL_SHIFT) /* FIFO full */
+#define SPI_SR_FTLVL_SHIFT        (11)      /* Bits 11-12: FIFO transmission level */
+#define SPI_SR_FTLVL_MASK         (3 << SPI_SR_FTLVL_SHIFT)
+#  define SPI_SR_FTLVL_EMPTY      (0 << SPI_SR_FTLVL_SHIFT) /* FIFO empty */
+#  define SPI_SR_FTLVL_QUARTER    (1 << SPI_SR_FTLVL_SHIFT) /* 1/4 FIFO */
+#  define SPI_SR_FTLVL_HALF       (2 << SPI_SR_FTLVL_SHIFT) /* 1/2 FIFO */
+#  define SPI_SR_FTLVL_FULL       (3 << SPI_SR_FTLVL_SHIFT) /* FIFO full */
+
+/* I2S configuration register */
+
+#define SPI_I2SCFGR_CHLEN          (1 << 0)  /* Bit 0: Channel length (number of bits per audio channel) */
+#define SPI_I2SCFGR_DATLEN_SHIFT   (1)       /* Bit 1-2: Data length to be transferred */
+#define SPI_I2SCFGR_DATLEN_MASK    (3 << SPI_I2SCFGR_DATLEN_SHIFT)
+#  define SPI_I2SCFGR_DATLEN_16BIT (0 << SPI_I2SCFGR_DATLEN_SHIFT) /* 00: 16-bit data length */
+#  define SPI_I2SCFGR_DATLEN_8BIT  (1 << SPI_I2SCFGR_DATLEN_SHIFT) /* 01: 24-bit data length */
+#  define SPI_I2SCFGR_DATLEN_32BIT (2 << SPI_I2SCFGR_DATLEN_SHIFT) /* 10: 32-bit data length */
+#define SPI_I2SCFGR_CKPOL          (1 << 3)  /* Bit 3: Steady state clock polarity */
+#define SPI_I2SCFGR_I2SSTD_SHIFT   (4)       /* Bit 4-5: I2S standard selection */
+#define SPI_I2SCFGR_I2SSTD_MASK    (3 << SPI_I2SCFGR_I2SSTD_SHIFT)
+#  define SPI_I2SCFGR_I2SSTD_PHILLIPS (0 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 00: I2S Phillips standard. */
+#  define SPI_I2SCFGR_I2SSTD_MSB      (1 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 01: MSB justified standard (left justified) */
+#  define SPI_I2SCFGR_I2SSTD_LSB      (2 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 10: LSB justified standard (right justified) */
+#  define SPI_I2SCFGR_I2SSTD_PCM      (3 << SPI_I2SCFGR_I2SSTD_SHIFT) /* 11: PCM standard */
+#define SPI_I2SCFGR_PCMSYNC        (1 << 7)  /* Bit 7: PCM frame synchronization */
+#define SPI_I2SCFGR_I2SCFG_SHIFT   (8)       /* Bit 8-9: I2S configuration mode */
+#define SPI_I2SCFGR_I2SCFG_MASK    (3 << SPI_I2SCFGR_I2SCFG_SHIFT)
+#  define SPI_I2SCFGR_I2SCFG_STX   (0 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 00: Slave - transmit */
+#  define SPI_I2SCFGR_I2SCFG_SRX   (1 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 01: Slave - receive */
+#  define SPI_I2SCFGR_I2SCFG_MTX   (2 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 10: Master - transmit */
+#  define SPI_I2SCFGR_I2SCFG_MRX   (3 << SPI_I2SCFGR_I2SCFG_SHIFT) /* 11: Master - receive */
+#define SPI_I2SCFGR_I2SE           (1 << 10) /* Bit 10: I2S Enable */
+#define SPI_I2SCFGR_I2SMOD         (1 << 11) /* Bit 11: I2S mode selection */
+#define SPI_I2SCFGR_ASTRTEN        (1 << 12) /* Bit 12: Asynchronous start enable */
+
+/* I2S prescaler register */
+
+#define SPI_I2SPR_I2SDIV_SHIFT    (0)       /* Bit 0-7: I2S Linear prescaler */
+#define SPI_I2SPR_I2SDIV_MASK     (0xff << SPI_I2SPR_I2SDIV_SHIFT)
+#define SPI_I2SPR_ODD             (1 << 8)  /* Bit 8: Odd factor for the prescaler */
+#define SPI_I2SPR_MCKOE           (1 << 9)  /* Bit 9: Master clock output enable */
+
+#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F72XX73XX_SPI_H */