Fixes for clean compile/link

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2102 42af7a65-404d-4744-a932-0658087f49c3

arch/arm/src/stm32/stm32_internal.h

@@ -133,14 +133,14 @@ extern "C" {
  ****************************************************************************/
 
 /****************************************************************************
- * Name: up_lowsetup
+ * Name: stm32_lowsetup
  *
  * Description:
  *   Called at the very beginning of _start.  Performs low level initialization.
  *
  ****************************************************************************/
 
-EXTERN void up_lowsetup(void);
+EXTERN void stm32_lowsetup(void);
 
 /****************************************************************************
  * Name: stm32_clockconfig
@@ -152,17 +152,6 @@ EXTERN void up_lowsetup(void);
 
 EXTERN void stm32_clockconfig(void);
 
-/****************************************************************************
- * Name: up_clockconfig
- *
- * Description:
- *   Called early in the bootsequence (before .data and .bss are available)
- *   in order to configure initial clocking.
- *
- ****************************************************************************/
-
-EXTERN void up_clockconfig(void);
-
 /****************************************************************************
  * Name: stm32_configgpio
  *

arch/arm/src/stm32/stm32_lowputc.c

@@ -40,6 +40,8 @@
 #include <nuttx/config.h>
 #include <sys/types.h>
 
+#include <arch/board/board.h>
+
 #include "up_internal.h"
 #include "up_arch.h"
 
@@ -206,7 +208,7 @@ void up_lowputc(char ch)
 }
 
 /**************************************************************************
- * Name: up_lowsetup
+ * Name: stm32_lowsetup
  *
  * Description:
  *   This performs basic initialization of the USART used for the serial
@@ -215,7 +217,7 @@ void up_lowputc(char ch)
  *
  **************************************************************************/
 
-void up_lowsetup(void)
+void stm32_lowsetup(void)
 {
 #if !defined(CONFIG_USART1_DISABLE) || !defined(CONFIG_USART2_DISABLE) || !defined(CONFIG_USART3_DISABLE)
   uint32 enr;

arch/arm/src/stm32/stm32_serial.c

@@ -438,7 +438,7 @@ static int up_setup(struct uart_dev_s *dev)
   uint16 regval;
 
   /* Note: The logic here depends on the fact that that the USART module
-   * was enabled and the pins were configured in up_lowsetup().
+   * was enabled and the pins were configured in stm32_lowsetup().
    */
 
   /* Configure CR2 */
@@ -961,7 +961,7 @@ static boolean up_txready(struct uart_dev_s *dev)
 void up_earlyserialinit(void)
 {
   /* NOTE:  All GPIO configuration for the USARTs was performed in
-   * up_lowsetup
+   * stm32_lowsetup
    */
 
   /* Disable all USARTS */

arch/arm/src/stm32/stm32_start.c

@@ -101,8 +101,8 @@ void __start(void)
 
   /* Configure the uart so that we can get debug output as soon as possible */
 
-  up_clockconfig();
-  up_lowsetup();
+  stm32_clockconfig();
+  stm32_lowsetup();
   showprogress('A');
 
   /* Clear .bss.  We'll do this inline (vs. calling memset) just to be

configs/stm3210e-eval/README.txt

@@ -193,6 +193,37 @@ STM3210E-EVAL-specific Configuration Options
 	   the 100 second delay then adjust CONFIG_ARCH_LOOPSPERMSEC until
 	   the delay actually is 100 seconds.
 
+  Individual subsystems can be enabled:
+
+	CONFIG_STM32_TIM2
+	CONFIG_STM32_TIM3
+	CONFIG_STM32_TIM4
+	CONFIG_STM32_TIM5
+	CONFIG_STM32_TIM6
+	CONFIG_STM32_TIM7
+	CONFIG_STM32_WWDG
+	CONFIG_STM32_SPI2
+	CONFIG_STM32_SPI4
+	CONFIG_STM32_USART2
+	CONFIG_STM32_USART3
+	CONFIG_STM32_UART4
+	CONFIG_STM32_UART5
+	CONFIG_STM32_I2C1
+	CONFIG_STM32_I2C2
+	CONFIG_STM32_USB
+	CONFIG_STM32_CAN
+	CONFIG_STM32_BKP
+	CONFIG_STM32_PWR
+	CONFIG_STM32_DAC
+	CONFIG_STM32_USB
+	CONFIG_STM32_ADC1
+	CONFIG_STM32_ADC2
+	CONFIG_STM32_TIM1
+	CONFIG_STM32_SPI1
+	CONFIG_STM32_TIM8
+	CONFIG_STM32_USART1
+	CONFIG_STM32_ADC3
+
   STM32F103Z specific device driver settings
 
 	CONFIG_U[S]ARTn_SERIAL_CONSOLE - selects the USARTn (n=1,2,3) or UART

configs/stm3210e-eval/include/board.h

@@ -78,7 +78,7 @@
 /* APB2 clock (PCLK2) is HCLK (72MHz) */
 
 #define STM32_RCC_CFGR_PPRE2   RCC_CFGR_PPRE2_HCLK
-#define STM32_PCLK_FREQUENCY   STM32_HCLK_FREQUENCY
+#define STM32_PCLK2_FREQUENCY  STM32_HCLK_FREQUENCY
 
 /* APB1 clock (PCLK1) is HCLK/2 (36MHz) */
 

configs/stm3210e-eval/ostest/defconfig

@@ -93,6 +93,36 @@ CONFIG_STM32_DEVKITARM=n
 CONFIG_STM32_RAISONANCE=n
 CONFIG_STM32_BUILDROOT=y
 
+#
+#  Individual subsystems can be enabled:
+CONFIG_STM32_TIM2=n
+CONFIG_STM32_TIM3=n
+CONFIG_STM32_TIM4=n
+CONFIG_STM32_TIM5=n
+CONFIG_STM32_TIM6=n
+CONFIG_STM32_TIM7=n
+CONFIG_STM32_WWDG=n
+CONFIG_STM32_SPI2=n
+CONFIG_STM32_SPI4=n
+CONFIG_STM32_USART2=y
+CONFIG_STM32_USART3=n
+CONFIG_STM32_UART4=n
+CONFIG_STM32_UART5=n
+CONFIG_STM32_I2C1=n
+CONFIG_STM32_I2C2=n
+CONFIG_STM32_USB=y
+CONFIG_STM32_CAN=n
+CONFIG_STM32_BKP=n
+CONFIG_STM32_PWR=n
+CONFIG_STM32_DAC=n
+CONFIG_STM32_ADC1=n
+CONFIG_STM32_ADC2=n
+CONFIG_STM32_TIM1=n
+CONFIG_STM32_SPI1=n
+CONFIG_STM32_TIM8=n
+CONFIG_STM32_USART1=y
+CONFIG_STM32_ADC3=n
+
 #
 # STM32F103Z specific serial device driver settings
 #