Add stm32 header files

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@2074 42af7a65-404d-4744-a932-0658087f49c3

arch/arm/src/stm32/Make.defs

+############################################################################
+# arch/arm/src/stm32/Make.defs
+#
+#   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+HEAD_ASRC	= stm32_vectors.S
+
+CMN_ASRCS	= up_context.S
+CMN_CSRCS	= up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
+		  up_createstack.c up_mdelay.c up_udelay.c up_exit.c \
+		  up_idle.c up_initialize.c up_initialstate.c up_interruptcontext.c \
+		  up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c \
+		  up_releasepending.c up_releasestack.c up_reprioritizertr.c \
+		  up_schedulesigaction.c up_sigdeliver.c up_unblocktask.c \
+		  up_usestack.c up_doirq.c up_hardfault.c up_svcall.c
+
+CHIP_ASRCS	= 
+CHIP_CSRCS	= stm32_start.c stm32_syscontrol.c stm32_irq.c \
+		  stm32_gpio.c stm32_gpioirq.c stm32_timerisr.c stm32_lowputc.c \
+		  stm32_serial.c stm32_ssi.c stm32_dumpgpio.c
+
+ifdef CONFIG_NET
+CHIP_CSRCS	+= stm32_ethernet.c
+endif

arch/arm/src/stm32/chip.h

+/************************************************************************************
+ * arch/arm/src/stm32/chip.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_CHIP_H
+#define __ARCH_ARM_SRC_STM32_CHIP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Get customizations for each supported chip (only the STM32F103Z right now) */
+
+#ifdef CONFIG_CHIP_STM32F103Z
+#  define STM32_NTIM     4 /* TIM1-TIM4 */
+#  define STM32_NSPI     2 /* SPI1-2 */
+#  define STM32_NUSART   3 /* USART1-3 */
+#  define STM32_NI2C     2 /* I2C1-2 */
+#  define STM32_NCAN     1 /* bxCAN1 */
+#  define STM32_NGPIO    5 /* GPIOA-E */
+#  define STM32_NADC     2 /* ADC 1-2 */
+#  define STM32_NDAC     0 /* No DAC */
+#  define STM32_NCRC     0 /* No CRC */
+#  define STM32_NTHERNET 0 /* No ethernet */
+#else
+#  error "Unsupported STM32 chip */
+#endif
+
+/* Then get all of the register definitions */
+
+#include "stm32_memorymap.h"
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32_CHIP_H */

arch/arm/src/stm32/stm32_memorymap.h

+/************************************************************************************
+ * arch/arm/src/stm32/stm32_memorymap.h
+ *
+ *   Copyright (C) 2009 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_STM32_MEMORYMAP_H
+#define __ARCH_ARM_SRC_STM32_STM32_MEMORYMAP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include "chip.h"
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* FLASH and SRAM *******************************************************************/
+
+#define STM32_FLASH_BASE    0x08000000     /* 0x08000000 - Up to 512Kb */
+#define STM32_SRAM_BASE     0x20000000     /* 0x20000000 - 64Kb SRAM */
+
+/* Register Base Address ************************************************************/
+
+/* APB1 bus */
+
+#define STM32_TIM2_BASE      0x40000000     /* 0x40000000 - 0x400003ff: TIM2 timer */
+#define STM32_TIM3_BASE      0x40000400     /* 0x40000400 - 0x400007ff: TIM3 timer */
+#define STM32_TIM4_BASE      0x40000800     /* 0x40000800 - 0x40000bff: TIM4 timer */
+#define STM32_TIM5_BASE      0x40000c00     /* 0x40000c00 - 0x40000fff: TIM5 timer */
+#define STM32_TIM6_BASE      0x40001000     /* 0x40001000 - 0x400013ff: TIM6 timer */
+#define STM32_TIM7_BASE      0x40001400     /* 0x40001400 - 0x400007ff: TIM7 timer */
+                                            /* 0x40001800 - 0x40000fff: Reserved */
+#define STM32_RTC_BASE       0x40002800     /* 0x40002800 - 0x40002bff: RTC */
+#define STM32_WWDG_BASE      0x40002C00     /* 0x40002C00 - 0x40002fff: Window watchdog (WWDG) */
+#define STM32_IWDG_BASE      0x40003000     /* 0x40003000 - 0x400033ff: Independent watchdog (IWDG) */
+                                            /* 0x40003400 - 0x400037ff: Reserved */
+#define STM32_SPI1_BASE      0x40003800     /* 0x40003800 - 0x40003bff: SPI1/I21 */
+#define STM32_I2S1_BASE      0x40003800
+#define STM32_SPI2_BASE      0x40003c00     /* 0x40003c00 - 0x40003fff: SPI2/I2S */
+#define STM32_I2S2_BASE      0x40003c00
+                                            /* 0x40004000 - 0x400043ff: Reserved */
+#define STM32_USART2_BASE    0x40004400     /* 0x40004400 - 0x400047ff: USART2 */
+#define STM32_USART3_BASE    0x40004800     /* 0x40004800 - 0x40004bff: USART3 */
+#define STM32_UART4_BASE     0x40004c00     /* 0x40004c00 - 0x40004fff: UART4 */
+#define STM32_UART5_BASE     0x40005000     /* 0x40005000 - 0x400053ff: UART5 */
+#define STM32_I2C1_BASE      0x40005400     /* 0x40005400 - 0x400057ff: I2C1 */
+#define STM32_I2C2_BASE      0x40005800     /* 0x40005800 - 0x40005Bff: I2C2 */
+#define STM32_USB_BASE       0x40005c00     /* 0x40005c00 - 0x40005fff: USB device FS registers */
+#define STM32_USBCANRAM_BASE 0x40006000     /* 0x40006000 - 0x400063ff: Shared USB/CAN SRAM 512 bytes */
+#define STM32_bxCAN1_BASE    0x40006400     /* 0x40006400 - 0x400067ff: bxCAN1 */
+#define STM32_bxCAN2_BASE    0x40006800     /* 0x40006800 - 0x40006bff: bxCAN2 */
+#define STM32_BKP_BASE       0x40006c00     /* 0x40006c00 - 0x40006fff: Backup registers (BKP) */
+#define STM32_PWR_BASE       0x40007000     /* 0x40007000 - 0x400073ff: Power control PWR */
+#define STM32_DAC_BASE       0x40007400     /* 0x40007400 - 0x400077ff: DAC */
+                                            /* 0x40007800 - 0x4000ffff: Reserved */
+
+/* APB2 bus */
+
+#define STM32_AFIO_BASE      0x40010000     /* 0x40010000 - 0x400103ff: AFIO */
+#define STM32_EXTI_BASE      0x40010400     /* 0x40010400 - 0x400107ff: EXTI */
+#define STM32_GPIOA_BASE     0x40010800     /* 0x40010800 - 0x40010bff: GPIO Port A */
+#define STM32_GPIOB_BASE     0X40010c00     /* 0X40010c00 - 0x40010fff: GPIO Port B */
+#define STM32_GPIOC_BASE     0x40011000     /* 0x40011000 - 0x400113ff: GPIO Port C */
+#define STM32_GPIOD_BASE     0x40011400     /* 0x40011400 - 0x400117ff: GPIO Port D */
+#define STM32_GPIOE_BASE     0x40011800     /* 0x40011800 - 0x40011bff: GPIO Port E */
+#define STM32_GPIOF_BASE     0x4001c000     /* 0x4001c000 - 0x400111ff: GPIO Port F */
+#define STM32_GPIOG_BASE     0x40012000     /* 0x40012000 - 0x400123ff: GPIO Port G */
+#define STM32_ADC1_BASE      0x40012400     /* 0x40012400 - 0x400127ff: ADC1 */
+#define STM32_ADC2_BASE      0x40012800     /* 0x40012800 - 0x40012bff: ADC2 */
+#define STM32_TIM1_BASE      0x40012c00     /* 0x40012c00 - 0x40012fff: TIM1 timer */
+#define STM32_SPI1_BASE      0x40013000     /* 0x40013000 - 0x400133ff: SPI1 */
+#define STM32_TIM8_BASE      0x40012c00     /* 0x40013400 - 0x400137ff: TIM8 timer */
+#define STM32_USART1_BASE    0x40013800     /* 0x40013800 - 0x40013bff: USART1 */
+#define STM32_ADC3_BASE      0x40012800     /* 0x40012800 - 0x40013fff: ADC3 */
+                                            /* 0x40014000 - 0x40017fff: Reserved */
+
+/* AHB bus */
+
+#define STM32_SDIO_BASE     0x40020000     /* 0x40018000 - 0x400183ff: SDIO  */
+                                           /* 0x40018400 - 0x40017fff: Reserved */
+#define STM32_DMA1_BASE     0x40020000     /* 0x40020000 - 0x400203ff: DMA1  */
+#define STM32_DMA2_BASE     0x40020400     /* 0x40020000 - 0x400207ff: DMA2  */
+                                           /* 0x40020800 - 0x40020fff: Reserved */
+#define STM32_RCC_BASE      0x40021000     /* 0x40021000 - 0x400213ff: Reset and Clock control RCC */
+                                           /* 0x40021400 - 0x40021fff:  Reserved */
+#define STM32_OTGFS_BASE    0x50000000     /* 0x50000000 - 0x500003ff: USB OTG FS */
+#define STM32_FLASH_BASE    0x40022000     /* 0x40022000 - 0x400223ff: Flash memory interface */
+#define STM32_CRC_BASE      0x40028000     /* 0x40023000 - 0x400233ff: RC */
+                                           /* 0x40023400 - 0x40027fff: Reserved */
+#define STM32_ETHERNET_BASE 0x40028000     /* 0x40028000 - 0x40029fff: Ethernet */
+                                           /* 0x40030000 - 0x4fffffff: Reserved */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32_STM32_MEMORYMAP_H */

configs/stm3210e-eval/README.txt

@@ -35,6 +35,9 @@ GNU Toolchain Options
     CONFIG_STM32_RAISONANCE=y
     CONFIG_STM32_BUILDROOT=y	(default)
 
+  If you are not using CONFIG_STM32_BUILDROOT, then you may also have to modify
+  the PATH in the setenv.h file if your make cannot find the tools.
+
   NOTE: the CodeSourcery, devkitARM, and Raisonance toolchains are Windows native
   toolchains.  The NuttX buildroot toolchain is a Cygwin or Linux native toolchain.
   There are several limitations to using a Windows based toolchain in a Cygwin

configs/stm3210e-eval/ostest/Make.defs

@@ -35,33 +35,15 @@
 
 include ${TOPDIR}/.config
 
-# The default value for CROSSDEV can be overridden from the make command line:
-#   make                         -- Will build for the devkitARM toolchain
-#   make CROSSDEV=arm-eabi-      -- Will build for the devkitARM toolchain
-#   make CROSSDEV=arm-none-eabi- -- Will build for the CodeSourcery toolchain
-#   make CROSSDEV=arm-elf-       -- Will build for the NuttX buildroot toolchain
+# Setup for the selected toolchain
 
-CROSSDEV		= arm-eabi-
-CC			= $(CROSSDEV)gcc
-CXX			= $(CROSSDEV)g++
-CPP			= $(CROSSDEV)gcc -E
-LD			= $(CROSSDEV)ld
-AR			= $(CROSSDEV)ar rcs
-NM			= $(CROSSDEV)nm
-OBJCOPY			= $(CROSSDEV)objcopy
-OBJDUMP			= $(CROSSDEV)objdump
-
-ARCHCCVERSION		= ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
-ARCHCCMAJOR		= ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
-
-ifeq ($(CROSSDEV),arm-elf-)
-  MKDEP			= $(TOPDIR)/tools/mkdeps.sh
-  ARCHCPUFLAGS		= -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft
-  ARCHINCLUDES		= -I. -isystem $(TOPDIR)/include
-  ARCHXXINCLUDES	= -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
-  ARCHSCRIPT		= -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/ostest/ld.script
-  MAXOPTIMIZATION	= -Os
+ifneq ($(CONFIG_STM32_BUILDROOT),y)
+  # Windows-native toolchains
+ifeq ($(CONFIG_STM32_DEVKITARM),y)
+  CROSSDEV		= arm-eabi-
 else
+  CROSSDEV		= arm-none-eabi-
+endif
   WINTOOL		= y
   DIRLINK 		= $(TOPDIR)/tools/winlink.sh
   DIRUNLINK		= $(TOPDIR)/tools/unlink.sh
@@ -71,8 +53,30 @@ else
   ARCHXXINCLUDES	= -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
   ARCHSCRIPT		= -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/ostest/ld.script}"
   MAXOPTIMIZATION	= -O2
+# The NuttX buildroot toolchain
+else
+  # Linux/Cygwin-native toolchain (assumed from the NuttX buildroot)
+  CROSSDEV			= arm-elf-
+  MKDEP			= $(TOPDIR)/tools/mkdeps.sh
+  ARCHCPUFLAGS		= -mtune=cortex-m3 -march=armv7-m -mfloat-abi=soft
+  ARCHINCLUDES		= -I. -isystem $(TOPDIR)/include
+  ARCHXXINCLUDES	= -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
+  ARCHSCRIPT		= -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/ostest/ld.script
+  MAXOPTIMIZATION	= -Os
 endif
 
+CC			= $(CROSSDEV)gcc
+CXX			= $(CROSSDEV)g++
+CPP			= $(CROSSDEV)gcc -E
+LD			= $(CROSSDEV)ld
+AR			= $(CROSSDEV)ar rcs
+NM			= $(CROSSDEV)nm
+OBJCOPY			= $(CROSSDEV)objcopy
+OBJDUMP			= $(CROSSDEV)objdump
+
+ARCHCCVERSION		= ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
+ARCHCCMAJOR		= ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
+
 ifeq ("${CONFIG_DEBUG_SYMBOLS}","y")
   ARCHOPTIMIZATION	= -g
 else