Kconfig changes to get a clean STM32 ADC example build

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5246 42af7a65-404d-4744-a932-0658087f49c3

Kconfig

@@ -244,17 +244,24 @@ config DEBUG_ENABLE
 
 comment "Subsystem Debug Options"
 
+config DEBUG_MM
+	bool "Enable Memory Manager Debug Output"
+	default n
+	---help---
+		Enable memory management debug output (disabled by default)
+
 config DEBUG_SCHED
 	bool "Enable Scheduler Debug Output"
 	default n
 	---help---
 		Enable OS debug output (disabled by default)
 
-config DEBUG_MM
-	bool "Enable Memory Manager Debug Output"
+config DEBUG_PAGING
+	bool "Enable Demand Paging Debug Output"
 	default n
+	depends on PAGING
 	---help---
-		Enable memory management debug output (disabled by default)
+		Enable demand paging debug output (disabled by default)
 
 config DEBUG_NET
 	bool "Enable Network Debug Output"
@@ -311,6 +318,13 @@ config DEBUG_INPUT
 		Enable low level debug output from the input device drivers such as
  		mice and touchscreens (disabled by default)
 
+config DEBUG_ANALOG
+	bool "Enable Analog Device Debug Output"
+	default n
+	---help---
+		Enable low level debug output from the analog device drivers such as
+ 		A/D and D/A converters (disabled by default)
+
 config DEBUG_I2C
 	bool "Enable I2C Debug Output"
 	default n
@@ -325,12 +339,18 @@ config DEBUG_SPI
 	---help---
 		Enable I2C driver debug output (disabled by default)
 
+config DEBUG_DMA
+	bool "Enable DMA Debug Output"
+	default n
+	---help---
+		Enable DMA-releated debug output (disabled by default)
+
 config DEBUG_WATCHDOG
 	bool "Enable Watchdog Timer Debug Output"
 	default n
 	depends on WATCHDOG
 	---help---
-		Enable  watchdog timer debug output (disabled by default)
+		Enable watchdog timer debug output (disabled by default)
 
 endif
 

arch/arm/src/stm32/Kconfig

@@ -909,16 +909,22 @@ choice
 
 config STM32_TIM1_ADC1
 	bool "TIM1 ADC channel 1"
+	depends on STM32_ADC1
+	select HAVE_ADC1_TIMER
 	---help---
 		Reserve TIM1 to trigger ADC1
 
 config STM32_TIM1_ADC2
 	bool "TIM1 ADC channel 2"
+	depends on STM32_ADC2
+	select HAVE_ADC2_TIMER
 	---help---
 		Reserve TIM1 to trigger ADC2
 
 config STM32_TIM1_ADC3
 	bool "TIM1 ADC channel 3"
+	depends on STM32_ADC3
+	select HAVE_ADC3_TIMER
 	---help---
 		Reserve TIM1 to trigger ADC3
 
@@ -945,16 +951,22 @@ choice
 
 config STM32_TIM2_ADC1
 	bool "TIM2 ADC channel 1"
+	depends on STM32_ADC1
+	select HAVE_ADC1_TIMER
 	---help---
 		Reserve TIM2 to trigger ADC1
 
 config STM32_TIM2_ADC2
 	bool "TIM2 ADC channel 2"
+	depends on STM32_ADC2
+	select HAVE_ADC2_TIMER
 	---help---
 		Reserve TIM2 to trigger ADC2
 
 config STM32_TIM2_ADC3
 	bool "TIM2 ADC channel 3"
+	depends on STM32_ADC3
+	select HAVE_ADC3_TIMER
 	---help---
 		Reserve TIM2 to trigger ADC3
 
@@ -981,16 +993,22 @@ choice
 
 config STM32_TIM3_ADC1
 	bool "TIM3 ADC channel 1"
+	depends on STM32_ADC1
+	select HAVE_ADC1_TIMER
 	---help---
 		Reserve TIM3 to trigger ADC1
 
 config STM32_TIM3_ADC2
 	bool "TIM3 ADC channel 2"
+	depends on STM32_ADC2
+	select HAVE_ADC2_TIMER
 	---help---
 		Reserve TIM3 to trigger ADC2
 
 config STM32_TIM3_ADC3
 	bool "TIM3 ADC channel 3"
+	depends on STM32_ADC3
+	select HAVE_ADC3_TIMER
 	---help---
 		Reserve TIM3 to trigger ADC3
 
@@ -1017,16 +1035,22 @@ choice
 
 config STM32_TIM4_ADC1
 	bool "TIM4 ADC channel 1"
+	depends on STM32_ADC1
+	select HAVE_ADC1_TIMER
 	---help---
 		Reserve TIM4 to trigger ADC1
 
 config STM32_TIM4_ADC2
 	bool "TIM4 ADC channel 2"
+	depends on STM32_ADC2
+	select HAVE_ADC2_TIMER
 	---help---
 		Reserve TIM4 to trigger ADC2
 
 config STM32_TIM4_ADC3
 	bool "TIM4 ADC channel 3"
+	depends on STM32_ADC3
+	select HAVE_ADC3_TIMER
 	---help---
 		Reserve TIM4 to trigger ADC3
 
@@ -1053,16 +1077,22 @@ choice
 
 config STM32_TIM5_ADC1
 	bool "TIM5 ADC channel 1"
+	depends on STM32_ADC1
+	select HAVE_ADC1_TIMER
 	---help---
 		Reserve TIM5 to trigger ADC1
 
 config STM32_TIM5_ADC2
 	bool "TIM5 ADC channel 2"
+	depends on STM32_ADC2
+	select HAVE_ADC2_TIMER
 	---help---
 		Reserve TIM5 to trigger ADC2
 
 config STM32_TIM5_ADC3
 	bool "TIM5 ADC channel 3"
+	depends on STM32_ADC3
+	select HAVE_ADC3_TIMER
 	---help---
 		Reserve TIM5 to trigger ADC3
 
@@ -1089,21 +1119,81 @@ choice
 
 config STM32_TIM8_ADC1
 	bool "TIM8 ADC channel 1"
+	depends on STM32_ADC1
+	select HAVE_ADC1_TIMER
 	---help---
 		Reserve TIM8 to trigger ADC1
 
 config STM32_TIM8_ADC2
 	bool "TIM8 ADC channel 2"
+	depends on STM32_ADC2
+	select HAVE_ADC2_TIMER
 	---help---
 		Reserve TIM8 to trigger ADC2
 
 config STM32_TIM8_ADC3
 	bool "TIM8 ADC channel 3"
+	depends on STM32_ADC3
+	select HAVE_ADC3_TIMER
 	---help---
 		Reserve TIM8 to trigger ADC3
 
 endchoice
 
+config HAVE_ADC1_TIMER
+	bool
+
+config HAVE_ADC2_TIMER
+	bool
+
+config HAVE_ADC3_TIMER
+	bool
+
+config STM32_ADC1_SAMPLE_FREQUENCY
+	int "ADC1 Sampling Frequency"
+	default 100
+	depends on HAVE_ADC1_TIMER
+	---help---
+		ADC1 sampling frequency.  Default:  100Hz
+
+config STM32_ADC1_TIMTRIG
+	int "ADC1 Timer Trigger"
+	default 0
+	range 0 4
+	depends on HAVE_ADC1_TIMER
+	---help---
+		Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
+
+config STM32_ADC2_SAMPLE_FREQUENCY
+	int "ADC2 Sampling Frequency"
+	default 100
+	depends on HAVE_ADC2_TIMER
+	---help---
+		ADC2 sampling frequency.  Default:  100Hz
+
+config STM32_ADC2_TIMTRIG
+	int "ADC2 Timer Trigger"
+	default 0
+	range 0 4
+	depends on HAVE_ADC2_TIMER
+	---help---
+		Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
+
+config STM32_ADC3_SAMPLE_FREQUENCY
+	int "ADC3 Sampling Frequency"
+	default 100
+	depends on HAVE_ADC3_TIMER
+	---help---
+		ADC3 sampling frequency.  Default:  100Hz
+
+config STM32_ADC3_TIMTRIG
+	int "ADC3 Timer Trigger"
+	default 0
+	range 0 4
+	depends on HAVE_ADC3_TIMER
+	---help---
+		Values 0:CC1 1:CC2 2:CC3 3:CC4 4:TRGO
+
 config STM32_TIM1_DAC
 	bool "TIM1 DAC"
 	default n

configs/shenzhou/README.txt

@@ -772,6 +772,34 @@ Where <subdir> is one of the following:
        before the networking finally gives up and decides that no network is
        available.
 
+    2. Enabling the ADC example:
+
+       The only internal signal for ADC testing is the potentiometer input:
+
+         ADC1_IN10(PC0) Potentiometer
+
+       External signals are also available on CON5 CN14:
+    
+         ADC_IN8 (PB0) CON5 CN14 Pin2
+         ADC_IN9 (PB1) CON5 CN14 Pin1
+
+       The signal selection is hard-coded in configs/shenzhou/src/up_adc.c:  The
+       potentiometer input (only) is selected.
+
+       These selections will enable sampling the potentiometer input at 100Hz using
+       Timer 1:
+
+         CONFIG_ANALOG=y                        : Enable analog device support
+         CONFIG_ADC=y                           : Enable generic ADC driver support
+         CONFIG_ADC_DMA=n                       : ADC DMA is not supported
+         CONFIG_STM32_ADC1=y                    : Enable ADC 1
+         CONFIG_STM32_TIM1=y                    : Enable Timer 1
+         CONFIG_STM32_TIM1_ADC=y                : Use Timer 1 for ADC
+         CONFIG_STM32_TIM1_ADC1=y               : Allocate Timer 1 to ADC 1
+         CONFIG_STM32_ADC1_SAMPLE_FREQUENCY=100 : Set sampling frequency to 100Hz
+         CONFIG_STM32_ADC1_TIMTRIG=0            : Trigger on timer output 0
+         CONFIG_EXAMPLES_ADC=y                  : Enable the apps/examples/adc built-in
+
   nxwm
   ----
     This is a special configuration setup for the NxWM window manager

configs/shenzhou/src/up_adc.c

@@ -85,12 +85,21 @@
  * Private Data
  ************************************************************************************/
 
-/* Identifying number of each ADC channel: Variable Resistor */
+/* Identifying number of each ADC channel. The only internal signal for ADC testing
+ * is the potentiometer input:
+ *
+ *   ADC1_IN10(PC0) Potentiometer
+ *
+ * External signals are also available on CON5 CN14:
+ *
+ *  ADC_IN8 (PB0) CON5 CN14 Pin2
+ *  ADC_IN9 (PB1) CON5 CN14 Pin1
+ */
 
 #ifdef CONFIG_STM32_ADC1
 static const uint8_t  g_chanlist[ADC1_NCHANNELS] = {10}; //{10, 8, 9};
 
-/* Configurations of pins used byte each ADC channels */
+/* Configurations of pins used by each ADC channel */
 
 static const uint32_t g_pinlist[ADC1_NCHANNELS]  = {GPIO_ADC12_IN10}; //{GPIO_ADC12_IN10, GPIO_ADC12_IN8, GPIO_ADC12_IN9};
 #endif

lib/string/Make.defs

@@ -48,7 +48,7 @@ ifneq ($(CONFIG_ARCH_MEMCPY),y)
 ifeq ($(CONFIG_MEMCPY_VIK),y)
 CSRCS += lib_vikmemcpy.c
 else
-CSRCS += lib_memccpy.c
+CSRCS += lib_memcpy.c
 endif
 endif